WO2023202079A1 - 太阳电池的制备方法、太阳电池 - Google Patents

太阳电池的制备方法、太阳电池 Download PDF

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WO2023202079A1
WO2023202079A1 PCT/CN2022/134855 CN2022134855W WO2023202079A1 WO 2023202079 A1 WO2023202079 A1 WO 2023202079A1 CN 2022134855 W CN2022134855 W CN 2022134855W WO 2023202079 A1 WO2023202079 A1 WO 2023202079A1
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layer
silicon oxide
solar cell
silicon
cell according
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French (fr)
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范建彬
孟夏杰
刑国强
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Tongwei Solar Chengdu Co Ltd
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Tongwei Solar Chengdu Co Ltd
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Priority to EP22938298.1A priority Critical patent/EP4513577A4/en
Priority to AU2022454233A priority patent/AU2022454233B2/en
Priority to US18/725,488 priority patent/US20250072156A1/en
Publication of WO2023202079A1 publication Critical patent/WO2023202079A1/zh
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    • H—ELECTRICITY
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    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H10F71/1221—The active layers comprising only Group IV materials comprising polycrystalline silicon
    • H—ELECTRICITY
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    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
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    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
    • H—ELECTRICITY
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    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
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    • H10F19/00—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules
    • H10F19/80—Encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells
    • H10F19/804—Materials of encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/128—Annealing
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    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/129—Passivating
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    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/131—Recrystallisation; Crystallization of amorphous or microcrystalline semiconductors
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    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H10F77/219—Arrangements for electrodes of back-contact photovoltaic cells
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    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • H10F77/703—Surface textures, e.g. pyramid structures of the semiconductor bodies, e.g. textured active layers
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    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
    • H10F77/162—Non-monocrystalline materials, e.g. semiconductor particles embedded in insulating materials
    • H10F77/164—Polycrystalline semiconductors
    • H10F77/1642—Polycrystalline semiconductors including only Group IV materials
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    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/30—Coatings
    • H10F77/306—Coatings for devices having potential barriers
    • H10F77/311—Coatings for devices having potential barriers for photovoltaic cells

Definitions

  • the present invention relates to the technical field of solar cell production, and in particular to a preparation method of solar cells and solar cells.
  • Back contact battery namely back contact battery, among which finger-shaped back contact solar battery is also called IBC (Interdigitated back contact) battery.
  • IBC Interdigitated back contact
  • the biggest feature of IBC batteries is that the PN junction area or PN-like junction area and metal electrodes are located on the back of the battery, and the front of the battery is not blocked by the metal electrodes.
  • IBC battery Due to the above structural characteristics of the IBC battery, it has a higher short-circuit current Jsc. At the same time, the back side can allow wider metal grid lines to reduce the series resistance Rs and thereby increase the fill factor FF. Moreover, this battery with no obstruction on the front not only The conversion efficiency is high and it looks more beautiful. Therefore, IBC cells have become one of the current technical directions for realizing high-efficiency crystalline silicon cells.
  • low-pressure chemical vapor deposition is usually first used to form an amorphous silicon layer, and then phosphorus diffusion is performed on the amorphous silicon layer to form a phosphorus-doped polysilicon layer on the P-type silicon wafer. and silicon oxide mask layer.
  • the silicon oxide mask layer prepared by this production process is PSG (phosphosilicate glass) formed by phosphorus diffusion through the amorphous silicon layer.
  • the phosphorus-doped silicon oxide mask layer can protect the polysilicon layer on the back of the P-type silicon wafer to a certain extent during texturing, and prevent the polysilicon layer from being damaged by texturing liquid containing alkali to a certain extent.
  • the silicon oxide mask layer prepared by the above process is formed by phosphorus diffusion of the amorphous silicon layer, and the growth of the silicon oxide mask layer is a self-limiting reaction.
  • the thickness is generally very small (less than 20nm), and its alkali corrosion resistance time is short; and there is a high concentration of phosphorus doping in the silicon oxide mask layer, and the high concentration of phosphorus doping will also cause the silicon oxide mask layer to deteriorate. Alkali resistance is reduced. Therefore, when texturing the P-type back contact solar cells prepared by the above process, there is still a problem that the phosphorus-doped silicon oxide mask layer has a narrow protection time window for the polysilicon layer. That is, the time interval from the beginning of texturing to the beginning of destruction of the polysilicon layer is short.
  • the texturing time In order to ensure that the polysilicon layer on the back side of the P-type silicon wafer prepared by the above method is not damaged, the texturing time must be controlled within this narrow time window. However, if the texturing time is too short, the oxide layer and polysilicon layer in the patterned area on the back of the P-type silicon wafer will not be etched cleanly, and the P/N area of the battery cannot be effectively isolated, thus affecting the conversion efficiency and yield of the battery.
  • a method for preparing a solar cell including the following steps:
  • a silicon wafer having a first surface and a second surface opposite the first surface
  • An ultra-thin silicon oxide layer is formed on the first surface of the silicon wafer, and a phosphorus-doped amorphous silicon layer and a silicon oxide mask layer are sequentially formed on the ultra-thin silicon oxide layer;
  • the silicon wafer is annealed to densify the silicon oxide mask layer and convert the amorphous silicon layer into a phosphorus-doped polysilicon layer.
  • the phosphorus-doped amorphous silicon layer and the silicon oxide mask layer are sequentially formed on the ultra-thin silicon oxide layer through a plasma-enhanced chemical vapor deposition method.
  • the deposition temperature of the phosphorus-doped amorphous silicon layer and the silicon oxide mask layer formed by plasma enhanced chemical vapor deposition is 350°C to 550°C.
  • the annealing temperature of the annealing treatment is 800°C to 950°C, and the annealing time is 30 min to 120 min.
  • the annealing temperature ranges from 850°C to 900°C.
  • the thickness of the phosphorus-doped amorphous silicon layer is 30 nm to 300 nm.
  • the thickness of the phosphorus-doped amorphous silicon layer is 100 nm to 150 nm.
  • the silicon oxide mask layer has a thickness of 10 nm to 100 nm.
  • the silicon oxide mask layer has a thickness of 20 nm to 50 nm.
  • the ultra-thin silicon oxide layer has a thickness of 0.5 nm to 2.5 nm.
  • the silicon wafer is a P-type silicon wafer.
  • the preparation method further includes:
  • the silicon oxide mask layer on the first surface is patterned to remove part of the silicon oxide mask layer to form a patterned area.
  • the preparation method further includes the following steps:
  • the first surface and the second surface of the silicon wafer are soaked in a texturing liquid to remove the ultra-thin silicon oxide layer and the polysilicon layer in the patterned area, and make The second surface forms a textured surface.
  • the texturing liquid is an alkali solution containing texturing additives
  • the soaking temperature is 35°C to 85°C
  • the soaking time is 200s to 550s.
  • the preparation method further includes the following steps:
  • An anti-reflective film layer is deposited on the passivation film layer on the first surface and the second surface.
  • the passivation film layer is an aluminum oxide film layer, and the thickness of the passivation film layer is 2 nm to 25 nm.
  • the anti-reflection film layer is any one of silicon nitride, silicon oxynitride and silicon oxide or a combination of multiple films, and the thickness of the anti-reflection film layer is 50 nm to 50 nm. 150nm.
  • the preparation method after depositing and forming the anti-reflection film layer, the preparation method further includes the following steps:
  • Electrode slurry is injected into the electrode contact area and the polysilicon layer to form a first electrode and a second electrode respectively.
  • the first electrode is an aluminum grid electrode, and the width of the first electrode ranges from 50 ⁇ m to 200 ⁇ m.
  • the second electrode is a silver grid electrode, and the width of the second electrode is 10 ⁇ m to 50 ⁇ m.
  • a solar cell is provided, which is prepared by the above-mentioned solar cell preparation method of the present invention.
  • the present invention has the following beneficial effects:
  • the present invention By sequentially forming a phosphorus-doped amorphous silicon layer and a silicon oxide mask layer on an ultra-thin silicon oxide layer; and then performing an annealing treatment to densify the silicon oxide mask layer.
  • LPCVD low-pressure chemical vapor deposition
  • the present invention can easily control the thickness of the silicon oxide mask layer according to the alkali resistance requirements; and the silicon oxide mask layer can be densified through annealing treatment to further enhance the Corrosion resistance of silicon oxide mask layer in alkaline solution (texturing solution).
  • the polysilicon layer in the N-type region can be better protected from corrosion and the texturing time window of the subsequent texturing process can be extended.
  • Figure 1 is a schematic structural diagram of a solar cell prepared in an embodiment of the present invention
  • Figure 2 is a bottom view of Figure 1;
  • Figure 3 is a schematic structural diagram of a P-type silicon wafer
  • Figure 4 is a schematic structural diagram of each film layer deposited on a P-type silicon wafer and annealed
  • Figure 5 is a bottom view of the silicon oxide mask layer after patterning
  • Figure 6 is a schematic structural diagram of the P-type silicon wafer after texturing and removing the silicon oxide mask layer
  • Figure 7 is a bottom view after opening holes in the patterned area.
  • P-type silicon wafer 11. First surface; 12. Second surface; 21. Ultra-thin silicon oxide layer; 22. Amorphous silicon layer; 23. Silicon oxide mask layer; 30. Polysilicon layer; 40. Pattern Chemicalized area; 50, passivation film layer; 60, anti-reflection film layer; 70, electrode contact area; 80, first electrode; 90, second electrode; 100, P-type back contact solar cell.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include at least one of these features.
  • “plurality” means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.
  • connection In the present invention, unless otherwise clearly stated and limited, the terms “installation”, “connection”, “connection”, “fixing” and other terms should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. , or integrated into one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two elements or an interactive relationship between two elements, unless otherwise specified restrictions. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
  • One embodiment of the present invention provides a method for preparing a P-type back contact solar cell 100.
  • the structure of the P-type back contact solar cell 100 is shown in Figures 1 and 2.
  • the preparation method includes the following steps S100 to S700.
  • Step S100 Provide a P-type silicon wafer 10.
  • the P-type silicon wafer 10 has a first surface 11 and a second surface 12 opposite to the first surface 11.
  • the structure of the P-type silicon wafer 10 is shown in Figure 3 .
  • first surface 11 and the second surface 12 of the P-type silicon wafer 10 one surface is the light-receiving surface (front surface) of the back-contact solar cell 100 , and the other surface is the back-light surface (rear surface) of the back-contact solar cell 100 .
  • first surface 11 of the P-type silicon wafer 10 is used as the back surface
  • second surface 12 is used as the front surface
  • the PN junction region and the metal electrode are both disposed on the first surface 11 .
  • the P-type silicon wafer 10 is also subjected to damage removal treatment, polishing treatment and cleaning treatment to make the surface of the P-type silicon wafer 10 clean and smooth, which facilitates subsequent coating processes.
  • the specific process is as follows: use a solution containing KOH at about 60°C to remove damage to the surface of the P-type silicon wafer 10; then use a solution containing KOH to polish the P-type silicon wafer 10 at about 75°C, so that The surface reflectivity of the polished P-type silicon wafer 10 reaches 30%; then a mixed solution containing hydrofluoric acid and hydrochloric acid is used to clean the polished P-type silicon wafer 10; finally, it is cleaned with deionized water and dried.
  • Step S200 Form an ultra-thin silicon oxide layer 21 with a thickness of 0.5 nm to 2.5 nm on the first surface 11 of the P-type silicon wafer 10, and sequentially form phosphorus-doped amorphous silicon on the ultra-thin silicon oxide layer 21 through PECVD. layer 22 and silicon oxide mask layer 23.
  • PECVD is first used to deposit an ultra-thin silicon oxide layer 21 on the first surface 11 , then PECVD is used to deposit an amorphous silicon layer 22 on the ultra-thin silicon oxide layer 21 , and then PECVD is used to deposit an amorphous silicon layer 22 on the amorphous silicon layer.
  • a silicon oxide mask layer 23 is deposited on 22 .
  • thermal oxygen or chain oxygen can also be used to grow the ultra-thin silicon oxide layer 21 on the first surface 11 , and then PECVD is used to sequentially deposit the amorphous silicon layer 22 and the ultra-thin silicon oxide layer 21 on the ultra-thin silicon oxide layer 21 . Silicon oxide mask layer 23.
  • the deposition temperature is generally 350°C to 550°C.
  • the ultra-thin silicon oxide layer 21 is a silicon oxide film layer disposed close to the first surface 11 , and the thickness of the ultra-thin silicon oxide layer 21 is 0.5 nm to 0.25 nm.
  • the thickness of the amorphous silicon layer 22 is 30 nm to 300 nm, preferably 100 nm to 150 nm.
  • the thickness of the silicon oxide mask layer 23 is 10 nm to 100 nm, preferably 20 nm to 50 nm.
  • the ultra-thin silicon oxide layer 21 and the phosphorus-doped amorphous silicon layer 22 form a PN junction together with the P-type silicon wafer 10 .
  • the main function of the silicon oxide mask layer 23 is to protect the PN junction area (ultra-thin silicon oxide layer 21, doped amorphous silicon layer 22, etc.) on the first surface 11 from being alkali-containing in the subsequent texturing process. Corroded by the texturing liquid.
  • low-pressure chemical vapor deposition is usually used to form the amorphous silicon layer 22, and then phosphorus diffusion is performed on the amorphous silicon layer 22 to form a phosphorus-doped polysilicon layer 30 and a silicon oxide mask layer 23 on the P-type silicon wafer 10.
  • the process method prepares the P-type back contact solar cell 100.
  • the silicon oxide mask layer 23 prepared by this production process is PSG (phosphosilicate glass) formed by phosphorus diffusion on the amorphous silicon layer 22 .
  • the silicon oxide mask layer 23 can protect the polysilicon layer 30 on the back of the P-type silicon wafer 10 to a certain extent during texturing, and prevent the polysilicon layer 30 from being damaged by texturing liquid containing alkali to a certain extent.
  • the silicon oxide mask layer 23 prepared using the above process is formed by phosphorus diffusion of the amorphous silicon layer 22, and the growth of the silicon oxide mask layer 23 is a self-limiting reaction.
  • the thickness of the film layer 23 is generally very small (less than 20 nm), and the corrosion resistance time to alkali solution is short; and there is a high concentration of phosphorus doping in the silicon oxide mask layer 23, and the high concentration of phosphorus doping will also cause oxidation.
  • the alkali resistance of the silicon mask layer 23 decreases. Generally, the higher the phosphorus doping concentration in the silicon oxide mask layer 23, the lower its alkali resistance.
  • the present invention can easily control the thickness of the silicon oxide mask layer 23 according to the actual alkali resistance requirements of the silicon oxide mask layer 23.
  • the thickness of the silicon oxide mask layer 23 can reach 100 nm, while the thickness of the silicon oxide mask layer 23 formed by LPCVD combined with phosphorus diffusion is generally less than 20 nm.
  • the growth rate of the coating layer has a linear relationship with time.
  • the thickness of the silicon oxide mask layer 23 is proportional to the alkali corrosion resistance time.
  • the thickness of the silicon oxide mask layer 23 increases, its alkali corrosion resistance time will also be extended.
  • a silicon oxide mask layer 23 with a larger thickness can be obtained, thereby effectively extending the texturing time window of the subsequent texturing process.
  • the main reason why the present invention uses PECVD to separately form the amorphous silicon layer 22 and the silicon oxide mask layer 23 instead of using LPCVD to separately form the amorphous silicon layer 22 and the additionally generated silicon oxide mask layer 23 is that: LPCVD
  • the temperature for depositing amorphous silicon/polycrystalline silicon is generally 550°C to 650°C; oxygen is directly introduced into the LPCVD equipment.
  • the growth of outer silicon oxide can be completed, the growth thickness of silicon oxide follows a parabolic curve with temperature/time. Silicon oxide larger than 10nm takes several hours to complete at 600°C; in order to block alkali corrosion and increase the concentration of phosphorus diffusion, the diffusion and oxidation temperature needs to be raised to above 800°C to quickly increase the silicon oxide thickness.
  • the equipment needs to be heated from the LPCVD deposition temperature of amorphous/polycrystalline silicon (550°C to 650°C) to 800°C, and then the equipment needs to be cooled down for the production process of the next batch of silicon wafers.
  • the equipment continuously cycles up and down with a temperature difference of more than 200°C, which requires more than two hours of additional process time. It is more economical to separate LPCVD deposition and doping element diffusion oxidation into two equipments. Therefore, the present invention uses PECVD to form the amorphous silicon layer 22 and the silicon oxide mask layer 23 separately.
  • Step S300 Perform annealing treatment on the silicon wafer substrate 10 to densify the silicon oxide mask layer 23, and crystallize the phosphorus-doped amorphous silicon layer 22 to form the phosphorus-doped polysilicon layer 30.
  • the structure of the P-type silicon wafer 10 and each film layer after the annealing treatment is shown in FIG. 4 .
  • the silicon oxide mask layer 23 prepared by PECVD is annealed, so that the silicon oxide mask layer 23 can be densified.
  • the silicon oxide mask layer 23 grown by PEVCD or LPCVD is usually relatively loose, and there are some holes inside it, which affects its alkali corrosion resistance.
  • the silicon oxide grown by PECVD will become denser during the high-temperature annealing process, eliminating some voids inside the film layer, and can enhance the resistance of the silicon oxide mask layer 23 in the alkaline solution. It has excellent corrosion resistance, which can better protect the N-type area (crystalline silicon film layer, etc.) from being corroded, extend the texturing time window of the subsequent texturing process, and reduce the risk of battery leakage.
  • the amorphous silicon (a-Si) deposited by PEVCD can also be converted into polycrystalline silicon (poly), and the grains can be grown larger, so that the phosphorus-doped amorphous silicon layer 22 can be converted into polycrystalline silicon.
  • a-Si amorphous silicon
  • poly polycrystalline silicon
  • the annealing temperature of the annealing treatment is 800°C to 950°C, and the annealing time is 30 min to 120 min.
  • the silicon oxide mask layer 23 can be fully densified, effectively extending the texturing time window; and the phosphorus-doped amorphous silicon layer 22 can be fully converted into the phosphorus-doped polysilicon layer 30 .
  • the annealing temperature can be specific values such as 800°C, 820°C, 850°C, 880°C, 900°C, 920°C, 950°C; further preferably, the annealing temperature is 850°C to 900°C.
  • the annealing time can be specific values such as 30min, 40min, 60min, 80min, 100min, 120min, etc.
  • Step S400 After annealing the P-type silicon wafer 10, pattern the silicon oxide mask layer 23 on the first surface 11 to remove part of the silicon oxide mask layer 23 to form a patterned area. 40.
  • the structure after patterning is shown in Figure 5.
  • the present invention After annealing the silicon oxide mask layer 23 on the first surface 11, the present invention performs a patterning process on the silicon oxide mask layer 23 on the first surface 11 to remove the oxidation in some areas of the first surface 11. Silicon mask layer 23, thereby forming patterned area 40.
  • the patterned area 40 is used to prepare electrodes directly connected to the P-type silicon wafer 10 .
  • the width of the patterned area 40 is 300 ⁇ m to 500 ⁇ m.
  • the silicon oxide mask layer 23 can be patterned using existing processes in the art, as long as part of the silicon oxide mask layer 23 can be removed according to a certain pattern.
  • Step S500 After forming the patterned area 40, use texturing liquid to soak the first surface 11 and the second surface 12 of the P-type silicon wafer 10 to remove the ultra-thin silicon oxide layer 21 and 21 in the patterned area 40.
  • the polysilicon layer 30 forms a textured surface on the second surface 11 .
  • the entire texturing process has multiple tanks. After the texturing is completed, it is cleaned with deionized water, alkali cleaning (a mixture of alkali and hydrogen peroxide), deionized water cleaning, and pickling (hydrofluoric acid or hydrofluoric acid and hydrochloric acid).
  • the structure of the mixed liquid (hydrofluoric acid can remove the silicon oxide mask), cleaning with deionized water, and removing the silicon oxide mask layer 23 after being soaked in hydrofluoric acid is shown in Figure 6.
  • the second surface 12 (front surface) of the P-type silicon wafer 10 can be textured to form a textured surface, and at the same time, the patterned area 40 on the first surface 11 can be etched to effectively remove the patterned area.
  • the ultra-thin silicon oxide layer 21 and the polysilicon layer 30 in the patterned area 40 are exposed to expose the first surface 11 corresponding to the patterned area 40 .
  • Other areas on the back of the cell are protected by the silicon oxide mask layer 23 and will not be corroded and damaged by the texturing solution.
  • the silicon oxide mask layer 23 can be removed by pickling with a solution containing hydrofluoric acid.
  • the texturing liquid is an alkali solution containing texturing additives
  • the temperature of the texturing soaking treatment is 35°C to 85°C
  • the time of the texturing soaking treatment is 200s to 550s.
  • Step S600 Deposit the passivation film layer 50 on the first surface 11 and the second surface 12 of the P-type silicon wafer 10 respectively; then deposit the passivation film layer 50 on the first surface 11 and the second surface 12 respectively.
  • Antireflection film layer 60 is deposited.
  • the passivation film layer 50 is an aluminum oxide film layer grown by an ALD (atomic layer deposition) method, and the thickness of the passivation film layer 50 is 2 nm to 25 nm;
  • the anti-reflection film layer 60 is silicon nitride. , silicon nitride oxide, silicon oxide, any one film layer or a combination of multiple film layers, and the thickness of the anti-reflection film layer 60 is 50 nm to 150 nm.
  • Step S700 Use a laser to pattern holes in the patterned area 40 on the first surface 11 of the silicon substrate 10 to remove the passivation film layer 50 and the anti-reflection film layer 60 at the hole to form the electrode contact area 70 ; Then inject electrode slurry into the electrode contact area 70 and the polysilicon layer 30 (the slurry injected into the polysilicon layer 30 is a burn-through type slurry, which can burn through the passivation film layer 50 and the anti-reflection film layer 60), respectively forming the first An electrode 80 and a second electrode 90 .
  • the structure after opening holes in the patterned area 40 is shown in FIG. 7 .
  • the first electrode 80 is directly connected to the silicon substrate 10, and the second electrode 90 is directly connected to the polysilicon layer 30 in the area other than the patterned area 40 on the first surface 11.
  • the first electrode 80 is an aluminum grid electrode, and the width of the first electrode 80 is 50 ⁇ m to 200 ⁇ m; the second electrode 90 is a silver grid electrode, and the width of the second electrode 90 is 10 ⁇ m to 50 ⁇ m.
  • the hole areas are distributed in a dotted line or dot shape, and the width of the holes is 30 ⁇ m to 50 ⁇ m, that is, the width of the electrode contact area 70 is 30 ⁇ m to 50 ⁇ m.
  • Screen printing may be used to form an electrode paste layer containing a conductive component in the electrode contact area 70 and the polysilicon layer 30 as the first electrode 80 and the second electrode 90 respectively.
  • Another embodiment of the present invention provides another method for preparing a P-type back contact solar cell 100.
  • the preparation method includes the following steps S100 to S1000.
  • Step S100 Provide a P-type silicon wafer 10.
  • the P-type silicon wafer 10 has a first surface 11 and a second surface 12 opposite to the first surface 11.
  • first surface 11 and the second surface 12 of the P-type silicon wafer 10 one surface is the light-receiving surface (front surface) of the back-contact solar cell 100 , and the other surface is the back-light surface (rear surface) of the back-contact solar cell 100 .
  • first surface 11 of the P-type silicon wafer 10 is used as the back surface
  • second surface 12 is used as the front surface
  • the PN junction region and the metal electrode are both disposed on the first surface 11 .
  • the P-type silicon wafer 10 is also subjected to damage removal treatment, polishing treatment and cleaning treatment to make the surface of the P-type silicon wafer 10 clean and smooth, which facilitates subsequent coating processes.
  • the specific process is as follows: use a solution containing KOH at about 60°C to remove damage to the surface of the P-type silicon wafer 10; then use a solution containing KOH to polish the P-type silicon wafer 10 at about 75°C, so that The surface reflectivity of the polished P-type silicon wafer 10 reaches 30%; then a mixed solution containing hydrofluoric acid and hydrochloric acid is used to clean the polished P-type silicon wafer 10; finally, it is cleaned with deionized water and dried.
  • Step S200 Form an ultra-thin silicon oxide layer 21 with a thickness of 0.5 nm to 2.5 nm on the first surface 11 of the P-type silicon wafer 10, and sequentially form phosphorus-doped amorphous silicon on the ultra-thin silicon oxide layer 21 through PECVD. layer 22 and silicon oxide mask layer 23.
  • PECVD is first used to deposit an ultra-thin silicon oxide layer 21 on the first surface 11 , then PECVD is used to deposit an amorphous silicon layer 22 on the ultra-thin silicon oxide layer 21 , and then PECVD is used to deposit an amorphous silicon layer 22 on the amorphous silicon layer.
  • a silicon oxide mask layer 23 is deposited on 22 .
  • thermal oxygen or chain oxygen can also be used to grow the ultra-thin silicon oxide layer 21 on the first surface 11 , and then PECVD is used to sequentially deposit the amorphous silicon layer 22 and the ultra-thin silicon oxide layer 21 on the ultra-thin silicon oxide layer 21 . Silicon oxide mask layer 23.
  • the deposition temperature is generally 350°C to 550°C.
  • the ultra-thin silicon oxide layer 21 is a silicon oxide film layer disposed close to the first surface 11 , and the thickness of the ultra-thin silicon oxide layer 21 is 0.5 nm to 0.25 nm.
  • the thickness of the amorphous silicon layer 22 is 30 nm to 300 nm, preferably 100 nm to 150 nm.
  • the thickness of the silicon oxide mask layer 23 is 10 nm to 100 nm, preferably 20 nm to 50 nm.
  • Step S300 Perform annealing treatment on the silicon wafer substrate 10 to densify the silicon oxide mask layer 23, and crystallize the phosphorus-doped amorphous silicon layer 22 to form the phosphorus-doped polysilicon layer 30.
  • the amorphous silicon (a-Si) deposited by PEVCD can be converted into polycrystalline silicon (poly), and the grains can grow larger, so that the phosphorus-doped amorphous silicon layer 22 can be converted into the polycrystalline silicon layer 30;
  • the silicon oxide mask layer 23 is densified.
  • the annealing temperature of the annealing treatment is 800°C to 950°C, and the annealing time is 30 min to 120 min.
  • Step S400 Use chain hydrofluoric acid (the volume ratio of hydrofluoric acid is 5% to 35%, normal temperature) to remove only the silicon oxide mask plating on the second surface 12 (chain type, that is, placed horizontally, traveling horizontally, with the upper surface Covered by a water film, the lower surface reacts with the solution, and the solution is not higher than the upper surface).
  • chain hydrofluoric acid the volume ratio of hydrofluoric acid is 5% to 35%, normal temperature
  • Step S500 trough texturing.
  • the complete process of texturing is alkali washing (hydrogen peroxide + strong alkali such as NaOH/KOH, temperature 50°C ⁇ 65°C, alkali volume ratio 0.3% ⁇ 1.5%, time 60s ⁇ 300s), deionized water cleaning, texturing, Deionized water cleaning, alkali cleaning, deionized water cleaning, pickling (hydrochloric acid solution, excluding hydrofluoric acid, because the reaction between HF and silicon oxide will remove the previous silicon oxide mask layer 23), deionized water cleaning, drying Dry.
  • alkali washing hydrogen peroxide + strong alkali such as NaOH/KOH, temperature 50°C ⁇ 65°C, alkali volume ratio 0.3% ⁇ 1.5%, time 60s ⁇ 300s
  • deionized water cleaning texturing
  • Step S600 The second surface 12 is oxidized at high temperature. At this time, the second surface 12 has been textured and is not protected by silicon oxide.
  • the temperature of high-temperature oxidation is 700°C ⁇ 900°C and the time is 20min ⁇ 50min.
  • Step S700 Pattern the silicon oxide mask layer 23 on the first surface 11 to remove part of the silicon oxide mask layer 23 to form a patterned area 40.
  • Step S800 groove etching.
  • the process is: etching - water washing - alkali washing - water washing - pickling (containing HF to remove excess silicon oxide mask layer 23 on the front and back) - water washing - drying.
  • Step S900 Deposit the passivation film layer 50 on the first surface 11 and the second surface 12 of the P-type silicon wafer 10 respectively; and then deposit the passivation film layer 50 on the first surface 11 and the second surface 12 respectively.
  • Antireflection film layer 60 is deposited.
  • Step S1000 Use a laser to pattern holes in the patterned area 40 on the first surface 11 of the silicon substrate 10 to remove the passivation film layer 50 and the anti-reflection film layer 60 at the hole to form the electrode contact area 70 ; Then inject electrode slurry into the electrode contact area 70 and the polysilicon layer 30 (the slurry injected into the polysilicon layer 30 is a burn-through type slurry, which can burn through the passivation film layer 50 and the anti-reflection film layer 60), respectively forming the first An electrode 80 and a second electrode 90 .

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Abstract

本发明提供了一种太阳电池的制备方法、太阳电池，该太阳电池的制备方法包括：提供硅片，该硅片具有第一表面和与第一表面相对的第二表面；在硅片的第一表面形成超薄氧化硅层，在超薄氧化硅层上依次形成磷掺杂非晶硅层和氧化硅掩膜层；对硅片进行退火处理，使氧化硅掩膜层致密化。本发明通过在超薄氧化硅层上依次形成磷掺杂非晶硅层和氧化硅掩膜层；然后进行退火处理，可以方便地控制氧化硅掩膜层的厚度；并且可使氧化硅掩膜层致密化，进一步增强氧化硅掩膜层在碱性溶液中的耐腐蚀性。通过本发明的方法可以更好地保护N型区域的多晶硅层不被腐蚀，延长后续制绒工序的制绒时间窗口。

Description

太阳电池的制备方法、太阳电池
本申请要求于2022年04月20日提交中国专利局、申请号为202210415006X、发明名称为“一种P型背接触太阳电池及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及太阳能电池生产技术领域，特别是涉及一种太阳电池的制备方法、太阳电池。
背景技术
背接触电池，即back contact电池，其中指状交叉背接触太阳电池又称为IBC(Interdigitated back contact)电池。IBC电池最大的特点是PN结区或类PN结区以及金属电极都处于电池的背面，电池正面没有金属电极遮挡的影响。
由于IBC电池的上述结构特点，使得其具有更高的短路电流Jsc，同时背面可以容许较宽的金属栅线来降低串联电阻Rs从而提高了填充因子FF，并且，这种正面无遮挡的电池不仅转换效率高，而且看上去也更加美观。因此，IBC电池已成为目前实现高效晶体硅电池的技术方向之一。
在制备P型背接触太阳电池时，目前通常先采用低压化学气相沉积(LPCVD)形成非晶硅层，然后对非晶硅层进行磷扩散，在P型硅片上形成磷掺杂的多晶硅层和氧化硅掩膜层。这种生产工艺制备的氧化硅掩膜层为非晶硅层通过磷扩散形成的PSG(磷硅玻璃)。该磷掺杂的氧化硅掩膜层在制绒时可以对P型硅片背面的多晶硅层起到一定的保护作用，在一定程度上避免多晶硅层被含碱的制绒药液所破坏。
然而，采用上述工艺制备的氧化硅掩膜层，由于其是通过对非晶硅层进 行磷扩散形成的，氧化硅掩膜层的生长是一种自限制反应，所制备的氧化硅掩膜层的厚度一般很小(小于20nm)，其耐碱液腐蚀时间较短；而且该氧化硅掩膜层中存在高浓度的磷掺杂，高浓度的磷掺杂也会导致氧化硅掩膜层的耐碱性降低。因此，上述工艺制备的P型背接触太阳电池在制绒时，仍然存在磷掺杂的氧化硅掩膜层对多晶硅层的保护时间窗口较窄的问题。即从制绒开始到多晶硅层开始被破坏的时间间隔较短。
为了确保采用上述方法制备的P型硅片背面的多晶硅层不被破坏，必须将制绒时间控制在该较窄的时间窗口之内。但是，制绒时间过短会导致P型硅片背面图案化区域内的氧化层和多晶硅层刻蚀不干净，不能有效地隔离开电池的P/N区，从而影响电池的转化效率和良率。
发明内容
基于此，有必要提供一种能够提高掩膜层的耐碱性、延长制绒时间窗口的太阳电池的制备方法、太阳电池。
本发明提出的技术方案如下：
根据本发明的一个方面，提供了一种太阳电池的制备方法，包括如下步骤：
提供硅片，所述硅片具有第一表面和与所述第一表面相对的第二表面；
在所述硅片的所述第一表面形成超薄氧化硅层，在所述超薄氧化硅层上依次形成磷掺杂非晶硅层和氧化硅掩膜层；及
对所述硅片进行退火处理，以使所述氧化硅掩膜层致密化，并使所述非晶硅层转化为磷掺杂的多晶硅层。
在其中一些实施例中，通过等离子体增强化学气相沉积法，在所述超薄氧化硅层上依次形成所述磷掺杂非晶硅层和所述氧化硅掩膜层。
在其中一些实施例中，通过等离子体增强化学气相沉积法形成所述磷 掺杂非晶硅层和所述氧化硅掩膜层的沉积温度为350℃～550℃。
在其中一些实施例中，所述退火处理的退火温度为800℃～950℃，退火时间为30min～120min。
在其中一些实施例中，所述退火温度为850℃～900℃。
在其中一些实施例中，所述磷掺杂非晶硅层的厚度为30nm～300nm。
在其中一些实施例中，所述磷掺杂非晶硅层的厚度为100nm～150nm。
在其中一些实施例中，所述氧化硅掩膜层的厚度为10nm～100nm。
在其中一些实施例中，所述氧化硅掩膜层的厚度为20nm～50nm。
在其中一些实施例中，所述超薄氧化硅层的厚度为0.5nm～2.5nm。
在其中一些实施例中，所述硅片为P型硅片。
在其中一些实施例中，对所述硅片进行退火处理之后，所述制备方法还包括：
对所述第一表面上的所述氧化硅掩膜层进行图案化处理，以将部分区域的所述氧化硅掩膜层去除形成图案化区域。
在其中一些实施例中，形成所述图案化区域之后，所述制备方法还包括如下步骤：
利用制绒药液对所述硅片的所述第一表面和所述第二表面进行浸泡处理，以去除所述图案化区域内的所述超薄氧化硅层和所述多晶硅层，并使所述第二表面形成绒面。
在其中一些实施例中，所述制绒药液为含有制绒添加剂的碱溶液，所述浸泡处理的温度为35℃～85℃，所述浸泡处理的时间为200s～550s。
在其中一些实施例中，在对所述第一表面和所述第二表面进行浸泡处理之后，所述制备方法还包括如下步骤：
在所述硅片的所述第一表面上和所述第二表面上沉积钝化膜层；及
在所述第一表面上和所述第二表面上的所述钝化膜层上沉积减反射膜 层。
在其中一些实施例中，所述钝化膜层为氧化铝膜层，所述钝化膜层的厚度为2nm～25nm。
在其中一些实施例中，所述减反射膜层为氮化硅、氮氧化硅和氧化硅中的任意一种膜层或者多种的组合膜层，所述减反射膜层的厚度为50nm～150nm。
在其中一些实施例中，在沉积形成所述减反射膜层之后，所述制备方法还包括如下步骤：
利用激光对所述第一表面上的所述图案化区域进行图案化开孔，去除开孔处的所述钝化膜层和所述减反射膜层形成电极接触区；及
在所述电极接触区内和所述多晶硅层内注入电极浆料，分别形成第一电极和第二电极。
在其中一些实施例中，所述第一电极为铝栅线电极，所述第一电极的宽度为50μm～200μm。
在其中一些实施例中，所述第二电极为银栅线电极，所述第二电极的宽度为10μm～50μm。
根据本发明的另一方面，提供了一种太阳电池，所述太阳电池通过本发明上述的太阳电池的制备方法制备得到。
与现有技术相比，本发明具有如下有益效果：
针对目前的采用低压化学气相沉积(LPCVD)形成非晶硅层，然后进行磷扩散形成掺杂非晶硅层和氧化硅掩膜层的生产工艺存在的制绒时间窗口较窄的问题；本发明通过在超薄氧化硅层上依次单独形成磷掺杂非晶硅层和氧化硅掩膜层；然后进行退火处理，使氧化硅掩膜层致密化。本发明通过在非晶硅层上单独形成氧化硅掩膜层，可以方便地根据耐碱性需要控制氧化硅掩膜层的厚度；并且通过退火处理可使氧化硅掩膜层致密化，进一步 增强氧化硅掩膜层在碱性溶液(制绒药液)中的耐腐蚀性。通过本发明的方法可以更好地保护N型区域的多晶硅层不被腐蚀，延长后续制绒工序的制绒时间窗口。
附图说明
图1为本发明一实施例所制备的太阳电池的结构示意图；
图2为图1的仰视图；
图3为P型硅片的结构示意图；
图4为P型硅片上沉积各膜层并退火后的结构示意图；
图5为对氧化硅掩膜层进行图案化处理后的仰视图；
图6为对P型硅片进行制绒并去除氧化硅掩膜层后的结构示意图；
图7为对图案化区域开孔后的仰视图。
附图标记说明：
10、P型硅片；11、第一表面；12、第二表面；21、超薄氧化硅层；22、非晶硅层；23、氧化硅掩膜层；30、多晶硅层；40、图案化区域；50、钝化膜层；60、减反射膜层；70、电极接触区；80、第一电极；90、第二电极；100、P型背接触太阳电池。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面对本发明的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本发明。但是本发明能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似改进，因此本发明不受下面公开的具体实施例的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示 相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本发明的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
在本发明中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
本发明一实施方式提供了一种P型背接触太阳电池100的制备方法，该P型背接触太阳电池100的结构如图1和图2所示。其制备方法包括如下步骤S100至步骤S700。
步骤S100：提供P型硅片10，该P型硅片10具有第一表面11和与第一表面11相对的第二表面12。P型硅片10的结构如图3所示。
P型硅片10的第一表面11和第二表面12中，其中一个表面为背接触太阳电池100的受光面(正面)，另一个表面为背接触太阳电池100的背光面(背面)。在其中一些实施例中，以P型硅片10的第一表面11作为背面，以第二表面12作为正面，PN结区及金属电极均设置在第一表面11上。
在其中一些实施例中，还对该P型硅片10进行去损伤处理、抛光处理 和清洗处理，以使P型硅片10的表面清洁平整，利于进行后续的镀膜工序。其具体流程如下：使用60℃左右的含有KOH的溶液对P型硅片10的表面进行去损伤处理；然后在75℃左右条件下使用含有KOH的溶液对P型硅片10进行抛光处理，使抛光后的P型硅片10表面反射率达到30％；再使用含有氢氟酸和盐酸的混合溶液对抛光后的P型硅片10进行清洗；最后用去离子水清洗并烘干。
步骤S200：在P型硅片10的第一表面11上形成厚度为0.5nm～2.5nm的超薄氧化硅层21，通过PECVD在超薄氧化硅层21上依次形成磷掺杂的非晶硅层22和氧化硅掩膜层23。
在其中一个具体示例中，先采用PECVD在第一表面11上沉积超薄氧化硅层21，然后采用PECVD在超薄氧化硅层21上沉积非晶硅层22，再采用PECVD在非晶硅层22上沉积氧化硅掩膜层23。
在另外一些实施例中，也可以采用热氧或链氧等方式在第一表面11上生长超薄氧化硅层21，然后采用PECVD在超薄氧化硅层21上依次沉积非晶硅层22和氧化硅掩膜层23。
采用PECVD形成非晶硅层22时以SiH 4为硅源，并采用PH 3气体作为磷源，对非晶硅层22进行磷掺杂。PECVD生长上述膜层时，沉积温度一般为350℃～550℃。
超薄氧化硅层21为一层紧靠第一表面11设置的氧化硅膜层，该超薄氧化硅层21的厚度为0.5nm～0.25nm。非晶硅层22的厚度为30nm～300nm，优选为100nm～150nm。氧化硅掩膜层23的厚度为10nm～100nm，优选为20nm～50nm。
超薄氧化硅层21和磷掺杂的非晶硅层22与P型硅片10一起形成PN结。而氧化硅掩膜层23的主要作用是，在后续制绒工序中保护第一表面11上的PN结区(超薄氧化硅层21、掺杂的非晶硅层22等)不被含碱的制绒 药液所腐蚀。
目前通常采用低压化学气相沉积(LPCVD)形成非晶硅层22，然后对非晶硅层22进行磷扩散，在P型硅片10上形成磷掺杂的多晶硅层30和氧化硅掩膜层23的工艺方法制备P型背接触太阳电池100。这种生产工艺制备的氧化硅掩膜层23为非晶硅层22通过磷扩散形成的PSG(磷硅玻璃)。该氧化硅掩膜层23在制绒时可以对P型硅片10背面的多晶硅层30起到一定的保护作用，在一定程度上避免多晶硅层30被含碱的制绒药液所破坏。
然而，采用上述工艺制备的氧化硅掩膜层23，由于其是通过对非晶硅层22进行磷扩散形成的，该氧化硅掩膜层23的生长是自限制反应，所制备的氧化硅掩膜层23的厚度一般很小(小于20nm)，对碱液的耐腐蚀时间较短；而且该氧化硅掩膜层23中存在高浓度的磷掺杂，高浓度的磷掺杂也会导致氧化硅掩膜层23的耐碱性降低。通常氧化硅掩膜层23中的磷掺杂浓度越高，其耐碱性能越低。通过上述工艺制备的P型背接触太阳电池100在制绒时，仍然存在磷掺杂的氧化硅掩膜层23对多晶硅层30的保护时间窗口较窄的问题。即从制绒开始到多晶硅层30开始被破坏的时间间隔较短。
本发明通过采用PECVD在非晶硅层22上单独形成氧化硅掩膜层23，可以方便地根据氧化硅掩膜层23的实际耐碱性需要，控制氧化硅掩膜层23的厚度。氧化硅掩膜层23的厚度可以达到100nm，而LPCVD结合磷扩散形成的氧化硅掩膜层23的厚度一般小于20nm。在同样的镀膜工艺条件，镀膜膜层生长速度和时间为线性关系，通过控制PECVD的沉积时间，即可方便地控制氧化硅掩膜层23的生长厚度。而在同样的碱腐蚀条件下，氧化硅掩膜层23的厚度与耐碱腐蚀的时间成正比，即氧化硅掩膜层23的厚度增加，其耐碱腐蚀的时间也将延长。采用本发明的方法可以获得厚度更大的氧化硅掩膜层23，从而可以有效地延长后续制绒工序的制绒时间窗口。
本发明中之所以采用PECVD单独形成非晶硅层22和氧化硅掩膜层23，而不采用LPCVD单独形成非晶硅层22和额外生成的氧化硅掩膜层23，其主要原因在于：LPCVD沉积非晶硅/多晶硅的温度一般为550℃～650℃；在LPCVD设备中直接通入氧气，虽然可以完成外侧氧化硅的生长，但是氧化硅的生长厚度随着温度/时间是抛物线型曲线。大于10nm的氧化硅在600℃时需要几个小时才能完成；为了实现阻挡碱液腐蚀以及增加磷扩散的浓度，需要将扩散和氧化温度提升到800℃以上，以快速增加氧化硅厚度。因此，需要将设备从LPCVD沉积非晶/多晶硅的温度(550℃～650℃)升温到800℃，之后设备还要降温进行下一批硅片的生产工艺。设备不断循环差异200℃以上升降温，需要增加两个小时以上的工艺时间。将LPCVD沉积和掺杂元素扩散氧化拆分为两个设备，是更加经济的做法。因此，本发明采用PECVD单独形成非晶硅层22和氧化硅掩膜层23。
步骤S300：对硅片衬底10进行退火处理，以使氧化硅掩膜层23致密化，并使磷掺杂的非晶硅层22晶化形成磷掺杂的多晶硅层30。退火处理之后的P型硅片10及各膜层的结构如图4所示。
本发明对PECVD制备的氧化硅掩膜层23进行退火处理，可使得氧化硅掩膜层23得到致密化。无论是采用PEVCD还是LPCVD所生长的氧化硅掩膜层23通常是较为疏松的，其内部存在一些空洞，影响其耐碱腐蚀性能。本发明通过对氧化硅掩膜层23进行退火处理，在高温退火过程中PECVD生长的氧化硅会变得更加致密，消除膜层内部的一些空洞，可以增强氧化硅掩膜层23在碱性溶液中的耐腐蚀性，从而可以更好地保护N型区域(晶硅膜层等)不被腐蚀，延长后续制绒工序的制绒时间窗口，降低电池的漏电风险。
与此同时，在退火过程中也可以使PEVCD沉积的非晶硅(a-Si)向多晶硅(poly)转化，并使晶粒生长变大，使磷掺杂的非晶硅层22转化为多 晶硅层30。
在其中一些实施例中，退火处理的退火温度为800℃～950℃，退火时间为30min～120min。在此退火工艺条件下，可以使氧化硅掩膜层23得到充分致密化，有效延长制绒时间窗口；并使磷掺杂的非晶硅层22充分转化为磷掺杂多晶硅层30。
可以理解，退火温度可以为800℃、820℃、850℃、880℃、900℃、920℃、950℃等具体值；进一步优选地，退火温度为850℃～900℃。退火时间可以为30min、40min、60min、80min、100min、120min等具体值。
步骤S400：对P型硅片10进行退火处理之后，对第一表面11上的氧化硅掩膜层23进行图案化处理，以将部分区域的氧化硅掩膜层23去除，从而形成图案化区域40。图案化处理后的结构如图5所示。
在对第一表面11上的氧化硅掩膜层23进行退火处理之后，本发明对第一表面11上的氧化硅掩膜层23进行图案化处理，去除掉第一表面11上部分区域的氧化硅掩膜层23，从而形成图案化区域40。该图案化区域40用于制备与P型硅片10直接相连的电极。图案化区域40的宽度为300μm～500μm。可以采用本领域中的现有工艺对氧化硅掩膜层23进行图案化处理，只要能够按照一定的图形将部分的氧化硅掩膜层23去除即可。
步骤S500：形成图案化区域40之后，利用制绒药液对P型硅片10的第一表面11和第二表面12进行浸泡处理，以去除图案化区域40内的超薄氧化硅层21和多晶硅层30，并使第二表面11形成绒面。整个制绒工序有多个槽体，制绒做完后，经去离子水清洗、碱洗(碱和双氧水的混合液)、去离子水清洗、酸洗(氢氟酸或者氢氟酸和盐酸的混合液，氢氟酸可以去除氧化硅掩膜)、去离子水清洗、经氢氟酸浸泡后去除氧化硅掩膜层23后的结构如图6所示。
通过上述方法，可以实现对P型硅片10的第二表面12(正面)进行制 绒形成绒面，同时对第一表面11上的图案化区域40进行刻蚀处理，有效地去除图案化区域40内的超薄氧化硅层21和多晶硅层30，从而露出图案化区域40对应的第一表面11。电池片背面的其他区域则由于有氧化硅掩膜层23的保护而不会被制绒药液腐蚀破坏。制绒完成之后，采用含有氢氟酸的溶液进行酸洗，即可将该氧化硅掩膜层23去除。
在其中一些实施例中，制绒药液为含有制绒添加剂的碱溶液，制绒浸泡处理的温度为35℃～85℃，制绒浸泡处理的时间为200s～550s。在此工艺条件下，既可以使P型硅片10的第二表面12能够充分制绒形成绒面，又能够有效地去除图案化区域40内的超薄氧化硅层21和多晶硅层30，露出相应的第一表面11，并且不会使露出的第一表面11产生绒面。
步骤S600：在P型硅片10的第一表面11上和第二表面12上分别沉积钝化膜层50；然后在第一表面11上和第二表面12上的钝化膜层50上分别沉积减反射膜层60。通过设置钝化膜层50和减反射膜层60可以分别起到钝化作用和减少电池片反射率的作用。
在其中一些实施例中，钝化膜层50为通过ALD(原子层沉积)方法生长的氧化铝膜层，该钝化膜层50的厚度为2nm～25nm；减反射膜层60为氮化硅、氮氧化硅和氧化硅中的任意一种膜层或者多种的组合膜层，该减反射膜层60的厚度为50nm～150nm。
步骤S700：利用激光对硅片衬底10的第一表面11上的图案化区域40进行图案化开孔，以去除开孔处的钝化膜层50和减反射膜层60形成电极接触区70；然后在电极接触区70内和多晶硅层30内注入电极浆料(多晶硅层30内注入的为烧穿型浆料，可以烧穿钝化膜层50和减反射膜层60)，分别形成第一电极80和第二电极90。对图案化区域40开孔后的结构如图7所示。
其中，第一电极80与硅片衬底10直接连接，第二电极90与第一表面 11上的图案化区域40以外区域的多晶硅层30直接连接。在其中一些实施例中，第一电极80为铝栅线电极，第一电极80的宽度为50μm～200μm；第二电极90为银栅线电极，第二电极90的宽度为10μm～50μm。
具体地，利用激光对图案化区域40进行图案化开孔时，使开孔区域呈虚线或者点状分布，开孔宽度为30μm～50μm，即电极接触区70的宽度为30μm～50μm。可以采用丝网印刷的方式在电极接触区70内和多晶硅层30内，形成包含导电成分的电极浆料层，分别作为第一电极80和第二电极90。
本发明另一实施例提供了另外一种P型背接触太阳电池100的制备方法，该制备方法包括如下步骤S100至步骤S1000。
步骤S100：提供P型硅片10，该P型硅片10具有第一表面11和与第一表面11相对的第二表面12。
P型硅片10的第一表面11和第二表面12中，其中一个表面为背接触太阳电池100的受光面(正面)，另一个表面为背接触太阳电池100的背光面(背面)。在其中一些实施例中，以P型硅片10的第一表面11作为背面，以第二表面12作为正面，PN结区及金属电极均设置在第一表面11上。
在其中一些实施例中，还对该P型硅片10进行去损伤处理、抛光处理和清洗处理，以使P型硅片10的表面清洁平整，利于进行后续的镀膜工序。其具体流程如下：使用60℃左右的含有KOH的溶液对P型硅片10的表面进行去损伤处理；然后在75℃左右条件下使用含有KOH的溶液对P型硅片10进行抛光处理，使抛光后的P型硅片10表面反射率达到30％；再使用含有氢氟酸和盐酸的混合溶液对抛光后的P型硅片10进行清洗；最后用去离子水清洗并烘干。
步骤S200：在P型硅片10的第一表面11上形成厚度为0.5nm～2.5nm的超薄氧化硅层21，通过PECVD在超薄氧化硅层21上依次形成磷掺杂的 非晶硅层22和氧化硅掩膜层23。
在其中一个具体示例中，先采用PECVD在第一表面11上沉积超薄氧化硅层21，然后采用PECVD在超薄氧化硅层21上沉积非晶硅层22，再采用PECVD在非晶硅层22上沉积氧化硅掩膜层23。
在另外一些实施例中，也可以采用热氧或链氧等方式在第一表面11上生长超薄氧化硅层21，然后采用PECVD在超薄氧化硅层21上依次沉积非晶硅层22和氧化硅掩膜层23。
采用PECVD形成非晶硅层22时以SiH 4为硅源，并采用PH 3气体作为磷源，对非晶硅层22进行磷掺杂。PECVD生长上述膜层时，沉积温度一般为350℃～550℃。
超薄氧化硅层21为一层紧靠第一表面11设置的氧化硅膜层，该超薄氧化硅层21的厚度为0.5nm～0.25nm。非晶硅层22的厚度为30nm～300nm，优选为100nm～150nm。氧化硅掩膜层23的厚度为10nm～100nm，优选为20nm～50nm。
步骤S300：对硅片衬底10进行退火处理，以使氧化硅掩膜层23致密化，并使磷掺杂的非晶硅层22晶化形成磷掺杂的多晶硅层30。
在退火过程中可以使PEVCD沉积的非晶硅(a-Si)向多晶硅(poly)转化，并使晶粒生长变大，使磷掺杂的非晶硅层22转化为多晶硅层30；并使氧化硅掩膜层23致密化。
在其中一些实施例中，退火处理的退火温度为800℃～950℃，退火时间为30min～120min。
步骤S400：使用链式氢氟酸(氢氟酸体积比为5％～35％，常温)仅去除第二表面12的氧化硅掩膜绕镀(链式，即水平放置，水平行进，上表面覆盖水膜，下表面与溶液反应，溶液不高于上表面)。
步骤S500：槽式制绒。制绒完整工艺流程为碱洗(双氧水+一元强碱如 NaOH/KOH，温度50℃～65℃，碱体积占比0.3％～1.5％，时间60s～300s)、去离子水清洗、制绒、去离子水清洗、碱洗、去离子水清洗、酸洗(盐酸溶液，不包含氢氟酸，因为HF和氧化硅反应，会去除之前的氧化硅掩膜层23)、去离子水清洗、烘干。
步骤S600：第二表面12高温氧化。此时第二表面12已经制绒，没有氧化硅保护，高温氧化的温度为700℃～900℃，时间为20min～50min。
步骤S700：对第一表面11上的氧化硅掩膜层23进行图案化处理，以将部分区域的氧化硅掩膜层23去除，从而形成图案化区域40。
步骤S800：槽式刻蚀。其流程为：刻蚀-水洗-碱洗-水洗-酸洗(含HF，去除正背面多余的氧化硅掩膜层23)-水洗-烘干。
步骤S900：在P型硅片10的第一表面11上和第二表面12上分别沉积钝化膜层50；然后在第一表面11上和第二表面12上的钝化膜层50上分别沉积减反射膜层60。
步骤S1000：利用激光对硅片衬底10的第一表面11上的图案化区域40进行图案化开孔，以去除开孔处的钝化膜层50和减反射膜层60形成电极接触区70；然后在电极接触区70内和多晶硅层30内注入电极浆料(多晶硅层30内注入的为烧穿型浆料，可以烧穿钝化膜层50和减反射膜层60)，分别形成第一电极80和第二电极90。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若 干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (21)

  1. 一种太阳电池的制备方法，其特征在于，包括如下步骤：
    提供硅片，所述硅片具有第一表面和与所述第一表面相对的第二表面；
    在所述硅片的所述第一表面形成超薄氧化硅层，在所述超薄氧化硅层上依次形成磷掺杂非晶硅层和氧化硅掩膜层；及
    对所述硅片进行退火处理，以使所述氧化硅掩膜层致密化，并使所述磷掺杂非晶硅层转化为磷掺杂的多晶硅层。
  2. 根据权利要求1所述的太阳电池的制备方法，其特征在于，通过等离子体增强化学气相沉积法，在所述超薄氧化硅层上依次形成所述磷掺杂非晶硅层和所述氧化硅掩膜层。
  3. 根据权利要求2所述的太阳电池的制备方法，其特征在于，通过等离子体增强化学气相沉积法形成所述磷掺杂非晶硅层和所述氧化硅掩膜层的沉积温度为350℃～550℃。
  4. 根据权利要求1至3任一项所述的太阳电池的制备方法，其特征在于，所述退火处理的退火温度为800℃～950℃，退火时间为30min～120min。
  5. 根据权利要求1至4任一项所述的太阳电池的制备方法，其特征在于，所述退火处理的退火温度为850℃～900℃。
  6. 根据权利要求1至5任一项所述的太阳电池的制备方法，其特征在于，所述磷掺杂非晶硅层的厚度为30nm～300nm。
  7. 根据权利要求1至6任一项所述的太阳电池的制备方法，其特征在于，所述磷掺杂非晶硅层的厚度为100nm～150nm。
  8. 根据权利要求1至7任一项所述的太阳电池的制备方法，其特征在于，所述氧化硅掩膜层的厚度为10nm～100nm。
  9. 根据权利要求1至8任一项所述的太阳电池的制备方法，其特征在于，所述氧化硅掩膜层的厚度为20nm～50nm。
  10. 根据权利要求1至9任一项所述的太阳电池的制备方法，其特征在于，所述超薄氧化硅层的厚度为0.5nm～2.5nm。
  11. 根据权利要求1所述的太阳电池的制备方法，其特征在于，所述硅片为P型硅片。
  12. 根据权利要求1至11任一项所述的太阳电池的制备方法，其特征在于，对所述硅片进行退火处理之后，所述制备方法还包括：
    对所述第一表面上的所述氧化硅掩膜层进行图案化处理，以将部分区域的所述氧化硅掩膜层去除形成图案化区域。
  13. 根据权利要求12所述的太阳电池的制备方法，其特征在于，形成所述图案化区域之后，所述制备方法还包括如下步骤：
    利用制绒药液对所述硅片的所述第一表面和所述第二表面进行浸泡处理，以去除所述图案化区域内的所述超薄氧化硅层和所述多晶硅层，并使所述第二表面形成绒面。
  14. 根据权利要求13所述的太阳电池的制备方法，其特征在于，所述浸泡处理的温度为35℃～85℃，所述浸泡处理的时间为200s～550s。
  15. 根据权利要求13或14所述的太阳电池的制备方法，其特征在于，在对所述第一表面和所述第二表面进行浸泡处理之后，所述制备方法还包括如下步骤：
    在所述硅片的所述第一表面上和所述第二表面上沉积钝化膜层；及
    在所述第一表面上和所述第二表面上的所述钝化膜层上沉积减反射膜层。
  16. 根据权利要求15所述的太阳电池的制备方法，其特征在于，所述钝化膜层为氧化铝膜层，所述钝化膜层的厚度为2nm～25nm。
  17. 根据权利要求15或16所述的太阳电池的制备方法，其特征在于，所述减反射膜层为氮化硅、氮氧化硅和氧化硅中的任意一种膜层或者多种 的组合膜层，所述减反射膜层的厚度为50nm～150nm。
  18. 根据权利要求15至17任一项所述的太阳电池的制备方法，其特征在于，在沉积形成所述减反射膜层之后，所述制备方法还包括如下步骤：
    利用激光对所述第一表面上的所述图案化区域进行图案化开孔，去除开孔处的所述钝化膜层和所述减反射膜层形成电极接触区；及
    在所述电极接触区内和所述多晶硅层注入电极浆料，分别形成第一电极和第二电极。
  19. 根据权利要求18所述的太阳电池的制备方法，其特征在于，所述第一电极为铝栅线电极，所述第一电极的宽度为50μm～200μm。
  20. 根据权利要求18或19所述的太阳电池的制备方法，其特征在于，所述第二电极为银栅线电极，所述第二电极的宽度为10μm～50μm。
  21. 一种太阳电池，其特征在于，所述太阳电池通过权利要求1至20任一项所述的太阳电池的制备方法制备得到。
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Families Citing this family (6)

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Publication number Priority date Publication date Assignee Title
CN114823973A (zh) * 2022-04-20 2022-07-29 通威太阳能(眉山)有限公司 一种p型背接触太阳电池及其制备方法
CN114792743B (zh) * 2022-05-05 2024-07-05 通威太阳能（成都）有限公司 太阳电池及其制备方法、光伏系统
CN115411150B (zh) * 2022-09-29 2024-07-09 通威太阳能（成都）有限公司 太阳电池及其制备方法
CN119730434A (zh) * 2023-09-25 2025-03-28 横店集团东磁股份有限公司 太阳能电池及其制备方法和用电装置
CN118658933B (zh) * 2024-08-20 2024-11-19 金阳(泉州)新能源科技有限公司 一种背接触电池的制备方法、背接触电池以及光伏组件
CN121463575B (zh) * 2026-01-05 2026-04-14 福建省金石能源股份有限公司 一种设置组合掩膜层的背接触太阳电池制造方法及其电池

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170047458A1 (en) * 2015-08-11 2017-02-16 Alliance For Sustainable Energy, Llc Hydrogenation of passivated contacts
CN108538962A (zh) * 2018-05-07 2018-09-14 泰州中来光电科技有限公司 一种钝化接触的ibc电池的制备方法
CN113345970A (zh) * 2021-06-04 2021-09-03 浙江爱旭太阳能科技有限公司 一种p型背接触式晶硅太阳能电池、制备方法及电池组件
CN113972302A (zh) * 2021-10-26 2022-01-25 通威太阳能(眉山)有限公司 TOPCon电池及其制备方法和电器设备
CN114823973A (zh) * 2022-04-20 2022-07-29 通威太阳能(眉山)有限公司 一种p型背接触太阳电池及其制备方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7659475B2 (en) * 2003-06-20 2010-02-09 Imec Method for backside surface passivation of solar cells and solar cells with such passivation
TWI559563B (zh) * 2011-12-21 2016-11-21 太陽電子公司 混合式多晶矽異質接面背接觸電池
US10014425B2 (en) * 2012-09-28 2018-07-03 Sunpower Corporation Spacer formation in a solar cell using oxygen ion implantation
CN107195704A (zh) * 2017-06-01 2017-09-22 晋能清洁能源科技有限公司 一种ibc电池制备方法
CN212750903U (zh) * 2020-10-15 2021-03-19 嘉兴阿特斯光伏技术有限公司 太阳能电池
CN113659033A (zh) * 2021-07-08 2021-11-16 浙江爱旭太阳能科技有限公司 一种p型背接触太阳能电池的制备方法
CN113611755A (zh) * 2021-08-06 2021-11-05 无锡琨圣智能装备股份有限公司 一种局部钝化接触的ibc电池结构及其制备方法
CN113964216B (zh) * 2021-09-22 2023-10-27 泰州隆基乐叶光伏科技有限公司 一种背接触电池及其制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170047458A1 (en) * 2015-08-11 2017-02-16 Alliance For Sustainable Energy, Llc Hydrogenation of passivated contacts
CN108538962A (zh) * 2018-05-07 2018-09-14 泰州中来光电科技有限公司 一种钝化接触的ibc电池的制备方法
CN113345970A (zh) * 2021-06-04 2021-09-03 浙江爱旭太阳能科技有限公司 一种p型背接触式晶硅太阳能电池、制备方法及电池组件
CN113972302A (zh) * 2021-10-26 2022-01-25 通威太阳能(眉山)有限公司 TOPCon电池及其制备方法和电器设备
CN114823973A (zh) * 2022-04-20 2022-07-29 通威太阳能(眉山)有限公司 一种p型背接触太阳电池及其制备方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4513577A4 *

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