WO2023205939A1 - 电容器及其制备方法 - Google Patents

电容器及其制备方法 Download PDF

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Publication number
WO2023205939A1
WO2023205939A1 PCT/CN2022/088747 CN2022088747W WO2023205939A1 WO 2023205939 A1 WO2023205939 A1 WO 2023205939A1 CN 2022088747 W CN2022088747 W CN 2022088747W WO 2023205939 A1 WO2023205939 A1 WO 2023205939A1
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Prior art keywords
plate
conductive part
capacitor
substrate
dielectric layer
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PCT/CN2022/088747
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English (en)
French (fr)
Inventor
汤岑
饶进
刘涛
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to EP22938798.0A priority Critical patent/EP4468367A4/en
Priority to CN202280088965.3A priority patent/CN118541810A/zh
Priority to PCT/CN2022/088747 priority patent/WO2023205939A1/zh
Priority to JP2024557681A priority patent/JP2025511636A/ja
Publication of WO2023205939A1 publication Critical patent/WO2023205939A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/62—Capacitors having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors (thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]

Definitions

  • the present disclosure relates to the field of capacitors, and more specifically to a capacitor with ultra-low loss performance at high frequencies and a preparation method thereof.
  • capacitors in the form of Metal-Oxide-Semiconductor Field-Effect Transistor can be introduced at the input end to match the input impedance, thereby striving to obtain RF devices.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • embodiments of the present disclosure relate to technical solutions related to capacitors, and specifically provide a capacitor and a preparation method thereof for reducing the loss of the capacitor at high frequencies.
  • a capacitor in a first aspect of the present disclosure, includes: a substrate having a first surface and a second surface opposite to the first surface; the substrate is provided with a through hole penetrating from the first surface to the second surface; a first plate coupled to the first surface of the substrate; a first conductive portion disposed on the second surface of the substrate; a second conductive portion disposed on a side of the first plate facing the through hole; and a third conductive portion part is disposed on the inner wall of the through hole, thereby coupling the first conductive part to the second conductive part.
  • an effective bypass effect can be formed on the substrate, thereby significantly reducing the risk of the capacitor under high-frequency operating conditions. Lower dielectric loss, thereby improving the performance of the capacitor.
  • the first plate includes a first portion and a second portion
  • the capacitor further includes: a first dielectric layer on and coupled to the first portion of the first plate; and a second An electrode plate is located on the first dielectric layer and coupled to the first electrode plate through the first dielectric layer. In this way, stable operation of the capacitor can be ensured.
  • the capacitor further includes a second dielectric layer located on the second portion of the first plate and at least a portion of the second plate. In this way, the components of the capacitor can be protected against water or shock.
  • the first dielectric layer includes at least one of the following materials: silicon nitride, silicon oxide, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide. In this way, a variety of materials can be used to prepare the first dielectric layer, which makes the preparation of the first dielectric layer more flexible.
  • the second plate includes at least one of the following materials: gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, tantalum, titanium nitride, tungsten silicide, and tantalum nitride .
  • gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, tantalum, titanium nitride, tungsten silicide, and tantalum nitride in this way, similarly, a variety of materials can be used to prepare the second electrode plate, which makes its preparation more flexible.
  • the second dielectric layer includes at least one of the following materials: silicon nitride, silicon oxide, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide. In this way, a suitable material can be selected from various materials according to actual design requirements to prepare the second dielectric layer.
  • the first conductive part, the second conductive part and the third conductive part are integrally formed. In this way, each conductive portion can be formed easily and quickly.
  • the cross-section of the through hole when viewed along a direction perpendicular to the first surface, is circular, elliptical, elongated, or polygonal. In this way, desired through holes can be obtained according to different design requirements.
  • the first conductive portion, the second conductive portion, and the third conductive portion include at least one of the following materials: nickel, titanium, aluminum, lead, platinum, gold, titanium nitride, nitride Tantalum and copper. In this way, the short-circuit effect between the first surface and the second surface of the substrate can be ensured through the conductive characteristics of the conductive portion, thereby ensuring the performance of the capacitor.
  • the first plate includes at least one of the following materials: gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, tantalum, titanium nitride, tungsten silicide, and tantalum nitride .
  • a suitable material can be flexibly selected from various materials according to actual design requirements to prepare the first electrode plate.
  • a method of manufacturing a capacitor includes: providing a substrate having a first surface and a second surface opposite to the first surface; providing a through hole penetrating from the first surface to the second surface in the substrate; A first electrode plate is provided on the substrate, and the first electrode plate is coupled to the first surface of the substrate; a first conductive portion is provided on the second surface of the substrate; a side of the first electrode plate facing the through A second conductive part is provided on one side of the hole; and a third conductive part is provided on an inner wall of the through hole, thereby coupling the first conductive part to the second conductive part.
  • the first plate includes a first portion and a second portion
  • the method further includes: providing a dielectric material on the first plate; and removing a portion of the dielectric material coupled to the second portion. part to form the first dielectric layer.
  • the method further includes providing a second plate on the first dielectric layer, the second plate being coupled to the first plate via the first dielectric layer.
  • the method further includes: providing a wrapping material on a second portion of the first plate and the second plate; and removing a portion of the wrapping material on the second plate to A second dielectric layer is formed.
  • the first dielectric layer includes at least one of the following materials: silicon nitride, silicon oxide, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.
  • the second plate includes at least one of the following materials: gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, tantalum, titanium nitride, tungsten silicide, and tantalum nitride .
  • the second dielectric layer includes at least one of the following materials: silicon nitride, silicon oxide, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.
  • the first conductive part, the second conductive part and the third conductive part are integrally formed.
  • the cross-section of the through hole when viewed along a direction perpendicular to the first surface, is circular, elliptical, elongated, or polygonal.
  • the first conductive portion, the second conductive portion, and the third conductive portion include at least one of the following materials: nickel, titanium, aluminum, lead, platinum, gold, titanium nitride, nitride Tantalum and copper.
  • the first plate includes at least one of the following materials: gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, tantalum, titanium nitride, tungsten silicide, and tantalum nitride .
  • Figure 1 shows a cross-sectional view of the structure of a conventional capacitor
  • Figure 2 shows a schematic equivalent circuit diagram of the capacitor of Figure 1;
  • FIG. 3 shows a structural cross-sectional view of a capacitor according to an illustrative embodiment of the present disclosure
  • Figure 4 shows an equivalent circuit schematic diagram of the capacitor of Figure 3
  • 5A-5I illustrate schematic steps for forming a capacitor according to an embodiment of the present disclosure
  • FIG. 6 illustrates a method of preparing a capacitor according to an illustrative embodiment of the present disclosure
  • FIG. 7A and 7B each illustrate a top view of a capacitor according to an illustrative embodiment of the present disclosure.
  • FIG. 1 a schematic diagram of a cross-section of a capacitor 100' structure in the prior art is shown.
  • the capacitor 100' generally includes a substrate 110', a dielectric layer 140' and an electrode plate 150' arranged in a stacked structure, wherein the dielectric layer 140' is located above the substrate 110', and the electrode plate 150' is located above the dielectric layer 140'.
  • FIG. 2 shows an equivalent circuit schematic diagram of the capacitor 100' in Figure 1. Since the substrate 110' will introduce resistance in the entire capacitor 100', the equivalent capacitor 200' in Figure 2 is equivalent to the equivalent series connection of the dielectric layer 240' and the plate 250' in the capacitor 200'. a resistor R'. Since the equivalent resistance R' introduced by the substrate 110' is proportional to its thickness d', in some conventional solutions, the thickness d' of the substrate 110' can be reduced. The thinning of the bottom 110' reduces the resistance R' introduced by the substrate 110' in the entire capacitor 100', thereby reducing the high-frequency loss of the capacitor 100'. However, due to process limitations, there is a certain bottleneck in thinning the substrate 110'.
  • the thickness d' of the substrate 110' it is difficult to reduce the thickness d' of the substrate 110' to less than 50 ⁇ m. Therefore, the degree of loss reduction is limited. What is even more undesirable is that since the substrate 110' itself has unavoidable high-frequency losses, no matter how low its thickness d' is reduced, it will still bring non-negligible losses to the capacitor 100'. Since the substrate 110' cannot be ignored, the resistor R' must also exist, and the resistance of the resistor R' will cause high-frequency loss.
  • embodiments of the present disclosure provide a capacitor capable of ultra-low loss performance at high frequencies and a manufacturing method thereof.
  • capacitor 300 In a first aspect, a capacitor according to an illustrative embodiment of the present disclosure is provided.
  • Figure 3 shows a cross-sectional view of the capacitor 300.
  • capacitor 300 generally includes a substrate 310, a first plate 320, a first dielectric layer 340, and a second plate 350 in a stacked structure.
  • the substrate 310 has a first surface 311 and a second surface 312 opposite the first surface 311 .
  • the first electrode plate 320 is coupled to the first surface 311 of the substrate 310, and a first dielectric layer 340 and a second electrode plate 350 are sequentially disposed above the first electrode plate 320.
  • a through hole 315 penetrating from the first surface 311 to the second surface 312 is provided in the substrate 310 .
  • the through hole 315 exposes a portion of the first plate 320 .
  • the capacitor 300 also has a plurality of conductive parts, including a first conductive part 331 disposed on the second surface 312 of the substrate 310, a side of the first plate 320 facing the through hole 315 (ie, the first plate 320
  • the second conductive portion 332 (the portion exposed by the through hole 315) and the third conductive portion 333 disposed on the inner wall 316 of the through hole 315.
  • the third conductive portion 333 can couple the first conductive portion 331 to the second conductive portion 332. , so that the conductive part of the capacitor 300 is formed as a whole.
  • the first plate 320 by arranging the first plate 320 on the first surface 311 of the substrate 310, applying a back hole process on the second surface 312 of the substrate 310, and on the second surface 312 and the through hole of the substrate 310, By applying a conductive part inside the hole 315, the first surface 311 and the second surface 312 of the substrate 310 can be short-circuited through the conductive part, thus forming an effective bypass effect on the substrate 310.
  • FIG. 4 shows an equivalent circuit diagram of the capacitor 300 in FIG. 3 .
  • the first plate 320 and the substrate 310 are short-circuited through the first plate 320 of the capacitor 300 in FIG. 3 , the through hole 315 penetrating the substrate 310 and each conductive part, so that the first The resistance introduced by the plate 320 and the substrate 310 can be ignored.
  • the first dielectric in the equivalent capacitor 400 The layer 440 and the second plate 450 can be considered not to be in series with the equivalent resistance R′. In this way, the dielectric loss of the capacitor 300 under high-frequency operating conditions can be significantly reduced.
  • the first conductive part 331 , the second conductive part 332 and the third conductive part 333 may include at least one of the following materials: nickel, titanium, aluminum, lead, platinum, gold, Titanium nitride, tantalum nitride and copper.
  • the conductive portion may be made from any combination of these materials. In this way, through the conductive effect of these conductive parts, a short circuit between the first plate 320 at the first surface 311 of the substrate 310 and the second surface 312 of the substrate 310 can be achieved, thereby ensuring high frequency loss. of reduction.
  • the materials listed here are only illustrative and not exhaustive.
  • the first conductive part 331 , the second conductive part 332 and the third conductive part 333 can also be made of other conductive materials existing or developed in the future, as long as such conductive materials can achieve the expected short circuit effect.
  • FIGS. 5A-5I A schematic process of forming the capacitor 500 of an embodiment of the present disclosure is described below with reference to the steps illustrated in FIGS. 5A-5I. It should be understood that these illustrated steps are only examples and are not intended to be exhaustive or limit the scope of the present disclosure. There may also be any other suitable transformation methods to form the capacitor 500, which will not be described again herein.
  • a substrate 510 having a first surface 511 and a second surface 512 is provided.
  • Substrate 510 may be fabricated from semiconductor wafers known in the industry or developed in the future.
  • such a semiconductor wafer may be made of one or more of silicon, silicon carbide, gallium nitride, aluminum nitride and other materials. It should be understood that the materials listed here are only illustrative and not exhaustive.
  • such a semiconductor wafer may be a conductive wafer, a semi-insulating wafer or an insulating wafer. That is to say, the embodiments of the present disclosure do not place any limitation on the conductivity of the semiconductor wafer.
  • the figure shows that the first surface 511 and the second surface 512 of the substrate 510 are parallel, it should be noted that this is not necessary.
  • the first surface 511 and the second surface 512 may have a certain non-zero included angle.
  • a first plate 520 is provided above the first surface 511 of the substrate 510 .
  • the first plate 520 is also called the lower plate.
  • the first plate 520 may be made of metal, such as one or more of gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, and tantalum.
  • the first electrode plate 520 may also be made of alloy materials, such as one or more of titanium nitride, tungsten silicide, and tantalum nitride. It should be understood that the materials listed here are illustrative only and not limiting. Those skilled in the art can consider other materials to make the first plate 520 .
  • the first plate 520 can be formed by depositing a layer of metal by electron beam evaporation, magnetron sputtering, or the like. It should be noted that the deposition method described here is only for illustrative purposes and is not limiting. The material can be deposited through other deposition methods that are known or developed in the future, so that the material can be deposited on the first surface 511 of the substrate 510 A first plate 520 is provided above.
  • a first dielectric layer 540 is deposited over the first plate 520 .
  • the thickness of the first dielectric layer 540 may range from 20 nm to 500 nm. It should be noted that the numerical values here are only illustrative and not restrictive.
  • the first dielectric layer 540 may include at least one of the following materials: silicon nitride, silicon oxide, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.
  • the first dielectric layer 540 may be a single-layer structure or a multi-layer stacked structure, and its specific structure is not limited by the embodiments of the present disclosure.
  • a first portion 521 and a second portion 522 different from the first portion 521 can be determined on the first plate 520 .
  • the portion of the first dielectric layer 540 coupled to the second portion 522 may be removed through an etching process while retaining the portion of the first dielectric layer 540 coupled to the first portion 521 to form the final first dielectric layer 540 . That is to say, unnecessary parts can be etched away through a suitable process and a part of the dielectric material can be left to form the first dielectric layer 540 .
  • the design capacitance of the capacitor 500 is proportional to the area of the first dielectric layer 540 , the area of the first dielectric layer 540 that needs to be retained can be calculated based on the desired capacitance of the final capacitor 500 .
  • the specific calculation method is not limited by the embodiments of the present disclosure.
  • the embodiments of the present disclosure do not limit the technology for obtaining the first dielectric layer 540 .
  • the final first dielectric layer 540 may be obtained through various wet etching or dry etching processes.
  • a second plate 550 is provided above the first dielectric layer 540 .
  • the second plate 550 is also called the upper plate.
  • the second electrode plate 550 may be made of metal material, such as one or more of gold, silver, aluminum, nickel, titanium, platinum, copper, tungsten, tin, and tantalum.
  • the second electrode plate 550 may be made of an alloy material, such as one or more of titanium nitride, tungsten silicide, and tantalum nitride.
  • the second electrode plate 550 may be made of the same material as the first electrode plate 520 , or may be made of a different material than the first electrode plate 520 .
  • the metal pattern of the second electrode plate 550 can be determined by means of a photolithography process. In other embodiments, the pattern can also be obtained through a metal evaporation process or a metal dry etching process. It should be understood that the processes mentioned here are only illustrative.
  • a second dielectric layer 560 may be formed above the second plate 550 .
  • the thickness of the second dielectric layer 560 may range from 20 nm to 2000 nm. It should be noted that the numerical values here are only illustrative and not restrictive.
  • the second dielectric layer 560 may include at least one of the following materials: silicon nitride, silicon oxide, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide. It should be understood that the materials listed here are illustrative only and not limiting. Those skilled in the art can envision other materials to make the second dielectric layer 560 .
  • second dielectric layer 560 may be the same material as first dielectric layer 540 . In other embodiments, the second dielectric layer 560 and the first dielectric layer 540 may also be made of different materials.
  • the second dielectric layer 560 may be a single-layer structure or a multi-layer stacked structure, and its specific structure is not limited by the embodiments of the present disclosure.
  • a portion of the second dielectric layer 560 can be removed through an etching process on the second plate 550 while retaining the remaining portion of the second dielectric layer 560 to form a final second dielectric layer. 560. That is to say, unnecessary parts can be etched away through appropriate processes and a part of the dielectric material can be retained to form the second dielectric layer 560 .
  • the second dielectric layer 560 may be called a wrapping layer and is used to protect other components of the capacitor 500 from moisture, impact, etc.
  • the final second dielectric layer 560 may be obtained through various wet etching or dry etching processes.
  • the second dielectric layer 560 may be obtained by using the same process as the first dielectric layer 540 , or may be obtained by using a different process from the first dielectric layer 540 .
  • deep hole etching is performed on the second surface 512 of the substrate 510 to obtain the through hole 515 shown in the figure.
  • etching the through hole 515 By etching the through hole 515, a portion of the first plate 520 will be exposed, and the inner wall 516 of the through hole 515 will also be exposed.
  • two through holes 515 are shown in the figure, this is not limiting. The number of through holes 515 can be determined according to actual process requirements.
  • the two through holes 515 shown in FIG. 5H extend parallel to each other. In this manner, the through hole 515 and a portion of the first plate 520 may be exposed.
  • the parallelism here is only illustrative, and it does not require absolute parallelism in a strict sense, but allows a certain degree of non-parallelism between the plurality of through holes 515 .
  • the depth direction of the through holes 515 is generally perpendicular to the second surface 512 of the substrate 510 . It should be understood that this is only illustrative, and the through hole 515 and the second surface 512 of the substrate 510 may be at other angles, such as 85 degrees, 80 degrees, 75 degrees, and so on. Specific angles are not limited by the embodiments of the present disclosure.
  • a metal stack material is deposited on one side of the second surface 512 of the substrate 510 .
  • Such metal stack materials will be deposited on the first surface 512 of the substrate 510 and the exposed parts of the first plate 520 respectively. and the inner wall 516 of the through hole 515 , thereby forming corresponding first conductive portions 531 , second conductive portions 532 and third conductive portions 533 .
  • the third conductive part 533 couples the first conductive part 531 and the second conductive part 532 together, so that each conductive part becomes a whole.
  • the thickness of the first conductive part 531 , the second conductive part 532 and the third conductive part 533 may range from 20 nm to 1500 nm. It should be noted that the numerical values here are only illustrative and not restrictive. In other embodiments, the first conductive part 531 , the second conductive part 532 and the third conductive part 533 may include at least one of the following materials: nickel, titanium, aluminum, lead, platinum, gold, titanium nitride, Tantalum nitride and copper. It should be understood that the materials listed here are illustrative only and not limiting. Those skilled in the art can envision other materials for making these conductive parts.
  • the substantially square wave-shaped electrodes are coupled to each other.
  • the conductive part can short-circuit the second surface 512 of the substrate 510 and the first plate 520 together, which can form an effective bypass effect on the substrate 510 and the first plate 520, thereby ensuring the reduction of high-frequency losses. .
  • FIGS. 5A to 5I show schematic steps for manufacturing the capacitor 500 , it should be understood that these steps do not have to be performed strictly in the order shown in the figures, and some of the steps may be interchanged with each other.
  • FIGS. 5D and 5E show that the pattern of the first dielectric layer 540 is formed first, and then the second plate 550 is provided above the patterned first dielectric layer 540 .
  • the first dielectric layer 540 and the second electrode plate 550 can be graphically defined. Such steps should be considered to fall within embodiments of the present disclosure.
  • the through hole 515 is formed after the first dielectric layer 540, the second plate 550 and the second dielectric layer 560 are formed.
  • the through hole 515 may also be formed.
  • the formation of the first dielectric layer 540, the second plate 550 and the second dielectric layer 560 is performed before or simultaneously. Such steps should also be considered to fall within embodiments of the present disclosure.
  • the individual components in the figures are not drawn to scale, and the dimensional relationships between these components are merely illustrative.
  • FIG. 6 illustrates in the form of a block diagram a preparation method 600 according to the second aspect of the present disclosure to prepare the aforementioned semiconductor device 500 .
  • a substrate 510 having a first surface 511 and a second surface 512 is provided.
  • the substrate 510 may be, for example, a wafer commonly referred to in the art.
  • a via 515 is provided in the substrate 510 from the first surface 511 to the second surface 512. This can be accomplished by any suitable means.
  • the first plate 520 is provided on the first surface 511 of the substrate 510 so that the first plate 520 is coupled to the first surface 511.
  • first conductive portion 531 is provided on second surface 512 of substrate 510.
  • a second conductive portion 532 is formed on the surface of the first plate 520 facing the through hole 515 and exposed by the through hole 515
  • a third conductive portion 532 is formed on the inner wall 516 of the through hole 515 .
  • FIG. 7A and 7B illustrate a top view of the capacitor 700 according to an exemplary embodiment of the present disclosure, in which some schematic structures and layouts of the through holes 715 and their positional relationship with the second plate 750 can be seen.
  • the cross-section of through hole 715 may be generally elliptical when viewed in a direction perpendicular to the surface of the substrate in FIG. 5 .
  • the through hole 715 may also be in a long strip shape.
  • those skilled in the art can conceive various other shapes, such as circles, semicircles, triangles, squares, rectangles, rounded rectangles or other polygons, and the specific shapes are not limited by the present disclosure. Limitations of Examples.

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Abstract

本公开的实施例提供了一种电容器以及制造电容器的方法。该电容器包括：衬底，具有第一表面和与该第一表面相对的第二表面，该衬底设置有从该第一表面贯穿至该第二表面的通孔；第一极板，耦合至该衬底的该第一表面；第一导电部，设置在该衬底的该第二表面；第二导电部，设置在该第一极板的面向该通孔的一侧；以及第三导电部，设置在该通孔的内壁，从而将该第一导电部耦合至该第二导电部。通过本方案，将衬底的第一表面与第二表面经由各个导电部进行短接，这样可以对衬底形成有效的旁路作用，从而能够显著地降低电容器在高频工况下的介质损耗，提高电容器的性能。

Description

电容器及其制备方法 技术领域
本公开涉及电容器领域，更具体而言涉及一种在高频下具有超低损耗性能的电容器及其制备方法。
背景技术
在射频信号的应用领域，往往涉及射频工况的信号放大和传输。在传统的射频器件封装结构中，可以在输入端引入采用金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)形式的电容器进行输入阻抗的匹配，从而力求获得射频器件性能的充分发挥。对于输入端的电容器而言，由于衬底的电极材料的物理特性限制，在高频工况下容易造成射频损耗。随着电容器的工作频段的提升，这些射频损耗会随之进一步加剧。因而，如何降低电容器的射频损耗，是设计者面临的一项挑战。
发明内容
鉴于上述问题，本公开的实施例涉及关于电容器的技术方案，并且具体提供了一种电容器及其制备方法，用于降低电容器在高频下的损耗。
在本公开的第一方面，提供了一种电容器。该电容器包括：衬底，具有第一表面和与该第一表面相对的第二表面，该衬底设置有从该第一表面贯穿至该第二表面的通孔；第一极板，耦合至该衬底的该第一表面；第一导电部，设置在该衬底的该第二表面；第二导电部，设置在该第一极板的面向该通孔的一侧；以及第三导电部，设置在该通孔的内壁，从而将该第一导电部耦合至该第二导电部。
根据本公开的实施例，通过将衬底的第一表面与第二表面经由各个导电部进行短接，这样可以对衬底形成有效的旁路作用，从而能够显著地降低电容器在高频工况下的介质损耗，由此提高电容器的性能。
在一些实现方式中，该第一极板包括第一部分和第二部分，该电容器还包括：第一介电层，位于该第一极板的第一部分上并耦合至该第一部分；以及第二极板，位于该第一介电层上经由该第一介电层耦合至该第一极板。以此方式，可以确保电容器的稳定工作。
在一些实现方式中，该电容器还包括：第二介电层，位于该第一极板的该第二部分以及该第二极板的至少一部分上。以此方式，可以对电容器的部件起到防水或者防冲击的作用。
在一些实现方式中，该第一介电层包括以下材料中的至少一种：氮化硅、氧化硅、氮氧化硅、氧化硅、氧化铝和氧化钛。以此方式，多种材料都可以用来制备第一介质层，这使得第一介质层的制备更加灵活。
在一些实现方式中，该第二极板包括以下材料中的至少一种：金、银、铝、镍、钛、铂、铜、钨、锡、钽、氮化钛、硅化钨和氮化钽。以此方式，类似地，多种材料都可以用来制备第二极板，这使得其制备更加灵活。
在一些实现方式中，该第二介电层包括以下材料中的至少一种：氮化硅、氧化硅、氮氧化硅、氧化硅、氧化铝和氧化钛。以此方式，可以从各种材料中根据实际的设计需求选择合适的材料制备第二介电层。
在一些实现方式中，该第一导电部、该第二导电部和该第三导电部是一体形成的。以此 方式，可以方便快速地形成各导电部。
在一些实现方式中，沿着垂直于该第一表面的方向观察，该通孔的截面是圆形、椭圆形、长条形或者多边形。以此方式，能够根据不同的设计需求来获得期望的通孔。
在一些实现方式中，该第一导电部、该第二导电部和该第三导电部包括以下材料中的至少一种：镍、钛、铝、铅、铂、金、氮化钛、氮化钽和铜。以此方式，通过导电部的导电特性，可以确保衬底的第一表面与第二表面的短接效果，从而保障电容器的性能。
在一些实现方式中，该第一极板包括以下材料中的至少一种：金、银、铝、镍、钛、铂、铜、钨、锡、钽、氮化钛、硅化钨和氮化钽。以此方式，可以从各种材料中根据实际的设计需求灵活地选择合适的材料制备第一极板。
在本公开的第二方面，提供了一种制造电容器的方法。该方法包括：提供衬底，该衬底具有第一表面和与该第一表面相对的第二表面；在该衬底内提供从该第一表面贯穿至该第二表面的通孔；在该衬底上提供第一极板，该第一极板耦合至该衬底的该第一表面；在该衬底的该第二表面提供第一导电部；在该第一极板的面向该通孔的一侧提供第二导电部；以及在该通孔的内壁提供第三导电部，从而将该第一导电部耦合至该第二导电部。
在一些实现方式中，该第一极板包括第一部分和第二部分，该方法还包括：在该第一极板提供介电材料；以及移除该介电材料的与该第二部分耦合的部分，以形成第一介电层。
在一些实现方式中，该方法还包括：在该第一介电层上提供第二极板，该第二极板经由该第一介电层耦合至该第一极板。
在一些实现方式中，该方法还包括：在该第一极板的第二部分以及该第二极板上提供包裹材料；以及移除该包裹材料的在该第二极板上的一部分，以形成第二介电层。
在一些实现方式中，该第一介电层包括以下材料中的至少一种：氮化硅、氧化硅、氮氧化硅、氧化硅、氧化铝和氧化钛。
在一些实现方式中，该第二极板包括以下材料中的至少一种：金、银、铝、镍、钛、铂、铜、钨、锡、钽、氮化钛、硅化钨和氮化钽。
在一些实现方式中，该第二介电层包括以下材料中的至少一种：氮化硅、氧化硅、氮氧化硅、氧化硅、氧化铝和氧化钛。
在一些实现方式中，该第一导电部、该第二导电部和该第三导电部是一体形成的。
在一些实现方式中，沿着垂直于该第一表面的方向观察，该通孔的截面是圆形、椭圆形、长条形或者多边形。
在一些实现方式中，该第一导电部、该第二导电部和该第三导电部包括以下材料中的至少一种：镍、钛、铝、铅、铂、金、氮化钛、氮化钽和铜。
在一些实现方式中，该第一极板包括以下材料中的至少一种：金、银、铝、镍、钛、铂、铜、钨、锡、钽、氮化钛、硅化钨和氮化钽。
应当理解，发明内容部分中所描述的内容并非旨在限定本公开的实现方式的关键或重要特征，亦非用于限制本公开的范围。本公开的其它特征将通过以下的描述变得容易理解。
附图说明
结合附图并参考以下详细说明，本公开各实施例的上述和其他特征、优点及方面将变得更加明显。在附图中，相同或相似的附图标记表示相同或相似的元素，其中：
图1示出了现有的电容器的结构的横截面视图；
图2示出了图1的电容器的等效电路示意图；
图3示出了根据本公开的示意性实施例的电容器的结构横截面视图；
图4示出了图3的电容器的等效电路示意图；
图5A至图5I示出了一种形成本公开的实施例的电容器的示意性步骤；
图6示出了根据本公开的示意性实施例的制备电容器的方法；以及
图7A和图7B分别示出了根据本公开的示意性实施例的电容器的俯视视图。
具体实施方式
下面将参照附图更详细地描述本公开的实施例。虽然附图中显示了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
在本公开的实施例的描述中，术语“包括”及其类似用语应当理解为开放性包含，即“包括但不限于”。术语“基于”应当理解为“至少部分地基于”。术语“一个实施例”或“该实施例”应当理解为“至少一个实施例”。术语“第一”、“第二”等等可以指代不同的或相同的对象。术语“和/或”表示由其关联的两项的至少一项。例如“A和/或B”表示A、B、或者A和B。下文还可能包括其他明确的和隐含的定义。
应理解，本公开实施例提供的技术方案，在以下具体实施例的介绍中，某些重复之处可能不再赘述，但应视为这些具体实施例之间已有相互引用，可以相互结合。
如上文所讨论的，业界希望找到一种能够降低射频损耗的电容器。如图1所示，其示出了现有技术中的电容器100’结构的横截面的示意图。如所示出，电容器100’总体上包括呈堆叠结构依次排布的衬底110’、介电层140’以及极板150’，其中介电层140’位于衬底110’的上方，极板150’位于介电层140’的上方。
随着电容器的工作频率的提升，介电层140’和极板150’都会随之存在射频损耗，这会导致信号的传输速度变慢，从而给信号的高速传输带来很大的调整。在现有技术中已经提出了一些方案来降低电容器100’的这种射频损耗。
图2示出了图1中的电容器100’的等效电路示意图。由于衬底110’会在整个电容器100’中引入电阻阻值，因此图2中的等效电容器200’就相当于在电容器200’内的介电层240’以及极板250’等效串联了一个电阻R’。由于衬底110’引入的等效电阻R’与其厚度d’存在比例关系，因此，在一些常规的方案中，可以使衬底110’的厚度d’减小，这种方式旨在通过使衬底110’变薄来降低衬底110’在整个电容器100’中引入的电阻R’的阻值，从而使电容器100’的高频损耗降低。然而，由于工艺制程的限制，衬底110’的变薄是存在一定瓶颈限制的，例如，很难将衬底110’的厚度d’降低至50μm以下。因此损耗降低的程度是有限的。更加不理想的是，由于衬底110’本身存在无法避免的高频损耗，因此无论将其厚度d’降到多低，也仍然会给电容器100’带来不可忽视的损耗。由于衬底110’是无法忽略的，因此电阻R’也是必然存在的，且该电阻R’的阻值会引起高频损耗。
至少为了解决上述问题，本公开的实施例提供了一种能够在高频下具有超低损耗性能的电容器及其制备方法。
在第一方面，提供了一种根据本公开的示意性实施例的电容器。图3示出了该电容器300的横截面视图。如所示出，电容器300总体上包括呈堆叠结构的衬底310、第一极板320、第 一介电层340和第二极板350。衬底310具有第一表面311和与第一表面311相对的第二表面312。第一极板320耦合至衬底310的第一表面311，并在第一极板320的上方依次设置有第一介电层340和第二极板350。此外，如图3所示，衬底310内设置有从第一表面311贯穿至第二表面312的通孔315。通孔315使第一极板320的一部分暴露出来。电容器300还具有多个导电部，包括设置在衬底310的第二表面312上的第一导电部331、设置在第一极板320的面向通孔315的一侧(即第一极板320的被通孔315暴露的部分)的第二导电部332以及设置在通孔315的内壁316的第三导电部333，第三导电部333可以将第一导电部331耦合至第二导电部332，从而使得电容器300的导电部是形成为一个整体的。
根据本公开的实施例，通过在衬底310的第一表面311设置第一极板320、在衬底310的第二表面312施加背孔工艺，并且在衬底310的第二表面312及通孔315的内部施加导电部，可以将衬底310的第一表面311与第二表面312经由导电部进行短接，这样可以对衬底310形成有效的旁路作用。
图4示出了图3中的电容器300的等效电路示意图。如图4所示，通过图3中的电容器300的第一极板320、贯穿衬底310的通孔315以及各导电部，实现第一极板320和衬底310的短接，这样第一极板320和衬底310所引入的电阻可以被忽略。相比于图2所示的现有方案中的电路结构，图4中的等效电容器400中并不存在由电阻R’引起的高频损耗，因此在等效电容器400内的第一介电层440以及第二极板450可以视为不与等效电阻R’串联。以此方式，可以显著地降低电容器300在高频工况下的介质损耗。
返回参考图3，在一些实施例中，第一导电部331、第二导电部332和第三导电部333可以包括以下材料中的至少一种：镍、钛、铝、铅、铂、金、氮化钛、氮化钽和铜。在其他实施例中，导电部可以由这些材料的任意组合来制成。以此方式，通过这些导电部的传导作用，可以实现设置衬底310的第一表面311处的第一极板320与衬底310的第二表面312之间的短接，从而确保高频损耗的降低。应该理解的是，这里所列举的材料仅仅是示意性的，并非是穷尽性的。第一导电部331、第二导电部332和第三导电部333还可以由现有的或者将来研究出的其他导电材料来制成，只要这样的导电材料可以实现预期的短接效果即可。
下面参考图5A至图5I示出的各步骤来描述形成本公开的实施例的电容器500的示意性过程。应当理解的是，这些示出的步骤只是示例，并非穷举也并非限制本公开的保护范围。还可能存在其他任意适当的变换方式来形成电容器500，在本文中将不再赘述。
如图5A所示，提供具有第一表面511和第二表面512的衬底510。衬底510可以由业界已知或者在将来开发出的半导体晶圆来制成。在一些实施例中，这样的半导体晶圆可以由硅、碳化硅、氮化镓、氮化铝等材料中的一种或多种来制成。应该理解的是，这里所列举的材料仅仅是示意性的，并非是穷尽性的。在另一些实施例中，这样的半导体晶圆的可以为导电性晶圆、半绝缘性晶圆或绝缘性晶圆。也就是说，本公开的实施例对半导体晶圆的导电性不做任何限定。虽然图上示出了衬底510的第一表面511和第二表面512是平行的，但是需要说明的是，这并非是必须的。第一表面511和第二表面512可以存在一定的非零夹角。
继续参照图5B，在衬底510的第一表面511的上方提供第一极板520。第一极板520又被称作下极板。在一些实施例中，第一极板520可以由金属制成，例如金、银、铝、镍、钛、铂、铜、钨、锡、钽中的一种或多种。在另一些实施例中，第一极板520也可以由合金材料制成，例如氮化钛、硅化钨和氮化钽中的一种或多种。应该理解的是，这里列举的材料仅是示意性的，而非限制性的。本领域技术人员可以设想其他材料来制作第一极板520。在一些 实施例中，可以通过电子束蒸发、磁控溅射等方式沉积一层金属来形成该第一极板520。需要说明的是，这里描述的沉积方式仅是起说明作用，而非限制作用，可以经由已知的或者将来开发出的其他沉积方式来对材料进行沉积，从而在衬底510的第一表面511的上方提供第一极板520。
继续参考图5C，在第一极板520的上方沉积第一介电层540。在一些实施例中，该第一介电层540的厚度可以介于20nm至500nm之间。需要说明的是，这里的数值仅是示意性的，而不是限制性的。在另一些实施例中，第一介电层540可以包括以下材料中的至少一种：氮化硅、氧化硅、氮氧化硅、氧化硅、氧化铝和氧化钛。第一介电层540可以是单层结构，也可以是多层堆叠结构，其具体构造不受到本公开的实施例的限制。
继续参考图5D，可以在第一极板520上确定出第一部分521以及与第一部分521不同的第二部分522。可以通过刻蚀工艺移除第一介电层540的与第二部分522耦合的部分，同时保留第一介电层540的与第一部分521耦合的部分，从而形成最终的第一介电层540。也就是说可以通过合适的工艺刻蚀掉不必要的部分并留下一部分介电材料，以形成第一介电层540。由于电容器500的设计电容与第一介电层540的面积是成比例的，因此，可以基于所需要得到的最终电容器500的所需电容来计算得到需要保留的第一介电层540的面积。具体的计算方法不受到本公开的实施例的限制。
需要说明的是，本公开的实施例对于得到第一介电层540的技术不做限制。例如，在一些实施例中，可以通过各种湿法刻蚀或者干法刻蚀工艺来获得最终的第一介电层540。
继续参考图5E，在第一介电层540上方提供第二极板550。第二极板550又被称作上极板。在一些实施例中，第二极板550可以由金属材料制成，例如金、银、铝、镍、钛、铂、铜、钨、锡、钽中的一种或多种。在另一些实施例中，第二极板550可以由合金材料来制成，例如氮化钛、硅化钨和氮化钽中的一种或多种。第二极板550可以与第一极板520是相同的材料，也可以与第一极板520是不同的材料。在第二极板550是金属的情况下，可以借助于光刻工艺来确定第二极板550的金属图形。在另一些实施例中，还可以通过金属蒸发工艺或者金属的干法刻蚀工艺来获得该图形。应该理解的是，这里提及的工艺也仅仅是示意性的。
继续参考图5F，可以在第二极板550的上方形成第二介电层560。在一些实施例中，该第二介电层560的厚度可以介于20nm至2000nm之间。需要说明的是，这里的数值仅是示意性的，而不是限制性的。在另一些实施例中，第二介电层560可以包括以下材料中的至少一种：氮化硅、氧化硅、氮氧化硅、氧化硅、氧化铝和氧化钛。应该理解的是，这里列举的材料仅是示意性的，而非限制性的。本领域技术人员可以设想其他材料来制作第二介电层560。在一些实施例中，第二介电层560可以与第一介电层540是相同的材料。在另一些实施例中，第二介电层560也可以与第一介电层540是不同的材料。第二介电层560可以是单层结构，也可以是多层堆叠结构，其具体构造不受到本公开的实施例的限制。
继续参考图5G，可以在第二极板550上通过刻蚀工艺移除掉第二介电层560的一部分，同时保留第二介电层560的其余部分，从而形成最终的第二介电层560。也就是说可以通过合适的工艺刻蚀掉不必要的部分且保留一部分介电材料，以形成第二介电层560。第二介电层560可以被称作包裹层，用于对电容器500的其他部件进行保护，以避免这些部件遭到水分、冲击等影响。
类似于第一介电层540，需要说明的是，本公开的实施例对于得到第二介电层560的技术不做限制。例如，在一些实施例中，可以通过各种湿法刻蚀或者干法刻蚀工艺来获得最终 的第二介电层560。第二介电层560既可以是采用与第一介电层540相同的工艺获得，也可以是与第一介电层540采用不同的工艺获得。
继续参考图5H，如图所示，对衬底510的第二表面512上进行深孔刻蚀，从而获得图上所示的通孔515。通过刻蚀出通孔515，第一极板520的一部分将会暴露，同时通孔515的内壁516也会被暴露出来。虽然图上示出了两个通孔515，然而这并不是限制性的。通孔515的数目可以根据实际的工艺需求来确定。此外，如图5H所示的两个通孔515彼此平行地延伸。以此方式，可以暴露出通孔515和第一极板520的一部分。应该理解的是，这里的平行仅是示意性的，其并不要求严格意义上的绝对平行，而是允许在多个通孔515之间存在一定的不平行程度。此外，在图5的实施例中，这些通孔515的深度方向是大体垂直于衬底510的第二表面512。应该理解的是，这也仅仅是示意性的，通孔515与衬底510的第二表面512可以呈其他的角度，例如85度、80度、75度，等等。具体的角度不受到本公开的实施例的限制。
最后参考图5I，在衬底510的第二表面512的一侧沉积金属叠层材料，这样的金属叠层材料会分别沉积在衬底510的第一表面512、第一极板520的被暴露的部分以及通孔515的内壁516上，从而形成对应的第一导电部531、第二导电部532以及第三导电部533。如图5I所示，第三导电部533将第一导电部531和第二导电部532耦合在一起，从而使得各导电部成为一个整体。在一些实施例中，第一导电部531、第二导电部532以及第三导电部533的厚度可以介于20nm至1500nm之间。需要说明的是，这里的数值仅是示意性的，而不是限制性的。在另一些实施例中，第一导电部531、第二导电部532以及第三导电部533可以包括以下材料中的至少一种：镍、钛、铝、铅、铂、金、氮化钛、氮化钽和铜。应该理解的是，这里列举的材料仅是示意性的，而非限制性的。本领域技术人员可以设想其他材料来制作这些导电部。
由于第一导电部531位于衬底510的第二表面512上，第二导电部532位于第一极板520的被暴露的部分上，因此经由相互被耦合在一起的大致呈方波形状的各导电部，可以将衬底510的第二表面512与第一极板520短接在一起，这样可以对衬底510和第一极板520形成有效的旁路作用，从而确保高频损耗的降低。
需要说明的是，虽然图5A至图5I示出了制造电容器500的示意性步骤，但是应该理解的是，这些步骤不必严格按照图上示出的次序来进行，其中的一些步骤可以相互对调。例如，图5D和图5E中示出了先形成第一介电层540的图形、随后在已经确定图形的第一介电层540上方提供第二极板550，然而，在其他实施例中，还可以在第一极板520整个表面的上方形成第一介电层540和第二极板550之后，再对第一介电层540和第二极板550进行图形化定义。这样的步骤应该视为落入本公开的实施例中。再如，在图示的实施例中，通孔515是在形成第一介电层540、第二极板550以及第二介电层560之后，然而，可以理解的是，通孔515也可以在形成第一介电层540、第二极板550以及第二介电层560之前进行或者同步进行。这样的步骤也应该视为落入本公开的实施例中。此外，图上的各个部件并不是按比例绘制的，这些部件之间的尺寸关系也仅是示意性的。
图6以框图的形式示出了根据本公开的第二方面的制备方法600，以制备前文中所提到的半导体器件500。如图6所示，在框602，提供具有第一表面511和第二表面512的衬底510。衬底510例如可以是本领域通常所提到的晶圆。接下来，在框604，在衬底510内提供从第一表面511贯穿至第二表面512的通孔515。这可以通过任意适当的方式来实现。在形 成通孔515之后，在框606，在衬底510的第一表面511上提供第一极板520，使第一极板520耦合该第一表面511。然后，在框608，在衬底510的第二表面512提供第一导电部531。如框610和框612分别示出，在第一极板520的面向通孔515的一侧的被通孔515暴露出的表面形成第二导电部532，并且在通孔515的内壁516形成第三导电部533。第三导电部533将第二导电部532与第一导电部531耦合在一起。
图7A和图7B示出了根据本公开的示意性实施例的电容器700的俯视视图，其中可以看出通孔715的一些示意性结构和布局，以及与第二极板750的位置关系。在一些实施例中，如图7A所示，当沿着垂直于图5中的衬底的表面的方向观察时，通孔715的截面可以是大致呈椭圆形。在图7B所示的实施例中，通孔715还可以是长条形。然而，可以理解的是，本领域技术人员可以构想出其他各种图形，例如圆形、半圆形、或者是三角形、正方形、长方形、圆角矩形或其他多边形，具体的形状不受到本公开的实施例的限制。
尽管已经采用特定于结构特征和/或方法逻辑动作的语言描述了本主题，但是应当理解所附权利要求书中所限定的主题未必局限于上面描述的特定特征或动作。相反，上面所描述的特定特征和动作仅仅是实现权利要求书的示例形式。

Claims (21)

  1. 一种电容器(1)，包括：
    衬底(10)，具有第一表面(11)和与所述第一表面(11)相对的第二表面(12)，所述衬底(10)内设置有从所述第一表面(11)贯穿至所述第二表面(12)的通孔(15)；
    第一极板(20)，耦合至所述衬底(10)的所述第一表面(11)；
    第一导电部(31)，设置在所述衬底(10)的所述第二表面(12)；
    第二导电部(32)，设置在所述第一极板(20)的面向所述通孔(15)的一侧；以及
    第三导电部(33)，设置在所述通孔(15)的内壁(16)，从而将所述第一导电部(31)耦合至所述第二导电部(32)。
  2. 根据权利要求1所述的电容器(1)，其中所述第一极板(20)包括第一部分(21)和第二部分(22)，所述电容器(1)还包括：
    第一介电层(40)，位于所述第一极板(20)的第一部分(21)上并耦合至所述第一部分(21)；以及
    第二极板(50)，位于所述第一介电层(40)上经由所述第一介电层(40)耦合至所述第一极板(20)。
  3. 根据权利要求2所述的电容器(1)，还包括：
    第二介电层(60)，位于所述第一极板(20)的所述第二部分(22)以及所述第二极板(50)的至少一部分上。
  4. 根据权利要求2至3中任一项所述的电容器(1)，其中所述第一介电层(40)包括以下材料中的至少一种：氮化硅、氧化硅、氮氧化硅、氧化硅、氧化铝和氧化钛。
  5. 根据权利要求2至4中任一项所述的电容器(1)，其中所述第二极板(50)包括以下材料中的至少一种：金、银、铝、镍、钛、铂、铜、钨、锡、钽、氮化钛、硅化钨和氮化钽。
  6. 根据权利要求3所述的电容器(1)，其中所述第二介电层(60)包括以下材料中的至少一种：氮化硅、氧化硅、氮氧化硅、氧化硅、氧化铝和氧化钛。
  7. 根据权利要求1至6中任一项所述的电容器(1)，其中所述第一导电部(31)、所述第二导电部(32)和所述第三导电部(33)是一体形成的。
  8. 根据权利要求1至7中任一项所述的电容器(1)，其中沿着垂直于所述第一表面(11)的方向观察，所述通孔(15)的截面是圆形、椭圆形、长条形或者多边形。
  9. 根据权利要求1至8中任一项所述的电容器(1)，其中所述第一导电部(31)、所述第二导电部(32)和所述第三导电部(33)包括以下材料中的至少一种：镍、钛、铝、铅、铂、金、氮化钛、氮化钽和铜。
  10. 根据权利要求1至9中任一项所述的电容器(1)，其中所述第一极板(20)包括以下材料中的至少一种：金、银、铝、镍、钛、铂、铜、钨、锡、钽、氮化钛、硅化钨和氮化钽。
  11. 一种制造电容器(1)的方法，包括：
    提供衬底(10)，所述衬底(10)具有第一表面(11)和与所述第一表面(11)相对的第二表面(12)；
    在所述衬底(10)内提供从所述第一表面(11)贯穿至所述第二表面(12)的通孔(15)；
    在所述衬底(10)上提供第一极板(20)，所述第一极板(20)耦合至所述衬底(10)的 所述第一表面(11)；
    在所述衬底(10)的所述第二表面(12)提供第一导电部(31)；
    在所述第一极板(20)的面向所述通孔(15)的一侧提供第二导电部(32)；以及
    在所述通孔(15)的内壁(16)提供第三导电部(33)，从而将所述第一导电部(31)耦合至所述第二导电部(32)。
  12. 根据权利要求11所述的方法，其中所述第一极板(20)包括第一部分(21)和第二部分(22)，所述方法还包括：
    在所述第一极板(20)提供介电材料；以及
    移除所述介电材料的与所述第二部分(22)耦合的部分，以形成第一介电层(40)。
  13. 根据权利要求12所述的方法，还包括：
    在所述第一介电层(40)上提供第二极板(50)，所述第二极板(50)经由所述第一介电层(40)耦合至所述第一极板(20)。
  14. 根据权利要求13所述的方法，还包括：
    在所述第一极板(20)的第二部分(22)以及所述第二极板(50)上提供包裹材料；以及
    移除所述包裹材料的在所述第二极板(50)上的一部分，以形成第二介电层(60)。
  15. 根据权利要求12至14中任一项所述的方法，其中所述第一介电层(40)包括以下材料中的至少一种：氮化硅、氧化硅、氮氧化硅、氧化硅、氧化铝和氧化钛。
  16. 根据权利要求13至14中任一项所述的方法，其中所述第二极板(50)包括以下材料中的至少一种：金、银、铝、镍、钛、铂、铜、钨、锡、钽、氮化钛、硅化钨和氮化钽。
  17. 根据权利要求14所述的方法，其中所述第二介电层(60)包括以下材料中的至少一种：氮化硅、氧化硅、氮氧化硅、氧化硅、氧化铝和氧化钛。
  18. 根据权利要求11至17中任一项所述的方法，其中所述第一导电部(31)、所述第二导电部(32)和所述第三导电部(33)是一体形成的。
  19. 根据权利要求11至18中任一项所述的方法，其中沿着垂直于所述第一表面(11)的方向观察，所述通孔(15)的截面是圆形、椭圆形、长条形或者多边形。
  20. 根据权利要求11至19中任一项所述的方法，其中所述第一导电部(31)、所述第二导电部(32)和所述第三导电部(33)包括以下材料中的至少一种：镍、钛、铝、铅、铂、金、氮化钛、氮化钽和铜。
  21. 根据权利要求11至20中任一项所述的方法，其中所述第一极板(20)包括以下材料中的至少一种：金、银、铝、镍、钛、铂、铜、钨、锡、钽、氮化钛、硅化钨和氮化钽。
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