WO2023213088A1 - 太阳电池及其制备方法、光伏系统 - Google Patents

太阳电池及其制备方法、光伏系统 Download PDF

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WO2023213088A1
WO2023213088A1 PCT/CN2022/141320 CN2022141320W WO2023213088A1 WO 2023213088 A1 WO2023213088 A1 WO 2023213088A1 CN 2022141320 W CN2022141320 W CN 2022141320W WO 2023213088 A1 WO2023213088 A1 WO 2023213088A1
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film layer
solar cell
silicon
layer
cell according
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French (fr)
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范建彬
孟夏杰
刑国强
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Tongwei Solar Chengdu Co Ltd
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Tongwei Solar Chengdu Co Ltd
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Priority to US18/834,693 priority Critical patent/US20250204077A1/en
Priority to AU2022457204A priority patent/AU2022457204B2/en
Priority to EP22940782.0A priority patent/EP4521473A4/en
Publication of WO2023213088A1 publication Critical patent/WO2023213088A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H10F77/219—Arrangements for electrodes of back-contact photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/128—Annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/129—Passivating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
    • H10F77/162—Non-monocrystalline materials, e.g. semiconductor particles embedded in insulating materials
    • H10F77/164—Polycrystalline semiconductors
    • H10F77/1642—Polycrystalline semiconductors including only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • H10F77/703—Surface textures, e.g. pyramid structures of the semiconductor bodies, e.g. textured active layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the technical field of solar cell production, and in particular to a solar cell, its preparation method, and a photovoltaic system.
  • Back contact battery that is, back contact battery, among which finger-shaped back contact solar cells are also called IBC (Interdigitated back contact) batteries.
  • IBC Interdigitated back contact
  • the biggest feature of IBC batteries is that the PN junction area or PN-like junction area and metal electrodes are located on the back of the battery, and the front of the battery is not blocked by the metal electrodes.
  • IBC battery Due to the above structural characteristics of the IBC battery, it has a higher short-circuit current Jsc. At the same time, the back side can allow wider metal grid lines to reduce the series resistance Rs and thereby increase the fill factor FF. Moreover, this battery with no obstruction on the front not only The conversion efficiency is high and it looks more beautiful. Therefore, IBC cells have become one of the current technical directions for realizing high-efficiency crystalline silicon cells.
  • the back area of the silicon wafer substrate corresponding to the patterned area is also textured, so that the surface of the silicon wafer substrate is textured.
  • the back also forms a suede structure.
  • the formation of a suede structure in the above-mentioned back area will greatly increase the metallization recombination in the back area and reduce the open circuit voltage and conversion efficiency of the battery.
  • a method for preparing a solar cell including the following steps:
  • a silicon wafer substrate having a first surface and a second surface opposite the first surface
  • a laser is used to pattern the first surface to destroy or remove the silicon oxide in the preset area on the first surface.
  • the mask layer and the doped polysilicon film layer form a patterned area.
  • the doped polysilicon film layer formed after annealing has a shallow absorption depth of laser light.
  • silicon oxide reacts slower than silicon in the same alkaline solution, that is, the front side of the battery has begun to texture, while the back side of the battery must first react with the oxide layer and then react with the first surface of the silicon wafer substrate.
  • the oxide layer can be preserved from obvious damage after patterning.
  • This oxide layer can be used to extend the time difference between texturing the front side of the cell and not texturing the back side, achieving good front side fabrication. Only the oxide layer is removed from the textured and back patterned areas, or the oxidized layer is removed from this area and the first surface is only "microtextured". The macroscopic appearance is still flat and has a high reflectivity. This ensures that the battery has higher open circuit voltage and conversion efficiency.
  • the laser is a picosecond pulsed laser.
  • the doped polysilicon film layer formed after annealing has a shallow absorption depth of the picosecond pulse laser. During the patterning process, it can be ensured that the interaction between the picosecond pulse laser and silicon is limited to the doped polysilicon film layer above the oxide layer. Better protect the oxide layer from obvious damage.
  • the wavelength of the picosecond pulsed laser is 355 nm or 532 nm.
  • the pulse width of the picosecond pulse laser is 1 ps to 100 ps.
  • the silicon oxide mask layer is formed by vapor deposition or annealing thermal oxidation.
  • the temperature of the annealing treatment is 800°C to 950°C.
  • the annealing treatment time is 30 to 50 minutes.
  • the doped amorphous silicon film layer can be fully crystallized and fully converted into a doped polysilicon film layer; at the same time, the silicon oxide mask layer can become denser and can be used in the subsequent texturing process.
  • the PN junction area (oxide layer, doped amorphous silicon film layer, etc.) on the first surface is less likely to be corroded by alkali-containing texturing liquid.
  • the oxide layer is a silicon oxide film layer, and the thickness of the oxide layer is 0.5 nm to 2.5 nm.
  • the silicon oxide mask layer has a thickness of 10 nm to 100 nm.
  • the thickness of the doped amorphous silicon film layer is 30 nm to 300 nm.
  • the preparation method further includes the following steps:
  • the silicon wafer substrate is soaked in a texturing liquid to remove the oxide layer in the patterned area and the remaining silicon oxide mask layer and doped polysilicon film layer, and make The second surface forms a textured surface.
  • the second surface of the silicon wafer substrate can be texturized to form a textured surface, while the patterned area on the first surface can be etched to effectively remove the oxide layer and doped polysilicon film in the patterned area.
  • layer, thereby exposing the first surface corresponding to the patterned area, or the exposed first surface is only "micro-textured", that is, it is in the "texturing" stage of texturing, and the macroscopic appearance is still flat with high reflectivity. , will not have a major impact on passivation and metallization composite. Other areas on the back of the cell are protected by the silicon oxide mask layer and will not be corroded and damaged by the texturing solution.
  • the texturing liquid is an alkali solution containing texturing additives.
  • the temperature of the soaking treatment is 30°C to 80°C.
  • the soaking treatment time is 300s to 600s.
  • the second surface of the silicon wafer substrate can be fully textured to form a textured surface, and the oxide layer and oxide layer in the patterned area can be effectively removed.
  • the polysilicon film layer is doped to expose the corresponding first surface, and the exposed first surface will not be textured.
  • the preparation method further includes the following step: depositing a passivation film layer on the first surface and the second surface of the silicon wafer substrate respectively. Passivation can be achieved by setting a passivation film layer.
  • the passivation film layer is an aluminum oxide film layer, and the thickness of the passivation film layer is 2 nm to 25 nm.
  • the preparation method further includes the following steps: respectively depositing anti-reflection on the passivation film layer on the first surface and the second surface. film layer.
  • the reflectivity of the cell can be reduced.
  • the anti-reflection film layer is any one of silicon nitride, silicon oxynitride and silicon oxide or a combination of multiple film layers, and the thickness of the anti-reflection film layer is 50 nm to 50 nm. 150nm.
  • the preparation method further includes the following steps:
  • Electrode slurry is injected into the electrode contact area and the doped polysilicon film layer to form a first electrode and a second electrode respectively.
  • a solar cell is provided, which is prepared by the above-mentioned preparation method of the present application.
  • a photovoltaic system is provided, and the photovoltaic system includes the above-mentioned solar cell of the present application.
  • the above preparation method involves annealing the doped amorphous silicon film layer on the first surface to convert the amorphous silicon in the doped amorphous silicon film layer into polycrystalline silicon to form a doped polycrystalline silicon film layer; and using laser Patterning is performed on a preset area of the first surface, destroying or removing the silicon oxide mask layer and doped polysilicon film layer in the preset area, and retaining all or part of the oxide layer to form a patterned area.
  • laser is used for patterning, all or part of the oxide layer is retained by limiting the interaction between the laser and silicon to the doped polysilicon film layer above the oxide layer.
  • This oxide layer can play a certain blocking role against the subsequent texturing alkali solution, and can extend the time difference from the start of texturing to the formation of a textured surface on the first surface corresponding to the patterned area. While achieving good texturing on the front of the cell, although the thin oxide layer in the laser-patterned area on the back will be corroded, it can ensure that the corresponding part of the patterned area on the back of the cell will not be textured, or will only be "micro-textured.” ”, macroscopically speaking, it is still flat and has high reflectivity, thus ensuring that the battery has high open circuit voltage and conversion efficiency.
  • a picosecond pulse laser is used to pattern the preset area of the first surface after annealing.
  • the doped polysilicon film layer formed after annealing has a shallow absorption depth of the picosecond pulse laser, which ensures the interaction between the laser and silicon. The interaction is limited to the doped polysilicon film layer above the oxide layer, and the oxide layer is retained while destroying or removing the silicon oxide mask layer and the doped polysilicon film layer in the patterned area.
  • Figure 1 is a schematic structural diagram of a solar cell prepared in an embodiment of the present application.
  • Figure 2 is a bottom view of Figure 1;
  • Figure 3 is a schematic structural diagram of a silicon wafer substrate
  • Figure 4 is a schematic structural diagram of the silicon wafer substrate after annealing
  • Figure 5 is a schematic structural diagram of the first surface after patterning
  • Figure 6 is a bottom view after patterning the first surface
  • Figure 7 is a schematic structural diagram of the silicon wafer substrate after texturing and removing the silicon oxide mask layer
  • Figure 8 is a bottom view of the patterned area after opening holes.
  • Silicon wafer substrate 11. First surface; 12. Second surface; 21. Oxide layer; 22. Doped amorphous silicon film layer; 23. Silicon oxide mask layer; 30. Doped polysilicon film layer; 40. Patterned area; 50. Passivation film layer; 60. Anti-reflection film layer; 70. Electrode contact area; 80. First electrode; 90. Second electrode; 100. Back contact solar cell.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include at least one of these features.
  • “plurality” means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.
  • connection In this application, unless otherwise clearly stated and limited, the terms “installation”, “connection”, “connection”, “fixing” and other terms should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. , or integrated into one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two elements or an interactive relationship between two elements, unless otherwise specified restrictions. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.
  • One embodiment of the present application provides a method for preparing a back contact solar cell 100.
  • the structure of the back contact solar cell 100 is as shown in Figures 1 and 2.
  • the preparation method includes the following steps S100 to S800.
  • Step S100 Provide a P-type silicon wafer substrate 10.
  • the silicon wafer substrate 10 has a first surface 11 and a second surface 12 opposite to the first surface 11.
  • the structure of the silicon wafer substrate 10 is shown in FIG. 3 .
  • the silicon wafer substrate 10 is also subjected to damage removal processing, polishing processing and cleaning processing to make the surface of the silicon wafer substrate 10 clean and smooth, which is convenient for subsequent coating processes.
  • the specific process is as follows: use a solution containing KOH at about 60°C to remove damage to the surface of the silicon wafer substrate 10; then use a solution containing KOH to polish the silicon wafer substrate 10 at about 75°C, so that The surface reflectivity of the polished silicon wafer substrate 10 reaches 30%; then a mixed solution containing hydrofluoric acid and hydrochloric acid is used to clean the polished silicon wafer substrate 10; finally, it is cleaned with deionized water and dried.
  • Step S200 sequentially deposit an oxide layer 21, a doped amorphous silicon film layer 22 and a silicon oxide mask layer 23 on the first surface 11 of the silicon substrate 10.
  • the oxide layer 21 is an ultra-thin silicon oxide film layer disposed close to the first surface 11 , and the thickness of the oxide layer 21 is 0.5 nm to 2.5 nm.
  • the doped amorphous silicon film layer 22 is a phosphorus-doped amorphous silicon film layer.
  • the thickness of the doped amorphous silicon film layer 22 is 30 nm to 300 nm, preferably 100 nm to 150 nm.
  • the thickness of the silicon oxide mask layer 23 is 10 nm to 100 nm, preferably 20 nm to 50 nm.
  • the oxide layer 21, the doped amorphous silicon film layer 22 and the silicon oxide mask layer 23 are prepared by the following method: first, chemical vapor deposition (such as LPCVD (Low Pressure Chemical Vapor Deposition, low pressure chemical vapor deposition)
  • the oxide layer 21 is formed on the first surface 11 of the silicon wafer substrate 10 by methods such as vapor phase deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition), hot oxygen, chain oxygen, etc.; and then through chemical vapor deposition ( Such as LPCVD, PECVD), the phosphorus-doped doped amorphous silicon film layer 22 is deposited on the surface of the oxide layer 21 away from the silicon substrate 10; and then the doped amorphous silicon film layer 22 is formed by plasma chemical vapor deposition (PECVD) or annealing thermal oxidation.
  • PECVD plasma chemical vapor deposition
  • a silicon oxide mask layer 23 is formed on the surface of the amorphous silicon film layer 22
  • the oxide layer 21 and the doped amorphous silicon film layer 22 form a PN junction together with the silicon substrate 10 .
  • the main function of the silicon oxide mask layer 23 is to protect the PN junction area (oxide layer 21, doped amorphous silicon film layer 22, etc.) on the first surface 11 from alkali-containing texturing in the subsequent texturing process. Corroded by liquid medicine.
  • Step S300 Perform annealing treatment on the silicon wafer substrate 10 to transform the doped amorphous silicon film layer 22 into the doped polysilicon film layer 30.
  • the structure of the silicon wafer substrate 10 after the annealing process is shown in FIG. 4 .
  • the amorphous silicon (a-Si) in the doped amorphous silicon film layer 22 can be converted into polysilicon (poly), and the crystal grains can grow larger to form the doped polysilicon film layer 30 .
  • the annealing temperature is 800°C to 950°C, and the annealing time is 30 to 50 minutes.
  • the doped amorphous silicon film layer 22 can be fully crystallized and fully converted into the doped polysilicon film layer 30; at the same time, the silicon oxide mask layer 23 can become denser and can be used in the subsequent texturing process.
  • the PN junction area (oxide layer 21, doped amorphous silicon film layer 22, etc.) on the first surface 11 is less likely to be corroded by the alkali-containing texturing solution.
  • Step S400 Use a picosecond pulse laser to pattern the first surface 11 to destroy or remove the silicon oxide mask layer 23 and the doped polysilicon film layer 30 in the preset area, and retain the oxide layer 21 to form a pattern. Area 40.
  • the structures after patterning are shown in Figures 5 and 6.
  • the present application uses a picosecond pulse laser to pattern the first surface 11 to destroy or remove the preset elements on the first surface 11 .
  • the silicon oxide mask layer 23 and the doped polysilicon film layer 30 in the area are formed to form a patterned area 40 .
  • the patterned area 40 is used to prepare electrodes directly connected to the silicon substrate 10 .
  • the width of the patterned area 40 is 300 ⁇ m to 500 ⁇ m.
  • the back-contact solar cell 100 When preparing the back-contact solar cell 100 , it is necessary to simultaneously texture the front side of the cell and etch the patterned area 40 on the back side of the cell to expose the first surface 11 of the P-type silicon substrate 10 .
  • laser is usually used to pattern the silicon oxide mask layer 23. During the patterning process, the laser interacts with silicon, which easily causes damage to the oxide layer 21 in the patterned area 40; thus making the texturing process difficult.
  • the back patterned area 40 While the front side is being textured, the back patterned area 40 will also be textured, so that the first surface 11 of the silicon substrate 10 corresponding to the patterned area 40 also forms a textured structure.
  • the formation of a textured structure in this area will greatly increase the metallization recombination of the first surface 11 in this area, thereby reducing the open circuit voltage and conversion efficiency of the battery.
  • the ideal shape after texturing of the first surface 11 area corresponding to the patterned area 40 is a planar structure.
  • this application performs annealing treatment on the doped amorphous silicon film layer 22 to form the doped polysilicon film layer 30, and then uses a picosecond pulse laser to pattern the first surface 11 to destroy or remove it.
  • the silicon oxide mask layer 23 and the doped polysilicon film layer 30 in the predetermined area on the first surface 11 are removed to form the patterned area 40 .
  • the doped polysilicon film layer 30 formed after annealing has a shallow absorption depth of the picosecond pulse laser. When the picosecond pulse laser is used for patterning, the interaction between the laser and silicon is limited to the doped polysilicon film above the oxide layer 21 Layer 30, oxide layer 21 will not be significantly damaged.
  • oxide layer 21 reacts slower than silicon in the same alkaline solution (such as texturing solution), that is, the front side of the battery has begun to texturize, while the back side of the battery must first react with the oxide layer 21 and then with the silicon.
  • the first surface 11 of the sheet substrate 10 reacts.
  • the oxide layer 21 can be preserved from obvious damage after patterning. This oxide layer 21 can be used to extend the time difference between texturing the front side of the cell and not texturing the back side.
  • the etching depth is less than 1 ⁇ m, and the macroscopic appearance remains It is flat and has high reflectivity, with the reflectivity above 25%. This ensures that the battery has higher open circuit voltage and conversion efficiency.
  • the wavelength of the picosecond pulse laser is 355 nm or 532 nm
  • the pulse width of the picosecond pulse laser is 1 ps to 100 ps, preferably 3 ps to 15 ps.
  • a picosecond laser can be used to remove the silicon oxide mask layer 23 in a partial area of the first surface 11 using the above-mentioned picosecond pulse laser to achieve pattern opening.
  • the first surface 11 area corresponding to the patterned area 40 can be formed into a polished topography structure after the subsequent texturing process. Compared with the case where the first surface 11 area has a textured structure , can effectively reduce the metallization recombination of the aluminum-silicon contact in this area, increase the open circuit voltage of the battery by 2mV to 5mV, thereby increasing the cell efficiency of the back contact solar cell 100 by about 0.1% to 0.2%.
  • Step S500 First use a mixture containing hydrofluoric acid or a mixture containing hydrofluoric acid and concentrated nitric acid to treat only the second surface 12 of the silicon wafer substrate 10 to remove possible bypass plating on the second surface 12, and then use The texturing chemical liquid soaks the silicon wafer substrate 10 to remove the oxide layer 21 in the patterned area 40 and the remaining silicon oxide mask layer 23 and doped polysilicon film layer 30 after the patterning process, and make the second Surface 12 forms a textured surface.
  • this application first uses a mixture containing hydrofluoric acid or a mixture containing hydrofluoric acid and concentrated nitric acid to only pattern the first surface 11.
  • the second surface 12 is processed to remove possible plating around the second surface 12, and then the silicon wafer substrate 10 is processed using texturing liquid to remove the oxide layer 21 and the remaining silicon oxide in the patterned area 40.
  • the mask layer 23 and the doped polysilicon film layer 30 form a textured surface on the second surface 12 .
  • the second surface 12 (front surface) of the silicon wafer substrate 10 can be textured to form a textured surface, and the patterned area 40 on the first surface 11 can be etched to effectively remove the patterned area.
  • the oxide layer 21 and the doped polysilicon film layer 30 in the patterned area 40 expose the first surface 11 corresponding to the patterned area 40, or the exposed first surface 11 is only "micro-textured", that is, in the "texturing" stage of texturing. " stage, the macroscopic appearance is still flat, with high reflectivity (above 25%), which will not have a major impact on passivation and metallization composite. Other areas on the back of the cell are protected by the silicon oxide mask layer 23 and will not be corroded and damaged by the texturing solution.
  • the silicon oxide mask layer 23 can be removed by using an acid solution formula containing hydrofluoric acid for acid cleaning.
  • the structure after texturing and removing the silicon oxide mask layer 23 is shown in FIG. 7 .
  • Texturing is a process of gradual reaction between alkali solution and silicon.
  • the surface is "textured" first, which can be understood as a large number of pyramid spiers.
  • the silicon is etched to a shallow depth, at the level of hundreds of nanometers. It still shows a planar structure, that is, the reflectivity is still high, generally above 25%; as the reaction progresses, due to the anisotropy of the reaction between the alkali solution and silicon, the alkali solution mainly corrodes along the ⁇ 100> crystal plane, and finally at Several four side cones are formed on the surface, that is, a "pyramid" structure.
  • the pyramids are smaller, but the reflectivity has dropped significantly.
  • the pyramids continue to grow larger, and the height of the pyramids at this time is about 1 ⁇ m ⁇ 3 ⁇ m, the reflectivity is generally 9% to 11%.
  • the texturing liquid is an alkali solution containing texturing additives
  • the temperature of the texturing soaking treatment is 30°C to 80°C
  • the time of the texturing soaking treatment is 300s to 600s.
  • Step S600 Deposit the passivation film layer 50 on the first surface 11 and the second surface 12 of the silicon wafer substrate 10 respectively; then deposit the passivation film layer 50 on the first surface 11 and the second surface 11 respectively.
  • Antireflection film layer 60 is deposited.
  • the passivation film layer 50 is an aluminum oxide film layer grown by an ALD (atomic layer deposition) method.
  • the passivation film layer 50 has a thickness of 2 nm to 25 nm;
  • the anti-reflection film layer 60 is silicon nitride. , silicon nitride oxide, silicon oxide, any one film layer or a combination of multiple film layers, and the thickness of the anti-reflection film layer 60 is 50 nm to 150 nm.
  • Step S700 Use a laser to pattern holes in the patterned area 40 on the first surface 11 of the silicon substrate 10 to remove the passivation film layer 50 and the anti-reflection film layer 60 at the hole to form the electrode contact area 70 ; Then, the electrode slurry is injected into the doped polysilicon film layer 30 in the electrode contact area 70 and outside the patterned area 40 to form the first electrode 80 and the second electrode 90 respectively.
  • the structure after opening holes in the patterned area 40 is shown in FIG. 8 .
  • the slurry used in the first electrode 80 is generally a non-burn-through type slurry, that is, it cannot burn through the passivation film layer 50 and the anti-reflection film layer 60 at high temperatures; while the slurry used in the N-type region is a burn-through type and can The passivation film layer 50 and the anti-reflection film layer 60 are burned through.
  • the first electrode 80 is directly connected to the silicon substrate 10
  • the second electrode 90 is directly connected to the doped polysilicon film layer 30 in the area other than the patterned area 40 on the first surface 11 .
  • the first electrode 80 is an aluminum grid electrode, and the width of the first electrode 80 is 50 ⁇ m to 200 ⁇ m; the second electrode 90 is a silver grid electrode, and the width of the second electrode 90 is 10 ⁇ m to 50 ⁇ m.
  • the hole areas are distributed in a dotted line or dot shape, and the width of the holes is 30 ⁇ m to 50 ⁇ m, that is, the width of the electrode contact area 70 is 30 ⁇ m to 50 ⁇ m.
  • Screen printing may be used to form an electrode paste layer containing a conductive component in the electrode contact area 70 and the area outside the patterned area 40 as the first electrode 80 and the second electrode 90 respectively.
  • the structure of the back contact solar cell 100 of the present application is shown in Figures 1 and 2.
  • the back contact solar cell 100 can be used as a battery unit in various photovoltaic systems.
  • the back-contact solar cell 100 of the present application can increase the open circuit voltage of the cell by 2 mV to 5 mV and improve the cell efficiency of the back-contact solar cell 100 by about 0.1% to 0.2%.

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Abstract

本申请涉及一种太阳电池的制备方法，包括如下步骤：提供硅片衬底，硅片衬底具有第一表面和与第一表面相对的第二表面；在硅片衬底的第一表面上依次沉积形成氧化层、掺杂非晶硅膜层和氧化硅掩膜层；对硅片衬底进行退火处理，以使掺杂非晶硅膜层转化为掺杂多晶硅膜层；采用激光对第一表面进行图案化处理，以破坏或去除预设区域的氧化硅掩膜层和掺杂多晶硅膜层，并保留全部或部分氧化层，从而形成图案化区域。该制备方法在对硅片衬底的正面进行制绒时，能够有效地避免硅片衬底的背面图案化区域对应的第一表面也被制绒，提高太阳电池的开路电压和电池效率。并涉及相应的太阳电池、光伏系统。

Description

太阳电池及其制备方法、光伏系统
本申请要求于2022年05月05日提交中国专利局、申请号为2022104796166、发明名称为“太阳电池及其制备方法、光伏系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及太阳电池生产技术领域，特别是涉及一种太阳电池及其制备方法、光伏系统。
背景技术
背接触电池，即back contact电池，其中指状交叉背接触太阳电池又称为IBC(Interdigitatedback contact)电池。IBC电池最大的特点是PN结区或类PN结区以及金属电极都处于电池的背面，电池正面没有金属电极遮挡的影响。
由于IBC电池的上述结构特点，使得其具有更高的短路电流Jsc，同时背面可以容许较宽的金属栅线来降低串联电阻Rs从而提高了填充因子FF，并且，这种正面无遮挡的电池不仅转换效率高，而且看上去也更加美观。因此，IBC电池已成为目前实现高效晶体硅电池的技术方向之一。
背接触电池在制绒时需要同时实现硅片衬底正面的制绒以及背面图案化区域的刻蚀。在图案化区域所对应的硅片衬底背面区域，只需要在制绒时通过制绒药液将该区域的隧穿氧化层和掺杂非晶硅膜层进行去除，而不需要对该区域的硅片衬底进行制绒。
然而，在目前的制绒生产工艺中，往往在对硅片衬底的正面进行制绒的同时，图案化区域所对应的硅片衬底背面区域也会被制绒，从而在硅片衬底的背面也形成绒面结构。而上述背面区域形成绒面结构，会大大增加 该背面区域的金属化复合，降低电池的开路电压以及转化效率。
发明内容
基于此，有必要提供一种在对硅片衬底的正面进行制绒时，能够有效避免图案化区域所对应的硅片衬底背面区域也被制绒的太阳电池及其制备方法、光伏系统。
本申请提出的技术方案如下：
根据本申请的一个方面，提供了一种太阳电池的制备方法，包括如下步骤：
提供硅片衬底，所述硅片衬底具有第一表面和与所述第一表面相对的第二表面；
在所述硅片衬底的所述第一表面上依次层叠形成氧化层、掺杂非晶硅膜层和氧化硅掩膜层；
对所述硅片衬底进行退火处理，以使所述掺杂非晶硅膜层转化为掺杂多晶硅膜层；及
采用激光对所述第一表面进行图案化处理，以破坏或去除预设区域的所述氧化硅掩膜层和所述掺杂多晶硅膜层，并保留全部或部分所述氧化层，从而形成图案化区域。
本申请通过在对掺杂非晶硅膜层进行退火处理，形成掺杂多晶硅膜层之后，采用激光对第一表面进行图案化处理，以破坏或去除掉第一表面上预设区域的氧化硅掩膜层和掺杂多晶硅膜层，形成图案化区域。退火后形成的掺杂多晶硅膜层对激光的吸收深度较浅，在采用激光进行图案化处理时激光和硅的相互作用仅限于氧化层之上的掺杂多晶硅膜层，氧化层不会受到明显的损伤。
由于在同样碱性溶液中氧化硅(氧化层)比硅反应慢，即电池正面已 经开始制绒面，而电池背面先要和氧化层反应，然后再和硅片衬底的第一表面反应。通过掺杂多晶硅膜层与激光的相互作用，使氧化层在图案化之后得以保存不受明显损伤，可以利用该氧化层延长电池片正面制绒而背面不制绒的时间差，实现正面良好地制绒和背面图案化区域仅被去除氧化层，或此区域被去除氧化层同时第一表面仅被“微制绒”，宏观表现依然为平面，有较高的反射率。从而可以确保电池具有较高的开路电压和转化效率。
在其中一些实施方式中，所述激光为皮秒脉冲激光。退火后形成的掺杂多晶硅膜层对皮秒脉冲激光的吸收深度较浅，在进行图案化处理时可以确保皮秒脉冲激光和硅的相互作用仅限于氧化层之上的掺杂多晶硅膜层，更好地保护氧化层不受明显损伤。
在其中一些实施方式中，所述皮秒脉冲激光的波长为355nm或532nm。
在其中一些实施方式中，所述皮秒脉冲激光的脉冲宽度为1ps～100ps。
在其中一些实施方式中，所述氧化硅掩膜层通过气相沉积或者退火热氧化形成。
在其中一些实施方式中，所述退火处理的温度为800℃～950℃。
在其中一些实施方式中，所述退火处理的时间为30min～50min。在此退火处理温度、时间工艺条件下，可使掺杂非晶硅膜层充分晶化，充分转化为掺杂多晶硅膜层；同时使氧化硅掩膜层变得更加致密，在后续制绒工序中保护第一表面上的PN结区(氧化层、掺杂非晶硅膜层等)更不易被含碱的制绒药液所腐蚀。
在其中一些实施方式中，所述氧化层为氧化硅膜层，所述氧化层的厚度为0.5nm～2.5nm。
在其中一些实施方式中，所述氧化硅掩膜层的厚度为10nm～100nm。
在其中一些实施方式中，所述掺杂非晶硅膜层的厚度为30nm～300nm。
在其中一些实施方式中，在形成所述图案化区域之后，所述制备方法 还包括如下步骤：
利用制绒药液对所述硅片衬底进行浸泡处理，以去除所述图案化区域内的所述氧化层以及剩余的所述氧化硅掩膜层和所述掺杂多晶硅膜层，并使所述第二表面形成绒面。如此，可以实现对硅片衬底的第二表面进行制绒形成绒面，同时对第一表面上的图案化区域进行刻蚀处理，有效地去除图案化区域内的氧化层和掺杂多晶硅膜层，从而露出图案化区域对应的第一表面，或者露出的第一表面仅被“微制绒”,即处于制绒的“起绒”阶段，宏观表现依然为平面，具有较高的反射率，不会对钝化以及金属化复合产生较大影响。电池片背面的其他区域则由于有氧化硅掩膜层的保护而不会被制绒药液腐蚀破坏。
在其中一些实施方式中，所述制绒药液为含有制绒添加剂的碱溶液。
在其中一些实施方式中，所述浸泡处理的温度为30℃～80℃。
在其中一些实施方式中，所述浸泡处理的时间为300s～600s。在上述的制绒药液、浸泡处理温度、浸泡处理时间工艺条件下，既可以使硅片衬底的第二表面能够充分制绒形成绒面，又能够有效去除图案化区域内的氧化层和掺杂多晶硅膜层，露出相应的第一表面，并且不会使露出的第一表面产生绒面。
在其中一些实施方式中，在浸泡处理之后，所述制备方法还包括如下步骤：在所述硅片衬底的所述第一表面上和所述第二表面上分别沉积钝化膜层。通过设置钝化膜层可以起到钝化作用。
在其中一些实施方式中，所述钝化膜层为氧化铝膜层，所述钝化膜层的厚度为2nm～25nm。
在其中一些实施方式中，在沉积钝化膜层之后，所述制备方法还包括如下步骤：在所述第一表面上和所述第二表面上的所述钝化膜层上分别沉积减反射膜层。通过设置减反射膜层可以起到减少电池片反射率的作用。
在其中一些实施方式中，所述减反射膜层为氮化硅、氮氧化硅和氧化硅中的任意一种膜层或者多种的组合膜层，所述减反射膜层的厚度为50nm～150nm。
在其中一些实施方式中，在沉积减反射膜层之后，所述制备方法还包括如下步骤：
利用激光对所述第一表面上的所述图案化区域进行图案化开孔，去除开孔处的所述钝化膜层和所述减反射膜层以形成电极接触区；及
在所述电极接触区内和所述掺杂多晶硅膜层内注入电极浆料，分别形成第一电极和第二电极。
根据本申请的另一方面，提供了一种太阳电池，所述太阳电池通过本申请上述的制备方法制备得到。
根据本申请的另一方面，提供了一种光伏系统，所述光伏系统中包括本申请上述的太阳电池。
上述的制备方法，通过对第一表面上的掺杂非晶硅膜层进行退火处理，使掺杂非晶硅膜层中的非晶硅向多晶硅转化，形成掺杂多晶硅膜层；并采用激光对第一表面的预设区域进行图案化处理，破坏或去除预设区域的氧化硅掩膜层和掺杂多晶硅膜层，并保留全部或部分氧化层，形成图案化区域。在采用激光进行图案化处理时通过使激光和硅的相互作用仅限于氧化层之上的掺杂多晶硅膜层，保留全部或部分氧化层。该氧化层可对后续制绒碱液起到一定的阻挡作用，可以延长从制绒开始至图案化区域对应的第一表面开始形成绒面的时间差。在实现电池片正面良好制绒的同时，虽然背面激光图形化区域的薄氧化层会被腐蚀，但可以确保电池片背面图案化区域对应的部分不会被制绒，或者仅被“微制绒”，宏观上来看依然为平面，具有较高的反射率，从而保证了电池具有较高的开路电压和转化效率。
另外，采用皮秒脉冲激光对退火后的第一表面的预设区域进行图案化 处理，退火后形成的掺杂多晶硅膜层对该皮秒脉冲激光的吸收深度较浅，可确保激光和硅的相互作用仅限于氧化层之上的掺杂多晶硅膜层，在破坏或去除图案化区域内的氧化硅掩膜层和掺杂多晶硅膜层的同时，保留氧化层。
附图说明
为了更好地描述和说明本申请的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的申请、目前描述的实施例和/或示例以及目前理解的这些申请的最佳模式中的任何一者的范围的限制。
图1为本申请一实施例所制备的太阳电池的结构示意图；
图2为图1的仰视图；
图3为硅片衬底的结构示意图；
图4为硅片衬底退火后的结构示意图；
图5为对第一表面进行图案化处理后的结构示意图；
图6为对第一表面进行图案化处理后的仰视图；
图7为对硅片衬底进行制绒并去除氧化硅掩膜层后的结构示意图；
图8为对图案化区域开孔后的仰视图。
附图标记说明：
10、硅片衬底；11、第一表面；12、第二表面；21、氧化层；22、掺杂非晶硅膜层；23、氧化硅掩膜层；30、掺杂多晶硅膜层；40、图案化区域；50、钝化膜层；60、减反射膜层；70、电极接触区；80、第一电极；90、第二电极；100、背接触太阳电池。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面对本申请的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本申请。但是本申请能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似改进，因此本申请不受下面公开的具体实施例的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
在本申请中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
本申请一实施方式提供了一种背接触太阳电池100的制备方法，该背接触太阳电池100的结构如图1和图2所示。该制备方法包括如下步骤S100至步骤S800。
步骤S100：提供P型的硅片衬底10，该硅片衬底10具有第一表面11 和与第一表面11相对的第二表面12。硅片衬底10的结构如图3所示。
在其中一些实施例中，还对该硅片衬底10进行去损伤处理、抛光处理和清洗处理，以使硅片衬底10的表面清洁平整，利于进行后续的镀膜工序。其具体流程如下：使用60℃左右的含有KOH的溶液对硅片衬底10的表面进行去损伤处理；然后在75℃左右条件下使用含有KOH的溶液对硅片衬底10进行抛光处理，使抛光后的硅片衬底10表面反射率达到30％；再使用含有氢氟酸和盐酸的混合溶液对抛光后的硅片衬底10进行清洗；最后用去离子水清洗并烘干。
步骤S200：在硅片衬底10的第一表面11上依次沉积形成氧化层21、掺杂非晶硅膜层22和氧化硅掩膜层23。
其中，氧化层21为一层紧靠第一表面11设置的超薄的氧化硅膜层，该氧化层21的厚度为0.5nm～2.5nm。掺杂非晶硅膜层22为磷掺杂的非晶硅膜层。掺杂非晶硅膜层22的厚度为30nm～300nm，优选为100nm～150nm。氧化硅掩膜层23的厚度为10nm～100nm，优选为20nm～50nm。
在其中一些实施例中，氧化层21、掺杂非晶硅膜层22和氧化硅掩膜层23通过如下方法制备得到：先通过化学气相沉积(如LPCVD(Low Pressure Chemical Vapor Deposition，低压力化学气相沉积)、PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积)、热氧、链氧等方式在硅片衬底10的第一表面11上形成氧化层21；然后通过化学气相沉积(如LPCVD、PECVD)在氧化层21背离硅片衬底10的表面上沉积形成磷掺杂的掺杂非晶硅膜层22；再通过等离子体化学气相沉积(PECVD)或者退火热氧化在掺杂非晶硅膜层22背离氧化层21的表面上形成氧化硅掩膜层23。
氧化层21和掺杂非晶硅膜层22与硅片衬底10一起形成PN结。而氧化硅掩膜层23的主要作用是，在后续制绒工序中保护第一表面11上的PN 结区(氧化层21、掺杂非晶硅膜层22等)不被含碱的制绒药液所腐蚀。
步骤S300：对硅片衬底10进行退火处理，以使掺杂非晶硅膜层22转化为掺杂多晶硅膜层30。退火处理之后的硅片衬底10的结构如图4所示。
通过进行退火处理，可使掺杂非晶硅膜层22中的非晶硅(a-Si)向多晶硅(poly)转化，并使晶粒生长变大，形成掺杂多晶硅膜层30。
在其中一些实施例中，退火处理的温度为800℃～950℃，退火处理时间为30min～50min。在此退火处理工艺条件下，可使掺杂非晶硅膜层22充分晶化，充分转化为掺杂多晶硅膜层30；同时使氧化硅掩膜层23变得更加致密，在后续制绒工序中保护第一表面11上的PN结区(氧化层21、掺杂非晶硅膜层22等)更不易被含碱的制绒药液所腐蚀。
步骤S400：采用皮秒脉冲激光对第一表面11进行图案化处理，以破坏或去除预设区域的氧化硅掩膜层23和掺杂多晶硅膜层30，并保留氧化层21，从而形成图案化区域40。图案化处理后的结构如图5和图6所示。
在对第一表面11上的掺杂非晶硅膜层22进行退火处理之后，本申请采用皮秒脉冲激光对第一表面11进行图案化处理，以破坏或去除掉第一表面11上预设区域的氧化硅掩膜层23和掺杂多晶硅膜层30，从而形成图案化区域40。该图案化区域40用于制备与硅片衬底10直接相连的电极。图案化区域40的宽度为300μm～500μm。
在制备背接触太阳电池100时，在制绒时需要同时实现电池正面的制绒以及电池背面图案化区域40的刻蚀以暴露出P型的硅片衬底10的第一表面11。然而，目前通常是采用激光对氧化硅掩膜层23进行图案化处理，在图案化处理过程中激光与硅作用，容易对图案化区域40内的氧化层21造成损伤；进而使得在制绒过程中在对正面进行制绒的同时，背面图案化区域40也会被制绒，使图案化区域40对应的硅片衬底10的第一表面11也形成绒面结构。而该区域形成绒面结构，会大大地增加该区域第一表面 11的金属化复合，从而降低电池的开路电压以及转化效率。图案化区域40对应的第一表面11区域制绒后的理想形貌为平面结构。
为了解决上述问题，本申请通过在对掺杂非晶硅膜层22进行退火处理，形成掺杂多晶硅膜层30之后，采用皮秒脉冲激光对第一表面11进行图案化处理，以破坏或去除掉第一表面11上预设区域的氧化硅掩膜层23和掺杂多晶硅膜层30，形成图案化区域40。退火后形成的掺杂多晶硅膜层30对皮秒脉冲激光的吸收深度较浅，在采用皮秒脉冲激光进行图案化处理时激光和硅的相互作用仅限于氧化层21之上的掺杂多晶硅膜层30，氧化层21不会受到明显的损伤。
由于在同样碱性溶液(如制绒药液)中氧化硅(氧化层21)比硅反应慢，即电池正面已经开始制绒面，而电池背面先要和氧化层21反应，然后再和硅片衬底10的第一表面11反应。通过掺杂多晶硅膜层30与皮秒脉冲激光的相互作用，使氧化层21在图案化之后得以保存不受明显损伤，可以利用该氧化层21延长电池片正面制绒而背面不制绒的时间差，实现正面良好地制绒和背面图案化区域40仅被去除氧化层21，或此区域被去除氧化层21同时第一表面11仅被“微制绒”，刻蚀深度小于1μm，宏观表现依然为平面，有较高的反射率，反射率在25％以上。从而可以确保电池具有较高的开路电压和转化效率。
在本申请的一些实施例中，皮秒脉冲激光的波长为355nm或532nm，皮秒脉冲激光的脉冲宽度为1ps～100ps，优选为3ps～15ps。可以采用皮秒激光器利用上述皮秒脉冲激光，对第一表面11上部分区域的氧化硅掩膜层23进行去除，实现图案化开模。
通过上述的图案化处理方法，可以在后续的制绒工序后将图案化区域40对应的第一表面11区域形成抛光的形貌结构，相比于该第一表面11区域为绒面结构的情况，可以有效地减少该区域铝硅接触的金属化复合，提 升电池的开路电压2mV～5mV，从而提升背接触太阳电池100的电池效率约0.1％～0.2％。
步骤S500：先利用含氢氟酸或者含氢氟酸和浓硝酸的混合液仅对硅片衬底10的第二表面12进行处理，以去除第二表面12上可能存在的绕镀，然后利用制绒药液对硅片衬底10进行浸泡处理，以去除图案化区域40内的氧化层21以及图案化处理后剩余的氧化硅掩膜层23和掺杂多晶硅膜层30，并使第二表面12形成绒面。
在采用上述皮秒脉冲激光对第一表面11的预设区域进行图案化处理，形成图案化区域40之后；本申请先利用含氢氟酸或者含氢氟酸和浓硝酸的混合液仅对第二表面12进行处理，以去除第二表面12上可能存在的绕镀，再利用制绒药液对硅片衬底10进行处理，以去除图案化区域40内的氧化层21以及剩余的氧化硅掩膜层23和掺杂多晶硅膜层30，并使第二表面12形成绒面。
通过上述方法，可以实现对硅片衬底10的第二表面12(正面)进行制绒形成绒面，同时对第一表面11上的图案化区域40进行刻蚀处理，有效地去除图案化区域40内的氧化层21和掺杂多晶硅膜层30，从而露出图案化区域40对应的第一表面11，或者露出的第一表面11仅被“微制绒”,即处于制绒的“起绒”阶段，宏观表现依然为平面，具有较高的反射率(25％以上)，不会对钝化以及金属化复合产生较大影响。电池片背面的其他区域则由于有氧化硅掩膜层23的保护而不会被制绒药液腐蚀破坏。制绒完成之后，依次经水洗、碱清洗、水洗、酸清洗、水洗等常规湿法表面清洗工艺，最后烘干。其中，酸清洗时采用含有氢氟酸的酸溶液配方进行酸洗，即可将氧化硅掩膜层23去除。制绒并去除氧化硅掩膜层23后的结构如图7所示。
制绒是碱溶液和硅渐进反应的过程，在最初反应阶段，表面先“起绒”， 可理解为大量的金字塔塔尖，该阶段硅被刻蚀的深度较浅，在百纳米级别，宏观表现依然为平面结构，即反射率依然较高，一般在25％以上；随着反应的深入，由于碱溶液和硅反应的各向异性，碱溶液主要沿着<100>晶面腐蚀，最后在表面上形成若干个四个侧锥体，即“金字塔”结构，此时金字塔较小，但反射率已有明显下降；随着时间继续延长，金字塔不断变大，此时的金字塔高度约1μm～3μm，反射率一般在9％～11％。
在其中一些实施例中，制绒药液为含有制绒添加剂的碱溶液，制绒浸泡处理的温度为30℃～80℃，制绒浸泡处理的时间为300s～600s。在此工艺条件下，既可以使硅片衬底10的第二表面12能够充分制绒形成绒面，又能够有效去除图案化区域40内的氧化层21和掺杂多晶硅膜层30，露出相应的第一表面11，并且不会使露出的第一表面11产生绒面。
步骤S600：在硅片衬底10的第一表面11上和第二表面12上分别沉积钝化膜层50；然后在第一表面11上和第二表面11上的钝化膜层50上分别沉积减反射膜层60。通过设置钝化膜层50和减反射膜层60可以分别起到钝化作用和减少电池片反射率的作用。
在其中一个实施例中，钝化膜层50为通过ALD(原子层沉积)方法生长的氧化铝膜层，该钝化膜层50的厚度为2nm～25nm；减反射膜层60为氮化硅、氮氧化硅和氧化硅中的任意一种膜层或者多种的组合膜层，该减反射膜层60的厚度为50nm～150nm。
步骤S700：利用激光对硅片衬底10的第一表面11上的图案化区域40进行图案化开孔，以去除开孔处的钝化膜层50和减反射膜层60形成电极接触区70；然后在电极接触区70内和图案化区域40之外的掺杂多晶硅膜层30内注入电极浆料，分别形成第一电极80和第二电极90。对图案化区域40开孔后的结构如图8所示。
开孔时只需要对图案化区域40的副栅下方的局部接触部分开膜，N型 区域(图案化区域40以外的区域)无需开膜。因为第一电极80使用的浆料一般为非烧穿型浆料，即高温下不能烧穿钝化膜层50和减反射膜层60；而N型区域使用的浆料为烧穿型，可以烧穿钝化膜层50和减反射膜层60。
其中，第一电极80与硅片衬底10直接连接，第二电极90与第一表面11上的图案化区域40以外区域的掺杂多晶硅膜层30直接连接。在其中一些实施例中，第一电极80为铝栅线电极，第一电极80的宽度为50μm～200μm；第二电极90为银栅线电极，第二电极90的宽度为10μm～50μm。
具体地，利用激光对图案化区域40进行图案化开孔时，使开孔区域呈虚线或者点状分布，开孔宽度为30μm～50μm，即电极接触区70的宽度为30μm～50μm。可以采用丝网印刷的方式在电极接触区70内和图案化区域40之外的区域，形成包含导电成分的电极浆料层，分别作为第一电极80和第二电极90。
本申请的背接触太阳电池100的结构如图1和图2所示。该背接触太阳电池100可以作为电池单元应用于各种光伏系统中。相比于传统方法制备的背接触太阳电池100，本申请的背接触太阳电池100可以提升电池的开路电压2mV～5mV，提升背接触太阳电池100的电池效率约0.1％～0.2％。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请发明构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请的保护范围应以所附权利要求为准，说明书及附图可以用于解释权利要求 的内容。

Claims (20)

  1. 一种太阳电池的制备方法，包括如下步骤：
    提供硅片衬底，所述硅片衬底具有第一表面和与所述第一表面相对的第二表面；
    在所述硅片衬底的所述第一表面上依次层叠形成氧化层、掺杂非晶硅膜层和氧化硅掩膜层；
    对所述硅片衬底进行退火处理，以使所述掺杂非晶硅膜层转化为掺杂多晶硅膜层；及
    采用激光对所述第一表面进行图案化处理，以破坏或去除预设区域的所述氧化硅掩膜层和所述掺杂多晶硅膜层，并保留全部或部分所述氧化层，从而形成图案化区域。
  2. 根据权利要求1所述的太阳电池的制备方法，其特征在于，所述激光为皮秒脉冲激光。
  3. 根据权利要求2所述的太阳电池的制备方法，其特征在于，所述皮秒脉冲激光的波长为355nm或532nm，所述皮秒脉冲激光的脉冲宽度为1ps～100ps。
  4. 根据权利要求1至3中任一项所述的太阳电池的制备方法，其特征在于，所述氧化硅掩膜层通过气相沉积或者退火热氧化形成。
  5. 根据权利要求1至4中任一项所述的太阳电池的制备方法，其特征在于，所述退火处理的温度为800℃～950℃。
  6. 根据权利要求1至5中任一项所述的太阳电池的制备方法，其特征在于，所述退火处理的时间为30min～50min。
  7. 根据权利要求1至6中任一项所述的太阳电池的制备方法，其特征在于，所述氧化层为氧化硅膜层，所述氧化硅膜层的厚度为0.5nm～2.5nm。
  8. 根据权利要求1至7中任一项所述的太阳电池的制备方法，其特征在于，所述氧化硅掩膜层的厚度为10nm～100nm。
  9. 根据权利要求1至8中任一项所述的太阳电池的制备方法，其特征在于，所述掺杂非晶硅膜层的厚度为30nm～300nm。
  10. 根据权利要求1至9中任一项所述的太阳电池的制备方法，其特征在于，在形成所述图案化区域之后，所述制备方法还包括如下步骤：
    利用制绒药液对所述硅片衬底进行浸泡处理，以去除所述图案化区域内的所述氧化层以及剩余的所述氧化硅掩膜层和所述掺杂多晶硅膜层，并使所述第二表面形成绒面。
  11. 根据权利要求10所述的太阳电池的制备方法，其特征在于，所述制绒药液为含有制绒添加剂的碱溶液。
  12. 根据权利要求10或11所述的太阳电池的制备方法，其特征在于，所述浸泡处理的温度为30℃～80℃。
  13. 根据权利要求10至12中任一项所述的太阳电池的制备方法，其特征在于，所述浸泡处理的时间为300s～600s。
  14. 根据权利要求10至13中任一项所述的太阳电池的制备方法，其特征在于，在浸泡处理之后，所述制备方法还包括如下步骤：
    在所述硅片衬底的所述第一表面上和所述第二表面上分别沉积钝化膜层。
  15. 根据权利要求14所述的太阳电池的制备方法，其特征在于，所述钝化膜层为氧化铝膜层，所述钝化膜层的厚度为2nm～25nm。
  16. 根据权利要求14或15所述的太阳电池的制备方法，其特征在于，在沉积钝化膜层之后，所述制备方法还包括如下步骤：
    在所述第一表面上和所述第二表面上的所述钝化膜层上分别沉积减反射膜层。
  17. 根据权利要求16所述的太阳电池的制备方法，其特征在于，所述减反射膜层为氮化硅、氮氧化硅和氧化硅中的任意一种膜层或者多种的组合膜层，所述减反射膜层的厚度为50nm～150nm。
  18. 根据权利要求16或17所述的太阳电池的制备方法，其特征在于，在沉积减反射膜层之后，所述制备方法还包括如下步骤：
    利用激光对所述第一表面上的所述图案化区域进行图案化开孔，去除开孔处的所述钝化膜层和所述减反射膜层以形成电极接触区；及
    在所述电极接触区内和所述掺杂多晶硅膜层内注入电极浆料，分别形成第一电极和第二电极。
  19. 一种太阳电池，其特征在于，所述太阳电池通过权利要求1至18任一项所述的制备方法制备得到。
  20. 一种光伏系统，其特征在于，所述光伏系统中包括权利要求19所述的太阳电池。
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