WO2023216628A1 - 异质结太阳电池、其制备方法及发电装置 - Google Patents

异质结太阳电池、其制备方法及发电装置 Download PDF

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WO2023216628A1
WO2023216628A1 PCT/CN2022/143685 CN2022143685W WO2023216628A1 WO 2023216628 A1 WO2023216628 A1 WO 2023216628A1 CN 2022143685 W CN2022143685 W CN 2022143685W WO 2023216628 A1 WO2023216628 A1 WO 2023216628A1
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layer
solar cell
sccm
silicon
wafer substrate
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French (fr)
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WO2023216628A9 (zh
WO2023216628A8 (zh
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孟夏杰
刑国强
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Tongwei Solar Chengdu Co Ltd
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Tongwei Solar Chengdu Co Ltd
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Priority to US18/834,069 priority Critical patent/US20250126923A1/en
Priority to AU2022457985A priority patent/AU2022457985B2/en
Priority to EP22941560.9A priority patent/EP4525059A4/en
Publication of WO2023216628A1 publication Critical patent/WO2023216628A1/zh
Publication of WO2023216628A9 publication Critical patent/WO2023216628A9/zh
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B31/00—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
    • C30B31/06—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor by contacting with diffusion material in the gaseous state
    • C30B31/18—Controlling or regulating
    • C30B31/185—Pattern diffusion, e.g. by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/129—Passivating
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B31/00—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
    • C30B31/06—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor by contacting with diffusion material in the gaseous state
    • C30B31/18—Controlling or regulating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • H10F77/703—Surface textures, e.g. pyramid structures of the semiconductor bodies, e.g. textured active layers

Definitions

  • the present invention relates to the field of batteries, and in particular to a solar cell and its preparation method and application.
  • the battery Due to the design of the front surface of the back-contact solar cell without grid electrodes, it does not block the light and can maximize the use of incident light. Combined with the pyramid suede structure and the light trapping structure composed of the anti-reflection film used on the front of the cell, the battery has a high The optical loss is reduced, effectively improving the short-circuit current density of the battery.
  • interdigitated back-contact solar cells due to the particularity of the device structure (the metal electrode is located on the back of the cell, and the positive and negative electrodes are arranged in a cross-finger shape), do not need to consider the contact resistance on the front, and can further optimize the front surface light trapping. and passivation performance; the backside can optimize the metal gate line electrode, thereby reducing the series resistance and thus improving the fill factor.
  • the traditional back contact solar cell structure has a tunneling oxygen passivation contact (TOPCon) structure, which includes an ultra-thin silicon oxide layer and a heavily doped polysilicon layer to passivate the back surface of the cell.
  • the passivation mechanism of this structure is: ultra-thin silicon oxide is in direct contact with the silicon substrate, neutralizing the dangling bonds on the silicon surface, and performing excellent chemical passivation; the heavily doped polysilicon layer has a Fermi level with the silicon substrate. The difference causes energy band bending on the surface of the silicon substrate, which can more effectively block the passage of minority carriers without affecting the transmission of majority carriers, achieving selective collection of carriers.
  • Carriers can directly and efficiently conduct one-dimensional longitudinal transmission through the oxide layer, minimizing the current transmission path, avoiding the recombination of carriers during the two-dimensional transmission process, reducing the series resistance of the battery, and making the battery have higher Fill factor, thus achieving higher photoelectric conversion efficiency.
  • the traditional preparation of the doped layer in the above TOPCon structure uses low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD) deposition methods, and due to the thick thickness of the doped layer, using the above deposition method will cause There is a certain thickness of doped layer material on the front side of the battery. The formed surrounding plating material will greatly reduce the conversion efficiency of the battery and cause a certain degree of leakage.
  • LPCVD low pressure chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the phosphorus diffusion in the LPCVD route will also affect the front side of the battery, so in order to remove these wraparound platings, a wet process is usually added.
  • increasing the wet process will not only increase equipment and labor costs, but may also affect the battery conversion efficiency because the wet process affects the morphology of the battery front itself.
  • the present disclosure provides a method for preparing a solar cell, including the following steps:
  • S10 Provide a silicon wafer substrate, the silicon wafer substrate having a first surface and a second surface opposite to the first surface;
  • S20 Form a silicon-containing film on the first surface of the silicon wafer substrate.
  • the silicon-containing film includes a silicon oxide layer, a doped layer and a mask sequentially formed on the first surface of the silicon wafer substrate.
  • layer, wherein the method of forming the doped layer with a thickness of 30 nm to 300 nm includes: forming the doped layer with a thickness of 10 nm to 30 nm in an atmosphere with a flow rate of a doping gas source of 100 sccm to 1000 sccm and a flow rate of silane of 1000 sccm to 4000 sccm.
  • Doping layer forming the remaining thickness of the doping layer in an atmosphere where the flow rate of the doping gas source is 1500 sccm ⁇ 3000 sccm and the flow rate of silane is 1000 sccm ⁇ 4000 sccm;
  • S40 Perform texturing on the silicon wafer substrate having the silicon-containing film and the patterned area.
  • the temperature at which the doped layer is formed in step S20 is 200°C to 700°C.
  • the doping gas source is selected from at least one of phosphane, diborane, trimethylborane, and boron trifluoride.
  • an annealing step is further included after step S20 and before step S30.
  • the temperature of the annealing treatment is 800°C to 950°C, and the time of the annealing treatment is 30 min to 50 min.
  • the silicon oxide layer is formed on the first surface by a plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, or thermal oxygen method.
  • the silicon oxide layer has a thickness of 0.5nm ⁇ 2.5nm.
  • the mask layer is formed on the doped layer by a method of thermal oxygen, plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition.
  • the thickness of the mask layer is 5 nm to 100 nm.
  • the method further includes: sequentially forming a first passivation film on the first surface of the silicon wafer substrate with a textured surface. layer and the first antireflection film layer.
  • the method further includes: sequentially forming a second passivation film on the second surface of the silicon wafer substrate with a textured surface. layer and a second anti-reflective coating layer.
  • step S60 is also included: using a laser to pattern holes in the patterned area on the first surface, and preparing a first electrode and a first electrode by screen printing. Two electrodes.
  • a solar cell is also provided, which is prepared by a preparation method including the following steps:
  • S10 Provide a silicon wafer substrate, the silicon wafer substrate having a first surface and a second surface opposite to the first surface;
  • S20 Form a silicon-containing film on the first surface of the silicon wafer substrate.
  • the silicon-containing film includes a silicon oxide layer, a doped layer and a mask sequentially formed on the first surface of the silicon wafer substrate.
  • layer, wherein the method of forming the doped layer with a thickness of 30 nm to 300 nm includes: forming the doped layer with a thickness of 10 nm to 30 nm in an atmosphere with a flow rate of a doping gas source of 100 sccm to 1000 sccm and a flow rate of silane of 1000 sccm to 4000 sccm.
  • Doping layer forming the remaining thickness of the doping layer in an atmosphere where the flow rate of the doping gas source is 1500 sccm ⁇ 3000 sccm and the flow rate of silane is 1000 sccm ⁇ 4000 sccm;
  • S40 Perform texturing on the silicon wafer substrate having the silicon-containing film and the patterned area.
  • the temperature at which the doped layer is formed in step S20 is 200°C to 700°C.
  • the doping gas source is selected from at least one of phosphane, diborane, trimethylborane, and boron trifluoride.
  • an annealing step is further included after step S20 and before step S30.
  • the temperature of the annealing treatment is 800°C to 950°C, and the time of the annealing treatment is 30 min to 50 min.
  • the silicon oxide layer is formed on the first surface by a plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, or thermal oxygen method.
  • the silicon oxide layer has a thickness of 0.5nm ⁇ 2.5nm.
  • the mask layer is formed on the doped layer by a method of thermal oxygen, plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition.
  • the thickness of the mask layer is 5 nm to 100 nm.
  • the method further includes: sequentially forming a first passivation film on the first surface of the silicon wafer substrate with a textured surface. layer and the first antireflection film layer.
  • the method further includes: sequentially forming a second passivation film on the second surface of the silicon wafer substrate with a textured surface. layer and a second anti-reflective coating layer.
  • step S60 is also included: using a laser to pattern holes in the patterned area on the first surface, and preparing a first electrode and a first electrode by screen printing. Two electrodes.
  • a photovoltaic system which includes a solar cell component and auxiliary equipment.
  • the solar cell component includes the solar cell as described in any of the above embodiments.
  • Figure 1 shows the structure of the solar cell of the present invention
  • Figure 2 is a bottom view of the patterned area after patterning the silicon-containing film
  • Figure 3 is a bottom view after opening holes in the patterned area
  • Figure 4 is a bottom view of the solar cell of the present invention.
  • the invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that a thorough understanding of the disclosure of the present invention will be provided. Of course, they are merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numbers and/or letters in different examples. This repetition is for purposes of simplicity and clarity and does not by itself indicate a relationship between the various embodiments and/or arrangements discussed.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include at least one of these features.
  • plural means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.
  • severeal means at least one, such as one, two, etc., unless otherwise expressly and specifically limited.
  • the present invention provides a method for preparing a solar cell 10 as shown in Figure 1, which includes the following steps.
  • Step S10 Provide a silicon wafer substrate 110.
  • the silicon wafer substrate 110 has a first surface and a second surface opposite to the first surface.
  • first surface is the backlight surface of the battery, also called the back surface
  • second surface is the light-receiving surface of the battery, also called the front surface
  • step S10 the silicon wafer substrate 110 is also subjected to damage removal processing, polishing processing and cleaning processing.
  • the damage removal treatment includes: using a strong monobasic base containing a substance with a concentration of 0.6 mol/L to 0.8 mol/L to perform treatment at 50°C to 70°C.
  • the temperature of the damage removal treatment may be, but is not limited to, 50°C, 55°C, 60°C, 65°C or 70°C.
  • the solution for the damage removal treatment is a mixed solution with a mass percentage of 46% sodium hydroxide solution and water, with a volume ratio of 4:96 to 6:94.
  • the polishing process includes: using a monobasic strong alkali solution with a concentration of 0.6 mol/L to 0.8 mol/L to process at 65°C to 85°C, so that the reflectivity after polishing is 20% to 40%.
  • the above-mentioned reflectivity after polishing may be, but is not limited to, 20%, 25%, 30%, 35% or 40%.
  • the reflectance after polishing of the silicon wafer substrate is 30%.
  • the cleaning process includes: sequentially using a mixed solution of hydrofluoric acid and hydrochloric acid, deionized water, and drying.
  • Step S20 Form a silicon-containing film 123 on the first surface of the silicon wafer substrate 110.
  • the silicon-containing film includes a silicon oxide layer 121, a doped layer 122 and a mask sequentially formed on the first surface of the silicon wafer substrate 110. layer.
  • a silicon oxide layer 121 with a thickness of 0.5 nm to 2.5 nm is formed on the silicon wafer substrate using plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition or thermal oxygen.
  • the thickness of the silicon oxide layer 121 may be, but is not limited to, 0.5 nm, 1 nm, 2 nm or 2.5 nm.
  • the silicon oxide layer 121 is preferably formed by a plasma enhanced chemical vapor deposition method
  • the step of forming the silicon oxide layer 121 in step S10 includes: passing in silane gas at a flow rate of 1000 sccm to 5000 sccm and passing in hydrogen gas at a flow rate of 6000 sccm to 15000 sccm.
  • 350°C to 600°C Glow discharge is performed at a temperature, a power supply of 9KW to 12KW, and a plasma pulse switching ratio of 1:100ms to form a silicon oxide layer 121 on the formation substrate.
  • the silane gas flow rate is 2500 sccm ⁇ 3000 sccm
  • the hydrogen gas flow rate is 8000 sccm ⁇ 10000 sccm.
  • the temperature at which the silicon oxide layer 121 is prepared is preferably 400°C to 450°C.
  • the temperature at which the silicon oxide layer 121 is prepared may be, but is not limited to, 410°C, 420°C, 430°C, 440°C or 450°C.
  • the power supply power is 9KW ⁇ 10KW
  • a doping layer 122 with a thickness of 30 nm to 300 nm is formed using a physical vapor deposition method in an atmosphere containing a doping gas source and silane,
  • a doping layer with a thickness of 10 nm to 30 nm is formed in an atmosphere containing a doping gas source with a flow rate of 100 sccm to 1000 sccm and a silane flow rate of 1000 sccm to 4000 sccm.
  • the remaining doped layer 122 is formed in an atmosphere with a flow rate of 1000 sccm to 4000 sccm.
  • a doping layer 122 with a thickness of 10 nm to 30 nm is formed in an atmosphere containing a doping gas source with a flow rate of 200 sccm to 800 sccm and a silane flow rate of 2000 sccm to 3600 sccm.
  • the flow rate of the doping gas source may be, but is not limited to, 200 sccm, 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm or 800 sccm
  • the flow rate of silane may be, but is not limited to, Is it 2000sccm, 2200sccm, 2400sccm, 2600sccm, 2700sccm, 2800sccm, 2900sccm, 3000sccm, 3200sccm, 3400sccm or 3600sccm.
  • the remaining doping layer 122 is formed in an atmosphere containing a doping gas source with a flow rate of 2000 sccm to 3000 sccm and a silane flow rate of 2000 sccm to 3600 sccm.
  • the flow rate of the doping gas source may be, but is not limited to, 2000 sccm, 2200 sccm, 2400 sccm, 2600 sccm, 2800 sccm or 3000 sccm
  • the flow rate of silane may be, but is not limited to, 2000 sccm, 2200 sccm, 2400 sccm , 2600sccm, 2700sccm, 2800sccm, 2900sccm, 3000sccm, 3200sccm, 3400sccm or 3600sccm.
  • the pressure inside the tube during the preparation process of forming the doped layer 122 is 1 Pa to 150 Pa. Furthermore, the time for preparing the doped layer 122 is 5 min to 20 min.
  • the temperature for forming the doped layer 122 is 200°C to 700°C.
  • the temperature for forming the doped layer 122 is preferably 300°C to 600°C, and further preferably 400°C to 500°C.
  • the temperature at which the doped layer 122 is formed may be, but is not limited to, 300°C, 350°C, 400°C, 450°C, 500°C, 550°C or 600°C.
  • the doping gas source is selected from at least one of phosphane, diborane, trimethylborane and boron trifluoride.
  • the doping gas source in order to prepare the p-type doped layer 122, can be phosphane, and in order to prepare the n-type doped layer 122, the doping gas source can be diborane, trimethylborane and trifluoride. At least one kind of boron.
  • the above-mentioned doping concentration of the doped layer 122 can be achieved by matching the flow rate of the doping gas source, the silane flow rate, and the deposition temperature in the physical vapor deposition method.
  • the thickness of the doped layer 122 is 100 nm to 150 nm. It is understandable that the thickness of the doped layer 122 may be, but is not limited to, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm or 150 nm.
  • a mask layer with a thickness of 5 nm to 100 nm is formed on the doped layer 122 by using thermal oxygen, plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition.
  • the thickness of the mask layer is 5 nm to 100 nm.
  • the material of the mask layer may be, but is not limited to, silicon oxide and silicon nitride.
  • the above-mentioned mask layer material is silicon oxide material.
  • the thermal oxygen growth method is used to in-situ grow a silicon oxide layer as a mask layer on the surface of the doped layer 122 through high-temperature oxygen.
  • the temperature is 600°C to 950°C and the time is 15 minutes. ⁇ 45min, oxygen flow rate is 8000sccm ⁇ 13000sccm.
  • an annealing process is performed. It can be understood that the above-mentioned annealing process includes the formed silicon oxide layer 121 and the doped layer 122, and the mask layer may also be annealed.
  • the annealing temperature in step S30 is 800°C to 950°C, and the annealing time is 30min to 50min.
  • the annealing treatment can not only transform the aforementioned physically vapor deposited amorphous silicon into polycrystalline silicon and make the grains grow larger, but also make the mask layer material denser and greatly improve its alkali resistance.
  • the physical vapor deposition method is used to prepare the doping layer 122 by controlling the flow rate of the doping source gas. This not only enables the preparation of the doping layer 122, but also further effectively reduces the amount of lining material.
  • the phenomenon of bypass plating that occurs on the bottom front surface After the silicon-containing film 123 is prepared and the patterned area is formed through laser processing, no additional process is required to remove the excess doped layer 122 material generated by the surround plating, effectively reducing the process of preparing the battery. Such as wet process, it will not affect the battery conversion efficiency and the front appearance of the battery.
  • Step S30 Use a laser to pattern the silicon-containing film 123 on the first surface to form a patterned region 111 on the first surface of the silicon substrate 110.
  • a picosecond laser is used to remove the silicon-containing film 123 in part of the first surface of the silicon wafer substrate 110 using ultraviolet 355nm or 532nm nanolaser to form a patterned area 111 with a width of 300 ⁇ m to 500 ⁇ m, and remove or Part of the silicon-containing film in the patterned area 111 is destroyed, making it more susceptible to corrosion by the alkali solution.
  • FIG. 2 is a bottom view of the patterned area 111 after the silicon-containing film 123 is patterned.
  • Step S40 Perform a texturing process on the silicon wafer substrate 110 having the silicon-containing film 123 and the patterned area 111.
  • the step of treating the mask layer material surrounding the second surface of the substrate 110 with a hydrofluoric acid solution having a concentration of 4 mol/L to 6 mol/L is also included.
  • the first surface of the substrate 110 away from the hydrofluoric acid solution, place it horizontally, and cover the first surface of the substrate 110 with deionized water to avoid contact with the hydrofluoric acid solution and damage to the silicon oxide mask layer on the first surface.
  • the second surface of the substrate 110 is brought into contact with the hydrofluoric acid solution to remove the silicon oxide mask layer produced by the circumferential plating, and the cleaning time is 60 to 240 seconds.
  • hydrofluoric acid solution uses a mass fraction of 49% hydrofluoric acid and water to be mixed with a volume ratio of (10-30): (70-90).
  • a mass fraction of 49% hydrogen is used.
  • Hydrofluoric acid solution is prepared by mixing hydrofluoric acid and water in a ratio of 20:80.
  • the pre-processed silicon wafer substrate 110 is subjected to texturing treatment: the silicon wafer substrate 110 with the silicon-containing film 123 and the patterned area 111 is placed in a substance containing concentration of 0.15 mol/L to 0.35
  • the texturing process is carried out in a texturing solution of mol/L monovalent strong alkali for a texturing time of 400s to 600s to prepare a silicon wafer substrate 110 with a textured surface.
  • the strong monobasic base is selected from at least one of potassium hydroxide and sodium hydroxide.
  • texturing is to form a pyramid-shaped texture surface on the second surface of the substrate 110, that is, the light-receiving surface.
  • the above-mentioned texturing liquid may also include additives, wherein the additives may be but are not limited to indolepropionic acid (IPA).
  • IPA indolepropionic acid
  • Additives usually do not directly participate in chemical reactions, but have the functions of reducing the surface tension of the solution, improving the uniformity of the reaction, adjusting the corrosion rate of the strong alkali to significantly reduce the reaction rate, and enhancing the anisotropy of corrosion.
  • the silicon wafer substrate 110 having the textured surface may also be subjected to steps that may include but are not limited to water washing, alkali washing, water washing, pickling, water washing and drying.
  • alkali cleaning uses a sodium hydroxide aqueous solution with an amount of 0.1% to 0.2% of the substance for cleaning.
  • pickling uses an acid solution containing hydrofluoric acid to remove the outermost silicon oxide mask layer on the non-patterned area outside the patterned area 111 on the first surface of the substrate 110 .
  • step S50 is also included: sequentially forming a first passivation on the first surface of the silicon wafer substrate 110 with a textured surface and the composite film layer 120 film layer 130 and the first anti-reflection film layer 150 .
  • first passivation film layer 130 and the first anti-reflection film layer 150 are sequentially formed on the first surface of the silicon wafer substrate 110 with texture, the silicon oxide layer 121 and the doped layer 122 .
  • a second passivation film and a second anti-reflection film layer 160 are sequentially formed on the second surface of the textured silicon wafer substrate 110 .
  • first passivation film layer 130 and the second passivation film layer 140 can be, but is not limited to, atomic layer deposition. Further, the materials of the first passivation film layer 130 and the second passivation film The layer 140 material may be, but is not limited to, aluminum oxide.
  • the thickness of the first passivation film layer 130 is 2 nm to 25 nm
  • the thickness of the second passivation film layer 140 is 2 nm to 25 nm.
  • the formation method of the first anti-reflection film layer 150 and the second anti-reflection film layer 160 can be, but is not limited to, plasma enhanced chemical vapor deposition.
  • the materials of the first anti-reflection film layer 150 and the second anti-reflection film layer The material of the film layer 160 may be, but is not limited to, at least one of silicon oxide, silicon oxynitride, and silicon nitride.
  • the thickness of the first anti-reflection film layer 150 is 50 nm to 150 nm
  • the thickness of the second anti-reflection film layer 160 is 60 nm to 150 nm.
  • the material of the first anti-reflection film layer 150 and the material of the second anti-reflection film layer 160 contain silicon oxide, silicon oxynitride and silicon nitride materials, and are three layers of materials stacked.
  • step S60 is also included: using a laser to pattern holes in the patterned area on the first surface, and preparing the first electrode 170 and the second electrode 180 through screen printing.
  • Electrode slurry is injected into the area to prepare the second electrode 180 .
  • a laser is used to pattern the patterned area 111 on the first surface with a hole width of 30 ⁇ m to 50 ⁇ m, and the passivation film layer and the anti-reflection film layer at the hole are removed to form the first electrode 170 contact area.
  • the opening areas are distributed in a dotted line or dot shape, as shown in FIG. 3 , a bottom view of the patterned area 111 after opening holes.
  • the above-mentioned method of forming the first electrode 170 and the second electrode 180 may be, but is not limited to, screen printing.
  • the first electrode 170 in contact with the doped layer 122 does not need to be drilled.
  • the first electrode preferably uses a burn-through electrode slurry.
  • the first passivation film layer 130, the first anti-reflection film layer 150 and the doped layer can be burned through at high temperature.
  • the hybrid layer 122 forms a contact, while the substrate 110 is only in partial contact. Non-burn-through electrode slurry is used, so the non-burn-through slurry forms contact with the substrate 110 at the laser opening.
  • first electrode 170 and the second electrode 180 are metal electrodes, and the materials of the first electrode 170 and the second electrode 180 are each independently selected from one of, but not limited to, aluminum and silver.
  • FIG. 4 is a bottom view of the solar cell 10 .
  • the solar cell 10 prepared through the above preparation process is preferably a back contact cell.
  • the present invention further provides a photovoltaic system, including a solar cell module and auxiliary equipment.
  • the solar cell module includes the above-mentioned solar cell 10 .
  • This embodiment provides a p-type back contact solar cell, the preparation steps of which are as follows:
  • S10 De-damage treatment, polishing and cleaning process of p-type silicon substrate: Use p-type single crystal silicon as the battery substrate, use 60°C solution containing potassium hydroxide for de-damage treatment, use potassium hydroxide-containing solution The solution is polished at a temperature of 75°C. The reflectivity after polishing is 30%. A mixed solution of hydrofluoric acid and hydrochloric acid is used for cleaning, and deionized water is used for cleaning and drying.
  • S20 Forming a silicon-containing film on a p-type silicon wafer substrate: in an atmosphere of silane gas with a flow rate of 2600 sccm and hydrogen gas with a flow rate of 9000 sccm, the power supply power is 9KW, the plasma pulse switching ratio is 1:100ms and 400°C At a temperature of 400°C, a silicon oxide layer with a thickness of 2nm is formed on the p-type silicon substrate; at a temperature of 400°C, an n-type layer with a thickness of 30nm is first prepared in an atmosphere of 500sccm phosphene and 2800sccm silane.
  • n-type doping layer with a thickness of 130nm in a phosphane atmosphere of 2500 sccm and a silane atmosphere of 2800 sccm.
  • the doping concentration of the n-type doping layer is 1E20cm -3 ⁇ 1E21cm -3 ; and then doped in the n-type
  • the thermal oxygen growth method is used on the doped layer, and high-temperature oxygen is passed to in-situ grow silicon oxide with a thickness of 30nm on the surface of the doped layer as a mask layer; the above-mentioned silicon-containing film is annealed at a temperature of 920°C for 45 minutes.
  • Patterning processing Use laser to pattern the silicon-containing film on the first surface to form a patterned area on the first surface of the silicon wafer substrate.
  • S50 Coating the front and back of the battery respectively.
  • PECVD plasma enhanced chemical vapor deposition
  • a 100nm composite film of silicon oxide, silicon oxynitride and silicon nitride is used as the second anti-reflective film.
  • PECVD is used to coat a 100nm composite film of silicon oxide, silicon oxynitride and silicon nitride on the back as the first anti-reflective film. film layer.
  • S60 Use laser to pattern the patterned area on the back and open the exposed p-type substrate area.
  • the opening area is distributed in a dotted line or dot shape.
  • the opening width is 40 ⁇ m.
  • the opening area is used as the p-type substrate area.
  • electrode contact area Screen printing is used to form an electrode paste layer containing conductive components on the electrode contact area of the p-type substrate area and the electrode contact area of the n-type doped layer on the back of the battery.
  • the aluminum grid electrode serves as the positive electrode of the battery, and the silver grid line The electrode serves as the negative pole of the battery.
  • This comparative example provides a p-type back contact solar cell, the preparation steps of which are as follows:
  • S10 De-damage treatment, polishing and cleaning process of p-type silicon substrate: Use p-type single crystal silicon as the battery substrate, use 60°C solution containing potassium hydroxide for de-damage treatment, use potassium hydroxide-containing solution The solution is polished at a temperature of 75°C. The reflectivity after polishing is 30%. A mixed solution of hydrofluoric acid and hydrochloric acid is used for cleaning, and deionized water is used for cleaning and drying.
  • S20 Forming a silicon-containing film on a p-type silicon wafer substrate: in an atmosphere of silane gas with a flow rate of 2600 sccm and hydrogen gas with a flow rate of 9000 sccm, the power supply power is 9KW, the plasma pulse switching ratio is 1:100ms and 400°C
  • a silicon oxide layer with a thickness of 2nm is formed on the p-type silicon substrate; at a temperature of 400°C, an n-type doped layer with a thickness of 160nm is prepared on the silicon oxide layer in an atmosphere of 2500sccm phosphene and 2800sccm silane.
  • Patterning processing Use laser to pattern the silicon-containing film on the first surface to form a patterned area on the first surface of the silicon wafer substrate.
  • S50 Coating the front and back of the battery respectively.
  • PECVD plasma enhanced chemical vapor deposition
  • the composite film layer of silicon oxide, silicon oxynitride and silicon nitride is used as the second anti-reflective film layer.
  • PECVD is used to coat the back surface with a 100nm composite film layer of silicon oxide, silicon oxynitride and silicon nitride as the first anti-reflective film. layer.
  • S60 Use laser to pattern the patterned area on the back and open the exposed p-type substrate area.
  • the opening area is distributed in a dotted line or dot shape.
  • the opening width is 40 ⁇ m.
  • the opening area is used as the p-type substrate area.
  • electrode contact area Screen printing is used to form an electrode paste layer containing conductive components on the electrode contact area of the p-type substrate area and the electrode contact area of the n-type doped layer on the back of the battery.
  • the aluminum grid electrode serves as the positive electrode of the battery, and the silver grid line The electrode serves as the negative pole of the battery.
  • This comparative example provides a p-type back contact solar cell, the preparation steps of which are as follows:
  • S10 De-damage treatment, polishing and cleaning process of p-type silicon substrate: Use p-type single crystal silicon as the battery substrate, use 60°C solution containing potassium hydroxide for de-damage treatment, use potassium hydroxide-containing solution The solution is polished at a temperature of 75°C. The reflectivity after polishing is 30%. A mixed solution of hydrofluoric acid and hydrochloric acid is used for cleaning, and deionized water is used for cleaning and drying.
  • S20 Forming a silicon-containing film on a p-type silicon wafer substrate: in an atmosphere of silane gas with a flow rate of 2600 sccm and hydrogen gas with a flow rate of 9000 sccm, with a power supply of 9KW, a plasma pulse switching ratio of 1 to 100ms, and a temperature of 400°C.
  • a silicon oxide layer with a thickness of 2nm is formed on the p-type silicon substrate;
  • an n-type layer with a thickness of 30nm is first prepared in a phosphene atmosphere of 2000sccm and a silane atmosphere of 2800sccm.
  • n-type doping layer with a thickness of 130nm in a phosphane atmosphere with a flow rate of 2500 sccm and a silane atmosphere of 2800 sccm; then the thermal oxygen growth method is used on the n-type doping layer, and high-temperature oxygen is passed through the doping layer Silicon oxide with a thickness of 30 nm was grown in situ on the surface as a mask layer; the silicon-containing film was annealed at a temperature of 920°C for 45 minutes.
  • Patterning processing Use laser to pattern the silicon-containing film on the first surface to form a patterned area on the first surface of the silicon wafer substrate.
  • S50 Coating the front and back of the battery respectively.
  • PECVD plasma enhanced chemical vapor deposition
  • a 100nm composite film of silicon oxide, silicon oxynitride and silicon nitride is used as the second anti-reflective film.
  • PECVD is used to coat a 100nm composite film of silicon oxide, silicon oxynitride and silicon nitride on the back as the first anti-reflective film. film layer.
  • S60 Use laser to pattern the patterned area on the back and open the exposed p-type substrate area.
  • the opening area is distributed in a dotted line or dot shape.
  • the opening width is 40 ⁇ m.
  • the opening area is used as the p-type substrate area.
  • electrode contact area Screen printing is used to form an electrode paste layer containing conductive components on the electrode contact area of the p-type substrate area and the electrode contact area of the n-type doped layer on the back of the battery.
  • the aluminum grid electrode serves as the positive electrode of the battery, and the silver grid line The electrode serves as the negative pole of the battery.
  • the performance of the p-type back contact solar cell provided in Embodiment 1 of the present invention is that the cell conversion efficiency is 24.8%, the open circuit voltage is 720mv, the current is 18A, and the fill factor FF is above 83%.
  • the p-type back contact solar cell was finally prepared by using only one flow condition to prepare the doping layer. The cell conversion efficiency was lower than 24.2%.
  • a high flow rate of doping was introduced when preparing the doping layer.
  • the p-type back contact solar cell prepared with source gas flow has an opening voltage lower than 715mV, a short-circuit current lower than 18A, a fill factor FF lower than 83%, and a conversion efficiency lower than 24%.
  • the conversion efficiency of traditional emitter and back-passivated PERC cells is usually 21 to 22%.

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Abstract

一种太阳电池及其制备方法和应用，制备方法包括以下步骤：提供具有第一表面以及与第一表面相对的第二表面的硅片衬底（110）；在硅片衬底（110）的第一表面上形成包括掺杂层（122）的含硅薄膜（123），掺杂层（122）的形成方法包括：在掺杂气源的流量为100～1000sccm以及硅烷的流量为1000～4000sccm气氛中形成部分掺杂层，在掺杂气源的流量为1500～3000sccm以及不改变硅烷的流量气氛中形成余下掺杂层；形成图案化区域（111）；进行制绒处理。通过对形成掺杂层的气体的流量的控制不仅实现有效掺杂，还减少绕镀现象发生，不需要额外的工艺去除绕镀产生的多余的多晶硅或氧化硅，不影响电池转换效率以及电池外观。

Description

异质结太阳电池、其制备方法及发电装置
本申请要求于2022年5月7日提交中国专利局、申请号为2022104894953、发明名称为“太阳电池及其制备方法和应用”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电池领域，特别是涉及一种太阳电池及其制备方法和以及应用。
背景技术
背接触太阳电池由于其前表面无栅线电极的设计，对光没有任何遮挡，能够最大限度利用入射光，结合电池正面采用的金字塔绒面结构和减反射膜组成的陷光结构，使得电池的光学损失减小，有效提高了电池的短路电流密度。其中指状交叉背接触太阳电池(IBC)因其器件结构的特殊性(金属电极位于电池片背面，正负极呈指交叉状排列)，无需考虑正面的接触电阻，可以进一步优化前表面陷光和钝化性能；背部可以优化金属栅线电极，从而降低串联电阻，从而提高了填充因子。
传统背接触太阳电池结构中具有隧穿氧钝化接触(TOPCon)结构，该钝化结构包括一层超薄的氧化硅层加上一层重掺杂的多晶硅层共同钝化电池的背表面。此结构的钝化机理是：超薄氧化硅直接与硅衬底接触，中和硅表面的悬挂键，进行优异的化学钝化；重掺杂的多晶硅层因与硅衬底存在费米能级的差异，在硅衬底表面造成能带弯曲，可以更加有效的阻挡少子的通过，而不会影响多子的传输，实现载流子的选择性收集。载流子可以直接高效的通过氧化层进行一维纵向传输，使得电流传输路径达到最短，避免了载流子在二维传输过程中引起的复合，降低了电池的串阻，使得电池具有更高的填充因子，因而可以获得更高的光电转换 效率。但是传统制备上述TOPCon结构中掺杂层的制备是采用低压化学气相沉积(LPCVD)以及等离子体增强化学气相沉积(PECVD)的沉积方式，且由于掺杂层的厚度较厚因此利用上述沉积方法会在电池的正面存在有一定厚度的掺杂层材料的绕镀。形成的绕镀材料会极大降低电池的转换效率，造成一定程度漏电。此外LPCVD路线的磷扩散还会影响电池正面，所以为了去除这些绕镀，通常还会加一步湿法工序。然而增加湿法工序不仅会增加设备以及人工成本，还可能因为湿法影响到电池正面本身的形貌等问题，也会影响电池转换效率。
发明内容
本公开提供了一种太阳电池的制备方法，包括以下步骤：
S10：提供硅片衬底，所述硅片衬底具有第一表面以及与所述第一表面相对的第二表面；
S20：在所述硅片衬底的第一表面上形成含硅薄膜，所述含硅薄膜包括在所述硅片衬底的第一表面上依次形成的氧化硅层、掺杂层以及掩膜层，其中厚度为30nm～300nm的所述掺杂层的形成方法包括：在掺杂气源的流量为100sccm～1000sccm以及硅烷的流量为1000sccm～4000sccm气氛中形成厚度为10nm～30nm的所述掺杂层，在所述掺杂气源的流量为1500sccm～3000sccm以及硅烷的流量为1000sccm～4000sccm气氛中形成余下厚度的所述掺杂层；
S30：对所述第一表面上的所述含硅薄膜进行图案化处理，形成图案化区域；
S40：对具有所述含硅薄膜以及所述图案化区域的所述硅片衬底进行制绒处理。
在本公开的一些实施例中，步骤S20中形成所述掺杂层的温度为200℃ ～700℃。
在本公开的一些实施例中，所述掺杂气源选自磷烷、乙硼烷、三甲基硼烷以及三氟化硼中的至少一种。
在本公开的一些实施例中，步骤S20之后以及步骤S30之前还包括退火处理的步骤。
在本公开的一些实施例中，在退火的步骤中，退火处理的温度为800℃～950℃，退火处理的时间为30min～50min。
在本公开的一些实施例中，通过等离子体增强化学气相沉积、低压化学气相沉积或热氧的方法在所述第一表面上形成所述氧化硅层。
在本公开的一些实施例中，所述氧化硅层的厚度为0.5nm～2.5nm。
在本公开的一些实施例中，通过热氧、等离子体增强化学气相沉积或低压化学气相沉积的方法在所述掺杂层上形成所述掩膜层。
在本公开的一些实施例中，所述掩膜层的厚度为5nm～100nm。
在本公开的一些实施例中，在制备所述具有绒面的硅片衬底之后还包括：在所述具有绒面的硅片衬底的所述第一表面上依次形成第一钝化膜层以及第一减反射膜层。
在本公开的一些实施例中，在制备所述具有绒面的硅片衬底之后还包括：在所述具有绒面的硅片衬底的所述第二表面上依次形成第二钝化膜层以及第二减反射膜层。
在本公开的一些实施例中，在步骤S50之后，还包括步骤S60：利用激光对所述第一表面上的所述图案化区域进行图案化开孔，通过丝网印刷制备第一电极和第二电极。
根据本公开的又一些实施例，还提供了一种太阳电池，由包括以下步骤的制备方法制备得到：
S10：提供硅片衬底，所述硅片衬底具有第一表面以及与所述第一表面 相对的第二表面；
S20：在所述硅片衬底的第一表面上形成含硅薄膜，所述含硅薄膜包括在所述硅片衬底的第一表面上依次形成的氧化硅层、掺杂层以及掩膜层，其中厚度为30nm～300nm的所述掺杂层的形成方法包括：在掺杂气源的流量为100sccm～1000sccm以及硅烷的流量为1000sccm～4000sccm气氛中形成厚度为10nm～30nm的所述掺杂层，在所述掺杂气源的流量为1500sccm～3000sccm以及硅烷的流量为1000sccm～4000sccm气氛中形成余下厚度的所述掺杂层；
S30：对所述第一表面上的所述含硅薄膜进行图案化处理，形成图案化区域；
S40：对具有所述含硅薄膜以及所述图案化区域的所述硅片衬底进行制绒处理。
在本公开的一些实施例中，步骤S20中形成所述掺杂层的温度为200℃～700℃。
在本公开的一些实施例中，所述掺杂气源选自磷烷、乙硼烷、三甲基硼烷以及三氟化硼中的至少一种。
在本公开的一些实施例中，步骤S20之后以及步骤S30之前还包括退火处理的步骤。
在本公开的一些实施例中，在退火的步骤中，退火处理的温度为800℃～950℃，退火处理的时间为30min～50min。
在本公开的一些实施例中，通过等离子体增强化学气相沉积、低压化学气相沉积或热氧的方法在所述第一表面上形成所述氧化硅层。
在本公开的一些实施例中，所述氧化硅层的厚度为0.5nm～2.5nm。
在本公开的一些实施例中，通过热氧、等离子体增强化学气相沉积或低压化学气相沉积的方法在所述掺杂层上形成所述掩膜层。
在本公开的一些实施例中，所述掩膜层的厚度为5nm～100nm。
在本公开的一些实施例中，在制备所述具有绒面的硅片衬底之后还包括：在所述具有绒面的硅片衬底的所述第一表面上依次形成第一钝化膜层以及第一减反射膜层。
在本公开的一些实施例中，在制备所述具有绒面的硅片衬底之后还包括：在所述具有绒面的硅片衬底的所述第二表面上依次形成第二钝化膜层以及第二减反射膜层。
在本公开的一些实施例中，在步骤S50之后，还包括步骤S60：利用激光对所述第一表面上的所述图案化区域进行图案化开孔，通过丝网印刷制备第一电极和第二电极。
根据本公开的又一些实施例，还提供了一种光伏系统，其包括太阳能电池组件以及辅助设备，所述太阳能电池组件包括如上述任一实施例所述的太阳电池。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明本申请的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1为本发明太阳电池结构；
图2为对含硅薄膜进行图案化处理后图案化区域的仰视图；
图3为对图案化区域开孔后的仰视图；
图4为本发明太阳电池的仰视图；
附图说明：10：太阳电池，110：衬底，111：图案化区域，120：复合膜层，121氧化硅层，122：掺杂层，123：含硅薄膜，130：第一钝化膜层，140：第二钝化膜层，150：第一减反射膜层，160：第二减反射膜层，170：第一电极，180：第二电极。
具体实施方式
本发明可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反地，提供这些实施方式的目的是使对本发明的公开内容理解的更加透彻全面。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在发明的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。在本发明的描述中，“若干”的含义是至少一个，例如一个，两个等，除非另有明确具体的限定。
本发明中的词语“优选地”、“更优选地”等是指，在某些情况下可提供某些有益效果的本发明实施方案。然而，在相同的情况下或其他情况下，其他实施方案也可能是优选的。此外，对一个或多个优选实施方案的表述并不暗示其他实施方案不可用，也并非旨在将其他实施方案排除在本发明的范围之外。
当本文中公开一个数值范围时，上述范围视为连续，且包括该范围的最小值及最大值，以及这种最小值与最大值之间的每一个值。进一步地，当范围是指整数时，包括该范围的最小值与最大值之间的每一个整数。此外，当 提供多个范围描述特征或特性时，可以合并该范围。换言之，除非另有指明，否则本文中所公开之所有范围应理解为包括其中所归入的任何及所有的子范围。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
本发明提供一种如图1所示太阳电池10的制备方法，包括以下步骤。
步骤S10：提供硅片衬底110，硅片衬底110具有第一表面以及与第一表面相对的第二表面。
进一步地，上述第一表面即为电池背光面也称背面，第二表面为电池受光面也称正面。
可以理解地，在步骤S10之前还包括对硅片衬底110进行去损伤处理，抛光处理和清洗处理。
进一步地，去损伤处理包括：使用含有物质的量浓度为0.6mol/L～0.8mol/L的一元强碱在50℃～70℃下进行处理。
具体地，去损伤处理的温度可以但不限于是50℃、55℃、60℃、65℃或70℃。
优选地，去损伤处理的溶液为质量百分数为46％的氢氧化钠溶液与水的体积比为4:96～6:94的混合溶液。
更进一步地，抛光处理包括：使用含有物质的量浓度为0.6mol/L～0.8mol/L的一元强碱溶液在65℃～85℃下进行处理，使抛光后反射率20％～40％，具体地，上述抛光后反射率可以但不限于是20％、25％、30％、35％或40％，优选地，硅片衬底抛光后的反射率为30％。
在一个具体示例中，清洗处理包括：依次使用氢氟酸和盐酸的混合溶液、去离子水清洗和烘干。
步骤S20：在硅片衬底110的第一表面上形成含硅薄膜123，含硅薄膜包括在硅片衬底110的第一表面上依次形成的氧化硅层121、掺杂层122以及掩膜层。
在硅片衬底上利用等离子体增强化学气相沉积、低压化学气相沉积或热氧的方法形成厚度为0.5nm～2.5nm的氧化硅层121。
可以理解地，上述氧化硅层121的厚度可以但不限于是0.5nm、1nm、2nm或2.5nm。
具体地，氧化硅层121的形成方法优选为等离子体增强化学气相沉积的方法，
在一个具体示例中，步骤S10中形成氧化硅层121的步骤包括：以1000sccm～5000sccm的流量通入硅烷气体以及以6000sccm～15000sccm的流量通入氢气，在上述气体氛围中，350℃～600℃的温度、电源功率为9KW～12KW以及等离子体脉冲开关比为1:100ms下进行辉光放电，在形成衬底上形成氧化硅层121。
优选地，硅烷气体流量为2500sccm～3000sccm，氢气气体流量为8000sccm～10000sccm。
进一步地，上述制备氧化硅层121的温度优选为400℃～450℃，具体地，上述制备氧化硅层121的温度可以但不限于是410℃、420℃、430℃、440℃或450℃。
更进一步地，电源功率为9KW～10KW
在氧化硅层上，利用物理气相沉积法在包含掺杂气源以及硅烷气氛中形成厚度为30nm～300nm的掺杂层122，
其中，在含有掺杂气源的流量为100sccm～1000sccm以及硅烷的流量为 1000sccm～4000sccm气氛中形成厚度为10nm～30nm的掺杂层，在含有掺杂气源的流量为1500sccm～3000sccm以及硅烷的流量为1000sccm～4000sccm气氛中形成余下的掺杂层122。
进一步地，在含有掺杂气源的流量为200sccm～800sccm以及硅烷的流量为2000sccm～3600sccm气氛中形成厚度为10nm～30nm的掺杂层122。
优选地，上述形成厚度为10nm～30nm的掺杂层122方法中，掺杂气源的流量可以但不限于是200sccm、300sccm、400sccm、500sccm、600sccm、700sccm或800sccm，硅烷的流量可以但不限于是2000sccm、2200sccm、2400sccm、2600sccm、2700sccm、2800sccm、2900sccm、3000sccm、3200sccm、3400sccm或3600sccm。
更进一步地，在含有掺杂气源的流量为2000sccm～3000sccm以及硅烷的流量为2000sccm～3600sccm气氛中形成余下的掺杂层122。
优选地，上述余下厚度的掺杂层122方法中，掺杂气源的流量可以但不限于是2000sccm、2200sccm、2400sccm、2600sccm、2800sccm或3000sccm，硅烷的流量可以但不限于是2000sccm、2200sccm、2400sccm、2600sccm、2700sccm、2800sccm、2900sccm、3000sccm、3200sccm、3400sccm或3600sccm。
进一步地，上述形成掺杂层122的制备过程中的管内压强为1Pa～150Pa，更进一步地，制备上述掺杂层122的时间为5min～20min。
在一个具体示例中，形成掺杂层122的温度为200℃～700℃形成掺杂层122的温度优选为300℃～600℃，进一步地优选为400℃～500℃。
进一步地，形成掺杂层122的温度可以但不限于是300℃、350℃、400℃、450℃、500℃、550℃或600℃。
在一个具体示例中，掺杂气源选自磷烷、乙硼烷、三甲基硼烷以及三氟化硼中的至少一种。
可以理解地，为了制备p型掺杂层122，掺杂气源可以选择磷烷，为了 制备n型掺杂层122，掺杂气源可以选择乙硼烷、三甲基硼烷以及三氟化硼中的至少一种。
上述掺杂层122的掺杂浓度可以通过物理气相沉积的方法中的掺杂气源的流量、硅烷流量以及沉积温度相配合来实现。
优选地，掺杂层122的厚度为100nm～150nm，可以理解地，掺杂层122的厚度可以但不限于是100nm、110nm、120nm、130nm、140nm或150nm。
在一个具体示例中，通过热氧、等离子体增强化学气相沉积或低压化学气相沉积的方法在掺杂层122上形成厚度为5nm～100nm的掩膜层。
在一个具体示例中，掩膜层的厚度为5nm～100nm。
可以理解地，掩膜层的材料可以但不限于是氧化硅以及氮化硅。
优选地，上述掩膜层材料为氧化硅材料，利用热氧生长法，高温通氧在掺杂层122表面原位生长氧化硅层作为掩膜层，温度为600℃～950℃，时间为15min～45min，氧气流量为8000sccm～13000sccm。
在制备生成含硅薄膜123后进行退火处理，可以理解地，上述退火处理对象包括对所形成氧化硅层121以及掺杂层122，还可以对掩膜层进行退火处理。
在一个具体示例中，步骤S30中退火的温度为800℃～950℃，退火的时间为30min～50min。
进一步，退火处理不仅可以使前述物理气相沉积的非晶硅向多晶硅转化，使晶粒生长变大，还可以使掩膜层材料变得更加致密，耐碱性大幅度提高。
上述太阳电池10的制备方法中，利用物理气相沉积的方法通过对掺杂源气体的流量的控制制备掺杂层122，不仅可以实现对掺杂层122的制备，还可以进一步地有效减少在衬底正面上发生的绕镀现象，制备含硅薄膜123 后以及经过激光处理形成图案化区域后，不需要额外的工艺去除绕镀产生的多余的掺杂层122材料，有效减少了制备电池的流程如湿法工艺流程，也不影响电池转换效率以及电池正面外观。
步骤S30：利用激光对第一表面上的含硅薄膜123进行图案化处理，在硅片衬底110的第一表面上形成图案化区域111。
具体地，采用皮秒激光器利用紫外光355nm或者532nm的纳米激光，对硅片衬底110第一表面上部分区域的含硅薄膜123进行去除，形成宽度300μm～500μm的图案化区域111，去除或破坏图案化区域111处的部分含硅薄膜，使其更易被碱溶液腐蚀。如图2为对含硅薄膜123进行图案化处理后图案化区域111的仰视图。
步骤S40：对具有含硅薄膜123以及图案化区域111的硅片衬底110进行制绒处理。
制绒之前还包括利用物质的量浓度为4mol/L～6mol/L的氢氟酸溶液处理绕镀于衬底110的第二表面的掩膜层材料的步骤。
将衬底110的第一表面远离氢氟酸溶液，水平放置，用去离子水覆盖衬底110的第一表面，避免与氢氟酸溶液接触而破坏第一表面上的氧化硅掩膜层。衬底110的第二表面与氢氟酸溶液接触去除绕镀产生的氧化硅掩膜层，清洗时间60s～240s。
可以理解地，上述氢氟酸溶液使用质量分数为49％的氢氟酸与水以(10～30):(70～90)的体积比进行混合，优选地，使用质量分数为49％的氢氟酸与水以20:80的比例进行混合制备氢氟酸溶液。
在一个具体示例中，将预处理硅片衬底110进行制绒处理：将具有含硅薄膜123以及图案化区域111的硅片衬底110置于含有物质的量浓度为0.15mol/L～0.35mol/L的一元强碱的制绒液中进行制绒处理，制绒时间400s～600s，制备具有绒面的硅片衬底110。
在一个具体示例中，一元强碱选自氢氧化钾和氢氧化钠中的至少一种。
可以理解地，制绒的目的是在衬底110的第二表面即受光面形成金字塔状的绒面。
进一步地，上述制绒液还可以包括添加剂，其中添加剂可以但不限于是吲哚丙酸(IPA)。添加剂通常不直接参与化学反应，但是具有降低溶液表面张力，提高反应均匀性、调节一元强碱腐蚀速度显著降低反应速度以及增强腐蚀的各向异性的功能。
在制绒后还包括对具有绒面的硅片衬底110进行可以但不限于是水洗、碱洗、水洗、酸洗、水洗以及烘干的步骤。
其中，碱洗为使用物质的量为0.1％～0.2％的氢氧化钠水溶液进行清洗。进一步地，酸洗使用含氢氟酸的酸溶液去除衬底110的第一表面上图案化区域111外的非图案化区域上最外侧氧化硅掩膜层。
在一个具体示例中，在制备具有绒面的硅片衬底110之后还包括以下步骤S50：在具有绒面的硅片衬底110的第一表面以及复合膜层120上依次形成第一钝化膜层130以及第一减反射膜层150。
可以理解地，在具有绒面的硅片衬底110的第一表面、氧化硅层121以及掺杂层122上依次形成第一钝化膜层130以及第一减反射膜层150。
进一步地，在具有绒面的硅片衬底110的第二表面上依次形成第二钝化膜以及第二减反射膜层160。
可以理解地，上述第一钝化膜层130以及第二钝化膜层140的形成方法可以但不限于是原子层沉积法，进一步地，第一钝化膜层130材料以及第二钝化膜层140材料可以但不限于是氧化铝。
在一个具体示例中，第一钝化膜层130的厚度为2nm～25nm，第二钝化膜层140的厚度为2nm～25nm。
进一步地，上述第一减反射膜层150以及第二减反射膜层160的形成 方法可以但不限于是等离子体增强化学气相沉积，进一步地，第一减反射膜层150材料以及第二减反射膜层160材料可以但不限于是氧化硅、氮氧化硅以及氮化硅中的至少一种。
进一步地，第一减反射膜层150的厚度为50nm～150nm，第二减反射膜层160的厚度为60nm～150nm。
可以理解地，第一减反射膜层150材料以及第二减反射膜层160材料含有氧化硅、氮氧化硅以及氮化硅材料，为三层材料叠置。
在一个具体示例中，还包括以下步骤S60：利用激光对第一表面上的图案化区域进行图案化开孔，通过丝网印刷制备第一电极170和第二电极180。
对第一表面上的图案化区域111以外的区域涂覆烧穿型电极浆料，去除涂覆烧穿型电极浆料处的第一钝化膜层130和第一减反射膜层150，并注入烧穿型电极浆料至烧穿型电极浆料与含硅薄膜123接触，制备第一电极170；
利用激光对第一表面上的图案化区域111进行图案化开孔，去除开孔处的第一钝化膜层130和第一减反射膜层150形成第二电极接触区，在第二电极接触区内注入电极浆料，制备第二电极180。
利用激光对第一表面上的图案化区域111进行图案化开孔，开孔宽度30μm～50μm，去除开孔处的钝化膜层和减反射膜层形成第一电极170接触区。开孔区域呈虚线或者点状分布，如图3所示对图案化区域111开孔后的仰视图。
可以理解地，上述形成第一电极170以及第二电极180的方式可以但不限于是采用丝网印刷方式。与掺杂层122接触的第一电极170不需要开孔处理，第一电极优选使用烧穿型电极浆料，高温可烧透第一钝化膜层130、第一减反射膜层150与掺杂层122形成接触，而衬底110只是局部接触，使用的是非烧穿电极浆料，所以在激光开孔处非烧穿浆料与衬底110形成 接触。
具体地，第一电极170和第二电极180为金属电极，第一电极170材料与第二电极180材料各自独立地选自可以但不限于铝和银中的一种。
进一步地，本发明提供的太阳电池10，按照上述的太阳电池10的制备方法制得的。如图4为太阳电池10的仰视图。
经过上述制备流程制备的太阳电池10优选为背接触电池。
本发明还更进一步地提供一种光伏系统，包括太阳能电池组件以及辅助设备，太阳能电池组件包括上述的太阳电池10。
以下提供具体的实施例对本发明的太阳电池的制备方法作进一步详细地说明。以下具体实施方式所涉及到的原料，若无特殊说明，均可来源于市售。
实施例1
本实施例提供一种p型背接触太阳电池，其制备步骤如下：
S10：对p型硅衬底进行去损伤处理，抛光处理和清洗过程：以p型单晶硅作为电池衬底，使用含有氢氧化钾的60℃溶液进行去损伤处理，使用含有氢氧化钾的溶液在75℃的温度下进行抛光处理，抛光后反射率30％，使用氢氟酸和盐酸的混合溶液进行清洗，以及去离子水进行清洗和烘干。
S20：在p型硅片衬底上形成含硅薄膜：在流量为2600sccm的硅烷气体以及流量为9000sccm的氢气的气氛中，电源功率为9KW，等离子体脉冲开关比为1比100ms以及400℃的温度下，在p型硅衬底上形成厚度为2nm的氧化硅层；在400℃的温度下在上述氧化硅层上先在500sccm的磷烷以及2800sccm的硅烷气氛中制备厚度为30nm的n型掺杂层，再在2500sccm的磷烷以及2800sccm的硅烷气氛中制备厚度为130nm的n型掺杂层，n型掺杂层的掺杂浓度为1E20cm -3～1E21cm -3；随后在n型掺杂层上利用热氧生长法，高温通氧在掺杂层表面原位生长厚度为30nm的氧化硅 作为掩膜层；对上述含硅薄膜在920℃的温度下退火45min。
S30：图形化处理：利用激光对第一表面上的含硅薄膜进行图案化处理，在硅片衬底的第一表面上形成图案化区域。
S40：使用质量分数为49％的氢氟酸与水以20:80的比例进行混合制备氢氟酸溶液去除衬底正面产生的氧化硅掩膜层的绕镀；
再利用含有氢氧化钾或者氢氧化钠溶液在80℃温度下实现对正面绒面的同时并对背面激光图案化区域做刻蚀处理，去除残留的的n型掺杂区的多晶硅材料，在依次进行水洗、碱洗、水洗，由于有氧化硅掩膜层的保护，最后使用含氢氟酸的溶液去除剩余的氧化硅掩膜层并进行水洗和烘干。
S50：分别在电池的正背面镀膜。使用原子层沉积设备单插的方式在正背面同时镀3nm氧化铝膜，作为第一钝化膜层和第二钝化膜层，再利用等离子体增强化学的气相沉积法(PECVD)在正面镀100nm氧化硅、氮氧化硅以及氮化硅的复合膜层作为第二减反射膜层，最后利用PECVD在背面镀100nm上氧化硅、氮氧化硅以及氮化硅的复合膜层作为第一减反射膜层。
S60：利用激光对背面的图案化区域进行图形化后露出的p型衬底区域进行开模，开孔区域呈虚线或者点状分布，开孔宽度40μm，开孔区域作为p型衬底区域的电极接触区。采用丝网印刷方式在电池背面p型衬底区域的电极接触区和n型掺杂层的电极接触区上形成包含导电成分的电极浆料层，铝栅线电极作为电池的正极，银栅线电极作为电池的负极。
对比例1
本对比例提供一种p型背接触太阳电池，其制备步骤如下：
S10：对p型硅衬底进行去损伤处理，抛光处理和清洗过程：以p型单晶硅作为电池衬底，使用含有氢氧化钾的60℃溶液进行去损伤处理，使用含有氢氧化钾的溶液在75℃的温度下进行抛光处理，抛光后反射率30％，使用氢氟酸和盐酸的混合溶液进行清洗，以及去离子水进行清洗和烘干。
S20：在p型硅片衬底上形成含硅薄膜：在流量为2600sccm的硅烷气体以及流量为9000sccm的氢气的气氛中，电源功率为9KW，等离子体脉冲开关比为1比100ms以及400℃的温度下，在p型硅衬底上形成厚度为2nm的氧化硅层；在400℃的温度下在上述氧化硅层上以2500sccm的磷烷以及2800sccm的硅烷气氛中制备厚度为160nm的n型掺杂层；随后在n型掺杂层上利用热氧生长法，高温通氧在掺杂层表面原位生长厚度为30nm的氧化硅作为掩膜层；对上述含硅薄膜在920℃的温度下退火45min。
S30：图形化处理：利用激光对第一表面上的含硅薄膜进行图案化处理，在硅片衬底的第一表面上形成图案化区域。
S40：使用质量分数为49％的氢氟酸与水以20:80的比例进行混合制备氢氟酸溶液去除衬底正面产生的氧化硅掩膜层的绕镀；
再利用含有氢氧化钾或者氢氧化钠溶液在80℃温度下实现对正面绒面的同时并对背面激光图案化区域做刻蚀处理，去除残留的的n型掺杂区的多晶硅材料，在依次进行水洗、碱洗、水洗，由于有氧化硅掩膜层的保护，最后使用含氢氟酸的溶液去除剩余的氧化硅掩膜层并进行水洗和烘干。
S50：分别在电池的正背面镀膜。使用原子层沉积设备单插的方式在正背面同时镀3nm氧化铝膜，作为第一钝化膜层和第二钝化膜层，再利用等离子体增强化学气相沉积法(PECVD)在正面镀100nm氧化硅、氮氧化硅以及氮化硅的复合膜层作为第二减反射膜层，最后利用PECVD在背面镀100nm上氧化硅、氮氧化硅以及氮化硅的复合膜层作为第一减反射膜层。
S60：利用激光对背面的图案化区域进行图形化后露出的p型衬底区域进行开模，开孔区域呈虚线或者点状分布，开孔宽度40μm，开孔区域作为p型衬底区域的电极接触区。采用丝网印刷方式在电池背面p型衬底区域的电极接触区和n型掺杂层的电极接触区上形成包含导电成分的电极浆料层，铝栅线电极作为电池的正极，银栅线电极作为电池的负极。
对比例2
本对比例提供一种p型背接触太阳电池，其制备步骤如下：
S10：对p型硅衬底进行去损伤处理，抛光处理和清洗过程：以p型单晶硅作为电池衬底，使用含有氢氧化钾的60℃溶液进行去损伤处理，使用含有氢氧化钾的溶液在75℃的温度下进行抛光处理，抛光后反射率30％，使用氢氟酸和盐酸的混合溶液进行清洗，以及去离子水进行清洗和烘干。
S20：在p型硅片衬底上形成含硅薄膜：在流量为2600sccm的硅烷气体以及流量为9000sccm的氢气的气氛中，电源功率为9KW、等离子体脉冲开关比为1比100ms以及400℃的温度下，在p型硅衬底上形成厚度为2nm的氧化硅层；在400℃的温度下在上述氧化硅层上先在2000sccm的磷烷以及2800sccm的硅烷气氛中制备厚度为30nm的n型掺杂层，再以流量为2500sccm的磷烷以及2800sccm的硅烷气氛中制备厚度为130nm的n型掺杂层；随后在n型掺杂层上利用热氧生长法，高温通氧在掺杂层表面原位生长厚度为30nm的氧化硅作为掩膜层；对上述含硅薄膜在920℃的温度下退火45min。
S30：图形化处理：利用激光对第一表面上的含硅薄膜进行图案化处理，在硅片衬底的第一表面上形成图案化区域。
S40：使用质量分数为49％的氢氟酸与水以20:80的比例进行混合制备氢氟酸溶液去除衬底正面产生的氧化硅掩膜层的绕镀；
再利用含有氢氧化钾或者氢氧化钠溶液在80℃温度下实现对正面绒面的同时并对背面激光图案化区域做刻蚀处理，去除残留的的n型掺杂区的多晶硅材料，在依次进行水洗、碱洗、水洗，由于有氧化硅掩膜层的保护，最后使用含氢氟酸的溶液去除剩余的氧化硅掩膜层并进行水洗和烘干。
S50：分别在电池的正背面镀膜。使用原子层沉积设备单插的方式在正背面同时镀3nm氧化铝膜，作为第一钝化膜层和第二钝化膜层，再利用等 离子体增强化学的气相沉积法(PECVD)在正面镀100nm氧化硅、氮氧化硅以及氮化硅的复合膜层作为第二减反射膜层，最后利用PECVD在背面镀100nm上氧化硅、氮氧化硅以及氮化硅的复合膜层作为第一减反射膜层。
S60：利用激光对背面的图案化区域进行图形化后露出的p型衬底区域进行开模，开孔区域呈虚线或者点状分布，开孔宽度40μm，开孔区域作为p型衬底区域的电极接触区。采用丝网印刷方式在电池背面p型衬底区域的电极接触区和n型掺杂层的电极接触区上形成包含导电成分的电极浆料层，铝栅线电极作为电池的正极，银栅线电极作为电池的负极。
本发明实施例1提供的p型背接触太阳电池，该电池性能为电池转换效率为24.8％，开路电压为720mv，电流18A，填充因子FF在83％以上。对比例1通过只使用一种流量条件制备掺杂层最终制备得到的p型背接触太阳电池，电池转换效率低于24.2％，对比例2通过在制备掺杂层时通入高流量的掺杂源气体流量制备得到的p型背接触太阳电池开压低于715mV，短路电流低于18A，填充因子FF低于83％，转换效率低于24％。传统发射极及背面钝化PERC电池的转换效率通常在21～22％。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，便于具体和详细地理解本发明的技术方案，但并不能因此而理解为对发明专利保护范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。应当理解，本领域技术人员在本发明提供的技术方案的基础上，通过合乎逻辑地分析、推理或者有限的实验得到的技术方案，均在本发明所附权利要求的保护范围内。因此，本发明专利的保护范围应以所附权利要求的内容为准， 说明书以及附图可以用于解释权利要求的内容。

Claims (25)

  1. 一种太阳电池的制备方法，包括以下步骤：
    S10：提供硅片衬底，所述硅片衬底具有第一表面以及与所述第一表面相对的第二表面；
    S20：在所述硅片衬底的第一表面上形成含硅薄膜，所述含硅薄膜包括在所述硅片衬底的第一表面上依次形成的氧化硅层、掺杂层以及掩膜层，其中厚度为30nm～300nm的所述掺杂层的形成方法包括：在掺杂气源的流量为100sccm～1000sccm以及硅烷的流量为1000sccm～4000sccm气氛中形成厚度为10nm～30nm的所述掺杂层，在所述掺杂气源的流量为1500sccm～3000sccm以及硅烷的流量为1000sccm～4000sccm气氛中形成余下厚度的所述掺杂层；
    S30：对所述第一表面上的所述含硅薄膜进行图案化处理，形成图案化区域；
    S40：对具有所述含硅薄膜以及所述图案化区域的所述硅片衬底进行制绒处理。
  2. 根据权利要求1所述的太阳电池的制备方法，步骤S20中形成所述掺杂层的温度为200℃～700℃。
  3. 根据权利要求1所述的太阳电池的制备方法，所述掺杂气源选自磷烷、乙硼烷、三甲基硼烷以及三氟化硼中的至少一种。
  4. 如权利要求1所述的太阳电池的制备方法，步骤S20之后以及步骤S30之前还包括退火处理的步骤。
  5. 根据权利要求4所述的太阳电池的制备方法，在退火的步骤中，退火处理的温度为800℃～950℃，退火处理的时间为30min～50min。
  6. 如权利要求1所述的太阳电池的制备方法，通过等离子体增强化学气相沉积、低压化学气相沉积或热氧的方法在所述第一表面上形成所述氧化硅层。
  7. 根据权利要求1所述的太阳电池的制备方法，所述氧化硅层的厚度为0.5nm～2.5nm。
  8. 如权利要求1所述的太阳电池的制备方法，通过热氧、等离子体增强化学气相沉积或低压化学气相沉积的方法在所述掺杂层上形成所述掩膜层。
  9. 根据权利要求1所述的太阳电池的制备方法，所述掩膜层的厚度为5nm～100nm。
  10. 如权利要求1～9任一项所述的太阳电池的制备方法，在制备所述具有绒面的硅片衬底之后还包括：在所述具有绒面的硅片衬底的所述第一表面上依次形成第一钝化膜层以及第一减反射膜层。
  11. 根据权利要求1～9任一项所述的太阳电池的制备方法，在制备所述具有绒面的硅片衬底之后还包括：在所述具有绒面的硅片衬底的所述第二表面上依次形成第二钝化膜层以及第二减反射膜层。
  12. 如权利要求1～9任一项所述的太阳电池的制备方法，在步骤S50之后，还包括步骤S60：利用激光对所述第一表面上的所述图案化区域进行图案化开孔，通过丝网印刷制备第一电极和第二电极。
  13. 一种太阳电池，由包括以下步骤的制备方法制备得到：
    S10：提供硅片衬底，所述硅片衬底具有第一表面以及与所述第一表面相对的第二表面；
    S20：在所述硅片衬底的第一表面上形成含硅薄膜，所述含硅薄膜包括在所述硅片衬底的第一表面上依次形成的氧化硅层、掺杂层以及掩膜层，其中厚度为30nm～300nm的所述掺杂层的形成方法包括：在掺杂气源的流量为100sccm～1000sccm以及硅烷的流量为1000sccm～4000sccm气氛中形成厚度为10nm～30nm的所述掺杂层，在所述掺杂气源的流量为1500sccm～3000sccm以及硅烷的流量为1000sccm～4000sccm气氛中形成余下厚度的所述掺杂层；
    S30：对所述第一表面上的所述含硅薄膜进行图案化处理，形成图案化区域；
    S40：对具有所述含硅薄膜以及所述图案化区域的所述硅片衬底进行制绒处理。
  14. 根据权利要求13所述的太阳电池，步骤S20中形成所述掺杂层的温度 为200℃～700℃。
  15. 根据权利要求13所述的太阳电池，所述掺杂气源选自磷烷、乙硼烷、三甲基硼烷以及三氟化硼中的至少一种。
  16. 如权利要求13所述的太阳电池，步骤S20之后以及步骤S30之前还包括退火处理的步骤。
  17. 根据权利要求16所述的太阳电池，在退火的步骤中，退火处理的温度为800℃～950℃，退火处理的时间为30min～50min。
  18. 如权利要求13所述的太阳电池，通过等离子体增强化学气相沉积、低压化学气相沉积或热氧的方法在所述第一表面上形成所述氧化硅层。
  19. 根据权利要求13所述的太阳电池，所述氧化硅层的厚度为0.5nm～2.5nm。
  20. 如权利要求13所述的太阳电池，通过热氧、等离子体增强化学气相沉积或低压化学气相沉积的方法在所述掺杂层上形成所述掩膜层。
  21. 根据权利要求13所述的太阳电池，所述掩膜层的厚度为5nm～100nm。
  22. 如权利要求13～21任一项所述的太阳电池，在制备所述具有绒面的硅片衬底之后还包括：在所述具有绒面的硅片衬底的所述第一表面上依次形成第一钝化膜层以及第一减反射膜层。
  23. 根据权利要求13～21任一项所述的太阳电池，在制备所述具有绒面的硅片衬底之后还包括：在所述具有绒面的硅片衬底的所述第二表面上依次形成第二钝化膜层以及第二减反射膜层。
  24. 如权利要求13～21任一项所述的太阳电池，在步骤S50之后，还包括步骤S60：利用激光对所述第一表面上的所述图案化区域进行图案化开孔，通过丝网印刷制备第一电极和第二电极。
  25. 一种光伏系统，其包括太阳能电池组件以及辅助设备，所述太阳能电池组件包括如权利要求13～24任一项所述的太阳电池。
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