WO2023226320A1 - 肖特基二极管器件及其制作方法 - Google Patents

肖特基二极管器件及其制作方法 Download PDF

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WO2023226320A1
WO2023226320A1 PCT/CN2022/131803 CN2022131803W WO2023226320A1 WO 2023226320 A1 WO2023226320 A1 WO 2023226320A1 CN 2022131803 W CN2022131803 W CN 2022131803W WO 2023226320 A1 WO2023226320 A1 WO 2023226320A1
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trench
level
sub
layer
trenches
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French (fr)
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袁俊
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Hubei Jiufengshan Laboratory
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Hubei Jiufengshan Laboratory
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Priority claimed from CN202210575076.1A external-priority patent/CN114759096A/zh
Priority claimed from CN202221291724.2U external-priority patent/CN217641350U/zh
Application filed by Hubei Jiufengshan Laboratory filed Critical Hubei Jiufengshan Laboratory
Priority to JP2024557155A priority Critical patent/JP2025511621A/ja
Priority to EP22943507.8A priority patent/EP4485548A4/en
Publication of WO2023226320A1 publication Critical patent/WO2023226320A1/zh
Priority to US18/897,434 priority patent/US20250015203A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H10D8/605—Schottky-barrier diodes  of the trench conductor-insulator-semiconductor barrier type, e.g. trench MOS barrier Schottky rectifiers [TMBS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/125—Shapes of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/051—Manufacture or treatment of Schottky diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H10P30/2042—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors into crystalline silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor

Definitions

  • the present application relates to the technical field of semiconductor devices, and more specifically, to a Schottky barrier diode (SBD for short) device and a manufacturing method thereof.
  • SBD Schottky barrier diode
  • SiC is a wide bandgap semiconductor material that has developed rapidly in the past decade. Compared with other semiconductor materials (such as Si, GaN and GaAs, etc.), SiC material has a wide bandgap, high thermal conductivity, high carrier saturation mobility, High power density and other advantages. SiC can be thermally oxidized to generate silicon dioxide, making it possible to realize power devices and circuits such as SiC MOSFETs and SBDs. Since the 1990s, power devices such as SiC MOSFETs and SBDs have been widely used in switching regulated power supplies, high-frequency heating, automotive electronics, and power amplifiers.
  • Figure 1 is a schematic structural diagram of a conventional SiC Schottky diode device, including: a substrate 11; an epitaxial layer 12 provided on the substrate 11; the side surface of the epitaxial layer 12 away from the substrate 11 includes a functional area There are also ion implantation areas 13 on both sides of the functional area; the surface of the epitaxial layer 12 facing away from the substrate 11 has an anode; and the thin film on the side of the substrate 11 facing away from the epitaxial layer 12 has a cathode.
  • the epitaxial layer is N-type doped SiC
  • the ion implantation region 13 is P+ doped (P-type heavily doped).
  • JBS high-voltage junction barrier Schottky diode
  • the trenched SBD structure can achieve deeper P+ implantation in the SiC epitaxial layer, the trenched SBD structure is prone to produce high electric field areas at the bottom of the trench, and premature breakdown and leakage at the trench corner positions at the bottom of the trench. question.
  • this application provides a Schottky diode device and a manufacturing method thereof.
  • the scheme is as follows:
  • a Schottky diode device including:
  • An epitaxial wafer having an epitaxial layer; the epitaxial layer has an opposite first surface and a second surface; the first surface has a functional area and trench areas located on both sides of the functional area;
  • a multi-level trench located in the trench region, with a first ion implantation region in the surface of the epitaxial layer exposed on the sidewalls and bottom of the multi-level trench;
  • the multi-level trenches include: a plurality of sub-trenches, the plurality of sub-trenches are sequentially from the 1st level sub-trench to the N-th level sub-trench in the first direction, and N is a positive integer greater than 1; so
  • the first direction is the direction in which the second surface points to the first surface; in the same multi-level trench, in the first direction, the width of each of the sub-trenches increases sequentially, at least in the first direction.
  • the side walls of the level 1 sub-trough have side wall protection structures;
  • the first metal electrode fills the multi-level trench, the first metal electrode also covers the functional area of the first surface, and has Schottky contact with the functional area of the first surface.
  • the sidewall protection structure has an opening for exposing the bottom of the multi-level trench
  • an ohmic contact structure located within said opening
  • the first metal electrode is electrically connected to the first ion implantation region at the bottom of the multi-level trench through the ohmic contact structure.
  • the epitaxial layer is a SiC layer
  • the ohmic contact structure is a metal complex formed based on the SiC layer.
  • the height of the ohmic contact structure is less than the height of the first-level sub-trench and less than the height of the sidewall protection structure.
  • the height of the spacer protection structure does not exceed the height of the first-level sub-trench.
  • the sidewall protection structure is a SiO 2 layer or a SiN layer.
  • the epitaxial wafer includes a semiconductor substrate, and the second surface is arranged opposite to the semiconductor substrate;
  • a side surface of the semiconductor substrate facing away from the epitaxial layer has a second metal electrode.
  • the first surface has a second ion implantation region surrounding the multi-level trench opening, and the second ion implantation region is in contact with the first ion implantation region.
  • the second ion implantation region and the first ion implantation region are both reverse-type doped with the epitaxial layer.
  • This application also provides a method for manufacturing a Schottky diode device, including:
  • An epitaxial wafer having an epitaxial layer; the epitaxial layer has an opposite first surface and a second surface; the first surface has a functional area and trench areas located on both sides of the functional area;
  • a multi-level trench is formed in the trench area.
  • the multi-level trench includes: a plurality of sub-trenches.
  • the plurality of sub-trenches are sequentially from the 1st level sub-trench to the N-th level sub-trench in the first direction.
  • Groove, N is a positive integer greater than 1;
  • the first direction is the direction in which the second surface points to the first surface; in the same multi-level groove, in the first direction, each The width of the sub-groove increases successively;
  • a side wall protection structure is formed on at least the side wall of the first-level sub-trench
  • a first-level metal electrode is formed in the multi-level trench.
  • the first metal electrode also covers the functional area of the first surface and has Schottky contact with the functional area of the first surface.
  • the method of forming the side wall protection structure includes:
  • the insulating dielectric layer covers the sidewalls and bottom of the multi-level trench, and covers the functional area of the first surface
  • the method before removing the insulating dielectric layer on the first surface and part of the insulating dielectric layer in the multi-level trench, the method further includes:
  • the ohmic contact structure is formed.
  • the Schottky diode device includes: an epitaxial wafer having an epitaxial layer; the epitaxial layer has an opposite first surface and a third Two surfaces; the first surface has a functional area and trench areas located on both sides of the functional area; a multi-level trench located in the trench area, sidewalls of the multi-level trench and an epitaxial extension exposed at the bottom There is a first ion implantation region in the layer surface; the multi-level trench includes: a plurality of sub-trenches, the plurality of sub-trenches are in order from the 1st level sub-trench to the N-th level sub-trench in the first direction , N is a positive integer greater than 1; the first direction is the direction in which the second surface points to the first surface; in the same multi-level trench, in the first direction, each of the sub-substrates The width of the trench increases sequentially, and
  • Figure 1 is a schematic structural diagram of a conventional SiC Schottky diode device
  • Figure 2 is a schematic structural diagram of a Schottky diode device provided by an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of a Schottky diode device provided by an embodiment of the present application.
  • 4 to 22 are process flow charts of a Schottky diode device manufacturing method provided by embodiments of the present application.
  • the trenched SBD structure is prone to generate high electric field areas at the bottom of the trench. Especially if the bottom of the trench is in direct contact with the metal electrode, it is easy to generate a high electric field, causing premature breakdown or leakage of the device at the trench corners; the metal electrode is directly formed It is also easy to form metal spikes at the bottom of the trench; even if various efforts are made to make the trench smoother, there will still be a high electric field problem at the bottom, making it difficult to produce reliable devices in stable mass production.
  • the technical solution of this application provides a Schottky diode device and a manufacturing method thereof.
  • the sidewall protection structure By arranging the sidewall protection structure, it can solve the problem of early breakdown or premature breakdown of the device at the corners of multi-level trenches due to high electric fields. It's a leakage problem.
  • an ohmic contact structure can be formed at the bottom of the multi-level trench, so that the first metal electrode is electrically connected to the first ion implantation region through the ohmic contact structure.
  • a composite filling structure is formed at the bottom of the multi-level trench to avoid the first
  • the metal electrode directly contacts the bottom of the multi-level trench to avoid leakage and breakdown problems caused by the high electric field at the slot angle caused by the direct contact of the first metal electrode with the multi-level trench at the bottom of the multi-level trench, thereby improving device reliability.
  • An ohmic contact structure is provided at the bottom of the multi-level trench, and a trench sidewall protection structure is provided on the side wall of the first-level sub-trench, thereby forming a composite filling at the bottom of the multi-level trench, which not only prevents the first metal electrode from directly Direct contact with the bottom of the multi-level trench, and the bottom of the first metal electrode is surrounded by the sidewall protection structure and the ohmic contact structure, thereby forming a MOS capacitor structure, which does not affect the Schottky sensitivity of the first ion implantation area
  • the shielding of the electric field in the multi-level trench can also alleviate the high electric field at the bottom of the multi-level trench, avoid premature breakdown and leakage at the bottom of the multi-level trench, and enhance the manufacturability and reliability of the device.
  • FIG. 2 is a schematic structural diagram of a Schottky diode device provided by an embodiment of the present application.
  • the Schottky diode device includes:
  • An epitaxial wafer having an epitaxial layer 21; the epitaxial layer 21 has an opposite first surface S1 and a second surface S2; the first surface S1 has a functional area S11 and trench areas S12 located on both sides of the functional area S11 ;
  • the multi-level trench 22 located in the trench region S12 has a first ion implantation region 23 in the surface of the epitaxial layer exposed on the sidewalls and bottom of the multi-level trench 22;
  • the multi-level trench 22 includes: a plurality of sub-trenches, and the plurality of sub-trench are in the first direction (the direction from bottom to top in FIG. 2 ), from the 1st level sub-trench to the N-th level sub-trench in order.
  • groove, N is a positive integer greater than 1;
  • the first direction is the direction in which the second surface S2 points to the first surface S1; in the same multi-level groove 22, in the first direction,
  • the width of each sub-trench increases sequentially, and at least the side wall of the first-level sub-trench has a side wall protection structure 25;
  • the first metal electrode 24 filling the multi-level trench 22, the first metal electrode 24 also covers the functional area S11 of the first surface S1, and has a Schottky relationship with the functional area S11 of the first surface S1. touch.
  • the contact surface between the first metal electrode 24 and the functional area S11 of the first surface S1 is a Schottky area.
  • multi-level trenches 22 are formed in the trench region S12, which can form deep trenches, thereby forming a first ion implantation region 23 with a larger depth in the epitaxial layer 21.
  • the epitaxial layer 21 is a SiC layer and the first ion implantation region 23 is a P+ doped ion implantation region, a larger depth of P+ ion implantation can be achieved in the SiC material without high-energy and high-dose ion implantation. Destroy the lattice structure of SiC.
  • the side walls of at least the first-level sub-trench are provided with side wall protection structures 25, which can effectively protect the bottom groove corners of the multi-stage trenches 22, and solve the problem that the groove corner positions of the multi-stage trenches are prone to premature breakdown. and leakage problems.
  • the Schottky diode device can also be shown in Figure 3.
  • Figure 3 is a schematic structural diagram of a Schottky diode device provided by an embodiment of the present application.
  • the side wall The protection structure 25 has an opening for exposing the bottom of the multi-level trench 22; an ohmic contact structure 26 located in the opening; wherein the first metal electrode 24 communicates with the multi-level trench 22 through the ohmic contact structure 25.
  • the first ion implantation region 23 at the bottom 22 of the stage trench is electrically connected.
  • an ohmic contact structure 26 is provided at the bottom of the multi-stage trench 22 , and a trench sidewall protection structure 25 is provided on the side wall of the first-stage sub-trench, thereby protecting the bottom of the multi-stage trench 22 .
  • Forming the composite filling not only avoids direct contact between the first metal electrode 24 and the bottom of the multi-level trench 22, but also allows the bottom of the first metal electrode 24 to be surrounded by the sidewall protection structure 25 and the ohmic contact structure 26.
  • MOS capacitor structure which does not affect the shielding of the Schottky region electric field by the first ion implantation region 23, and at the same time can alleviate the high electric field at the bottom of the multi-level trench 22 and avoid premature breakdown and leakage at the bottom of the multi-level trench 22. , enhance device manufacturability and reliability.
  • the epitaxial layer 21 is a SiC layer; the ohmic contact structure 26 is a metal complex formed based on the SiC layer 21 .
  • Using a metal complex as the ohmic contact structure 26 can effectively improve device performance and enhance device manufacturability and reliability.
  • the height of the ohmic contact structure 26 is smaller than the height of the first-level sub-trench and smaller than the height of the side wall protection structure 25 . A smaller height is used.
  • the thickness of the ohmic contact structure 26 can meet the filling requirements of the bottom of the multi-level trench 22, reduce the manufacturing cost, and improve the production efficiency.
  • the height of the sidewall protection structure 25 does not exceed the first-level sub-trench the height of.
  • the side wall protection structure 25 is a SiO 2 layer or a SiN layer.
  • the material of the side wall protection structure 25 can be selected based on requirements, which is not specifically limited in the embodiment of the present application.
  • the epitaxial wafer includes a semiconductor substrate 20 , and the second surface S2 is opposite to the semiconductor substrate 20 ; wherein, one surface of the semiconductor substrate 20 faces away from the epitaxial layer 21 There is a second metal electrode 27 .
  • the first metal electrode 24 is the anode of the Schottky diode device
  • the second metal electrode 27 is the cathode of the Schottky diode device.
  • the thickness of the first ion implantation region 23 in the second direction gradually decreases along the first direction, and the second direction is parallel to the first surface. S1.
  • the thickness of the first ion implantation region 23 is the thinnest, problems such as leakage and leakage or breakdown caused by electric field accumulation will occur at this position, affecting the manufacturability of the device. and reliability.
  • the surface of the epitaxial layer 21 facing away from the semiconductor substrate 20 has a second layer surrounding the multi-level trench opening.
  • the second ion implantation region 28 is in contact with the first ion implantation region 23 .
  • the second ion implantation region 28 can be used as a voltage buffer region to achieve voltage buffering in the opening region of the multi-level trench 22 .
  • the second ion implantation region 28 and the first ion implantation region 23 are both inversely doped with the epitaxial layer 21 .
  • the epitaxial layer 21 is an N- (N-type lightly doped) epitaxial layer, and the second ion implantation region 28 and the first ion implantation region 23 can both be P+ ion implantation regions.
  • the voltage buffering of the opening area of the multi-level trench 22 is achieved through the second ion implantation region 28 .
  • the multi-level trench structure can avoid the contradiction between the forward conduction resistance of the device caused by a single-width trench and the withstand voltage of the Schottky region and the reliability of the surface electric field, further enhancing the withstand voltage capability of the SBD device while maintaining Lower forward conduction resistance.
  • the second ion implantation region 28 can enhance the process tolerance of the device, avoid leakage caused by the Schottky contact process near the opening of the multi-level trench 22, and leakage or breakdown problems caused by electric field accumulation, and enhance the manufacturability of the device. and reliability.
  • Another embodiment of the present application also provides a method for manufacturing a Schottky diode device.
  • the manufacturing method is shown in Figures 4 to 22.
  • Figures 4 to 22 are process flow charts of a Schottky diode device manufacturing method provided by embodiments of the present application.
  • the manufacturing method includes:
  • Step S11 As shown in Figure 4, an epitaxial wafer is provided with an epitaxial layer 21.
  • the epitaxial layer 21 has an opposite first surface S1 and a second surface S2; the first surface S1 has a functional region S11 and trench regions S12 located on both sides of the functional region S11.
  • the epitaxial wafer has a base 20, the epitaxial layer 21 is disposed on the base 20, and the second surface S2 and the base 20 are arranged oppositely.
  • the substrate 20 may be an N+ (N-type heavily doped) SiC substrate.
  • the epitaxial layer 21 is an N-SiC epitaxial layer.
  • Step S12 As shown in FIG. 5, multi-level trenches 22 are formed in the trench region S12.
  • the multi-level trenches include: a plurality of sub-trenches, the plurality of sub-trenches are sequentially from the 1st level sub-trench to the N-th level sub-trench in the first direction, and N is a positive integer greater than 1; so
  • the first direction is the direction in which the second surface S2 points to the first surface S1; in the same multi-level trench 22, in the first direction, the width of each sub-trench increases sequentially. .
  • N is a positive integer greater than 1.
  • the distance between the i-th sub-trench is Li
  • Li -1 is greater than Li
  • i is a positive integer greater than 1 and not greater than N.
  • the depth of the i-th sub-trench is ti .
  • the depth of the first-level sub-trench is t 1 and the depth of the i-th sub-trench is t 2 .
  • the value of t i can be set based on requirements, and this is not specifically limited in the embodiments of this application.
  • the epitaxial wafer is photolithographed and etched twice or multiple times to form a two-level trench or a multi-level trench larger than two levels.
  • alignment marks need to be made for position alignment in the subsequent photolithography process.
  • the technical solution of this application is to prepare the first-level sub-trench while making the alignment mark. There is no need to add a separate etching process. The etching process of the alignment mark is reused to prepare the first-level sub-trench, which reduces the manufacturing cost. cost.
  • the multi-level trench 22 may be formed based on the mask layer 30 disposed on the first surface S1.
  • the embodiment of the present application does not specifically limit the manner of corresponding multi-level trenches 22 .
  • the mask layer 30 on the first surface S1 is removed.
  • Step S13 As shown in FIGS. 6 to 11 , a first ion implantation region 23 is formed in the surface of the epitaxial layer exposed on the sidewalls and bottom of the multi-level trench 22 .
  • step S13 specifically includes:
  • a sacrificial layer 31 is deposited on the first surface S1, including a first silicon dioxide layer 311, a polysilicon layer 312 and a second silicon dioxide layer 313 stacked in sequence.
  • the sacrificial layer 31 is patterned in a subsequent process, it can be used as a shielding structure for ion implantation.
  • P-type doping of SiC materials generally uses high-energy Al ion implantation, and the polysilicon layer 312 can form a post-implantation masking effect.
  • first use etching silicon oxide polysilicon has a higher selectivity etching gas, such as at least one of CF 4 , or CHF 3 , or CH 2 F 2 , or C 4 F 8 , together with oxygen, nitrogen, and argon.
  • the formed mixed gas etches the second silicon dioxide layer 313, and the etching stops on the surface of the polysilicon layer 312.
  • the opening in the second silicon dioxide layer 313 is determined based on the mask 32 .
  • an etching gas with a high selectivity ratio of polysilicon to silicon oxide such as a mixed gas of HBr and Ar, is used to etch the polysilicon layer 312 .
  • a gas with good etching properties for silicon oxide is used, such as at least one of CF 4 , or CHF 3 , or CH 2 F 2 , or C 4 F 8 , together with oxygen,
  • the first silicon dioxide layer 311 is etched by a mixed gas of nitrogen and argon.
  • F-based gases such as CHF 3 and CF 4 are used to etch away the first silicon dioxide layer 311 .
  • P ions are implanted into the sidewalls and bottom of the multi-level trench 22 to form the first ion implantation region 23 , where the implanted ions are preferably Al ions.
  • the remaining sacrificial layer 31 is removed.
  • dry etching and wet etching processes are used to remove the remaining sacrificial layer 31 on the first surface S1.
  • the manufacturing method further includes: performing annealing activation and lattice repair in the ion implantation region.
  • the carbon film protection commonly used in silicon carbide device technology is used, and the injected P-type ions such as Al ions are annealed, activated and lattice repaired in a high-temperature furnace tube at 1500°C-1900°C for 10 minutes to 30 minutes.
  • the ion implantation window is larger than the opening of the multi-level trench 22 on the first surface S1, and a portion of the first surface S1 around the opening of the multi-level trench 22 on the first surface S1 is exposed. In this way, While ion implantation is performed to form the first ion implantation region 23, the second ion implantation region 28 can be simultaneously formed on the first surface S1.
  • Step S14 As shown in Figures 12-22, form sidewall protection structures 25 on at least the side walls of the first-level sub-trench.
  • Step S14 includes: forming an insulating dielectric layer covering the sidewalls and bottom of the multi-level trench, and covering the functional area of the first surface; the insulating dielectric layer corresponding to the multi-level trench forming an opening in the area at the bottom of the trench to expose part of the bottom area of the multi-level trench; removing the insulating dielectric layer on the first surface and part of the insulating dielectric layer in the multi-level trench, The insulating dielectric layer remaining in the multi-level trench is the sidewall protection structure.
  • the method further includes: forming a first metal layer at the bottom of the opening; based on the first A metal layer forms the ohmic contact structure.
  • step S14 includes:
  • an insulating dielectric layer 250 is formed.
  • the insulating dielectric layer is SiO 2 or SiN.
  • the insulating dielectric layer 250 covers the first surface S1 and the sidewalls and bottom of the multi-level trench 22 .
  • the insulating dielectric layer 250 can be prepared using a CVD process or a LPCVD process, and the insulating dielectric layer 250 with good trench step coverage can be formed.
  • Figure 13 is an SEM image of the multi-level trench 22 covered with the insulating dielectric layer 250. Based on Figure 13, it can be seen that an insulating dielectric layer with good trench step coverage can be formed on the surface of the multi-level trench 22. 250.
  • an opening is formed in the bottom of the insulating dielectric layer 250 corresponding to the multi-level trench 22 to expose part of the bottom region of the multi-level trench 22 .
  • the insulating dielectric layer 250 at the bottom of the multi-level trench 22 can be opened through photolithography and etching to facilitate subsequent processes to form the ohmic contact structure 26 . Openings may be formed in the insulating dielectric layer 250 based on the mask 33 . When forming an opening in the insulating dielectric layer 250, the etching depth of the underlying epitaxial layer 21 does not exceed 500 nm.
  • a metal layer 260 is deposited.
  • the metal layer 260 covers the side surface of the insulating dielectric layer 250 facing away from the epitaxial wafer and covers the bottom of the multi-level trench 22 exposed by the insulating dielectric layer 250 .
  • the metal layer 260 can be formed using PVD or evaporation process.
  • the metal layer 260 is a material that can perform a complexing reaction with SiC to form a good ohmic contact, such as Ni.
  • the metal layer 260 is formed, through a rapid annealing process (RTA), such as RTA annealing at 800-1100°C for 30 seconds to 5 minutes, the metal layer 260 at the bottom of the trench is separated from the silicon carbide.
  • RTA rapid annealing process
  • a metal silicide reaction occurs to form a metal complex, which is converted into an ohmic contact structure 26. Since the metal layer 260 on the surface of the insulating dielectric layer 250 is isolated by the insulating dielectric layer 250, no metal silicide reaction occurs.
  • the ohmic contact structure is metal silicide.
  • FIG. 17 dry etching or wet etching such as Ni etching solution is used to etch away the metal layer 260 where no metal silicide reaction has occurred, leaving only the ohmic contact structure 26 at the bottom of the trench. .
  • FIG. 18 is an SEM image after the ohmic contact structure 26 is formed. Based on Figure 18, it can be seen that a good ohmic contact effect can be formed.
  • an etching method such as a combination of dry etching and wet etching is used to remove the insulating dielectric layer 250 in the plane area above the first surface, and remove the insulating dielectric layer 250 in the multi-level trench 22 near the opening area.
  • the insulating dielectric layer 250 is removed, leaving at least the insulating dielectric layer 250 on the sidewalls of the first-level sub-trench.
  • the isolation ring formation method in the CMOS process can be used to etch the insulating dielectric layer 250 to form the sidewall protection structure 25 .
  • Figure 20 is an SEM image after the sidewall protection structure 25 is formed. Based on Figure 20, it can be seen that the sidewall protection structure 25 with good morphology can be formed at the bottom of the multi-level trench.
  • the etching degree of the insulating dielectric layer 250 in the multi-level trench 22 can be controlled to form sidewall protection structures 25 with different coverage, which is not limited to covering only the sidewalls of the first-level trench, but can also Covering the side walls or step structures of other sub-trenches above it.
  • Step S15 Form a first-level metal electrode 24 in the multi-level trench.
  • the first metal electrode 24 also covers the functional area S11 of the first surface S1 and the functional area S11 of the first surface S1.
  • the final Schottky diode device is formed as shown in Figure 3.
  • Figure 21 is an SEM image of a Schottky diode device finally formed using the manufacturing method of the embodiment of the present application.
  • a process such as PVD or evaporation may be used to form the first metal electrode 24 on the first surface S1 and the second metal electrode 27 on the lower surface of the semiconductor substrate 20 .
  • the first metal electrode 24 may be a composite metal layer structure formed of two or more metals such as Ti, Al, or Ti/TiW/Mo/Pt/Al.
  • the first metal electrode 24 forms a non-ohmic contact with the sidewall of the multi-level trench 22 and forms an ohmic contact at the bottom of the multi-level trench 22 .
  • the first metal electrode 24 needs to undergo RTA processing to form Schottky contact with the functional area S11.
  • the electrode metal material can be deposited through a process such as PVD and etched to form a pad.
  • the metal material can be Ti, Al, or two or more of Ti/TiW/Mo/Pt/Al.
  • the preparation of multi-level trenches in the trench area S12 is not limited, and single-level trenches may also be used.
  • Figure 22 is an SEM image of a single-stage trench forming an ohmic contact structure and a sidewall protection structure.
  • the manufacturing method described in the technical solution of the embodiment of the present application can form a multi-step trench Schottky diode device (Multi-Step Trench Junction Barrier Diode with Bottom corner spacer protection) cell structure with side wall protection structure , by constructing a multi-level trench junction barrier Schottky diode device design with a sidewall protection structure in the silicon carbide SBD device cell, it can avoid the trench JBS device from being directly connected to the trench bottom due to the metal layer at the bottom of the trench. Reliability problems such as leakage and breakdown caused by the high electric field at the slot corners caused by corner contact.
  • sidewall protection By setting sidewall protection with a dielectric layer structure at the bottom corner of the multi-level trench JBS, it avoids direct contact between the metal and the trench corner where the strong electric field accumulates at the bottom of the trench, which is conducive to enhancing the reliability of trench devices; filling in the trench
  • the metal layer and sidewall protection structure form a MOS capacitor structure, which does not affect the shielding of the electric field in the Schottky region by the P-type area.
  • it can alleviate the high electric field at the relatively fragile corners of the bottom trench and avoid premature breakdown and leakage at the bottom. Produce, enhance device manufacturability and reliability.

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Abstract

本申请公开了一种肖特基二极管器件及其制作方法，所述肖特基二极管器件包括：外延片，具有外延层；所述外延层具有相对的第一表面和第二表面；所述第一表面具有功能区以及位于所述功能区两侧的沟槽区；位于所述沟槽区的多级沟槽，所述多级沟槽的侧壁以及底部露出的外延层表面内具有第一离子注入区域；所述多级沟槽包括：多个子沟槽，所述多个子沟槽在第一方向上，依次为第1级子沟槽至第N级子沟槽；同一所述多级沟槽中，在所述第一方向上，各个所述子沟槽的宽度依次增大，至少第1级子沟槽的侧壁具有侧墙保护结构；填充所述多级沟槽的第一金属电极，所述第一金属电极还覆盖所述第一表面的功能区，与所述第一表面的功能区具有肖特基接触。

Description

肖特基二极管器件及其制作方法
本申请要求于2022年5月25日提交中国专利局、申请号为202210575076.1、发明名称为“肖特基二极管器件及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
本申请要求于2022年5月25日提交中国专利局、申请号为202221291724.2、发明名称为“肖特基二极管器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体器件技术领域，更具体的说，涉及一种肖特基二极管(Schottky barrier diodes，简称SBD)器件及其制作方法。
背景技术
SiC作为近十几年来迅速发展的宽禁带半导体材料，与其它半导体材料(如Si，GaN及GaAs等)相比，SiC材料具有宽禁带、高热导率、高载流子饱和迁移率、高功率密度等优点。SiC可以热氧化生成二氧化硅，使得SiC MOSFET及SBD等功率器件和电路的实现成为可能。自20世纪90年代以来，SiC MOSFET和SBD等功率器件已在开关稳压电源、高频加热、汽车电子以及功率放大器等方面取得了广泛的应用。
如图1所示，图1为一种常规SiC肖特基二极管器件的结构示意图，包括：基底11；设置在基底11上的外延层12；外延层12背离基底11的一侧表面包括功能区以及在功能区两侧的离子注入区13；外延层12背离基底11的一侧表面具有阳极；基底11背离外延层12的一侧薄膜具有阴极。一般的，外延层为N型掺杂 的SiC，离子注入区13为P+掺杂(P型重掺杂)。对于图1所示器件结构，尤其是高压SBD器件，击穿电压和导通电阻的优化设计是互相影响，且相互矛盾的，获得高击穿电压一般就很难获得低的导通电阻，特别是平面型JBS(高压结势垒肖特基二极管)器件，高耐压设计时由于P+掺杂的离子注入区13注入深度受到工艺设备的限制，很难实现1um以上结深的P+注入。
虽然沟槽式SBD结构能够在SiC外延层中实现较深的P+注入，但是沟槽式SBD结构在沟槽底部容易产生高电场区域，在沟槽底部的槽角位置容易产生提前击穿和漏电问题。
发明内容
有鉴于此，本申请提供了一种肖特基二极管器件及其制作方法，方案如下：
一种肖特基二极管器件，包括：
外延片，具有外延层；所述外延层具有相对的第一表面和第二表面；所述第一表面具有功能区以及位于所述功能区两侧的沟槽区；
位于所述沟槽区的多级沟槽，所述多级沟槽的侧壁以及底部露出的外延层表面内具有第一离子注入区域；
所述多级沟槽包括：多个子沟槽，所述多个子沟槽在第一方向上，依次为第1级子沟槽至第N级子沟槽，N为大于1的正整数；所述第一方向为所述第二表面指向所述第一表面的方向；同一所述多级沟槽中，在所述第一方向上，各个所述子沟槽的宽度依次增大，至少第1级子沟槽的侧壁具有侧墙保护结构；
填充所述多级沟槽的第一金属电极，所述第一金属电极还覆盖所述第一表面的功能区，与所述第一表面的功能区具有肖特基接触。
优选的，在上述肖特基二极管器件中，所述侧墙保护结构具有开口，用于露出所述多级沟槽的底部；
位于所述开口内的欧姆接触结构；
其中，所述第一金属电极通过所述欧姆接触结构与所述多级沟槽底部的所述第一离子注入区电连接。
优选的，在上述肖特基二极管器件中，所述外延层为SiC层；
所述欧姆接触结构为基于所述SiC层形成的金属络合物。
优选的，在上述肖特基二极管器件中，在所述第一方向上，所述欧姆接触结构的高度小于所述第1级子沟槽的高度，且小于所述侧墙保护结构的高度。
优选的，在上述肖特基二极管器件中，在所述第一方向上，所述侧墙保护结构的高度不超过所述第1级子沟槽的高度。
优选的，在上述肖特基二极管器件中，所述侧墙保护结构为SiO 2层，或SiN层。
优选的，在上述肖特基二极管器件中，所述外延片包括半导体基底，所述第二表面与所述半导体基底相对设置；
其中，所述半导体基底背离所述外延层的一侧表面具有第二金属电极。
优选的，在上述肖特基二极管器件中，所述第一表面内具有包围所述多级沟槽开口的第二离子注入区，所述第二离子注入区与所述第一离子注入区接触；
其中，所述第二离子注入区与所述第一离子注入区均是与所述外延层反型掺杂。
本申请还提供了一种肖特基二极管器件的制作方法，包括：
提供外延片，具有外延层；所述外延层具有相对的第一表面和第二表面；所述第一表面具有功能区以及位于所述功能区两侧的沟槽区；
在所述沟槽区形成多级沟槽，所述多级沟槽包括：多个子沟槽，所述多个子沟槽在第一方向上，依次为第1级子沟槽至第N级子沟槽，N为大于1的正整数；所述第一方向为所述第二表面指向所述第一表面的方向；同一所述多级沟槽中，在所述第一方向上，各个所述子沟槽的宽度依次增大；
在所述多级沟槽的侧壁以及底部露出的外延层表面内形成第一离子注入区域；
至少在第1级子沟槽的侧壁形成侧墙保护结构；
在所述多级沟槽内形成第一级金属电极，所述第一金属电极还覆盖所述第一表面的功能区，与所述第一表面的功能区具有肖特基接触。
优选的，在上述制作方法中，形成所述侧墙保护结构的方法包括：
形成绝缘介质层，所述绝缘介质层覆盖所述多级沟槽的侧壁以及底部，且覆盖所述第一表面的功能区；
在所述绝缘介质层对应所述多级沟槽底部的区域形成开口，以露出所述多级沟槽的部分底部区域；
去除所述第一表面上的所述绝缘介质层以及所述多级沟槽内的部分所述绝缘介质层，所述多级沟槽内保留的所述绝缘介质层为所述侧墙保护结构。
优选的，在上述制作方法中，在去除所述第一表面上的所述绝缘介质层以及所述多级沟槽内的部分所述绝缘介质层前，还包括：
在所述开口的底部形成第一金属层；
基于所述第一金属层，形成所述欧姆接触结构。
通过上述描述可知，本申请技术方案提供的肖特基二极管器件及其制作方法中，所述肖特基二极管器件包括：外延片，具有外延层；所述外延层具有相对的第一表面和第二表面；所述第一表面具有功能区以及位于所述功能区两侧的沟槽区；位于所述沟槽区的多级沟槽，所述多级沟槽的侧壁以及底部露出的外延层表面内具有第一离子注入区域；所述多级沟槽包括：多个子沟槽，所述多个子沟槽在第一方向上，依次为第1级子沟槽至第N级子沟槽，N为大于1的正整数；所述第一方向为所述第二表面指向所述第一表面的方向；同一所述多级沟槽中，在所述第一方向上，各个所述子沟槽的宽度依次增大，至少第1级子沟槽的侧壁具有侧墙保护结构；填充所述多级沟槽的第一金属电极，所述第一金属电极还覆盖所述第一表面的功能区，与所述第一表面的功能区具有肖特基接触。本申请技术方案通过设置所述侧墙保护结构，解决了多级沟槽的槽角位置容易产生提前击穿和漏电问题。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士了解与阅读，并非用以限定本申请可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本申请所能产生的功效及所能达成的目的下，均应仍落在本申请所揭示的技术内容得能涵盖的范围内。
图1为一种常规SiC肖特基二极管器件的结构示意图；
图2为本申请实施例提供的一种肖特基二极管器件的结构示意图；
图3为本申请实施例提供的一种肖特基二极管器件的结构示意图；
图4-图22为本申请实施例提供的一种肖特基二极管器件制作方法的工艺流程图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请中的实施例进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
沟槽式SBD结构在沟槽底部容易产生高电场区域，特别是沟槽底部如果直接和金属电极接触，容易产生高电场导致器件在沟槽槽角处提前击穿或是漏电；金属电极直接形成在沟槽底部也容易形成金属的尖刺；即使采用各种努力把沟槽刻的更圆滑，也依然会有底部高电场问题，难以稳定量产制作出有可靠性的器件。
有鉴于此，本申请技术方案提供了一种肖特基二极管器件及其制作方法，通过设置所述侧墙保护结构，能够解决高电场导致器件在多级沟槽的槽角处提前击穿或是漏电问题。
进一步的，可以在多级沟槽的底部形成欧姆接触结构，使得第一金属电极通过欧姆接触结构和第一离子注入区电连接，这样，在多级沟槽底部形成复合填充结构，避免第一金属电极直接和多级沟槽底部接触，避免器件在多级沟槽底部由于第一金属电极直接和多级沟槽接触导致的槽角高电场产生的漏电和 击穿问题，提高器件可靠性。
在多级沟槽的底部设置欧姆接触结构，并在第1级子沟槽的侧壁设置沟侧墙保护结构，从而对多级沟槽的底部形成复合填充，不仅能够避免第一金属电极直接和多级沟槽底部的直接接触，并使得第一金属电极的底部被所述侧墙保护结构以及所述欧姆接触结构环绕，从而形成MOS电容结构，不影响第一离子注入区域对肖特基区电场的屏蔽，同时可以缓和多级沟槽底部的高电场，避免多级沟槽底部的提前击穿和漏电产生，增强器件的可制造性和可靠性。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本申请作进一步详细的说明。
如图2所示，图2为本申请实施例提供的一种肖特基二极管器件的结构示意图，所示肖特基二极管器件包括：
外延片，具有外延层21；所述外延层21具有相对的第一表面S1和第二表面S2；所述第一表面S1具有功能区S11以及位于所述功能区S11两侧的沟槽区S12；
位于所述沟槽区S12的多级沟槽22，所述多级沟槽22的侧壁以及底部露出的外延层表面内具有第一离子注入区域23；
所述多级沟槽22包括：多个子沟槽，所述多个子沟槽在第一方向(图2中由下至上的方向)上，依次为第1级子沟槽至第N级子沟槽，N为大于1的正整数；所述第一方向为所述第二表面S2指向所述第一表面S1的方向；同一所述多级沟槽22中，在所述第一方向上，各个所述子沟槽的宽度依次增大，至少第1级子沟槽的侧壁具有侧墙保护结构25；
填充所述多级沟槽22的第一金属电极24，所述第一金属电极24还覆盖 所述第一表面S1的功能区S11，与所述第一表面S1的功能区S11具有肖特基接触。其中，所述第一金属电极24与所述第一表面S1的功能区S11接触面为肖特基区。
本申请实施例中，在沟槽区S12形成多级沟槽22，能够形成深沟槽，从而实现在外延层21内形成较大深度的第一离子注入区23。当外延层21为SiC层，第一离子注入区23为P+掺杂的离子注入区时，无需高能量高剂量的离子注入，即可在SiC材料中实现较大深度的P+离子注入，不会破坏SiC的晶格结构。另外，设置至少第1级子沟槽的侧壁具有侧墙保护结构25，能够对多级沟槽22的底部槽角形成有效防护，解决了多级沟槽的槽角位置容易产生提前击穿和漏电问题。
当所述多级沟槽22的底部直接和所述第一金属电极24接触时，容易产生高电场导致器件在沟槽槽角处提前击穿或是漏电，通过设置所述侧墙保护结构25能够一定程度上提升槽角区域耐压以及抗漏电性能。
为了进一步提升器件在槽角区域耐压性能以及抗漏电性能，所述肖特基二极管器件还可以如图3所示。
如图3所示，图3为本申请实施例提供的一种肖特基二极管器件的结构示意图，在图2所示方式基础上，图3所示肖特基二极管器件中，所述侧墙保护结构25具有开口，用于露出所述多级沟槽22的底部；位于所述开口内的欧姆接触结构26；其中，所述第一金属电极24通过所述欧姆接触结构25与所述多级沟槽底部22的所述第一离子注入区23电连接。
在图3所示方式中，在多级沟槽22的底部设置欧姆接触结构26，并在第1级子沟槽的侧壁设置沟侧墙保护结构25，从而对多级沟槽22的底部形成复 合填充，不仅能够避免第一金属电极24直接和多级沟槽22底部的直接接触，并使得第一金属电极24的底部被所述侧墙保护结构25以及所述欧姆接触结构26环绕，从而形成MOS电容结构，不影响第一离子注入区域23对肖特基区电场的屏蔽，同时可以缓和多级沟槽22底部的高电场，避免多级沟槽22底部的提前击穿和漏电产生，增强器件的可制造性和可靠性。
本申请实施例中，所述外延层21为SiC层；所述欧姆接触结构26为基于所述SiC层21形成的金属络合物。采用金属络合物作为所述欧姆接触结构26，能够有效提升器件性能，增强器件的可制造性和可靠性。
如图3所示，在所述第一方向上，设置所述欧姆接触结构26的高度小于所述第1级子沟槽的高度，且小于所述侧墙保护结构25的高度，采用较小厚度的所述欧姆接触结构26，即可实现对多级沟槽22的底部符合填充需求，降低制作成本，提高生产效率。
在本申请实施例所述肖特基二极管器件中，如图2和图3所示，在所述第一方向上，所述侧墙保护结构25的高度不超过所述第1级子沟槽的高度。
可选的，所述侧墙保护结构25为SiO 2层，或SiN层。可以基于需求选择所述侧墙保护结构25的材料，本申请实施例中对此不作具体限定。
如图2和图3所示，所述外延片包括半导体基底20，所述第二表面S2与所述半导体基底20相对设置；其中，所述半导体基底20背离所述外延层21的一侧表面具有第二金属电27。其中，所述第一金属电极24为肖特基二极管器件的阳极，所述第二金属电27为肖特基二极管器件的阴极。
由于多级沟槽22的深度较大，会导致第一离子注入区23在第二方向(图2中水平方向)上的厚度沿第一方向上逐渐减小，第二方向平行于第一表面S1。 特别是在靠近多级沟槽22开口的位置，由于第一离子注入区23的厚度最较薄，在此位置会产生漏电以及电场集聚导致的漏电或击穿等问题，影响器件的可制造性和可靠性。为了解决这些问题，如图2和图3所示，所述肖特基二极管器件中，所述外延层21背离所述半导体基底20一侧表面内具有包围所述多级沟槽开口的第二离子注入区28，所述第二离子注入区28与所述第一离子注入区23接触。所述第二离子注入区28与可以作为电压缓冲区，实现多级沟槽22开口区域的电压缓冲。
其中，所述第二离子注入区28与所述第一离子注入区23均是与所述外延层21反型掺杂。例如，所述外延层21为N-(N型轻掺杂)外延层，所述第二离子注入区28与所述第一离子注入区23可以均为P+离子注入区。
本申请技术方案中，通过所述第二离子注入区28实现多级沟槽22开口区域的电压缓冲。而通过多级沟槽结构，能够避免单一宽度沟槽导致的器件正向导通阻抗与肖特基区耐压以及表面电场可靠性之间的矛盾，进一步增强SBD器件的耐压能力的同时，保持较低的正向导通阻抗。所述第二离子注入区28可以增强器件的工艺容差，避免肖特基接触工艺在多级沟槽22开口附近产生漏电，以及电场集聚导致的漏电或击穿问题，增强器件的可制造性和可靠性。
本申请另一实施例还提供了一种肖特基二极管器件的制作方法，所述制作方法如图4-图22所示。
参考图4-图22所示，图4-图22为本申请实施例提供的一种肖特基二极管器件制作方法的工艺流程图，该制作方法包括：
步骤S11：如图4所示，提供外延片，具有外延层21。
所述外延层21具有相对的第一表面S1和第二表面S2；所述第一表面S1具有功能区S11以及位于所述功能区S11两侧的沟槽区S12。
其中，外延片具有基底20，基底20上行程有所述外延层21，第二表面S2和基底20相对设置。基底20可以为N+(N型重掺杂)的SiC基底。外延层21为N-的SiC外延层。
步骤S12：如图5所示，在所述沟槽区S12形成多级沟槽22。
所述多级沟槽包括：多个子沟槽，所述多个子沟槽在第一方向上，依次为第1级子沟槽至第N级子沟槽，N为大于1的正整数；所述第一方向为所述第二表面S2指向所述第一表面S1的方向；同一所述多级沟槽22中，在所述第一方向上，各个所述子沟槽的宽度依次增大。
设定同一多级沟槽22中，在第一方向上具有依次设置的第1级子沟槽-第N级子沟槽，N为大于1的正整数。可以基于需求设定N的取值，本申请对此不作具体限定。本申请实施例中，以N＝2为例进行说明，即多级沟槽22具有两级沟槽。
在功能区S11两侧，两个多级沟槽22中，第i级子沟槽之间的间距为L i，L i-1大于L i，i为大于1，且不大于N的正整数，这样，以使得同一多级沟槽22中，从上到下，各级子沟槽的宽度依次递减，L i的取值可以基于需求设定，本申请实施例对此不作具体限定。以N＝2为例，两个多级沟槽22中，第1级子沟槽之间的间距为L 1，第二级子沟槽之间的间距为L 2，L 1大于L 2。同一多级沟槽22中，第i级子沟槽的深度为t i。以N＝2为例，同一多级沟槽22中，第1级子沟槽的深度为t 1，第i级子沟槽的深度为t 2。t i的取值可以基于需求设定，本申请实施例对此不作具体限定。
对外延片进行两次或是多次光刻和刻蚀，形成两级沟槽或是大于两级的多级沟槽。其中，外延片在进入工艺产线后需要制作对位标记，用于后续光刻工艺的位置对准。本申请技术方案在制作所述对位标记的同时制备第一级子沟槽，无需单独增加刻蚀工艺，复用对位标记的刻蚀工序制备所述第一级子沟槽，降低了制作成本。
可以基于设置在第一表面S1上的掩膜层30形成多级沟槽22。本申请实施例对应多级沟槽22的方式不作具体限定。形成多级沟槽22后，去除第一表面S1上的掩膜层30。
步骤S13：如图6-图11所示，在所述多级沟槽22的侧壁以及底部露出的外延层表面内形成第一离子注入区域23。
其中，步骤S13具体包括：
首先，如图6所示，在第一表面S1沉积牺牲层31，包括依次层叠的第一二氧化硅层311、多晶硅层312和第二二氧化硅层313。后续工序对牺牲层31进行图形化后，可以作为离子注入的掩蔽结构。SiC材料的P型掺杂一般采用高能Al离子注入，多晶硅层312能够形成后的离子注入掩蔽效果。
然后，如图7所示，同光光刻和干法刻蚀，在第二二氧化硅层313形成开口，以便于后续通过离子注入形成第一离子注入区23。先采用刻蚀氧化硅：多晶硅有较高选择比的刻蚀气体，如CF 4、或CHF 3、或CH 2F 2、或C 4F 8中的至少一种，与氧气、氮气、氩气形成的混合气体对第二二氧化硅层313进行刻蚀，刻蚀停在多晶硅层312的表面。基于掩膜版32确定第二二氧化硅层313中开口。
进一步的，如图8所示，采用多晶硅：氧化硅有高选择比的刻蚀气体，如 HBr和Ar的混合气体，对多晶硅层312进行刻蚀。
进一步的，如图9所示，采用对氧化硅具有较好刻蚀特性的气体，如CF 4、或CHF 3、或CH 2F 2、或C 4F 8中的至少一种，与氧气、氮气、氩气形成的混合气体对第一二氧化硅层311进行刻蚀。或者，采用CHF 3、CF 4等F基气体刻蚀掉第一二氧化硅层311。
进一步的，如图10所示，基于图形化的牺牲层31，对多级沟槽22的侧壁以及底部进行P离子注入，形成第一离子注入区23，其中，注入离子优选为Al离子。
最后，如图11所示，去除剩余的牺牲层31。可选的，采用干法刻蚀和湿法腐蚀工艺去除第一表面S1除剩余的牺牲层31。
可选的，在形成第一离子注入区23后，在形成侧墙保护结构25之前，所述制作方法还包括：进行离子注入区进行退火激活和晶格修复。采用碳化硅器件工艺常用的碳膜保护，并在1500℃-1900℃下的高温炉管中，10分钟-30分钟，对注入的P型离子如Al离子等进行退火激活和晶格修复。
通过设置牺牲层31的图形结构，使得离子注入窗口大于多级沟槽22在第一表面S1的开口，且露出多级沟槽22在第一表面S1开口周围的部分第一表面S1，这样，在进行离子注入形成第一离子注入区23的同时，能够在第一表面S1同时形成第二离子注入区28。
步骤S14：如图12-图22所示，至少在第1级子沟槽的侧壁形成侧墙保护结构25。
在步骤S14包括：形成绝缘介质层，所述绝缘介质层覆盖所述多级沟槽的侧壁以及底部，且覆盖所述第一表面的功能区；在所述绝缘介质层对应所述多 级沟槽底部的区域形成开口，以露出所述多级沟槽的部分底部区域；去除所述第一表面上的所述绝缘介质层以及所述多级沟槽内的部分所述绝缘介质层，所述多级沟槽内保留的所述绝缘介质层为所述侧墙保护结构。
在去除所述第一表面上的所述绝缘介质层以及所述多级沟槽内的部分所述绝缘介质层前，还包括：在所述开口的底部形成第一金属层；基于所述第一金属层，形成所述欧姆接触结构。
具体的，步骤S14的实现方法包括：
首先，如图12所示，形成绝缘介质层250。绝缘介质层为SiO 2或是SiN。绝缘介质层250覆盖第一表面S1以及多级沟槽22的侧壁和底部。可以采用CVD工艺或是LPCVD工艺制备绝缘介质层250，可以形成具有良好沟槽台阶覆盖性的绝缘介质层250。如图13所示，图13为覆盖有绝缘介质层250的多级沟槽22的SEM图，基于图13可知，可以在多级沟槽22表面形成具有良好沟槽台阶覆盖性的绝缘介质层250。
然后，如图14所示，在绝缘介质层250对应多级沟槽22的底部形成开口，以露出多级沟槽22的部分底部区域。可以通过光刻和刻蚀，打开多级沟槽22底部的绝缘介质层250，以便于后续工艺形成欧姆接触结构26。可以基于掩膜版33在绝缘介质层250形成开口。绝缘介质层250形成开口时，对下方外延层21的刻蚀深度不超过500nm。
进一步，如图15所示，沉积金属层260，金属层260覆盖绝缘介质层250背离外延片的一侧表面，覆盖绝缘介质层250露出的多级沟槽22底部。可以采用PVD或是蒸镀工艺，形成该金属层260。该金属层260为能够和SiC进行络合反应形成良好欧姆接触的材料，如Ni。
进一步的，如图16所示，形成金属层260后，通过快速退火工艺(RTA)，如在800-1100℃下进行RTA退火30秒-5分钟，在沟槽底部的金属层260与碳化硅接触的部分，发生金属硅化物反应，形成金属络合物，转化为欧姆接触结构26，绝缘介质层250表面上的金属层260由于绝缘介质层250隔离，不发生金属硅化物反应。本申请实施例中，欧姆接触结构为金属硅化物。
进一步的，如图17所示，采用干法刻蚀、或湿法腐蚀如Ni腐蚀液等，将未发生金属硅化物反应的金属层260腐蚀掉，只留下沟槽底部的欧姆接触结构26。如图18所示，图18为形成欧姆接触结构26后的SEM图。基于图18可知，可以形成良好的欧姆接触效果。
最后，如图19所示，采用干法刻蚀和湿法腐蚀结合等刻蚀方法，将第一表面上方平面区域的绝缘介质层250去除掉，并将多级沟槽22内靠近开口区域的绝缘介质层250去掉，至少保留第一级子沟槽侧壁的绝缘介质层250。可以采用CMOS工艺中的隔离环的形成方法，对绝缘介质层250进行刻蚀，以形成所述侧墙保护结构25。如图20所示，图20为形成侧墙保护结构25后的SEM图，基于图20可知，能够在多级沟槽底部形成形貌良好的侧墙保护结构25。
需要说明的是，可以控制绝缘介质层250在多级沟槽22中的刻蚀程度，以形成不同覆盖的侧墙保护结构25，不局限于仅覆盖第一级沟槽的侧壁，还可以覆盖其上方其他子沟槽的侧壁或是台阶结构。
步骤S15：在所述多级沟槽内形成第一级金属电极24，所述第一金属电极24还覆盖所述第一表面S1的功能区S11，与所述第一表面S1的功能区S11具有肖特基接触，最终形成如图3所示的肖特基二极管器件。如图21所示， 图21为采用本申请实施例制作方法最终形成肖特基二极管器件的SEM图。
在步骤S15中，可以采用PVD或是蒸镀等工艺，在第一表面S1形成第一金属电极24，在半导体基底20下表面形成第二金属电极27。第一金属电极24可以为Ti，或Al，或Ti/TiW/Mo/Pt/Al等两种或多种金属形成的复合金属层结构。第一金属电极24与多级沟槽22的侧壁形成非欧姆接触，在多级沟槽22的底部形成欧姆接触。第一金属电极24需要进行RTA处理，以和功能区S11形成肖特基接触。形成第一金属电极24后，可以通过PVD等工艺沉积电极金属材料并刻蚀形成焊盘，该金属材料可以为Ti，或Al，或Ti/TiW/Mo/Pt/Al等两种或多种金属形成的复合金属层结构。
上述制作方法，以制备图3所示器件结构为例进行说明。显然对应图2所示器件结构，其制作方法可以参考上述工艺流程获得，本申请实施例对此不再赘述。
本申请实施例中，不局限于在沟槽区域S12制备多级沟槽，也可以采用单级沟槽。如图22所示，图22为单级沟槽形成欧姆接触结构和侧墙保护结构的SEM图。
通过上述描述可知，本申请实施例技术方案所述制作方法，能够形成具有侧墙保护结构的多级沟槽肖特基二极管器件(Multi-Step Trench Junction Barrier Diode with Bottom corner spacer protection)元胞结构，通过在碳化硅SBD器件元胞中构造具有侧墙保护结构的多级沟槽结势垒肖特基二极管器件设计，能避免沟槽JBS器件在沟槽底部由于金属层直接和沟槽底部槽角接触导致的槽角高电场产生的漏电和击穿等可靠性问题。通过对多级沟槽JBS的底部槽角设置介 质层构造的侧墙保护，避免金属与沟槽底部强电场聚集的槽角直接接触，有利于增强沟槽类器件的可靠性；沟槽内填充的金属层与侧墙保护结构形成MOS电容结构，不影响P型区对肖特基区电场的屏蔽，同时可以缓和底部沟槽相对脆弱的槽角的高电场，避免底部的提前击穿和漏电产生，增强器件的可制造性和可靠性。
本说明书中各个实施例采用递进、或并列、或递进和并列结合的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。
需要说明的是，在本申请的描述中，需要理解的是，幅图和实施例的描述是说明性的而不是限制性的。贯穿说明书实施例的同样的幅图标记标识同样的结构。另外，处于理解和易于描述，幅图可能夸大了一些层、膜、面板、区域等厚度。同时可以理解的是，当诸如层、膜、区域或基板的元件被称作“在”另一元件“上”时，该元件可以直接在其他元件上或者可以存在中间元件。另外，“在…上”是指将元件定位在另一元件上或者另一元件下方，但是本质上不是指根据重力方向定位在另一元件的上侧上。
术语“上”、“下”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。当一个组件被认为是“连接”另一个组件，它可以是直接连接到另一个组件或者可能同时存在居中设置的组件。
还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来 将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括上述要素的物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (11)

  1. 一种肖特基二极管器件，其特征在于，包括：
    外延片，具有外延层；所述外延层具有相对的第一表面和第二表面；所述第一表面具有功能区以及位于所述功能区两侧的沟槽区；
    位于所述沟槽区的多级沟槽，所述多级沟槽的侧壁以及底部露出的外延层表面内具有第一离子注入区域；
    所述多级沟槽包括：多个子沟槽，所述多个子沟槽在第一方向上，依次为第1级子沟槽至第N级子沟槽，N为大于1的正整数；所述第一方向为所述第二表面指向所述第一表面的方向；同一所述多级沟槽中，在所述第一方向上，各个所述子沟槽的宽度依次增大，至少第1级子沟槽的侧壁具有侧墙保护结构；
    填充所述多级沟槽的第一金属电极，所述第一金属电极还覆盖所述第一表面的功能区，与所述第一表面的功能区具有肖特基接触。
  2. 根据权利要求1所述的肖特基二极管器件，其特征在于，所述侧墙保护结构具有开口，用于露出所述多级沟槽的底部；
    位于所述开口内的欧姆接触结构；
    其中，所述第一金属电极通过所述欧姆接触结构与所述多级沟槽底部的所述第一离子注入区电连接。
  3. 根据权利要求2所述的肖特基二极管器件，其特征在于，所述外延层为SiC层；
    所述欧姆接触结构为基于所述SiC层形成的金属络合物。
  4. 根据权利要求2所述的肖特基二极管器件，其特征在于，在所述第一方向上，所述欧姆接触结构的高度小于所述第1级子沟槽的高度，且小于所述侧墙保护结构的高度。
  5. 根据权利要求1所述的肖特基二极管器件，其特征在于，在所述第一方向上，所述侧墙保护结构的高度不超过所述第1级子沟槽的高度。
  6. 根据权利要求1所述的肖特基二极管器件，其特征在于，所述侧墙保护结构为SiO 2层，或SiN层。
  7. 根据权利要求1所述的肖特基二极管器件，其特征在于，所述外延片包括半导体基底，所述第二表面与所述半导体基底相对设置；
    其中，所述半导体基底背离所述外延层的一侧表面具有第二金属电极。
  8. 根据权利要求1-7任一项所述的肖特基二极管器件，其特征在于，所述第一表面内具有包围所述多级沟槽开口的第二离子注入区，所述第二离子注入区与所述第一离子注入区接触；
    其中，所述第二离子注入区与所述第一离子注入区均是与所述外延层反型掺杂。
  9. 一种肖特基二极管器件的制作方法，其特征在于，包括：
    提供外延片，具有外延层；所述外延层具有相对的第一表面和第二表面；所述第一表面具有功能区以及位于所述功能区两侧的沟槽区；
    在所述沟槽区形成多级沟槽，所述多级沟槽包括：多个子沟槽，所述多个子沟槽在第一方向上，依次为第1级子沟槽至第N级子沟槽，N为大于1的正整数；所述第一方向为所述第二表面指向所述第一表面的方向；同一所述多级沟槽中，在所述第一方向上，各个所述子沟槽的宽度依次增大；
    在所述多级沟槽的侧壁以及底部露出的外延层表面内形成第一离子注入区域；
    至少在第1级子沟槽的侧壁形成侧墙保护结构；
    在所述多级沟槽内形成第一级金属电极，所述第一金属电极还覆盖所述第一表面的功能区，与所述第一表面的功能区具有肖特基接触。
  10. 根据权利要求8所述的制作方法，其特征在于，形成所述侧墙保护结构的方法包括：
    形成绝缘介质层，所述绝缘介质层覆盖所述多级沟槽的侧壁以及底部，且覆盖所述第一表面的功能区；
    在所述绝缘介质层对应所述多级沟槽底部的区域形成开口，以露出所述多级沟槽的部分底部区域；
    去除所述第一表面上的所述绝缘介质层以及所述多级沟槽内的部分所述绝缘介质层，所述多级沟槽内保留的所述绝缘介质层为所述侧墙保护结构。
  11. 根据权利要求10所述的制作方法，其特征在于，在去除所述第一表面上的所述绝缘介质层以及所述多级沟槽内的部分所述绝缘介质层前，还包括：
    在所述开口的底部形成第一金属层；
    基于所述第一金属层，形成所述欧姆接触结构。
PCT/CN2022/131803 2022-05-25 2022-11-15 肖特基二极管器件及其制作方法 Ceased WO2023226320A1 (zh)

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