WO2023226688A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2023226688A1
WO2023226688A1 PCT/CN2023/091472 CN2023091472W WO2023226688A1 WO 2023226688 A1 WO2023226688 A1 WO 2023226688A1 CN 2023091472 W CN2023091472 W CN 2023091472W WO 2023226688 A1 WO2023226688 A1 WO 2023226688A1
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Prior art keywords
layer
conductive layer
conductive
array substrate
gate
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French (fr)
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WO2023226688A8 (zh
Inventor
王明
张大成
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to KR1020247042308A priority Critical patent/KR20250019669A/ko
Priority to JP2024569473A priority patent/JP2025518596A/ja
Priority to EP23810761.9A priority patent/EP4521466A4/en
Publication of WO2023226688A1 publication Critical patent/WO2023226688A1/zh
Anticipated expiration legal-status Critical
Publication of WO2023226688A8 publication Critical patent/WO2023226688A8/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a manufacturing method thereof, and a display device.
  • the array substrate can use a 5-pass mask (can be called 5Mask) process.
  • TFT Thin Film Transistor
  • an array substrate including: a substrate structure; an active layer on the substrate structure; and a pattern on a side of the active layer away from the substrate structure.
  • a first insulating layer having a first through hole exposing a portion of the active layer; a first conductive layer in the first through hole and in contact with the active layer; and A first connector on the side of the first insulating layer away from the substrate structure, the first connector is in contact with the first conductive layer, and the first connector covers the first conductive layer The first part does not cover the second part of the first conductive layer.
  • the first insulating layer further has a second through hole exposing another part of the active layer;
  • the array substrate further includes: a second conductive layer in the second through hole; a second connector electrically connected to the second conductive layer; and a gate located on a side of the first insulating layer away from the active layer; wherein the second connector and the gate are at The same layer, and both the first connection member and the second connection member are isolated from the gate electrode.
  • the substrate structure includes: a substrate; a light-shielding layer and a third conductive layer on the base substrate, and the orthographic projection of the light-shielding layer on the base substrate is consistent with the Orthographic projections of the active layer on the base substrate at least partially overlap, wherein the third conductive layer covers the light shielding layer, or the light shielding layer a layer overlying the third conductive layer; and a buffer layer between the third conductive layer and the active layer.
  • an orthographic projection of the first conductive layer on the base substrate at least partially overlaps an orthographic projection of the light shielding layer on the base substrate.
  • the second through hole also exposes a portion of the buffer layer;
  • the second conductive layer includes: a third portion located on the surface of the active layer and a third portion located on the surface of the buffer layer Part IV above.
  • materials of the first conductive layer, the second conductive layer and the third conductive layer include transparent conductive materials.
  • the thickness of the third conductive layer is greater than the thickness of the second conductive layer, and the thickness of the second conductive layer is equal to the thickness of the first conductive layer.
  • the thickness of the first conductive layer is greater than the thickness of the active layer.
  • the area of the overlapping portion of the first connecting member and the first conductive layer is smaller than the area of the overlapping portion of the second connecting member and the second conductive layer.
  • the first insulating layer includes a gate insulating layer located under the gate;
  • the active layer includes: a first conductive region electrically connected to the first connector, and the The second conductive region electrically connected by the second connecting member and the channel region between the first conductive region and the second conductive region, the channel region and the gate insulating layer The edges are flush.
  • the width of the overlapping portion of the first connection member and the first conductive layer in the direction from the first connection member to the gate is smaller than that between an edge of the first conductive layer and the first conductive layer. The distance between the channel areas.
  • the area of the first conductor layer is larger than the area of the overlapping portion of the first connector and the first conductive layer.
  • the area of the first conductor layer is smaller than the area of the channel region.
  • the width of the overlapping portion of the first conductive layer and the active layer in the direction from the first connection to the gate is smaller than that of the second conductive layer and the active layer. The width of the overlapping portion of the layers in the direction from the first connection to the gate.
  • the distance between the first conductive layer and the gate is greater than the overlapping portion of the first connector and the first conductive layer along the line from the first connector to the gate. and the width of the overlapping portion of the first connector and the first conductive layer in the direction from the first connector to the gate is greater than the width of the second portion of the first conductive layer. The width of the portion in the direction from the first connection to the gate.
  • the array substrate further includes: a second insulating layer covering the first connector, the second connector and the gate; A planarization layer on one side of the base structure; A first electrode layer and a pixel definition layer on the side of the planarization layer away from the substrate structure, the first electrode layer is electrically connected to the second connector, and the pixel definition layer has a structure exposing the A first opening of at least a portion of the first electrode layer; a light-emitting layer located at least in the first opening; and a second electrode layer electrically connected to the light-emitting layer.
  • the overlapping portion between the orthographic projection of the second conductive layer on the base substrate and the orthographic projection of the third conductive layer on the base substrate is along the line from the first
  • the width in the direction from the connecting member to the gate is less than the overlap between the orthographic projection of the second conductive layer on the base substrate and the orthographic projection of the first electrode layer on the base substrate. The width in the direction from the first connection to the gate.
  • the overlapping portion between the orthographic projection of the second conductive layer on the base substrate and the orthographic projection of the third conductive layer on the base substrate is along the line from the first
  • the width in the direction from the connecting member to the gate is less than the overlap between the orthographic projection of the third conductive layer on the base substrate and the orthographic projection of the first electrode layer on the base substrate. The width in the direction from the first connection to the gate.
  • an array substrate including: a substrate structure; and a thin film transistor on the substrate structure, the thin film transistor including: an active layer on the substrate structure ;A patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a portion of the active layer; a first conductive layer in a through hole and in contact with the active layer; and a first connector, a second connector and a gate on a side of the first insulating layer away from the substrate structure, wherein , the first connector is in contact with the first conductive layer, the first connector, the second connector and the gate are on the same layer and isolated from each other, and the gate is located on the third between a connecting member and the second connecting member; wherein the active layer includes: a first conductive area electrically connected to the first connecting member, a second conductive area electrically connected to the second connecting member a conductive region and a channel region between the first conductive region and the second
  • the width of the second portion in a direction from the first connector to the gate is smaller than that of the first portion in a direction from the first connector to the gate. The width in the polar direction.
  • the width of the second portion in a direction from the first connection to the gate is smaller than the width of the channel region in a direction from the first connection to the gate. Width in the direction of the gate.
  • the thickness of the second portion is less than the thickness of the first portion.
  • the width of the first portion is 2 to 5 times the width of the second portion.
  • the active layer further includes a semiconductor region located on a side of the first conductive region away from the channel region; wherein the second portion is disposed along the A width in a direction from the first connecting member to the gate electrode is smaller than a width of the semiconductor region in a direction from the first connecting member to the gate electrode.
  • a display device including: the array substrate as mentioned above.
  • a method for manufacturing an array substrate including: forming an active layer on a substrate structure; forming a patterned third layer on a side of the active layer away from the substrate structure.
  • the layer is patterned to form a first connector in contact with the first conductive layer, the first connector covering a first portion of the first conductive layer and not covering the first
  • the second part of the conductive layer using the mask layer, etching the first insulating layer through a self-alignment process to enlarge the first through hole, wherein the enlarged first through hole exposes
  • FIG. 1 is a schematic cross-sectional view showing an array substrate according to one embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view showing an array substrate according to another embodiment of the present disclosure.
  • Figure 3 is an enlarged schematic diagram schematically showing the array substrate in Figure 1 at block 201;
  • FIG. 4 is a top view schematically showing a partial structure of an array substrate according to one embodiment of the present disclosure
  • FIG. 5 is a flow chart illustrating a method of manufacturing an array substrate according to one embodiment of the present disclosure
  • 6A to 6I are schematic cross-sectional views illustrating structures at several stages in a manufacturing process of an array substrate according to some embodiments of the present disclosure
  • FIG. 7 is a schematic cross-sectional view showing a structure at one stage in the manufacturing process of an array substrate according to another embodiment of the present disclosure.
  • FIG. 8 is a schematic cross-sectional view showing a structure at one stage in the manufacturing process of an array substrate according to another embodiment of the present disclosure
  • 9A to 9C are schematic cross-sectional views illustrating structures at several stages in the manufacturing process of an array substrate according to other embodiments of the present disclosure.
  • 10A to 10C are schematic cross-sectional views illustrating structures at several stages in a manufacturing process of an array substrate according to other embodiments of the present disclosure.
  • a specific device when a specific device is described as being between a first device and a second device, there may or may not be an intervening device between the specific device and the first device or the second device.
  • the specific device When a specific device is described as being connected to another device, the specific device may be directly connected to the other device without an intervening device, or may not be directly connected to the other device but with an intervening device.
  • the inventor of the present disclosure found that in the related art, during the process of forming the TFT of the array substrate, in the overlapping area between the source or drain electrode and the active layer, the active layer was etched twice, which caused There are missing parts of the source layer. This makes the conduction channel in the overlapping area between the source or drain and the active layer very short, which may limit the current flow capability and easily cause poor contact, affecting the performance of the display product.
  • embodiments of the present disclosure provide an array substrate to reduce the possibility of missing portions of the active layer.
  • FIG. 1 is a schematic cross-sectional view showing an array substrate according to one embodiment of the present disclosure.
  • the array substrate includes a substrate structure 110 .
  • the array substrate further includes an active layer 120 on a substrate structure 110 .
  • the material of the active layer includes a semiconductor material such as IGZO (Indium Gallium Zinc Oxide).
  • the array substrate further includes a patterned first insulating layer 130 on a side of the active layer 120 away from the substrate structure.
  • the first insulation layer 130 has a first through hole 141 exposing a portion of the active layer 120 .
  • the first insulation layer 130 covers the active layer 120 .
  • the material of the first insulating layer includes inorganic insulating material (for example, silicon dioxide or silicon nitride, etc.).
  • the array substrate further includes a first conductive layer 151 in the first through hole 141 and in contact with the active layer 120 .
  • the material of the first conductive layer includes a metallic material.
  • the material of the first conductive layer includes transparent conductive material.
  • the transparent conductive material includes: ITO (Indium Tin Oxide, indium tin oxide) or IZO (Indium Zinc Oxide, indium zinc oxide), etc.
  • the first conductive layer uses a transparent conductive material, which can improve the light transmittance of the array substrate.
  • the array substrate further includes a first connection member 161 on a side of the first insulating layer 130 away from the substrate structure 110 .
  • the first connection member 161 is in contact with the first conductive layer 151 .
  • the material of the first connecting member 161 includes metal materials such as copper.
  • the first connection may be a source or a drain.
  • the first connector 161 covers the first part of the first conductive layer 151 and does not cover the second part of the first conductive layer 151 (which will be described later in conjunction with FIG. 3 ).
  • the array substrate includes: a substrate structure; an active layer on the substrate structure; a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a portion exposing the active layer the first through hole; the first conductor in the first through hole and in contact with the active layer electrical layer; and a first connector on a side of the first insulating layer away from the substrate structure, the first connector is in contact with the first conductive layer, the first connector covers the first portion of the first conductive layer and does not cover the first The second part of the conductive layer.
  • the first conductive layer since the first conductive layer is formed in the first through hole of the first insulating layer, the first conductive layer can protect the active layer below it to a certain extent during the manufacturing process. part, thereby reducing the possibility of missing parts of the active layer, thereby improving the performance of the array substrate and the display device formed therefrom.
  • the first insulating layer 130 also has a second through hole 142 exposing another portion of the active layer 120 .
  • the array substrate further includes a second conductive layer 152 in the second through hole 142 .
  • the second conductive layer 152 fills the second through hole 142 .
  • the material of the second conductive layer includes transparent conductive material.
  • the transparent conductive material includes: ITO or IZO, etc.
  • the second conductive layer uses a transparent conductive material, which can improve the light transmittance of the array substrate.
  • the second conductive layer can protect a part of the active layer below it, thereby reducing the possibility of missing parts of the active layer, thereby improving the performance of the array substrate and the display formed by it. Device performance.
  • the width of the overlapping portion of the first conductive layer 151 and the active layer 120 in the direction from the first connection to the gate is smaller than that of the second conductive layer 152 and the active layer 120 .
  • the second conductive layer 152 is made relatively large.
  • the area or width of the second conductive layer 152 ie, the lateral dimension shown in the cross-sectional view
  • the second conductive layer can also act as an electrode plate of the capacitor. This is beneficial to forming a transparent capacitor structure and improving capacitance and conductivity.
  • the array substrate further includes a second connection member 162 electrically connected to the second conductive layer 152 .
  • the second connection member 162 is in contact with the second conductive layer 152 .
  • the second connecting member 162 is made of metal material such as copper.
  • the second connection may be a source or a drain.
  • the first connection member 161 is a source electrode
  • the second connection member 162 is a drain electrode.
  • the first connection member 161 is a drain electrode
  • the second connection member 162 is a source electrode.
  • the array substrate further includes a gate 163 located on a side of the first insulating layer 130 away from the active layer 120 .
  • the material of the gate 163 includes metal materials such as copper.
  • the second connection member 162 and the gate electrode 163 are on the same layer.
  • the first connection member 161 and the gate electrode 163 are also on the same layer. Both the first connection member 161 and the second connection member 162 are isolated from the gate electrode 163 .
  • the gate 163 is located between the first connecting member 161 and the second connecting member 162 .
  • the same layer refers to the film layer used to form a specific pattern formed using the same film forming process.
  • the same mask is then used to pattern the film layer through a patterning process to form a layer structure.
  • two structural layers in the same layer may be located on the same structural layer, or may be located on different structural layers.
  • Two structural layers on the same layer may be at different heights or have different thicknesses.
  • substrate structure 110 includes substrate substrate 111 .
  • the base substrate includes a rigid substrate or a flexible substrate.
  • the base substrate may include a glass substrate or the like.
  • the substrate structure 110 further includes a light-shielding layer 112 on the substrate substrate 111 .
  • the orthographic projection of the light shielding layer 112 on the base substrate 111 and the orthographic projection of the active layer 120 on the base substrate 111 at least partially overlap.
  • the material of the light shielding layer includes metal materials such as aluminum, molybdenum or copper.
  • the substrate structure 110 further includes a third conductive layer 113 covering the light-shielding layer 112 .
  • the third conductive layer may extend from the light shielding layer 112 to the base substrate 111 .
  • the third conductive layer 113 can serve as another electrode plate of the capacitor.
  • the positions of the light-shielding layer 112 and the third conductive layer 113 can be interchanged.
  • the third conductive layer 113 may be located on the base substrate 111, and the light-shielding layer 112 is located on a side of the third conductive layer 113 away from the base substrate, that is, the light-shielding layer covers the third conductive layer.
  • the material of the third conductive layer 113 includes transparent conductive material.
  • the transparent conductive material includes: ITO or IZO, etc.
  • the third conductive layer uses a transparent conductive material, which can improve the light transmittance of the array substrate.
  • the substrate structure 110 further includes a buffer layer 114 between the third conductive layer 113 and the active layer 120 .
  • the buffer layer may include an inorganic insulating material such as silicon dioxide.
  • the buffer layer 114 covers the third conductive layer 113 and the base substrate 111 and so on.
  • the base substrate 110 may further include traces 115 .
  • the first connection member 161 may be electrically connected to the trace 115 through a third via hole (as a conductive via hole) 143 passing through the first insulation layer 130 and the buffer layer 114 .
  • the wiring 115 may be on the same layer as the light shielding layer 112 .
  • the material of the wiring 115 is the same as the material of the light-shielding layer 112 .
  • the trace 115 is isolated from the light shielding layer 112 .
  • the orthographic projection of the first conductive layer 151 on the base substrate 111 and the orthographic projection of the light shielding layer 112 on the base substrate 111 at least partially overlap.
  • the light-shielding layer can play a role in shading light.
  • the thickness of the third conductive layer 113 is greater than the thickness of the second conductive layer 152 .
  • the thickness of the second conductive layer 152 is equal to the thickness of the first conductive layer 151 . This makes the second conductive layer relatively thin, thereby further improving the light transmittance of the array substrate.
  • the thickness of the third conductive layer 113 is relatively thick, which can reduce resistance.
  • the thickness of the third conductive layer 113 is 3000 angstroms to 5000 angstroms.
  • second conductive layer 152 (or The first conductive layer 151) has a thickness of 500 angstroms to 1000 angstroms.
  • the thickness of the first conductive layer 151 is greater than the thickness of the active layer 120 .
  • the thickness of active layer 120 is 300 angstroms to 500 angstroms.
  • the area of the overlapping portion of the first connecting member 161 and the first conductive layer 151 is smaller than the area of the overlapping portion of the second connecting member 162 and the second conductive layer 151 .
  • the area of the overlapping portion of the second connecting member and the second conductive layer is relatively large, which can reduce contact resistance.
  • the first insulating layer 130 includes a gate insulating layer 131 located under the gate 163 .
  • the active layer 120 includes: a first conductive region 121 electrically connected to the first connector 161 , a second conductive region 122 electrically connected to the second connector 162 , and a second conductive region 122 electrically connected to the second connector 162 .
  • the channel region 123 is flush with the edge of the gate insulating layer 131 .
  • the first conductive layer 151 is in contact with the first conductorized region 121
  • the second conductive layer 152 is in contact with the second conductorized region 122 .
  • the contact resistance between the first conductive layer and the active layer and the contact resistance between the second conductive layer and the active layer can be reduced to facilitate the transmission of current. , improve the performance of the array substrate and the display device formed therefrom.
  • FIG. 3 is an enlarged schematic diagram schematically showing the array substrate in FIG. 1 at block 201 .
  • the first conductive layer 151 includes a first portion 1511 away from the gate electrode 163 and a second portion 1512 close to the gate electrode 163 .
  • the first part 1511 is completely covered by the first connecting member 161
  • the second part 1512 is not covered by the first connecting member 161 .
  • the width d1 of the overlapping portion of the first connection member 161 and the first conductive layer 151 in the direction from the first connection member 161 to the gate 163 is smaller than the width d1 of the first conductive layer 151 .
  • the area of the first conductor layer 151 is larger than the area of the overlapping portion of the first connector 161 and the first conductive layer 151 (ie, the portion corresponding to the width d1). This is beneficial to the full contact between the first connecting member and the first conductive layer and prevents the problem of poor contact.
  • the area of the first conductor layer 151 is smaller than the area of the channel region 123 .
  • the area of the channel region is relatively large, which is beneficial to improving the performance of the thin film transistor.
  • the “area” mentioned in this disclosure refers to the area of the surface of the structural layer that is parallel to the plane of the base substrate.
  • the area may be the area of the upper surface of the structural layer.
  • the area of the upper surface of the first conductor layer 151 is the area of the first conductor layer 151; the area of the upper surface of the channel region 123 is the channel region. area of domain 123, etc.
  • the distance d3 between the first conductive layer 151 and the gate 163 is greater than the overlapping portion of the first connection 161 and the first conductive layer 151 in the direction from the first connection to the gate. and the width d1 of the overlapping portion of the first connection member 161 and the first conductive layer 151 in the direction from the first connection member to the gate is greater than the second portion of the first conductive layer 151 (i.e., The width d2 of the portion (not covered by the first connector 161) 1512 in the direction from the first connector 161 to the gate. That is, d3>d1>d2.
  • Such size design is conducive to improving the performance of the thin film transistor, thereby improving the performance of the array substrate and the display device formed therefrom.
  • a gap 301 exists between the first conductive layer 151 and the gate insulating layer 131 .
  • the array substrate further includes a second insulation layer 171 covering the first connection member 161 , the second connection member 162 and the gate electrode 163 .
  • the material of the second insulating layer 171 includes at least one of silicon dioxide or silicon nitride.
  • the array substrate further includes a planarization layer 172 on a side of the second insulating layer 171 away from the substrate structure 110 .
  • the material of the planarization layer includes organic insulating materials such as resin.
  • the array substrate further includes a first electrode layer 181 and a pixel defining layer 174 on a side of the planarization layer 172 away from the substrate structure 110 .
  • the first electrode layer 181 is electrically connected to the second connection member 162 (for example, through a conductive via).
  • the pixel defining layer 174 has a first opening 1742 exposing at least a portion of the first electrode layer 181 .
  • the first electrode layer is an anode layer.
  • the material of the first electrode layer 181 includes metal such as copper, silver, aluminum or aluminum alloy, or transparent conductive material such as ITO or IZO.
  • the array substrate further includes a light-emitting layer 180 located at least in the first opening 1742 .
  • the luminescent layer may include a luminescent layer for emitting red light, a luminescent layer for emitting green light, or a luminescent layer for emitting blue light.
  • the array substrate further includes a second electrode layer 182 electrically connected to the light-emitting layer 180 .
  • the second electrode layer 182 covers the pixel defining layer 174 and the light emitting layer 180 .
  • the second electrode layer may be a cathode layer.
  • the material of the second electrode layer 182 includes metal such as copper, silver, aluminum or aluminum alloy, or transparent conductive material such as ITO or IZO.
  • the array substrate may also include other functional layers between the first electrode layer 181 and the second electrode layer 182, such as an electron transport layer, a hole transport layer, an electron blocking layer or a hole blocking layer. ,etc. Therefore, the scope of the present disclosure is not limited thereto.
  • the overlapping portion between the orthographic projection of the second conductive layer 152 on the base substrate 111 and the orthographic projection of the third conductive layer 113 on the base substrate 111 is along the line from First connection to gate
  • the width in the direction is less than the overlapping portion between the orthographic projection of the second conductive layer 152 on the base substrate 111 and the orthographic projection of the first electrode layer 181 on the base substrate 111 along the line from the first connector to Width in the direction of the gate. This is beneficial to improving the light transmittance of the array substrate.
  • the overlapping portion between the orthographic projection of the second conductive layer 152 on the base substrate 111 and the orthographic projection of the third conductive layer 113 on the base substrate 111 is along the line from
  • the width in the direction from the first connector to the gate is less than the overlap portion between the orthographic projection of the third conductive layer 113 on the base substrate 111 and the orthographic projection of the first electrode layer 181 on the base substrate 111 along the edge.
  • the width in the direction from the first connecting member to the gate electrode is beneficial to improving the light transmittance of the array substrate.
  • the present disclosure provides an array substrate.
  • the array substrate includes: a substrate structure 110 and a thin film transistor on the substrate structure 110 .
  • the thin film transistor includes an active layer 120 on a substrate structure 110 .
  • the thin film transistor further includes a patterned first insulating layer 130 on a side of the active layer 120 remote from the substrate structure.
  • the first insulating layer 130 has a first through hole 141 exposing a portion of the active layer 120 .
  • the thin film transistor also includes a first conductive layer 151 in the first through hole 141 and in contact with the active layer 120 .
  • the thin film transistor further includes a first connection member 161, a second connection member 162 and a gate electrode 163 on a side of the first insulation layer 130 away from the substrate structure.
  • the first connection member 161 is in contact with the first conductive layer 151 .
  • the first connection member 161, the second connection member 162 and the gate electrode 163 are on the same layer and are isolated from each other.
  • the gate 163 is located between the first connection member 161 and the second connection member 162 .
  • the active layer 120 includes: a first conductive region 121 electrically connected to the first connector 161 , a second conductorized region 122 electrically connected to the second connector 162 , and a first conductor region 122 electrically connected to the second connector 162 .
  • Channel region 123 is below gate 163 .
  • the first conductive layer 151 includes a first portion 1511 away from the gate electrode 163 and a second portion 1512 close to the gate electrode 163 .
  • the first part 1511 is completely covered by the first connecting member 161
  • the second part 1512 is not covered by the first connecting member 161 .
  • the orthographic projection of the first conductive layer 151 on the substrate structure 110 is located inside the orthographic projection of the active layer 120 on the substrate structure 110 .
  • the first conductive layer since the first conductive layer is formed in the first through hole of the first insulating layer, the first conductive layer can protect the active layer below it to a certain extent during the manufacturing process. part, thereby reducing the possibility of missing parts of the active layer, thereby improving the performance of the array substrate and the display device formed therefrom.
  • the width d2 of the second portion 1512 in the direction from the first connector to the gate is smaller than the width d2 of the first portion 1511 in the direction from the first connector to the gate.
  • the width of the first portion 1511 is equal to the width of the overlapping portion of the first connecting member 161 and the first conductive layer 151. etc., both are d1.
  • the width d1 of the first portion 1511 is 2 to 5 times the width d2 of the second portion 1512 .
  • the width d2 of the second portion 1512 in the direction from the first connection to the gate is smaller than the width d2 of the channel region 123 in the direction from the first connection to the gate. Width in direction d5.
  • the thickness H2 of the second portion 1512 is less than the thickness H1 of the first portion 1511 .
  • the active layer 120 may further include a semiconductor region (which may be referred to as a first semiconductor region) 124 .
  • the semiconductor region 124 is located on a side of the first conductive region 121 remote from the channel region 123 .
  • the width d2 of the second portion 1512 in the direction from the first connection to the gate is smaller than the width d6 of the semiconductor region 124 in the direction from the first connection to the gate.
  • the active layer may further include another semiconductor region, which may be called a second semiconductor region (not shown in the figure).
  • the second semiconductor region is located on a side of the second conductive region 122 away from the channel region 123 .
  • FIG. 2 is a schematic cross-sectional view showing an array substrate according to another embodiment of the present disclosure.
  • the structure of the array substrate shown in FIG. 2 is similar to the structure of the array substrate shown in FIG. 1 . What is different from the structure of the array substrate shown in FIG. 1 is that in the array substrate shown in FIG. 2 , the second through hole 142 also exposes a part of the buffer layer 114 , and the second conductive layer 152 includes: located on the active layer 120 A third portion 1521 on the surface and a fourth portion 1522 on the surface of the buffer layer 114 .
  • the lateral dimensions of the active layer 120 are smaller than those of the active layer in FIG. 1
  • the area of the third portion of the second conductive layer 152 is smaller than that of the second conductive layer in FIG. 1
  • the area of overlap with the active layer Therefore, in the array substrate shown in FIG. 2 , the area of the overlapping portion of the second conductive layer and the active layer is reduced, which can improve the light transmittance of the array substrate.
  • FIG. 4 is a top view schematically showing a partial structure of an array substrate according to one embodiment of the present disclosure.
  • the first conductive area 121, the first conductive layer 151 and the first connection member 161 of the active layer of the array substrate are shown in FIG. 4 .
  • the first conductive layer 151 due to the existence of the first conductive layer 151 , there is no missing portion in the first conductive region 121 . Therefore, current can flow from the first connector through the first conductive region 121 relatively uniformly, providing an array. The signal transmission capability of the substrate.
  • a display device including the array substrate as described above, for example, the array substrate shown in FIG. 1 or FIG. 2 .
  • the display device can be: a display panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • FIG. 5 is a flowchart illustrating a manufacturing method of an array substrate according to one embodiment of the present disclosure. As shown in Figure 5, the manufacturing method includes steps S502 to S508.
  • 6A to 6I are schematic cross-sectional views illustrating structures at several stages in a manufacturing process of an array substrate according to some embodiments of the present disclosure.
  • 9A to 9C are schematic cross-sectional views illustrating structures at several stages in a manufacturing process of an array substrate according to other embodiments of the present disclosure. The manufacturing process of the array substrate according to some embodiments of the present disclosure is described in detail below with reference to FIGS. 5 , 6A to 6I and 9A to 9C .
  • step S502 an active layer is formed on the substrate structure.
  • the active layer 120 is formed on the substrate structure 110 by, for example, a deposition process.
  • the specific structure of the substrate structure 110 has been described in detail before and will not be described again here.
  • a patterned first insulating layer is formed on a side of the active layer away from the substrate structure, and the first insulating layer has a first through hole exposing a portion of the active layer.
  • the process of forming the patterned first insulating layer may be described in detail with reference to FIGS. 6A to 6F .
  • a first insulating layer 130 is formed on a side of the active layer 120 away from the substrate structure 110 .
  • a first mask layer 610 is formed on the side of the first insulating layer 130 away from the substrate structure 110 .
  • the material of the first mask layer is positive photoresist.
  • the first mask layer 610 is patterned using the patterned first mask plate 621 to form the patterned first mask layer 610 , for example, through exposure and development techniques,
  • the patterned first mask layer is caused to have a second opening 6102 exposing a portion of the first insulating layer 130 .
  • the patterned first mask layer 610 is used to remove the portion of the first insulating layer 130 exposed by the second opening 6102 through an etching process (eg, dry etching). A portion of the first through hole 141 is formed, thereby forming the patterned first insulating layer 130 . The first through hole 141 exposes a portion of the active layer 120 .
  • an etching process eg, dry etching
  • step S506 a first conductorization process is performed on the exposed portion of the active layer.
  • a first conductorization process may be performed on the exposed portion of the active layer 120 .
  • a dry etching process may be used and He gas (helium gas) may be used to perform the first conductorization process.
  • He gas helium gas
  • the first mask layer 610 is removed.
  • step S508 a first conductive layer in contact with the active layer is formed in the first through hole.
  • the process of forming the first conductive layer may be described in detail with reference to FIGS. 6G to 6I.
  • the patterned first insulating layer 130 is formed away from the substrate structure through a deposition process. 110 side and a first conductive layer 151 is formed in the first through hole 141 .
  • the material of the first conductive layer 151 includes transparent conductive material.
  • a second mask layer 612 is formed on the side of the first conductive layer 151 away from the substrate structure 110 , and the second mask layer 612 is processed using the first mask plate 621 described above. Exposure and development processes are performed to form the structure of the second mask layer 612 shown in FIG. 6H.
  • the material of the second mask layer is negative photoresist.
  • the first conductive layer 151 is etched to remove the portion of the first conductive layer 151 that is not blocked by the second mask layer 612 and to retain the portion of the first conductive layer 151 that is blocked by the second mask layer 612 .
  • the portion blocked by the mask layer 612 forms a structure as shown in FIG. 6I .
  • the patterned first conductive layer 151 is formed, and the first conductive layer 151 can protect the underlying active layer 120 from being etched as much as possible.
  • a connection material layer is formed on the side of the first insulating layer away from the substrate structure through a deposition process.
  • connection material layer 160 is formed on a side of the first insulating layer 130 away from the substrate structure 110 through a deposition process.
  • the material of the connection material layer 160 includes metal such as copper.
  • connection material layer is patterned using the patterned mask layer to form a first connection member, the first connection member is in contact with the first conductive layer, and the first connection member covers the first A first portion of the conductive layer and a second portion not covering the first conductive layer.
  • a patterned mask layer (which may be called a third mask layer) 637 is formed on a side of the connection material layer away from the substrate structure 110 .
  • the material of the third mask layer is photoresist.
  • connection material layer 160 is patterned using the third mask layer 637 to form the first connection member 161 .
  • the second connection member 162 and the gate electrode 163 may also be formed during this process.
  • the etching liquid may etch a part of the connecting material layer under the edge of the third mask layer, so that the formed first connecting member is recessed inward.
  • step S514 the mask layer is used to etch the first insulating layer through a self-alignment process to enlarge the first through hole, wherein the enlarged first through hole exposes another part of the active layer.
  • the first insulating layer 130 is etched through a self-alignment process using a patterned mask layer (ie, the third mask layer) 637 to enlarge the first through hole 141 , where the enlarged The rear first through hole 141 is exposed Another part of the active layer 120 comes out.
  • this etching is dry etching.
  • the entire surface of the first insulating layer is etched to form a gap between the first conductive layer and the gate insulating layer, that is, the aforementioned gap 301.
  • step S516 the other exposed portion of the active layer is subjected to a second conductorization process.
  • the other exposed portion of the active layer 120 is subjected to a second conductorization process.
  • a dry etching process may be employed and He gas (helium gas) may be used to perform the second conductorization process.
  • He gas helium gas
  • the manufacturing method includes: forming an active layer on a substrate structure; forming a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a portion of the active layer ; Performing a first conductorization process on the exposed portion of the active layer; forming a first conductive layer in contact with the active layer in the first through hole; forming the first insulating layer on a side away from the substrate structure through a deposition process Connecting the material layer; patterning the connecting material layer using a patterned mask layer to form a first connecting member, the first connecting member is in contact with the first conductive layer, the first connecting member covers the first portion of the first conductive layer and The second part of the first conductive layer is not covered; using the mask layer, the first insulating layer is etched through a self-alignment process to enlarge the first through hole, wherein the enlarged first through
  • the second mask layer uses negative photoresist, so that the first mask plate mentioned above can be used for exposure and development, without the need to manufacture an additional mask plate, thereby reducing the process complexity. .
  • FIG. 7 is a schematic cross-sectional view showing a structure at one stage in the manufacturing process of an array substrate according to another embodiment of the present disclosure.
  • FIG. 7 shows a schematic cross-sectional view of the structure at one stage in the process of forming the first conductive layer according to other embodiments.
  • a first layer is formed on the patterned first mask layer 610 and in the first through hole 141 of the first insulation layer 130 through a deposition process.
  • Conductive layer 151 is formed on the patterned first mask layer 610 and in the first through hole 141 of the first insulation layer 130 through a deposition process.
  • first mask layer 610 and the portion of the first conductive layer 151 on the first mask layer 610 are removed through an off-ground lift-off process, leaving the portion of the first conductive layer 151 in the first through hole 141, This results in a structure as shown in Figure 6I.
  • an off-the-ground lift-off process is used, which eliminates the need to add additional mask processes and further reduces process complexity.
  • FIG. 8 is a schematic cross-sectional view showing a structure at one stage in the manufacturing process of an array substrate according to another embodiment of the present disclosure.
  • FIG. 8 shows a schematic cross-sectional view of the structure at one stage in the process of forming the first conductive layer according to other embodiments.
  • a patterned second mask 630 and an evaporation process are used to form a first conductive layer in the first through hole 141 of the first insulating layer 130 .
  • Layer 151 forms the structure shown in Figure 6I.
  • the second mask 630 has a through hole (which may be called a fourth through hole), and the opening is aligned with the first through hole 141 .
  • the second mask is an FMM mask (Fine Metal Mask).
  • an evaporation source 635 is shown in FIG. 8 .
  • the material of the evaporation source includes transparent conductive materials (such as ITO or IZO, etc.).
  • an evaporation process is used to form the first conductive layer, which can reduce process complexity.
  • FIGS. 10A to 10C are schematic cross-sectional views illustrating structures at several stages in a manufacturing process of an array substrate according to other embodiments of the present disclosure.
  • the manufacturing process of the array substrate according to other embodiments of the present disclosure is described in detail below with reference to FIGS. 10A to 10C and FIG. 1 .
  • a substrate structure is provided.
  • the step of providing a substrate structure includes the following steps.
  • the light-shielding layer 112 is formed on the base substrate 111 through a deposition and patterning process. Additionally, traces 115 are formed.
  • a third conductive layer 113 covering the light shielding layer 112 is formed through a deposition and patterning process.
  • the third conductive layer 113 may first be formed on the base substrate 111 through a deposition and patterning process; and then, the light-shielding layer 112 may be formed on the third conductive layer 113 through a deposition and patterning process.
  • a buffer layer 114 covering the third conductive layer 113 is formed through a deposition process.
  • the substrate structure 110 is formed.
  • the active layer 120 , the first insulating layer 130 , the first through hole 141 , the first conductive layer 151 and the first connector 161 are formed using the previously described process.
  • the second through hole 142, the third through hole 143, the second conductive layer 152, the second connection member 162 and the gate electrode 163 are also formed.
  • the second conductive layer 152 is formed using the same process as the first conductive layer 151 , and the second connector 162 and the gate 163 are formed using the same patterning process as the first connector 161 . I won’t go into details here.
  • first through hole 141 is formed
  • second through hole 142 and the third through hole 143 may also be formed.
  • the formation process of the second through hole 142 and the third through hole 143 is similar to the formation process of the first through hole 141 and will not be described again here.
  • a second insulating layer 171 covering the first connector 161 , the second connector 162 and the gate electrode 163 is formed through a deposition process.
  • a planarization layer 172 is formed on the side of the second insulating layer 171 away from the substrate structure 110 .
  • a first electrode layer 181 electrically connected to the second connector 162 is formed on the side of the planarization layer 172 away from the substrate structure 110 .
  • a pixel definition layer 174 is formed on the side of the planarization layer 172 away from the substrate structure 110 .
  • the pixel defining layer 174 has a first opening 1742 exposing at least a portion of the first electrode layer 181 .
  • the light emitting layer 180 located at least in the first opening 1742 is formed.
  • a second electrode layer 182 electrically connected to the light-emitting layer 180 is formed through a deposition process.
  • a manufacturing method of an array substrate according to some embodiments of the present disclosure is provided. This manufacturing method can reduce the possibility of missing parts of the active layer, thereby improving the performance of the array substrate and the display device formed therefrom.

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Abstract

本公开提供了一种阵列基板及其制造方法、显示装置。阵列基板包括：衬底结构；在衬底结构上的有源层；在有源层的远离衬底结构一侧的图案化的第一绝缘层，第一绝缘层具有露出有源层的一部分的第一通孔；在第一通孔中且与有源层接触的第一导电层；和在第一绝缘层的远离衬底结构一侧的第一连接件，第一连接件与第一导电层接触，第一连接件覆盖第一导电层的第一部分且未覆盖第一导电层的第二部分。本公开可以减小有源层出现缺失部分的可能性，进而提高阵列基板及由其所形成的显示装置的性能。

Description

阵列基板及其制造方法、显示装置
相关申请的交叉引用
本申请是以CN申请号为202210590935.4，申请日为2022年5月27日的申请为基础，并主张其优先权，该CN申请的公开内容在此作为整体引入本申请中。
技术领域
本公开涉及显示技术领域，特别涉及一种阵列基板及其制造方法、显示装置。
背景技术
目前，OLED(Organic Light-Emitting Diode，有机发光二极管)技术越来越成熟。在某些OLED显示面板中，阵列基板可以采用5次掩模(可以称为5Mask)工艺。在制造阵列基板的过程中，需要制造TFT(Thin Film Transistor，薄膜晶体管)晶体管。
发明内容
根据本公开的一个方面，提供了一种阵列基板，包括：衬底结构；在所述衬底结构上的有源层；在所述有源层的远离所述衬底结构一侧的图案化的第一绝缘层，所述第一绝缘层具有露出所述有源层的一部分的第一通孔；在所述第一通孔中且与所述有源层接触的第一导电层；和在所述第一绝缘层的远离所述衬底结构一侧的第一连接件，所述第一连接件与所述第一导电层接触，所述第一连接件覆盖所述第一导电层的第一部分且未覆盖所述第一导电层的第二部分。
在一些实施例中，所述第一绝缘层还具有露出所述有源层的另一部分的第二通孔；所述阵列基板还包括：在所述第二通孔中的第二导电层；与所述第二导电层电连接的第二连接件；和位于所述第一绝缘层的远离所述有源层一侧的栅极；其中，所述第二连接件与所述栅极处于同一层，且所述第一连接件和所述第二连接件均与所述栅极隔离开。
在一些实施例中，所述衬底结构包括：衬底基板；在所述衬底基板上的遮光层和第三导电层，所述遮光层在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影至少部分重叠，其中，所述第三导电层覆盖在所述遮光层上，或者所述遮光 层覆盖在所述第三导电层上；和在所述第三导电层与所述有源层之间的缓冲层。
在一些实施例中，所述第一导电层在所述衬底基板上的正投影与所述遮光层在所述衬底基板上的正投影至少部分重叠。
在一些实施例中，所述第二通孔还露出所述缓冲层的一部分；所述第二导电层包括：位于所述有源层的表面上的第三部分和位于所述缓冲层的表面上的第四部分。
在一些实施例中，所述第一导电层、所述第二导电层和所述第三导电层的材料均包括透明导电材料。
在一些实施例中，所述第三导电层的厚度大于所述第二导电层的厚度，且所述第二导电层的厚度与所述第一导电层的厚度相等。
在一些实施例中，所述第一导电层的厚度大于所述有源层的厚度。
在一些实施例中，所述第一连接件与所述第一导电层的交叠部分的面积小于所述第二连接件与所述第二导电层的交叠部分的面积。
在一些实施例中，所述第一绝缘层包括位于所述栅极下方的栅极绝缘层；所述有源层包括：与所述第一连接件电连接的第一导体化区域、与所述第二连接件电连接的第二导体化区域和在所述第一导电化区域与所述第二导体化区域之间的沟道区域，所述沟道区域与所述栅极绝缘层的边缘齐平。
在一些实施例中，所述第一连接件与所述第一导电层的交叠部分在沿着从第一连接件至栅极的方向上的宽度小于所述第一导电层的边缘与所述沟道区域之间的距离。
在一些实施例中，所述第一导体层的面积大于所述第一连接件与所述第一导电层的交叠部分的面积。
在一些实施例中，所述第一导体层的面积小于所述沟道区域的面积。
在一些实施例中，所述第一导电层与所述有源层的交叠部分在沿着从第一连接件至栅极的方向上的宽度小于所述第二导电层与所述有源层的交叠部分在沿着从第一连接件至栅极的方向上的宽度。
在一些实施例中，所述第一导电层与所述栅极之间的距离大于所述第一连接件与所述第一导电层的交叠部分在沿着从第一连接件至栅极的方向上的宽度，且所述第一连接件与所述第一导电层的交叠部分在沿着从第一连接件至栅极的方向上的宽度大于所述第一导电层的第二部分在沿着从第一连接件至栅极的方向上的宽度。
在一些实施例中，所述阵列基板还包括：覆盖所述第一连接件、所述第二连接件和所述栅极的第二绝缘层；在所述第二绝缘层的远离所述衬底结构一侧的平坦化层； 在所述平坦化层的远离所述衬底结构一侧的第一电极层和像素界定层，所述第一电极层电连接至所述第二连接件，所述像素界定层具有露出所述第一电极层的至少一部分的第一开口；至少位于所述第一开口中的发光层；和与所述发光层电连接的第二电极层。
在一些实施例中，所述第二导电层在所述衬底基板上的正投影与所述第三导电层在所述衬底基板上的正投影之间的重叠部分在沿着从第一连接件至栅极的方向上的宽度，小于所述第二导电层在所述衬底基板上的正投影与所述第一电极层在所述衬底基板上的正投影之间的重叠部分在沿着从第一连接件至栅极的方向上的宽度。
在一些实施例中，所述第二导电层在所述衬底基板上的正投影与所述第三导电层在所述衬底基板上的正投影之间的重叠部分在沿着从第一连接件至栅极的方向上的宽度，小于所述第三导电层在所述衬底基板上的正投影与所述第一电极层在所述衬底基板上的正投影之间的重叠部分在沿着从第一连接件至栅极的方向上的宽度。
根据本公开的另一个方面，提供了一种阵列基板，包括：衬底结构；和在所述衬底结构上的薄膜晶体管，所述薄膜晶体管包括：在所述衬底结构上的有源层；在所述有源层的远离所述衬底结构一侧的图案化的第一绝缘层，所述第一绝缘层具有露出所述有源层的一部分的第一通孔；在所述第一通孔中且与所述有源层接触的第一导电层；和在所述第一绝缘层的远离所述衬底结构一侧的第一连接件、第二连接件和栅极，其中，所述第一连接件与所述第一导电层接触，所述第一连接件、所述第二连接件和所述栅极处于同一层且互相隔离开，所述栅极位于所述第一连接件与所述第二连接件之间；其中，所述有源层包括：与所述第一连接件电连接的第一导体化区域、与所述第二连接件电连接的第二导体化区域和在所述第一导电化区域与所述第二导体化区域之间的沟道区域，所述沟道区域在所述栅极的下方；所述第一导电层包括远离所述栅极的第一部分和靠近所述栅极的第二部分，所述第一部分被所述第一连接件完全覆盖，所述第二部分未被所述第一连接件覆盖，所述第一导电层在所述衬底结构上的正投影位于所述有源层在所述衬底结构上的正投影的内部。
在一些实施例中，所述第二部分在沿着从所述第一连接件至所述栅极的方向上的宽度小于所述第一部分在沿着从所述第一连接件至所述栅极的方向上的宽度。
在一些实施例中，所述第二部分在沿着从所述第一连接件至所述栅极的方向上的宽度小于所述沟道区域在沿着从所述第一连接件至所述栅极的方向上的宽度。
在一些实施例中，所述第二部分的厚度小于所述第一部分的厚度。
在一些实施例中，所述第一部分的宽度是所述第二部分的宽度的2至5倍。
在一些实施例中，所述有源层还包括半导体区域，所述半导体区域位于所述第一导体化区域的远离所述沟道区域的一侧；其中，所述第二部分在沿着从所述第一连接件至所述栅极的方向上的宽度小于所述半导体区域在沿着从所述第一连接件至所述栅极的方向上的宽度。
根据本公开的另一个方面，提供了一种显示装置，包括：如前所述的阵列基板。
根据本公开的另一个方面，提供了一种阵列基板的制造方法，包括：在衬底结构上形成有源层；在所述有源层的远离所述衬底结构一侧形成图案化的第一绝缘层，所述第一绝缘层具有露出所述有源层的一部分的第一通孔；对所述有源层被露出的所述一部分执行第一导体化处理；在所述第一通孔中形成与所述有源层接触的第一导电层；通过沉积工艺在所述第一绝缘层的远离衬底结构一侧形成连接材料层；利用图案化的掩模层对所述连接材料层进行图案化，以形成第一连接件，所述第一连接件与所述第一导电层接触，所述第一连接件覆盖所述第一导电层的第一部分且未覆盖所述第一导电层的第二部分；利用所述掩模层，通过自对准工艺对所述第一绝缘层进行刻蚀以扩大所述第一通孔，其中，扩大后的第一通孔露出所述有源层的另一部分；和对所述有源层的被露出的所述另一部分进行第二导体化处理。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1是示出根据本公开一个实施例的阵列基板的截面示意图；
图2是示出根据本公开另一个实施例的阵列基板的截面示意图；
图3是示意性地示出图1中的阵列基板在方框201处的放大示意图；
图4是示意性地示出根据本公开一个实施例的阵列基板的部分结构的俯视图；
图5是示出根据本公开一个实施例的阵列基板的制造方法的流程图；
图6A至图6I是示出根据本公开一些实施例的阵列基板的制造过程中若干阶段的结构的截面示意图；
图7是示出根据本公开另一个实施例的阵列基板的制造过程中一个阶段的结构的截面示意图；
图8是示出根据本公开另一个实施例的阵列基板的制造过程中一个阶段的结构的截面示意图；
图9A至图9C是示出根据本公开另一些实施例的阵列基板的制造过程中若干阶段的结构的截面示意图；
图10A至图10C是示出根据本公开另一些实施例的阵列基板的制造过程中若干阶段的结构的截面示意图。
应当明白，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分、数字表达式和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定器件位于第一器件和第二器件之间时，在该特定器件与第一器件或第二器件之间可以存在居间器件，也可以不存在居间器件。当描述到特定器件连接其它器件时，该特定器件可以与所述其它器件直接连接而不具有居间器件，也可以不与所述其它器件直接连接而具有居间器件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应 用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
本公开的发明人发现，在相关技术中，在形成阵列基板的TFT的过程中，在源极或漏极与有源层的搭接区域，由于有源层受到2次刻蚀，这造成有源层出现缺失部分。这使得源极或漏极与有源层的搭接区域的导通通道很短，可能会限制电流流过能力，容易发生接触不良，影响显示产品的性能。
鉴于此，本公开的实施例提供一种阵列基板，以减小有源层出现缺失部分的可能性。
图1是示出根据本公开一个实施例的阵列基板的截面示意图。
如图1所示，阵列基板包括衬底结构110。
如图1所示，该阵列基板包括还包括在衬底结构110上的有源层120。例如，该有源层的材料包括诸如IGZO(氧化铟镓锌)等的半导体材料。
如图1所示，该阵列基板还包括在有源层120的远离衬底结构一侧的图案化的第一绝缘层130。第一绝缘层130具有露出有源层120的一部分的第一通孔141。该第一绝缘层130覆盖有源层120。例如，该第一绝缘层的材料包括无机绝缘材料(例如，二氧化硅或氮化硅等)。
如图1所示，该阵列基板还包括在第一通孔141中且与有源层120接触的第一导电层151。在一些实施例中，该第一导电层的材料包括金属材料。例如，该第一导电层的材料包括透明导电材料。例如，该透明导电材料包括：ITO(Indium Tin Oxide，氧化铟锡)或IZO(Indium Zinc Oxide，氧化铟锌)等。这里，第一导电层采用透明导电材料，可以提高阵列基板的透光率。
如图1所示，该阵列基板还包括在第一绝缘层130的远离衬底结构110一侧的第一连接件161。该第一连接件161与第一导电层151接触。该第一连接件161的材料包括诸如铜等金属材料。例如，该第一连接件可以为源极或漏极。该第一连接件161覆盖第一导电层151的第一部分且未覆盖第一导电层151的第二部分(后面将结合图3描述)。
至此，提供了根据本公开一些实施例的阵列基板。该阵列基板包括：衬底结构；在衬底结构上的有源层；在有源层的远离衬底结构一侧的图案化的第一绝缘层，第一绝缘层具有露出有源层的一部分的第一通孔；在第一通孔中且与有源层接触的第一导 电层；和在第一绝缘层的远离衬底结构一侧的第一连接件，第一连接件与第一导电层接触，第一连接件覆盖第一导电层的第一部分且未覆盖第一导电层的第二部分。在该实施例中，由于在第一绝缘层的第一通孔中形成有第一导电层，这样在制造过程中，该第一导电层可以在一定程度上保护在其下面的有源层的一部分，从而减小有源层出现缺失部分的可能性，进而提高阵列基板及由其所形成的显示装置的性能。
如图1所示，第一绝缘层130还具有露出有源层120的另一部分的第二通孔142。
在一些实施例中，如1所示，阵列基板还包括在第二通孔142中的第二导电层152。该第二导电层152填充该第二通孔142。例如，该第二导电层的材料包括透明导电材料。例如，该透明导电材料包括：ITO或IZO等。这里，第二导电层采用透明导电材料，可以提高阵列基板的透光率。
与前面第一导电层类似的，该第二导电层可以保护在其下面的有源层的一部分，从而减小有源层出现缺失部分的可能性，进而提高阵列基板及由其所形成的显示装置的性能。
在一些实施例中，如图1所示，第一导电层151与有源层120的交叠部分在沿着从第一连接件至栅极的方向上的宽度小于第二导电层152与有源层120的交叠部分在沿着从第一连接件至栅极的方向上的宽度。换言之，该第二导电层152被制造的比较大。例如，第二导电层152的面积或宽度(即，截面图显示的横向尺寸)大于第一导电层151的面积或宽度。这样，第二导电层还可以充当电容器的一个电极板。这有利于形成透明电容结构，提高电容能力和导电能力。
在一些实施例中，如图1所示，阵列基板还包括与第二导电层152电连接的第二连接件162。该第二连接件162与第二导电层152接触。该第二连接件162的材料包括诸如铜等金属材料。该第二连接件可以为源极或漏极。例如，第一连接件161为源极，第二连接件162为漏极。又例如，第一连接件161为漏极，第二连接件162为源极。
在一些实施例中，如图1所示，阵列基板还包括位于第一绝缘层130的远离有源层120一侧的栅极163。栅极163的材料包括诸如铜等金属材料。
如图1所示，第二连接件162与栅极163处于同一层。第一连接件161与栅极163也处于同一层。第一连接件161和第二连接件162均与栅极163隔离开。该栅极163位于第一连接件161与第二连接件162之间。
需要说明的是，“同一层”指的是采用同一成膜工艺形成用于形成特定图形的膜层， 然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。例如，处于同一层中的两个结构层可以位于相同的结构层上，或者，也可以位于不同的结构层上。处于同一层的两个结构层可能处于不同的高度或者具有不同的厚度。
在一些实施例中，如图1所示，衬底结构110包括衬底基板111。该衬底基板包括刚性基板或柔性基板等。例如，该衬底基板可以包括玻璃基板等。
如图1所示，衬底结构110还包括在衬底基板111上的遮光层112。该遮光层112在衬底基板111上的正投影与有源层120在衬底基板111上的正投影至少部分重叠。例如，该遮光层的材料包括诸如铝、钼或铜等金属材料。
如图1所示，衬底结构110还包括覆盖遮光层112的第三导电层113。该第三导电层可以从遮光层112上延伸到衬底基板111上。该第三导电层113可以作为电容器的另一个电极板。
需要说明的是，另一些实施例中，遮光层112与第三导电层113的位置可以互换。例如，第三导电层113可以位于衬底基板111上，遮光层112位于第三导电层113的远离衬底基板一侧，即遮光层覆盖在第三导电层上。
在一些实施例中，该第三导电层113的材料包括透明导电材料。例如，该透明导电材料包括：ITO或IZO等。这里，第三导电层采用透明导电材料，可以提高阵列基板的透光率。
如图1所示，衬底结构110还包括在第三导电层113与有源层120之间的缓冲层114。例如，该缓冲层可以包括诸如二氧化硅等无机绝缘材料。该缓冲层114覆盖第三导电层113和衬底基板111等。
在一些实施例中，如图1所示，该衬底基板110还可以包括走线115。第一连接件161可以通过穿过第一绝缘层130和缓冲层114的第三通孔(作为导电通孔)143电连接至该走线115。该走线115可以与遮光层112处于同一层。例如，该走线115的材料与遮光层112的材料相同。该走线115与该遮光层112隔离开。
在一些实施例中，第一导电层151在衬底基板111上的正投影与遮光层112在衬底基板111上的正投影至少部分重叠。遮光层可以起到遮光的作用。
在一些实施例中，第三导电层113的厚度大于第二导电层152的厚度。第二导电层152的厚度与第一导电层151的厚度相等。这样使得第二导电层比较薄，从而可以进一步提高阵列基板的透光率。另外，第三导电层113的厚度比较厚，可以降低电阻。
例如，该第三导电层113的厚度为3000埃至5000埃。例如，第二导电层152(或 第一导电层151)的厚度为500埃至1000埃。
在一些实施例中，第一导电层151的厚度大于有源层120的厚度。例如，有源层120的厚度为300埃至500埃。
在一些实施例中，第一连接件161与第一导电层151的交叠部分的面积小于第二连接件162与第二导电层151的交叠部分的面积。这里，第二连接件与第二导电层的交叠部分的面积比较大，可以降低接触电阻。
在一些实施例中，如图1所示，第一绝缘层130包括位于栅极163下方的栅极绝缘层131。
如图1所示，有源层120包括：与第一连接件161电连接的第一导体化区域121、与第二连接件162电连接的第二导体化区域122和在第一导电化区域121与第二导体化区域122之间的沟道区域123。沟道区域123与栅极绝缘层131的边缘齐平。这里，第一导电层151与第一导体化区域121接触，第二导电层152与第二导体化区域122接触。通过将有源层的沟道区域两侧的部分导体化，可以降低第一导电层与有源层之间的接触电阻以及第二导电层与有源层之间的接触电阻，方便电流的传输，提高阵列基板及由其所形成的显示装置的性能。
图3是示意性地示出图1中的阵列基板在方框201处的放大示意图。
如图3所示，第一导电层151包括远离栅极163的第一部分1511和靠近栅极163的第二部分1512。该第一部分1511被第一连接件161完全覆盖，该第二部分1512未被第一连接件161覆盖。
在一些实施例中，如图3所示，第一连接件161与第一导电层151的交叠部分在沿着从第一连接件161至栅极163的方向上的宽度d1小于第一导电层151的边缘与沟道区域123之间的距离d4。
在一些实施例中，第一导体层151的面积大于第一连接件161与第一导电层151的交叠部分(即宽度d1所对应的部分)的面积。这有利于第一连接件与第一导电层的充分接触，防止出现接触不良的问题。
在一些实施例中，第一导体层151的面积小于沟道区域123的面积。沟道区域的面积比较大，有利于提高薄膜晶体管的性能。
需要说明的是，本公开中所述的“面积”是指结构层的平行于衬底基板所在平面的表面的面积。例如，该面积可以是结构层的上表面的面积。例如，第一导体层151的上表面的面积即为第一导体层151的面积；沟道区域123的上表面的面积即为沟道区 域123的面积，等等。
在一些实施例中，第一导电层151与栅极163之间的距离d3大于第一连接件161与第一导电层151的交叠部分在沿着从第一连接件至栅极的方向上的宽度d1，且第一连接件161与第一导电层151的交叠部分在沿着从第一连接件至栅极的方向上的宽度d1大于第一导电层151的第二部分(即，未被第一连接件161覆盖的部分)1512在沿着从第一连接件至栅极的方向上的宽度d2。即，d3>d1>d2。这样的尺寸设计，有利于提高薄膜晶体管的性能，从而提供阵列基板及由其所形成的显示装置的性能。
另外，如图3所示，第一导电层151与栅极绝缘层131之间存在缝隙301。
回到图1，在一些实施例中，阵列基板还包括覆盖第一连接件161、第二连接件162和栅极163的第二绝缘层171。例如，该第二绝缘层171的材料包括二氧化硅或氮化硅等中的至少一种。
如图1所示，该阵列基板还包括在第二绝缘层171的远离衬底结构110一侧的平坦化层172。例如，该平坦化层的材料包括诸如树脂等有机绝缘材料。
如图1所示，该阵列基板还包括在平坦化层172的远离衬底结构110一侧的第一电极层181和像素界定层174。该第一电极层181(例如，通过导电通孔)电连接至第二连接件162。该像素界定层174具有露出第一电极层181的至少一部分的第一开口1742。例如，该第一电极层为阳极层。例如，第一电极层181的材料包括诸如铜、银、铝或铝合金等金属，或者诸如ITO或IZO等透明导电材料。
如图1所示，该阵列基板还包括至少位于第一开口1742中的发光层180。该发光层可以包括：用于发出红光的发光层、用于发出绿光的发光层或者用于发出蓝光的发光层。
如图1所示，该阵列基板还包括与发光层180电连接的第二电极层182。该第二电极层182覆盖在像素界定层174和发光层180上。该第二电极层可以为阴极层。例如，第二电极层182的材料包括诸如铜、银、铝或铝合金等金属，或者诸如ITO或IZO等透明导电材料。
在一些实施例中，该阵列基板还可以包括在第一电极层181与第二电极层182之间的其他功能层，例如，电子传输层、空穴传输层、电子阻挡层或者空穴阻挡层，等等。因此，本公开的范围并不仅限于此。
在一些实施例中，如图1所示，第二导电层152在衬底基板111上的正投影与第三导电层113在衬底基板111上的正投影之间的重叠部分在沿着从第一连接件至栅极 的方向上的宽度，小于第二导电层152在衬底基板111上的正投影与第一电极层181在衬底基板111上的正投影之间的重叠部分在沿着从第一连接件至栅极的方向上的宽度。这有利于提高阵列基板的透光率。
在一些实施例中，如图1所示，第二导电层152在衬底基板111上的正投影与第三导电层113在衬底基板111上的正投影之间的重叠部分在沿着从第一连接件至栅极的方向上的宽度，小于第三导电层113在衬底基板111上的正投影与第一电极层181在衬底基板111上的正投影之间的重叠部分在沿着从第一连接件至栅极的方向上的宽度。这有利于提高阵列基板的透光率。
本公开提供了一种阵列基板。如图1所示，该阵列基板包括：衬底结构110和在衬底结构110上的薄膜晶体管。
该薄膜晶体管包括在衬底结构110上的有源层120。该薄膜晶体管还包括在有源层120的远离衬底结构一侧的图案化的第一绝缘层130。该第一绝缘层130具有露出有源层120的一部分的第一通孔141。该薄膜晶体管还包括在第一通孔141中且与有源层120接触的第一导电层151。该薄膜晶体管还包括在第一绝缘层130的远离衬底结构一侧的第一连接件161、第二连接件162和栅极163。第一连接件161与第一导电层151接触。第一连接件161、第二连接件162和栅极163处于同一层且互相隔离开。栅极163位于第一连接件161与第二连接件162之间。
如图1和图3所示，有源层120包括：与第一连接件161电连接的第一导体化区域121、与第二连接件162电连接的第二导体化区域122和在第一导电化区域121与第二导体化区域122之间的沟道区域123。沟道区域123在栅极163的下方。
如图3所示，第一导电层151包括远离栅极163的第一部分1511和靠近栅极163的第二部分1512。第一部分1511被第一连接件161完全覆盖，第二部分1512未被第一连接件161覆盖。第一导电层151在衬底结构110上的正投影位于有源层120在衬底结构110上的正投影的内部。
在上述实施例中，由于在第一绝缘层的第一通孔中形成有第一导电层，这样在制造过程中，该第一导电层可以在一定程度上保护在其下面的有源层的一部分，从而减小有源层出现缺失部分的可能性，进而提高阵列基板及由其所形成的显示装置的性能。
在一些实施例中，如图3所示，第二部分1512在沿着从第一连接件至栅极的方向上的宽度d2小于第一部分1511在沿着从第一连接件至栅极的方向上的宽度d1。这里，第一部分1511的宽度与第一连接件161与第一导电层151的交叠部分的宽度相 等，均为d1。
例如，第一部分1511的宽度d1是第二部分1512的宽度d2的2至5倍。
在一些实施例中，如图3所示，第二部分1512在沿着从第一连接件至栅极的方向上的宽度d2小于沟道区域123在沿着从第一连接件至栅极的方向上的宽度d5。
在一些实施例中，如图3所示，第二部分1512的厚度H2小于第一部分1511的厚度H1。
在一些实施例中，如图1和图3所示，有源层120还可以包括半导体区域(可以称为第一半导体区域)124。半导体区域124位于第一导体化区域121的远离沟道区域123的一侧。第二部分1512在沿着从第一连接件至栅极的方向上的宽度d2小于半导体区域124在沿着从第一连接件至栅极的方向上的宽度d6。
在另一些实施例中，有源层还可以包括另一半导体区域，可以称为第二半导体区域(图中未示出)。该第二半导体区域位于第二导体化区域122的远离沟道区域123的一侧。
图2是示出根据本公开另一个实施例的阵列基板的截面示意图。
该图2所示的阵列基板的结构与图1所示的阵列基板的结构相似。与图1所示的阵列基板的结构不同的是：图2所示的阵列基板中，第二通孔142还露出缓冲层114的一部分，并且第二导电层152包括：位于有源层120的表面上的第三部分1521和位于缓冲层114的表面上的第四部分1522。例如，在图2所示的结构中，有源层120的横向尺寸小于图1中的有源层的横向尺寸，第二导电层152的第三部分的面积小于图1中的第二导电层与有源层的交叠部分的面积。因此，在图2所示的阵列基板中，第二导电层与有源层的交叠部分的面积被降低，这可以提高阵列基板的透光率。
图4是示意性地示出根据本公开一个实施例的阵列基板的部分结构的俯视图。
为了示出的方便，图4中示出了阵列基板的有源层的第一导体化区域121、第一导电层151和第一连接件161。如图4所示，由于第一导电层151的存在，第一导体化区域121不存在缺失部分，因此，电流可以从第一连接件比较均匀地流过第一导体化区域121，提供了阵列基板的信号传输能力。
在本公开的一些实施例中，还提供了一种显示装置，包括如前所述的阵列基板，例如，图1或图2所示的阵列基板。例如，该显示装置可以为：显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
图5是示出根据本公开一个实施例的阵列基板的制造方法的流程图。如图5所示，该制造方法包括步骤S502至S508。图6A至图6I是示出根据本公开一些实施例的阵列基板的制造过程中若干阶段的结构的截面示意图。图9A至图9C是示出根据本公开另一些实施例的阵列基板的制造过程中若干阶段的结构的截面示意图。下面结合图5、图6A至图6I以及图9A至图9C详细描述根据本公开一些实施例的阵列基板的制造过程。
如图5所示，在步骤S502，在衬底结构上形成有源层。
例如，如图6A所示，例如通过沉积工艺在衬底结构110上形成有源层120。关于该衬底结构110的具体结构，前面已经详细描述，这里不再赘述。
回到图5，在步骤S504，在有源层的远离衬底结构一侧形成图案化的第一绝缘层，第一绝缘层具有露出有源层的一部分的第一通孔。
例如，可以参考图6A至图6F详细描述形成图案化的第一绝缘层的过程。
如图6A所示，例如通过沉积工艺，在有源层120的远离衬底结构110一侧形成第一绝缘层130。
接下来，如图6B所示，在第一绝缘层130的远离衬底结构110一侧形成第一掩模层610。例如，第一掩模层的材料为正性光刻胶。
接下来，如图6B和图6C所示，例如通过曝光和显影技术，利用图案化的第一掩模板621对第一掩模层610进行图案化以形成图案化的第一掩模层610，使得图案化的第一掩模层具有露出第一绝缘层130的一部分的第二开口6102。
接下来，如图6D和图6E所示，利用图案化的第一掩模层610，通过刻蚀工艺(例如干法刻蚀)去除被第二开口6102露出的第一绝缘层130的所述一部分以形成第一通孔141，从而形成图案化的第一绝缘层130。该第一通孔141露出有源层120的一部分。
回到图5，在步骤S506，对有源层被露出的所述一部分执行第一导体化处理。
例如，如图6E所示，可以对有源层120被露出的所述一部分执行第一导体化处理。例如，可以采用干法刻蚀工艺并采用He气(氦气)来执行第一导体化处理。
接下来，如图6F所示，去除第一掩模层610。
回到图5，在步骤S508，在第一通孔中形成与有源层接触的第一导电层。
例如，可以参考图6G至图6I详细描述形成第一导电层的过程。
例如，如图6G所示，通过沉积工艺在图案化的第一绝缘层130的远离衬底结构 110一侧和在第一通孔141中形成第一导电层151。例如，该第一导电层151的材料包括透明导电材料。
接下来，如图6H所示，在第一导电层151的远离衬底结构110一侧形成第二掩模层612，并利用前面所述的第一掩模板621对第二掩模层612进行曝光和显影处理，从而形成图6H所示的第二掩模层612的结构。例如，第二掩模层的材料为负性光刻胶。
接下来，如图6H所示，对第一导电层151进行刻蚀，以去除第一导电层151的未被第二掩模层612遮挡的部分，并保留第一导电层151的被第二掩模层612遮挡的部分，从而形成如图6I所示的结构。
接下来，如图6I所示，去除第二掩模层612。
至此，形成了图案化的第一导电层151，该第一导电层151可以尽可能地保护在其下面的有源层120不被刻蚀。
回到图5，在步骤S510，通过沉积工艺在第一绝缘层的远离衬底结构一侧形成连接材料层。
例如，如图9A所示，通过沉积工艺在第一绝缘层130的远离衬底结构110一侧形成连接材料层160。连接材料层160的材料包括诸如铜等的金属。
回到图5，在步骤S512，利用图案化的掩模层对连接材料层进行图案化，以形成第一连接件，该第一连接件与第一导电层接触，第一连接件覆盖第一导电层的第一部分且未覆盖第一导电层的第二部分。
例如，如图9A所示，在连接材料层的远离衬底结构110一侧形成图案化的掩模层(可以称为第三掩模层)637。例如，该第三掩模层的材料为光刻胶。
接下来，如图9B所示，例如，通过湿法刻蚀工艺，利用第三掩模层637对连接材料层160进行图案化，以形成第一连接件161。另外，该过程中还可以形成第二连接件162和栅极163等。在该湿法刻蚀的过程中，刻蚀液可能会刻蚀第三掩模层的边缘下方的连接材料层的一部分，因此，形成的第一连接件向内凹陷。
这样，形成了第一连接件。
回到图5，在步骤S514，利用掩模层，通过自对准工艺对第一绝缘层进行刻蚀以扩大第一通孔，其中，扩大后的第一通孔露出有源层的另一部分。
例如，如图9C所示，利用图案化的掩模层(即第三掩模层)637，通过自对准工艺对第一绝缘层130进行刻蚀以扩大第一通孔141，其中，扩大后的第一通孔141露 出有源层120的另一部分。例如，该刻蚀为干法刻蚀。这里，实施了对第一绝缘层的整面进行刻蚀，形成了第一导电层与栅极绝缘层之间的缝隙，即前面所述的缝隙301。
回到图5，在步骤S516，对有源层的被露出的所述另一部分进行第二导体化处理。
例如，如图9C所示，对有源层120的被露出的所述另一部分进行第二导体化处理。例如，可以采用干法刻蚀工艺并采用He气(氦气)来执行第二导体化处理。在该过程中，由于存在第一导电层151，因此可以保护在第一导电层151正下方的有源层的部分不被刻蚀。
接下来，去除第三掩模层637。
至此，提供了本公开一些实施例的阵列基板的制造方法。制造方法包括：在衬底结构上形成有源层；在有源层的远离衬底结构一侧形成图案化的第一绝缘层，第一绝缘层具有露出有源层的一部分的第一通孔；对有源层被露出的一部分执行第一导体化处理；在第一通孔中形成与有源层接触的第一导电层；通过沉积工艺在第一绝缘层的远离衬底结构一侧形成连接材料层；利用图案化的掩模层对连接材料层进行图案化，以形成第一连接件，第一连接件与第一导电层接触，第一连接件覆盖第一导电层的第一部分且未覆盖第一导电层的第二部分；利用掩模层，通过自对准工艺对第一绝缘层进行刻蚀以扩大第一通孔，其中，扩大后的第一通孔露出有源层的另一部分；和对有源层的被露出的另一部分进行第二导体化处理。该制造方法可以减小有源层出现缺失部分的可能性，进而提高阵列基板及由其所形成的显示装置的性能。
进一步地，在上述制造过程中，第二掩模层采用负性光刻胶，这样可以采用前面所述的第一掩模板进行曝光和显影，不需要额外制造掩模板，从而减小工艺复杂度。
图7是示出根据本公开另一个实施例的阵列基板的制造过程中一个阶段的结构的截面示意图。该图7示出了根据另一些实施例的形成第一导电层的过程中一个阶段的结构的截面示意图。
例如，如图7所示，在形成图6E所示的结构后，通过沉积工艺，在图案化的第一掩模层610上和在第一绝缘层130的第一通孔141中形成第一导电层151。
接下来，通过离地剥离工艺去除第一掩模层610和第一导电层151的在第一掩模层610上的部分，保留第一导电层151的在第一通孔141中的部分，从而形成如图6I所示的结构。
在该实施例中，采用离地剥离工艺，不需要增加额外的掩模工序，进一步降低工艺复杂度。
图8是示出根据本公开另一个实施例的阵列基板的制造过程中一个阶段的结构的截面示意图。该图8示出了根据另一些实施例的形成第一导电层的过程中一个阶段的结构的截面示意图。
例如，如图8所示，在形成图6F所示的结构后，利用图案化的第二掩模板630并采用蒸镀工艺，在第一绝缘层130的第一通孔141中形成第一导电层151，即形成了图6I所示的结构。如图8所示，该第二掩模板630具有通孔(可以称为第四通孔)，该开口与第一通孔141相对准。例如，该第二掩模板为FMM掩模板(Fine Metal Mask，精细金属掩模板)。另外，图8中还示出了蒸发源635。该蒸发源的材料包括透明导电材料(例如ITO或IZO等)。
在该实施例中，采用蒸发工艺形成第一导电层，可以降低工艺复杂度。
图10A至图10C是示出根据本公开另一些实施例的阵列基板的制造过程中若干阶段的结构的截面示意图。下面结合图10A至图10C和图1详细描述根据本公开另一些实施例的阵列基板的制造过程。
首先，如图10A所示，提供衬底结构。该提供衬底结构的步骤包括如下步骤。
例如，如图10A所示，通过沉积和图案化工艺在衬底基板111上形成遮光层112。另外，还形成了走线115。
接下来，如图10A所示，通过沉积和图案化工艺形成覆盖遮光层112的第三导电层113。
在另一些实施例中，也可以先通过沉积和图案化工艺在衬底基板111上形成第三导电层113；然后，通过沉积和图案化工艺在第三导电层113上形成遮光层112。
接下来，如图10A所示，通过沉积工艺形成覆盖第三导电层113的缓冲层114。
至此，形成了衬底结构110。
接下来，如图10B所示，采用前面描述的工艺形成有源层120、第一绝缘层130、第一通孔141、第一导电层151和第一连接件161。这里，还形成了第二通孔142、第三通孔143、第二导电层152、第二连接件162和栅极163。
需要说明的是，第二导电层152采用与第一导电层151相同的工艺过程一起形成，第二连接件162和栅极163与第一连接件161采用同一构图工艺形成。这里不再赘述。
还需要说明的是，在形成第一通孔141的同时，还可以形成第二通孔142和第三通孔143。第二通孔142和第三通孔143的形成过程与第一通孔141的形成过程类似，这里不再赘述。
接下来，如图10B所示，通过沉积工艺形成覆盖第一连接件161、第二连接件162和栅极163的第二绝缘层171。
接下来，如图10C所示，在第二绝缘层171的远离衬底结构110一侧形成平坦化层172。
接下来，如图10C所示，在平坦化层172的远离衬底结构110一侧形成与第二连接件162电连接的第一电极层181。
接下来，如图10C所示，在平坦化层172的远离衬底结构110一侧形成像素界定层174。像素界定层174具有露出第一电极层181的至少一部分的第一开口1742。
接下来，如图1所示，形成至少位于第一开口1742中的发光层180。
接下来，如图1所示，通过沉积工艺形成与发光层180电连接的第二电极层182。
至此，提供了根据本公开一些实施例的阵列基板的制造方法。该制造方法可以减小有源层出现缺失部分的可能性，进而提高阵列基板及由其所形成的显示装置的性能。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (26)

  1. 一种阵列基板，包括：
    衬底结构；
    在所述衬底结构上的有源层；
    在所述有源层的远离所述衬底结构一侧的图案化的第一绝缘层，所述第一绝缘层具有露出所述有源层的一部分的第一通孔；
    在所述第一通孔中且与所述有源层接触的第一导电层；和
    在所述第一绝缘层的远离所述衬底结构一侧的第一连接件，所述第一连接件与所述第一导电层接触，所述第一连接件覆盖所述第一导电层的第一部分且未覆盖所述第一导电层的第二部分。
  2. 根据权利要求1所述的阵列基板，其中：
    所述第一绝缘层还具有露出所述有源层的另一部分的第二通孔；
    所述阵列基板还包括：
    在所述第二通孔中的第二导电层；
    与所述第二导电层电连接的第二连接件；和
    位于所述第一绝缘层的远离所述有源层一侧的栅极；
    其中，所述第二连接件与所述栅极处于同一层，且所述第一连接件和所述第二连接件均与所述栅极隔离开。
  3. 根据权利要求2所述的阵列基板，其中，所述衬底结构包括：
    衬底基板；
    在所述衬底基板上的遮光层和第三导电层，所述遮光层在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影至少部分重叠，其中，所述第三导电层覆盖在所述遮光层上，或者所述遮光层覆盖在所述第三导电层上；和
    在所述第三导电层与所述有源层之间的缓冲层。
  4. 根据权利要求3所述的阵列基板，其中，所述第一导电层在所述衬底基板上的正投影与所述遮光层在所述衬底基板上的正投影至少部分重叠。
  5. 根据权利要求3所述的阵列基板，其中，
    所述第二通孔还露出所述缓冲层的一部分；
    所述第二导电层包括：位于所述有源层的表面上的第三部分和位于所述缓冲层的表面上的第四部分。
  6. 根据权利要求3所述的阵列基板，其中，所述第一导电层、所述第二导电层和所述第三导电层的材料均包括透明导电材料。
  7. 根据权利要求3所述的阵列基板，其中，所述第三导电层的厚度大于所述第二导电层的厚度，且所述第二导电层的厚度与所述第一导电层的厚度相等。
  8. 根据权利要求1所述的阵列基板，其中，所述第一导电层的厚度大于所述有源层的厚度。
  9. 根据权利要求2所述的阵列基板，其中，所述第一连接件与所述第一导电层的交叠部分的面积小于所述第二连接件与所述第二导电层的交叠部分的面积。
  10. 根据权利要求3所述的阵列基板，其中：
    所述第一绝缘层包括位于所述栅极下方的栅极绝缘层；
    所述有源层包括：与所述第一连接件电连接的第一导体化区域、与所述第二连接件电连接的第二导体化区域和在所述第一导电化区域与所述第二导体化区域之间的沟道区域，所述沟道区域与所述栅极绝缘层的边缘齐平。
  11. 根据权利要求10所述的阵列基板，其中，所述第一连接件与所述第一导电层的交叠部分在沿着从第一连接件至栅极的方向上的宽度小于所述第一导电层的边缘与所述沟道区域之间的距离。
  12. 根据权利要求1所述的阵列基板，其中，所述第一导体层的面积大于所述第一连接件与所述第一导电层的交叠部分的面积。
  13. 根据权利要求10所述的阵列基板，其中，所述第一导体层的面积小于所述沟道区域的面积。
  14. 根据权利要求2所述的阵列基板，其中，所述第一导电层与所述有源层的交叠部分在沿着从所述第一连接件至所述栅极的方向上的宽度小于所述第二导电层与所述有源层的交叠部分在沿着从所述第一连接件至所述栅极的方向上的宽度。
  15. 根据权利要求2所述的阵列基板，其中，
    所述第一导电层与所述栅极之间的距离大于所述第一连接件与所述第一导电层的交叠部分在沿着从所述第一连接件至所述栅极的方向上的宽度，且所述第一连接件与所述第一导电层的交叠部分在沿着从所述第一连接件至所述栅极的方向上的宽度大于所述第一导电层的第二部分在沿着从所述第一连接件至所述栅极的方向上的宽度。
  16. 根据权利要求3所述的阵列基板，还包括：
    覆盖所述第一连接件、所述第二连接件和所述栅极的第二绝缘层；
    在所述第二绝缘层的远离所述衬底结构一侧的平坦化层；
    在所述平坦化层的远离所述衬底结构一侧的第一电极层和像素界定层，所述第一电极层电连接至所述第二连接件，所述像素界定层具有露出所述第一电极层的至少一部分的第一开口；
    至少位于所述第一开口中的发光层；和
    与所述发光层电连接的第二电极层。
  17. 根据权利要求16所述的阵列基板，其中，
    所述第二导电层在所述衬底基板上的正投影与所述第三导电层在所述衬底基板上的正投影之间的重叠部分在沿着从所述第一连接件至所述栅极的方向上的宽度，小于所述第二导电层在所述衬底基板上的正投影与所述第一电极层在所述衬底基板上的正投影之间的重叠部分在沿着从所述第一连接件至所述栅极的方向上的宽度。
  18. 根据权利要求16所述的阵列基板，其中，
    所述第二导电层在所述衬底基板上的正投影与所述第三导电层在所述衬底基板上的正投影之间的重叠部分在沿着从所述第一连接件至所述栅极的方向上的宽度，小于所述第三导电层在所述衬底基板上的正投影与所述第一电极层在所述衬底基板上的正投影之间的重叠部分在沿着从所述第一连接件至所述栅极的方向上的宽度。
  19. 一种阵列基板，包括：
    衬底结构；和
    在所述衬底结构上的薄膜晶体管，所述薄膜晶体管包括：
    在所述衬底结构上的有源层；
    在所述有源层的远离所述衬底结构一侧的图案化的第一绝缘层，所述第一绝缘层具有露出所述有源层的一部分的第一通孔；
    在所述第一通孔中且与所述有源层接触的第一导电层；和
    在所述第一绝缘层的远离所述衬底结构一侧的第一连接件、第二连接件和栅极，其中，所述第一连接件与所述第一导电层接触，所述第一连接件、所述第二连接件和所述栅极处于同一层且互相隔离开，所述栅极位于所述第一连接件与所述第二连接件之间；
    其中，所述有源层包括：与所述第一连接件电连接的第一导体化区域、与所述第二连接件电连接的第二导体化区域和在所述第一导电化区域与所述第二导体化区域之间的沟道区域，所述沟道区域在所述栅极的下方；
    所述第一导电层包括远离所述栅极的第一部分和靠近所述栅极的第二部分，所述第一部分被所述第一连接件完全覆盖，所述第二部分未被所述第一连接件覆盖，所述第一导电层在所述衬底结构上的正投影位于所述有源层在所述衬底结构上的正投影的内部。
  20. 根据权利要求19所述的阵列基板，其中，所述第二部分在沿着从所述第一连接件至所述栅极的方向上的宽度小于所述第一部分在沿着从所述第一连接件至所述栅极的方向上的宽度。
  21. 根据权利要求19所述的阵列基板，其中，所述第二部分在沿着从所述第一连 接件至所述栅极的方向上的宽度小于所述沟道区域在沿着从所述第一连接件至所述栅极的方向上的宽度。
  22. 根据权利要求19所述的阵列基板，其中，所述第二部分的厚度小于所述第一部分的厚度。
  23. 根据权利要求20所述的阵列基板，其中，所述第一部分的宽度是所述第二部分的宽度的2至5倍。
  24. 根据权利要求20所述的阵列基板，其中：
    所述有源层还包括半导体区域，所述半导体区域位于所述第一导体化区域的远离所述沟道区域的一侧；
    其中，所述第二部分在沿着从所述第一连接件至所述栅极的方向上的宽度小于所述半导体区域在沿着从所述第一连接件至所述栅极的方向上的宽度。
  25. 一种显示装置，包括：如权利要求1至24任意一项所述的阵列基板。
  26. 一种阵列基板的制造方法，包括：
    在衬底结构上形成有源层；
    在所述有源层的远离所述衬底结构一侧形成图案化的第一绝缘层，所述第一绝缘层具有露出所述有源层的一部分的第一通孔；
    对所述有源层被露出的所述一部分执行第一导体化处理；
    在所述第一通孔中形成与所述有源层接触的第一导电层；
    通过沉积工艺在所述第一绝缘层的远离衬底结构一侧形成连接材料层；
    利用图案化的掩模层对所述连接材料层进行图案化，以形成第一连接件，所述第一连接件与所述第一导电层接触，所述第一连接件覆盖所述第一导电层的第一部分且未覆盖所述第一导电层的第二部分；
    利用所述掩模层，通过自对准工艺对所述第一绝缘层进行刻蚀以扩大所述第一通孔，其中，扩大后的第一通孔露出所述有源层的另一部分；和
    对所述有源层的被露出的所述另一部分进行第二导体化处理。
PCT/CN2023/091472 2022-05-27 2023-04-28 阵列基板及其制造方法、显示装置 Ceased WO2023226688A1 (zh)

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