WO2023231122A1 - 封装结构及其制作方法、半导体器件 - Google Patents

封装结构及其制作方法、半导体器件 Download PDF

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Publication number
WO2023231122A1
WO2023231122A1 PCT/CN2022/102515 CN2022102515W WO2023231122A1 WO 2023231122 A1 WO2023231122 A1 WO 2023231122A1 CN 2022102515 W CN2022102515 W CN 2022102515W WO 2023231122 A1 WO2023231122 A1 WO 2023231122A1
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WIPO (PCT)
Prior art keywords
pad
layer
pads
edge
semiconductor functional
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PCT/CN2022/102515
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English (en)
French (fr)
Inventor
田凯
李红文
全昌镐
陈亮
汪玉霞
郭迎冬
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to JP2023501542A priority Critical patent/JP7576152B2/ja
Priority to KR1020227040889A priority patent/KR102774939B1/ko
Priority to EP22836031.9A priority patent/EP4307352B1/en
Priority to US18/163,802 priority patent/US20230395441A1/en
Publication of WO2023231122A1 publication Critical patent/WO2023231122A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together

Definitions

  • the present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a packaging structure and a manufacturing method thereof, and a semiconductor device.
  • ports for testing and performing functional interactions need to be prepared on the packaging structure.
  • embodiments of the present disclosure propose a packaging structure, a manufacturing method thereof, and a semiconductor device.
  • a packaging structure including:
  • An isolation layer with a plurality of via holes covers the surface of the interconnection layer, the via holes expose part of the interconnection layer, and the interconnection layer is provided on the surface of the semiconductor functional structure;
  • each first pad is composed of the interconnection layer exposed by one of the via holes; the N is a positive integer greater than 1;
  • each redistribution layer covers the isolation layer and is electrically connected to a corresponding first pad among the N first pads; some of the first pads are arranged side by side along the first direction. At a position close to the first edge of the semiconductor functional structure, another part of the first pad is arranged juxtaposed along the first direction at a position close to the second edge of the semiconductor functional structure, the first edge and the The second edges are two opposite edges of the semiconductor functional structure;
  • a first insulating layer covers and exposes a partial area of each redistribution layer
  • each redistribution layer includes a second pad and a third pad; wherein, the center point of each second pad is relative to the center of the corresponding first pad.
  • the offset direction and offset distance of the points are equal; the relative position between the second pad and the third pad in part of the rewiring layer is the same as that of the third pad in another part of the rewiring layer.
  • the relative positions between the two pads and the third pad are different; the first pad and the second pad are respectively used for testing when the semiconductor functional structure is at different operating speeds, and the third pad Used to perform functional interaction corresponding to the content of the second pad test.
  • the second pad and the third pad included in each of the N redistribution layers are arranged side by side along a second direction, and the second direction is parallel to the second pad.
  • the first direction is vertical.
  • the orthographic projection of the center point of each second pad on the plane where the interconnection layer is located is offset by a first distance in the second direction relative to the center point of the corresponding first pad.
  • the shape of the orthographic projection of each redistribution layer on the plane where the interconnection layer is located includes a strip shape.
  • the first end of part of the first pad close to the first edge and the second end of part of the redistribution layer close to the first edge are substantially flush with each other in the third direction.
  • the first direction and the second direction are both vertical;
  • the third end of the other part of the first pad close to the second edge is substantially flush with the fourth end of the other part of the redistribution layer close to the second edge along the third direction.
  • the second pad in part of the redistribution layer is located close to the second end, and the third pad is located away from the second end;
  • the second pad in another part of the redistribution layer is located near the fourth end, and the third pad is located away from the fourth end.
  • each redistribution layer further includes a first region for conductive connection with the first pad
  • the second pad and the third pad in part of the redistribution layer are located on one side of the first area; the second pad and the third pad in the other part of the redistribution layer are located on one side of the first area.
  • Third pads are located on both sides of the first area.
  • the redistribution layer is in direct contact with the corresponding first pad
  • the packaging structure further includes: conductive pillars located between the redistribution layer and the corresponding first pad, and the redistribution layer is conductively connected to the interconnection layer through the conductive pillars.
  • the packaging structure includes the conductive pillars, the number of the conductive pillars may include multiple, and the multiple conductive pillars are arranged side by side along the first direction.
  • the rewiring layer is in direct contact with the corresponding first pad
  • the packaging structure further includes:
  • a second insulating layer is located in the groove surrounded by each redistribution layer, and the hardness of the material of the second insulating layer is smaller than the hardness of the material of the redistribution layer.
  • a semiconductor device including: a semiconductor functional structure and a packaging structure as described in the above embodiments of the disclosure.
  • the semiconductor device further includes:
  • a plurality of stacked die each die includes a semiconductor functional structure and a packaging structure located on the semiconductor functional structure;
  • Each die is electrically connected to the substrate through leads on a third pad in the package structure.
  • a method for manufacturing a packaging structure including:
  • the surface of the semiconductor functional structure is provided with an interconnection layer
  • An isolation layer is formed with a plurality of via holes, the isolation layer covers the surface of the interconnection layer, the via hole exposes a portion of the interconnection layer, and the portion of the interconnection layer exposed by each via hole serves as a first Pads to form N first pads; the first pads are used to perform the first type of test; the N is a positive integer greater than 1;
  • N rewiring layers are formed on the N first pads and the isolation layer, and each rewiring layer covers the isolation layer and is connected to the N first pads.
  • a corresponding first pad in the pad is electrically connected; some of the first pads are arranged side by side along the first direction close to the first edge of the semiconductor functional structure, and the other part of the first pads are arranged along the first edge along the first direction.
  • One direction is arranged side by side at a position close to the second edge of the semiconductor functional structure, and the first edge and the second edge are two opposite edges of the semiconductor functional structure;
  • first insulating layer covering and exposing part of the redistribution layer, and the exposed part of the redistribution layer serves as a second pad and a third pad; wherein, the center point of each second pad The offset direction and offset distance relative to the center point of the corresponding first pad are equal; the relative position between the second pad and the third pad in the partial rewiring layer is the same as that of the other part.
  • the relative position between the second pad and the third pad in the rewiring layer is different; the second pad is used to perform the second type of test, and the third pad is used to perform the The functional interaction corresponding to the content of the second type of test; the running speed of the semiconductor functional structure when performing the first type of test is lower than the running speed when performing the second type of test.
  • N first pads are provided in the top metal layer to perform testing on the semiconductor functional structure at the first operating speed; wherein part of the first pads are along The first pads are arranged side by side in a first direction close to the first edge of the semiconductor functional structure, and the other part of the first pads are arranged side by side in a first direction close to the second edge of the semiconductor functional structure; in the first After the test at the second operating speed is completed, a second pad corresponding to the first pad is provided in the rewiring layer on the first pad to execute the semiconductor functional structure at the second operating speed.
  • the relative position between the second pad and the third pad in part of the redistribution layer is different from the second pad and the second pad in the other part of the redistribution layer.
  • the relative positions between the third pads are different; here, by setting the center point of each second pad to be offset in the same direction and by an equal distance relative to the center point of the corresponding first pad, such that The N first pads and the N second pads maintain exactly the same relative position; at the same time, by setting the positions between the second pads and the third pads at different edge positions to be different, such that the positions between the two pads are
  • the rewiring layer at each edge position maintains a large fault tolerance rate and can be close to the edge but not beyond the edge.
  • Figure 1 is a schematic cross-sectional view of a packaging structure provided in an embodiment of the present disclosure
  • Figure 2a is a schematic cross-sectional view of another packaging structure provided in an embodiment of the present disclosure.
  • Figure 2b is a schematic top view of Figure 2a
  • Figure 2c is a schematic cross-sectional view of a packaging structure with conductive pillars provided in an embodiment of the present disclosure
  • Figure 3 is a schematic diagram of the relative positions of the first pad and the second pad provided in the embodiment of the present disclosure
  • Figure 4 is a schematic diagram of the relative positions of the second pad and the third pad provided in the embodiment of the present disclosure
  • Figure 5 is a schematic flow chart of a manufacturing method of a packaging structure provided in an embodiment of the present disclosure
  • 6a-6d are schematic diagrams of a manufacturing process of a packaging structure provided in an embodiment of the present disclosure.
  • the term "A and B are connected” includes the situation where A and B are in direct contact, or the situation where A and B are in indirect contact through an intermediate conductive structure; the terms “first”, “second”, etc. are Used to distinguish similar objects, not necessarily to describe a specific order or sequence.
  • the term "layer” refers to a portion of material that includes a region having a thickness.
  • a layer may extend on the lower or upper surface of the structure and may have an area less than or equal to the surface on which it extends.
  • the semiconductor functional structure involved in the embodiments of the present disclosure is a part that will be used in subsequent processes to form a final semiconductor device, and is a core part for realizing the main functions of the semiconductor device.
  • the final semiconductor device may include, but is not limited to, a memory.
  • DRAM Dynamic Random Access Memory
  • RDL Redistribution Layer
  • the top metal window opening refers to forming a passivation layer (Passivation) or an insulating layer on the top metal layer of the semiconductor functional structure to protect the semiconductor functional structure from being damaged; then, forming a passivation layer or insulating layer on the passivation layer or the insulating layer Window areas to expose part of the top metal layer to form a pad.
  • Passivation passivation layer
  • insulating layer on the passivation layer or the insulating layer Window areas to expose part of the top metal layer to form a pad.
  • probe clamping needle testing can be performed on the pad to test the electrical properties of the semiconductor functional structure; bonding wires can also be drawn out on the pad to test the semiconductor function. Electrical extraction from the structure.
  • the rewiring layer opening refers to forming a rewiring layer on the top metal layer of the semiconductor functional structure, forming a passivation layer or an insulating layer on the rewiring layer, and then forming an opening on the passivation layer or insulating layer. window area to expose part of the rewiring layer, forming two pads placed side by side. One of the two pads is used for probe clamping pin testing, and the other is used for drawing out bonding wires on the pad.
  • the rewiring layer can play the role of adjusting the pad position in the semiconductor device, and can also play the role of enhancing the power supply network of the power ground.
  • the top metal layer is relatively thin, and there is a gasket structure underneath, which can support the same windowed metal area. It is first tested by the probe clamping needle, and then the bonding wire is packaged in the packaging factory. Affects the yield of package wiring; the material of the rewiring layer is generally metal. The rewiring layer is thicker than the top metal layer. After the probe pin is stuck, there will be deep and rough needle marks on the surface. This needle mark will affect Yield of package bonding, so the pads in the redistribution layer for testing and for bringing out the bond wires need to be separated. No matter which of the above windowing methods is used in the packaging structure, it will not have much impact on the function of the semiconductor device. Windowing on the rewiring layer will help improve performance, but it will increase the production cycle and production cost.
  • one of the above two window opening methods is generally selected to design the packaging structure according to the actual needs of the semiconductor device.
  • the demand is not single, and there are often multiple demands.
  • multiple requirements are some examples of multiple requirements:
  • the packaging structure includes a top metal window opening method and a rewiring layer window opening method; wherein, in the top metal window opening method, in the top metal layer A first type of pad 102 is provided in 101; the first type of pad 102 can be used to perform low-speed testing and lead out bonding wires; in the rewiring layer windowing method, two types of pads are provided in the rewiring layer 103 (Second type pad 104 and third type pad 105), the second type pad 104 is used to perform high-speed testing, and the third type pad 105 is used to lead out bonding wires.
  • the test probe card when using the first type of pads 102 to perform a low-speed test, the test probe card needs to hit the center points of all the first type of pads 102 at the same time.
  • the test probe card When using the second type of pads 104 to perform a high-speed test, , the test probe card needs to be hit on the center points of all the second type pads 104 at the same time.
  • FIG. 1 it can be seen from FIG. 1 that the first type pads 102 and the second pads 104 are in different layers of the packaging structure, and the relative positions of the first type pads 102 and each second pads 104 in different layers are different. In this way, in order to meet the needs of low-speed testing and high-speed testing, two sets of test probe cards have to be made, and making two sets of test probe cards will greatly increase the test cost and test time.
  • the redistribution layer 103 also needs to be disposed at the positions of the two opposite edges of the semiconductor functional structure.
  • the second type pad 104 and the third type pad 105 Together they occupy a larger area than the first type of pad 102 . At this time, the redistribution layer 103 at the position of at least one edge easily exceeds the edge.
  • the packaging structure includes: an isolation layer with multiple via holes, and the isolation layer layer covers the surface of the interconnection layer, and the via hole exposes part of the interconnection layer, and the interconnection layer is provided on the surface of the semiconductor functional structure; N first pads, each first pad consists of one of the via holes The interconnection layer is composed of holes exposed; the N is a positive integer greater than 1; N rewiring layers, each rewiring layer covers the isolation layer and is corresponding to one of the N first pads.
  • the first pads are electrically connected; part of the first pads are arranged side by side in the first direction close to the first edge of the semiconductor functional structure, and another part of the first pads are arranged side by side in the first direction close to the first edge of the semiconductor functional structure.
  • a first insulating layer covers and exposes each of the rewiring A partial area of the layer; the exposed partial area of each redistribution layer includes a second pad and a third pad; wherein the center point of each second pad is relative to the corresponding third pad
  • the offset direction and offset distance of the center point of a pad are equal; the relative position between the second pad and the third pad in part of the redistribution layer is different from that of another part of the redistribution layer.
  • the relative positions between the second pad and the third pad are different; the first pad and the second pad are respectively used for testing when the semiconductor functional structure is at different operating speeds, so The third pad is used to perform functional interaction
  • first direction involved in the embodiment of the present disclosure is parallel to the surface of the semiconductor functional structure
  • second direction involved in the embodiment of the present disclosure is parallel to the semiconductor functional structure and perpendicular to the first direction
  • third direction involved in the embodiment of the present disclosure is perpendicular to both the first direction and the second direction.
  • first direction may be parallel to the X-axis direction
  • second direction may be parallel to the Y-axis direction
  • third direction may be parallel to the Z-axis direction.
  • the packaging structure includes: a substrate (not shown in Figure 2a), the constituent materials of the substrate may include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon on insulator (Silicon on Insulator, SOI) or Germanium on Insulator (GOI).
  • a substrate not shown in Figure 2a
  • the constituent materials of the substrate may include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon on insulator (Silicon on Insulator, SOI) or Germanium on Insulator (GOI).
  • the semiconductor functional structure 200 is located on a substrate; specifically, the semiconductor functional structure 200 includes a semiconductor functional layer 201 and an interconnection layer 202 located on the surface of the semiconductor functional layer 201.
  • the interconnection layer 202 is used to extract electrical signals from the functional structures in the semiconductor functional layer 201 to run the functional structures.
  • the interconnect layer 202 includes a top metal layer, which is used not only to extract electrical signals from the functional structure, but also to support the semiconductor functional structure 200 .
  • any signals connected to the rewiring layer formed in subsequent processes are connected to the interconnection layer 202 , which ensures that the function of the semiconductor functional structure 200 is complete without the rewiring layer.
  • the interconnection layer 202 shown in Figure 2a is a cross-sectional rendering of a certain section after the part has been removed. In practical applications, the parts in the interconnection layer are not truncated, but interconnected, that is, on other sections , the parts in the interconnection layer may be continuous.
  • the isolation layer 203 covers the surface of the interconnection layer 202 and is used to isolate the interconnection layer 202 and the subsequently formed rewiring layer 206 in some areas.
  • a via hole 204 is provided in the isolation layer 203, and the via hole 204 exposes a portion of the interconnection layer 202.
  • the shape of the via hole 204 may be cylindrical, inverted trapezoidal, or any suitable shape; the composition material of the isolation layer 203 includes but is not limited to tetraethylorthosilicate (TEOS).
  • the first pad 205 is composed of the interconnection layer 202 exposed by one via hole 204; the isolation layer 203 may contain multiple via holes 204, thereby forming a plurality of first pads exposed by the via hole 204.
  • the number of pads 205 includes multiple pads.
  • the first pad 205 can be used to perform the first type of test; on the other hand, it can also be used to perform functional interaction corresponding to the content of the first type of test.
  • the first type of tests can be understood as some tests performed on the semiconductor functional structure at a lower operating speed. It should be noted that in memory, the operating speed refers to the read and write speed of the memory.
  • the execution of the functional interaction corresponding to the contents of the first type of test may be understood as drawing out a bonding wire on the first pad. That is to say, when performing the first type of test, the first pad 205 can be used to contact the probe card, and the multiple probes in the probe card correspond to the N first pads in a one-to-one manner to achieve interaction. electrical connections to other test systems.
  • the first pads 205 may not be placed near one edge of the semiconductor functional structure.
  • the first pads 205 can be arranged opposite to the semiconductor functional structure.
  • the N first pads are divided into two parts, namely the first part of the first pad 2051 and the second part of the first pad.
  • the M2 first pads are juxtaposed along the first direction at a position close to the second edge 20b of the semiconductor functional structure.
  • the first edge 20a and The second edges 20b are two opposite edges of the semiconductor functional structure.
  • M1+M2 N.
  • FIG. 2a is a partial cross-sectional schematic diagram of the packaging structure in which the first pad 205 is in direct contact with the redistribution layer 206
  • FIG. 2b is an example of a top view of the packaging structure, in which, for better clarity, in FIG. 2b The position arrangement of the first pad is shown, and other layers are hidden
  • FIG. 2c is a partial cross-sectional schematic diagram of the packaging structure in which the first pad 205 is in indirect contact with the redistribution layer 206 through the conductive pillar 207.
  • the number of the first part of first pads 2051 and the number of the second part of first pads 2052 may be the same or different.
  • the six first pads in Figure 2b are divided into a first part of the first pad 2051 and a second part of the first pad 2052.
  • the first part of the first pad 2051 includes three first pads, along the first direction.
  • the second part of the first pads 2052 includes three first pads, which are juxtaposed and arranged near the first edge 20a of the semiconductor functional structure along the first direction. at the position of edge 20b.
  • N redistribution layers 206 are located on the surface of the isolation layer 203 and on the via holes 204.
  • each redistribution layer 206 covers the isolation layer 203; and, the N redistribution layers 206 are in direct contact with the corresponding first pads 205 of the N first pads 205.
  • the redistribution layer 206 and the first pad 205 may be in direct contact (refer to FIG. 2a); or may be in indirect contact, that is, a conductive material layer is provided between the redistribution layer 206 and the first pad 205 (refer to FIG. 2b, Figure 2c, for example, conductive pillars 207).
  • the conductive pillar 207 may be made of the same material as the redistribution layer 206 , or may be different. It should be noted that the height of the conductive pillar 207 may be less than or equal to the depth of the via hole 204 . As shown in FIG. 2 c , the height of the conductive pillar 207 is equal to the depth of the via hole 204 .
  • the packaging structure includes the conductive pillars 207, the number of the conductive pillars includes multiple, and the multiple conductive pillars are arranged side by side along the first direction.
  • the number of the conductive pillars 207 in the same via hole 204 may include one or multiple, and adjacent conductive pillars 207 are separated by insulating materials; accordingly, each conductive pillar 207 corresponds to a first pad 205 , that is, when the number of conductive pillars 207 is multiple, the bottom of the same via hole 204 has multiple first pads 205 .
  • the number of conductive pillars 207 includes multiple, multiple conductive pillars 207 are connected to the redistribution layer 206 and the interconnection layer 202. In this way, the number of electrical connections between the redistribution layer 206 and the interconnection layer 202 can be increased. reliability.
  • a first insulating layer 208 is located on the redistribution layer 206.
  • the first insulating layer 208 covers the surface of the redistribution layer 206 , and the thickness of the redistribution layer 206 on the exposed portion of the interconnection layer 202 may be the same as the thickness of the redistribution layer 206 on the surface of the isolation layer 203 . In some embodiments, when the diameter width of the via hole 204 is greater than twice the thickness of the redistribution layer 206 , the redistribution layer 206 covers the sidewalls and bottom of the via hole 204 , and the redistribution layer 206 is surrounded by a groove 209 .
  • the redistribution layer 206 is in direct contact with the corresponding first pad 205, and the packaging structure further includes: a second insulating layer 210 located on each redistribution layer.
  • the hardness of the material of the second insulating layer 210 is less than the hardness of the material of the rewiring layer 206. In this way, on the one hand, the stress of the packaging structure can be reduced and the reliability of the packaging structure can be increased; On the other hand, compared with filling the groove 209 with the redistribution layer 206, filling the groove 209 with the material of the second insulating layer 210 can avoid generating more parasitic capacitance.
  • the second insulating layer 210 and the first insulating layer 208 may have an integrated structure or a separate structure. When they are separate structures, the materials of the two may be different. What is shown in FIG. 2a is the case where the second insulating layer 210 and the first insulating layer 208 have an integrated structure.
  • the composition material of the second insulating layer 210 includes but is not limited to polyimide (PI).
  • At least a portion of the N redistribution layers 206 in which the redistribution layer 206 is exposed includes a second pad 211 and a third pad 212.
  • one second pad 211 and one third pad 212 are provided in each of the N redistribution layers 206; in other words, N second pads 211 and N third pads 212 One-to-one correspondence.
  • the second pad 211 is used to perform a second type of test
  • the third pad 212 is used to perform functional interaction corresponding to the content of the second type of test.
  • the second type of tests can be understood as tests performed on semiconductor functional structures at higher operating speeds.
  • the execution of functional interactions corresponding to the content of the second type of test can be understood as drawing out bonding wires on the third pad and performing signal interactions.
  • the second liner 211 and the third liner 212 may be continuously arranged, that is, there is no partition wall between the second liner 211 and the third liner 212; they may also be arranged at intervals. , that is, a partition wall is provided between the second pad 211 and the third pad 212 .
  • the second pad 211 and the third pad 212 are continuously arranged, during the test process, damage to the probe card caused by the partition wall when the probe is not aimed can be avoided, thus The service life of the probe card is extended; at the same time, the generation of impurities is reduced, thereby improving the test efficiency; in addition, the damage of the probe card to the partition wall is reduced, thereby improving the overall reliability of the packaging structure.
  • a partition wall is provided between the second liner 211 and the third liner 212 as an example for description.
  • the following description of the partition wall is only used to illustrate the present disclosure and is not intended to be used. Limit the scope of this disclosure.
  • each probe in the probe card can correspond to the second pad.
  • the center of each second pad 211 is The points are offset in the same direction and by the same distance relative to the center point of the corresponding first pad 205.
  • the N first pads and the N second pads can maintain exactly the same relative position.
  • the same set of probe cards can be aligned with the center points of all second pads 211 after moving a certain distance from the center point of the first pad 205 in a certain direction.
  • the probe card can directly perform the second type test on all the second pads that need to be tested without replacing a new probe card.
  • the second pad and the third pad included in each of the N redistribution layers are arranged side by side along a second direction, and the second direction is The first direction is vertical.
  • the first pads 205 are distributed at the positions of two opposite edges of the semiconductor functional structure.
  • the left side of the arrow in Figure 3 shows an example of the arrangement of the first pads 205. This example is the same as Figure 2b and will not be described again here.
  • the N second pads are divided into two parts, namely the third part and the fourth part; wherein, the third part includes M1 second pads; the fourth part includes M2 second pads; M1 second pads in the third part are arranged side by side along the first direction close to the first edge of the semiconductor functional structure; M2 second pads in the fourth part are arranged side by side along the second direction. Disposed close to the second edge of the semiconductor functional structure.
  • the N third pads are divided into two parts, namely the fifth part and the sixth part; wherein the fifth part includes M1 third pads; the sixth part includes M2 third pads; M1 third pads and M1 second pads in the fifth part are arranged side by side in the second direction close to the first edge of the semiconductor functional structure; M2 third pads in the sixth part and M2 second pads are arranged side by side along the second direction close to the second edge of the semiconductor functional structure.
  • the right side of the arrow in Figure 3 shows an arrangement example of the rewiring layer 206.
  • the six rewiring layers 206 are divided into two parts, each part includes three rewiring layers, and each part The three redistribution layers 206 are arranged side by side along the X-axis direction.
  • Each redistribution layer 206 includes a second pad 211 and a corresponding third pad 212.
  • the pads 212 are all arranged side by side along the Y-axis direction; the dotted line in FIG. 3 shows the straight line where the center point of the first pad 205 is located.
  • the first pad 205, the second pad 211, and the third pad 212 are all in strip shape, and each of the redistribution layers 206 is located on the plane of the interconnection layer.
  • Orthographic projection shapes include strips.
  • the width of each first pad 205 along the first direction may be the same as the width of each second pad 211 and third pad 212 along the first direction.
  • Each first pad 205 may have a width along the second direction.
  • the length in the second direction may be different from the length of each of the second pad 211 and the third pad 212 in the second direction.
  • the orthographic projection of the center point of each second pad on the plane where the interconnection layer is located is offset in the second direction relative to the center point of the corresponding first pad. A distance.
  • the center point O 2 of each second pad at the first edge 20 a is offset by the Y-axis direction relative to the center point O 1 of the corresponding first pad.
  • a distance H1; at the same time, the center point O 2 of each second pad at the second edge 20 b is offset by a first distance in the Y-axis direction relative to the center point O 1 of the corresponding first pad. H1.
  • a first end of a portion of the first pad near the first edge and a second end of a portion of the redistribution layer near the first edge are substantially flush along a third direction.
  • the direction is perpendicular to both the first direction and the second direction;
  • the third end of the other part of the first pad close to the second edge is substantially flush with the fourth end of the other part of the redistribution layer close to the second edge along the third direction.
  • the second pad in part of the redistribution layer is located near the second end, and the third pad is located away from the second end;
  • the second pad in another part of the redistribution layer is located near the fourth end, and the third pad is located away from the fourth end.
  • part of the third pad in the redistribution layer is located close to the second end, and the second pad is located away from the second end; another part of the redistribution layer is located close to the second end.
  • the third pad in the redistribution layer is located near the fourth end, and the second pad is located away from the fourth end.
  • the second pad can also be provided At a greater distance from the first pad.
  • each of the redistribution layers further includes a first region for conductively connecting to the first pad
  • the second pad and the third pad in part of the redistribution layer are located on one side of the first area; the second pad and the third pad in the other part of the redistribution layer are located on one side of the first area.
  • Third pads are located on both sides of the first area.
  • the first area 213 is in contact with the conductive pillars 207 and is located around the conductive pillars to achieve the first The pad and the redistribution layer are electrically connected.
  • the first region 213 is located in the via hole 204 .
  • the material of the first region 213 may be the same as or different from the material of the redistribution layer 206 , or may be any suitable conductive material.
  • the relative positional relationship between the second pad and the third pad is different.
  • the second pad in part of the package structure, is located between the conductive pillar and the third pad, and in another part of the package structure
  • the conductive pillar 207 is located between the second pad 211 and the third pad 212.
  • the position of the first region 213 can be set between the corresponding second pad 211 and the third pad 212, or it can arranged on one side of the corresponding second pad 211 and third pad 212 .
  • the conductive pillar 207 and/or the first region 213 is disposed between the corresponding second pad 211 and the third pad 212, the corresponding second pad 211 and the third pad Partition walls can be set up between 212.
  • FIG. 4 only shows the rewiring one by one near the first edge 20a. layer, and a rewiring layer near the second edge 20b; and, Figures 3 and 4 only schematically show the rewiring layer near the first edge 20a, and the corresponding rewiring layer near the second edge.
  • the distance between the rewiring layers at position 20b does not represent the distance between the two in actual applications, and the actual distance can be set according to actual needs.
  • the same set of probe cards can be used to implement the above two tests of different operating speeds. , compared with using two sets of probe cards for testing separately, it saves testing costs and testing time, and reduces production cycle and manufacturing costs.
  • a semiconductor device including: a semiconductor functional structure and a packaging structure as described in the above embodiments of the disclosure.
  • the semiconductor device further includes: a substrate; a plurality of stacked die; each die includes a semiconductor functional structure and a packaging structure located on the semiconductor functional structure; each die passes Leads on the third pad in the package structure are electrically connected to the substrate.
  • a method for manufacturing a packaging structure includes the following steps:
  • Step S501 Provide a semiconductor functional structure, the surface of which is provided with an interconnection layer;
  • Step S502 Form an isolation layer with a plurality of via holes, the isolation layer covers the surface of the interconnect layer, the via holes expose part of the interconnect layer, and the part of the interconnect layer exposed by each via hole serves as One first pad, forming N first pads; the first pads are used to perform the first type of test; the N is a positive integer greater than 1;
  • Step S503 After completing the first type of test, form N rewiring layers on the N first pads and the isolation layer, and each rewiring layer covers the isolation layer and is connected to the N rewiring layers.
  • a corresponding first pad among the first pads is electrically connected; some of the first pads are arranged side by side in the first direction close to the first edge of the semiconductor functional structure, and the other part of the first pads are The pads are arranged side by side in the first direction close to the second edge of the semiconductor functional structure, and the first edge and the second edge are two opposite edges of the semiconductor functional structure;
  • Step S504 Form a first insulating layer covering and exposing part of the redistribution layer, and the exposed part of the redistribution layer serves as a second pad and a third pad; wherein each of the second pads The offset direction and offset distance of the center point of the corresponding first pad are equal; the relative position between the second pad and the third pad in the partial redistribution layer is equal to The relative positions between the second pad and the third pad in another part of the redistribution layer are different; the second pad is used for the second type of test, and the third pad is used for In order to perform functional interactions corresponding to the content of the second type of test; the operating speed of the semiconductor functional structure when performing the first type of test is lower than the operating speed when performing the second type of test.
  • 6a to 6d are schematic cross-sectional views of a manufacturing process of a packaging structure provided by an embodiment of the present disclosure. The manufacturing method of the packaging structure provided by the embodiment of the present disclosure will be described in detail below with reference to FIG. 5 and FIG. 6 a to FIG. 6 d.
  • a semiconductor functional structure 600 which includes a semiconductor functional layer 601 and an interconnection layer 602.
  • the providing a semiconductor functional structure 600 includes: providing a substrate (not shown in Figure 6a), forming a semiconductor functional layer 601 on the substrate, and forming an interconnect layer 602 on the semiconductor functional layer.
  • the semiconductor functional layer 601 includes a single layer or a multi-layer film, and the semiconductor functional layer has a conductive layer and/or a dielectric layer.
  • the interconnection layer 602 is used to extract electrical signals from the functional structures in the semiconductor functional layer 601 to run the functional structures.
  • the interconnect layer 602 includes a top metal layer that is used not only to extract electrical signals from the functional structure but also to support the semiconductor functional structure 600 .
  • the method further includes: removing part of the interconnection layer 602 and reducing the area of the interconnection layer to reduce parasitic capacitance generated by the interconnection layer.
  • Figure 6a shows a cross-sectional rendering of a section after the interconnection layer 602 has been partially removed.
  • the parts in the interconnection layer are not cut off, but interconnected, that is, in other sections , the parts in the interconnection layer may be continuous.
  • an isolation layer 603 is formed on the interconnection layer 602.
  • the constituent materials of the isolation layer include but are not limited to ethyl orthosilicate.
  • the isolation layer is removed to form a plurality of via holes 604 .
  • the via hole exposes a portion of the interconnect layer, and each via hole exposes a portion of the interconnect layer as a first pad 605 to form N first pads 605 .
  • the via hole 604 may be cylindrical, inverted trapezoidal, or any suitable shape, and the cross-sectional area of the via hole includes the area of the orthographic projection of the via hole on the plane where the interconnected layer is located. , for example, when the via hole is an inverted trapezoid, the cross-sectional area of the first pad is the minimum cross-sectional area of the via hole.
  • the first pad 605 can be used to perform the first type of test; it can also be used to perform functional interactions corresponding to the contents of the first type of test, such as drawing out bonding wires and performing signal interaction.
  • the first type of tests can be understood as tests performed on semiconductor functional structures at lower operating speeds. It should be noted that in memory, the operating speed refers to the read and write speed of the memory.
  • step S503 referring to FIG. 6c, a rewiring layer 606 is formed in the isolation layer 603 and the via hole 604.
  • the specific method of forming the redistribution layer 606 on the isolation layer 603 includes: forming a new conductor pattern on the isolation layer by exposure and development, and then using electroplating technology to form a redistribution layer 606 according to the new conductor pattern.
  • a wiring layer, the rewiring layer includes a new wire path, and the new wire path is conductively connected to the interconnection layer.
  • each redistribution layer 606 covers the isolation layer 603 and is electrically connected to a corresponding first pad 605 among the N first pads; it should be noted that the first pad 605 includes a first portion and a first pad 605. A pad and a second part of the first pad, the first part of the first pad is juxtaposed along the first direction at a position close to the first edge of the semiconductor functional structure, and the second part of the first pad is arranged along the first edge of the semiconductor functional structure. The first direction is juxtaposed at a position close to the second edge of the semiconductor functional structure, and the first edge and the second edge are two opposite edges of the semiconductor functional structure.
  • step S504 referring to FIG. 6d, a first insulating layer 608 is formed on the redistribution layer 606.
  • the exposed portion of the redistribution layer includes a second pad 611 and a third pad 612, wherein the The second pad 611 is used to perform a second type of test, and the third pad 612 is used to perform functional interactions corresponding to the content of the second type of test.
  • the second type of test can be understood as testing the semiconductor functional structure. Some tests performed at higher operating speeds.
  • the positions of the second pad 611 and the third pad 612 can be selected and set according to actual needs.
  • the first insulating layer not only exposes part of the redistribution layer to form the second pad and the third pad, but also exposes the redistribution layer located above the first pad.
  • the density of the second insulating layer may be less than or equal to the first insulating layer; in other embodiments, the first insulating layer It also covers the bottom surface and sidewalls of the groove 609 formed by the redistribution layer, and subsequently the second insulating layer 610 is formed in the groove 609 formed by the first insulating layer.
  • the packaging structure further includes conductive pillars.
  • the method further includes: after completing the first type of test, forming conductive pillars on the first pad; Forming a redistribution layer on the first pad and the isolation layer includes: forming a redistribution layer on the conductive pillar and the isolation layer, and the redistribution layer is connected to the interconnection through the conductive pillar. layer conductive connection.
  • the relative positional relationship between the second pad and the third pad can be set according to actual needs.
  • the second pad is located between the conductive pillar and the third pad in the packaging structure, and/or, In the packaging structure, the conductive pillar is located between the second pad 611 and the third pad 612. Based on this, the relative position between the second pad 611 and the third pad 612 in the partial redistribution layer 606 is different from that of the other pads.
  • the relative positions between the second pad 611 and the third pad 612 in a part of the redistribution layer 606 may be the same or different. This has been mentioned before and will not be described again here.
  • the offset direction and offset distance of the center point of each second pad relative to the center point of the corresponding first pad are equal. In this way, the same set of probe cards can be used to perform the first type of test. Then, after moving a certain distance in a certain direction from the center point of the first pad, it can be aligned with the center points of all the second pads, that is, the probe card can directly perform the second step on all the second pads. class testing without the need to replace new probe cards.
  • a packaging structure compatible with two types of tests is adopted, so that the semiconductor functional structure can undergo different types of tests at different process stages; however, it should be noted that when testing the packaging structure When performing layout design, it is necessary to reserve via holes for the rewiring layer on the top metal layer to ensure that when a rewiring layer needs to be added, there is no need to change the top metal layer or any other photoresist and process.
  • the disclosed devices and methods can be implemented in a non-target manner.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the components shown or discussed are coupled to each other, or directly coupled.
  • the units described above as separate components may or may not be physically separated.
  • the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units; Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • N first pads are provided in the top metal layer to perform testing on the semiconductor functional structure at the first operating speed; wherein part of the first pads are along The first pads are arranged side by side in a first direction close to the first edge of the semiconductor functional structure, and the other part of the first pads are arranged side by side in a first direction close to the second edge of the semiconductor functional structure; in the first After the test at the second operating speed is completed, a second pad corresponding to the first pad is provided in the rewiring layer on the first pad to execute the semiconductor functional structure at the second operating speed.
  • the relative position between the second pad and the third pad in part of the redistribution layer is different from the second pad and the second pad in the other part of the redistribution layer.
  • the relative positions between the third pads are different; here, by setting the center point of each second pad to be offset in the same direction and by an equal distance relative to the center point of the corresponding first pad, such that The N first pads and the N second pads maintain exactly the same relative position; at the same time, by setting the positions between the second pads and the third pads at different edge positions to be different, such that the positions between the two pads are
  • the rewiring layer at each edge position maintains a large fault tolerance rate and can be close to the edge but not beyond the edge.

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Abstract

本公开实施例提出了一种封装结构及其制作方法、半导体器件，封装结构包括：N个第一衬垫，每一第一衬垫由一个过孔暴露的互连层构成；N个重布线层，每一重布线层覆盖隔离层并与N个第一衬垫中一相应第一衬垫电连接；部分第一衬垫沿第一方向并列设置在靠近半导体功能结构第一边缘的位置处，另一部分第一衬垫沿第一方向并列设置在靠近半导体功能结构第二边缘的位置处；每一重布线层被暴露出的部分区域均包括第二衬垫和第三衬垫；其中，每一第二衬垫的中心点相对于对应的第一衬垫的中心点的偏移方向和偏移距离均相等；部分重布线层中第二衬垫和第三衬垫之间的相对位置与另一部分重布线层中的第二衬垫和第三衬垫之间的相对位置不同。

Description

封装结构及其制作方法、半导体器件
相关的交叉引用
本公开基于申请号为202210619084.1、申请日为2022年06月01日、发明名称为“封装结构及其制作方法、半导体器件”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，涉及但不限于一种封装结构及其制作方法、半导体器件。
背景技术
随着电子设备普及率快速提升、电子设备市场的蓬勃发展，越来越要求电子产品在具有高性能、多功能、高可靠性以及便捷性的同时要向着小型化、薄型化的方向演进。这样的需求对半导体器件的封装提出了更好、更轻、更薄、封装密度更高、更好的电性能和热性能、更高的可靠性以及更高的性价比要求。
为保证半导体器件的性能满足对应要求，需要在封装结构上制备用于测试和执行功能交互的端口。
发明内容
基于此，为解决相关技术问题中的一个或多个，本公开实施例提出了一种封装结构及其制作方法、半导体器件。
根据本公开实施例的一方面，提供一种封装结构，包括：
具有多个过孔的隔离层，所述隔离层覆盖互连层表面，所述过孔暴露部分所述互连层，所述互连层设置在半导体功能结构的表面；
N个第一衬垫，每一第一衬垫由一个所述过孔暴露的所述互连层构成；所述N为大于1的正整数；
N个重布线层，每一重布线层覆盖所述隔离层并与所述N个第一衬垫中一相应所述第一衬垫电连接；部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第一边缘的位置处，另一部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第二边缘的位置处，所述第一边缘与所述第二边缘为所述半导体功能结构相对的两个边缘；
第一绝缘层，覆盖且暴露出每一所述重布线层的部分区域；
每一所述重布线层被暴露出的部分区域均包括第二衬垫和第三衬垫；其中，每一所述第二衬垫的中心点相对于对应的所述第一衬垫的中心点的偏移方向和偏移距离均相等；部分所述重布线层中所述第二衬垫和所述第三衬垫之间的相对位置与另一部分所述重布线层中的所述第二衬垫和所述第三衬垫之间的相对位置不同；所述第一衬垫和第二衬垫分别用于所述半导体功能结构处于不同运行速度时的测试，所述第三衬垫用于执行与所述第二衬垫测试的内容对应的功能交互。
上述方案中，所述N个重布线层中每一所述重布线层包括的所述第二衬垫与所述第三衬垫均沿第二方向并列设置，所述第二方向与所述第一方向垂直。
上述方案中，每一所述第二衬垫的中心点在所述互连层所在平面的正投影相对于对应的所述第一衬垫的中心点向所述第二方向偏移第一距离。
上述方案中，每一所述重布线层在所述互连层所在平面的正投影的形状均包括长条状。
上述方案中，部分所述第一衬垫靠近所述第一边缘的第一端与部分所述重布线层靠近所述第一边缘的第二端沿第三方向基本齐平，第三方向与所述第一方向和所述第二方向均垂直；
另一部分所述第一衬垫靠近所述第二边缘的第三端与另一部分所述重布线层靠近所述第二边缘的第四端沿所述第三方向基本齐平。
上述方案中，部分所述重布线层中的所述第二衬垫位于靠近所述第二端的位置处，所述第三衬垫位于远离所述第二端的位置处；
另一部分所述重布线层中的所述第二衬垫位于靠近所述第四端的位置处，所述第三衬垫位于远离所述第四端的位置处。
上述方案中，每一所述重布线层还包括用于与所述第一衬垫进行导电连接的第一区域；
部分所述重布线层中的所述第二衬垫和所述第三衬垫均位于所述第一区域的一侧；另一部分所述重布线层中的所述第二衬垫和所述第三衬垫均位于所述第一区域的两侧。
上述方案中，所述重布线层与对应的所述第一衬垫直接接触；
或者，
所述封装结构还包括：导电柱，位于所述重布线层与对应的所述第一衬垫之间，所述重布线层通过所述导电柱与所述互连层导电连接。
上述方案中，所述封装结构包括所述导电柱，所述导电柱的数量多括多个，多个导电柱沿第一方向并列设置。
上述方案中，所述重布线层与对应的所述第一衬垫直接接触，所述封装结构还包括：
第二绝缘层，位于每一所述重布线层围成的凹槽内，所述第二绝缘层 的材料的硬度小于所述重布线层的材料的硬度。
根据本公开实施例的另一方面，提供了一种半导体器件，包括：半导体功能结构及如本公开上述实施例中所述的封装结构。
上述方案中，所述半导体器件还包括：
基板；
多个堆叠设置的裸片；每一所述裸片包括半导体功能结构及位于所述半导体功能结构上的封装结构；
每一裸片通过所述封装结构中的第三衬垫上的引线电连接到所述基板上。
根据本公开实施例的又一方面，提供了一种封装结构的制作方法，包括：
提供半导体功能结构，所述半导体功能结构的表面设置有互连层；
形成具有多个过孔的隔离层，所述隔离层覆盖互连层表面，所述过孔暴露部分所述互连层，每一所述过孔暴露的部分所述互连层作为一个第一衬垫，形成N个第一衬垫；所述第一衬垫用于进行第一类测试；所述N为大于1的正整数；
在完成所述第一类测试后，在所述N个第一衬垫及所述隔离层上形成N个重布线层，每一重布线层覆盖所述隔离层并与所述N个第一衬垫中一相应所述第一衬垫电连接；部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第一边缘的位置处，另一部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第二边缘的位置处，所述第一边缘与所述第二边缘为所述半导体功能结构相对的两个边缘；
形成覆盖且暴露出部分所述重布线层的第一绝缘层，被暴露的部分所述重布线层作为第二衬垫和第三衬垫；其中，每一所述第二衬垫的中心点相对于对应的所述第一衬垫的中心点的偏移方向和偏移距离均相等；部分重布线层中的第二衬垫和所述第三衬垫之间的相对位置与另一部分所述重布线层中的所述第二衬垫和所述第三衬垫之间的相对位置不同；所述第二衬垫用于进行第二类测试，所述第三衬垫用于执行与所述第二类测试的内容对应的功能交互；所述半导体功能结构在进行所述第一类测试时的运行速度低于在进行所述第二类测试时的运行速度。
本公开各实施例中，通过在顶层金属层中设置N个第一衬垫，用于对所述半导体功能结构执行处于第一种运行速度时的测试；其中，部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第一边缘的位置处，另一部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第二边缘的位置处；在第一种运行速度时的测试完成后，在第一衬垫上的重布线层中设置与第一衬垫一一对应的第二衬垫，用于对所述半导体功能结构执行处于第二种运行速度时的测试；其中，部分所述重布线层中所述第二衬垫和所述第三衬垫之间的相对位置与另一部分所述重布线层中的 所述第二衬垫和所述第三衬垫之间的相对位置不同；这里，通过将每一第二衬垫的中心点设置为相对于对应的第一衬垫的中心点偏移相同的方向和偏移相等的距离，使得N个第一衬垫和N个第二衬垫保持完全相同的相对位置；同时，通过将位于不同边缘位置处的第二衬垫和第三衬垫之间的位置设置为不同，使得位于两个边缘位置处的重布线层保有较大的容错率，均可以靠近边缘但不超出边缘，如此，可以保证第一衬垫和第二衬垫均处于有利于节省总面积的有利位置，同时还可以利用同一套探针卡来实现上述两种不同运行速度的测试，相较于使用两套探针卡分别进行测试，节省了测试成本和测试时间，降低了生产周期和制造成本。
附图说明
图1为本公开实施例中提供的一种封装结构的剖面示意图；
图2a为本公开实施例中提供的另一种封装结构的剖面示意图；
图2b为图2a的俯视示意图；
图2c为本公开实施例中提供的一种具有导电柱的封装结构的剖面示意图；
图3本公开实施例中提供的第一衬垫和第二衬垫的相对位置示意图；
图4为本公开实施例中提供的第二衬垫和第三衬垫的相对位置示意图；
图5为本公开实施例中提供的一种封装结构的制造方法的流程示意图；
图6a-6d为本公开实施例中提供的一种封装结构的制造过程的示意图。
附图标记说明
101-顶层金属层；102-第一类衬垫；103-重布线层；104-第二类衬垫；105-第三类衬垫；200-半导体功能结构；201-半导体功能层；202-互连层；203-隔离层；204-过孔；205-第一衬垫；2051-第一部分第一衬垫；2052-第二部分第一衬垫；2051a-第一衬垫的第一端；2052a-第一衬垫的第三端；206-重布线层；206a-重布线层的第二端；206b-重布线层的第四端；207-导电柱；208-第一绝缘层；209-凹槽；210-第二绝缘层；211-第二衬垫；212-第三衬垫；213-第一区域；600-半导体功能结构；601-半导体功能层；602-互连层；603-隔离层；604-过孔；605-第一衬垫；606-重布线层；608-第一绝缘层；609-凹槽；610-第二绝缘层；611-第二衬垫；612-第三衬垫。
在上述附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
具体实施方式
下面将结合附图和实施例对本公开的技术方案进一步详细阐述。虽然 附图中显示了本公开的示例性实施方法，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻的理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下列段落中参照附图以举例方式更具体的描述本公开各实施例。根据下面说明和权利要求书，本公开的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本公开实施例的目的。
可以理解的是，本公开的“在……上”、“在……之上”和“在……上方”的含义应当以最宽方式被解读，以使得“在……上”不仅表示其“在”某物“上”且其间没有居间特征或层(即直接在某物上)的含义，而且还包括在某物“上”且其间有居间特征或层的含义。
在本公开实施例中，术语“A与B相连”包含A、B两者直接接触的情形，或者A和B通过中间导电结构间接接触的情形；术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
在本公开实施例中，术语“层”是指包括具有厚度的区域的材料部分。层可以在结构的下方表面或上方表面上延伸，其面积可以小于等于所在的延伸表面。需要说明的是，本公开实施例所记载的技术方案之间，在不冲突的情况下，可以任意组合。
本公开实施例涉及的半导体功能结构是将被用于后续制程以形成最终的半导体器件的一部分，是实现半导体器件的主要功能的核心部分。这里，所述最终的半导体器件可以包括但不限于存储器。
在半导体器件如，动态随机存取存储器(DRAM，Dynamic Random Access Memory)的封装结构的设计中，衬垫(还可以被称为焊盘，英文表达为PAD)有两种设置方式：一种是顶层金属开窗的方式；另一种是重布线层(RDL，Redistribution Layer)开窗的方式。
所述顶层金属开窗是指在半导体功能结构的顶层金属层上形成钝化层(Passivation)或绝缘层，以保护半导体功能结构不被破坏；然后，在所述钝化层或绝缘层上形成开窗区域，以暴露部分顶层金属层，形成衬垫。其中，可以在该衬垫上进行探针卡扎针测试，以实现对半导体功能结构的电学性能的测试；也可以在该衬垫上进行键合线(Bonding wire)的引出，以实现对半导体功能结构的电引出。
所述重布线层开窗是指在半导体功能结构的顶层金属层上形成重布线层，在重布线层上形成钝化层或绝缘层，然后，在所述钝化层或绝缘层上形成开窗区域，以暴露出部分重布线层，形成并列设置的两个衬垫。其中，该两个衬垫中的一个用于进行探针卡扎针测试，另一个用于在该衬垫上进行键合线的引出。这里，重布线层在半导体器件中可以起到调整衬垫位置的作用，还能起到增强电源地的供电网络的作用。
可以理解的是，顶层金属层比较薄，且下面有垫片结构，能够支持在同一片开窗的金属区域上，先经过探针卡扎针测试，再到封装厂进行键合线封装，而不影响封装打线的成品率；重布线层的材料一般是金属，重布线层相较于顶层金属层比较厚，经过探针卡扎针会有比较深且表面粗糙的针痕，这个针痕会影响封装打线的成品率，因此重布线层中用于测试和用于引出键合线的衬垫需要分开。封装结构中无论采用上述哪种开窗方式对半导体器件的功能并没有太大的影响，重布线层开窗有利于性能的提升，但需要增加生产周期和生产成本。
相关技术中，一般会根据半导体器件的实际需求选择以上两种开窗方式中的一种来设计封装结构。然而，实际应用中，在半导体器件的生产过程中，需求并不是单一的，经常存在多需求的情况。以下给出几种多需求的示例：
示例性的，在半导体器件(或称为“产品”)量产化之前，有较长的功能调试过程，在该调试过程中，测试是在半导体功能结构运行速度较低的情况下完成的，此时，仅需要采用顶层金属开窗方式，即可以完成对半导体功能结构的封装、测试。而在产品的制程工艺成熟后，需要测试半导体功能结构在高速运行下的状态时，则需要采用重布线层开窗方式进行封装测试。
基于此，本公开实施例提供了一种封装结构，参考图1，所述封装结构中包括顶层金属开窗方式和重布线层开窗方式；其中，顶层金属开窗方式中，在顶层金属层101中设置有第一类衬垫102；该第一类衬垫102可以用于执行低速测试和引出键合线；重布线层开窗方式中，在重布线层103中设置有两类衬垫(第二类衬垫104和第三类衬垫105)，第二类衬垫104用于执行高速测试，第三类衬垫105用于引出键合线。
这里，一方面，在利用第一类衬垫102执行低速测试时，测试探针卡需要同时打在所有第一类衬垫102的中心点上，在利用第二类衬垫104执行高速测试时，测试探针卡需要同时打在所有第二类衬垫104的中心点上。然而，从图1可以看出第一类衬垫102和第二衬垫104处于封装结构不同的层，不同层中的各第一类衬垫102和各第二衬垫104的相对位置不同。这样，为了满足低速测试和高速测试的需求，不得不制作两套测试探针卡，而制作两套测试探针卡将大大的增加测试成本和测试时间。
另一方面，在测试的点比较多时，靠近半导体功能结构的一个边缘的位置处可能摆放不下所有的第一类衬垫102，此时需要将第一类衬垫分别设置在半导体功能结构的相对设置的两个边缘的位置处，相应地，重布线层103也需要分别设置在半导体功能结构的相对的两个边缘的位置处，但由于第二类衬垫104和第三类衬垫105一起占用的面积比第一类衬垫102占用的面积大。此时，至少一个边缘的位置处的重布线层103容易超出边缘。
基于此，为了进一步解决上述问题，本公开实施例中又提供了一种封 装结构及其制作方法以及半导体器件，其中，所述封装结构，包括：具有多个过孔的隔离层，所述隔离层覆盖互连层表面，所述过孔暴露部分所述互连层，所述互连层设置在半导体功能结构的表面；N个第一衬垫，每一第一衬垫由一个所述过孔暴露的所述互连层构成；所述N为大于1的正整数；N个重布线层，每一重布线层覆盖所述隔离层并与所述N个第一衬垫中一相应所述第一衬垫电连接；部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第一边缘的位置处，另一部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第二边缘的位置处，所述第一边缘与所述第二边缘为所述半导体功能结构相对的两个边缘；第一绝缘层，覆盖且暴露出每一所述重布线层的部分区域；每一所述重布线层被暴露出的部分区域均包括第二衬垫和第三衬垫；其中，每一所述第二衬垫的中心点相对于对应的所述第一衬垫的中心点的偏移方向和偏移距离均相等；部分所述重布线层中所述第二衬垫和所述第三衬垫之间的相对位置与另一部分所述重布线层中的所述第二衬垫和所述第三衬垫之间的相对位置不同；所述第一衬垫和第二衬垫分别用于所述半导体功能结构处于不同运行速度时的测试，所述第三衬垫用于执行与所述第二衬垫测试的内容对应的功能交互。
需要说明的是，本公开实施例中涉及的第一方向与半导体功能结构的表面平行，本公开实施例中涉及的第二方向平行于所述半导体功能结构，且垂直于所述第一方向，本公开实施例中涉及的第三方向与第一方向和第二方向均垂直。在一些实施例中，第一方向可以与X轴方向平行，第二方向可以与Y轴方向平行，第三方向与Z轴方向平行。
这里，参考图2a，所述封装结构包括：基底(图2a中未示出)，所述基底的组成材料可以包括硅(Si)、锗(Ge)、锗化硅(SiGe)、绝缘体上硅(Silicon on Insulator，SOI)或者绝缘体上锗(Germanium on Insulator，GOI)。
半导体功能结构200，所述半导体功能结构200位于基底上；具体地，所述半导体功能结构200包括半导体功能层201和位于所述半导体功能层201表面上的互连层202，根据实际需求，在所述半导体功能层201中可以设置多种功能结构；相应地，所述互连层202用于将半导体功能层201中功能结构的电信号引出，以运行所述功能结构。在一些实施例中，互连层202包括顶层金属层，顶层金属层不仅用于将功能结构的电信号引出，还用于支撑半导体功能结构200。
需要说明的是，后续制程中形成的重布线层连接的任何信号都均连接于所述互连层202，即保证在没有重布线层的情况下，半导体功能结构200的功能是完整的。图2a中展示的互连层202是被去除部分后的某一截面的剖面效果图，实际应用中，互连层中的各部分并不是截断的，而是互连的，即在其他截面上，互连层中的各部分可能是连续的。
隔离层203，覆盖互连层202表面，用于在部分区域隔离互连层202和 后续形成的重布线层206。隔离层203中设置有过孔204，过孔204暴露部分互连层202。其中，过孔204的形状可以是圆柱形，也可以是倒梯形，或者是任何合适的形状；隔离层203的组成材料包括但不限于正硅酸乙酯(TEOS)。
由一个所述过孔204暴露的所述互连层202构成的第一衬垫205；隔离层203内可包含多个过孔204，从而形成多个被过孔204暴露的所述第一衬垫205的数量包括多个。这里，所述第一衬垫205一方面可以用于进行第一类测试；另一方面还可以用于执行与所述第一类测试的内容对应的功能交互。
示例性的，所述第一类测试可以理解为对半导体功能结构执行较低运行速度时的一些测试。需要说明的是，在存储器中，所述运行速度指的是存储器的读写速度。所述执行与所述第一类测试的内容对应的功能交互可以理解为在第一衬垫上引出键合线。也就是说，在执行第一类测试时，第一衬垫205可以用于与探针卡接触，且探针卡中的多个探针与N个第一衬垫一一对应，以实现互连层与其他测试系统的电连接。
实际应用中，在测试的点比较多时，靠近半导体功能结构的一个边缘的位置处可能摆放不下所有的第一衬垫205，此时可以将第一衬垫205分别设置在半导体功能结构的相对设置的两个边缘的位置处，参考图2b，N个第一衬垫205中，N个所述第一衬垫分为两个部分，即第一部分第一衬垫2051和第二部分第一衬垫2052；其中，第一部分第一衬垫2051包括M1个第一衬垫，M1个第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第一边缘20a的位置处；第二部分第一衬垫2052包括M2个第一衬垫，M2个第一衬垫沿所述第一方向并列设置在靠近所述半导体功能结构第二边缘20b的位置处，所述第一边缘20a与所述第二边缘20b为所述半导体功能结构相对的两个边缘。这里，M1+M2＝N。
需要说明的是，图2a为第一衬垫205与重布线层206直接接触的封装结构的局部剖面示意图；图2b为一种封装结构的俯视图的示例，其中，在图2b中为了更清楚的展示第一衬垫的位置排布，隐去了其它层；图2c为第一衬垫205通过导电柱207与重布线层206间接接触的封装结构的局部剖面示意图。
在一些实施例中，第一部分第一衬垫2051的数量和第二部分第一衬垫2052的数量可以相同，也可以不同。
具体地，图2b中六个第一衬垫分为第一部分第一衬垫2051和第二部分第一衬垫2052，第一部分第一衬垫2051包括三个第一衬垫，沿第一方向并列设置在靠近所述半导体功能结构第一边缘20a的位置处；第二部分第一衬垫2052包括三个第一衬垫，沿所述第一方向并列设置在靠近所述半导体功能结构第二边缘20b的位置处。
参考图2a，位于所述隔离层203表面上和所述过孔204上的N个重布 线层206。这里，每一重布线层206覆盖所述隔离层203；并且，N个重布线层206与所述N个第一衬垫205中相应所述第一衬垫205直接接触。
重布线层206和第一衬垫205之间既可以直接接触(参考图2a)；也可以间接接触，即在重布线层206与第一衬垫205之间设置导电材料层(参考图2b、图2c，例如，导电柱207)。所述导电柱207的组成材料可以与重布线层206的组成材料相同，也可以不同。需要说明的是，所述导电柱207的高度可以小于或等于所述过孔204的深度，图2c中示出的导电柱207的高度等于所述过孔204的深度的情况。
在一些实施例中，所述封装结构包括所述导电柱207，所述导电柱的数量包括多个，多个导电柱沿第一方向并列设置。
上述实施例中，同一个过孔204内的所述导电柱207的数量可以包括一个，也可以包括多个，相邻导电柱207之间被绝缘材料隔离；相应地，每一所述导电柱207对应一第一衬垫205，也就是说，当导电柱207的数量为多个时，同一过孔204的底部具有多个第一衬垫205。
可以理解的是，导电柱207的数量包括多个时，多个导电柱207均与所述重布线层206以及互连层202连接，这样，可以增加重布线层206与互连层202电连接的可靠性。
可以理解的是，通过在过孔的底面积不变的情况下，设置多个第一衬垫205，有利于减小同一过孔204底部所有第一衬垫205的总面积，进而减小第一衬垫205与周边导电材料之间的寄生电容，有利于进一步优化信号传输性能。
参考图2a，位于所述重布线层206上的第一绝缘层208。
所述第一绝缘层208覆盖重布线层206的表面，被暴露的部分所述互连层202上的重布线层206的厚度与隔离层203表面上的重布线层206的厚度可以相同。在一些实施例中，过孔204的径宽大于两倍重布线层206的厚度时，重布线层206覆盖过孔204的侧壁和底部，重布线层206围成有凹槽209。
在一些实施例中，参考图2a，所述重布线层206与对应的所述第一衬垫205直接接触，所述封装结构还包括：第二绝缘层210，位于每一所述重布线层围成的凹槽209内，所述第二绝缘层210的材料的硬度小于所述重布线层206的材料的硬度，如此，一方面可以减小封装结构的应力，增加封装结构的可靠性；另一方面相较于采用重布线层206填充凹槽209，利用第二绝缘层210材料填充凹槽209可以避免产生更多的寄生电容。
在一些实施例中，第二绝缘层210与第一绝缘层208可以为一体结构，也可以为分体结构，当两者为分体结构时，两者的材料可以不同。图2a中示出的是第二绝缘层210与第一绝缘层208为一体结构的情况。所述第二绝缘层210的组成材料包括但不限于聚酰亚胺(PI)。
参考图2a，N个重布线层206中至少部分所述重布线层206被暴露出 的部分区域包括第二衬垫211和第三衬垫212。
这里，N个重布线层206中的每一个重布线层206中均设置一个第二衬垫211和一个第三衬垫212；换言之，N个第二衬垫211和N个第三衬垫212一一对应。第二衬垫211用于进行第二类测试，所述第三衬垫212用于执行与所述第二类测试的内容对应的功能交互。所述第二类测试可以理解为对半导体功能结构在较高运行速度时执行的一些测试。所述执行与第二类测试的内容对应的功能交互可以理解为在第三衬垫上引出键合线并进行信号交互。
需要说明的是，第二衬垫211与第三衬垫212之间可以是连续设置的，即第二衬垫211与第三衬垫212之间并未设置隔墙；也可以是间隔设置的，即第二衬垫211与第三衬垫212之间设置有隔墙。
这里，在第二衬垫211与第三衬垫212之间为连续设置时，可以在执行测试的过程中，避免探针出现未瞄准的情况下，隔墙对探针卡造成的损伤，从而延长了探针卡的使用寿命；同时，减少杂质的产生，从而提高了测试效率；另外，减少探针卡对隔墙的破坏，进而从整体上提高了封装结构的可靠性。
而在第二衬垫211与第三衬垫212之间设置有隔墙时，可以在执行测试的过程中，提高机台对每个衬垫的识别精度。
以下实施例中，以第二衬垫211与第三衬垫212之间设置有隔墙为例进行说明，但可以理解的是，以下关于隔墙的描述仅用于说明本公开，并不用来限制本公开的范围。
为了便于探针卡在执行第二类测试时，探针卡中的每一探针均能与第二衬垫相对应，本公开实施例中，将每一所述第二衬垫211的中心点相对于对应的所述第一衬垫205的中心点，偏移相同的方向和偏移相等距离，这样，可以使得N个第一衬垫和N个第二衬垫保持完全相同的相对位置，如此，可以使得同一套探针卡在执行第一类测试后，从第一衬垫205的中心点向一定的方向移动一定的距离后能够与全部的第二衬垫211的中心点均对准，即探针卡可以直接对全部需要测试的第二衬垫执行第二类测试，而无需更换新的探针卡。
同时，通过将位于不同边缘位置处的第二衬垫211和第三衬垫212之间的位置设置为不同，可实现均可以靠近边缘但不超出边缘。以下，通过一个示例具体说明第一衬垫和第二衬垫的位置设置方式。
在一些实施例中，所述N个重布线层中每一所述重布线层包括的所述第二衬垫与所述第三衬垫均沿第二方向并列设置，所述第二方向与所述第一方向垂直。
这里，第一衬垫205分布在半导体功能结构的相对设置的两个边缘的位置处，示例性的，参考图3，图3中箭头的左边示出了第一衬垫205的排布示例，该示例与图2b相同，这里不再赘述。
同样，N个所述第二衬垫分为两个部分，即第三部分和第四部分；其中，第三部分包括M1个第二衬垫；第四部分包括M2个第二衬垫；该第三部分中的M1个第二衬垫沿第一方向并列设置在靠近所述半导体功能结构第一边缘的位置处；该第四部分中的M2个第二衬垫沿所述第二方向并列设置在靠近所述半导体功能结构第二边缘的位置处。同样，N个所述第三衬垫分为两个部分，即第五部分和第六部分；其中，第五部分包括M1个第三衬垫；第六部分包括M2个第三衬垫；该第五部分中的M1个第三衬垫与M1个第二衬垫沿第二方向并列设置在靠近所述半导体功能结构第一边缘的位置；该第六部分中的M2个第三衬垫和M2个第二衬垫沿第二方向并列设置在靠近所述半导体功能结构第二边缘的位置处。
示例性的，图3中箭头的右边示出了重布线层206的排布示例，具体地：六个重布线层206分为两个部分，每个部分中包括三个重布线层，每一部分中的三个重布线层206均沿X轴方向并列排布，每一个重布线层206中包括一个第二衬垫211与对应的第三衬垫212，该第二衬垫211和第三衬垫212均沿Y轴方向并列设置；图3中的虚线示出了第一衬垫205的中心点所在的直线。
在一些实施例中，所述第一衬垫205、所述第二衬垫211、第三衬垫212均为长条状，每一所述重布线层206在所述互连层所在平面的正投影的形状包括长条状。每一第一衬垫205沿第一方向上的宽度与每一第二衬垫211、第三衬垫212沿第一方向上的宽度可以相同，每一所述第一衬垫205沿第二方向上的长度与每一所述第二衬垫211、第三衬垫212沿第二方向上的长度可以不同。
在一些实施例中，每一所述第二衬垫的中心点在所述互连层所在平面的正投影相对于对应的所述第一衬垫的中心点向所述第二方向偏移第一距离。
示例性的，参考图3，第一边缘20a处的每一所述第二衬垫的中心点O 2相对于对应的所述第一衬垫的中心点O 1的沿Y轴方向偏移第一距离H1；同时，第二边缘20b处的每一所述第二衬垫的中心点O 2相对于对应的所述第一衬垫的中心点O 1的沿Y轴方向偏移第一距离H1。
在一些实施例中，部分所述第一衬垫靠近所述第一边缘的第一端与部分所述重布线层靠近所述第一边缘的第二端沿第三方向基本齐平，第三方向与所述第一方向和所述第二方向均垂直；
另一部分所述第一衬垫靠近所述第二边缘的第三端与另一部分所述重布线层靠近所述第二边缘的第四端沿所述第三方向基本齐平。
在一些实施例中，部分所述重布线层中的所述第二衬垫位于靠近所述第二端的位置处，所述第三衬垫位于远离所述第二端的位置处；
另一部分所述重布线层中的所述第二衬垫位于靠近所述第四端的位置处，所述第三衬垫位于远离所述第四端的位置处。
在另一些实施例中，部分所述重布线层中的所述第三衬垫位于靠近所述第二端的位置处，所述第二衬垫位于远离所述第二端的位置处；另一部分所述重布线层中的所述第三衬垫位于靠近所述第四端的位置处，所述第二衬垫位于远离所述第四端的位置处。
也就是说，满足每一所述第二衬垫的中心点相对于对应的所述第一衬垫的中心点的偏移方向和偏移距离均相等的前提下，第二衬垫也可以设置在离第一衬垫较远的距离处。
可以理解的是，部分所述重布线层中的第二衬垫位于靠近所述第二端的位置处且另一部分所述重布线层中的第二衬垫位于靠近所述第四端的位置处，相较于部分所述重布线层中的第二衬垫位于远离所述第二端的位置处且另一部分所述重布线层中的第二衬垫位于靠近所述第四端的位置处，在进行第二测试时，探针移动的距离更短，更能提高测试效率和降低错误发生的概率。在一些实施例中，每一所述重布线层还包括用于与所述第一衬垫进行导电连接的第一区域；
部分所述重布线层中的所述第二衬垫和所述第三衬垫均位于所述第一区域的一侧；另一部分所述重布线层中的所述第二衬垫和所述第三衬垫均位于所述第一区域的两侧。
应当理解的是，在所述封装结构中设置导电柱207时，参考图3、图4，第一区域213与所述导电柱207接触，且位于所述导电柱的周围，用于实现第一衬垫和重布线层电性连接。在所述封装结构中未设置导电柱207时，第一区域213位于过孔204内。所述第一区域213的材料可以与重布线层206的材料相同，也可不同，还可以是任何合适的导电材料。
本公开实施例中，第二衬垫和第三衬垫的相对位置关系不同，如图4中示出的一部分封装结构中第二衬垫位于导电柱与第三衬垫之间，另一部分封装结构中导电柱207位于第二衬垫211和第三衬垫212之间，基于此，第一区域213的位置可以设置在对应的第二衬垫211和第三衬垫212之间，也可以设置在对应的第二衬垫211和第三衬垫212的一侧。
另外，应当理解的是，在导电柱207和/或第一区域213设置在对应的第二衬垫211和第三衬垫212之间时，该对应的第二衬垫211和第三衬垫212之间可以设置隔墙。
需要说明的是，为了更清楚的展示第一衬垫、第二衬垫和第三衬垫之间的相对位置关系，图4中仅表示出了靠近第一边缘20a位置处的一个一个重布线层，以及靠近第二边缘20b位置处的一个重布线层；并且，图3、图4中仅示意性的示出了靠近第一边缘20a位置处的重布线层，与对应的靠近第二边缘20b位置处的重布线层之间的距离不代表实际应用中二者的距离，其实际距离可以根据实际需求进行设置。
本公开各实施例中，通过将位于不同边缘位置处的第二衬垫和第三衬垫之间的位置设置为不同，实现可以利用同一套探针卡来实现上述两种不 同运行速度的测试，相较于使用两套探针卡分别进行测试，节省了测试成本和测试时间，降低了生产周期和制造成本。
根据本公开实施例的另一方面，提供了一种半导体器件，包括：半导体功能结构及如本公开上述实施例中所述的封装结构。
在一些实施例中，所述半导体器件还包括：基板；多个堆叠设置的裸片；每一所述裸片包括半导体功能结构及位于所述半导体功能结构上的封装结构；每一裸片通过所述封装结构中的第三衬垫上的引线电连接到所述基板上。
根据本公开实施例的又一方面，提供了一种封装结构的制作方法，如图5所示，本公开实施例提供的封装结构的制造方法包括以下步骤：
步骤S501：提供半导体功能结构，所述半导体功能结构的表面设置有互连层；
步骤S502：形成具有多个过孔的隔离层，所述隔离层覆盖互连层表面，所述过孔暴露部分所述互连层，每一所述过孔暴露的部分所述互连层作为一个第一衬垫，形成N个第一衬垫；所述第一衬垫用于进行第一类测试；所述N为大于1的正整数；
步骤S503：在完成所述第一类测试后，在所述N个第一衬垫及所述隔离层上形成N个重布线层，每一重布线层覆盖所述隔离层并与所述N个第一衬垫中一相应所述第一衬垫电连接；部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第一边缘的位置处，另一部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第二边缘的位置处，所述第一边缘与所述第二边缘为所述半导体功能结构相对的两个边缘；
步骤S504：形成覆盖且暴露出部分所述重布线层的第一绝缘层，被暴露的部分所述重布线层作为第二衬垫和第三衬垫；其中，每一所述第二衬垫的中心点相对于对应的所述第一衬垫的中心点的偏移方向和偏移距离均相等；部分重布线层中的第二衬垫和所述第三衬垫之间的相对位置与另一部分所述重布线层中的所述第二衬垫和所述第三衬垫之间的相对位置不同；所述第二衬垫用于进行第二类测试，所述第三衬垫用于执行与所述第二类测试的内容对应的功能交互；所述半导体功能结构在进行所述第一类测试时的运行速度低于在进行所述第二类测试时的运行速度。
应当理解，图5中所示的步骤并非排他的，也可以在所示操作中的任何步骤之前、之后或之间执行其他步骤；图5中所示的各步骤可以根据实际需求进行顺序调整。图6a至图6d为本公开实施例提供的一种封装结构的制作过程的剖面示意图。下面结合图5、图6a至图6d，对本公开实施例提供的封装结构的制作方法进行详细地说明。
在步骤S501中，参考图6a，提供半导体功能结构600，所述半导体功能结构600包括半导体功能层601和互连层602。所述提供半导体功能结构600包括：提供基底(图6a中未示出)，在所述基底上形成半导体功能层 601，在所述半导体功能层上形成互连层602。
具体地，所述半导体功能层601包括单层或多层薄膜，半导体功能层具有导电层和/或介电层，根据实际需求，所述半导体功能层601中可以设置多种功能结构；相应地，所述互连层602用于将半导体功能层601中功能结构的电信号引出，以运行所述功能结构。在一些实施例中，互连层602包括顶层金属层，顶层金属层不仅用于将功能结构的电信号引出，还用于支撑半导体功能结构600。
在一些实施例中，所述方法还包括：去除部分互连层602，减小互连层的面积，以减小由所述互连层产生的寄生电容。图6a中展示的是互连层602被去除部分后的某一截面的剖面效果图，实际应用中，互连层中的各部分并不是截断的，而是互连的，即在其他截面上，互连层中的各部分可能是连续的。
在步骤S502中，参考图6b，在所述互连层602上形成隔离层603。所述隔离层的组成材料包括但不限于正硅酸乙酯。
接下来，去除部分所述隔离层，以形成多个过孔604。所述过孔暴露部分所述互连层，每一所述过孔暴露的部分所述互连层作为一个第一衬垫605，形成N个第一衬垫605。其中，所述过孔604可以是圆柱形，也可以是倒梯形，或者是任何合适的形状，所述过孔的横截面积包括所述过孔在所互连层所在平面的正投影的面积，例如，过孔是个倒梯形时，则所述第一衬垫的横截面积为所述过孔的最小横截面积。
所述第一衬垫605可以用于执行第一类测试；还可以用于执行与所述第一类测试的内容对应的功能交互，例如引出键合线并进行信号交互。所述第一类测试可以理解为对半导体功能结构执行较低运行速度时的一些测试。需要说明的是，在存储器中，所述运行速度指的是存储器的读写速度。
在步骤S503中，参考图6c，在所述隔离层603和所述过孔604中形成重布线层606。
其中，在所述隔离层603上形成重布线层606的具体方式包括：以曝光显影的方式在所述隔离层上形成新的导线图案，然后，利用电镀技术按照所述新的导线图案形成重布线层，所述重布线层包括新的导线路径，该新的导线路径与所述互连层导电连接。
这里，每一重布线层606覆盖所述隔离层603并与所述N个第一衬垫中一相应所述第一衬垫605电连接；需要说明的是，第一衬垫605包括第一部分第一衬垫和第二部分第一衬垫，第一部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第一边缘的位置处，第二部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第二边缘的位置处，所述第一边缘与所述第二边缘为所述半导体功能结构相对的两个边缘。
在步骤S504中，参考图6d，在所述重布线层606上形成第一绝缘层608。
接下来，去除部分所述第一绝缘层608，暴露出部分重布线层606，这里，被暴露出的部分所述重布线层包括第二衬垫611和第三衬垫612，其中，所述第二衬垫611用于进行第二类测试，所述第三衬垫612用于执行与所述第二类测试的内容对应的功能交互，所述第二类测试可以理解为对半导体功能结构在较高运行速度时执行的一些测试。这里，第二衬垫611和第三衬垫612的位置可以根据实际需求进行选择设置。
需要说明的是，在本实施例中，参考图6d，第一绝缘层除了暴露部分所述重布线层以构成第二衬垫和第三衬垫以外，还暴露位于第一衬垫上方的重布线层，以在重布线层构成的凹槽609内填充后续的第二绝缘层610，此时，第二绝缘层的密度可以小于等于第一绝缘层；在其他实施例中，第一绝缘层还覆盖重布线层构成的凹槽609的底面和侧壁，后续第二绝缘层610形成于第一绝缘层构成的凹槽609内。
在另一些实施例中，所述封装结构还包括导电柱，对应的，所述方法还包括：在完成所述第一类测试后，在所述第一衬垫上形成导电柱；所述在所述第一衬垫及所述隔离层上形成重布线层，包括：在所述导电柱及所述隔离层上形成重布线层，所述重布线层通过所述导电柱与所述互连层导电连接。
本公开实施例中，第二衬垫和第三衬垫的相对位置关系可以根据实际需求进行设置，例如，封装结构中第二衬垫位于导电柱与第三衬垫之间，和/或，封装结构中导电柱位于第二衬垫611和第三衬垫612之间，基于此，部分重布线层606中的第二衬垫611和所述第三衬垫612之间的相对位置与另一部分所述重布线层606中的所述第二衬垫611和所述第三衬垫612之间的相对位置可以相同也可以不同，前已述及，这里不再赘述。
每一所述第二衬垫的中心点相对于对应的所述第一衬垫的中心点的偏移方向和偏移距离均相等，如此，可以使得同一套探针卡在执行第一类测试后，从第一衬垫的中心点向一定的方向移动一定的距离后能够与全部的第二衬垫的中心点均对准，即探针卡可以直接对全部的第二衬垫执行第二类测试，而无需更换新的探针卡。
另外，需要说明的是，本公开上述实施例中，采用兼容两种类型测试的封装结构，满足半导体功能结构在不同制程阶段能够进行不同类型的测试；然而，需要注意的是，在对封装结构进行布局设计时，需要在顶层金属层上预留重布线层的过孔位置，保证在需要增加重布线层的时候，不用改动顶层金属层或其他任何光刻板及工艺制程。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过非目标的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的 各组成部分相互之间的耦合、或直接耦合。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开各实施例中，通过在顶层金属层中设置N个第一衬垫，用于对所述半导体功能结构执行处于第一种运行速度时的测试；其中，部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第一边缘的位置处，另一部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第二边缘的位置处；在第一种运行速度时的测试完成后，在第一衬垫上的重布线层中设置与第一衬垫一一对应的第二衬垫，用于对所述半导体功能结构执行处于第二种运行速度时的测试；其中，部分所述重布线层中所述第二衬垫和所述第三衬垫之间的相对位置与另一部分所述重布线层中的所述第二衬垫和所述第三衬垫之间的相对位置不同；这里，通过将每一第二衬垫的中心点设置为相对于对应的第一衬垫的中心点偏移相同的方向和偏移相等的距离，使得N个第一衬垫和N个第二衬垫保持完全相同的相对位置；同时，通过将位于不同边缘位置处的第二衬垫和第三衬垫之间的位置设置为不同，使得位于两个边缘位置处的重布线层保有较大的容错率，均可以靠近边缘但不超出边缘，如此，可以保证第一衬垫和第二衬垫均处于有利于节省总面积的有利位置，同时还可以利用同一套探针卡来实现上述两种不同运行速度的测试，相较于使用两套探针卡分别进行测试，节省了测试成本和测试时间，降低了生产周期和制造成本。

Claims (13)

  1. 一种封装结构，包括：
    具有多个过孔的隔离层，所述隔离层覆盖互连层表面，所述过孔暴露部分所述互连层，所述互连层设置在半导体功能结构的表面；
    N个第一衬垫，每一第一衬垫由一个所述过孔暴露的所述互连层构成；所述N为大于1的正整数；
    N个重布线层，每一重布线层覆盖所述隔离层并与所述N个第一衬垫中一相应所述第一衬垫电连接；部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第一边缘的位置处，另一部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第二边缘的位置处，所述第一边缘与所述第二边缘为所述半导体功能结构相对的两个边缘；
    第一绝缘层，覆盖且暴露出每一所述重布线层的部分区域；
    每一所述重布线层被暴露出的部分区域均包括第二衬垫和第三衬垫；其中，每一所述第二衬垫的中心点相对于对应的所述第一衬垫的中心点的偏移方向和偏移距离均相等；部分所述重布线层中所述第二衬垫和所述第三衬垫之间的相对位置与另一部分所述重布线层中的所述第二衬垫和所述第三衬垫之间的相对位置不同；所述第一衬垫和第二衬垫分别用于所述半导体功能结构处于不同运行速度时的测试，所述第三衬垫用于执行与所述第二衬垫测试的内容对应的功能交互。
  2. 根据权利要求1所述的封装结构，其中，
    所述N个重布线层中每一所述重布线层包括的所述第二衬垫与所述第三衬垫均沿第二方向并列设置，所述第二方向与所述第一方向垂直。
  3. 根据权利要求2所述的封装结构，其中，每一所述第二衬垫的中心点在所述互连层所在平面的正投影相对于对应的所述第一衬垫的中心点向所述第二方向偏移第一距离。
  4. 根据权利要求3所述的封装结构，其中，每一所述重布线层在所述互连层所在平面的正投影的形状均包括长条状。
  5. 根据权利要求4所述的封装结构，其中，
    部分所述第一衬垫靠近所述第一边缘的第一端与部分所述重布线层靠近所述第一边缘的第二端沿第三方向基本齐平，第三方向与所述第一方向和所述第二方向均垂直；
    另一部分所述第一衬垫靠近所述第二边缘的第三端与另一部分所述重布线层靠近所述第二边缘的第四端沿所述第三方向基本齐平。
  6. 根据权利要求5所述的封装结构，其中，
    部分所述重布线层中的所述第二衬垫位于靠近所述第二端的位置处，所述第三衬垫位于远离所述第二端的位置处；
    另一部分所述重布线层中的所述第二衬垫位于靠近所述第四端的位置处，所述第三衬垫位于远离所述第四端的位置处。
  7. 根据权利要求6所述的封装结构，其中，每一所述重布线层还包括用于与所述第一衬垫进行导电连接的第一区域；
    部分所述重布线层中的所述第二衬垫和所述第三衬垫均位于所述第一区域的一侧；另一部分所述重布线层中的所述第二衬垫和所述第三衬垫均位于所述第一区域的两侧。
  8. 根据权利要求1所述的封装结构，其中，
    所述重布线层与对应的所述第一衬垫直接接触；
    或者，
    所述封装结构还包括：导电柱，位于所述重布线层与对应的所述第一衬垫之间，所述重布线层通过所述导电柱与所述互连层导电连接。
  9. 根据权利要求8所述的封装结构，其中，所述封装结构包括所述导电柱，所述导电柱的数量多括多个，多个导电柱沿第一方向并列设置。
  10. 根据权利要求8所述的封装结构，其中，所述重布线层与对应的所述第一衬垫直接接触，所述封装结构还包括：
    第二绝缘层，位于每一所述重布线层围成的凹槽内，所述第二绝缘层的材料的硬度小于所述重布线层的材料的硬度。
  11. 一种半导体器件，包括：半导体功能结构及如权利要求1至10中任一项所述的封装结构。
  12. 根据权利要求11所述的半导体器件，其中，所述半导体器件还包括：
    基板；
    多个堆叠设置的裸片；每一所述裸片包括半导体功能结构及位于所述半导体功能结构上的封装结构；
    每一裸片通过所述封装结构中的第三衬垫上的引线电连接到所述基板上。
  13. 一种封装结构的制作方法，包括：
    提供半导体功能结构，所述半导体功能结构的表面设置有互连层；
    形成具有多个过孔的隔离层，所述隔离层覆盖互连层表面，所述过孔暴露部分所述互连层，每一所述过孔暴露的部分所述互连层作为一个第一衬垫，形成N个第一衬垫；所述第一衬垫用于进行第一类测试；所述N为大于1的正整数；
    在完成所述第一类测试后，在所述N个第一衬垫及所述隔离层上形成N个重布线层，每一重布线层覆盖所述隔离层并与所述N个第一衬垫中一相应所述第一衬垫电连接；部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第一边缘的位置处，另一部分所述第一衬垫沿第一方向并列设置在靠近所述半导体功能结构第二边缘的位置处，所述第一边缘与所述第二边缘为所述半导体功能结构相对的两个边缘；
    形成覆盖且暴露出部分所述重布线层的第一绝缘层，被暴露的部分所述重布线层作为第二衬垫和第三衬垫；其中，每一所述第二衬垫的中心点 相对于对应的所述第一衬垫的中心点的偏移方向和偏移距离均相等；部分重布线层中的第二衬垫和所述第三衬垫之间的相对位置与另一部分所述重布线层中的所述第二衬垫和所述第三衬垫之间的相对位置不同；所述第二衬垫用于进行第二类测试，所述第三衬垫用于执行与所述第二类测试的内容对应的功能交互；所述半导体功能结构在进行所述第一类测试时的运行速度低于在进行所述第二类测试时的运行速度。
PCT/CN2022/102515 2022-06-01 2022-06-29 封装结构及其制作方法、半导体器件 Ceased WO2023231122A1 (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100314619A1 (en) * 2009-06-15 2010-12-16 Erdem Kaltalioglu Test Structures and Methods for Semiconductor Devices
CN105548851A (zh) * 2014-08-14 2016-05-04 三星电子株式会社 半导体器件及其制造方法及测试半导体器件的装置
CN106920797A (zh) * 2017-03-08 2017-07-04 长江存储科技有限责任公司 存储器结构及其制备方法、存储器的测试方法
CN107424970A (zh) * 2016-05-11 2017-12-01 日月光半导体制造股份有限公司 半导体装置封装及其制造方法
CN112582365A (zh) * 2019-09-27 2021-03-30 台湾积体电路制造股份有限公司 半导体封装件、封装件及其形成方法
CN112864130A (zh) * 2021-01-08 2021-05-28 上海华虹宏力半导体制造有限公司 用于晶圆级测试的芯片和晶圆

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW490784B (en) * 2001-05-31 2002-06-11 Chipmos Technologies Inc A semiconductor wafer is disclosed for avoiding scrub mark while testing
TW200905844A (en) * 2007-07-31 2009-02-01 United Microelectronics Corp Group probing over active area pads arrangement
KR102398663B1 (ko) * 2015-07-09 2022-05-16 삼성전자주식회사 칩 패드, 재배선 테스트 패드 및 재배선 접속 패드를 포함하는 반도체 칩
US10396001B2 (en) * 2015-08-20 2019-08-27 Adesto Technologies Corporation Offset test pads for WLCSP final test
US10381278B2 (en) * 2017-09-14 2019-08-13 Powertech Technology Inc. Testing method of packaging process and packaging structure
US11222839B1 (en) * 2020-09-29 2022-01-11 Nanya Technology Corporation Semiconductor structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100314619A1 (en) * 2009-06-15 2010-12-16 Erdem Kaltalioglu Test Structures and Methods for Semiconductor Devices
CN105548851A (zh) * 2014-08-14 2016-05-04 三星电子株式会社 半导体器件及其制造方法及测试半导体器件的装置
CN107424970A (zh) * 2016-05-11 2017-12-01 日月光半导体制造股份有限公司 半导体装置封装及其制造方法
CN106920797A (zh) * 2017-03-08 2017-07-04 长江存储科技有限责任公司 存储器结构及其制备方法、存储器的测试方法
CN112582365A (zh) * 2019-09-27 2021-03-30 台湾积体电路制造股份有限公司 半导体封装件、封装件及其形成方法
CN112864130A (zh) * 2021-01-08 2021-05-28 上海华虹宏力半导体制造有限公司 用于晶圆级测试的芯片和晶圆

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4307352A4 *

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