WO2023245760A1 - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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Publication number
WO2023245760A1
WO2023245760A1 PCT/CN2022/105152 CN2022105152W WO2023245760A1 WO 2023245760 A1 WO2023245760 A1 WO 2023245760A1 CN 2022105152 W CN2022105152 W CN 2022105152W WO 2023245760 A1 WO2023245760 A1 WO 2023245760A1
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Prior art keywords
insulating layer
layer
trench
insulating
sub
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PCT/CN2022/105152
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English (en)
French (fr)
Inventor
曾以志
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to JP2022562320A priority Critical patent/JP7588153B2/ja
Priority to EP22769874.3A priority patent/EP4318558A4/en
Priority to KR1020227031206A priority patent/KR102838911B1/ko
Priority to US17/948,918 priority patent/US12419043B2/en
Publication of WO2023245760A1 publication Critical patent/WO2023245760A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a manufacturing method thereof.
  • a semiconductor structure generally includes a substrate, a plurality of transistors located on the substrate, and an isolation structure located within the substrate for isolating the plurality of transistors.
  • Transistors usually use a planar gate structure with intersections between the gate structure and the isolation structure.
  • Embodiments of the present disclosure provide a semiconductor structure, including:
  • a first insulating layer covering the bottom surface of the first isolation trench and the lower portion of the sidewall
  • a third insulating layer is at least partially located between the first insulating layer and the second insulating layer to isolate the first insulating layer and the second insulating layer.
  • the materials of the first insulating layer and the second insulating layer include nitride, and the material of the third insulating layer includes oxide.
  • the ratio of the height of the first insulating layer to the height of the second insulating layer ranges from 2 to 6, and the third insulating layer is located between the first insulating layer and the third insulating layer.
  • the ratio of the height of the portion between the two insulating layers to the height of the second insulating layer ranges from 0.3 to 0.7.
  • the thickness of the first insulating layer and the second insulating layer is 5-30 nm.
  • it also includes:
  • the fourth insulating layer is located between the inner wall of the first isolation trench and the first insulating layer, and the fourth insulating layer covers the bottom surface of the first isolation trench; lower part of side wall;
  • a first filling layer fills the depression defined by the first insulation layer in the first isolation trench.
  • the third insulating layer includes a bottom layer and a sidewall layer.
  • the bottom layer covers the fourth insulating layer, the first insulating layer and the top of the first filling layer.
  • the sidewall layer A layer is located between the upper sidewall of the first isolation trench and the second insulating layer.
  • it also includes:
  • a second filling layer fills a depression defined in the first isolation trench by the second insulating layer and the bottom layer of the third insulating layer.
  • it also includes:
  • the second isolation trench includes a first sub-trench and a second sub-trench, and the width of the second sub-trench is greater than the width of the first sub-trench.
  • the fourth insulating layer covers the bottom surface of the second sub-trench and a lower portion of the sidewall, and the first insulating layer fills the fourth insulating layer in the second sub-trench. a recess defined within; the third insulating layer covers the upper part of the sidewall of the second sub-trench and the tops of the fourth insulating layer and the first insulating layer; the second filling layer fills the Three insulating layers define recesses within the second sub-trench.
  • the first isolation trench is located in the core area or peripheral area of the device for isolating the selection transistor, and the second isolation trench is located in the device unit area for isolating the memory cell.
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, including:
  • first insulating layer covering a bottom surface of the first isolation trench and a lower portion of the sidewall
  • a second insulating layer is formed above the third insulating layer, the second insulating layer covers an upper portion of the sidewall of the first isolation trench, and the third insulating layer connects the first insulating layer and the A second insulating layer isolates.
  • the same step of etching the substrate to form the first isolation trench it also includes:
  • Etching the substrate to form a second isolation trench the second isolation trench including a first sub-trench and a second sub-trench, the width of the second sub-trench is larger than the first sub-trench width.
  • the method before forming the first insulating layer, the method further includes:
  • a fourth insulating material layer is formed, covering inner surfaces of the first isolation trench and the second sub-trench, and filling the first sub-trench.
  • forming the first insulating layer includes:
  • forming the third insulating layer includes:
  • forming the second insulating layer includes:
  • the second insulating material layer covers the bottom surface and side walls of the first accommodation cavity and fills the second accommodation cavity;
  • Etch the second insulating material layer remove the second insulating material layer located in the second accommodating cavity and the second insulating material layer covering the bottom surface of the first accommodating cavity, to form a second insulating material layer covering the first accommodating cavity.
  • the method further includes:
  • a second filling material layer is formed above the third insulating layer and the second insulating layer, and the second filling material layer completely fills the first accommodating cavity and the second accommodating cavity;
  • the second filling material layer is etched so that the top of the second filling material layer is flush with the top of the second insulating layer, thereby forming a second filling layer.
  • a semiconductor structure and a manufacturing method thereof provided by embodiments of the present disclosure, wherein the semiconductor structure includes: a substrate and a first isolation trench located in the substrate; a first insulating layer covering the first isolation trench The bottom surface and the lower part of the sidewalls; a second insulating layer covering the upper part of the sidewalls of the first isolation trench; a third insulating layer at least partially located between the first insulating layer and the second insulating layer space to isolate the first insulating layer and the second insulating layer.
  • Embodiments of the present disclosure use a third insulating layer to separate the first insulating layer and the second insulating layer, thereby separating hot electrons trapped in the first insulating layer from hot electrons trapped in the second insulating layer.
  • the first insulating layer and the second insulating layer are isolated from each other. Compared with when the first insulating layer and the second insulating layer are not isolated, the first insulating layer and the second insulating layer have fewer carriers for storing hot electrons, so they can store fewer hot electrons. In this way, the HEIP effect can be effectively alleviated.
  • Figure 1 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a schematic cross-sectional structural diagram taken along lines AA' and BB' of Figure 1;
  • Figure 3 is a flow chart of a semiconductor structure manufacturing method provided by an embodiment of the present disclosure.
  • 4 to 12 are process flow diagrams of semiconductor structures provided by embodiments of the present disclosure.
  • Spatial relational terms such as “under”, “below”, “under”, “below”, “on”, “above”, etc. are used here for convenience Descriptions are used to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as “below” or “under” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • a semiconductor structure generally includes a substrate, a plurality of transistors located on the substrate, an isolation trench located in the substrate for isolating the multiple transistors, and an isolation structure located in the isolation trench.
  • Transistors usually use a planar gate structure with intersections between the gate structure and the isolation structure.
  • the isolation structure usually includes an oxide layer covering the inner wall of the isolation trench, a nitride layer covering the oxide layer, and a filling layer filling the isolation trench.
  • the HEIP effect is usually mitigated by increasing the thickness of the oxide layer to increase the distance between the nitride layer and the substrate. However, this increases the process difficulty of forming the isolation structure.
  • FIG. 1 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional structural view taken along lines AA′ and BB′ of FIG. 1 .
  • the semiconductor structure provided by the embodiment of the present disclosure will be further described below with reference to FIGS. 1 to 2 .
  • the semiconductor structure includes: a substrate 10 and a first isolation trench 11 located in the substrate 10; a first insulating layer 13 covering the bottom surface of the first isolation trench 11 and the lower part of the sidewall; The insulating layer 16 covers the upper part of the sidewall of the first isolation trench 11; the third insulating layer 15 is at least partially located between the first insulating layer 13 and the second insulating layer 16 to connect the first insulating layer 13 and the second insulating layer 16. Insulating layer 16 isolates.
  • the semiconductor structure provided by the embodiment of the present disclosure may be a three-dimensional dynamic random access memory (3D DRAM), but it is not limited to this, and the semiconductor structure may also be any semiconductor structure.
  • 3D DRAM three-dimensional dynamic random access memory
  • the substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (for example, a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor material known in the art.
  • the substrate is a silicon substrate, which may be doped or undoped.
  • the substrate 10 includes a device unit area 101 and a device core area or peripheral area 102.
  • the first isolation trench 11 is located in the device core region or peripheral region 102 for isolating the selection transistor. Specifically, the first isolation trench 11 defines at least one first active area AA1 in the device core area or peripheral area 102. In actual operation, an option having a planar gate structure may be formed on the first active area AA1.
  • Transistors such as P-type transistors or N-type transistors.
  • the materials of the first insulating layer 13 and the second insulating layer 16 include nitride.
  • the embodiment of the present disclosure uses nitride as the material of the first insulating layer 13 and the second insulating layer 16.
  • nitride as the material of the first insulating layer 13 and the second insulating layer 16.
  • the mobility of carriers in the channel region Specifically, tensile stress forms tensile strain in the channel region, which can increase the electron mobility of the N-type transistor, while compressive stress forms compressive strain in the channel region, which can increase the hole mobility of the P-type transistor.
  • the materials of the first insulating layer 13 and the second insulating layer 16 may be the same or different.
  • the first insulating layer 13 and the second insulating layer 16 are made of the same material, for example, silicon nitride. But it is not limited thereto. Any material that meets the above stress requirements can be used as the material of the first insulating layer 13 and the second insulating layer 16 .
  • the material of the third insulating layer 15 includes oxide, for example, silicon oxide.
  • the first insulating layer 13 and the second insulating layer 16 have the ability to capture hot electrons.
  • the embodiment of the present disclosure uses the third insulating layer 15 to separate the first insulating layer 13 and the second insulating layer 16, so that the hot electrons trapped in the first insulating layer 13 and the hot electrons trapped in the second insulating layer 16 are separated.
  • the hot electrons are spaced apart, preventing the hot electrons trapped in the second insulating layer 16 from flowing into the first insulating layer 13 and reducing the number of hot electrons stored in the first insulating layer 13.
  • the first insulating layer 13 and the second insulating layer 16 are separated.
  • the insulating layer 16 is isolated.
  • the first insulating layer 13 and the second insulating layer 16 Compared with when the first insulating layer 13 and the second insulating layer 16 are not isolated, the first insulating layer 13 and the second insulating layer 16 have fewer carriers for storing hot electrons, so they can store There are fewer hot electrons, which can effectively alleviate the HEIP effect.
  • the ratio between the height of the first insulating layer 13 and the height of the second insulating layer 16 should not be too large or too small.
  • the ratio between the height of the first insulating layer 13 and the height of the second insulating layer 16 is too large, the first insulating layer 13 will extend to the upper part of the first isolation trench 11 , and the hot electrons stored in the first insulating layer 13 will be relatively large. If the ratio of the height of the first insulating layer 13 to the height of the second insulating layer 16 is too small, the upper part of the first active area AA1 will accumulate more holes, so the effect of mitigating the HEIP effect is not obvious.
  • the height of the second insulating layer 16 in the upper part of an isolation trench 11 is higher, and the second insulating layer 16 can capture a larger number of hot electrons, and the upper part of the first active area AA1 will collect more holes. In this way, The effect of alleviating the HEIP effect is not obvious.
  • the ratio of the height of the first insulating layer 13 to the height of the second insulating layer 16 ranges from 2 to 6, specifically, for example, 3, 4, 5, etc.
  • the height of the portion of the third insulating layer 15 located between the first insulating layer 13 and the second insulating layer 16 should not be too large or too small.
  • the sum of the heights of the first insulating layer 13 and the second insulating layer 16 is smaller. In this way, the first The effect of the insulating layer 13 and the second insulating layer 16 on increasing the stress of the substrate 10 is not obvious; when the height of the part of the third insulating layer 15 between the first insulating layer 13 and the second insulating layer 16 is too small, the HEIP effect can be alleviated. no significant effect.
  • the ratio of the height of the portion of the third insulating layer 15 between the first insulating layer 13 and the second insulating layer 16 to the height of the second insulating layer 16 ranges from 0.3 to 0.7. Specifically, For example, 0.4, 0.5, 0.6, etc.
  • the thickness of the first insulating layer 13 and the second insulating layer 16 is 5-30 nm. In some embodiments, the thickness of the first insulating layer 13 and the second insulating layer 16 is 10-25 nm. In a specific embodiment, the thickness of the first insulating layer 13 is greater than the thickness of the second insulating layer 16, and the second insulating layer 16 has a thinner thickness. Therefore, fewer hot electrons can be stored in the first insulating layer 13. Effectively alleviate HEIP effect.
  • the semiconductor structure further includes: a fourth insulating layer 18.
  • the fourth insulating layer 18 is located between the inner wall of the first isolation trench 11 and the first insulating layer 13, and the fourth insulating layer 18 covers the first isolation layer.
  • the bottom surface of the trench 11 and the lower part of the sidewall; the first filling layer 14 fills the depression S1 defined by the first insulating layer 13 in the first isolation trench 11 .
  • the material of the fourth insulating layer 18 may be the same as the material of the third insulating layer 15 , such as silicon oxide.
  • the material of the first filling layer 14 may be an oxide, such as silicon oxide.
  • the third insulating layer 15 includes a bottom layer 151 and a spacer layer 152.
  • the bottom layer 151 covers the fourth insulating layer 18, the first insulating layer 13 and the top of the first filling layer 14.
  • the spacer layer 152 is located on the first between the upper sidewall of the trench 11 and the second insulating layer 16 .
  • the third insulating layer 15 also covers the upper surface of the substrate 10 .
  • the embodiment of the present disclosure disposes the fourth insulating layer 18 and the third insulating layer 15 between the substrate 10 and the first insulating layer 13 and the second insulating layer 16 to insulate the substrate 10 from the first insulating layer 13 and the second insulating layer 16 .
  • Layers 16 are spaced apart to further mitigate the HEIP effect.
  • the embodiment of the present disclosure effectively alleviates the HEIP effect by using the third insulating layer 15 to separate the first insulating layer 13 and the second insulating layer 16. In this way, there is no need to additionally thicken the fourth insulating layer 18 and the third insulating layer 16.
  • the thickness of layer 15 simplifies the process and increases the process window.
  • the semiconductor structure further includes: a second filling layer 17 .
  • the second filling layer 17 fills the recess defined in the first isolation trench 11 by the second insulating layer 16 and the bottom layer 151 of the third insulating layer 15 .
  • S2 The material of the second filling layer 17 may be the same as the material of the first filling layer 14, such as silicon oxide.
  • the semiconductor structure further includes: a second isolation trench 12.
  • the second isolation trench 12 includes a first sub-trench 121 and a second sub-trench 122.
  • the width of the second sub-trench 122 is greater than the first sub-trench 121.
  • the second isolation trench 12 is located in the device unit area 101 for isolating the memory cells, and defines a plurality of second active areas AA2 arranged in parallel with each other in the device unit area 101.
  • the first isolation trench 11 and the second isolation trench 12 are formed in the same process step, and the width of the first isolation trench 11 is greater than the width of the first sub-trench 121 and the second sub-trench 122 .
  • first isolation trench 11 and the second sub-trench 122 is greater than the width of the first sub-trench 121, under the same etching process conditions, the first isolation trench 11 and the second sub-trench 122 will be larger than the width of the first isolation trench 11 and the second sub-trench 122.
  • the depth of the trench 122 is greater than the depth of the first sub-trench 121 .
  • the fourth insulating layer 18 covers the bottom surface of the second sub-trench 122 and the lower part of the sidewall, and the first insulating layer 13 fills the recess S3 defined by the fourth insulating layer 18 in the second sub-trench 122 ;
  • the third insulating layer 15 covers the upper part of the sidewall of the second sub-trench 122 and the tops of the fourth insulating layer 18 and the first insulating layer 13 ;
  • the second filling layer 17 fills the third insulating layer 15 in the second sub-trench 122 Within the defined recess S4.
  • the fourth insulating layer 18 fills the lower part of the first sub-trench 121 , and the third insulating layer 15 fills the upper part of the first sub-trench 121 .
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure. As shown in Figure 3, the method includes the following steps:
  • Step 301 Provide a substrate
  • Step 302 Etch the substrate to form a first isolation trench
  • Step 303 Form a first insulating layer that covers the bottom surface of the first isolation trench and the lower part of the sidewall;
  • Step 304 Form a third insulating layer above the first insulating layer, and the third insulating layer covers at least the top of the first insulating layer;
  • Step 305 Form a second insulating layer above the third insulating layer.
  • the second insulating layer covers the upper portion of the sidewall of the first isolation trench.
  • the third insulating layer isolates the first insulating layer and the second insulating layer.
  • FIGS. 4 to 12 illustrate each process step along the lines A-A' and B of FIG. 1 Schematic diagram of the cross-sectional structure taken by -B'.
  • step 301 is performed to provide a substrate 10 .
  • the substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (for example, a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor material known in the art.
  • the substrate is a silicon substrate, which may be doped or undoped.
  • the substrate 10 includes a device unit region 101 and a device core or peripheral region 102.
  • a memory cell may be formed in the device unit area 101, and a selection transistor may be formed in the device core area or peripheral area 102.
  • step 302 is performed. As shown in FIG. 5 , the substrate 10 is etched to form a first isolation trench 11 .
  • the first isolation trench 11 is formed in the device core area or peripheral area 102 and within the device core area or peripheral area 102. At least one first active area AA1 is defined.
  • a selection transistor having a planar gate structure such as a P-type transistor or an N-type transistor, may be subsequently formed on the first active area AA1.
  • the same step of etching the substrate 10 to form the first isolation trench 11 also includes: etching the substrate 10 to form a second isolation trench 12, and the second isolation trench 12 includes the first sub-section.
  • the groove 121 and the second sub-trench 122, the width of the second sub-trench 122 is greater than the width of the first sub-trench 121.
  • the second isolation trench 12 is formed in the device unit area 101 and defines a plurality of second active areas AA2 arranged parallel to each other in the device unit area 101 .
  • a memory cell may be subsequently formed on the second active area AA2, and the second isolation trench 12 is used to isolate the memory cell.
  • the first isolation trench 11 and the second isolation trench 12 are formed in the same process step. In this way, one mask process can be reduced, thereby simplifying the process.
  • the width of the first isolation trench 11 is greater than the width of the first sub-trench 121 and the second sub-trench 122 . It can be understood that since the width of the first isolation trench 11 and the second sub-trench 122 is greater than the width of the first sub-trench 121, under the same etching process conditions, the first isolation trench 11 and the second sub-trench 122 will be larger than the width of the first isolation trench 11 and the second sub-trench 122.
  • the depth of the trench 122 is greater than the depth of the first sub-trench 121 .
  • step 303 is performed. As shown in FIGS. 7 to 8 , a first insulating layer 13 is formed. The first insulating layer 13 covers the bottom surface of the first isolation trench 11 and the lower part of the sidewall.
  • the method before forming the first insulating layer 13 , the method further includes: forming a fourth insulating material layer 18 ′, and the fourth insulating material layer 18 ′ covers the first isolation trench 11 and the second isolation trench 11 .
  • the fourth layer of insulating material 18' also covers the upper surface of the substrate 10. It can be understood that since the depth and width of the first sub-trench 121 are small, under the same deposition process conditions, the fourth insulating material layer 18' can fill the first sub-trench 121 but not the first isolation trench.
  • the groove 11 and the second sub-trench 122 are formed so that the finally formed fourth insulating layer 18 fills the lower part of the first sub-trench 121 .
  • the fourth insulating material layer 18' can be formed using an atomic layer deposition (ALD) process combined with an in-situ water vapor generation (ISSG) process.
  • the material of the fourth insulating layer 18 includes oxide, for example, silicon oxide.
  • forming the first insulating layer 13 includes:
  • first insulating material layer 13' Form a first insulating material layer 13', the first insulating material layer 13' covers the fourth insulating material layer 18', and fills the second sub-trench 122;
  • first filling material layer 14' Form a first filling material layer 14', the first filling material layer 14' covers the first insulating material layer 13' and fills the first isolation trench 11;
  • the top is lower than the upper surface of the substrate 10 , thereby forming the first insulating layer 13 , the fourth insulating layer 18 and the first filling layer 14 .
  • the first insulating material layer 13' and the first filling material layer 14' may be formed using a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, or a combination thereof.
  • the material of the first insulating layer 13 includes nitride, such as silicon nitride.
  • the material of the first filling layer 14 includes oxide, such as silicon oxide.
  • step 304 is performed.
  • a third insulating layer 15 is formed above the first insulating layer 13 .
  • the third insulating layer 15 at least covers the top of the first insulating layer 13 .
  • forming the third insulating layer 15 includes: forming a third insulating material layer (not shown), etching the third insulating material layer (not shown) to form a layer covering the fourth insulating layer 18, the first insulating layer 13 and The top of the first filling layer 14 and the third insulating layer 15 on the sidewalls of the first isolation trench 11 and the second sub-trench 122 .
  • the portion of the third insulating layer 15 within the first isolation trench 11 defines the third insulating layer 15 .
  • An accommodating cavity T1 the part of the third insulating layer 15 in the second sub-trench 122 defines a second accommodating cavity T2.
  • the third insulating layer 15 also covers the upper surface of the substrate 10 .
  • the third insulating layer 15 can fill the portion of the first sub-trench 121 that is not filled by the fourth insulating layer 18 .
  • the third insulating layer 15 may be formed using a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, or a combination thereof.
  • the material of the third insulating layer 15 includes oxide, such as silicon oxide.
  • step 305 is performed.
  • a second insulating layer 16 is formed above the third insulating layer 15 .
  • the second insulating layer 16 covers the upper part of the sidewall of the first isolation trench 11 .
  • the insulating layer 15 isolates the first insulating layer 13 and the second insulating layer 16 .
  • forming the second insulating layer 16 includes:
  • the second insulating material layer 16' covers the bottom surface and side walls of the first accommodating cavity T1, and fills the second accommodating cavity T2;
  • Etch the second insulating material layer 16' remove the second insulating material layer 16' located in the second accommodating cavity T2 and the second insulating material layer 16' covering the bottom surface of the first accommodating cavity T1, to form a layer covering the second insulating material layer 16'.
  • the width of the second sub-trench 122 is smaller, so the width of the second accommodation cavity T2 is smaller than the width of the first accommodation cavity T1.
  • the second insulating material layer 16' may fill the second accommodating cavity T2 without filling the first accommodating cavity T1.
  • the second insulating material layer 16' may be formed using a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, or a combination thereof.
  • the material of the second insulating layer 16 includes nitride.
  • the embodiment of the present disclosure uses nitride as the material of the first insulating layer 13 and the second insulating layer 16, allowing the tensile stress or compressive stress in the transistor channel region to be increased as required, thereby meeting the stress requirements of the transistor and improving the transistor channel. area carrier mobility. Specifically, tensile stress forms tensile strain in the channel region, which can increase the electron mobility of the N-type transistor, while compressive stress forms compressive strain in the channel region, which can increase the hole mobility of the P-type transistor.
  • the materials of the first insulating layer 13 and the second insulating layer 16 may be the same or different.
  • the first insulating layer 13 and the second insulating layer 16 are made of the same material, such as silicon nitride. But it is not limited thereto. Any material that meets the above stress requirements can be used as the material of the first insulating layer 13 and the second insulating layer 16 .
  • the first insulating layer 13 and the second insulating layer 16 have the ability to capture hot electrons.
  • the embodiment of the present disclosure uses the third insulating layer 15 to separate the first insulating layer 13 and the second insulating layer 16, so that the hot electrons trapped in the first insulating layer 13 and the hot electrons trapped in the second insulating layer 16 are separated.
  • the hot electrons are separated, especially during subsequent heat treatment and other processes, the hot electrons in the second insulating layer 16 will be lost.
  • the existence of the third insulating layer 15 can prevent the hot electrons trapped in the second insulating layer 16 from flowing to the third insulating layer 16 . In an insulating layer 13, in this way, the number of hot electrons stored in the first insulating layer 13 can be reduced.
  • the first insulating layer 13 and the second insulating layer 16 are isolated from the first insulating layer 13 and the second insulating layer 13. Compared with when the insulating layer 16 is not blocked, the first insulating layer 13 and the second insulating layer 16 have fewer carriers for storing hot electrons, so they can store fewer hot electrons. In this way, the HEIP effect can be effectively alleviated.
  • the ratio between the height of the first insulating layer 13 and the height of the second insulating layer 16 should not be too large or too small.
  • the ratio between the height of the first insulating layer 13 and the height of the second insulating layer 16 is too large, the first insulating layer 13 will extend to the upper part of the first isolation trench 11 , and the hot electrons stored in the first insulating layer 13 will be relatively large. If the ratio of the height of the first insulating layer 13 to the height of the second insulating layer 16 is too small, the upper part of the first active area AA1 will accumulate more holes, so the effect of mitigating the HEIP effect is not obvious.
  • the height of the second insulating layer 16 in the upper part of an isolation trench 11 is higher, and the second insulating layer 16 can capture a larger number of hot electrons, and the upper part of the first active area AA1 will collect more holes. In this way, The effect of alleviating the HEIP effect is not obvious.
  • the ratio of the height of the first insulating layer 13 to the height of the second insulating layer 16 ranges from 2 to 6, specifically, for example, 3, 4, 5, etc.
  • the height of the portion of the third insulating layer 15 located between the first insulating layer 13 and the second insulating layer 16 should not be too large or too small.
  • the sum of the heights of the first insulating layer 13 and the second insulating layer 16 is smaller. In this way, the first The effect of the insulating layer 13 and the second insulating layer 16 on increasing the stress of the substrate 10 is not obvious; when the height of the part of the third insulating layer 15 between the first insulating layer 13 and the second insulating layer 16 is too small, the HEIP effect can be alleviated. no significant effect.
  • the ratio of the height of the portion of the third insulating layer 15 between the first insulating layer 13 and the second insulating layer 16 to the height of the second insulating layer 16 ranges from 0.3 to 0.7. Specifically, For example, 0.4, 0.5, 0.6, etc.
  • the thickness of the first insulating layer 13 and the second insulating layer 16 is 5-30 nm. In some embodiments, the thickness of the first insulating layer 13 and the second insulating layer 16 is 10-25 nm. In a specific embodiment, the thickness of the first insulating layer 13 is greater than the thickness of the second insulating layer 16, and the second insulating layer 16 has a thinner thickness. Therefore, fewer hot electrons can be stored in the first insulating layer 13. Effectively alleviate HEIP effect.
  • the fourth insulating layer 18 and the third insulating layer 15 separate the substrate 10 from the first insulating layer 13 and the second insulating layer 16.
  • the embodiment of the present disclosure effectively alleviates the HEIP effect by using the third insulating layer 15 to separate the first insulating layer 13 and the second insulating layer 16 without the need to add additional fourth insulating layer 18 and third insulating layer 15 . thickness, simplifying the process and increasing the process window.
  • the method further includes:
  • a second filling material layer 17' is formed above the third insulating layer 15 and the second insulating layer 16, and the second filling material layer 17' completely fills the first accommodating cavity T1 and the second accommodating cavity T2;
  • the second filling material layer 17 ′ is etched so that the top of the second filling material layer 17 ′ is flush with the top of the second insulating layer 16 , thereby forming the second filling layer 17 .
  • Embodiments of the present disclosure use a third insulating layer to separate the first insulating layer and the second insulating layer, thereby separating hot electrons trapped in the first insulating layer from hot electrons trapped in the second insulating layer. , preventing the hot electrons trapped in the second insulating layer from flowing into the first insulating layer, reducing the number of hot electrons stored in the first insulating layer.
  • the first insulating layer and the second insulating layer are isolated from each other. Compared with when the first insulating layer and the second insulating layer are not isolated, the first insulating layer and the second insulating layer have fewer carriers for storing hot electrons, so they can store fewer hot electrons. In this way, the HEIP effect can be effectively alleviated.

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Abstract

本公开实施例公开了一种半导体结构及其制造方法，所述半导体结构包括：衬底以及位于所述衬底内的第一隔离沟槽；第一绝缘层，覆盖所述第一隔离沟槽的底表面和侧壁的下部；第二绝缘层，覆盖所述第一隔离沟槽的侧壁的上部；第三绝缘层，至少部分位于所述第一绝缘层和所述第二绝缘层之间，以将所述第一绝缘层和所述第二绝缘层隔离。

Description

一种半导体结构及其制造方法
相关申请的交叉引用
本公开基于申请号为202210726332.2、申请日为2022年06月23日、发明名称为“一种半导体结构及其制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体制造领域，尤其涉及一种半导体结构及其制造方法。
背景技术
半导体结构，通常包括衬底、位于衬底上的多个晶体管以及位于衬底内用于隔离多个晶体管的隔离结构。晶体管通常采用平面栅结构，其栅极结构与隔离结构具有交叉部分。
然而，随着半导体结构不断朝着小型化、高集成度的方向发展，晶体管沟道区之间的电场迅速增加，进而产生许多热电子，导致热电子诱导穿通(Hot Electron Induced Punch Through，HEIP)效应，热电子会被捕获在隔离结构内，使晶体管的关断特性劣化，降低半导体结构的性能。
发明内容
本公开实施例提供一种半导体结构，包括:
衬底以及位于所述衬底内的第一隔离沟槽；
第一绝缘层，覆盖所述第一隔离沟槽的底表面和侧壁的下部；
第二绝缘层，覆盖所述第一隔离沟槽的侧壁的上部；
第三绝缘层，至少部分位于所述第一绝缘层和所述第二绝缘层之间，以将所述第一绝缘层和所述第二绝缘层隔离。
在一些实施例中，所述第一绝缘层、所述第二绝缘层的材料包括氮化物，所述第三绝缘层的材料包括氧化物。
在一些实施例中，所述第一绝缘层的高度和所述第二绝缘层的高度的比值范围在2至6之间，所述第三绝缘层位于所述第一绝缘层和所述第二绝缘层之间的部分的高度和所述第二绝缘层的高度的比值范围在0.3至0.7之间。
在一些实施例中，所述第一绝缘层与所述第二绝缘层的厚度为5-30nm。
在一些实施例中，还包括：
第四绝缘层，所述第四绝缘层位于所述第一隔离沟槽的内壁与所述第一绝缘层之间，且所述第四绝缘层覆盖所述第一隔离沟槽的底表面以及侧壁的下部；
第一填充层，所述第一填充层填充所述第一绝缘层在所述第一隔离沟槽内定义出的凹陷。
在一些实施例中，所述第三绝缘层包括底层和侧墙层，所述底层覆盖所述第四绝缘层、所述第一绝缘层与所述第一填充层的顶部，所述侧墙层位于所述第一隔离沟槽上部侧壁与所述第二绝缘层之间。
在一些实施例中，还包括：
第二填充层，所述第二填充层填充所述第二绝缘层与所述第三绝缘层的所述底层共同在所述第一隔离沟槽内定义出的凹陷。
在一些实施例中，还包括：
第二隔离沟槽，所述第二隔离沟槽包括第一子沟槽和第二子沟槽，所述第二子沟槽的宽度大于所述第一子沟槽的宽度。
在一些实施例中，所述第四绝缘层覆盖所述第二子沟槽的底表面和侧壁的下部，所述第一绝缘层填充所述第四绝缘层在所述第二子沟槽内定义的凹陷；所述第三绝缘层覆盖所述第二子沟槽侧壁的上部以及所述第四绝缘层和所述第一绝缘层的顶部；所述第二填充层填充所述第三绝缘层在所述第二子沟槽内定义的凹陷。
在一些实施例中，所述第一隔离沟槽位于器件核心区或外围区，用于隔离选择晶体管，所述第二隔离沟槽位于器件单元区，用于隔离存储单元。
本公开实施例还提供了一种半导体结构的制造方法，包括：
提供衬底；
刻蚀所述衬底形成第一隔离沟槽；
形成第一绝缘层，所述第一绝缘层覆盖所述第一隔离沟槽的底表面和侧壁的下部；
在所述第一绝缘层上方形成第三绝缘层，所述第三绝缘层至少覆盖所述第一绝缘层的顶部；
在所述第三绝缘层上方形成第二绝缘层，所述第二绝缘层覆盖所述第一隔离沟槽的侧壁的上部，所述第三绝缘层将所述第一绝缘层和所述第二绝缘层隔离。
在一些实施例中，在刻蚀所述衬底形成第一隔离沟槽的同一步骤中，还包括：
刻蚀所述衬底形成第二隔离沟槽，所述第二隔离沟槽包括第一子沟槽和第二子沟槽，所述第二子沟槽的宽度大于所述第一子沟槽的宽度。
在一些实施例中，在形成第一绝缘层之前，所述方法还包括：
形成第四绝缘材料层，所述第四绝缘材料层覆盖所述第一隔离沟槽和所述第二子沟槽的内表面，并填充所述第一子沟槽。
在一些实施例中，形成第一绝缘层包括：
形成第一绝缘材料层，所述第一绝缘材料层覆盖所述第四绝缘材料层，并充满所述第二子沟槽；
形成第一填充材料层，所述第一填充材料层覆盖所述第一绝缘材料层并充满所述第一隔离沟槽；
刻蚀所述第一填充材料层、所述第一绝缘材料层与所述第四绝缘材料层，使得所述第一绝缘材料层、所述第四绝缘材料层与所述第一填充材料层的顶部低于所述衬底的上表面，从而形成第一绝缘层、第四绝缘层和第一填充层。
在一些实施例中，所述形成第三绝缘层，包括：
形成第三绝缘材料层，刻蚀所述第三绝缘材料层形成覆盖所述第四绝缘层、所述第一绝缘层和所述第一填充层的顶部以及所述第一隔离沟槽和所述第二子沟槽侧壁的上部的第三绝缘层，所述第三绝缘层在所述第一隔离沟槽内的部分定义出第一容置腔，所述第三绝缘层在所述第二子沟槽内的部分定义出第二容置腔。
在一些实施例中，所述形成第二绝缘层，包括：
形成第二绝缘材料层，所述第二绝缘材料层覆盖所述第一容置腔的底表面和侧壁，且充满所述第二容置腔；
刻蚀所述第二绝缘材料层，去除位于所述第二容置腔内的第二绝缘材料层以及覆盖所述第一容置腔底表面的第二绝缘材料层，以形成覆盖所述第一容置腔侧壁的第二绝缘层。
在一些实施例中，在形成所述第二绝缘层之后，所述方法还包括：
在所述第三绝缘层和所述第二绝缘层上方形成第二填充材料层，所述第二填充材料层完全填充所述第一容置腔和所述第二容置腔；
刻蚀所述第二填充材料层使得所述第二填充材料层的顶部与所述第二绝缘层的顶部齐平，从而形成第二填充层。
本公开实施例提供的半导体结构及其制造方法，其中，所述半导体结构包括：衬底以及位于所述衬底内的第一隔离沟槽；第一绝缘层，覆盖所述第一隔离沟槽的底表面和侧壁的下部；第二绝缘层，覆盖所述第一隔离沟槽的侧壁的上部；第三绝缘层，至少部分位于所述第一绝缘层和所述第二绝缘层之间，以将所述第一绝缘层和所述第二绝缘层隔离。本公开实施例使用第三绝缘层将第一绝缘层和第二绝缘层间隔开，从而将被捕获在第一绝缘层内的热电子和被捕获在第二绝缘层内的热电子间隔开，阻止被捕获在第二绝缘层内的热电子流向第一绝缘层内，降低第一绝缘层内储存的热电子数量，同时，第一绝缘层和第二绝缘层是被隔断的，与第一绝缘层和第二绝缘层未被隔断时相比，第一绝缘层和第二绝缘层储存热电子的载体减少了，因此其能够储存的热电子较少，如此，能够有效缓解HEIP效应。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其它特征和优点将从说明书附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的半导体结构的俯视示意图；
图2为沿图1的线A-A'、B-B'截取的剖面结构示意图；
图3为本公开实施例提供的半导体结构制造方法的流程框图；
图4至图12为本公开实施例提供的半导体结构的工艺流程图。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在…… 之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
半导体结构，通常包括衬底、位于衬底上的多个晶体管、位于衬底内用于隔离多个晶体管的隔离沟槽以及位于隔离沟槽内的隔离结构。晶体管通常采用平面栅结构，其栅极结构与隔离结构具有交叉部分。隔离结构通常包括覆盖隔离沟槽内壁的氧化物层、覆盖氧化层的氮化物层，以及填充隔离沟槽的填充层。
然而，随着半导体结构不断朝着小型化、高集成度的方向发展，晶体管沟道区之间的电场迅速增加，进而产生许多热电子，热电子会被捕获在具有捕获高能电子能力的氮化物层内，被捕获的热电子可以吸引空穴集中到与隔离结构相邻的衬底内，使得晶体管的有效沟道长度小于原始长度，因此，即使没有向晶体管的栅极结构施加电压，电流也可以流动，使晶体管的关断特性劣化，并且晶体管的漏电流增加，降低半导体结构的性能。这就是热电子诱导穿通(Hot Electron Induced Punch Through Effect，HEIP)效应。
通常通过增加氧化物层的厚度使氮化物层和衬底之间的距离增大来缓解HEIP效应，然而，这增加了形成隔离结构的工艺难度。
基于此，提出了本公开实施例的以下技术方案。下面结合附图对本公开的具体实施方式做详细的说明。在详述本公开实施例时，为便于说明，示意图会不依一般比例做局部放大，而且所述示意图只是示例，其在此不应限制本公开的保护范围。
图1为本公开实施例提供的半导体结构的俯视示意图，图2为沿图1的线A-A'、B-B'截取的剖面结构示意图。以下结合图1至图2对本公开实施例提供的半导体结构再作进一步说明。
如图所示，半导体结构包括：衬底10以及位于衬底10内的第一隔离沟槽11；第一绝缘层13，覆盖第一隔离沟槽11的底表面和侧壁的下部；第二绝缘层16，覆盖第一隔离沟槽11的侧壁的上部；第三绝缘层15，至少部分位于第一绝缘层13和第二绝缘层16之间，以将第一绝缘层13和第二绝缘层16隔离。
在实际操作中，本公开实施例提供的半导体结构可以是三维动态随机存储器(3D DRAM)，但不限于此，半导体结构还可以是任何半导体结构。
衬底可以为半导体衬底，并且可以包括至少一个单质半导体材料(例如为硅(Si)衬底、锗(Ge)衬底)、至少一个III-V化合物半导体材料、至少一个II-VI化合物半导体材料、至少一个有机半导体材料或者在本领域已知的其他半导体材料。在一具体实施例中，衬底为硅衬底，硅衬底可经掺杂或未经掺杂。
在一实施例中，衬底10包括器件单元区101和器件核心区或外围区102。在一些实施例中，第一隔离沟槽11位于器件核心区或外围区102，用于隔离选择晶体管。具体地，第一隔离沟槽11在器件核心区或外围区102内限定出至少一个第一有源区AA1，在实际操作中，可以在第一有源区AA1上形成具有平面栅结构的选择晶体管，例如P型晶体管或N型晶体管。
在一实施例中，第一绝缘层13、第二绝缘层16的材料包括氮化物。本公开实施例使用氮化物作为第一绝缘层13和第二绝缘层16的材料，如此，可以根据需求提高晶体管沟道区的拉伸应力或压缩应力，从而满足晶体管对应力的需求，提高晶体管沟道区载流子的迁移率。具体的，拉伸应力在沟道区形成拉伸应变，可以增加N型晶体管的电子迁移率，而压缩应力在沟道区形成压缩应变，可以增加P型晶体管的空穴迁移率。第一绝缘层13、 第二绝缘层16的材料可以相同或不同。在一具体实施例中，第一绝缘层13和第二绝缘层16的材料相同，例如，氮化硅。但不限于此，任何满足上述应力要求的材料都可以作为第一绝缘层13和第二绝缘层16的材料。第三绝缘层15的材料包括氧化物，例如，氧化硅。
第一绝缘层13和第二绝缘层16具有捕获热电子的能力。本公开实施例使用第三绝缘层15将第一绝缘层13和第二绝缘层16间隔开，从而将被捕获在第一绝缘层13内的热电子和被捕获在第二绝缘层16内的热电子间隔开，阻止被捕获在第二绝缘层16内的热电子流向第一绝缘层13内，降低第一绝缘层13内储存的热电子的数量，同时，第一绝缘层13和第二绝缘层16是被隔断的，与第一绝缘层13和第二绝缘层16未被隔断时相比，第一绝缘层13和第二绝缘层16储存热电子的载体减少了，因此其能够储存的热电子较少，如此，能够有效缓解HEIP效应。
第一绝缘层13的高度和第二绝缘层16的高度的比值不宜过大也不宜过小。第一绝缘层13的高度和第二绝缘层16的高度的比值过大时，第一绝缘层13将延伸至第一隔离沟槽11的上部，且第一绝缘层13内储存的热电子较多，第一有源区AA1的上部将聚集较多的空穴，如此，缓解HEIP效应的效果不明显；第一绝缘层13的高度和第二绝缘层16的高度的比值过小时，位于第一隔离沟槽11上部的第二绝缘层16的高度较高，第二绝缘层16能够捕获的热电子的数量较多，第一有源区AA1的上部将聚集较多的空穴，如此，缓解HEIP效应的效果不明显。在一实施例中，第一绝缘层13的高度和第二绝缘层16的高度的比值范围在2至6之间，具体的，例如，3、4、5等。
第三绝缘层15位于第一绝缘层13和第二绝缘层16之间的部分的高度不宜过大也不宜过小。当第三绝缘层15位于第一绝缘层13和第二绝缘层16之间的部分的高度过大时，第一绝缘层13和第二绝缘层16的高度之和较小，如此，第一绝缘层13和第二绝缘层16提升衬底10应力的效果不明显；当第三绝缘层15位于第一绝缘层13和第二绝缘层16之间的部分的高度过小时，缓解HEIP效应的效果不明显。在一实施例中，第三绝缘层15位于第一绝缘层13和第二绝缘层16之间的部分的高度和第二绝缘层16的高度的比值范围在0.3至0.7之间，具体的，例如0.4、0.5、0.6等。
在一实施例中，第一绝缘层13与第二绝缘层16的厚度为5-30nm。在一些实施例中，第一绝缘层13与第二绝缘层16的厚度为10-25nm。在一具体实施例中，第一绝缘层13的厚度大于第二绝缘层16的厚度，第二绝缘层16具有较薄的厚度，如此，第一绝缘层13内能够储存的热电子更少，有效缓解HEIP效应。
在一实施例中，半导体结构还包括：第四绝缘层18，第四绝缘层18位于第一隔离沟槽11的内壁与第一绝缘层13之间，且第四绝缘层18覆盖第一隔离沟槽11的底表面以及侧壁的下部；第一填充层14，第一填充层14填充第一绝缘层13在第一隔离沟槽11内定义出的凹陷S1。第四绝缘层18的材料可以和第三绝缘层15的材料相同，例如为氧化硅。第一填充层14的材料可以为氧化物，例如氧化硅。
在一实施例中，第三绝缘层15包括底层151和侧墙层152，底层151覆盖第四绝缘层18、第一绝缘层13与第一填充层14的顶部，侧墙层152位于第一隔离沟槽11上部侧壁与第二绝缘层16之间。在一些实施例中，第三绝缘层15还覆盖衬底10的上表面。
本公开实施例通过在衬底10和第一绝缘层13、第二绝缘层16之间设置第四绝缘层18、第三绝缘层15，将衬底10与第一绝缘层13、第二绝缘层16间隔开，能够进一步缓解HEIP效应。此外，本公开实施例通过使用第三绝缘层15将第一绝缘层13和第二绝缘层16间隔开，有效缓解了HEIP效应，如此，不需要额外加厚第四绝缘层18、第三绝缘层15的厚度，简化了工艺且提高了工艺窗口。
在一实施例中，半导体结构还包括：第二填充层17，第二填充层17填充第二绝缘层16与第三绝缘层15的底层151共同在第一隔离沟槽11内定义出的凹陷S2。第二填充层17的材料可以和第一填充层14的材料相同，例如为氧化硅。
在一实施例中，半导体结构还包括：第二隔离沟槽12，第二隔离沟槽12包括第一子沟槽121和第二子沟槽122，第二子沟槽122的宽度大于第一子沟槽121的宽度。具体的，第二隔离沟槽12位于器件单元区101，用于隔离存储单元，并在器件单元区101内限定出多个相互平行排列的第二有源区AA2。在实际操作中，第一隔离沟槽11和第二隔离沟槽12在同一 工艺步骤中形成，且第一隔离沟槽11的宽度大于第一子沟槽121、第二子沟槽122的宽度。可以理解的，由于第一隔离沟槽11、第二子沟槽122的宽度大于第一子沟槽121的宽度，在相同的刻蚀工艺条件下会使得第一隔离沟槽11、第二子沟槽122的深度大于第一子沟槽121的深度。
在一实施例中，第四绝缘层18覆盖第二子沟槽122的底表面和侧壁的下部，第一绝缘层13填充第四绝缘层18在第二子沟槽122内定义的凹陷S3；第三绝缘层15覆盖第二子沟槽122侧壁的上部以及第四绝缘层18和第一绝缘层13的顶部；第二填充层17填充第三绝缘层15在第二子沟槽122内定义的凹陷S4。在一些实施例中，第四绝缘层18填充第一子沟槽121的下部，第三绝缘层15填充第一子沟槽121的上部。
本公开实施例还提供了一种半导体结构的制造方法，如图3所示，方法包括以下步骤：
步骤301、提供衬底；
步骤302、刻蚀衬底形成第一隔离沟槽；
步骤303、形成第一绝缘层，第一绝缘层覆盖第一隔离沟槽的底表面和侧壁的下部；
步骤304、在第一绝缘层上方形成第三绝缘层，第三绝缘层至少覆盖第一绝缘层的顶部；
步骤305、在第三绝缘层上方形成第二绝缘层，第二绝缘层覆盖第一隔离沟槽的侧壁的上部，第三绝缘层将第一绝缘层和第二绝缘层隔离。
下面结合图4至图12、图2对本公开实施例的半导体结构的制造方法再做进一步详细的说明，其中，图4至图12为各工艺步骤沿着图1的线A-A'、B-B'截取的剖面结构示意图。
首先，如图4所示，执行步骤301，提供衬底10。
衬底可以为半导体衬底，并且可以包括至少一个单质半导体材料(例如为硅(Si)衬底、锗(Ge)衬底)、至少一个III-V化合物半导体材料、至少一个II-VI化合物半导体材料、至少一个有机半导体材料或者在本领域已知的其他半导体材料。在一具体实施例中，衬底为硅衬底，硅衬底可经掺杂或未经掺杂。
在一实施例中，衬底10包括器件单元区101和器件核心区或外围区 102。在实际操作中，可在器件单元区101形成存储单元，在器件核心区或外围区102形成选择晶体管。
接下来，执行步骤302，如图5所示，刻蚀衬底10形成第一隔离沟槽11。
具体的，可采用光刻和干法/湿法刻蚀工艺形成第一隔离沟槽11，第一隔离沟槽11形成于器件核心区或外围区102，并在器件核心区或外围区102内限定出至少一个第一有源区AA1，在实际操作中，后续可以在第一有源区AA1上形成具有平面栅结构的选择晶体管，例如P型晶体管或N型晶体管。
在一实施例中，在刻蚀衬底10形成第一隔离沟槽11的同一步骤中，还包括：刻蚀衬底10形成第二隔离沟槽12，第二隔离沟槽12包括第一子沟槽121和第二子沟槽122，第二子沟槽122的宽度大于第一子沟槽121的宽度。在一些实施例中，第二隔离沟槽12形成于器件单元区101并在器件单元区101内限定出多个相互平行排列的第二有源区AA2。在实际操作中，后续可以在第二有源区AA2上形成存储单元，第二隔离沟槽12用于隔离存储单元。本公开实施例中，第一隔离沟槽11和第二隔离沟槽12在同一工艺步骤中形成，如此，能够减少一道掩膜工艺，从而简化工艺。
在一实施例中，第一隔离沟槽11的宽度大于第一子沟槽121、第二子沟槽122的宽度。可以理解的，由于第一隔离沟槽11、第二子沟槽122的宽度大于第一子沟槽121的宽度，在相同的刻蚀工艺条件下会使得第一隔离沟槽11、第二子沟槽122的深度大于第一子沟槽121的深度。
接下来，执行步骤303，如图7至图8所示，形成第一绝缘层13，第一绝缘层13覆盖第一隔离沟槽11的底表面和侧壁的下部。
在一实施例中，如图6所示，在形成第一绝缘层13之前，还包括：形成第四绝缘材料层18'，第四绝缘材料层18'覆盖第一隔离沟槽11和第二子沟槽122的内表面，并填充第一子沟槽121。在一些实施例中，第四绝缘材料层18'还覆盖衬底10的上表面。可以理解的，由于第一子沟槽121的深度和宽度较小，因此在相同的沉积工艺条件下，第四绝缘材料层18'能够充满第一子沟槽121而不会充满第一隔离沟槽11、第二子沟槽122，使得最终形成的第四绝缘层18填充第一子沟槽121的下部。第四绝缘材料层18' 可以采用原子层沉积(ALD)工艺结合原位水汽生成工艺(ISSG)形成。第四绝缘层18的材料包括氧化物，例如，氧化硅。
再次参见图7至图8，形成第一绝缘层13包括：
形成第一绝缘材料层13'，第一绝缘材料层13'覆盖第四绝缘材料层18'，并充满第二子沟槽122；
形成第一填充材料层14'，第一填充材料层14'覆盖第一绝缘材料层13'并充满第一隔离沟槽11；
刻蚀第一填充材料层14'、第一绝缘材料层13'与第四绝缘材料层18'，使得第一绝缘材料层13'、第四绝缘材料层18'与第一填充材料层14'的顶部低于衬底10的上表面，从而形成第一绝缘层13、第四绝缘层18和第一填充层14。
可以理解的，与第一隔离沟槽11相比，第二子沟槽122的宽度较小，因此在相同的沉积工艺条件下，第一绝缘材料层13'能够充满第二子沟槽122而不会充满第一隔离沟槽11。第一绝缘材料层13'、第一填充材料层14'可以采用化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺或其组合形成。第一绝缘层13的材料包括氮化物，例如氮化硅。第一填充层14的材料包括氧化物，例如氧化硅。
接下来，执行步骤304，如图9所示，在第一绝缘层13上方形成第三绝缘层15，第三绝缘层15至少覆盖第一绝缘层13的顶部。
具体的，形成第三绝缘层15，包括：形成第三绝缘材料层(未图示)，刻蚀第三绝缘材料层(未图示)形成覆盖第四绝缘层18、第一绝缘层13和第一填充层14的顶部以及第一隔离沟槽11和第二子沟槽122侧壁的上部的第三绝缘层15，第三绝缘层15在第一隔离沟槽11内的部分定义出第一容置腔T1，第三绝缘层15在第二子沟槽122内的部分定义出第二容置腔T2。第三绝缘层15还覆盖衬底10的上表面。
可以理解的，第一子沟槽121的宽度和深度较小，因此在相同的沉积工艺条件下，第三绝缘层15可以充满第一子沟槽121未被第四绝缘层18填充的部分。第三绝缘层15可以采用化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺或其组合形成。第三绝缘层15的材料包括氧化物，例如氧化硅。
接下来，执行步骤305，如图10至图11所示，在第三绝缘层15上方形成第二绝缘层16，第二绝缘层16覆盖第一隔离沟槽11的侧壁的上部，第三绝缘层15将第一绝缘层13和第二绝缘层16隔离。
具体的，形成第二绝缘层16，包括：
形成第二绝缘材料层16'，第二绝缘材料层16'覆盖第一容置腔T1的底表面和侧壁，且充满第二容置腔T2；
刻蚀第二绝缘材料层16'，去除位于第二容置腔T2内的第二绝缘材料层16'以及覆盖第一容置腔T1底表面的第二绝缘材料层16'，以形成覆盖第一容置腔T1侧壁的第二绝缘层16。
可以理解的，与第一隔离沟槽11相比，第二子沟槽122的宽度较小，因此第二容置腔T2的宽度小于第一容置腔T1的宽度，在相同的沉积工艺条件下，第二绝缘材料层16'可以充满第二容置腔T2而不充满第一容置腔T1。第二绝缘材料层16'可以采用化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺或其组合形成。
在一实施例中，第二绝缘层16的材料包括氮化物。本公开实施例使用氮化物作为第一绝缘层13和第二绝缘层16的材料，允许根据需求提高晶体管沟道区的拉伸应力或压缩应力，从而满足晶体管对应力的需求，提高晶体管沟道区载流子的迁移率。具体的，拉伸应力在沟道区形成拉伸应变，可以增加N型晶体管的电子迁移率，而压缩应力在沟道区形成压缩应变，可以增加P型晶体管的空穴迁移率。第一绝缘层13、第二绝缘层16的材料可以相同或不同。在一具体实施例中，第一绝缘层13和第二绝缘层16的材料相同，例如氮化硅。但不限于此，任何满足上述应力要求的材料都可以作为第一绝缘层13和第二绝缘层16的材料。
第一绝缘层13和第二绝缘层16具有捕获热电子的能力。本公开实施例使用第三绝缘层15将第一绝缘层13和第二绝缘层16间隔开，从而将被捕获在第一绝缘层13内的热电子和被捕获在第二绝缘层16内的热电子间隔开，尤其是在后续的热处理等工艺中，第二绝缘层16内的热电子会流失，第三绝缘层15的存在能够阻止被捕获在第二绝缘层16内的热电子流向第一绝缘层13内，如此，能够降低第一绝缘层13内储存的热电子的数量，同时，第一绝缘层13和第二绝缘层16是被隔断的，与第一绝缘层13和第 二绝缘层16未被隔断时相比，第一绝缘层13和第二绝缘层16储存热电子的载体减少了，因此其能够储存的热电子较少，如此，能够有效缓解HEIP效应。
第一绝缘层13的高度和第二绝缘层16的高度的比值不宜过大也不宜过小。第一绝缘层13的高度和第二绝缘层16的高度的比值过大时，第一绝缘层13将延伸至第一隔离沟槽11的上部，且第一绝缘层13内储存的热电子较多，第一有源区AA1的上部将聚集较多的空穴，如此，缓解HEIP效应的效果不明显；第一绝缘层13的高度和第二绝缘层16的高度的比值过小时，位于第一隔离沟槽11上部的第二绝缘层16的高度较高，第二绝缘层16能够捕获的热电子的数量较多，第一有源区AA1的上部将聚集较多的空穴，如此，缓解HEIP效应的效果不明显。在一实施例中，第一绝缘层13的高度和第二绝缘层16的高度的比值范围在2至6之间，具体的，例如，3、4、5等。
第三绝缘层15位于第一绝缘层13和第二绝缘层16之间的部分的高度不宜过大也不宜过小。当第三绝缘层15位于第一绝缘层13和第二绝缘层16之间的部分的高度过大时，第一绝缘层13和第二绝缘层16的高度之和较小，如此，第一绝缘层13和第二绝缘层16提升衬底10应力的效果不明显；当第三绝缘层15位于第一绝缘层13和第二绝缘层16之间的部分的高度过小时，缓解HEIP效应的效果不明显。在一实施例中，第三绝缘层15位于第一绝缘层13和第二绝缘层16之间的部分的高度和第二绝缘层16的高度的比值范围在0.3至0.7之间，具体的，例如0.4、0.5、0.6等。
在一实施例中，第一绝缘层13与第二绝缘层16的厚度为5-30nm。在一些实施例中，第一绝缘层13与第二绝缘层16的厚度为10-25nm。在一具体实施例中，第一绝缘层13的厚度大于第二绝缘层16的厚度，第二绝缘层16具有较薄的厚度，如此，第一绝缘层13内能够储存的热电子更少，有效缓解HEIP效应。
再次参见图11，可以看出，第四绝缘层18、第三绝缘层15将衬底10和第一绝缘层13、第二绝缘层16间隔开，如此，能够进一步缓解HEIP效应。此外，本公开实施例通过使用第三绝缘层15将第一绝缘层13和第二绝缘层16间隔开，有效缓解了HEIP效应，不需要额外增加第四绝缘层18、 第三绝缘层15的厚度，简化了工艺且提高了工艺窗口。
接下来，如图12和图2所示，在形成第二绝缘层16之后，方法还包括：
在第三绝缘层15和第二绝缘层16上方形成第二填充材料层17'，第二填充材料层17'完全填充第一容置腔T1和第二容置腔T2；
刻蚀第二填充材料层17'使得第二填充材料层17'的顶部与第二绝缘层16的顶部齐平，从而形成第二填充层17。
应当说明的是，本领域技术人员能够对上述步骤顺序进行变换而并不离开本公开的保护范围，以上所述，仅为本公开的可选实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例使用第三绝缘层将第一绝缘层和第二绝缘层间隔开，从而将被捕获在第一绝缘层内的热电子和被捕获在第二绝缘层内的热电子间隔开，阻止被捕获在第二绝缘层内的热电子流向第一绝缘层内，降低第一绝缘层内储存的热电子数量，同时，第一绝缘层和第二绝缘层是被隔断的，与第一绝缘层和第二绝缘层未被隔断时相比，第一绝缘层和第二绝缘层储存热电子的载体减少了，因此其能够储存的热电子较少，如此，能够有效缓解HEIP效应。

Claims (17)

  1. 一种半导体结构，包括：
    衬底以及位于所述衬底内的第一隔离沟槽；
    第一绝缘层，覆盖所述第一隔离沟槽的底表面和侧壁的下部；
    第二绝缘层，覆盖所述第一隔离沟槽的侧壁的上部；
    第三绝缘层，至少部分位于所述第一绝缘层和所述第二绝缘层之间，以将所述第一绝缘层和所述第二绝缘层隔离。
  2. 根据权利要求1所述的半导体结构，其中，所述第一绝缘层、所述第二绝缘层的材料包括氮化物，所述第三绝缘层的材料包括氧化物。
  3. 根据权利要求1所述的半导体结构，其中，所述第一绝缘层的高度和所述第二绝缘层的高度的比值范围在2至6之间，所述第三绝缘层位于所述第一绝缘层和所述第二绝缘层之间的部分的高度和所述第二绝缘层的高度的比值范围在0.3至0.7之间。
  4. 根据权利要求1所述的半导体结构，其中，
    所述第一绝缘层与所述第二绝缘层的厚度为5-30nm。
  5. 根据权利要求1所述的半导体结构，其中，还包括：
    第四绝缘层，所述第四绝缘层位于所述第一隔离沟槽的内壁与所述第一绝缘层之间，且所述第四绝缘层覆盖所述第一隔离沟槽的底表面以及侧壁的下部；
    第一填充层，所述第一填充层填充所述第一绝缘层在所述第一隔离沟槽内定义出的凹陷。
  6. 根据权利要求5所述的半导体结构，其中，
    所述第三绝缘层包括底层和侧墙层，所述底层覆盖所述第四绝缘层、所述第一绝缘层与所述第一填充层的顶部，所述侧墙层位于所述第一隔离沟槽上部侧壁与所述第二绝缘层之间。
  7. 根据权利要求6所述的半导体结构，其中，还包括：
    第二填充层，所述第二填充层填充所述第二绝缘层与所述第三绝缘层的所述底层共同在所述第一隔离沟槽内定义出的凹陷。
  8. 根据权利要求7所述的半导体结构，其中，还包括：
    第二隔离沟槽，所述第二隔离沟槽包括第一子沟槽和第二子沟槽，所 述第二子沟槽的宽度大于所述第一子沟槽的宽度。
  9. 根据权利要求8所述的半导体结构，其中，
    所述第四绝缘层覆盖所述第二子沟槽的底表面和侧壁的下部，所述第一绝缘层填充所述第四绝缘层在所述第二子沟槽内定义的凹陷；
    所述第三绝缘层覆盖所述第二子沟槽侧壁的上部以及所述第四绝缘层和所述第一绝缘层的顶部；
    所述第二填充层填充所述第三绝缘层在所述第二子沟槽内定义的凹陷。
  10. 根据权利要求8所述的半导体结构，其中，所述第一隔离沟槽位于器件核心区或外围区，用于隔离选择晶体管，所述第二隔离沟槽位于器件单元区，用于隔离存储单元。
  11. 一种半导体结构的制造方法，包括：
    提供衬底；
    刻蚀所述衬底形成第一隔离沟槽；
    形成第一绝缘层，所述第一绝缘层覆盖所述第一隔离沟槽的底表面和侧壁的下部；
    在所述第一绝缘层上方形成第三绝缘层，所述第三绝缘层至少覆盖所述第一绝缘层的顶部；
    在所述第三绝缘层上方形成第二绝缘层，所述第二绝缘层覆盖所述第一隔离沟槽的侧壁的上部，所述第三绝缘层将所述第一绝缘层和所述第二绝缘层隔离。
  12. 根据权利要求11所述的制造方法，其中，在刻蚀所述衬底形成第一隔离沟槽的同一步骤中，还包括：
    刻蚀所述衬底形成第二隔离沟槽，所述第二隔离沟槽包括第一子沟槽和第二子沟槽，所述第二子沟槽的宽度大于所述第一子沟槽的宽度。
  13. 根据权利要求12所述的方法，其中，在形成第一绝缘层之前，所述方法还包括：
    形成第四绝缘材料层，所述第四绝缘材料层覆盖所述第一隔离沟槽和所述第二子沟槽的内表面，并填充所述第一子沟槽。
  14. 根据权利要求13所述的方法，其中，形成第一绝缘层包括：
    形成第一绝缘材料层，所述第一绝缘材料层覆盖所述第四绝缘材料层，并充满所述第二子沟槽；
    形成第一填充材料层，所述第一填充材料层覆盖所述第一绝缘材料层并充满所述第一隔离沟槽；
    刻蚀所述第一填充材料层、所述第一绝缘材料层与所述第四绝缘材料层，使得所述第一绝缘材料层、所述第四绝缘材料层与所述第一填充材料层的顶部低于所述衬底的上表面，从而形成第一绝缘层、第四绝缘层和第一填充层。
  15. 根据权利要求14所述的方法，其中，所述形成第三绝缘层，包括：
    形成第三绝缘材料层，刻蚀所述第三绝缘材料层形成覆盖所述第四绝缘层、所述第一绝缘层和所述第一填充层的顶部以及所述第一隔离沟槽和所述第二子沟槽侧壁的上部的第三绝缘层，所述第三绝缘层在所述第一隔离沟槽内的部分定义出第一容置腔，所述第三绝缘层在所述第二子沟槽内的部分定义出第二容置腔。
  16. 根据权利要求15所述的方法，其中，所述形成第二绝缘层，包括：
    形成第二绝缘材料层，所述第二绝缘材料层覆盖所述第一容置腔的底表面和侧壁，且充满所述第二容置腔；
    刻蚀所述第二绝缘材料层，去除位于所述第二容置腔内的第二绝缘材料层以及覆盖所述第一容置腔底表面的第二绝缘材料层，以形成覆盖所述第一容置腔侧壁的第二绝缘层。
  17. 根据权利要求16所述的方法，其中，在形成所述第二绝缘层之后，所述方法还包括：
    在所述第三绝缘层和所述第二绝缘层上方形成第二填充材料层，所述第二填充材料层完全填充所述第一容置腔和所述第二容置腔；
    刻蚀所述第二填充材料层使得所述第二填充材料层的顶部与所述第二绝缘层的顶部齐平，从而形成第二填充层。
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US12419043B2 (en) 2025-09-16
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US20230017189A1 (en) 2023-01-19
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