WO2024000496A1 - 栅极驱动电路和显示面板 - Google Patents

栅极驱动电路和显示面板 Download PDF

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Publication number
WO2024000496A1
WO2024000496A1 PCT/CN2022/103086 CN2022103086W WO2024000496A1 WO 2024000496 A1 WO2024000496 A1 WO 2024000496A1 CN 2022103086 W CN2022103086 W CN 2022103086W WO 2024000496 A1 WO2024000496 A1 WO 2024000496A1
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WO
WIPO (PCT)
Prior art keywords
transistor
pull
shift register
electrically connected
register unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/103086
Other languages
English (en)
French (fr)
Other versions
WO2024000496A9 (zh
Inventor
霍培荣
刘长城
徐敬义
梁朝
肖振宏
刘鹏
闫伟
刘建涛
李波
刘弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Ordos Yuansheng Optoelectronics Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to PCT/CN2022/103086 priority Critical patent/WO2024000496A1/zh
Priority to EP22948599.0A priority patent/EP4425469A4/en
Priority to US18/563,532 priority patent/US12456438B2/en
Priority to CN202280002048.9A priority patent/CN115298726B/zh
Publication of WO2024000496A1 publication Critical patent/WO2024000496A1/zh
Publication of WO2024000496A9 publication Critical patent/WO2024000496A9/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the purpose of this disclosure is to overcome the above-mentioned shortcomings of the prior art, provide a gate drive circuit and a display panel, and reduce the frame of the display panel.
  • a display panel including a display area and a peripheral area surrounding the display area; a gate driving circuit is provided in the peripheral area; the gate driving circuit includes a plurality of cascaded circuits in sequence. shift register unit;
  • the shift register unit includes a first shift register unit and a second shift register unit, the first shift register unit and the second shift register unit are spaced apart from each other; the first shift register unit The number of transistors of the unit is smaller than the number of transistors of the second shift register unit.
  • the display area is provided with a plurality of pixel driving circuits; at least part of the signal output by the first shift register unit and at least part of the signal output by the second shift register unit are used for drive the pixel driving circuit.
  • the gate driving circuit is provided on one side of the display area in the row direction;
  • the peripheral area is provided with a first circuit area for laying out the first shift register unit and a second circuit area for laying out the second shift register unit;
  • a part of the second circuit area is located on a side of the first circuit area away from the display area.
  • the display panel is provided with an inner wiring group and an outer wiring group corresponding to the gate driving circuit, and the driver in the inner wiring group and the outer wiring group
  • the wiring is used to drive the gate drive circuit, and the inner wiring group is located on the side of the outer wiring group close to the display area;
  • the shift register unit group is electrically connected to any drive wire of the external wire group through at most one adapter wire.
  • the first shift register unit and the second shift register unit that are respectively located in two different shift register unit groups and are adjacent are electrically connected to the same first low-level signal line;
  • the reset control line is used to provide a reset control signal to the shift register unit group
  • the first scan control line is used to provide a first scan control signal to the shift register unit group; the second scan control line is used to provide a second scan control signal to the shift register unit group; A scan control signal and the second scan control signal are inverted signals.
  • the first shift register unit includes a first input transistor and a second input transistor
  • the second shift register unit includes a first input transistor and a second input transistor
  • An input transistor is located between the first input transistor and the external wiring group and is arranged along the row direction
  • the second input transistor is located between the second input transistor and the external wiring group, and Arrange along the row direction
  • the source of the first input transistor and the source of the first input transistor are electrically connected to the first scan control line through the same conductive structure;
  • the source electrode of the second input transistor and the source electrode of the second input transistor are electrically connected to the second scan control line through the same conductive structure.
  • the first shift register unit includes:
  • a first input transistor The source of the first input transistor is used to load the first scan control signal.
  • the drain of the first input transistor is electrically connected to the pull-up node.
  • the gate of the first input transistor is used to load the first scan control signal. Electrically connected to the output end of the upper stage shift register unit;
  • a second input transistor The source of the second input transistor is used to load the second scan control signal.
  • the drain of the second input transistor is electrically connected to the pull-up node.
  • the gate of the second input transistor is Electrically connected to the pull-down node, and used to be electrically connected to the output end of the next-level shift register unit; the first scan control signal and the second scan control signal are inverted signals;
  • the third capacitor has a first electrode plate of the third capacitor and a second electrode plate of the third capacitor; the second electrode plate of the third capacitor is electrically connected to the pull-up node, and the first electrode plate of the third capacitor The electrode plate is electrically connected to the output end of the first shift register unit;
  • the drain of the first output transistor is electrically connected to the first electrode plate of the third capacitor, the gate of the first output transistor is electrically connected to the pull-up node;
  • the first clock signal and the second clock signal are inverted signals;
  • the source of the second output transistor is used to load a low-level signal.
  • the drain of the second output transistor is electrically connected to the first electrode plate of the third capacitor.
  • the second output The gate of the transistor is electrically connected to the pull-down node;
  • the source of the pull-down control transistor is used to load the low-level signal
  • the drain of the pull-down control transistor is electrically connected to the pull-down node
  • the gate of the pull-down control transistor is connected to the third pull-down control transistor.
  • the gate of an input transistor is electrically connected.
  • the first input transistor includes two sub-transistors connected in series, and the two sub-transistors have a common gate;
  • the second input transistor includes two sub-transistors connected in series, and the two sub-transistors have a common gate.
  • the first shift register unit further includes:
  • the source of the touch control transistor is used to load the low-level signal
  • the drain of the touch control transistor is electrically connected to the first electrode plate of the third capacitor
  • the touch control transistor The gate of the control transistor is used to load the touch control signal.
  • the second shift register unit includes:
  • a first input transistor The source of the first input transistor is used to load the first scan control signal.
  • the drain of the first input transistor is used to be electrically connected to the pull-up control node.
  • the gate of the first input transistor is used to load the first scan control signal.
  • the pole is used for electrical connection with the output end of the shift register unit of the upper stage;
  • a second input transistor The source of the second input transistor is used to load a second scan control signal.
  • the drain of the second input transistor is used to be electrically connected to the pull-up control node.
  • the second input transistor The gate is used to be electrically connected to the output end of the shift register unit of the next stage; the first scan control signal and the second scan control signal are inverted signals;
  • the first capacitor includes a first electrode plate of the first capacitor and a second electrode plate of the first capacitor; the first electrode plate of the first capacitor is electrically connected to the output end of the second shift register unit, and the The second electrode plate of the first capacitor is electrically connected to the pull-up node;
  • the second capacitor includes a first electrode plate of the second capacitor and a second electrode plate of the second capacitor; the first electrode plate of the second capacitor is electrically connected to the pull-down node, and the second electrode plate of the second capacitor is For loading low-level signals;
  • the drain of the first output transistor is electrically connected to the pull-up node, the drain of the first output transistor is electrically connected to the first electrode plate of the first capacitor;
  • the first clock signal and the second clock signal are inverted signals;
  • the source of the second output transistor is used to load the low-level signal.
  • the drain of the second output transistor is electrically connected to the first electrode plate of the first capacitor.
  • the gates of the two output transistors are electrically connected to the pull-down node;
  • a first pull-down control transistor The source of the first pull-down control transistor is used to load the low-level signal.
  • the drain of the first pull-down control transistor is electrically connected to the pull-down node.
  • the gate of the pull-up control transistor is electrically connected to the pull-up control node;
  • a second pull-down control transistor the drain of the second pull-down control transistor is electrically connected to the pull-down node, and the gate of the second pull-down control transistor is electrically connected to the source of the second pull-down control transistor;
  • One of the source of the second pull-down control transistor and the source of the first output transistor is used to load the first clock signal and the other is used to load the second clock signal;
  • the source of the second pull-down transistor is used to load the low-level signal
  • the drain of the second pull-down transistor is electrically connected to the pull-down node
  • the gate of the second pull-down transistor electrically connected to the first electrode plate of the first capacitor
  • the source of the reset transistor is used to load the low level signal
  • the drain of the reset transistor is electrically connected to the pull-up control node
  • the gate of the reset transistor is used to load the reset control signal ;
  • the first input transistor includes two sub-transistors connected in series, and the two sub-transistors have a common gate;
  • the second shift register unit further includes an enable transistor and a touch control transistor; the pull-up control node and the pull-up node are electrically connected through the enable transistor;
  • each shift register unit is used to drive one row of pixel driving circuits.
  • a first input transistor The source of the first input transistor is used to load the first scan control signal.
  • the drain of the first input transistor is electrically connected to the pull-up node.
  • the gate of the first input transistor is used to load the first scan control signal. Electrically connected to the output end of the upper stage shift register unit;
  • a second input transistor The source of the second input transistor is used to load the second scan control signal.
  • the drain of the second input transistor is electrically connected to the pull-up node.
  • the gate of the second input transistor is Electrically connected to the pull-down node, and used to be electrically connected to the output end of the next-level shift register unit; the first scan control signal and the second scan control signal are inverted signals;
  • the third capacitor has a first electrode plate of the third capacitor and a second electrode plate of the third capacitor; the second electrode plate of the third capacitor is electrically connected to the pull-up node, and the first electrode plate of the third capacitor The electrode plate is electrically connected to the output end of the first shift register unit;
  • the drain of the first output transistor is electrically connected to the first electrode plate of the third capacitor, the gate of the first output transistor is electrically connected to the pull-up node;
  • the first clock signal and the second clock signal are inverted signals;
  • the second input transistor includes two sub-transistors connected in series, and the two sub-transistors have a common gate.
  • the second shift register unit includes:
  • a first input transistor The source of the first input transistor is used to load the first scan control signal.
  • the drain of the first input transistor is used to be electrically connected to the pull-up control node.
  • the gate of the first input transistor is used to load the first scan control signal.
  • the pole is used for electrical connection with the output end of the shift register unit of the upper stage;
  • the drain of the first output transistor is electrically connected to the pull-up node, the drain of the first output transistor is electrically connected to the first electrode plate of the first capacitor;
  • the first clock signal and the second clock signal are inverted signals;
  • the source of the second output transistor is used to load the low-level signal.
  • the drain of the second output transistor is electrically connected to the first electrode plate of the first capacitor.
  • the gates of the two output transistors are electrically connected to the pull-down node;
  • a first pull-down transistor the source of the first pull-down transistor is used to load the low-level signal, the drain of the first pull-down transistor is electrically connected to the pull-up control node, the first pull-down transistor is The gate of the pull-down transistor is electrically connected to the pull-down node;
  • a first pull-down control transistor The source of the first pull-down control transistor is used to load the low-level signal.
  • the drain of the first pull-down control transistor is electrically connected to the pull-down node.
  • the gate of the pull-up control transistor is electrically connected to the pull-up control node;
  • a second pull-down control transistor the drain of the second pull-down control transistor is electrically connected to the pull-down node, and the gate of the second pull-down control transistor is electrically connected to the source of the second pull-down control transistor;
  • One of the source of the second pull-down control transistor and the source of the first output transistor is used to load the first clock signal and the other is used to load the second clock signal;
  • the source of the second pull-down transistor is used to load the low-level signal
  • the drain of the second pull-down transistor is electrically connected to the pull-down node
  • the gate of the second pull-down transistor electrically connected to the first electrode plate of the first capacitor
  • the source of the reset transistor is used to load the low level signal
  • the drain of the reset transistor is electrically connected to the pull-up control node
  • the gate of the reset transistor is used to load the reset control signal ;
  • the pull-up control node and the pull-up node are electrically connected.
  • the first input transistor includes two sub-transistors connected in series, and the two sub-transistors have a common gate;
  • the second input transistor includes two sub-transistors connected in series, and the two sub-transistors have a common gate.
  • FIG. 3 is a schematic distribution diagram of a gate driving circuit in an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a shift register unit in an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a semiconductor layer in an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of the source and drain metal layers in an embodiment of the present disclosure.
  • FIG. 9 is a schematic timing diagram between two adjacent levels of shift register units in an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • a transistor is a component that includes at least three terminals: a gate, a drain, and a source.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to the area through which current mainly flows.
  • the structural layer A is located on the side of the structural layer B facing away from the base substrate. It can be understood that the structural layer A is formed on the side of the structural layer B facing away from the base substrate.
  • part of the structure of structural layer A may also be located at the same physical height of structural layer B or lower than the physical height of structural layer B, where the base substrate is the height reference.
  • a display panel PNL includes a display area AA and a peripheral area BB surrounding the display area AA.
  • a display area AA there are sub-pixels and a pixel driving circuit PDC for driving the sub-pixels.
  • the sub-pixels may be light valves or self-luminous elements. Under the control of the pixel driving circuit PDC, each sub-pixel emits light independently, so that the display panel PNL displays a picture.
  • the display panel PNL may be a liquid crystal display panel, which includes an array substrate and a color filter substrate arranged in a box, and the liquid crystal box formed by the array substrate and the color filter substrate is filled with liquid crystal.
  • the sub-pixel can be a liquid crystal cell acting as a light valve; the liquid crystal cell includes two electrodes for controlling the electric field and a liquid crystal that flips or collapses under the control of the electric field.
  • One of the two electrodes can be used as a pixel electrode, and the other can be used as a common electrode; the common electrodes can be electrically connected to each other to jointly load a common voltage; the pixel driving circuit PDC can be electrically connected to each pixel electrode in a one-to-one correspondence to pass Controlling the voltage on the pixel electrode adjusts the electric field in the area corresponding to the pixel electrode, thereby controlling the degree of flipping or lodging of the liquid crystal in the area corresponding to the pixel electrode. In this way, the display panel PNL can control the light transmittance of each sub-pixel with the cooperation of the upper polarizer and the lower polarizer.
  • the display panel PNL may be a display panel with a self-luminous element.
  • the self-luminous element includes but is not limited to existing OLED, PLED, QLED, Q-OLED, Micro LED, Mini LED etc.
  • the display panel PNL may include a base substrate BP, a driving layer and a pixel layer that are stacked in sequence; wherein the light-emitting element is provided in the pixel layer as a sub-pixel, and the driving layer is provided with a pixel driving circuit PDC for driving the sub-pixel.
  • the pixel driving circuit PDC can control the size of the current flowing through the light-emitting element, thereby controlling the brightness of the light-emitting element.
  • the display panel PNL may also be provided with a scan line GL extending in the row direction DH and a drive data line extending in the column direction DV.
  • the pixel drive circuit PDC may be electrically connected to the scan line GL and the drive data line. Under the control of the scanning signal on the scanning line GL, the pixel driving circuit PDC can receive the driving data loaded on the driving data line, and then control the brightness of the sub-pixel according to the received driving data.
  • the pixel driving circuit PDC may include a data writing transistor, the control terminal of the data writing transistor is electrically connected to the scan line GL, and the input terminal of the data writing transistor is electrically connected to the driving data line.
  • the data writing transistor When a scan signal is loaded on the scan line GL, the data writing transistor is turned on, thereby causing the driving data loaded on the driving data line to be written into the capacitor of the pixel driving circuit PDC. When no scan signal is loaded on the scan line GL, the data writing transistor is electrically turned off, so that the driving data loaded on the driving data line cannot be written into the capacitor of the pixel driving circuit PDC.
  • a gate driving circuit GDC may be provided on one side of the display area AA for loading scanning signals to each scanning line GL.
  • the gate drive circuit GDC is disposed on one side of the display area AA along the row direction DH. It may include multiple shift register units GOA connected in sequence. Each scan line GL may be connected to one shift register unit GOA. The output terminal is electrically connected. In this way, when the shift register unit GOA outputs a scan signal, the scan signal can be loaded to the scan line GL.
  • each shift register unit GOA in the gate driving circuit GDC is the same and is arranged sequentially along the column direction DV. However, this arrangement will cause the gate drive circuit GDC to occupy a larger area, which will in turn cause the frame of the display panel PNL to increase, which is not conducive to narrowing the frame of the display panel PNL.
  • two different shift register units GOA are provided in the gate drive circuit GDC, namely a first shift register unit GOAA and a second shift register unit GOAB; the first shift register unit The number of transistors of GOAA is smaller than the number of transistors of the second shift register unit GOAB.
  • the first shift register unit GOAA and the second shift register unit GOAB are spaced apart from each other.
  • the pixel driving circuit PDC of the present disclosure includes a plurality of shift register units GOA connected in sequence.
  • the shift register unit GOA includes a first shift register unit GOAA and a second shift register unit GOAB.
  • the first shift register unit GOA The register unit GOAA and the second shift register unit GOAB are arranged spaced apart from each other.
  • the display area AA is provided with a plurality of pixel driving circuits PDC; at least part of the signal output by the first shift register unit GOAA and at least part of the second shift register unit GOAA.
  • the signal output by the bit register unit GOAB is used to drive the pixel driving circuit PDC.
  • both the first shift register unit GOAA and the second shift register unit GOAB have the ability to drive the pixel driving circuit PDC, which can reduce the number of shift register units GOA in the gate driving circuit GDC. This further reduces the area of the gate drive circuit GDC.
  • each shift register unit GOA in the pixel driving circuit PDC is arranged in one-to-one correspondence with the scan line GL, and each shift register unit GOA has a drive corresponding to the scan line GL.
  • the gate driving circuit is provided on one side of the display area AA in the row direction DH.
  • the peripheral area BB is provided with a first circuit area XA for laying out the first shift register unit GOAA and a second circuit area XB for laying out the second shift register unit GOAB; wherein, the second Part of the circuit area XB is located on the side of the first circuit area XA away from the display area AA.
  • some of the transistors in the second shift register unit GOAB can be arranged on the side of the first shift register unit GOAA away from the display area AA; on the one hand, this can reduce the size of the second shift register unit GOAB in the row direction.
  • this can avoid the second circuit area XB being spaced between the first circuit area XA and the display area AA, thereby preventing the output trace of the first shift register unit GOAA from penetrating the second circuit area XB to drive the scan line GL. , thereby avoiding parasitic capacitance caused by overlap, etc.
  • the gate drive circuit includes a plurality of shift register unit groups GOAS, each of the shift register unit groups GOAS includes an adjacent first shift register unit GOAA and a second Shift register unit GOAB; in the same shift register unit group GOAS, the first circuit area XA corresponding to the first shift register unit GOAA and the second circuit area XB corresponding to the second shift register unit GOAB complement each other to form a rectangle.
  • each of the shift register unit groups GOAS includes an adjacent first shift register unit GOAA and a second Shift register unit GOAB; in the same shift register unit group GOAS, the first circuit area XA corresponding to the first shift register unit GOAA and the second circuit area XB corresponding to the second shift register unit GOAB complement each other to form a rectangle.
  • the first circuit area XA for laying out the first shift register unit GOAA and the second circuit area XB for laying out the second shift register unit GOAB are not rectangular to each other, then the The first shift register unit GOAA and the second shift register unit GOAB may serve as a shift register unit group GOAS.
  • This arrangement can make the layout of the gate drive circuit GDC more compact, reduce area waste, and help reduce the frame of the display panel PNL.
  • the display panel PNL is provided with an inner wiring group WLAS and an outer wiring group WLBS corresponding to the gate driving circuit.
  • the inner wiring group The driving traces in the group WLAS and the outer wiring group WLBS are used to drive the gate driving circuit, and the inner wiring group WLAS is located in the outer wiring group WLBS close to the display area AA. side.
  • the shift register unit group GOAS is electrically connected to any drive wire of the external wire group WLBS through at most one adapter wire.
  • the first shift register unit GOAA and the second shift register unit GOAB in the shift register unit group GOAS do not need to be electrically connected to the drive wires in the external wire group WLBS independently through the adapter wires. This can Reduce the overlap between traces, thereby reducing impedance and crosstalk, and improving the stability of the gate drive circuit GDC.
  • the second shift register unit GOAB is electrically connected to each driving wire in the external wiring group WLBS through a patch cord.
  • the second shift register unit GOAB can be fully utilized by setting more transistors With more functions and better performance, the second shift register unit GOAB can be used as a buffer to a certain extent to improve the stability of the signal transmitted to the first shift register unit GOAA and reduce the risk of the first shift register unit GOAA.
  • the bit register unit GOAA faces the problem of insufficient performance due to fewer transistors.
  • the outer wiring group WLBS includes a first low-level signal line VGLLA extending along the column direction DV, a reset control line RSTL, a first scan control line CNL, and a second scan control line CNBL. .
  • the adjacent first shift register unit GOAA and the second shift register unit GOAB which are respectively located in two different shift register unit groups GOAS, are electrically connected to the same first low-level signal line VGLLA;
  • the reset control line RSTL is used to provide a reset control signal Rst to the shift register unit group GOAS;
  • the first scan control line CNL is used to provide a first scan control signal CN to the shift register unit group GOAS;
  • the second scan control line CNBL provides a second scan control signal CNB to the shift register unit group GOAS; the first scan control signal CN and the second scan control signal CNB are inverted signals.
  • the first shift register unit GOAA includes a first input transistor AT1 and a second input transistor AT2;
  • the second shift register unit GOAB includes a first input transistor BT1 and a second input transistor AT2.
  • the first input transistor BT1 is located between the first input transistor AT1 and the external wiring group WLBS, and is arranged along the row direction DH;
  • the second input transistor BT2 is located between the second input between the transistor AT2 and the external wiring group WLBS, and arranged along the row direction DH.
  • the source electrode AT1S of the first input transistor and the source electrode BT1S of the first input transistor are electrically connected to the first scan control line CNL through the same conductive structure.
  • the source electrode AT2S of the second input transistor and the source electrode BT2S of the second input transistor are electrically connected to the second scan control line CNBL through the same conductive structure.
  • the wiring of the shift register unit group GOAS can be simplified, and the compactness of the transistor layout in the shift register unit group GOAS can be improved.
  • the gate driving circuit GDC when the gate driving circuit GDC is working, it can control the second scan control signal CNB loaded on the second scan control line CNBL and the first scan control signal CN loaded on the first scan control line CNL so that the gate
  • the pole drive circuit GDC realizes different working modes such as forward scan and reverse scan.
  • the first shift register unit GOAA has a smaller number of transistors, it can still be cascaded with the first shift register unit GOAA and realize the forward scan mode and the reverse scan mode. This can make the function of the gate drive circuit GDC more complete.
  • the first shift register unit GOAA includes:
  • the first input transistor AT1 the source electrode AT1S of the first input transistor is used to load the first scan control signal CN, the drain electrode AT1D of the first input transistor is electrically connected to the pull-up node APU (also serving as the pull-up control node). Connection, the gate AT1G of the first input transistor is used to be electrically connected to the output end of the upper-level shift register unit GOA;
  • the second input transistor AT2 has its source AT2S used to load the second scan control signal CNB.
  • the drain AT2D of the second input transistor is electrically connected to the pull-up node APU.
  • the gate AT2G of the input transistor is electrically connected to the pull-down node APD, and is used to be electrically connected to the output end of the next-stage shift register unit GOA; the first scan control signal CN and the second scan control signal CNB are inverse Believe the signal;
  • the third capacitor C3 has a first electrode plate CP5 of the third capacitor and a second electrode plate CP6 of the third capacitor; the second electrode plate CP6 of the third capacitor is electrically connected to the pull-up node APU.
  • the first electrode plate CP5 of the three capacitors is electrically connected to the output end of the first shift register unit GOAA;
  • the source electrode AT4S of the second output transistor is used to load the low level signal VGL
  • the drain electrode AT4D of the second output transistor is electrically connected to the first electrode plate CP5 of the third capacitor
  • the gate AT4G of the second output transistor is electrically connected to the pull-down node APD;
  • Pull-down control transistor AT12 the source electrode AT12S of the pull-down control transistor is used to load the low-level signal VGL, the drain electrode AT12D of the pull-down control transistor is electrically connected to the pull-down node APD, and the gate of the pull-down control transistor The electrode AT12G is electrically connected to the gate electrode AT1G of the first input transistor.
  • the first input transistor AT1 and the second input transistor AT2 can be used as input modules for receiving the output of the upper-level shift register unit GOA and the output of the next-level shift register unit GOA. output, and realize the forward scan mode and the reverse scan mode through the first scan control signal CN and the second scan control signal CNB.
  • the pull-down control transistor AT12 can be electrically connected to the output of the upper-level shift register unit GOA, and thus can regulate the voltage of the pull-down node APD under the control of the voltage at the output end of the upper-level shift register unit GOA. , avoiding possible instability caused by floating drop-down node APD.
  • the first input transistor AT1 includes two sub-transistors connected in series, and the two sub-transistors have a common gate.
  • the second input transistor AT2 includes two sub-transistors connected in series, and the two sub-transistors have a common gate.
  • the voltage at the connection of the two sub-transistors can be 9V, which makes the source-drain voltage of one sub-transistor The difference is 7V, and the source-drain voltage difference of the other sub-transistor is 9V, thereby reducing the source-drain voltage difference and reducing the risk of back breakdown of the first input transistor AT1.
  • the size of each sub-transistor of the first input transistor AT1 and the second input transistor AT2 is the same.
  • the channel region width of each sub-transistor is 15.7 microns, and the channel region length of each sub-transistor is 5 microns.
  • the first output transistor AT3A may have a large width-to-length ratio to improve the driving capability of the first output transistor AT3.
  • the first output transistor AT3 can be divided into a plurality of parallel sub-transistors to facilitate the preparation and arrangement of the first output transistor AT3.
  • the first output transistor AT3 can be divided into four sub-transistors.
  • the four sub-transistors are divided into two groups.
  • the two groups of sub-transistors have a common source, and the drains of the two groups of sub-transistors are electrically connected to It is electrically connected to the first output line OUTLA.
  • the total length of the first output transistor AT3A is 108 microns, and the width of the first output transistor AT3A is 7 microns.
  • the second output transistor AT4A may also have a slightly larger width-to-length ratio, and the width-to-length ratio of the second output transistor AT4A is smaller than the width-to-length ratio of the first output transistor AT3A.
  • the total length of the second output transistor AT4A is 32 microns
  • the width of the second output transistor AT4A is 7 microns.
  • the second output transistor AT4 can be divided into multiple parallel sub-transistors to facilitate the preparation and arrangement of the second output transistor AT4.
  • the second output transistor AT4 may be divided into two sub-transistors.
  • two sub-transistors of the second output transistor AT4 and two sub-transistors of the first output transistor AT3 may be provided with a common drain and be electrically connected to the first output line OUTLA. In this way, the compactness of the first shift register unit GOAA wiring can be improved.
  • the first shift register unit GOAA further includes:
  • Touch control transistor AT11 the source electrode AT11S of the touch control transistor is used to load the low level signal VGL, and the drain electrode AT11D of the touch control transistor is electrically connected to the first electrode plate CP5 of the third capacitor. connection, the gate AT11G of the touch control transistor is used to load the touch control signal ENT.
  • the touch control signal ENT is loaded to the gate electrode AT11G of the touch control transistor, causing the gate electrode AT11G of the touch control transistor to be turned on, thereby causing the first output line OUTLA not to output a scanning signal.
  • the inner wiring group WLAS includes a touch control line ENTL for loading the touch control signal ENT, and the gate electrode AT11G of the touch control transistor is electrically connected to the touch control line ENTL.
  • the number starting with BT is used to represent the transistor in the second shift register unit GOAB or the source, gate, drain, and channel region of the transistor, so as to be consistent with the first shift register unit GOAA.
  • the transistors are distinguished by numbers.
  • the second shift register unit GOAB includes:
  • the first input transistor BT1 has its source BT1S used to load the first scan control signal CN, and its drain BT1D is used to be electrically connected to the pull-up control node BPUCN.
  • the gate BT1G of an input transistor is used to be electrically connected to the output terminal of the shift register unit GOA of the upper stage;
  • the first capacitor C1 includes a first electrode plate CP1 of the first capacitor and a second electrode plate CP2 of the first capacitor; the first electrode plate CP1 of the first capacitor and the output end of the second shift register unit GOAB Electrically connected, the second electrode plate CP2 of the first capacitor is electrically connected to the pull-up node BPU;
  • the second capacitor C2 includes a first electrode plate CP3 of the second capacitor and a second electrode plate CP4 of the second capacitor; the first electrode plate CP3 of the second capacitor is electrically connected to the pull-down node BPD, and the second electrode plate CP3 of the second capacitor is electrically connected to the pull-down node BPD.
  • the second electrode plate CP4 is used to load the low-level signal VGL;
  • the first output transistor BT3 has a drain BT3D electrically connected to the pull-up node BPU, and a drain BT3D of the first output transistor electrically connected to the first electrode plate CP1 of the first capacitor. ;
  • One of the source BT3S of the first output transistor of the second shift register unit GOAB and the source BT3S of the first output transistor of the adjacent shift register unit GOA is used to load the first clock signal CK And the other one is used to load the second clock signal CKB; the first clock signal CK and the second clock signal CKB are inverted signals;
  • the second output transistor BT4 has a source BT4S for loading the low-level signal VGL, and a drain BT4D of the second output transistor is electrically connected to the first electrode plate CP1 of the first capacitor. connected, the gate BT4G of the second output transistor is electrically connected to the pull-down node BPD;
  • the source BT5S of the first pull-down transistor is used to load the low-level signal VGL.
  • the drain BT5D of the first pull-down transistor is electrically connected to the pull-up control node BPUCN.
  • the gate BT5G of the first pull-down transistor is electrically connected to the pull-down node BPD;
  • the first pull-down control transistor BT6 has its source BT6S used to load the low-level signal VGL.
  • the drain BT6D of the first pull-down control transistor is electrically connected to the pull-down node BPD.
  • the gate BT6G of the first pull-down control transistor is electrically connected to the pull-up control node BPUCN;
  • the second pull-down control transistor BT7 has a drain BT7D electrically connected to the pull-down node BPD, a gate BT7G of the second pull-down control transistor and a source BT7S of the second pull-down control transistor. Electrical connection; one of the source BT7S of the second pull-down control transistor and the source BT3S of the first output transistor is used to load the first clock signal CK and the other is used to load the second clock signal CKB;
  • the second pull-down transistor BT8 has its source BT8S used to load the low-level signal VGL.
  • the drain BT8D of the second pull-down transistor is electrically connected to the pull-down node BPD.
  • the gate BT8G of the pull-down transistor is electrically connected to the first electrode plate CP1 of the first capacitor;
  • Reset transistor BT10 the source BT10S of the reset transistor is used to load the low level signal VGL, the drain BT10D of the reset transistor is electrically connected to the pull-up control node BPUCN, and the gate BT10G of the reset transistor Used to load the reset control signal Rst;
  • the pull-up control node BPUCN and the pull-up node BPU are electrically connected.
  • the first input transistor BT1 and the second input transistor BT2 can be used as input modules for receiving the output of the upper-level shift register unit GOA and the output of the next-level shift register unit GOA. output, and realize the forward scan mode and the reverse scan mode through the first scan control signal CN and the second scan control signal CNB.
  • the second pull-down control transistor BT7 is used to control the pull-down node BPD in response to the second clock signal CKB, so as to periodically control the first pull-down transistor BT5 to turn on through the voltage of the pull-down node BPD, thereby achieving
  • the pull-down control node BPUCN is periodically pulled down; and the second output transistor BT4 remains turned on by the high-level signal of the pull-down node BPD, so that the second shift register unit GOAB outputs a low-level signal.
  • the first pull-down control transistor BT6 can pull down the pull-down node BPD, thereby causing the first pull-down transistor BT5 and the second output transistor BT4 to turn off, so that the voltage of the pull-up control node BPUCN is maintained, thereby causing the voltage of the pull-up node BPU to be maintained at a high level, causing the first output transistor BT3 to be turned on and output the scanning signal.
  • the second pull-down transistor BT8 can be turned on to pull down the pull-down node BPD, thereby causing the pull-down node BPD to maintain a low level and the pull-up control node BPUCN to maintain a high level and pull up.
  • the node BPU maintains a high level
  • the first output transistor BT3 is turned on to output the scan signal until the first clock signal CK changes to a low level signal.
  • the second shift register unit GOAB also includes an enable transistor BT9 and a touch control transistor BT11; the pull-up control node BPUCN and the pull-up node BPU are configured through the enable transistor BT9 and the touch control transistor BT11. Energy transistor BT9 is electrically connected;
  • the source BT9S of the enable transistor is electrically connected to the pull-up control node BPUCN, the drain BT9D of the enable transistor is electrically connected to the pull-up node BPU, and the gate BT9G of the enable transistor Used to load the high-level signal VGH; the source BT11S of the touch control transistor is electrically connected to the low-level signal VGL, and the drain BT11D of the touch control transistor is connected to the first electrode of the first capacitor.
  • the board CP1 is electrically connected, and the gate BT11G of the touch control transistor is used to load the touch control signal ENT; the touch control signal ENT and the high-level signal VGH are inverted signals.
  • the high-level touch control signal ENT can be loaded to the gate electrode BT11G of the touch control transistor through the touch control line ENTL, thereby causing the touch control transistor BT11 to be turned on, which makes The output of the second shift register unit GOAB is a low level signal. corresponding.
  • the high-level signal VGH becomes a level signal, thereby turning off the enable transistor BT9, thereby preventing the first output transistor BT3 from being turned on.
  • the source and drain ends of the first input transistor BT1 and the second input transistor BT2 will maintain a large voltage difference for a long time, this is not conducive to the tolerance of the first input transistor BT1 and the second input transistor BT2; for this reason, this It is disclosed that by making the first input transistor BT1 and the second input transistor BT2 both be two series-connected sub-transistors, the voltage of the two sub-transistors can be divided, thereby reducing the voltage difference between the source and drain terminals of each sub-transistor, and improving the performance of the first input transistor.
  • the threshold shift tolerance of the first input transistor BT1 and the second input transistor BT2 can reach 6V.
  • the first input transistor BT1A of the second shift register unit GOAB has the same size as the first input transistor AT1A of the first shift register unit GOAA; the second input transistor of the second shift register unit GOAB The size of the transistor BT2A is the same as the size of the second input transistor AT2A of the first shift register unit GOAA.
  • the first output transistor BT3A may have a large width-to-length ratio to improve the driving capability of the first output transistor BT3.
  • the first output transistor BT3 can be divided into a plurality of parallel sub-transistors to facilitate the preparation and arrangement of the first output transistor BT3.
  • the first output transistor BT3 can be divided into four parallel sub-transistors, and the four sub-transistors are arranged in sequence along the row direction.
  • the size of the first output transistor BT3A of the second shift register unit GOAB is the same as the size of the first output transistor AT3A of the first shift register unit GOAA.
  • the second output transistor BT4A may also have a slightly larger width-to-length ratio, and the width-to-length ratio of the second output transistor BT4A is smaller than the width-to-length ratio of the first output transistor BT3A.
  • the second output transistor BT4 can be divided into multiple parallel sub-transistors to facilitate the preparation and arrangement of the second output transistor BT4. For example, referring to Figure 8, the second output transistor BT4 may be divided into two sub-transistors.
  • the size of the second output transistor BT4A of the second shift register unit GOAB is the same as the size of the second output transistor AT4A of the first shift register unit GOAA.
  • the number of transistors of the first shift register unit GOAA and the second shift register unit GOAB is different, they both have similar input modules (the first The first input transistor AT1 and the second input transistor AT2 in the shift register unit GOAA, the first input transistor BT1 and the second input transistor BT2 in the second shift register unit GOAB) and the output module (the first shift register unit The first output transistor AT3 and the second output transistor AT4 in GOAA, and the first output transistor BT3 and the second output transistor BT4 in the second shift register unit GOAB respectively also have capacitances electrically connected to the pull-up node.
  • the third capacitor C3 in the first shift register unit GOAA is electrically connected to the pull-up node APU, and the first capacitor C1 in the second shift register unit GOAB is electrically connected to the pull-up node BPU), and both are provided with pull-down nodes (eg pull-down node APD in the first shift register unit GOAA and pull-down node BPD in the second shift register unit GOAB). Therefore, both the first shift register unit GOAA and the second shift register unit GOAB can realize signal input through the input module, so that the cascaded shift register unit GOA can output the scanning signal step by step.
  • the first shift register unit GOAA and the second shift register unit GOAB can both respond to the voltage rise of the pull-up node and output a high-level scan signal; the first shift register unit GOAA and the second shift register unit GOAB Both can respond to the pull-down voltage pull-up and output low-level signals.
  • the second shift register unit GOAB is provided with other transistors that improve the performance and function of the second shift register unit GOAB (for example, the second pull-down control transistor BT7, the first pull-down transistor in the second shift register unit GOAB BT5, the first pull-down control transistor BT6, the second pull-down transistor BT8 and the reset transistor BT10), these transistors in the second shift register unit GOAB can stabilize the performance of the second shift register unit GOAB by
  • the first input transistor BT12 of the first shift register unit GOAA loads a signal so that the pull-down node APD of the first shift register unit GOAA remains stable and avoids the floating connection of the pull-down node APD, which enables the first shift register unit GOAA to rely on
  • the second shift register unit GOAB is stable and maintains stable performance.
  • the first shift register unit GOAA and the second shift register unit GOAB can be configured to have basically the same output module, so that the first shift register unit GOAA and the second shift register unit GOAB can
  • the register unit GOAB has similar or identical driving capabilities; by controlling the pull-down node APD of the first shift register unit GOAA by the output end of the second shift register unit GOAB, the first shift register unit GOAA and the second shift register unit GOAA can also be connected.
  • the shift register unit GOAB has essentially the same response speed.
  • the shift register unit GOA of one level is the first shift register unit GOAA
  • the shift register unit GOA of the other level is the second shift register unit GOAB.
  • the source and gate of the first output transistor of the upper-level shift register unit GOA are used to load the second clock signal CKB
  • the source of the first output transistor of the current-level shift register unit GOA is used to load the second clock signal CKB
  • the gate are used to load the first clock signal CK.
  • the second clock signal CKB is a high-level signal and the first clock signal CK is a low-level signal.
  • the upper-level shift register unit GOA outputs a high-level scan signal; This causes the PU first scan control signal CN of the shift register unit GOA of this level to start to pull up, which in turn causes PU to start to pull up, and the pull-down node is pulled down.
  • the shift register unit GOA of this level outputs a low level signal.
  • the second clock signal CKB becomes a low-level signal, and the voltage output by the upper-level shift register unit GOA becomes a low-level signal.
  • the sum of the voltages of each node of the current-level shift register unit GOA is The output voltage has no effect.
  • the first clock signal CK becomes a high-level signal; at this time, the shift register unit GOA of this level can output the high-level signal of the first clock signal CK, thereby causing the shift register unit of this level to GOA outputs a high-level scanning signal.
  • the voltages of the pull-up node and the pull-up control node are pulled up, further causing the shift register unit GOA to keep outputting a high-level scan signal.
  • the first clock signal CK changes to a low level signal, which in turn causes the voltage at the output end of the shift register unit GOA of this stage to drop. Through the coupling effect, the voltage of the pull-down node and the pull-down control node drops.
  • the output terminal of the shift register unit GOA is a low-level signal.
  • the next-level shift register unit GOA outputs a high-level signal, which in turn causes the second input transistor of the current-level shift register unit GOA to load a low-level signal to the pull-up node, thereby causing the current-level shift register
  • the pull-up node of unit GOA is a low-level signal.
  • the upper-level shift register unit GOA, the current-level shift register unit GOA, and the next-level shift register unit GOA sequentially output high-level scanning signals. This sequential output is the same as the shift register unit GOA. It does not matter whether the shift register unit GOAA or the second shift register unit GOAB.
  • the gate driving circuit GDC of the above examples of the present disclosure can reduce the number of transistors of the gate driving circuit GDC while ensuring the stable performance and complete functions of the gate driving circuit GDC, thereby helping to reduce the frame of the display panel PNL.
  • the above-mentioned exemplary gate driving circuit GDC especially the exemplary structures of the first shift register unit GOAA and the second shift register unit GOAB in FIG. 4 provided by the present disclosure are only for the purpose of this disclosure.
  • the gate driving circuit GDC may also use the first shift register unit GOAA of other structures and the second shift register unit GOAB of other structures.
  • the display panel PNL includes two gate driving circuits, and the two gate driving circuits are respectively located on both sides of the display area AA;
  • the pixel driving circuit PDC is driven simultaneously by the two gate driving circuits.
  • the display panel PNL of the present disclosure can be provided with gate driving circuits GDC on both sides of the display area AA, and each row of pixel driving circuits PDC is driven by two gate driving circuits GDC at the same time.
  • the driving capability of the pixel driving circuit PDC in each row can be improved, thereby increasing the charging rate of the pixel driving circuit PDC, and overcoming the possible insufficient charging capability of a single gate driving circuit GDC.
  • this can significantly improve the charging rate of the pixel driving circuit PDC; in some embodiments, the charging rate of the pixel driving circuit PDC can be increased by 2.37% or more.
  • gate driving circuits GDC are respectively provided on both sides of the display panel PNL
  • the width of each gate driving circuit GDC is smaller, which can be more effective
  • the reduced frame of the display panel PNL makes the gate driving circuit GDC particularly suitable for the display panel PNL of the dual gate driving circuit GDC.
  • the first shift register unit GOAA can not only obtain functional support from the adjacent second shift register unit GOAB in the same gate driving circuit GDC to maintain stability and maintain good performance, but also be connected to the third shift register unit GOAB on the same scan line GL.
  • the second shift register unit GOAB can also provide influence on its output end, avoiding the influence of the first shift register unit GOAA on the next-level second shift register unit GOAB due to possible fluctuations and slow response.
  • the two gate drive circuits GDC are connected through the scan lines GL, and each scan line GL is connected to the second shift register unit GOAB, which is equivalent to the second shift register unit GOAB to a certain extent.
  • the bit register units GOAB are cascaded across the display area AA in order to maintain the high performance of the gate drive circuit GDC; the first shift register unit GOAA serves as a compensation circuit to drive the scan line GL and is connected to the second shift register unit GL on the same scan line GL.
  • the shift register unit GOAB cooperates to improve the driving capability of the pixel driving circuit PDC on the scanning line GL.
  • the gate drive circuit GDC of the present disclosure will be further described with reference to a specific example.
  • the equivalent currents of the first shift register unit GOAA and the second shift register unit GOAB are as shown in FIG. 4 .
  • the display panel PNL includes a base substrate BP, a semiconductor layer SEMI, a gate layer GT and a semiconductor layer SD which are stacked in sequence.
  • a gate insulating layer is provided between the semiconductor layer SEMI and the gate layer GT.
  • An interlayer dielectric layer is provided between the gate layer GT and the semiconductor layer SD.
  • the semiconductor layer SEMI may include the channel area of each transistor of the shift register unit GOA, and include The source of the transistor and the drain of the transistor are located on either side of the channel region.
  • the semiconductor layer SEMI can also be provided with some capacitor electrode plates to increase the capacity of the capacitor or reduce the area of the capacitor.
  • the channel region of the transistor can maintain semiconductor characteristics, specifically N-type semiconductor characteristics, so that each transistor is an N-type transistor.
  • the source electrode of the transistor, the drain electrode of the transistor, and the electrode plate can be made into conductors.
  • the first circuit area XA and the second circuit area XB are both located close to the display area AA; the second circuit area XB has a protruding area located far away from the first circuit area XA and the display area AA side. In this way, the width of the second circuit region XB can be reduced, thereby reducing the width of the gate driving circuit GDC.
  • the first input transistor BT1 and the second input transistor BT2 of the second shift register unit GOAB are provided in the protruding area of the second circuit area XB; on the side of the first circuit area XA away from the display area AA, There are a first input transistor AT1 and a second input transistor AT2 of the shift register unit GOA.
  • the electrode plates provided in the semiconductor layer SEMI include a fourth bottom electrode plate CP4A, a first bottom electrode plate CP1A and a fifth top electrode plate CP5A.
  • the fourth bottom electrode plate CP4A has a first bottom via hole region H1A for connecting with the fourth top electrode plate CP4B through a via hole.
  • the first bottom electrode plate CP1A has a first electrode plate CP1LA of the first capacitor for connecting to the first top electrode plate CP1B through a via hole;
  • the fifth top electrode plate CP5A has a via hole for connecting to the fifth bottom electrode plate CP5B Connect the first protrusion CP5LA of the fifth electrode plate.
  • Some of the transistors may have a common drain.
  • a part of the drain BT3D of the first output transistor may be multiplexed as the drain BT4D of the second output transistor
  • a part of the drain AT3D of the first output transistor may be multiplexed as the second output transistor.
  • the drain AT4D of the output transistor, the drain BT1D of the first input transistor and the drain BT2D of the second input transistor are multiplexed with each other, and the drain AT1D of the first input transistor and the drain AT2D of the second input transistor are multiplexed with each other.
  • the gate layer GT is provided with the gates of each transistor, as well as electrode plates provided with capacitors and some transfer wiring.
  • the semiconductor layer SD is provided with driving traces, electrode plates and some transfer traces.
  • the driving wiring includes the first low-level signal line VGLLA, the reset control line RSTL, the high-level wiring VGHL located on the side of the first circuit area XA and the second circuit area XB away from the display area AA, The first scan control line CNL and the second scan control line CNBL.
  • the first low-level signal line VGLLA is used to load the low-level signal VGL
  • the reset control line RSTL is used to load the reset control signal Rst
  • the high-level wiring VGHL is used to load the high-level signal VGH
  • the first scan control The line CNL is used to load the first scan control signal CN
  • the second scan control line CNBL is used to load the second scan control signal CNB.
  • the driving traces also include a first clock trace CKL, a second clock trace CKBL, a second low-level transfer line VGLLB and a touch control line located at one end of the first circuit area XA and the second circuit area XB close to the display area AA.
  • ENTL where the first clock line CKL is used to load the first clock signal CK, the second clock line CKBL is used to load the second clock signal CKB, and the second low-level transfer line VGLLB is used to load the low-level signal VGL , the touch control line ENTL is used to load the touch control signal ENT.
  • the semiconductor layer SD is also provided with a fifth top transfer line TRB5;
  • the gate layer GT is provided with a first low-level transfer line VGLTA;
  • the first low-level transfer line VGLTA is located away from the end of the display area AA It is connected to the first low-level signal line VGLLA through a via hole, and the end of the first low-level switching line VGLTA close to the display area AA has a third bottom via hole area H3A.
  • One end of the fourth top electrode plate CP4B close to the fifth bottom transfer line TRA5 is connected to a twelfth top transfer line TRB12.
  • One end of the fourth top electrode plate CP4B close to the display area AA has a first top via hole area H1B.
  • the fourth top electrode The side of board CP4B close to the first output transistor BT3 is connected to an eleventh top transfer line TRB11; among them, the twelfth top transfer line TRB12 is electrically connected to the source electrode BT6S of the first pull-down control transistor through a via hole.
  • the top transfer wire TRB11 is electrically connected to the source electrode BT8S of the second pull-down transistor and the source electrode BT4S of the second output transistor through the via hole.
  • the low-level signal VGL can be loaded to the source electrode BT10S of the reset transistor, the source electrode BT5S of the first pull-down transistor, the source electrode BT6S of the first pull-down control transistor, and the source electrode BT6S of the second pull-down control transistor.
  • the source BT8S of the pull-down transistor and the source BT4S of the second output transistor are loaded to the first electrode plate CP3 of the second capacitor.
  • the semiconductor layer SD is provided with a nineteenth top transfer line TRB19, and the nineteenth top transfer line TRB19 is electrically connected to the fourth top electrode plate CP4B in the adjacent second circuit area XB, And the nineteenth transfer line TRB19 is electrically connected to the source electrode AT12S of the pull-down control transistor and the source electrode AT4S of the second output transistor through the via hole.
  • the low-level signal VGL can also be loaded to the source electrode AT4S of the second output transistor and the source electrode AT12S of the pull-down control transistor.
  • the semiconductor layer SD is provided with a reset control line RSTL
  • the gate layer GT is provided with a reset transfer line RSTT.
  • one end of the reset transfer line RSTT away from the display area AA is electrically connected to the reset control line RSTL through a via hole.
  • One end of the reset transfer line RSTT close to the display area AA serves as the gate electrode BT10G of the reset transistor and overlaps with the reset transistor BT10A.
  • the semiconductor layer SD is provided with a high-level wiring VGHL
  • the gate layer GT is provided with a high-level transfer line VGHT.
  • one end of the high-level transfer line VGHT away from the display area AA is electrically connected to the high-level trace VGHL through a via hole
  • one end of the high-level transfer line VGHT close to the display area AA serves as the gate electrode BT9G of the enabling transistor and is connected to the enable transistor BT9G.
  • the transistors BT9A are overlapped.
  • the semiconductor layer SD is provided with a first scan control line CNL and a first top transfer line TRB1
  • the gate layer GT is provided with a first scan control transfer line CNT.
  • one end of the first scan control transfer line CNT away from the display area AA is electrically connected to the first scan control line CNL through a via hole, and one end of the first scan control transfer line CNT close to the display area AA is away from the first top transfer line TRB1.
  • the semiconductor layer SD is provided with a second scan control transfer line CNBT that is electrically connected to the second scan control line CNBL.
  • the second scan control transfer line CNBT extends along the row direction DH toward the display area AA side, and It is electrically connected to the source electrode BT2S of the second input transistor and the source electrode AT2S of the second input transistor through via holes respectively.
  • the semiconductor layer SD is also provided with a seventh top transfer line TRB7, a ninth top transfer line TRB9, and a fifteenth top transfer line TRB15; wherein, the gate layer GT is provided with a first clock transfer line CKBTA, Second clock adapter cable CKBTB.
  • One end of the first clock transfer line CKBTA close to the display area AA is electrically connected to the second clock line CKBL through a via hole, and one end of the first clock transfer line CKBTA away from the display area AA is connected to the fifteenth top transfer line TRB15 close to the display through a via hole.
  • the end of area AA is connected; the fifteenth top transfer line TRB15 is electrically connected to the source electrode AT3S of the first output transistor through a via hole.
  • One end of the second clock transfer line CKBTB close to the display area AA is electrically connected to the second clock line CKBL through a via hole.
  • One end of the second clock transfer line CKBTB away from the display area AA serves as the gate electrode BT7G of the second pull-down control transistor and is connected to the second clock line CKBL.
  • Two pull-down control transistors BT7A overlap.
  • the second clock transfer line CKBTB has a twelfth bottom via area H12A; the ninth top transfer line TRB9 has a twelfth top via area H12B, and the twelfth bottom via area H12A and the twelfth top via area H12B are mutually exclusive. overlapping and electrically connected through vias.
  • one end of the ninth top transfer line TRB9 is electrically connected to the second clock transfer line CKBTB through a via hole, and the other end is electrically connected to the source electrode BT7S of the second pull-down control transistor through a via hole.
  • the seventh transfer line TRB7 is electrically connected to the first clock line CKL, extends in a direction away from the display area AA, and is electrically connected to the source BT3S of the first output transistor through a via hole.
  • the source BT7S of the second pull-down control transistor of the second shift register unit GOAB in this example can be loaded with the second clock signal CKB
  • the source of the first output transistor of the first shift register unit GOAA in this example AT3S can be loaded with the second clock signal CKB
  • the source BT3S of the first output transistor of the second shift register unit GOAB in this example can be loaded with the first clock signal CK.
  • the semiconductor layer SD is provided with a third top transfer line TRB3.
  • One end of the third top transfer line TRB3 is electrically connected to the drain BT1D of the first input transistor through a via hole, and the other end has a ninth top via hole area. H9B.
  • the third top transfer wire TRB3 is provided with a side branch electrically connected to the source electrode BT9S of the enable transistor through a via hole, and can be electrically connected to the drain electrode BT10D of the reset transistor and the drain electrode BT5D of the first pull-down transistor through a via hole. connect.
  • the gate electrode BT6G of the first pull-down control transistor has a protruding portion.
  • the protruding portion has a ninth bottom via hole region H9A.
  • the ninth bottom via hole region H9A and the ninth top via hole region H9B pass through the via holes. Electrical connection.
  • the drain BT1D of the first input transistor as part of the pull-up control node BPUCN, can be connected with the source BT9S of the enable transistor, the drain BT10D of the reset transistor, the drain BT5D of the first pull-down transistor, and the first pull-down transistor BPUCN.
  • the gate of the control transistor BT6G is electrically connected.
  • the semiconductor layer SD is provided with the sixth top transfer line TRB6, the first top electrode plate CP1B, and the fourth top transfer line TRB4;
  • the gate layer GT is provided with the second electrode plate CP2 of the first capacitor, the first top electrode plate CP1B, and the fourth top transfer line TRB4.
  • One end of the fourth top transfer wire TRB4 is electrically connected to the drain BT9D of the enable transistor through a via hole, and the other end has a seventh top via hole area H7B; the seventh top via hole area H7B and the seventh bottom via hole area H7A pass through the via hole Electrical connection.
  • the sixth top transfer line TRB6 is electrically connected to the first top electrode plate CP1B, and is electrically connected to the drain BT3D of the first output transistor.
  • the end of the sixth top transfer line TRB6 close to the display area AA is provided with a thirteenth top via hole area H13B, and the end of the second output line OUTLB away from the display area AA is provided with a thirteenth bottom via hole area H13A;
  • the via hole area H11A and the eleventh top via hole area H11B overlap each other and are electrically connected through via holes.
  • the sixth top transfer wire TRB6 has an enlarged portion, and a tenth top via hole area H10B is provided on the enlarged portion;
  • the gate electrode BT8G of the second pull-down transistor has a protruding portion, and the tenth bottom via hole area H10A is provided on the protruding portion;
  • the bottom via hole area H10A and the tenth top via hole area H10B overlap each other and are electrically connected through via holes.
  • the first bottom electrode plate CP1A has a first protruding portion CL1LA of the first electrode plate
  • the first top electrode plate CP1B has a third protruding portion CP1LC of the first electrode plate; the third protruding portion CP1LC of the first electrode plate and The first protrusions CL1LA of the first electrode plate overlap each other and are electrically connected through via holes.
  • the first top electrode plate CP1B has a second protruding portion CP1LB of the first electrode plate, and the second protruding portion CP1LB of the first electrode plate is provided with a sixth top via hole region H6B; the gate layer GT is provided with a connection with the first input transistor.
  • the fourth bottom transfer line TRA4 is connected to the gate AT1G.
  • the end of the fourth bottom transfer line TRA4 has a sixth bottom via area H6A; the sixth bottom via area H6A and the sixth top via area H6B overlap and pass through each other. Via-hole electrical connections.
  • the first top electrode plate CP1B has a fourth protruding portion CP1LD of the first electrode plate, and the second protruding portion CP1LB of the first electrode plate is provided with an eighth top via hole region H8B;
  • the gate layer GT is provided with a third bottom transfer line TRA3, one end of the third bottom transfer line TRA3 is connected to the gate AT2G of the second input transistor of the upper-level first shift register unit GOAA, and the other end has an eighth bottom via area H8A; the eighth bottom via area H8A and the The eight via holes H8B overlap each other and are electrically connected through via holes.
  • the gate layer GT is provided with the first electrode plate CP3 of the second capacitor, one end is connected to the gate BT5G of the first pull-down transistor, and the other end is connected to the gate BT4G of the second output transistor, and
  • the first electrode plate CP3 of the second capacitor has a second bottom via area H2A; the gate electrode BT4G of the second output transistor has an enlarged portion at one end away from the first electrode plate CP3 of the second capacitor, and an eleventh inflated portion is provided on the enlarged portion.
  • the semiconductor layer SD is provided with an eighth transfer line TRB8 and a tenth transfer line TRB10.
  • one end of the eighth top transfer wire TRB8 has a second top via hole area H2B, and the second bottom via hole area H2A and the second top via hole area H2B overlap with each other and are electrically connected through via holes.
  • the eighth top transfer line TRB8 is electrically connected to the drain BT8D of the second pull-down transistor and the drain BT6D of the first pull-down control transistor through a via hole.
  • the tenth top transfer line TRB10 is electrically connected to the drain BT7D of the second pull-down control transistor through a via hole, and the tenth top transfer line TRB10 has an eleventh top via hole area H11B, an eleventh bottom via hole area H11A and a tenth top via hole area H11B.
  • a top via hole area H11B overlaps with each other and is electrically connected through the via holes.
  • the fourth top electrode plate CP4B has a first top via hole region H1B, and the first bottom via hole region H1A and the first top via hole region H1B overlap each other and are electrically connected through via holes.
  • the semiconductor layer SD is provided with a fifth bottom electrode plate CP5B, a sixteenth top transfer line TRB16, and a seventeenth top transfer line TRB17; the fifth bottom electrode plate CP5B has a second protrusion of the fifth electrode plate.
  • Part CP5LB, the fifth top electrode plate CP5A provided on the semiconductor layer SEMI has a first protruding portion CP5LA of the fifth electrode plate; the first protruding portion CP5LA of the fifth electrode plate and the second protruding portion CP5LB of the fifth electrode plate intersect with each other. stacked and electrically connected through vias.
  • the sixteenth top transfer line TRB16 is electrically connected to the fifth bottom electrode plate CP5B, and is electrically connected to a part of the drain AT3D of the first output transistor; the seventeenth top transfer line TRB17 is electrically connected to the fifth bottom electrode plate CP5B, and It is electrically connected to the remaining part of the drain electrode AT3D of the first output transistor; the seventeenth top transfer line TRB17 is also electrically connected to the drain electrode AT4D of the second output transistor.
  • the gate layer GT is provided with a first output line OUTLA.
  • the end of the seventeenth top transfer line TRB17 close to the display area AA is electrically connected to the end of the first output line OUTLA away from the display area AA through a via hole.
  • the semiconductor layer SD is provided with a fourteenth top transfer line TRB14 and an eighteenth top transfer line TRB18, and the gate layer GT is provided with a sixth bottom transfer line TRA6 and the second electrode plate CP6 of the third capacitor.
  • the end of the fourteenth top transfer line TRB14 close to the display area AA is provided with a sixteenth top via hole area H16B
  • the second electrode plate CP6 of the third capacitor is provided with a fifteenth bottom via hole area H16A;
  • the via hole area H16A and the sixteenth top via hole area H16B overlap each other and are electrically connected through via holes.
  • the end of the fourteenth transfer wire TRB14 away from the display area AA is electrically connected to the drain electrode AT1D of the first input transistor through a via hole.
  • the gate electrode AT2G of the second input transistor has a protruding portion, and the protruding portion is provided with the fourteenth bottom via hole region H14A;
  • the gate electrode AT4G of the second output transistor has a protruding portion, and the protruding portion is provided with the fifteenth bottom via hole region H14A.
  • H15A; both ends of the eighteenth top transfer line TRB18 have a fourteenth top via area H14B and a fifteenth top via area H15B respectively, and the fourteenth bottom via area H14A and the fourteenth top via area H14B are mutually exclusive.
  • the fifteenth bottom via hole region H15A and the fifteenth top via hole region H15B overlap with each other and are electrically connected through via holes.
  • One end of the sixth bottom transfer line TRA6 is electrically connected to the gate AT1G of the first input transistor, and the other end is electrically connected to the gate AT12G of the pull-down control transistor.
  • the semiconductor layer SD is provided with a second top transfer line TRB2, and the gate layer GT is provided with a first bottom transfer line TRA1; the first bottom transfer line TRA1 is electrically connected to the gate BT1G of the first input transistor, And a fourth bottom via area H4A is provided at the end; the second top transfer line TRB2 is arranged across the shift register unit group GOAS, and one end thereof has a fourth top via area H4B, a fourth bottom via area H4A and a fourth top via area.
  • the hole areas H4B overlap each other and are electrically connected through via holes.
  • the other end of the second top transfer line TRB2 is electrically connected to the fifth bottom electrode plate CP5B of the upper-stage first shift register unit GOAA.
  • the gate layer GT is provided with a second bottom transfer line TRA2.
  • One end of the second bottom transfer line TRA2 is electrically connected to the gate BT2G of the second input transistor, and the other end has a fifth bottom via region H5A;
  • the second top transfer wire TRB2 has a fifth top via hole area H5B.
  • the fifth bottom via hole area H5A and the fifth top via hole area H5B overlap each other and are electrically connected through via holes.
  • the semiconductor layer SD is also provided with a thirteenth transfer line TRB13 and a twentieth transfer line TRB20;
  • the gate layer GT is also provided with a first touch transfer line TSA and a second touch transfer line TSB.
  • the first touch transfer line TSA is electrically connected to the touch control line ENTL through the via hole, and is electrically connected to the gate BT11G of the touch control transistor;
  • the second touch transfer line TSB is electrically connected to the touch control line ENTL through the via hole. , and is electrically connected to the gate AT11G of the touch control transistor.
  • the thirteenth top transfer line TRB13 is electrically connected to the second output line OUTLB through a via hole, and is electrically connected to the drain electrode BT11D of the touch control transistor.
  • the source electrode BT11S of the touch control transistor is connected to the second low level switch through the via hole.
  • the twentieth transfer line TRB20 is electrically connected to the first output line OUTLA through a via hole, and is electrically connected to the drain electrode AT11D of the touch control transistor.
  • the source electrode AT11S of the touch control transistor is connected to the second low level switch through the via hole. Wire the VGLLB electrical connection.

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Abstract

一种栅极驱动电路（GDC）和显示面板（PNL）。显示面板（PNL），包括显示区（AA）和围绕显示区（AA）的外围区（BB）；外围区（BB）中设置有栅极驱动电路（GDC）；栅极驱动电路（GDC）包括依次级联的多个移位寄存器单元（GOA）。其中，移位寄存器单元（GOA）包括第一移位寄存器单元（GOAA）和第二移位寄存器单元（GOAB），第一移位寄存器单元（GOAA）和第二移位寄存器单元（GOAB）相互间隔；第一移位寄存器单元（GOAA）的晶体管数量小于第二移位寄存器单元（GOAB）的晶体管数量。

Description

栅极驱动电路和显示面板 技术领域
本公开涉及显示技术领域，具体而言，涉及一种栅极驱动电路和显示面板。
背景技术
随着显示技术的发展，窄边框产品的应用范围越来越广泛。显示面板的边缘一般需要设置栅极驱动电路，栅极驱动电路的尺寸过大会制约显示面板的窄边框化。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种栅极驱动电路和显示面板，减小显示面板的边框。
根据本公开的一个方面，提供一种显示面板，包括显示区和围绕所述显示区的外围区；所述外围区中设置有栅极驱动电路；所述栅极驱动电路包括依次级联的多个移位寄存器单元；
其中，所述移位寄存器单元包括第一移位寄存器单元和第二移位寄存器单元，所述第一移位寄存器单元和所述第二移位寄存器单元相互间隔；所述第一移位寄存器单元的晶体管数量小于所述第二移位寄存器单元的晶体管数量。
根据本公开的一种实施方式，所述显示区设置有多个像素驱动电路；至少部分所述第一移位寄存器单元输出的信号和至少部分所述第二移位寄存器单元输出的信号用于驱动所述像素驱动电路。
根据本公开的一种实施方式，所述栅极驱动电路设于所述显示区在行方向的一侧；
所述外围区设置有用于布设所述第一移位寄存器单元的第一电路区 域和用于布设所述第二移位寄存器单元的第二电路区域；
其中，所述第二电路区域的部分区域位于所述第一电路区域远离所述显示区的一侧。
根据本公开的一种实施方式，所述栅极驱动电路包括多个移位寄存器单元组，每个所述移位寄存器单元组包括相邻的一个第一移位寄存器单元和一个第二移位寄存器单元；同一所述移位寄存器单元组中，第一移位寄存器单元对应的第一电路区域和第二移位寄存器单元对应的第二电路区域互补成矩形。
根据本公开的一种实施方式，所述显示面板设置有与所述栅极驱动电路对应的内走线组和外走线组，所述内走线组和所述外走线组中的驱动走线均用于驱动所述栅极驱动电路，且所述内走线组位于所述外走线组靠近所述显示区的一侧；
所述移位寄存器单元组与所述外走线组的任意一个驱动走线之间通过最多一个转接线电连接。
根据本公开的一种实施方式，所述外走线组包括沿列方向延伸的第一低电平信号线、复位控制线、第一扫描控制线和第二扫描控制线；
分别位于两个不同的移位寄存器单元组中且相邻的第一移位寄存器单元和第二移位寄存器单元，与同一所述第一低电平信号线电连接；
所述复位控制线用于向所述移位寄存器单元组提供复位控制信号；
所述第一扫描控制线用于向所述移位寄存器单元组提供第一扫描控制信号；所述第二扫描控制线拥有向所述移位寄存器单元组提供第二扫描控制信号；所述第一扫描控制信号和所述第二扫描控制信号为反相信号。
根据本公开的一种实施方式，所述第一移位寄存器单元包括第一输入晶体管和第二输入晶体管；所述第二移位寄存器单元包括第一输入晶体管和第二输入晶体管；所述第一输入晶体管位于所述第一输入晶体管与所述外走线组之间，且沿行方向排列；所述第二输入晶体管位于所述第二输入晶体管与所述外走线组之间，且沿行方向排列；
所述第一输入晶体管的源极和所述第一输入晶体管的源极通过同一导电结构电连接至所述第一扫描控制线；
所述第二输入晶体管的源极和所述第二输入晶体管的源极通过同一导电结构电连接至所述第二扫描控制线。
根据本公开的一种实施方式，所述第一移位寄存器单元包括：
第一输入晶体管，所述第一输入晶体管的源极用于加载第一扫描控制信号，所述第一输入晶体管的漏极与上拉节点电连接，所述第一输入晶体管的栅极用于与上一级移位寄存器单元的输出端电连接；
第二输入晶体管，所述第二输入晶体管的源极用于加载第二扫描控制信号，所述第二输入晶体管的漏极与所述上拉节点电连接，所述第二输入晶体管的栅极与下拉节点电连接，且用于与下一级移位寄存器单元的输出端电连接；所述第一扫描控制信号和所述第二扫描控制信号为反相信号；
第三电容，具有第三电容的第一电极板和第三电容的第二电极板；所述第三电容的第二电极板与所述上拉节点电连接，所述第三电容的第一电极板与所述第一移位寄存器单元的输出端电连接；
第一输出晶体管，所述第一输出晶体管的漏极与第三电容的第一电极板电连接，所述第一输出晶体管的栅极与所述上拉节点电连接；所述第一移位寄存器单元的第一输出晶体管的源极和相邻的所述移位寄存器单元的第一输出晶体管的源极中，一个用于加载第一时钟信号且另一个用于加载第二时钟信号；所述第一时钟信号和所述第二时钟信号为反相信号；
第二输出晶体管，所述第二输出晶体管的源极用于加载低电平信号，所述第二输出晶体管的漏极与所述第三电容的第一电极板电连接，所述第二输出晶体管的栅极与所述下拉节点电连接；
下拉控制晶体管，所述下拉控制晶体管的源极用于加载所述低电平信号，所述下拉控制晶体管的漏极与所述下拉节点电连接，所述下拉控制晶体管的栅极与所述第一输入晶体管的栅极电连接。
根据本公开的一种实施方式，所述第一输入晶体管包括串联的两个亚晶体管，两个亚晶体管共栅极；
所述第二输入晶体管包括串联的两个亚晶体管，两个亚晶体管共栅极。
根据本公开的一种实施方式，所述第一移位寄存器单元还包括：
触控控制晶体管，所述触控控制晶体管的源极用于加载所述低电平信号，所述触控控制晶体管的漏极与所述第三电容的第一电极板电连接，所述触控控制晶体管的栅极用于加载触控控制信号。
根据本公开的一种实施方式，所述第二移位寄存器单元包括：
第一输入晶体管，所述第一输入晶体管的源极用于加载第一扫描控制信号，所述第一输入晶体管的漏极用于与上拉控制节点电连接，所述第一输入晶体管的栅极用于与上一级所述移位寄存器单元的输出端电连接；
第二输入晶体管，所述第二输入晶体管的源极用于加载第二扫描控制信号，所述第二输入晶体管的漏极用于与所述上拉控制节点电连接，所述第二输入晶体管的栅极用于与下一级所述移位寄存器单元的输出端电连接；所述第一扫描控制信号和所述第二扫描控制信号为反相信号；
第一电容，包括第一电容的第一电极板和第一电容的第二电极板；所述第一电容的第一电极板与所述第二移位寄存器单元的输出端电连接，所述第一电容的第二电极板与上拉节点电连接；
第二电容，包括第二电容的第一电极板和第二电容的第二电极板；所述第二电容的第一电极板与下拉节点电连接，所述第二电容的第二电极板用于加载低电平信号；
第一输出晶体管，所述第一输出晶体管的漏极与所述上拉节点电连接，所述第一输出晶体管的漏极与所述第一电容的第一电极板电连接；所述第二移位寄存器单元的第一输出晶体管的源极和相邻的所述移位寄存器单元的第一输出晶体管的源极中，一个用于加载第一时钟信号且另一个用于加载第二时钟信号；所述第一时钟信号和所述第二时钟信号为反相信号；
第二输出晶体管，所述第二输出晶体管的源极用于加载所述低电平信号，所述第二输出晶体管的漏极与所述第一电容的第一电极板电连接，所述第二输出晶体管的栅极与所述下拉节点电连接；
第一下拉晶体管，所述第一下拉晶体管的源极用于加载所述低电平信号，所述第一下拉晶体管的漏极与所述上拉控制节点电连接，所述第 一下拉晶体管的栅极与所述下拉节点电连接；
第一下拉控制晶体管，所述第一下拉控制晶体管的源极用于加载所述低电平信号，所述第一下拉控制晶体管的漏极与所述下拉节点电连接，所述第一下拉控制晶体管的栅极与所述上拉控制节点电连接；
第二下拉控制晶体管，所述第二下拉控制晶体管的漏极与所述下拉节点电连接，所述第二下拉控制晶体管的栅极与所述第二下拉控制晶体管的源极电连接；所述第二下拉控制晶体管的源极和所述第一输出晶体管的源极中的一个用于加载所述第一时钟信号且另一个用于加载所述第二时钟信号；
第二下拉晶体管，所述第二下拉晶体管的源极用于加载所述低电平信号，所述第二下拉晶体管的漏极与所述下拉节点电连接，所述第二下拉晶体管的栅极与所述第一电容的第一电极板电连接；
复位晶体管，所述复位晶体管的源极用于加载所述低电平信号，所述复位晶体管的漏极与所述上拉控制节点电连接，所述复位晶体管的栅极用于加载复位控制信号；
所述上拉控制节点和所述上拉节点电连接。
根据本公开的一种实施方式，所述第一输入晶体管包括串联的两个亚晶体管，两个亚晶体管共栅极；
所述第二输入晶体管包括串联的两个亚晶体管，两个亚晶体管共栅极。
根据本公开的一种实施方式，所述第二移位寄存器单元还包括使能晶体管和触控控制晶体管；所述上拉控制节点和所述上拉节点通过所述使能晶体管电连接；
其中，所述使能晶体管的源极与所述上拉控制节点电连接，所述使能晶体管的漏极与所述上拉节点电连接，所述使能晶体管的栅极用于加载高电平信号；所述触控控制晶体管的源极与所述低电平信号电连接，所述触控控制晶体管的漏极与所述第一电容的第一电极板电连接，所述触控控制晶体管的栅极用于加载触控控制信号；所述触控控制信号与所述高电平信号为反相信号。
根据本公开的一种实施方式，所述显示面板包括两个所述栅极驱动 电路，两个所述栅极驱动电路分别位于所述显示区的两侧；
任意一行所述像素驱动电路被两个所述栅极驱动电路同时驱动。
根据本公开的一种实施方式，任意一行所述像素驱动电路，被一个所述栅极驱动电路的第一移位寄存器单元驱动，且被另一个所述栅极驱动电路的第二移位寄存器单元驱动。
根据本公开的第二个方面，提供一种栅极驱动电路，包括依次级联的多个移位寄存器单元；其中，所述移位寄存器单元包括第一移位寄存器单元和第二移位寄存器单元，所述第一移位寄存器单元和所述第二移位寄存器单元相互间隔；所述第一移位寄存器单元的晶体管数量小于所述第二移位寄存器单元的晶体管数量。
根据本公开的一种实施方式，每个所述移位寄存器单元用于驱动一行像素驱动电路。
根据本公开的一种实施方式，所述第一移位寄存器单元包括：
第一输入晶体管，所述第一输入晶体管的源极用于加载第一扫描控制信号，所述第一输入晶体管的漏极与上拉节点电连接，所述第一输入晶体管的栅极用于与上一级移位寄存器单元的输出端电连接；
第二输入晶体管，所述第二输入晶体管的源极用于加载第二扫描控制信号，所述第二输入晶体管的漏极与所述上拉节点电连接，所述第二输入晶体管的栅极与下拉节点电连接，且用于与下一级移位寄存器单元的输出端电连接；所述第一扫描控制信号和所述第二扫描控制信号为反相信号；
第三电容，具有第三电容的第一电极板和第三电容的第二电极板；所述第三电容的第二电极板与所述上拉节点电连接，所述第三电容的第一电极板与所述第一移位寄存器单元的输出端电连接；
第一输出晶体管，所述第一输出晶体管的漏极与第三电容的第一电极板电连接，所述第一输出晶体管的栅极与所述上拉节点电连接；所述第一移位寄存器单元的第一输出晶体管的源极和相邻的所述移位寄存器单元的第一输出晶体管的源极中，一个用于加载第一时钟信号且另一个用于加载第二时钟信号；所述第一时钟信号和所述第二时钟信号为反相信号；
第二输出晶体管，所述第二输出晶体管的源极用于加载低电平信号，所述第二输出晶体管的漏极与所述第三电容的第一电极板电连接，所述第二输出晶体管的栅极与所述下拉节点电连接；
下拉控制晶体管，所述下拉控制晶体管的源极用于加载所述低电平信号，所述下拉控制晶体管的漏极与所述下拉节点电连接，所述下拉控制晶体管的栅极与所述第一输入晶体管的栅极电连接。
根据本公开的一种实施方式，所述第一输入晶体管包括串联的两个亚晶体管，两个亚晶体管共栅极；
所述第二输入晶体管包括串联的两个亚晶体管，两个亚晶体管共栅极。
根据本公开的一种实施方式，所述第二移位寄存器单元包括：
第一输入晶体管，所述第一输入晶体管的源极用于加载第一扫描控制信号，所述第一输入晶体管的漏极用于与上拉控制节点电连接，所述第一输入晶体管的栅极用于与上一级所述移位寄存器单元的输出端电连接；
第二输入晶体管，所述第二输入晶体管的源极用于加载第二扫描控制信号，所述第二输入晶体管的漏极用于与所述上拉控制节点电连接，所述第二输入晶体管的栅极用于与下一级所述移位寄存器单元的输出端电连接；所述第一扫描控制信号和所述第二扫描控制信号为反相信号；
第一电容，包括第一电容的第一电极板和第一电容的第二电极板；所述第一电容的第一电极板与所述第二移位寄存器单元的输出端电连接，所述第一电容的第二电极板与上拉节点电连接；
第二电容，包括第二电容的第一电极板和第二电容的第二电极板；所述第二电容的第一电极板与下拉节点电连接，所述第二电容的第二电极板用于加载低电平信号；
第一输出晶体管，所述第一输出晶体管的漏极与所述上拉节点电连接，所述第一输出晶体管的漏极与所述第一电容的第一电极板电连接；所述第二移位寄存器单元的第一输出晶体管的源极和相邻的所述移位寄存器单元的第一输出晶体管的源极中，一个用于加载第一时钟信号且另一个用于加载第二时钟信号；所述第一时钟信号和所述第二时钟信号为 反相信号；
第二输出晶体管，所述第二输出晶体管的源极用于加载所述低电平信号，所述第二输出晶体管的漏极与所述第一电容的第一电极板电连接，所述第二输出晶体管的栅极与所述下拉节点电连接；
第一下拉晶体管，所述第一下拉晶体管的源极用于加载所述低电平信号，所述第一下拉晶体管的漏极与所述上拉控制节点电连接，所述第一下拉晶体管的栅极与所述下拉节点电连接；
第一下拉控制晶体管，所述第一下拉控制晶体管的源极用于加载所述低电平信号，所述第一下拉控制晶体管的漏极与所述下拉节点电连接，所述第一下拉控制晶体管的栅极与所述上拉控制节点电连接；
第二下拉控制晶体管，所述第二下拉控制晶体管的漏极与所述下拉节点电连接，所述第二下拉控制晶体管的栅极与所述第二下拉控制晶体管的源极电连接；所述第二下拉控制晶体管的源极和所述第一输出晶体管的源极中的一个用于加载所述第一时钟信号且另一个用于加载所述第二时钟信号；
第二下拉晶体管，所述第二下拉晶体管的源极用于加载所述低电平信号，所述第二下拉晶体管的漏极与所述下拉节点电连接，所述第二下拉晶体管的栅极与所述第一电容的第一电极板电连接；
复位晶体管，所述复位晶体管的源极用于加载所述低电平信号，所述复位晶体管的漏极与所述上拉控制节点电连接，所述复位晶体管的栅极用于加载复位控制信号；
所述上拉控制节点和所述上拉节点电连接。
根据本公开的一种实施方式，所述第一输入晶体管包括串联的两个亚晶体管，两个亚晶体管共栅极；
所述第二输入晶体管包括串联的两个亚晶体管，两个亚晶体管共栅极。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一种实施方式中，显示面板的结构示意图。
图2为本公开一种实施方式中，栅极驱动电路的分布示意图。
图3为本公开一种实施方式中，栅极驱动电路的分布示意图。
图4为本公开一种实施方式中，移位寄存器单元的结构示意图。
图5为本公开一种实施方式中，半导体层的结构示意图。
图6为本公开一种实施方式中，栅极层的结构示意图。
图7为本公开一种实施方式中，源漏金属层的结构示意图。
图8为本公开一种实施方式中，半导体层、栅极层和源漏金属层的层叠结构示意图。
图9为本公开一种实施方式中，相邻两级移位寄存器单元之间的时序示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上， 或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区，并且电流可以流过漏极、沟道区以及源极。沟道区是指电流主要流过的区域。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。
结构层A位于结构层B背离衬底基板的一侧，可以理解为，结构层A在结构层B背离衬底基板的一侧形成。当结构层B为图案化结构时，结构层A的部分结构也可以位于结构层B的同一物理高度或低于结构层B的物理高度，其中，衬底基板为高度基准。
本公开提供一种显示面板PNL以及驱动该显示面板PNL的栅极驱动电路GDC。参见图1，显示面板PNL包括显示区AA和围绕所述显示区AA的外围区BB。在显示区AA中，设置有子像素和用于驱动子像素的像素驱动电路PDC，子像素可以为光阀或者自发光元件。在像素驱动电路PDC的控制下，各个子像素各自独立的发光，以使得显示面板PNL显示画面。
举例而言，在本公开的一种实施方式中，显示面板PNL可以为液晶显示面板，其包括对盒设置的阵列基板和彩膜基板，在阵列基板和彩膜基板形成的液晶盒中填充有液晶。这样，子像素可以为作为光阀的液晶单元；该液晶单元包括用于控制电场的两个电极和在电场的控制下翻转或者倒伏的液晶。两个电极中的一个可以作为像素电极，且另一个可以作为公共电极；各个公共电极可以相互电连接以共同加载公共电压；像素驱动电路 PDC可以与各个像素电极一一对应的电连接，以通过对像素电极上的电压的控制来调节像素电极对应的区域的电场，进而控制该像素电极对应的区域的液晶的翻转或者倒伏程度。如此，显示面板PNL在上偏光片、下偏光片的配合下，能够控制各个子像素的透光率。
再举例而言，在本公开的一种实施方式中，显示面板PNL可以为具有自发光元件的显示面板，自发光元件包括但不现有OLED、PLED、QLED、Q-OLED、Micro LED、Mini LED等。显示面板PNL可以包括依次层叠设置的衬底基板BP、驱动层和像素层；其中，发光元件设置于像素层中以作为子像素，驱动层中设置有驱动子像素的像素驱动电路PDC。像素驱动电路PDC可以控制流过发光元件的电流的大小，进而控制发光元件的发光亮度。
参见图1，显示面板PNL还可以设置有沿行方向DH延伸的扫描线GL和沿列方向DV延伸的驱动数据线，像素驱动电路PDC可以与扫描线GL和驱动数据线电连接。在扫描线GL上的扫描信号的控制下，像素驱动电路PDC可以接收加载在驱动数据线上的驱动数据，进而根据所接收的驱动数据控制子像素的亮度。示例性的，像素驱动电路PDC可以包括一个数据写入晶体管，该数据写入晶体管的控制端与扫描线GL电连接，该数据写入晶体管的输入端与驱动数据线电连接。当扫描线GL上加载扫描信号时，该数据写入晶体管导通，进而使得驱动数据线上加载的驱动数据被写入像素驱动电路PDC的电容中。当扫描线GL上不加载扫描信号时，该数据写入晶体管电截止，进而使得驱动数据线上加载的驱动数据不能够被写入像素驱动电路PDC的电容中。
参见图1，在显示区AA的一侧可以设置有栅极驱动电路GDC，以用于向各个扫描线GL加载扫描信号。可选的，栅极驱动电路GDC设置于显示区AA沿行方向DH的一侧，其可以包括依次级联的多个移位寄存器单元GOA，每个扫描线GL可以与一个移位寄存器单元GOA的输出端电连接。这样，当移位寄存器单元GOA输出扫描信号时，该扫描信号可以加载至扫描线GL。在相关技术中，栅极驱动电路GDC中的各个移位寄存器单元GOA均是相同的，且沿列方向DV依次排列。然而，这种设置方式会导致栅极驱动电路GDC占用的面积较大，进而会导致显示面板PNL 的边框增大，不利于显示面板PNL的窄边框化。
在本公开的实施方式中，栅极驱动电路GDC中设置两种不同的移位寄存器单元GOA，即第一移位寄存器单元GOAA和第二移位寄存器单元GOAB；所述第一移位寄存器单元GOAA的晶体管数量小于所述第二移位寄存器单元GOAB的晶体管数量。其中，在级联关系上，第一移位寄存器单元GOAA和第二移位寄存器单元GOAB相互间隔。这样，本公开的像素驱动电路PDC包括依次级联的多个移位寄存器单元GOA，移位寄存器单元GOA包括第一移位寄存器单元GOAA和第二移位寄存器单元GOAB两种，第一移位寄存器单元GOAA和所述第二移位寄存器单元GOAB相互间隔设置。
如此，本公开的栅极驱动电路GDC通过交替设置第一移位寄存器单元GOAA和第二移位寄存器单元GOAB，既可以利用第二移位寄存器单元GOAB具有更多晶体管而带来的功能和益处，例如具有更高的稳定性等；又可以通过设置第一移位寄存器单元GOAA来减少栅极驱动电路GDC所需的晶体管的总体数量，且借助第二移位寄存器单元GOAB来提高自身的稳定性，克服全部采用第一移位寄存器单元GOAA时所面临的功能不足的问题。这样，本公开的栅极驱动电路GDC，即避免了全部设置第二移位寄存器单元GOAB所面临的晶体管数量太多的问题，又避免了全部设置第一移位寄存器单元GOAA而导致在整体上面临功能不足的问题，通过间隔与第一移位寄存器单元GOAA之间的第二移位寄存器单元GOAB来在整体层面对栅极驱动电路GDC的功能进行补足。
在本公开的一种实施方式中，参见图1，所述显示区AA设置有多个像素驱动电路PDC；至少部分所述第一移位寄存器单元GOAA输出的信号和至少部分所述第二移位寄存器单元GOAB输出的信号用于驱动所述像素驱动电路PDC。换言之，在该实施方式中，第一移位寄存器单元GOAA和第二移位寄存器单元GOAB均具有驱动像素驱动电路PDC的能力，这样可以减少栅极驱动电路GDC中移位寄存器单元GOA的数量，进而减小栅极驱动电路GDC的面积。
在一种示例中，参见图1，像素驱动电路PDC中的各个移位寄存器单元GOA与扫描线GL一一对应设置，每个移位寄存器单元GOA拥有驱动 对应的扫描线GL。
在本公开的一种实施方式中，参见图2，所述栅极驱动电路设于所述显示区AA在行方向DH的一侧。所述外围区BB设置有用于布设所述第一移位寄存器单元GOAA的第一电路区域XA和用于布设所述第二移位寄存器单元GOAB的第二电路区域XB；其中，所述第二电路区域XB的部分区域位于所述第一电路区域XA远离所述显示区AA的一侧。这样，第二移位寄存器单元GOAB中的部分晶体管可以布设在第一移位寄存器单元GOAA远离显示区AA的一侧；一方面，这可以减小第二移位寄存器单元GOAB在行方向上的尺寸，进而减小显示面板PNL的边框宽度。另一方面，这可以避免第二电路区域XB间隔在第一电路区域XA和显示区AA之间，进而避免第一移位寄存器单元GOAA的输出走线贯穿第二电路区域XB以驱动扫描线GL，进而避免了因交叠等而引起的寄生电容。
可选的，参见图2，所述栅极驱动电路包括多个移位寄存器单元组GOAS，每个所述移位寄存器单元组GOAS包括相邻的一个第一移位寄存器单元GOAA和一个第二移位寄存器单元GOAB；同一所述移位寄存器单元组GOAS中，第一移位寄存器单元GOAA对应的第一电路区域XA和第二移位寄存器单元GOAB对应的第二电路区域XB互补成矩形。换言之，在图2的示例中，用于布设第一移位寄存器单元GOAA的第一电路区域XA和用于布设第二移位寄存器单元GOAB的第二电路区域XB之间互不成矩形，则该第一移位寄存器单元GOAA和第二移位寄存器单元GOAB可以作为一个移位寄存器单元组GOAS。这种设置方式，能够使得栅极驱动电路GDC的布图更为紧凑，减少面积浪费以利于减小显示面板PNL的边框。
在本公开的一种实施方式中，参见图2和图3，所述显示面板PNL设置有与所述栅极驱动电路对应的内走线组WLAS和外走线组WLBS，所述内走线组WLAS和所述外走线组WLBS中的驱动走线均用于驱动所述栅极驱动电路，且所述内走线组WLAS位于所述外走线组WLBS靠近所述显示区AA的一侧。所述移位寄存器单元组GOAS与所述外走线组WLBS的任意一个驱动走线之间通过最多一个转接线电连接。这样，移位寄存器单元组GOAS中的第一移位寄存器单元GOAA和第二移位寄存器 单元GOAB，无需均各自独立地通过转接线与外走线组WLBS中的驱动走线电连接，这样可以减少走线之间的交叠，进而减低阻抗和减小串扰，提高栅极驱动电路GDC的稳定性。
进一步的，参见图8，在第一移位寄存器单元GOAA中，第二移位寄存器单元GOAB通过转接线与外走线组WLBS中的各个驱动走线电连接。这样，即便走线交叠引起的信号波动等，也可以被第二移位寄存器单元GOAB凭借更多的功能而抑制或者耐受，既能够充分利用第二移位寄存器单元GOAB通过设置更多晶体管而具有更多功能和更好性能的特点，又可以使得第二移位寄存器单元GOAB在一定程度上作为缓冲，来提高传输至第一移位寄存器单元GOAA的信号的稳定性，降低第一移位寄存器单元GOAA因晶体管较少而面临的性能不足的问题。
在一种示例中，参见图8，述外走线组WLBS包括沿列方向DV延伸的第一低电平信号线VGLLA、复位控制线RSTL、第一扫描控制线CNL和第二扫描控制线CNBL。分别位于两个不同的移位寄存器单元组GOAS中且相邻的第一移位寄存器单元GOAA和第二移位寄存器单元GOAB，与同一所述第一低电平信号线VGLLA电连接；所述复位控制线RSTL用于向所述移位寄存器单元组GOAS提供复位控制信号Rst；所述第一扫描控制线CNL用于向所述移位寄存器单元组GOAS提供第一扫描控制信号CN；所述第二扫描控制线CNBL拥有向所述移位寄存器单元组GOAS提供第二扫描控制信号CNB；所述第一扫描控制信号CN和所述第二扫描控制信号CNB为反相信号。
在一种示例中，参见图8，所述第一移位寄存器单元GOAA包括第一输入晶体管AT1和第二输入晶体管AT2；所述第二移位寄存器单元GOAB包括第一输入晶体管BT1和第二输入晶体管BT2；所述第一输入晶体管BT1位于所述第一输入晶体管AT1与所述外走线组WLBS之间，且沿行方向DH排列；所述第二输入晶体管BT2位于所述第二输入晶体管AT2与所述外走线组WLBS之间，且沿行方向DH排列。所述第一输入晶体管的源极AT1S和所述第一输入晶体管的源极BT1S通过同一导电结构电连接至所述第一扫描控制线CNL。所述第二输入晶体管的源极AT2S和所述第二输入晶体管的源极BT2S通过同一导电结构电连接至所述第二扫描控 制线CNBL。这样，可以简化移位寄存器单元组GOAS的布线，且提高移位寄存器单元组GOAS中晶体管布设的紧凑性。另一方面，栅极驱动电路GDC在工作时，可以通过控制第二扫描控制线CNBL上加载的第二扫描控制信号CNB和第一扫描控制线CNL上加载的第一扫描控制信号CN，使得栅极驱动电路GDC实现正扫和反扫等不同的工作模式。换言之，在该示例中，尽管第一移位寄存器单元GOAA具有较少的晶体管数量，但是其依然可以与第一移位寄存器单元GOAA级联，且实现正扫模式和反扫模式。这可以使得栅极驱动电路GDC的功能更为完善。
在本公开实施方式中，AT开头的编号用于表示第一移位寄存器单元GOAA中的晶体管或者晶体管的源极、栅极、漏极、沟道区，以便与第二移位寄存器单元GOAB中的晶体管在标号上进行区分。
在本公开的一种实施方式中，所述第一移位寄存器单元GOAA包括：
第一输入晶体管AT1，所述第一输入晶体管的源极AT1S用于加载第一扫描控制信号CN，所述第一输入晶体管的漏极AT1D与上拉节点APU(同时作为上拉控制节点)电连接，所述第一输入晶体管的栅极AT1G用于与上一级移位寄存器单元GOA的输出端电连接；
第二输入晶体管AT2，所述第二输入晶体管的源极AT2S用于加载第二扫描控制信号CNB，所述第二输入晶体管的漏极AT2D与所述上拉节点APU电连接，所述第二输入晶体管的栅极AT2G与下拉节点APD电连接，且用于与下一级移位寄存器单元GOA的输出端电连接；所述第一扫描控制信号CN和所述第二扫描控制信号CNB为反相信号；
第三电容C3，具有第三电容的第一电极板CP5和第三电容的第二电极板CP6；所述第三电容的第二电极板CP6与所述上拉节点APU电连接，所述第三电容的第一电极板CP5与所述第一移位寄存器单元GOAA的输出端电连接；
第一输出晶体管AT3，所述第一输出晶体管的漏极AT3D与第三电容的第一电极板CP5电连接，所述第一输出晶体管的栅极AT3G与所述上拉节点APU电连接；所述第一移位寄存器单元GOAA的第一输出晶体管的源极AT3S和相邻的所述移位寄存器单元GOA的第一输出晶体管的源极BT3S中，一个用于加载第一时钟信号CK且另一个用于加载第二时钟信 号CKB；所述第一时钟信号CK和所述第二时钟信号CKB为反相信号；
第二输出晶体管AT4，所述第二输出晶体管的源极AT4S用于加载低电平信号VGL，所述第二输出晶体管的漏极AT4D与所述第三电容的第一电极板CP5电连接，所述第二输出晶体管的栅极AT4G与所述下拉节点APD电连接；
下拉控制晶体管AT12，所述下拉控制晶体管的源极AT12S用于加载所述低电平信号VGL，所述下拉控制晶体管的漏极AT12D与所述下拉节点APD电连接，所述下拉控制晶体管的栅极AT12G与所述第一输入晶体管的栅极AT1G电连接。
在该第一移位寄存器单元GOAA中，第一输入晶体管AT1和第二输入晶体管AT2可以作为输入模块，用于接收上一级移位寄存器单元GOA的输出和下一级移位寄存器单元GOA的输出，并通过第一扫描控制信号CN和第二扫描控制信号CNB来实现正扫模式和反扫模式。在该示例中，下拉控制晶体管AT12可以与上一级移位寄存器单元GOA的输出电连接，进而可以在上一级移位寄存器单元GOA的输出端的电压的控制下，对下拉节点APD进行稳压，避免了下拉节点APD浮接而可能出现的不稳定。
在本公开的一种实施方式中，参见图8，所述第一输入晶体管AT1包括串联的两个亚晶体管，两个亚晶体管共栅极。所述第二输入晶体管AT2包括串联的两个亚晶体管，两个亚晶体管共栅极。由于第一输入晶体管AT1和第二输入晶体管AT2的源漏两端会较长时间保持较大的压差，这不利于第一输入晶体管AT1和第二输入晶体管AT2的耐受；为此，本公开通过使得第一输入晶体管AT1和第二输入晶体管AT2均为两个串联的亚晶体管，可以使得两个亚晶体管分压，进而降低每个亚晶体管的源漏端的电压差，提高第一输入晶体管AT1、第二输入晶体管AT2的耐受性。举例而言，当第一输入晶体管AT1两端的点压差为16V时，通过两个亚晶体管的分压，两个亚晶体管的连接处的电压可以为9V，这使得一个亚晶体管的源漏压差为7V，且另一个亚晶体管的源漏压差为9V，进而减小了源漏压差，降低了第一输入晶体管AT1背击穿的风险。
在本公开的一种实施方式中，第一输入晶体管AT1和第二输入晶体管AT2的每个亚晶体管的尺寸相同。例如每个亚晶体管的沟道区宽度为15.7 微米，每个亚晶体管的沟道区长度为5微米。
在本公开的一种实施方式中，第一输出晶体管AT3A可以具有大的宽长比，以提高第一输出晶体管AT3的驱动能力。进一步的，可以将第一输出晶体管AT3分为多个并联的亚晶体管，以利于第一输出晶体管AT3的制备和排布。举例而言，参见图8，第一输出晶体管AT3可以被分为四个亚晶体管，四个亚晶体管分为两组，两组亚晶体管共源极设置，两组亚晶体管的漏极电连接以与第一输出线OUTLA电连接。
作为一种示例，第一输出晶体管AT3A的总长度为108微米，第一输出晶体管AT3A的宽度为7微米。
在本公开的一种实施方式中，第二输出晶体管AT4A也可以具有稍大的宽长比，且第二输出晶体管AT4A的宽长比小于第一输出晶体管AT3A的宽长比。例如，第二输出晶体管AT4A总长度为32微米，第二输出晶体管AT4A的宽度为7微米。进一步的，可以将第二输出晶体管AT4可以分为多个并联的亚晶体管，以利于第二输出晶体管AT4的制备和排布。举例而言，参见图8，第二输出晶体管AT4可以被分为两个亚晶体管。
在一种示例中，第二输出晶体管AT4的两个亚晶体管和第一输出晶体管AT3的其中两个亚晶体管可以共漏极设置，并与第一输出线OUTLA电连接。这样，可以提高第一移位寄存器单元GOAA布线的紧凑性。
在本公开的一种实施方式中，所述第一移位寄存器单元GOAA还包括：
触控控制晶体管AT11，所述触控控制晶体管的源极AT11S用于加载所述低电平信号VGL，所述触控控制晶体管的漏极AT11D与所述第三电容的第一电极板CP5电连接，所述触控控制晶体管的栅极AT11G用于加载触控控制信号ENT。当显示面板PNL进行触控时，触控控制信号ENT会加载至触控控制晶体管的栅极AT11G而使得触控控制晶体管的栅极AT11G导通，进而使得第一输出线OUTLA不输出扫描信号。
进一步的，参见图2和图8，内走线组WLAS包括用于加载触控控制信号ENT的触控控制线ENTL，触控控制晶体管的栅极AT11G与触控控制线ENTL电连接。
在本公开实施方式中，BT开头的编号用于表示第二移位寄存器单元 GOAB中的晶体管或者晶体管的源极、栅极、漏极、沟道区，以便与第一移位寄存器单元GOAA中的晶体管在标号上进行区分。
在本公开的一种实施方式中，所述第二移位寄存器单元GOAB包括：
第一输入晶体管BT1，所述第一输入晶体管的源极BT1S用于加载第一扫描控制信号CN，所述第一输入晶体管的漏极BT1D用于与上拉控制节点BPUCN电连接，所述第一输入晶体管的栅极BT1G用于与上一级所述移位寄存器单元GOA的输出端电连接；
第二输入晶体管BT2，所述第二输入晶体管的源极BT2S用于加载第二扫描控制信号CNB，所述第二输入晶体管的漏极BT2D用于与所述上拉控制节点BPUCN电连接，所述第二输入晶体管的栅极BT2G用于与下一级所述移位寄存器单元GOA的输出端电连接；所述第一扫描控制信号CN和所述第二扫描控制信号CNB为反相信号；
第一电容C1，包括第一电容的第一电极板CP1和第一电容的第二电极板CP2；所述第一电容的第一电极板CP1与所述第二移位寄存器单元GOAB的输出端电连接，所述第一电容的第二电极板CP2与上拉节点BPU电连接；
第二电容C2，包括第二电容的第一电极板CP3和第二电容的第二电极板CP4；所述第二电容的第一电极板CP3与下拉节点BPD电连接，所述第二电容的第二电极板CP4用于加载低电平信号VGL；
第一输出晶体管BT3，所述第一输出晶体管的漏极BT3D与所述上拉节点BPU电连接，所述第一输出晶体管的漏极BT3D与所述第一电容的第一电极板CP1电连接；所述第二移位寄存器单元GOAB的第一输出晶体管的源极BT3S和相邻的所述移位寄存器单元GOA的第一输出晶体管的源极BT3S中，一个用于加载第一时钟信号CK且另一个用于加载第二时钟信号CKB；所述第一时钟信号CK和所述第二时钟信号CKB为反相信号；
第二输出晶体管BT4，所述第二输出晶体管的源极BT4S用于加载所述低电平信号VGL，所述第二输出晶体管的漏极BT4D与所述第一电容的第一电极板CP1电连接，所述第二输出晶体管的栅极BT4G与所述下拉节点BPD电连接；
第一下拉晶体管BT5，所述第一下拉晶体管的源极BT5S用于加载所述低电平信号VGL，所述第一下拉晶体管的漏极BT5D与所述上拉控制节点BPUCN电连接，所述第一下拉晶体管的栅极BT5G与所述下拉节点BPD电连接；
第一下拉控制晶体管BT6，所述第一下拉控制晶体管的源极BT6S用于加载所述低电平信号VGL，所述第一下拉控制晶体管的漏极BT6D与所述下拉节点BPD电连接，所述第一下拉控制晶体管的栅极BT6G与所述上拉控制节点BPUCN电连接；
第二下拉控制晶体管BT7，所述第二下拉控制晶体管的漏极BT7D与所述下拉节点BPD电连接，所述第二下拉控制晶体管的栅极BT7G与所述第二下拉控制晶体管的源极BT7S电连接；所述第二下拉控制晶体管的源极BT7S和所述第一输出晶体管的源极BT3S中的一个用于加载所述第一时钟信号CK且另一个用于加载所述第二时钟信号CKB；
第二下拉晶体管BT8，所述第二下拉晶体管的源极BT8S用于加载所述低电平信号VGL，所述第二下拉晶体管的漏极BT8D与所述下拉节点BPD电连接，所述第二下拉晶体管的栅极BT8G与所述第一电容的第一电极板CP1电连接；
复位晶体管BT10，所述复位晶体管的源极BT10S用于加载所述低电平信号VGL，所述复位晶体管的漏极BT10D与所述上拉控制节点BPUCN电连接，所述复位晶体管的栅极BT10G用于加载复位控制信号Rst；
所述上拉控制节点BPUCN和所述上拉节点BPU电连接。
在该第二移位寄存器单元GOAB中，第一输入晶体管BT1和第二输入晶体管BT2可以作为输入模块，用于接收上一级移位寄存器单元GOA的输出和下一级移位寄存器单元GOA的输出，并通过第一扫描控制信号CN和第二扫描控制信号CNB来实现正扫模式和反扫模式。在该示例中，第二下拉控制晶体管BT7用于响应第二时钟信号CKB以控制下拉节点BPD，以通过下拉节点BPD的电压来周期性的控制第一下拉晶体管BT5导通，进而实现对上拉控制节点BPUCN的周期性下拉；且通过下拉节点BPD的高电平信号使得第二输出晶体管BT4保持导通，使得第二移位寄存器单元GOAB输出低电平信号。当输入模块使得上拉控制节点BPUCN 上拉时，第一下拉控制晶体管BT6可以下拉下拉节点BPD，进而使得第一下拉晶体管BT5和第二输出晶体管BT4截止，使得上拉控制节点BPUCN的电压被维持，进而使得上拉节点BPU的电压为维持在高电平，使得第一输出晶体管BT3导通而输出扫描信号。在第一输出晶体管BT3导通而输出扫描信号时，第二下拉晶体管BT8可以导通以下拉下拉节点BPD，进而使得下拉节点BPD维持低电平、上拉控制节点BPUCN维持高电平、上拉节点BPU维持高电平、第一输出晶体管BT3导通而输出扫描信号，直至第一时钟信号CK变为低电平信号。
在一种示例中，参见图4，所述第二移位寄存器单元GOAB还包括使能晶体管BT9和触控控制晶体管BT11；所述上拉控制节点BPUCN和所述上拉节点BPU通过所述使能晶体管BT9电连接；
其中，所述使能晶体管的源极BT9S与所述上拉控制节点BPUCN电连接，所述使能晶体管的漏极BT9D与所述上拉节点BPU电连接，所述使能晶体管的栅极BT9G用于加载高电平信号VGH；所述触控控制晶体管的源极BT11S与所述低电平信号VGL电连接，所述触控控制晶体管的漏极BT11D与所述第一电容的第一电极板CP1电连接，所述触控控制晶体管的栅极BT11G用于加载触控控制信号ENT；所述触控控制信号ENT与所述高电平信号VGH为反相信号。
这样，当显示面板PNL进行触控时，可以通过触控控制线ENTL向触控控制晶体管的栅极BT11G加载高电平的触控控制信号ENT，进而使得触控控制晶体管BT11导通，这使得第二移位寄存器单元GOAB的输出为低电平信号。相应的。高电平信号VGH变为电平信号，进而使得使能晶体管BT9截止，进而避免第一输出晶体管BT3导通。
在一种示例中，参见图8，所述第一输入晶体管BT1包括串联的两个亚晶体管，两个亚晶体管共栅极；所述第二输入晶体管BT2包括串联的两个亚晶体管，两个亚晶体管共栅极。由于第一输入晶体管BT1和第二输入晶体管BT2的源漏两端会较长时间保持较大的压差，这不利于第一输入晶体管BT1和第二输入晶体管BT2的耐受；为此，本公开通过使得第一输入晶体管BT1和第二输入晶体管BT2均为两个串联的亚晶体管，可以使得两个亚晶体管分压，进而降低每个亚晶体管的源漏端的电压差，提高第 一输入晶体管BT1、第二输入晶体管BT2的耐受性。进一步的，第一输入晶体管BT1和第二输入晶体管BT2对阈值偏移的耐受可以达到6V。
在一种示例中，第二移位寄存器单元GOAB的第一输入晶体管BT1A的尺寸与第一移位寄存器单元GOAA的第一输入晶体管AT1A的尺寸相同；第二移位寄存器单元GOAB的第二输入晶体管BT2A的尺寸与第一移位寄存器单元GOAA的第二输入晶体管AT2A的尺寸相同。
在一种示例中，参见图8，第一输出晶体管BT3A可以具有大的宽长比，以提高第一输出晶体管BT3的驱动能力。进一步的，可以将第一输出晶体管BT3分为多个并联的亚晶体管，以利于第一输出晶体管BT3的制备和排布。举例而言，参见图8，第一输出晶体管BT3可以被分为四个并联亚晶体管，四个亚晶体管沿行方向依次排列。
在一种示例中，在一种示例中，第二移位寄存器单元GOAB的第一输出晶体管BT3A的尺寸与第一移位寄存器单元GOAA的第一输出晶体管AT3A的尺寸相同。
在本公开的一种实施方式中，第二输出晶体管BT4A也可以具有稍大的宽长比，且第二输出晶体管BT4A的宽长比小于第一输出晶体管BT3A的宽长比。进一步的，可以将第二输出晶体管BT4可以分为多个并联的亚晶体管，以利于第二输出晶体管BT4的制备和排布。举例而言，参见图8，第二输出晶体管BT4可以被分为两个亚晶体管。
在一种示例中，在一种示例中，第二移位寄存器单元GOAB的第二输出晶体管BT4A的尺寸与第一移位寄存器单元GOAA的第二输出晶体管AT4A的尺寸相同。
在本公开提供的上述示例性的栅极驱动电路GDC中，尽管第一移位寄存器单元GOAA和第二移位寄存器单元GOAB的晶体管的数量并不相同，但是均具有类似的输入模块(第一移位寄存器单元GOAA中的第一输入晶体管AT1和第二输入晶体管AT2，第二移位寄存器单元GOAB中的第一输入晶体管BT1、第二输入晶体管BT2)和输出模块(第一移位寄存器单元GOAA中的第一输出晶体管AT3和第二输出晶体管AT4，第二移位寄存器单元GOAB中的第一输出晶体管BT3和第二输出晶体管BT4)，相应的也都具有与上拉节点电连接的电容(例如第一移位寄存器单元 GOAA中与上拉节点APU电连接的第三电容C3、第二移位寄存器单元GOAB中与上拉节点BPU电连接的第一电容C1)，且都设置有下拉节点(例如第一移位寄存器单元GOAA中的下拉节点APD和第二移位寄存器单元GOAB中的下拉节点BPD)。因此，第一移位寄存器单元GOAA和第二移位寄存器单元GOAB均能够通过输入模块实现信号的输入，使得级联的移位寄存器单元GOA能够逐级输出扫描信号。第一移位寄存器单元GOAA和第二移位寄存器单元GOAB均能够响应上拉节点的电压拉升，而输出高电平的扫描信号；第一移位寄存器单元GOAA和第二移位寄存器单元GOAB均能够响应下拉的电压拉升，而输出低电平信号。相应的，第二移位寄存器单元GOAB中设置有其他提高第二移位寄存器单元GOAB性能和功能的晶体管(例如第二移位寄存器单元GOAB中的第二下拉控制晶体管BT7、第一下拉晶体管BT5、第一下拉控制晶体管BT6、第二下拉晶体管BT8和复位晶体管BT10)，第二移位寄存器单元GOAB中的这些晶体管在使得第二移位寄存器单元GOAB性能稳定的同时，还可以通过向第一移位寄存器单元GOAA的第一输入晶体管BT12加载信号而使得第一移位寄存器单元GOAA的下拉节点APD保持稳定，避免下拉节点APD的浮接，这使得第一移位寄存器单元GOAA能够依赖第二移位寄存器单元GOAB的稳定而保持性能稳定。同时，该示例性的栅极驱动电路GDC中，第一移位寄存器单元GOAA和第二移位寄存器单元GOAB通过设置基本相同的输出模块，可以使得第一移位寄存器单元GOAA与第二移位寄存器单元GOAB具有类似或者相同的驱动能力；通过第二移位寄存器单元GOAB的输出端对第一移位寄存器单元GOAA的下拉节点APD的控制，还可以使得第一移位寄存器单元GOAA和第二移位寄存器单元GOAB具有基本相同的响应速度。
参见图9，其示例了相邻的两个移位寄存器单元GOA之间的驱动时序，工作模式为正扫描模式。其中，其中一级移位寄存器单元GOA为第一移位寄存器单元GOAA，且另一级移位寄存器单元GOA为第二移位寄存器单元GOAB。其中，在该示例中，上一级移位寄存器单元GOA的第一输出晶体管的源极和栅极用于加载第二时钟信号CKB，本级移位寄存器单元GOA的第一输出晶体管的源极和栅极用于加载第一时钟信号CK。
参见图9，在第一时刻t1，第二时钟信号CKB为高电平信号且第一时钟信号CK为低电平信号，此时上一级移位寄存器单元GOA输出高电平的扫描信号；这使得本级移位寄存器单元GOA的PU第一扫描控制信号CN开始拉升，进而使得PU开始拉升，下拉节点被下拉。本级移位寄存器单元GOA输出低电平信号。在第二时刻t2，第二时钟信号CKB变为低电平信号，上一级移位寄存器单元GOA输出的电压变为低电平信号，因此对本级移位寄存器单元GOA的各个节点的电压和输出的电压没有影响。在第三时刻t3，第一时钟信号CK变为高电平信号；此时，本级移位寄存器单元GOA可以将第一时钟信号CK的高电平信号输出，进而使得本级移位寄存器单元GOA输出高电平的扫描信号。在耦合作用下，上拉节点和上拉控制节点的电压被拉升，进一步使得移位寄存器单元GOA保持输出高电平的扫描信号。在第四时刻t4，第一时钟信号CK变为低电平信号，进而使得本级移位寄存器单元GOA的输出端的电压下降，通过耦合作用，使得下拉节点和下拉控制节点的电压下降，此时移位寄存器单元GOA的输出端为低电平信号。在第五时刻t5，下一级移位寄存器单元GOA输出高电平信号，进而使得本级移位寄存器单元GOA的第二输入晶体管向上拉节点加载低电平信号，进而使得本级移位寄存器单元GOA的上拉节点为低电平信号。如此，上一级移位寄存器单元GOA、本级移位寄存器单元GOA和下一级移位寄存器单元GOA依次输出高电平的扫描信号，这种依次输出，与移位寄存器单元GOA是第一移位寄存器单元GOAA还是第二移位寄存器单元GOAB没有关系。
因此，本公开上述示例的栅极驱动电路GDC能够在保证栅极驱动电路GDC性能稳定和功能完整的情况下，减少栅极驱动电路GDC的晶体管数量，进而利于减小显示面板PNL的边框。可以理解的是，本公开通过的上述示例的栅极驱动电路GDC，尤其是提供的图4中的第一移位寄存器单元GOAA和第二移位寄存器单元GOAB的示例性的结构，仅为本公开的栅极驱动电路GDC的一种示例。为了达成相同的目的和适应显示面板PNL的需要，栅极驱动电路GDC也可以采用其他结构的第一移位寄存器单元GOAA和其他结构的第二移位寄存器单元GOAB。
在本公开的一些实施方式中，参见图1，所述显示面板PNL包括两个 所述栅极驱动电路，两个所述栅极驱动电路分别位于所述显示区AA的两侧；任意一行所述像素驱动电路PDC被两个所述栅极驱动电路同时驱动。换言之，本公开的显示面板PNL可以在显示区AA的两侧分别设置栅极驱动电路GDC，且每行像素驱动电路PDC同时通过两个栅极驱动电路GDC进行驱动。这样，可以提高对每行像素驱动电路PDC的驱动能力，进而提高像素驱动电路PDC的充电率，克服了单个栅极驱动电路GDC可能的充电能力不足的问题。尤其是在大尺寸显示面板PNL中，这可以显著的提高像素驱动电路PDC的充电率；在一些实施方式中，像素驱动电路PDC的充电率可以提高2.37％或者更多。
在相关技术中，显示面板PNL两侧分别设置栅极驱动电路GDC的方式会导致显示面板PNL边框更大；然而在本公开中，每个栅极驱动电路GDC的宽度更小，这可以更有效的减小显示面板PNL的边框，使得该栅极驱动电路GDC尤其适合在双栅极驱动电路GDC的显示面板PNL中。
在本公开的一种实施方式中，任意一行所述像素驱动电路PDC，被一个所述栅极驱动电路的第一移位寄存器单元GOAA驱动，且被另一个所述栅极驱动电路的第二移位寄存器单元GOAB驱动。换言之，扫描线GL的两端分别连接两个移位寄存器单元GOA，两个移位寄存器单元GOA分别为第一移位寄存器单元GOAA和第二移位寄存器单元GOAB。这样，连接于同一扫描线GL上的第一移位寄存器单元GOAA和第二移位寄存器单元GOAB分别属于不同的栅极驱动电路GDC，但是可以通过所连接的扫描线GL相互配合，达成对扫描线GL上所连接的像素驱动电路PDC的共同驱动。这样，第一移位寄存器单元GOAA不仅可以获得同一栅极驱动电路GDC中相邻的第二移位寄存器单元GOAB的功能支持而维持稳定和保持良好性能，而且连接于同一扫描线GL上的第二移位寄存器单元GOAB也可以对其输出端提供影响，避免了第一移位寄存器单元GOAA因可能的波动、响应慢而对下一级第二移位寄存器单元GOAB的影响。
从另一方面看，参见图1，两个栅极驱动电路GDC通过扫描线GL连接，且每一个扫描线GL均连接有第二移位寄存器单元GOAB，这在一定程度上相当于第二移位寄存器单元GOAB跨显示区AA依次级联，进而保持栅极驱动电路GDC的高性能；第一移位寄存器单元GOAA作为补偿电 路对扫描线GL进行驱动与连接于同一扫描线GL上的第二移位寄存器单元GOAB进行协同来提高对该扫描线GL上的像素驱动电路PDC的驱动能力。
如下，结合一种具体的示例，对本公开的栅极驱动电路GDC的结构、原理和实现做更进一步的说明。该示例性的栅极驱动电路GDC中，第一移位寄存器单元GOAA和第二移位寄存器单元GOAB的等效电流如图4所示。
在该示例中，显示面板PNL包括依次层叠设置的衬底基板BP、半导体层SEMI、栅极层GT和半导体层SD，在半导体层SEMI和栅极层GT之间设置有栅极绝缘层，在栅极层GT和半导体层SD之间设置有层间电介质层。其中
参见图5和图8，在一个移位寄存器单元组GOAS对应的第一电路区域XA和第二电路区域XB内，半导体层SEMI可以包括移位寄存器单元GOA的各个晶体管的沟道区，以及包括位于沟道区两侧的晶体管的源极和晶体管的漏极。半导体层SEMI还可以设置有一些电容的电极板，以增大电容的容量或者缩小电容的面积。其中，晶体管的沟道区可以保持半导体特性，具体的可以保持N型半导体特性，以使得各个晶体管为N型晶体管。晶体管的源极和晶体管的漏极、电极板可以被导体化。
参见图5和图8，第一电路区域XA和第二电路区域XB均靠近显示区AA设置；在第二电路区域XB具有一凸出区域，该凸出区域位于第一电路区域XA远离显示区AA的一侧。这样，可以减小第二电路区域XB的宽度，进而减小栅极驱动电路GDC的宽度。其中，在第二电路区域XB的凸出区域，设置有第二移位寄存器单元GOAB的第一输入晶体管BT1和第二输入晶体管BT2；在第一电路区域XA远离显示区AA的一侧，设置有移位寄存器单元GOA的第一输入晶体管AT1和第二输入晶体管AT2。
其中，半导体层SEMI中设置的电极板包括第四底电极板CP4A、第一底电极板CP1A和第五顶电极板CP5A。在第四底电极板CP4A，具有用于与第四顶电极板CP4B通过过孔连接的第一底过孔区H1A。第一底电极板CP1A具有用于与第一顶电极板CP1B通过过孔连接的第一电容的第一电极板CP1LA；第五顶电极板CP5A具有用于与第五底电极板CP5B通 过过孔连接的第五电极板的第一突出部CP5LA。
其中，部分晶体管可以共漏极设置，例如第一输出晶体管的漏极BT3D的一部分可以复用为第二输出晶体管的漏极BT4D，第一输出晶体管的漏极AT3D的一部分可以复用为第二输出晶体管的漏极AT4D，第一输入晶体管的漏极BT1D和第二输入晶体管的漏极BT2D相互复用，第一输入晶体管的漏极AT1D和第二输入晶体管的漏极AT2D相互复用。
参见图6和图8，栅极层GT设置有各个晶体管的栅极，以及设置有电容的电极板和一些转接走线。参见图7和图8，半导体层SD设置有驱动走线、电极板和一些转接走线。
其中，参见图7，驱动走线包括位于第一电路区域XA和第二电路区域XB远离显示区AA一侧的第一低电平信号线VGLLA、复位控制线RSTL、高电平走线VGHL、第一扫描控制线CNL和第二扫描控制线CNBL。其中，第一低电平信号线VGLLA用于加载低电平信号VGL，复位控制线RSTL用于加载复位控制信号Rst，高电平走线VGHL用于加载高电平信号VGH，第一扫描控制线CNL用于加载第一扫描控制信号CN，第二扫描控制线CNBL用于加载第二扫描控制信号CNB。驱动走线还包括位于第一电路区域XA和第二电路区域XB靠近显示区AA一端的第一时钟走线CKL、第二时钟走线CKBL、第二低电平转接线VGLLB和触控控制线ENTL，其中，第一时钟走线CKL用于加载第一时钟信号CK，第二时钟走线CKBL用于加载第二时钟信号CKB，第二低电平转接线VGLLB用于加载低电平信号VGL，触控控制线ENTL用于加载触控控制信号ENT。
参见图5～图8，半导体层SD还设置有第五顶转接线TRB5；栅极层GT设置有第一低电平转接线VGLTA；第一低电平转接线VGLTA远离显示区AA的端部与第一低电平信号线VGLLA通过过孔连接，第一低电平转接线VGLTA靠近显示区AA的端部具有第三底过孔区H3A。第五顶转接线TRB5远离显示区AA的端部与复位晶体管的源极BT10S通过过孔连接，第五顶转接线TRB5靠近显示区AA的端部与位于半导体层SD的第四顶电极板CP4B连接。在第五顶转接线TRB5上，设置有具有第三顶过孔区H3B的膨胀部和与第一下拉晶体管的源极BT5S通过过孔连接的侧枝部；第三顶过孔区H3B与第三底过孔区H3A通过过孔连接。第四顶电极 板CP4B靠近第五底转接线TRA5的一端连接有第十二顶转接线TRB12，第四顶电极板CP4B靠近显示区AA的一端具有第一顶过孔区H1B，第四顶电极板CP4B靠近第一输出晶体管BT3的一侧连接有第十一顶转接线TRB11；其中，第十二顶转接线TRB12通过过孔与第一下拉控制晶体管的源极BT6S电连接，第十一顶转接线TRB11通过过孔与第二下拉晶体管的源极BT8S、第二输出晶体管的源极BT4S电连接。这样，在第二移位寄存器单元GOAB中，低电平信号VGL可以加载至复位晶体管的源极BT10S、第一下拉晶体管的源极BT5S、第一下拉控制晶体管的源极BT6S、第二下拉晶体管的源极BT8S和第二输出晶体管的源极BT4S，以及加载至第二电容的第一电极板CP3。其中，在第一电路区域XA中，半导体层SD设置有第十九顶转接线TRB19，第十九顶转接线TRB19与相邻的第二电路区域XB中的第四顶电极板CP4B电连接，且第十九顶转接线TRB19通过过孔与下拉控制晶体管的源极AT12S、第二输出晶体管的源极AT4S电连接。这样，低电平信号VGL也可以加载至第二输出晶体管的源极AT4S和下拉控制晶体管的源极AT12S。
参见图5～图8，半导体层SD设置有复位控制线RSTL，栅极层GT设置有复位转接线RSTT。其中，复位转接线RSTT远离显示区AA的一端通过过孔与复位控制线RSTL电连接，复位转接线RSTT靠近显示区AA的一端作为复位晶体管的栅极BT10G而与复位晶体管BT10A交叠设置。
参见图5～图8，半导体层SD设置有高电平走线VGHL，栅极层GT设置有高电平转接线VGHT。其中，高电平转接线VGHT远离显示区AA的一端通过过孔与高电平走线VGHL电连接，高电平转接线VGHT靠近显示区AA的一端作为使能晶体管的栅极BT9G而与使能晶体管BT9A交叠设置。
参见图5～图8，半导体层SD设置有第一扫描控制线CNL和第一顶转接线TRB1，栅极层GT设置有第一扫描控制转接线CNT。其中，第一扫描控制转接线CNT远离显示区AA的一端通过过孔与第一扫描控制线CNL电连接，第一扫描控制转接线CNT靠近显示区AA的一端与第一顶转接线TRB1远离显示区AA的一端通过过孔连接；第一顶转接线TRB1 向靠近显示区AA的方向延伸，且依次通过过孔与第一输入晶体管的源极BT1S、第一输入晶体管的源极AT1S电连接。
参见图5～图8，半导体层SD设置有与第二扫描控制线CNBL电连接的第二扫描控制转接线CNBT，第二扫描控制转接线CNBT沿行方向DH向显示区AA一侧延伸，且分别通过过孔与第二输入晶体管的源极BT2S、第二输入晶体管的源极AT2S电连接。
参见图5～图8，半导体层SD还设置有第七顶转接线TRB7、第九顶转接线TRB9、第十五顶转接线TRB15；其中，栅极层GT设置有第一时钟转接线CKBTA、第二时钟转接线CKBTB。第一时钟转接线CKBTA靠近显示区AA的一端通过过孔与第二时钟走线CKBL电连接，第一时钟转接线CKBTA远离显示区AA的一端通过过孔与第十五顶转接线TRB15靠近显示区AA的端部连接；第十五顶转接线TRB15与第一输出晶体管的源极AT3S通过过孔电连接。第二时钟转接线CKBTB靠近显示区AA的一端通过过孔与第二时钟走线CKBL电连接，第二时钟转接线CKBTB远离显示区AA的一端作为第二下拉控制晶体管的栅极BT7G而与第二下拉控制晶体管BT7A交叠。第二时钟转接线CKBTB具有第十二底过孔区H12A；第九顶转接线TRB9具有第十二顶过孔区H12B，第十二底过孔区H12A和第十二顶过孔区H12B相互交叠且通过过孔电连接。这样，第九顶转接线TRB9一端与第二时钟转接线CKBTB通过过孔电连接，另一端与第二下拉控制晶体管的源极BT7S通过过孔电连接。第七顶转接线TRB7与第一时钟走线CKL电连接，且向远离显示区AA的方向延伸，并与第一输出晶体管的源极BT3S通过过孔电连接。这样，该示例中的第二移位寄存器单元GOAB的第二下拉控制晶体管的源极BT7S能够加载第二时钟信号CKB，该示例中的第一移位寄存器单元GOAA的第一输出晶体管的源极AT3S能够加载第二时钟信号CKB，该示例中的第二移位寄存器单元GOAB的第一输出晶体管的源极BT3S能够加载第一时钟信号CK。
参见图5～图8，半导体层SD设置有第三顶转接线TRB3，第三顶转接线TRB3一端与第一输入晶体管的漏极BT1D通过过孔电连接，另一端具有第九顶过孔区H9B。其中，第三顶转接线TRB3设置有与使能晶体管的源极BT9S通过过孔电连接的侧枝部，且能够与复位晶体管的漏极 BT10D、第一下拉晶体管的漏极BT5D通过过孔电连接。栅极层GT中，第一下拉控制晶体管的栅极BT6G具有突出部，该突出部具有第九底过孔区H9A，第九底过孔区H9A与第九顶过孔区H9B通过过孔电连接。这样，第一输入晶体管的漏极BT1D作为上拉控制节点BPUCN的一部分，可以与使能晶体管的源极BT9S、复位晶体管的漏极BT10D、第一下拉晶体管的漏极BT5D、第一下拉控制晶体管的栅极BT6G电连接。
参见图5～图8，半导体层SD设置有第六顶转接线TRB6、第一顶电极板CP1B、第四顶转接线TRB4；栅极层GT设置有第一电容的第二电极板CP2、第一输出晶体管BT3A和第二输出线OUTLB；其中，第一电容的第二电极板CP2具有第七底过孔区H7A，且与第一输出晶体管的栅极BT3G电连接。第四顶转接线TRB4一端与使能晶体管的漏极BT9D通过过孔电连接，另一端具有第七顶过孔区H7B；第七顶过孔区H7B与第七底过孔区H7A通过过孔电连接。第六顶转接线TRB6与第一顶电极板CP1B电连接，且与第一输出晶体管的漏极BT3D电连接。第六顶转接线TRB6靠近显示区AA的端部设置有第十三顶过孔区H13B，第二输出线OUTLB远离显示区AA的端部具有第十三底过孔区H13A；第十一底过孔区H11A和第十一顶过孔区H11B相互交叠且通过过孔电连接。第六顶转接线TRB6具有膨大部，膨大部上设置有第十顶过孔区H10B；第二下拉晶体管的栅极BT8G具有突出部，突出部上述设置有第十底过孔区H10A；第十底过孔区H10A和第十顶过孔区H10B相互交叠且通过过孔电连接。
进一步的，第一底电极板CP1A具有第一电极板的第一突出部CL1LA，第一顶电极板CP1B具有第一电极板的第三突出部CP1LC；第一电极板的第三突出部CP1LC和第一电极板的第一突出部CL1LA相互交叠且通过过孔电连接。第一顶电极板CP1B具有第一电极板的第二突出部CP1LB，第一电极板的第二突出部CP1LB设置有第六顶过孔区H6B；栅极层GT设置有与第一输入晶体管的栅极AT1G连接的第四底转接线TRA4，第四底转接线TRA4的端部具有第六底过孔区H6A；第六底过孔区H6A和第六顶过孔区H6B相互交叠且通过过孔电连接。第一顶电极板CP1B具有第一电极板的第四突出部CP1LD，第一电极板的第二突出部CP1LB设置有第八顶过孔区H8B；栅极层GT设置有与第三底转接线TRA3，第三底转接 线TRA3一端连接上一级第一移位寄存器单元GOAA的第二输入晶体管的栅极AT2G，另一端具有第八底过孔区H8A；第八底过孔区H8A和第八顶过孔区H8B相互交叠且通过过孔电连接。
参见图5～图8，栅极层GT设置有第二电容的第一电极板CP3，一端与第一下拉晶体管的栅极BT5G连接，另一端与第二输出晶体管的栅极BT4G连接，且第二电容的第一电极板CP3具有第二底过孔区H2A；第二输出晶体管的栅极BT4G远离第二电容的第一电极板CP3的一端具有膨大部，膨大部上设置有第十一底过孔区H11A。半导体层SD设置有第八顶转接线TRB8和第十顶转接线TRB10。其中，第八顶转接线TRB8一端具有第二顶过孔区H2B，第二底过孔区H2A和第二顶过孔区H2B相互交叠且通过过孔电连接。第八顶转接线TRB8通过过孔与第二下拉晶体管的漏极BT8D、第一下拉控制晶体管的漏极BT6D电连接。第十顶转接线TRB10通过过孔与第二下拉控制晶体管的漏极BT7D电连接，且第十顶转接线TRB10具有第十一顶过孔区H11B，第十一底过孔区H11A和第十一顶过孔区H11B相互交叠且通过过孔电连接。其中，第四顶电极板CP4B具有第一顶过孔区H1B，第一底过孔区H1A和第一顶过孔区H1B相互交叠且通过过孔电连接。
参见图5～图8，半导体层SD设置有第五底电极板CP5B、第十六顶转接线TRB16和第十七顶转接线TRB17；第五底电极板CP5B具有第五电极板的第二突出部CP5LB，设置于半导体层SEMI的第五顶电极板CP5A具有第五电极板的第一突出部CP5LA；第五电极板的第一突出部CP5LA和第五电极板的第二突出部CP5LB相互交叠且通过过孔电连接。第十六顶转接线TRB16与第五底电极板CP5B电连接，且与第一输出晶体管的漏极AT3D的一部分电连接；第十七顶转接线TRB17与第五底电极板CP5B电连接，且与第一输出晶体管的漏极AT3D的其余部分电连接；第十七顶转接线TRB17还与第二输出晶体管的漏极AT4D电连接。栅极层GT设置有第一输出线OUTLA，第十七顶转接线TRB17靠近显示区AA的端部与第一输出线OUTLA远离显示区AA的端部通过过孔电连接。
参见图5～图8，半导体层SD设置有第十四顶转接线TRB14、第十八顶转接线TRB18，栅极层GT设置第六底转接线TRA6和第三电容的第二 电极板CP6。其中，第十四顶转接线TRB14靠近显示区AA的一端设置有第十六顶过孔区H16B，第三电容的第二电极板CP6设置有第十五底过孔区H16A；第十五底过孔区H16A和第十六顶过孔区H16B相互交叠且通过过孔电连接。第十四顶转接线TRB14远离显示区AA的端部通过过孔与第一输入晶体管的漏极AT1D电连接。第二输入晶体管的栅极AT2G具有突出部，该突出部设置有第十四底过孔区H14A；第二输出晶体管的栅极AT4G具有突出部，该突出部设置有第十五底过孔区H15A；第十八顶转接线TRB18的两端分别具有第十四顶过孔区H14B和第十五顶过孔区H15B，第十四底过孔区H14A和第十四顶过孔区H14B相互交叠且通过过孔电连接，第十五底过孔区H15A和第十五顶过孔区H15B相互交叠且通过过孔电连接。第六底转接线TRA6一端与第一输入晶体管的栅极AT1G电连接，另一端与下拉控制晶体管的栅极AT12G电连接。
参见图5～图8，半导体层SD设置有第二顶转接线TRB2，栅极层GT设置有第一底转接线TRA1；第一底转接线TRA1与第一输入晶体管的栅极BT1G电连接，且末端设置有第四底过孔区H4A；第二顶转接线TRB2跨移位寄存器单元组GOAS设置，其一端具有第四顶过孔区H4B，第四底过孔区H4A和第四顶过孔区H4B相互交叠且通过过孔电连接。第二顶转接线TRB2的另一端，与上一级第一移位寄存器单元GOAA的第五底电极板CP5B电连接。
参见图5～图8，栅极层GT设置有第二底转接线TRA2，第二底转接线TRA2一端与第二输入晶体管的栅极BT2G电连接，另一端具有第五底过孔区H5A；第二顶转接线TRB2具有第五顶过孔区H5B，第五底过孔区H5A和第五顶过孔区H5B相互交叠且通过过孔电连接。
参见图5～图8，半导体层SD还设置有第十三顶转接线TRB13和第二十顶转接线TRB20；栅极层GT还设置有第一触控转接线TSA和第二触控转接线TSB。第一触控转接线TSA通过过孔与触控控制线ENTL电连接，且与触控控制晶体管的栅极BT11G电连接；第二触控转接线TSB通过过孔与触控控制线ENTL电连接，且与触控控制晶体管的栅极AT11G电连接。第十三顶转接线TRB13通过过孔与第二输出线OUTLB电连接，且与触控控制晶体管的漏极BT11D电连接，触控控制晶体管的源极BT11S 通过过孔与第二低电平转接线VGLLB电连接。第二十顶转接线TRB20通过过孔与第一输出线OUTLA电连接，且与触控控制晶体管的漏极AT11D电连接，触控控制晶体管的源极AT11S通过过孔与第二低电平转接线VGLLB电连接。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (21)

  1. 一种显示面板，包括显示区和围绕所述显示区的外围区；所述外围区中设置有栅极驱动电路；所述栅极驱动电路包括依次级联的多个移位寄存器单元；
    其中，所述移位寄存器单元包括第一移位寄存器单元和第二移位寄存器单元，所述第一移位寄存器单元和所述第二移位寄存器单元相互间隔；所述第一移位寄存器单元的晶体管数量小于所述第二移位寄存器单元的晶体管数量。
  2. 根据权利要求1所述的显示面板，其中，所述显示区设置有多个像素驱动电路；至少部分所述第一移位寄存器单元输出的信号和至少部分所述第二移位寄存器单元输出的信号用于驱动所述像素驱动电路。
  3. 根据权利要求1所述的显示面板，其中，所述栅极驱动电路设于所述显示区在行方向的一侧；
    所述外围区设置有用于布设所述第一移位寄存器单元的第一电路区域和用于布设所述第二移位寄存器单元的第二电路区域；
    其中，所述第二电路区域的部分区域位于所述第一电路区域远离所述显示区的一侧。
  4. 根据权利要求3所述的显示面板，其中，所述栅极驱动电路包括多个移位寄存器单元组，每个所述移位寄存器单元组包括相邻的一个第一移位寄存器单元和一个第二移位寄存器单元；同一所述移位寄存器单元组中，第一移位寄存器单元对应的第一电路区域和第二移位寄存器单元对应的第二电路区域互补成矩形。
  5. 根据权利要求4所述的显示面板，其中，所述显示面板设置有与所述栅极驱动电路对应的内走线组和外走线组，所述内走线组和所述外走线组中的驱动走线均用于驱动所述栅极驱动电路，且所述内走线组位于所述外走线组靠近所述显示区的一侧；
    所述移位寄存器单元组与所述外走线组的任意一个驱动走线之间通过最多一个转接线电连接。
  6. 根据权利要求5所述的显示面板，其中，所述外走线组包括沿列方向延伸的第一低电平信号线、复位控制线、第一扫描控制线和第二扫 描控制线；
    分别位于两个不同的移位寄存器单元组中且相邻的第一移位寄存器单元和第二移位寄存器单元，与同一所述第一低电平信号线电连接；
    所述复位控制线用于向所述移位寄存器单元组提供复位控制信号；
    所述第一扫描控制线用于向所述移位寄存器单元组提供第一扫描控制信号；所述第二扫描控制线拥有向所述移位寄存器单元组提供第二扫描控制信号；所述第一扫描控制信号和所述第二扫描控制信号为反相信号。
  7. 根据权利要求6所述的显示面板，其中，所述第一移位寄存器单元包括第一输入晶体管和第二输入晶体管；所述第二移位寄存器单元包括第一输入晶体管和第二输入晶体管；所述第一输入晶体管位于所述第一输入晶体管与所述外走线组之间，且沿行方向排列；所述第二输入晶体管位于所述第二输入晶体管与所述外走线组之间，且沿行方向排列；
    所述第一输入晶体管的源极和所述第一输入晶体管的源极通过同一导电结构电连接至所述第一扫描控制线；
    所述第二输入晶体管的源极和所述第二输入晶体管的源极通过同一导电结构电连接至所述第二扫描控制线。
  8. 根据权利要求1所述的显示面板，其中，所述第一移位寄存器单元包括：
    第一输入晶体管，所述第一输入晶体管的源极用于加载第一扫描控制信号，所述第一输入晶体管的漏极与上拉节点电连接，所述第一输入晶体管的栅极用于与上一级移位寄存器单元的输出端电连接；
    第二输入晶体管，所述第二输入晶体管的源极用于加载第二扫描控制信号，所述第二输入晶体管的漏极与所述上拉节点电连接，所述第二输入晶体管的栅极与下拉节点电连接，且用于与下一级移位寄存器单元的输出端电连接；所述第一扫描控制信号和所述第二扫描控制信号为反相信号；
    第三电容，具有第三电容的第一电极板和第三电容的第二电极板；所述第三电容的第二电极板与所述上拉节点电连接，所述第三电容的第一电极板与所述第一移位寄存器单元的输出端电连接；
    第一输出晶体管，所述第一输出晶体管的漏极与第三电容的第一电极板电连接，所述第一输出晶体管的栅极与所述上拉节点电连接；所述第一移位寄存器单元的第一输出晶体管的源极和相邻的所述移位寄存器单元的第一输出晶体管的源极中，一个用于加载第一时钟信号且另一个用于加载第二时钟信号；所述第一时钟信号和所述第二时钟信号为反相信号；
    第二输出晶体管，所述第二输出晶体管的源极用于加载低电平信号，所述第二输出晶体管的漏极与所述第三电容的第一电极板电连接，所述第二输出晶体管的栅极与所述下拉节点电连接；
    下拉控制晶体管，所述下拉控制晶体管的源极用于加载所述低电平信号，所述下拉控制晶体管的漏极与所述下拉节点电连接，所述下拉控制晶体管的栅极与所述第一输入晶体管的栅极电连接。
  9. 根据权利要求8所述的显示面板，其中，所述第一输入晶体管包括串联的两个亚晶体管，两个亚晶体管共栅极；
    所述第二输入晶体管包括串联的两个亚晶体管，两个亚晶体管共栅极。
  10. 根据权利要求8所述的显示面板，其中，所述第一移位寄存器单元还包括：
    触控控制晶体管，所述触控控制晶体管的源极用于加载所述低电平信号，所述触控控制晶体管的漏极与所述第三电容的第一电极板电连接，所述触控控制晶体管的栅极用于加载触控控制信号。
  11. 根据权利要求1所述的显示面板，其中，所述第二移位寄存器单元包括：
    第一输入晶体管，所述第一输入晶体管的源极用于加载第一扫描控制信号，所述第一输入晶体管的漏极用于与上拉控制节点电连接，所述第一输入晶体管的栅极用于与上一级所述移位寄存器单元的输出端电连接；
    第二输入晶体管，所述第二输入晶体管的源极用于加载第二扫描控制信号，所述第二输入晶体管的漏极用于与所述上拉控制节点电连接，所述第二输入晶体管的栅极用于与下一级所述移位寄存器单元的输出端 电连接；所述第一扫描控制信号和所述第二扫描控制信号为反相信号；
    第一电容，包括第一电容的第一电极板和第一电容的第二电极板；所述第一电容的第一电极板与所述第二移位寄存器单元的输出端电连接，所述第一电容的第二电极板与上拉节点电连接；
    第二电容，包括第二电容的第一电极板和第二电容的第二电极板；所述第二电容的第一电极板与下拉节点电连接，所述第二电容的第二电极板用于加载低电平信号；
    第一输出晶体管，所述第一输出晶体管的漏极与所述上拉节点电连接，所述第一输出晶体管的漏极与所述第一电容的第一电极板电连接；所述第二移位寄存器单元的第一输出晶体管的源极和相邻的所述移位寄存器单元的第一输出晶体管的源极中，一个用于加载第一时钟信号且另一个用于加载第二时钟信号；所述第一时钟信号和所述第二时钟信号为反相信号；
    第二输出晶体管，所述第二输出晶体管的源极用于加载所述低电平信号，所述第二输出晶体管的漏极与所述第一电容的第一电极板电连接，所述第二输出晶体管的栅极与所述下拉节点电连接；
    第一下拉晶体管，所述第一下拉晶体管的源极用于加载所述低电平信号，所述第一下拉晶体管的漏极与所述上拉控制节点电连接，所述第一下拉晶体管的栅极与所述下拉节点电连接；
    第一下拉控制晶体管，所述第一下拉控制晶体管的源极用于加载所述低电平信号，所述第一下拉控制晶体管的漏极与所述下拉节点电连接，所述第一下拉控制晶体管的栅极与所述上拉控制节点电连接；
    第二下拉控制晶体管，所述第二下拉控制晶体管的漏极与所述下拉节点电连接，所述第二下拉控制晶体管的栅极与所述第二下拉控制晶体管的源极电连接；所述第二下拉控制晶体管的源极和所述第一输出晶体管的源极中的一个用于加载所述第一时钟信号且另一个用于加载所述第二时钟信号；
    第二下拉晶体管，所述第二下拉晶体管的源极用于加载所述低电平信号，所述第二下拉晶体管的漏极与所述下拉节点电连接，所述第二下拉晶体管的栅极与所述第一电容的第一电极板电连接；
    复位晶体管，所述复位晶体管的源极用于加载所述低电平信号，所述复位晶体管的漏极与所述上拉控制节点电连接，所述复位晶体管的栅极用于加载复位控制信号；
    所述上拉控制节点和所述上拉节点电连接。
  12. 根据权利要求11所述的显示面板，其中，所述第一输入晶体管包括串联的两个亚晶体管，两个亚晶体管共栅极；
    所述第二输入晶体管包括串联的两个亚晶体管，两个亚晶体管共栅极。
  13. 根据权利要求11所述的显示面板，其中，所述第二移位寄存器单元还包括使能晶体管和触控控制晶体管；所述上拉控制节点和所述上拉节点通过所述使能晶体管电连接；
    其中，所述使能晶体管的源极与所述上拉控制节点电连接，所述使能晶体管的漏极与所述上拉节点电连接，所述使能晶体管的栅极用于加载高电平信号；所述触控控制晶体管的源极与所述低电平信号电连接，所述触控控制晶体管的漏极与所述第一电容的第一电极板电连接，所述触控控制晶体管的栅极用于加载触控控制信号；所述触控控制信号与所述高电平信号为反相信号。
  14. 根据权利要求1～13任意一项所述的显示面板，其中，所述显示面板包括两个所述栅极驱动电路，两个所述栅极驱动电路分别位于所述显示区的两侧；
    任意一行所述像素驱动电路被两个所述栅极驱动电路同时驱动。
  15. 根据权利要求14所述的显示面板，其中，任意一行所述像素驱动电路，被一个所述栅极驱动电路的第一移位寄存器单元驱动，且被另一个所述栅极驱动电路的第二移位寄存器单元驱动。
  16. 一种栅极驱动电路，包括依次级联的多个移位寄存器单元；其中，所述移位寄存器单元包括第一移位寄存器单元和第二移位寄存器单元，所述第一移位寄存器单元和所述第二移位寄存器单元相互间隔；所述第一移位寄存器单元的晶体管数量小于所述第二移位寄存器单元的晶体管数量。
  17. 根据权利要求16所述的栅极驱动电路，其中，每个所述移位寄 存器单元用于驱动一行像素驱动电路。
  18. 根据权利要求16所述的栅极驱动电路，其中，
    所述第一移位寄存器单元包括：
    第一输入晶体管，所述第一输入晶体管的源极用于加载第一扫描控制信号，所述第一输入晶体管的漏极与上拉节点电连接，所述第一输入晶体管的栅极用于与上一级移位寄存器单元的输出端电连接；
    第二输入晶体管，所述第二输入晶体管的源极用于加载第二扫描控制信号，所述第二输入晶体管的漏极与所述上拉节点电连接，所述第二输入晶体管的栅极与下拉节点电连接，且用于与下一级移位寄存器单元的输出端电连接；所述第一扫描控制信号和所述第二扫描控制信号为反相信号；
    第三电容，具有第三电容的第一电极板和第三电容的第二电极板；所述第三电容的第二电极板与所述上拉节点电连接，所述第三电容的第一电极板与所述第一移位寄存器单元的输出端电连接；
    第一输出晶体管，所述第一输出晶体管的漏极与第三电容的第一电极板电连接，所述第一输出晶体管的栅极与所述上拉节点电连接；所述第一移位寄存器单元的第一输出晶体管的源极和相邻的所述移位寄存器单元的第一输出晶体管的源极中，一个用于加载第一时钟信号且另一个用于加载第二时钟信号；所述第一时钟信号和所述第二时钟信号为反相信号；
    第二输出晶体管，所述第二输出晶体管的源极用于加载低电平信号，所述第二输出晶体管的漏极与所述第三电容的第一电极板电连接，所述第二输出晶体管的栅极与所述下拉节点电连接；
    下拉控制晶体管，所述下拉控制晶体管的源极用于加载所述低电平信号，所述下拉控制晶体管的漏极与所述下拉节点电连接，所述下拉控制晶体管的栅极与所述第一输入晶体管的栅极电连接。
  19. 根据权利要求18所述的栅极驱动电路，其中，所述第一输入晶体管包括串联的两个亚晶体管，两个亚晶体管共栅极；
    所述第二输入晶体管包括串联的两个亚晶体管，两个亚晶体管共栅极。
  20. 根据权利要求16所述的栅极驱动电路，其中，所述第二移位寄存器单元包括：
    第一输入晶体管，所述第一输入晶体管的源极用于加载第一扫描控制信号，所述第一输入晶体管的漏极用于与上拉控制节点电连接，所述第一输入晶体管的栅极用于与上一级所述移位寄存器单元的输出端电连接；
    第二输入晶体管，所述第二输入晶体管的源极用于加载第二扫描控制信号，所述第二输入晶体管的漏极用于与所述上拉控制节点电连接，所述第二输入晶体管的栅极用于与下一级所述移位寄存器单元的输出端电连接；所述第一扫描控制信号和所述第二扫描控制信号为反相信号；
    第一电容，包括第一电容的第一电极板和第一电容的第二电极板；所述第一电容的第一电极板与所述第二移位寄存器单元的输出端电连接，所述第一电容的第二电极板与上拉节点电连接；
    第二电容，包括第二电容的第一电极板和第二电容的第二电极板；所述第二电容的第一电极板与下拉节点电连接，所述第二电容的第二电极板用于加载低电平信号；
    第一输出晶体管，所述第一输出晶体管的漏极与所述上拉节点电连接，所述第一输出晶体管的漏极与所述第一电容的第一电极板电连接；所述第二移位寄存器单元的第一输出晶体管的源极和相邻的所述移位寄存器单元的第一输出晶体管的源极中，一个用于加载第一时钟信号且另一个用于加载第二时钟信号；所述第一时钟信号和所述第二时钟信号为反相信号；
    第二输出晶体管，所述第二输出晶体管的源极用于加载所述低电平信号，所述第二输出晶体管的漏极与所述第一电容的第一电极板电连接，所述第二输出晶体管的栅极与所述下拉节点电连接；
    第一下拉晶体管，所述第一下拉晶体管的源极用于加载所述低电平信号，所述第一下拉晶体管的漏极与所述上拉控制节点电连接，所述第一下拉晶体管的栅极与所述下拉节点电连接；
    第一下拉控制晶体管，所述第一下拉控制晶体管的源极用于加载所述低电平信号，所述第一下拉控制晶体管的漏极与所述下拉节点电连接， 所述第一下拉控制晶体管的栅极与所述上拉控制节点电连接；
    第二下拉控制晶体管，所述第二下拉控制晶体管的漏极与所述下拉节点电连接，所述第二下拉控制晶体管的栅极与所述第二下拉控制晶体管的源极电连接；所述第二下拉控制晶体管的源极和所述第一输出晶体管的源极中的一个用于加载所述第一时钟信号且另一个用于加载所述第二时钟信号；
    第二下拉晶体管，所述第二下拉晶体管的源极用于加载所述低电平信号，所述第二下拉晶体管的漏极与所述下拉节点电连接，所述第二下拉晶体管的栅极与所述第一电容的第一电极板电连接；
    复位晶体管，所述复位晶体管的源极用于加载所述低电平信号，所述复位晶体管的漏极与所述上拉控制节点电连接，所述复位晶体管的栅极用于加载复位控制信号；
    所述上拉控制节点和所述上拉节点电连接。
  21. 根据权利要求20所述的栅极驱动电路，其中，所述第一输入晶体管包括串联的两个亚晶体管，两个亚晶体管共栅极；
    所述第二输入晶体管包括串联的两个亚晶体管，两个亚晶体管共栅极。
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Families Citing this family (4)

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Publication number Priority date Publication date Assignee Title
CN116524857B (zh) * 2023-04-27 2025-11-14 武汉天马微电子有限公司 显示面板及显示装置
CN116597763B (zh) * 2023-05-22 2025-12-23 昆山龙腾光电股份有限公司 显示面板及显示装置
CN117456914A (zh) * 2023-07-12 2024-01-26 武汉华星光电半导体显示技术有限公司 显示装置
TWI890249B (zh) * 2023-12-28 2025-07-11 瀚宇彩晶股份有限公司 閘極驅動電路和顯示裝置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110002437A1 (en) * 2009-07-01 2011-01-06 Au Optronics Corp. Shift registers
CN103400559A (zh) * 2013-07-31 2013-11-20 京东方科技集团股份有限公司 显示装置
CN106448595A (zh) * 2016-10-24 2017-02-22 南京华东电子信息科技股份有限公司 一种高可靠性的栅极驱动电路
CN106548740A (zh) * 2016-12-02 2017-03-29 京东方科技集团股份有限公司 移位寄存电路及其驱动方法、栅极驱动电路及显示装置
CN108806581A (zh) * 2018-06-29 2018-11-13 厦门天马微电子有限公司 扫描驱动电路和显示面板
CN108877636A (zh) * 2018-08-29 2018-11-23 合肥鑫晟光电科技有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN109147711A (zh) * 2018-11-27 2019-01-04 南京中电熊猫平板显示科技有限公司 一种双边驱动栅极扫描电路及显示装置
CN112735315A (zh) * 2020-12-31 2021-04-30 厦门天马微电子有限公司 显示面板及显示装置

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101166819B1 (ko) 2005-06-30 2012-07-19 엘지디스플레이 주식회사 쉬프트 레지스터
CN202084307U (zh) 2011-05-11 2011-12-21 京东方科技集团股份有限公司 一种移位寄存器及显示装置
TWI493872B (zh) 2012-07-05 2015-07-21 Au Optronics Corp 移位暫存器
CN103985363B (zh) 2013-12-05 2017-03-15 上海中航光电子有限公司 栅极驱动电路、tft阵列基板、显示面板及显示装置
JP6601667B2 (ja) 2014-12-03 2019-11-06 Ｔｉａｎｍａ Ｊａｐａｎ株式会社 シフトレジスタ回路及びゲートドライバ並びに表示装置
CN104766587B (zh) 2015-04-30 2016-03-02 京东方科技集团股份有限公司 扫描驱动电路及其驱动方法、阵列基板、显示装置
KR102420489B1 (ko) 2015-10-27 2022-07-14 엘지디스플레이 주식회사 표시장치
CN105244005B (zh) 2015-11-24 2018-01-09 厦门天马微电子有限公司 阵列基板、触控显示装置及其驱动方法
KR102557841B1 (ko) * 2016-04-29 2023-07-24 엘지디스플레이 주식회사 게이트 구동회로와 이를 이용한 표시장치
US11006372B2 (en) 2016-07-12 2021-05-11 Sony Corporation Management server, communication device, method and recording medium
CN106157912B (zh) * 2016-08-30 2018-10-30 合肥京东方光电科技有限公司 移位寄存器单元、其驱动方法、栅极驱动电路及显示装置
CN106228942B (zh) 2016-09-23 2018-05-15 南京华东电子信息科技股份有限公司 用于液晶显示器的栅极驱动电路
WO2018235130A1 (ja) 2017-06-19 2018-12-27 シャープ株式会社 表示装置およびその駆動方法
CN107452350B (zh) * 2017-08-17 2019-12-03 京东方科技集团股份有限公司 栅极驱动装置和显示面板
KR102548841B1 (ko) 2017-12-29 2023-06-27 엘지디스플레이 주식회사 스캔구동회로 및 이를 포함하는 표시장치
CN108230981B (zh) 2018-01-19 2021-06-01 厦门天马微电子有限公司 一种显示面板和显示装置
CN109872636B (zh) 2019-03-29 2021-08-06 武汉天马微电子有限公司 显示面板及显示装置
CN109979374A (zh) * 2019-05-13 2019-07-05 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN110322826B (zh) 2019-07-11 2021-12-31 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路、显示装置
CN112309335B (zh) 2019-07-31 2021-10-08 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN110415664B (zh) * 2019-08-01 2021-10-08 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN110619838B (zh) 2019-11-04 2021-12-21 京东方科技集团股份有限公司 移位寄存器单元电路及驱动方法、栅极驱动器和显示装置
KR20260014041A (ko) 2019-11-20 2026-01-29 보에 테크놀로지 그룹 컴퍼니 리미티드 디스플레이 기판 및 이의 제조 방법, 디스플레이 장치
CN111243543B (zh) 2020-03-05 2021-07-23 苏州华星光电技术有限公司 Goa电路、tft基板、显示装置及电子设备
CN111415695B (zh) 2020-03-16 2022-06-21 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及显示控制方法
CN111653228A (zh) 2020-06-17 2020-09-11 京东方科技集团股份有限公司 移位寄存单元的驱动方法、栅极驱动电路和显示装置
KR102912391B1 (ko) * 2020-11-19 2026-01-15 엘지디스플레이 주식회사 표시장치와 그 구동 방법
CN115083324A (zh) * 2021-03-11 2022-09-20 联咏科技股份有限公司 时序控制装置以及其控制方法
CN114005411A (zh) * 2021-11-05 2022-02-01 武汉天马微电子有限公司 阵列基板、显示面板及显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110002437A1 (en) * 2009-07-01 2011-01-06 Au Optronics Corp. Shift registers
CN103400559A (zh) * 2013-07-31 2013-11-20 京东方科技集团股份有限公司 显示装置
CN106448595A (zh) * 2016-10-24 2017-02-22 南京华东电子信息科技股份有限公司 一种高可靠性的栅极驱动电路
CN106548740A (zh) * 2016-12-02 2017-03-29 京东方科技集团股份有限公司 移位寄存电路及其驱动方法、栅极驱动电路及显示装置
CN108806581A (zh) * 2018-06-29 2018-11-13 厦门天马微电子有限公司 扫描驱动电路和显示面板
CN108877636A (zh) * 2018-08-29 2018-11-23 合肥鑫晟光电科技有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN109147711A (zh) * 2018-11-27 2019-01-04 南京中电熊猫平板显示科技有限公司 一种双边驱动栅极扫描电路及显示装置
CN112735315A (zh) * 2020-12-31 2021-04-30 厦门天马微电子有限公司 显示面板及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4425469A4 *

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