WO2024001924A1 - 温度传感器、温度传感器封装方法及温度测量方法 - Google Patents

温度传感器、温度传感器封装方法及温度测量方法 Download PDF

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Publication number
WO2024001924A1
WO2024001924A1 PCT/CN2023/101903 CN2023101903W WO2024001924A1 WO 2024001924 A1 WO2024001924 A1 WO 2024001924A1 CN 2023101903 W CN2023101903 W CN 2023101903W WO 2024001924 A1 WO2024001924 A1 WO 2024001924A1
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Prior art keywords
thermistor
temperature sensor
diode
temperature
layer
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PCT/CN2023/101903
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English (en)
French (fr)
Inventor
孙钮一
杨丹
梅娜
孙拓北
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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Priority to EP23830103.0A priority Critical patent/EP4549898A4/en
Priority to US18/875,523 priority patent/US20250383242A1/en
Publication of WO2024001924A1 publication Critical patent/WO2024001924A1/zh
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
    • G01K7/16—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements
    • G01K7/22—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a non-linear resistance, e.g. thermistor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
    • G01K7/16—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements
    • G01K7/22—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a non-linear resistance, e.g. thermistor
    • G01K7/24—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a non-linear resistance, e.g. thermistor in a specially-adapted circuit, e.g. bridge circuit
    • G01K7/25—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a non-linear resistance, e.g. thermistor in a specially-adapted circuit, e.g. bridge circuit for modifying the output characteristic, e.g. linearising

Definitions

  • Embodiments of the present disclosure relate to the field of electronic circuit technology, and specifically, to a temperature sensor, a temperature sensor packaging method, and a temperature measurement method.
  • Embodiments of the present disclosure provide a temperature sensor, a temperature sensor packaging method and a temperature measurement method to at least solve the parasitic problem existing in the technical solution of inferring the local temperature of the system based on the resistance value of the thermistor RT .
  • a temperature sensor including: a first thermistor, a second thermistor connected in parallel with the first thermistor, and a third thermistor connected in series with the first thermistor.
  • the first diode and the second diode are two adjacent diodes with the same selection but opposite polarity.
  • a temperature sensor packaging method is provided, which is applied to the above temperature sensor, including: forming a first thermistor, a second thermistor, and a third thermistor on a silicon wafer chip through a diffusion process. a diode and a second diode, and the first thermistor, the second thermistor, the first diode and the second diode are interconnected by metal on the silicon wafer chip so as to The temperature sensor is formed on the silicon wafer chip.
  • a packaging method for a temperature sensor is also provided, which is applied to the above-mentioned temperature sensor and includes: embedding a first thermistor, a second thermistor, and a first diode. tube and the second diode is buried into the buried layer of the substrate, or set the first thermistor, the second thermistor, the first diode and the second diode on the substrate through surface mounting, wherein the first thermal resistor The sensitive resistor, the second thermistor, the first diode and the second diode are discrete devices.
  • a temperature sensor packaging method is also provided, which is applied to the above-mentioned temperature sensor, including: arranging multiple temperature sensors in different system levels of the stacked packaging structure, wherein, the The temperature sensor is at the wafer level or the substrate level; the ports of each temperature sensor are uniformly led to the highest level packaging port through internal interconnection for multi-layer parallel testing.
  • a temperature measurement method including: changing the voltage polarity between two ports of the temperature sensor, and measuring the temperature sensor before and after the voltage polarity change.
  • the resistance after the voltage polarity is changed; obtain the difference ⁇ R between the first thermistor and the second thermistor in the temperature sensor through the resistance obtained by two measurements, and obtain the temperature sensor based on the following formula Detected temperature T:
  • ⁇ 0 is the low temperature resistivity of the first thermistor or the second thermistor
  • ⁇ is the temperature coefficient of the first thermistor or the second thermistor
  • L 1 is the first thermistor.
  • the length, L 2 is the length of the second thermistor
  • S 1 is the cross-sectional area of the first thermistor
  • S 2 is the cross-sectional area of the second thermistor.
  • Figure 1 is a schematic diagram of an abstract two-port pure resistor network in the related art
  • Figure 2 is a schematic diagram of a temperature sensor according to an embodiment of the present disclosure
  • Figure 3 is a flow chart of a temperature sensor packaging method according to an embodiment of the present disclosure
  • Figure 4 is a flow chart of a temperature sensor packaging method according to another embodiment of the present disclosure.
  • Figure 5 is a flow chart of a temperature sensor packaging method according to yet another embodiment of the present disclosure.
  • Figure 6 is a flow chart of a temperature measurement method according to an embodiment of the present disclosure.
  • Figure 7 is a schematic diagram of diode characteristics and equivalent circuit in related technology
  • Figure 8 is a schematic diagram of a core circuit of a temperature sensor according to an embodiment of the present disclosure.
  • Figure 9 is a schematic diagram of the temperature measurement and calibration process of a temperature sensor according to an embodiment of the present disclosure.
  • Figure 10 is a schematic diagram of a wafer-level application of a temperature sensor according to an embodiment of the present disclosure
  • Figure 11 is a schematic diagram of a substrate level application of a temperature sensor according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of the application of a temperature sensor on an advanced packaging structure according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a temperature sensor according to an embodiment of the present disclosure.
  • the temperature sensor includes: a first thermistor. (101), a second thermistor (102) connected in parallel with the first thermistor (101), and in series with the first thermistor (101) The first diode (103), and the second diode (104) connected in series with the second thermistor (102), wherein the first thermistor (101) and the second thermistor (102)
  • the thermistor (102) is two adjacent thermistors with the same material and process but different geometric dimensions.
  • the first diode (103) and the second diode (104) are two options. Adjacent diodes of the same type but opposite polarity.
  • the first thermistor (101) and the second thermistor (102) are formed by the metal interconnection layer. Made of metal interconnect lines.
  • the first thermistor (101) and the second thermistor (102) are polysilicon resistors.
  • the first diode (103) and the second diode (104) are discrete devices or integrated devices.
  • the spacing between the first thermistor (101) and the second thermistor (102), and the spacing between the first diode (103) and the second diode (104) is determined by the manufacturing process used; for example, in this embodiment, between the first thermistor (101) and the second thermistor (102), and between the first diode (103) and the second thermistor (102).
  • the optimal spacing between the diodes (104) is the minimum spacing allowed by the rules of the manufacturing process used.
  • a new resistance-based temperature sensor based on a diode/resistor hybrid circuit is built using the one-way conduction characteristics of the diode. Then, by changing the port voltage polarity of the new resistance-based temperature sensor, the parasitic resistance part of the circuit is controlled. deduct. Therefore, the parasitic problem existing in the technical solution of inferring the local temperature of the system based on the resistance value of the thermistor RT can be solved, and the accuracy of temperature detection at the detection location can be improved.
  • Embodiments of the present disclosure also provide a packaging method for the temperature sensor in one or more of the above embodiments.
  • Figure 3 is a flow chart of a temperature sensor packaging method according to an embodiment of the present disclosure. As shown in Figure 3, The process includes the following steps:
  • Step S302 forming the first thermistor, the second thermistor, the first diode and the second diode on the silicon wafer chip through a diffusion process
  • Step S304 interconnect the first thermistor, the second thermistor, the first diode and the second diode using metal on the silicon wafer chip to form a temperature sensor on the silicon wafer chip.
  • the packaging method further includes: in the case where the first thermistor and the second thermistor are polysilicon resistors, passing the temperature sensor through the through hole and the metal interconnect layer on the silicon wafer chip Take out the silicon wafer chip.
  • the packaging method further includes electroplating the first thermistor and the second thermistor onto the silicon wafer chip.
  • FIG. 4 is a flow chart of a temperature sensor packaging method according to another embodiment of the present disclosure. As shown in Figure 4, the process includes the following steps:
  • Step S402 bury the first thermistor, the second thermistor, the first diode and the second diode in the buried layer of the substrate by burying them, or set them on the substrate by surface mounting.
  • the first thermistor, the second thermistor, the first diode and the second diode, wherein the first thermistor, the second thermistor, the first diode and the second diode Diodes are discrete devices.
  • the first thermistor and the second thermistor are formed from metal interconnect lines of the detection layer of the substrate.
  • FIG. 5 is a flow chart of a temperature sensor packaging method according to another embodiment of the present disclosure. As shown in Figure 5, the process includes the following steps:
  • Step S502 Arrange multiple temperature sensors in different system levels of the stacked packaging structure, where the temperature sensors are at the wafer level or substrate level;
  • Step S504 The ports of each temperature sensor are uniformly led to the highest-level packaging port through internal interconnection for multi-layer parallel testing.
  • uniformly leading the ports of each temperature sensor to the highest-level packaging port through internal interconnection includes: after interconnecting the ports of each temperature sensor through the The bump (bump) layer, interposer layer, IC substrate and BGAball (solder ball array package) layer of the stacked package structure are led out, or each of the temperature sensors is led out to the stacked package through independent interconnection paths.
  • the topmost output layer of the structure includes: after interconnecting the ports of each temperature sensor through the The bump (bump) layer, interposer layer, IC substrate and BGAball (solder ball array package) layer of the stacked package structure are led out, or each of the temperature sensors is led out to the stacked package through independent interconnection paths.
  • the topmost output layer of the structure includes: after interconnecting the ports of each temperature sensor through the The bump (bump) layer, interposer layer, IC substrate and BGAball (solder ball array package) layer of the stacked package structure are led out, or each of the temperature sensors is led out to the stacked package through independent interconnection
  • FIG. 6 is a flow chart of the temperature measurement method according to the embodiment of the present disclosure. As shown in Figure 6, the process includes the following steps :
  • Step S602 change the voltage polarity between the two ports of the temperature sensor, and measure the resistance of the temperature sensor before the voltage polarity is changed and after the voltage polarity is changed;
  • Step S604 obtain the difference ⁇ R between the first thermistor and the second thermistor in the temperature sensor through the resistance obtained by the two measurements, and obtain the temperature T detected by the temperature sensor based on the following formula (1):
  • ⁇ 0 is the low-temperature resistivity of the first thermistor or the second thermistor
  • ⁇ is the temperature coefficient of the first thermistor or the second thermistor
  • L 1 is the length of the first thermistor
  • L 2 is the length of the second thermistor
  • S 1 is the cross-sectional area of the first thermistor
  • S 2 is the cross-sectional area of the second thermistor.
  • the temperature flow measurement method further includes: setting a plurality of different ambient temperatures where the temperature sensor is located; and determining the plurality of different ambient temperatures by changing the voltage polarity between two ports of the temperature sensor. Multiple differences between the first thermistor and the second thermistor at different ambient temperatures, and at least one of the following parameters is performed based on the linear regression relationship between the multiple differences and multiple different ambient temperatures. Verification: ⁇ 0 , ⁇ , L 1 , L 2 , S 1 and S 2 .
  • the embodiment of the present disclosure proposes a temperature sensor design based on the resistance temperature effect and immune to interconnect parasitics, and provides relevant circuit analysis, testing principles and processes of the temperature sensor, as well as the use of the temperature sensor in various electronic systems. applications in.
  • the circuit design of the parasitic immunity temperature sensor in this embodiment is as follows: using the one-way conduction characteristics of the diode, a new resistance-based temperature sensor based on a diode/resistor hybrid circuit is built. In the process of measuring temperature, by changing the port voltage polarity of the temperature sensor, the change in resistance difference ⁇ R between two adjacent thermistors of the same type but with different geometric sizes can be obtained, so that the circuit can be modified By deducting the parasitic resistance part, the temperature at the detection location can be accurately detected.
  • adjacent locations can ensure that the local temperatures of the two thermistors are the same as much as possible, homogeneity ensures that the resistivity and temperature coefficient of the two thermistors are the same, and different geometric sizes mean that the resistance values of the two thermistors are different.
  • FIG 7 is a schematic diagram of diode characteristics and equivalent circuit in related technology.
  • Rs and Rp are the series and parallel resistances of the diode respectively. Generally, Rs is much smaller than Rp.
  • the IV characteristic corresponds to the Rp-dominated (Rp-controlled) region in Figure 7(b), and the equivalent circuit can be approximated as shown in Figure 7(c) I It is the series connection of Rs and Rp.
  • the IV characteristic of the Rp-dominated area is generally expressed as current cutoff; if the external voltage V is greater than the turn-on voltage Vt of the diode, The ideal diode in Figure 7(a) is short-circuited thereby bypassing Rp. At this time, the IV characteristics are shown in the Rs-dominated (Rs-controlled) area in Figure 7(b), and the resistance value is shown in Figure 7(c) II Shown is the resistance characteristic of Rs, which can be approximated as a pure resistor circuit with extremely small resistance.
  • FIG 8 is a schematic diagram of the core circuit of a temperature sensor according to an embodiment of the present disclosure.
  • the temperature sensor is composed of two thermistors R1 and R2 and two diodes D1 and D2 connected in series and parallel, where , Rc is the lumped parasitic resistance of other interconnections and components other than the sensor, D1 and D2 are two diodes with opposite polarity and adjacent positions.
  • Rc is the lumped parasitic resistance of other interconnections and components other than the sensor
  • D1 and D2 are two diodes with opposite polarity and adjacent positions.
  • the materials, manufacturing processes and geometric dimensions must be as consistent as possible; and R1 and R2 are respectively two adjacent thermistors with the same material and process (that is, the same ⁇ 0 and ⁇ ), but with different geometric sizes. For the convenience of description, it is assumed that R1>R2.
  • the testing principle of the parasitic immune temperature sensor includes: using the above parasitic immune temperature sensor and formula (6) to provide the following test process:
  • the process of measuring the resistance difference ⁇ R and predicting the temperature includes:
  • Step S901 set the port voltage Va-Vb>>Vt, then D1 is turned on and D2 is turned off;
  • Step S902 measure the port resistance Rs1+R1+Rc
  • Step S903 set the port voltage Vb-Va>>Vt, then D2 is turned on and D1 is turned off;
  • Step S904 measure the port resistance Rs2+R2+Rc
  • Step S905 calculate ⁇ R
  • Step S906 use formula (6) to predict the local temperature T.
  • parameter verification can also be performed through linear fitting of the resistance difference ⁇ R and the measured data of temperature T.
  • Step S1001 set the new ambient temperature to Ti
  • Step S1002 wait for the system to reach thermal balance
  • Step S1003 obtain ⁇ Ri according to the process of steps S901 to S905;
  • the parasitic immune temperature sensor can be applied to wafer-level, substrate-level packaging structures and advanced packaging structures.
  • FIG 10 is a schematic diagram of the wafer-level application of the temperature sensor according to an embodiment of the present disclosure.
  • the temperature sensor can be used at the wafer level through a diffusion process directly on the Si die (bare chip).
  • the required symmetrical diodes D1 and D2 and the asymmetric thermistors R1 and R2 are formed, and then connected by the metal interconnection on the Si Die; if the detection position is the metal interconnection on the Si Die, then R1 and R2 are measured by It is composed of metal interconnection lines corresponding to the detection layer.
  • Thermistors R1 and R2 and diodes D1 and D2 are placed in the layout positions between similar devices and heterogeneous devices using the minimum spacing allowed by process rules, thereby improving the detection accuracy of the sensor.
  • Figure 10(b) is a layout diagram of building the required diodes and thermistors using the front-end process of the wafer manufacturing process.
  • the NP junction of the diode is realized through the N+ and Pwell diffusion layers respectively, and the thermistor is composed of two polysilicon (Poly) resistors with different lengths, and finally through the through hole (CT) and the metal interconnection layer (M1) Take out. Since the thermistor is Poly, it is generally used to test the junction temperature of the Si Die or the temperature of the adjacent lower metal interconnect.
  • the above-mentioned wafer process implementation solution can achieve miniaturization and cost reduction of embedded sensors. If it is necessary to achieve mass production testing, taking the FCBGA package shown in Figure 10(a) as an example, the signal can be extracted through the bump layer, IC substrate and BGA ball connecting the Si Die and the packaging substrate.
  • FIG. 11 is a schematic diagram of a substrate-level application of a temperature sensor according to an embodiment of the present disclosure.
  • applicable substrate types include but are not limited to common IC substrates and PCBs.
  • Figures 11(a) and 11(b) are respectively schematic diagrams of implementation examples of the buried layer of the substrate. This embodiment can be applied to temperature monitoring of any inner layer of the substrate.
  • Figure 11(b) is a schematic diagram of an embodiment of temperature detection on the surface of a substrate.
  • the symmetrical diodes D1 and D2 can be discrete devices; while the thermistors R1 and R2 can be either discrete devices for embedded or surface mounting, or they can be constructed directly using metal interconnections of the required detection layer. .
  • the layout design requirements are similar to the above-mentioned wafer-level embodiments, and the spacing between devices of the same type and between devices of different types must be minimized.
  • Figure 12 is a schematic diagram of the application of a temperature sensor in an advanced packaging structure according to an embodiment of the present disclosure.
  • Figures 12(a) and 12(b) are respectively schematic diagrams of embodiments of a 2.5D packaging structure and a 3D stacked packaging structure.
  • the sensor location can be configured at different system levels and physical layers according to actual needs.
  • the sensor can be at the wafer level or on the substrate.
  • CoWoS is an example.
  • the sensors on each packaged chip are passed through the bump, interposer (silicon interposer), IC substrate, and finally output through the BGAball.
  • interposer silicon interposer
  • IC substrate silicon substrate
  • BGAball BGAball
  • the stacked chips in the 3D package can be output through their independent interconnectors.
  • the connection path is output to the topmost output layer.
  • the temperature detection accuracy of the sensor since the temperature sensor is immune to parasitic effects, the temperature detection accuracy of the sensor has nothing to do with the winding length of the interconnection traces outside the sensor, the layout design, and the local temperature of other layers. Therefore, it is possible to achieve comparison of hot spot distribution in complex packaging structures through multi-point control of temperature sensors.
  • the specific requirements are similar to those at the wafer level and substrate level.
  • the temperature sensor in the above embodiments of the present disclosure can be used in many fields such as analog integrated circuit design, wafer and package thermal design, and reliability engineering, and can be used for different systems (for example, at the automotive level (such as automotive chips, etc.) and Industrial-grade system products) thermal design and temperature detection provide powerful measurement support.
  • each module or each step of the above-mentioned embodiments of the present disclosure can be implemented by a general computing device, and they can be concentrated on a single computing device, or distributed among multiple computing devices. over a network, they may be implemented with program code executable by a computing device, such that they may be stored in a storage device for execution by the computing device, and in some cases, may be executed in a sequence different from that described here.
  • the steps shown or described may be implemented by fabricating them separately into individual integrated circuit modules, or by fabricating multiple modules or steps among them into a single integrated circuit module. As such, the present disclosure is not limited to any specific combination of hardware and software.

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Abstract

一种温度传感器，包括：第一热敏电阻（101）、与第一热敏电阻（101）并联的第二热敏电阻（102）、与第一热敏电阻（101）串联的第一二极管（103），以及与第二热敏电阻（102）串联的第二二极管（104），其中，第一热敏电阻（101）和第二热敏电阻（102）为两个材质和工艺相同，但几何尺寸存在差异的毗邻热敏电阻，第一二极管（103）和第二二极管（104）为两个选型相同，但极性相反的毗邻二极管。还公开了温度传感器封装方法及温度测量方法。

Description

温度传感器、温度传感器封装方法及温度测量方法
相关申请的交叉引用
本申请基于2022年6月30日提交的发明名称为“温度传感器、温度传感器封装方法及温度测量方法”的中国专利申请CN202210764620.7，并且要求该专利申请的优先权，通过引用将其所公开的内容全部并入本申请。
技术领域
本公开实施例涉及电子电路技术领域，具体而言，涉及一种温度传感器、温度传感器封装方法及温度测量方法。
背景技术
微纳尺度精确量热一直是芯片和半导体行业极为关注的技术领域之一。其中，利用电阻的温度特性设计的温度传感器，通过监控热敏电阻的阻值变化而预测局部温升，是一种简便易行且具有良好线性度的量热解决方案。然而，此类电阻基的温度传感器实际仍需经过外部互连连接其他元器件、电源及测试设备，所以当测量热敏电阻时不可避免地引入了传感器之外的寄生效应。如图1所示，可将上述情况抽象为一个二端口的纯电阻网络，Rc为集总寄生电阻，RT为传感器的热敏电阻。则从该二端口电阻网络看进去，其实际电阻为Rc+RT，而非真正的RT。而且，Rc和RT的在系统中的位置不同，使用材料不同(即温度系数和低温电阻率不同)、尺寸以及局部温度都可能存在差异，因此，寄生问题对基于热敏电阻RT的阻值测量来推断系统局部温度的方案而言，无疑是一个巨大挑战。
发明内容
本公开实施例提供了一种温度传感器、温度传感器封装方法及温度测量方法，以至少解决基于热敏电阻RT的阻值来推断系统局部温度的技术方案里存在的寄生问题。
根据本公开的一个实施例，提供了一种温度传感器，包括：第一热敏电阻、与所述第一热敏电阻并联的第二热敏电阻、与所述第一热敏电阻串联的第一二极管，以及与所述第二热敏电阻串联的第二二极管，其中，所述第一热敏电阻和所述第二热敏电阻为两个材质和工艺相同，但几何尺寸存在差异的毗邻热敏电阻，所述第一二极管和所述第二二极管为两个选型相同，但极性相反的毗邻二极管。
根据本公开的另一个实施例，提供了一种温度传感器的封装方法，应用于上述温度传感器，包括：在硅晶圆芯片上通过扩散工艺形成第一热敏电阻、第二热敏电阻、第一二极管和第二二极管，并由硅晶圆芯片上的金属互连所述第一热敏电阻、第二热敏电阻、第一二极管和第二二极管以在所述硅晶圆芯片上形成所述温度传感器。
根据本公开的又一个实施例，还提供了一种温度传感器的封装方法，应用于上述温度传感器，包括：通过埋入的方式将第一热敏电阻、第二热敏电阻、第一二极管和第二二极管埋 入基板埋层中，或通过表面贴装的方式在基板上设置所述第一热敏电阻、第二热敏电阻、第一二极管和第二二极管，其中，所述第一热敏电阻、第二热敏电阻、第一二极管和第二二极管为分立器件。
根据本公开的又一个实施例，还提供了一种温度传感器的封装方法，应用于上述温度传感器，包括：将多个温度传感器分别设置在叠层封装结构的不同系统层级中，其中，所述温度传感器为晶圆级或基板级；将各所述温度传感器的端口通过内部互连后统一引出至最高一级的封装口，以进行多层间平行测试。
根据本公开的又一个实施例，还提供了一种温度测量方法，包括：改变所述温度传感器两端口之间的电压极性，并测量所述温度传感器在所述电压极性改变之前和所述电压极性改变之后的电阻；通过两次测量所得到的电阻获取所述温度传感器中的第一热敏电阻与第二热敏电阻的差值ΔR，并基于如下公式获取所述温度传感器所检测到的温度T：
其中，ρ0为所述第一热敏电阻或第二热敏电阻的低温电阻率，α为所述第一热敏电阻或第二热敏电阻的温度系数，L1为第一热敏电阻的长度，L2为第二热敏电阻的长度，S1为第一热敏电阻的截面积，S2为第二热敏电阻的截面积。
附图说明
图1是相关技术中一种抽象的二端口的纯电阻网络示意图；
图2是根据本公开实施例的温度传感器的示意图；
图3是根据本公开实施例的温度传感器封装方法的流程图；
图4是根据本公开另一实施例的温度传感器封装方法的流程图；
图5是根据本公开又一实施例的温度传感器封装方法的流程图；
图6是根据本公开实施例的温度测量方法的流程图；
图7是相关技术中二极管特性以及等效电路示意图；
图8是根据本公开实施例的温度传感器的核心电路的示意图；
图9是根据本公开实施例的温度传感器的测温及校验流程的示意图；
图10是根据本公开实施例的温度传感器的晶圆级应用的示意图；
图11是根据本公开实施例的温度传感器的基板级应用的示意图；
图12是根据本公开实施例的温度传感器的在先进封装结构上应用的示意图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本公开的实施例。
需要说明的是，本公开的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
本公开实施例提供一种基于电阻温度效应且互连寄生免疫的温度传感器设计，图2是根据本公开实施例的温度传感器的示意图，如图2所示该温度传感器包括：第一热敏电阻(101)、与所述第一热敏电阻(101)并联的第二热敏电阻(102)、与所述第一热敏电阻(101)串联 的第一二极管(103)，以及与所述第二热敏电阻(102)串联的第二二极管(104)，其中，所述第一热敏电阻(101)和所述第二热敏电阻(102)为两个材质和工艺相同，但几何尺寸存在差异的毗邻热敏电阻，所述第一二极管(103)和所述第二二极管(104)为两个选型相同，但极性相反的毗邻二极管。
在一个示例性实施例中，在探测位置在硅晶圆芯片上的金属互连层上的情况下，第一热敏电阻(101)和第二热敏电阻(102)由金属互连层的金属互连线构成。
在一个示例性实施例中，第一热敏电阻(101)和第二热敏电阻(102)为多晶硅电阻。
在一个示例性实施例中，第一二极管(103)和第二二极管(104)为分立器件或集成器件。
在一个示例性实施例中，第一热敏电阻(101)和第二热敏电阻(102)之间的间距，以及第一二极管(103)和第二二极管(104)间的间距，由所采用的制成工艺确定；例如，在本实施例中，第一热敏电阻(101)和第二热敏电阻(102)之间，以及第一二极管(103)和第二二极管(104)之间的最优间距为所采用制成工艺的规则允许下的最小间距，。
通过上述实施例，利用二极管的单向导通特性，搭建了基于二极管/电阻混合电路的新型电阻基温度传感器，进而通过改变该新型电阻基温度传感器的端口电压极性，实现对电路寄生电阻部分的扣除。因此，可以解决基于热敏电阻RT的阻值来推断系统局部温度的技术方案里存在的寄生问题，提高了对探测位置的温度探测的精确度。
在本公开的实施例中还提供了应用于上述一个或多个实施例中的温度传感器的封装方法，图3是根据本公开实施例的温度传感器封装方法的流程图，如图3所示，该流程包括如下步骤：
步骤S302，在硅晶圆芯片上通过扩散工艺形成第一热敏电阻、第二热敏电阻、第一二极管和第二二极管，
步骤S304，由硅晶圆芯片上的金属互连第一热敏电阻、第二热敏电阻、第一二极管和第二二极管以在硅晶圆芯片上形成温度传感器。
在一个示例性实施例中，该封装方法还包括：在第一热敏电阻和第二热敏电阻为多晶硅电阻的情况下，将温度传感器通过通孔和硅晶圆芯片上的金属互连层接出硅晶圆芯片。
在一个示例性实施例中，该封装方法还包括：将第一热敏电阻和第二热敏电阻电镀至硅晶圆芯片上。
图4是根据本公开另一实施例的温度传感器封装方法的流程图，如图4所示，该流程包括如下步骤：
步骤S402，通过埋入的方式将第一热敏电阻、第二热敏电阻、第一二极管和第二二极管埋入基板埋层中，或通过表面贴装的方式在基板上设置所述第一热敏电阻、第二热敏电阻、第一二极管和第二二极管，其中，所述第一热敏电阻、第二热敏电阻、第一二极管和第二二极管为分立器件。
在一个示例性实施例中，第一热敏电阻和第二热敏电阻由基板的探测层的金属互连线构成。
图5是根据本公开又一实施例的温度传感器封装方法的流程图，如图5所示，该流程包括如下步骤：
步骤S502，将多个温度传感器分别设置在叠层封装结构的不同系统层级中，其中，温度传感器为晶圆级或基板级；
步骤S504，将各温度传感器的端口通过内部互连后统一引出至最高一级的封装口，以进行多层间平行测试。
在一个示例性实施例中，将各所述温度传感器的端口通过内部互连后统一引出至最高一级的封装口，包括：将各所述温度传感器的端口通过内部互连后，经由所述叠层封装结构的bump(凸点)层、中介层、IC基板和BGAball(焊球阵列封装)层引出，或，将各所述温度传感器经由各自独立的互连路径引出至所述叠层封装结构的最顶部的输出层。
本公开实施例还提供了应用于上述任一实施例中的温度传感器的温度测量方法，图6是根据本公开实施例的温度测量方法的流程图，如图6所示，该流程包括如下步骤：
步骤S602，改变温度传感器两端口之间的电压极性，并测量温度传感器在电压极性改变之前和电压极性改变之后的电阻；
步骤S604，通过两次测量所得到的电阻获取温度传感器中的第一热敏电阻与第二热敏电阻的差值ΔR，并基于如下公式(1)获取温度传感器所检测到的温度T：
其中，ρ0为第一热敏电阻或第二热敏电阻的低温电阻率，α为第一热敏电阻或第二热敏电阻的温度系数，L1为第一热敏电阻的长度，L2为第二热敏电阻的长度，S1为第一热敏电阻的截面积，S2为第二热敏电阻的截面积。
在一个示例性实施例中，该温度测流量方法还包括：设置所述温度传感器所处的多个不同的环境温度；通过改变所述温度传感器两端口之间的电压极性分别确定所述多个不同环境温度下的第一热敏电阻与第二热敏电阻的多个差值，基于所述多个差值与多个不同的环境温度之间的线性回归关系进行至少如下之一的参数的校验：ρ0、α、L1、L2、S1和S2。
为便于对本公开所提供的技术方案的理解，下面将结合具体场景的实施例进行详细的阐述。
本公开实施例提出了一种基于电阻温度效应的且能够免疫互连寄生的温度传感器设计，并提供了该温度传感器的相关电路分析、测试原理和流程，以及该温度传感器在多种不同电子系统中的应用。
具体地，在本实施例中的寄生免疫温度传感器的电路设计为：利用二极管的单向导通特性，搭建了基于二极管/电阻混合电路的新型电阻基温度传感器。在测量温度的过程中，通过改变该温度传感器的端口电压极性，来获取位置毗邻、同质但几何尺寸不同的两个热敏电阻之间的电阻差值ΔR的变化，从而能实现对电路寄生电阻部分的扣除，进而可对探测位置的温度精确探测。其中，位置毗邻能够尽可能地保证两热敏电阻的局部温度相同，同质则保证两热敏电阻的电阻率和温度系数相同，几何尺寸不同则表示两个热敏电阻的阻值不同。
图7是相关技术中二极管特性以及等效电路示意图，如图7(a)所示，Rs和Rp分别为二极管的串联和并联电阻，一般Rs远远小于Rp，当外部电压V小于图7(a)中理想二极管的开启电压Vt时，理想二极管开路，IV特性对应于图7(b)中Rp-dominated(Rp-控制)区域，等效电路则如图7(c)I所示可近似为Rs和Rp的串联，由于并联电阻阻值很大，通过二极管的电流很小，所以一般将Rp-dominated区域的IV特性表现为电流截止；若当外部电压V大于二极管的开启电压Vt时候，图7(a)中的理想二极管短路从而旁路了Rp，此时，IV特性如图7(b)中Rs-dominated(Rs-控制)区域所示，表现阻值如图7(c)II所示为Rs电阻特性，即可近似为一个阻值极小的纯电阻电路。
图8是根据本公开实施例的温度传感器的核心电路的示意图，如图8(a)所示，该温度传感器由两个热敏电阻R1、R2和两个二极管D1、D2串并联构成，其中，Rc为传感器之外其他互连和元器件的集总寄生电阻，D1和D2为两个极性相反、位置毗邻的二极管，不论是材料、制作工艺和几何尺寸都要求尽可能保持一致；而R1和R2则分别为两个材质和工艺相同(即相同的ρ0和α)，但几何尺寸存在差异的毗邻热敏电阻，此处为描述方便假设R1＞R2。
根据二极管IV关系和单向导通性可知，若改变端口a和b的电压极性，即可实现对电路中不同电阻成分的分辨，进而实现消除寄生效应Rc的影响。具体地，如图8所示，若Va-Vb＞＞Vt，则D1导通而D2截止，等效电路如图8(b)所示，而从端口a、b看网络的总电阻为Rs1+R1+Rc；若Vb-Va＞＞Vt，则D2导通而D1截止，等效电路如图8(c)所示，而从端口a、b看网络的总电阻为Rs2+R2+Rc。由于D1和D2为两个相同选型(即材质、工艺和尺寸一致)且位置毗邻的二极管，所以可知Rs1＝Rs2，则R1和R2之间的ΔR可通过公式(2)获得。
ΔR＝(Rs1+R1+Rc)-(Rs2+R2+Rc)＝R1-R2  公式(2)
由公式(2)可见，通过改变端口的电压极性，将前后两次端口等效电阻作差就可以消除电路中的寄生部分Rc，并且ΔR只与R1和R2有关。由于前述R1和R2毗邻、同质的假设，很容易参考电阻的温度特性(即公式(3))建立两个热敏电阻电阻差值ΔR与温度T的关系。
具体地，电阻差值ΔR和温度T的数学关系推导如下：
基于上述R1和R2毗邻、同质的假设，结合公式(3)，则R1和R2与温度的关系可分别表示为公式(4)和(5)，其中L1、L2、S1和S2分别为热敏电阻R1、R2的长度和截面积：

将公式(4)和(5)代入公式(2)，则可得公式(6)：
可见，电阻差值和温度仍满足类似公式(3)的线性关系，其中，A为结构因子，和热敏 电阻尺寸有关，定义为
在本实施例中，该寄生免疫温度传感器的测试原理包括：利用上述寄生免疫的温度传感器以及公式(6)提供了如下测试流程：
(1)在已知两个热敏电阻尺寸和温度系数的前提下，进行电阻差值ΔR测量和温度预测流程包括：
通过改变端口电压极性的两次电阻测量，获得热敏电阻差值ΔR的相关流程如图9(a)所示，包括如下步骤：
步骤S901，设置端口电压Va-Vb＞＞Vt，则D1导通而D2截止；
步骤S902，测量端口电阻Rs1+R1+Rc；
步骤S903，设置端口电压Vb-Va＞＞Vt，则D2导通而D1截止；
步骤S904，测量端口电阻Rs2+R2+Rc；
步骤S905，计算ΔR；
步骤S906，利用公式(6)预测局部温度T。
(2)在热敏电阻尺寸和温度系数未知情况下，还可通过电阻差值ΔR和温度T实测数据的线性拟合进行参数校验。
重要参数未知前提下的电阻差值和温度校准流程如图9(b)所示，包括如下步骤：
步骤S1001，设置新的环境温度到Ti；
步骤S1002，等待系统达到热平衡；
步骤S1003，按照步骤S901～S905的流程获得ΔRi；
切换下一个温度Ti+1，重复步骤S1001～S1003；
经过上述步骤，可获取一个如图9(b)中的电阻差值ΔR和温度T中间的线性关系，如此，在热敏电阻尺寸和温度系数未知情况下，便可通过该线性关系进行参数校验。
在发明实施例中，寄生免疫温度传感器可应用于晶圆级、基板级封装结构以及先进封装结构。
图10是根据本公开实施例的温度传感器的晶圆级应用的示意图，如图10(a)所示，在晶圆级运用该温度传感器可以通过在Si die(裸芯片)上直接通过扩散工艺形成所需的对称二极管D1和D2和非对称的热敏电阻R1和R2，然后由Si Die上的金属互连连出；若探测位置为Si Die的上的金属互连测，则R1和R2由对应探测层的金属互连线构成。热敏电阻R1和R2、二极管D1和D2在同类器件和异类器件间的版图位置摆放采用工艺规则允许下的最小间距，从而提高传感器的探测精度。图10(b)是以晶圆制造工艺中前段工艺来搭建所需二极管和热敏电阻的版图示意。
在本实施例中，二极管的NP结分别通过N+和Pwell扩散层实现，热敏电阻则由两个长度不同多晶硅(Poly)电阻构成，最后通过通孔(CT)和金属互连层(M1)接出。由于，热敏电阻选择Poly，所以一般用于测试Si Die的结温或临近的低层金属(1ower metal)互连测的温度。上述借助晶圆工艺实现方案可以实现嵌入式传感器的小型化和成本降低。如需要达成量产测试，以图10(a)所示的FCBGA封装形式为例，可进而通过连接Si Die与封装基板的bump层、IC基板和BGA ball引出信号。
图11是根据本公开实施例的温度传感器的基板级应用的示意图，在本实施例中，适用的基板类型包括但不限于常见的IC基板和PCB。图11(a)和图11(b)分别为基板埋层的实施用例示意图，该实施例可以应用于基板任意内层的温度监控。图11(b)为基板表层探温的实施例示意图。
在本实施例中，对称二极管D1和D2可选择分立器件；而热敏电阻R1和R2既可选择分立器件进行埋入或表面贴装，也可直接使用所需探测层的金属互连来构造。版图设计上的需求和上述晶圆级的实施例相似，同类器件之间和异类器件间的间距做最小化处理。
图12是根据本公开实施例的温度传感器的在先进封装结构上应用的示意图，图12(a)和图12(b)分别为2.5D封装结构及3D叠层封装结构的实施例示意图。传感器位置可以根据实际需求配置在不同的系统层级和物理层，该传感器可以是晶圆级也可以是基板。为了实现2.5D和3D封装结构中多层间平行测试，可参考图12所示将不同位置传感器的端口经过内部互连统一引出到最高一级的封装接口进行测量，如图12(a)中CoWoS为例，将各个合封芯片上的传感器经由bump、interposer(硅中介层)、IC基板，最终通过BGAball输出；如图12(b)中3D封装中的叠层芯片可经由各自独立的互连路径输出到最顶部的输出层(output layer)。
在本实施例中，由于该温度传感器具有寄生效应免疫的特征，所以传感器的温度探测精度与传感器之外的互连走线绕线长度、版图设计及他层的局部温度无关。因此，可以很好地通过温度传感器多点布控，实现复杂封装结构中热点分布的对比。对于先进封装结构中传感器的版图设计，其具体要求则与晶圆级和基板级类同。
本公开上述实施例中的温度传感器可应用于模拟集成电路设计、晶圆和封装热设计及可靠性工程等多个领域，为不同系统(例如，在车规级(如车规芯片等)和工业级系统产品)热设计和温度探测提供有力的量测支持。
显然，本领域的技术人员应该明白，上述的本公开实施例的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本公开不限制于任何特定的硬件和软件结合。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (14)

  1. 一种温度传感器，包括：第一热敏电阻(101)、与所述第一热敏电阻(101)并联的第二热敏电阻(102)、与所述第一热敏电阻(101)串联的第一二极管(103)，以及与所述第二热敏电阻(102)串联的第二二极管(104)，其中，所述第一热敏电阻(101)和所述第二热敏电阻(102)为两个材质和工艺相同，但几何尺寸存在差异的毗邻热敏电阻，所述第一二极管(103)和所述第二二极管(104)为两个选型相同，但极性相反的毗邻二极管。
  2. 根据权利要求1所述的传感器，其中，在探测位置在硅晶圆芯片上的金属互连层的情况下，所述第一热敏电阻(101)和所述第二热敏电阻(102)由所述金属互连层的金属互连线构成。
  3. 根据权利要求1所述的传感器，其中，所述第一热敏电阻(101)和所述第二热敏电阻(102)为多晶硅电阻。
  4. 根据权利要求1所述的传感器，其中，所述第一二极管(103)和所述第二二极管(104)为分立器件或集成器件。
  5. 根据权利要求1所述传感器，其中，所述第一热敏电阻(101)和所述第二热敏电阻(102)之间的间距，以及所述第一二极管(103)和所述第二二极管(104)之间的间距由所采用的制成工艺确定。
  6. 一种温度传感器的封装方法，应用于权利要求1-3、5任一项所述温度传感器，包括：
    在硅晶圆芯片上通过扩散工艺形成第一热敏电阻、第二热敏电阻、第一二极管和第二二极管，并由硅晶圆芯片上的金属互连所述第一热敏电阻、第二热敏电阻、第一二极管和第二二极管以在所述硅晶圆芯片上形成所述温度传感器。
  7. 根据权利要求6所述的方法，还包括，
    在所述第一热敏电阻和所述第二热敏电阻为多晶硅电阻的情况下，将所述温度传感器通过通孔和所述硅晶圆芯片上的金属互连层接出所述硅晶圆芯片。
  8. 根据权利要求7所述的方法，还包括：
    将所述第一热敏电阻和所述第二热敏电阻电镀至所述硅晶圆芯片上。
  9. 一种温度传感器的封装方法，应用于权利要求1或4或5所述温度传感器，包括：
    通过埋入的方式将第一热敏电阻、第二热敏电阻、第一二极管和第二二极管埋入基板埋层中，或通过表面贴装的方式在基板上设置所述第一热敏电阻、第二热敏电阻、第一二极管和第二二极管，其中，所述第一热敏电阻、第二热敏电阻、第一二极管和第二二极管为分立器件。
  10. 根据权利要求9所述的方法，其中，所述第一热敏电阻和所述第二热敏电阻由所述基板的探测层的金属互连线构成。
  11. 一种温度传感器的封装方法，应用于权利要求1-5任一项所述的温度传感器，包括：
    将多个温度传感器分别设置在叠层封装结构的不同系统层级中，其中，所述温度传感器 为晶圆级或基板级；
    将各所述温度传感器的端口通过内部互连后统一引出至最高一级的封装口，以进行多层间平行测试。
  12. 根据权利要求11所述的方法，其中，将各所述温度传感器的端口通过内部互连后统一引出至最高一级的封装口，包括：
    将各所述温度传感器的端口通过内部互连后，经由所述叠层封装结构的bump层、中介层、IC基板和BGAball层引出，或，将各所述温度传感器经由各自独立的互连路径引出至所述叠层封装结构的最顶部的输出层。
  13. 一种温度测量方法，应用于权利要求1至5任一项所述的温度传感器，该方法包括：
    改变所述温度传感器两端口之间的电压极性，并测量所述温度传感器在所述电压极性改变之前和所述电压极性改变之后的电阻；
    通过两次测量所得到的电阻获取所述温度传感器中的第一热敏电阻与第二热敏电阻的差值ΔR，并基于如下公式获取所述温度传感器所检测到的温度T：
    其中，ρ0为所述第一热敏电阻或第二热敏电阻的低温电阻率，α为所述第一热敏电阻或第二热敏电阻的温度系数，L1为第一热敏电阻的长度，L2为第二热敏电阻的长度，S1为第一热敏电阻的截面积，S2为第二热敏电阻的截面积。
  14. 根据权利要求13所述的方法，还包括：
    设置所述温度传感器所处的多个不同的环境温度；
    通过改变所述温度传感器两端口之间的电压极性分别确定所述多个不同环境温度下的第一热敏电阻与第二热敏电阻的多个差值，基于所述多个差值与多个不同的环境温度之间的线性回归关系进行至少如下之一的参数的校验：ρ0、α、L1、L2、S1和S2。
PCT/CN2023/101903 2022-06-30 2023-06-21 温度传感器、温度传感器封装方法及温度测量方法 Ceased WO2024001924A1 (zh)

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