WO2024011749A1 - 一种像素单元及其制作方法、微显示屏、分立器件 - Google Patents

一种像素单元及其制作方法、微显示屏、分立器件 Download PDF

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Publication number
WO2024011749A1
WO2024011749A1 PCT/CN2022/119546 CN2022119546W WO2024011749A1 WO 2024011749 A1 WO2024011749 A1 WO 2024011749A1 CN 2022119546 W CN2022119546 W CN 2022119546W WO 2024011749 A1 WO2024011749 A1 WO 2024011749A1
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layer
electrical connection
type contact
backplane
contact layer
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English (en)
French (fr)
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王亚洲
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Nuoshi Technology Suzhou Co Ltd
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Nuoshi Technology Suzhou Co Ltd
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Priority to EP22950860.1A priority Critical patent/EP4550430A4/en
Priority to JP2025500977A priority patent/JP2025524616A/ja
Priority to KR1020257001246A priority patent/KR20250053838A/ko
Publication of WO2024011749A1 publication Critical patent/WO2024011749A1/zh
Priority to US19/017,751 priority patent/US20250151476A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/831—Electrodes characterised by their shape
    • H10H20/8316—Multi-layer electrodes comprising at least one discontinuous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/30—Active-matrix LED displays
    • H10H29/49—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/813—Bodies having a plurality of light-emitting regions, e.g. multi-junction LEDs or light-emitting devices having photoluminescent regions within the bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/01—Manufacture or treatment
    • H10H29/012—Manufacture or treatment of active-matrix LED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/01—Manufacture or treatment
    • H10H29/032—Manufacture or treatment of electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/01—Manufacture or treatment
    • H10H29/036—Manufacture or treatment of packages
    • H10H29/0364—Manufacture or treatment of packages of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
    • H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/30—Active-matrix LED displays
    • H10H29/39—Connection of the pixel electrodes to the driving transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/80—Constructional details
    • H10H29/832—Electrodes
    • H10H29/8321—Electrodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/80—Constructional details
    • H10H29/962—Stacked configurations of light-emitting semiconductor components or devices, the components or devices emitting at different wavelengths
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/017—Etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H10H20/0364—Manufacture or treatment of packages of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/831—Electrodes characterised by their shape
    • H10H20/8312—Electrodes characterised by their shape extending at least partially through the bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/30—Active-matrix LED displays
    • H10H29/34—Active-matrix LED displays characterised by the geometry or arrangement of subpixels within a pixel, e.g. relative disposition of the RGB subpixels

Definitions

  • the present application relates to the technical field of semiconductor devices, and in particular to a pixel unit and a manufacturing method thereof, a microdisplay screen, and discrete devices.
  • Micro-LED display has many advantages over existing LCD, OLED and other display technologies. It is generally considered to be the core of next-generation display technology and has great potential in many fields such as watches, TVs, projections, virtual reality, augmented reality, and mixed reality. Application prospects, but these application requirements have put forward new requirements in terms of chip manufacturing, size, structure, yield, drive, etc. Traditional LED preparation solutions are difficult to match and require a high degree of integration to meet the needs.
  • the current mainstream Micro-LED colorization technology includes: three primary colors, color conversion, prism light combining and other solutions.
  • the colorization implementation is basically based on three colors on a planar structure. For There are certain challenges in further compressing the device size and performing ultra-high-density pixel array display.
  • Mini LEDs are on the order of microns, they are much different from traditional LEDs, which are often hundreds or thousands of microns. And in use The number of chips involved is huge, making it difficult to use traditional solutions.
  • a mobile phone screen with a 1080P resolution has more than 2 million pixels (1920*1080), and each pixel is composed of three sub-pixels: red, green, and blue. That is a mobile phone screen with a 1080P resolution. More than 6 million LEDs are needed. For traditional LED chips, one chip is transferred every second. It takes nearly a year to complete such a screen, which is extremely expensive.
  • Mass transfer uses pick and place methods similar to traditional solutions, but traditional LED solutions in different areas are one-time Pick up one or a few, and mass transfer picks up a large number of chips at one time for transfer;
  • Monolithic Integration refers to forming a densely arranged LED matrix area or a whole wafer LED array, and then aligning the metal contacts A solution that is quasi-bonded to the driver and has a higher density of integration.
  • the current solutions for realizing colorized Micro-LED display chips mainly include mass transfer integration, non-aligned bonding horizontal display (such as the published Chinese patent CN110462850A), and aligned bonding vertical display.
  • Currently disclosed horizontal display technologies with massive transfer integration and non-alignment bonding generally suffer from space waste and intra-pixel optical crosstalk problems. The waste of space is reflected in the horizontal layout of red, green and blue colors, showing a loss of pixel density.
  • Alignment bonding vertical stacking integration requires extremely high alignment requirements, is expensive, and the alignment accuracy is difficult to guarantee. For example, some literature mentions that when the pixel size increases or decreases by 1 ⁇ m, ultra-small pixels must be processed. During the preparation, the alignment deviation is unacceptable, and because the monochromatic device is prepared first, there is a step difference in the device itself. During the bonding process, array cracks or disconnections are easily caused by the step difference, affecting the yield.
  • the purpose of this application is to provide a pixel unit and a manufacturing method thereof, a microdisplay screen, and a discrete device, which can realize ultra-high-density, micron-scale color display.
  • the first aspect of this application proposes a pixel unit.
  • the pixel unit includes a backplane, a display unit, a cathode electrical connection structure and at least one anode electrical connection structure.
  • the display unit is provided on the backplane.
  • the cathode electrical connection structure and the at least one anode electrical connection structure are respectively embedded in the display unit from the side surface away from the back plate;
  • the display unit includes at least one device layer.
  • the at least one device layer is vertically stacked in sequence. Any of the device layers includes a P-type contact layer, a pixel layer and an N-type contact layer that are stacked in sequence.
  • the P-type contact layer is located at The device layer to which it belongs faces the side of the backplane;
  • any of the anode electrical connection structures is electrically connected to the P-type contact layer of the corresponding device layer, and the cathode electrical connection structure is electrically connected to the N-type contact layer of any of the device layers.
  • any one of the anode electrical connection structures is connected to the backplane
  • the at least one anode electrical connection structure includes a first anode electrical connection structure, and the first anode electrical connection structure includes a first partial structure and a second partial structure connected in sequence;
  • the at least one device layer includes a first device layer, the first device layer includes a first bonding layer, a first P-type contact layer, a first pixel layer and a first N-type contact layer stacked in sequence, and the A P-type contact layer is located on the side of the first device layer close to the backplane;
  • the first partial structure is embedded in the first bonding layer and the first P-type contact layer, part of the second partial structure is embedded in the first pixel layer, and the second partial structure
  • the structure is electrically connected to the first P-type contact layer.
  • the end area of the second partial structure is larger than the end area of the first partial structure, so as to form a first flange at the connection between the two;
  • the first flange is connected to the first P-type contact layer.
  • the at least one anode electrical connection structure further includes a second anode electrical connection structure
  • the display unit also includes a second device layer stacked on a side surface of the first device layer away from the backplane, and the second device layer includes second bonding layers stacked in sequence. , a second P-type contact layer, a second pixel layer and a second N-type contact layer, the second bonding layer is connected to the first pixel layer;
  • the second anode electrical connection structure includes a second flange connected to the second P-type contact layer.
  • the second N-type contact layer is disposed directly above the first N-type contact layer.
  • the first N-type contact layer has a protruding structure, and the first N-type contact layer is embedded in the second bonding layer.
  • the cathode electrical connection structure includes a third partial structure embedded in the second device layer, and one end of the third partial structure is connected to the The first N-type contact layer is connected.
  • the cathode electrical connection structure further includes a fourth partial structure.
  • One end of the fourth partial structure is connected to the backplane, and the other end passes through the first device layer and is connected to the backplane.
  • the third part is structural connection.
  • the second bonding layer includes a second bonding layer body and a functional layer, and the functional layer is provided between the second bonding layer body and the first pixel layer. between.
  • the at least one anode electrical connection structure further includes a third anode electrical connection structure
  • the display unit also includes a third device layer, the third device layer is stacked on a side surface of the second device layer away from the first device layer, and the third device layer includes third keys stacked in sequence.
  • the third anode electrical connection structure includes a third flange, and the third flange is connected to the third P-type contact layer.
  • the cathode electrical connection structure further includes a fifth partial structure connected to the third partial structure, and the fifth partial structure is embedded in the third device layer;
  • the end area of the fifth partial structure is larger than the end area of the third partial structure, so as to form a fourth flange at the connection between the two;
  • the fourth flange is connected to the second N-type contact layer.
  • the second N-type contact layer has a protruding structure, and the second N-type contact layer is embedded in the third bonding layer.
  • both the second bonding layer and the third bonding layer are made of transparent material.
  • the pixel unit further includes a passivation layer, part of the passivation layer is attached to the outer surface of the display unit and the backplane, and part of the passivation layer is attached to Between the at least one anode electrical connection structure and the display unit, part of the passivation layer is attached between the cathode electrical connection structure and the display unit.
  • the passivation layer is provided with at least one through hole, and the at least one through hole is provided between any anode electrical connection structure and the corresponding P-type contact layer, and, between the cathode electrical connection structure and the corresponding N-type contact layer.
  • the passivation layer is made of transparent insulating material.
  • the first pixel layer is an AlGaInP or InGaN red light compound epitaxy
  • the second pixel layer is an InGaN green light compound epitaxy
  • the third pixel layer is an InGaN blue light compound epitaxy.
  • a method of manufacturing a pixel unit includes:
  • At least one device layer is stacked vertically on the backplane in sequence to form a display unit.
  • Any of the device layers includes a P-type contact layer, a pixel layer and an N-type contact layer stacked in sequence.
  • the P-type contact layer is located where it belongs.
  • the device layer faces the side of the backplane;
  • a cathode electrical connection channel and at least one anode electrical connection channel are formed by etching inward from the surface of the side of the display unit away from the back plate;
  • the cathode electrical connection channel and the at least one anode electrical connection channel are filled with metal to form a cathode electrical connection structure and at least one anode electrical connection structure; the cathode electrical connection structure has an N-type contact with any of the device layers The layers are electrically connected respectively, and any of the anode electrical connection structures is electrically connected to the P-type contact layer of the corresponding device layer.
  • the at least one device layer includes a first device layer, and the at least one device layer is sequentially vertically stacked on the backplane to form a display unit, including:
  • Bonding materials are respectively plated on the surface of the backplane and the P-type contact layer of the previously prepared first compound semiconductor wafer and bonded to form a first bonding layer;
  • the substrate of the first compound semiconductor wafer is removed and the compound semiconductor is thinned to expose a first N-type contact layer, where the first N-type contact layer is a protruding structure.
  • the at least one device layer further includes a second device layer and a third device layer; after completing the first device layer, at least one device is stacked vertically on the backplane in sequence.
  • layers to form the display unit also including:
  • a second device layer and a third device layer are vertically stacked in sequence on a side surface of the first device layer away from the backplane to form the display unit.
  • the cathode electrical connection channel and at least one anode electrical connection channel are etched inward from the side surface of the display unit away from the back plate, including:
  • the cathode electrical connection channel and at least one anode electrical connection channel are etched inward from the side surface of the display unit away from the back plate, including:
  • Patterned wet etching is used to deeply etch the display unit that has completed preliminary deep etching until the backplane is exposed to form the cathode electrical connection channel and at least one anode electrical connection channel.
  • the metal filling of the cathode electrical connection channel and the at least one anode electrical connection channel to form a cathode electrical connection structure and at least one anode electrical connection structure includes:
  • the outer surfaces of the display unit and the backplane, the inner walls of the cathode electrical connection channel and the at least one anode electrical connection channel are passivated to form a passivation layer, and at least one is opened through patterned etching.
  • the at least one through hole is provided between any anode electrical connection structure and the corresponding P-type contact layer, and the at least one through hole is provided between the cathode electrical connection structure and the corresponding N-type contact layer between;
  • the cathode electrical connection channel and the at least one anode electrical connection channel are filled with metal by sputtering, electroplating, chemical plating or evaporation to construct the cathode electrical connection structure and at least one anode electrical connection structure.
  • a micro display screen in a third aspect, includes:
  • a driving backplane which includes a driving circuit and an input and output interface
  • a display area the display area is provided on the driving backplane, and the display area includes at least two display units according to any one of the first aspects, and at least two of the display units are arranged in an array;
  • a peripheral common cathode is provided around the circumference of the display area, and the peripheral common cathode is respectively connected to the cathode electrical connection structure of any of the display units.
  • the backplane is integrated with a driving circuit
  • the driving circuit includes at least one anode, and any of the anode electrical connection structures is electrically connected to the corresponding anode.
  • the microdisplay further includes an insulating layer and a transparent conductive layer sequentially attached to the surface of the display area from the inside to the outside, and the transparent conductive layer is connected to the peripheral common cathode. ;
  • the insulating layer is provided with at least one hollow, and the cathode electrical connection structure is connected to the transparent conductive layer through the hollow in the insulating layer.
  • a discrete device in a fourth aspect, includes:
  • the device body is provided on the backplane of the discrete device, and the device body includes at least two display units as described in any one of the first aspects, and the at least two display units are arranged in an array. cloth;
  • At least two pads including one cathode pad and at least one anode pad, at least part of any one of the anode pads and at least part of the cathode pad are respectively embedded in the discrete backplane, any The anode electrical connection structure is connected to the corresponding anode pad, and the cathode electrical connection structure is connected to the corresponding cathode pad.
  • the pixel unit includes a backplane, a display unit, a cathode electrical connection structure, and at least one anode electrical connection structure.
  • the display unit is located on the backplane, and the cathode
  • the electrical connection structure and at least one anode electrical connection structure are respectively embedded in the display unit from the side surface away from the backplane;
  • the display unit includes at least one device layer, and at least one device layer is stacked vertically in sequence, and any device layer includes in sequence Stacked P-type contact layer, pixel layer and N-type contact layer, the P-type contact layer is located on the side of its device layer facing the backplane;
  • any anode electrical connection structure is electrically connected to the P-type contact layer of the corresponding device layer, and the cathode
  • the electrical connection structure is electrically connected to the N-type contact layer of any device layer respectively;
  • the pixel unit provided by this application realizes color display by stacking and integrating at least two device layers vertically on the backplane.
  • the pixel unit in this application occupies less space in the horizontal direction, achieving ultra-high-density color Micro-LED display, thereby achieving a smaller display size or the same screen size at the same resolution.
  • the first anode electrical connection structure includes a first partial structure and a second partial structure connected in sequence, and the end area of the second partial structure is larger than the end area of the first partial structure to form a first flange at the connection between the two parts, and the pixel
  • the unit also includes a passivation layer, part of the passivation layer is attached to the outer surface of the display unit and the backplane, part of the passivation layer is attached between at least one anode electrical connection structure and the display unit, part of the passivation layer is attached to the cathode
  • the anode electrical connection structure in this application constructs a flange structure through diameter changes to realize the connection between the anode electrical connection structure and the P-type contact layer, or the cathode electrical connection structure and the N-type contact layer. Electrical connection, thereby simplifying the structure and reducing process difficulty;
  • the manufacturing method of the pixel unit provided by this application includes preparing a backplane; vertically stacking at least one device layer on the backplane to form a display unit, and any device layer includes a sequentially stacked P-type contact layer, a pixel layer and N-type contact layer, and the P-type contact layer is located on the side of the device layer to which it belongs facing the backplane; the surface of the side of the display unit away from the backplane is etched inward to construct a cathode electrical connection channel and at least one anode electrical connection channel; The cathode electrical connection channel and at least one anode electrical connection channel are filled with metal to form a cathode electrical connection structure and at least one anode electrical connection structure; the cathode electrical connection structure is electrically connected to the N-type contact layer of any device layer, and any anode The electrical connection structure is electrically connected to the P-type contact layer of the corresponding device layer; the manufacturing method of the pixel unit in this application adopts a stacking first and
  • Figure 1 is a top view of the pixel unit in Embodiment 1;
  • Figure 2 is a sectional view of the A-B section in Figure 1;
  • Figure 3 is a top view of the smallest light-emitting unit included in the discrete device of Embodiments 1 and 3;
  • Figure 4 is a cross-sectional view of the C-D section in Figure 3;
  • Figure 5 is a cross-sectional view of the C-D section in Figure 3 when the sacrificial layer is included;
  • Figure 6 is a top view of the microdisplay
  • Figures 7 to 9 are schematic diagrams of three exemplary circuit structures included in the backplane in Embodiment 1;
  • Figure 10 is a schematic diagram of the circuit structure of any device layer.
  • connection should be understood in a broad sense.
  • connection or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two components.
  • connection or integral connection
  • connection or integral connection
  • connection can be a mechanical connection or an electrical connection
  • it can be a direct connection or an indirect connection through an intermediate medium
  • it can be an internal connection between two components.
  • specific meanings of the above terms in this application can be understood on a case-by-case basis.
  • this embodiment provides a pixel unit 100, which can be used as the smallest light-emitting unit of the discrete device 300 as shown in Figures 3 to 5, or can be used as a micro display screen as shown in Figure 6 Minimum lighting unit of 200.
  • the pixel unit 100 includes a backplane 10 , a display unit 20 , a cathode electrical connection structure 30 and at least one anode electrical connection structure.
  • the display unit 20 is disposed on the back plate 10 , and the cathode electrical connection structure 30 and at least one anode electrical connection structure are respectively embedded in the display unit 20 from a side surface away from the back plate 10 . Any anode electrical connection structure is connected to the backplane 10 .
  • the display unit 20 includes at least one device layer, and the at least one device layer is vertically stacked in sequence in a direction perpendicular to the backplane 10 to form a Wafer Level Vertical Stack Pixel (WLVSP).
  • Any device layer includes a P-type contact layer, a pixel layer and an N-type contact layer stacked in sequence.
  • the P-type contact layer is located on the side of its corresponding device layer facing the backplane 10 .
  • Any anode electrical connection structure is electrically connected to the P-type contact layer of the corresponding device layer, and the cathode electrical connection structure is electrically connected to the N-type contact layer of any device layer.
  • the pixel unit in this embodiment includes a number of ground anode electrical connection structures corresponding to the number of device layers.
  • This embodiment does not limit the number of device layers included in the display unit 20, and it can be one layer, two layers, three layers or even more.
  • the epitaxial luminescent compounds included in any two device layers may be the same or different.
  • the brightness of the light source of the same color can be improved, or a backup redundant device layer can be formed to improve the yield of the pixel unit.
  • the luminescent compounds included in any two device layers are epitaxially different, colored display, such as full-color display, such as red, green, and blue primary color pixels, can be achieved.
  • the display unit 20 includes a first device layer 40 that emits red light, a second device layer 50 that emits green light, and a third device layer 60 that emits blue light.
  • any device layer in this embodiment may be a quadrilateral, hexagon, octagon, circle or other common graphics or a combination of graphics, which is not further limited in this embodiment.
  • the backplane 10 is a passive backplane or an active backplane integrated with a driving circuit.
  • the backplane 10 is preferably an active backplane, and the drive circuit is provided with at least one anode, thin film transistor (TFT), LTPS low-temperature polysilicon, CMOS integrated circuit, high mobility transistor HEMT, etc.
  • TFT thin film transistor
  • LTPS low-temperature polysilicon
  • CMOS integrated circuit high mobility transistor HEMT, etc.
  • One or more active drive backplanes and semi-active drive backplanes For example, if you select a CMOS integrated circuit backplane, its R, G, and B are respectively equipped with top metal (Top metal) corresponding to the anode surface.
  • Top metal top metal
  • Figures 8 and 9 respectively show the stacking of two red light device layers, and then the green light device layer and the blue light device layer.
  • the two layers The red light device layers can be connected in parallel or in series.
  • the circuits of each device layer may include active, passive or semi-passive control circuits.
  • An exemplary circuit is shown in Figure 10. It should be noted that the circuit diagram in this embodiment is only a simple schematic diagram. In this embodiment, at least one anode can be arranged on the same straight line, in a Z-shaped arrangement, or in an array. Any anode is located in the middle or edge of the driving backplane 10 , and this embodiment does not limit this. .
  • the backplane is preferably a passive backplane.
  • the backplane is preferably made of PCB, sapphire, glass, Si and other materials.
  • the passive backplane is connected to the power supply through a downstream packaging process.
  • the first device layer 40 includes a first bonding layer 41 , a first P-type contact layer 42 , a first pixel layer 43 and a first N-type contact layer 44 stacked in sequence.
  • the type contact layer 42 is located on the side of the first device layer 40 close to the backplane 10 .
  • the second device layer 50 is stacked on the side surface of the first device layer 40 away from the backplane 10 .
  • the second device layer 50 includes a second bonding layer 51 , a second P-type contact layer 52 , and a second pixel layer 53 stacked in sequence. and the second N-type contact layer 54, the second bonding layer 51 is connected to the first pixel layer 43.
  • the third device layer 60 is stacked on a side surface of the second device layer 50 away from the first device layer 40 .
  • the third device layer 60 includes a third bonding layer 61 , a third P-type contact layer 62 , and a third P-type contact layer 62 .
  • the pixel layer 63 and the third N-type contact layer 64 are connected to the third bonding layer 61 and the second pixel layer 53 .
  • the second bonding layer 51 and the third bonding layer 61 are both made of transparent bonding material to facilitate the transmission of light.
  • Transparent bonding materials can be transparent dielectrics, such as organic transparent dielectrics such as SU8, inorganic transparent dielectrics such as SiO 2 , Si 3 N 4 , and sapphire, or semiconductor transparent materials such as ITO, GaAs, GaP, and GaN. wait.
  • any of the above P-type contact layers includes ohmic contact and Schottky contact, and can be a transparent conductive material such as ITO, or a laminate or alloy of metal materials such as Au, Ni, Ag, Mg, Be, Zn, etc. ITO is preferred.
  • the N-type contact layer is made of one or more stacks and alloys of Cr, Al, Ni, Ti, Au, Ge, Au, ITO, ZnO, etc., such as AuGeNiAu, etc.
  • any P-type contact layer is formed by ITO coating on the first compound semiconductor wafer by evaporation, sputtering, etc., and as a preference, the ITO film thickness is 500nm and is formed by high-temperature annealing at 500°C in an N2 environment. Ohmic contact.
  • surface roughening treatment is performed on the surface of the N-type contact layer, including randomly or regularly distributed pits, cones and other structures.
  • the first pixel layer 43 is made of AlGaInP or InGaN red light compound epitaxy
  • the second pixel layer 53 is made of InGaN green light compound epitaxy
  • the third pixel layer 63 is made of InGaN blue light compound epitaxy.
  • the second bonding layer 51 includes a functional layer 511 and a second bonding layer body 512 , and the functional layer 511 is provided between the second bonding layer body 512 and the first pixel layer 43 .
  • the functional layer 511 is at least one of a light screen, a Bragg reflective layer, an ODR structure, and a contact electrode.
  • the functional layer is a filter material, which is disposed on the first N-type contact layer 44. It can be a colored glue of organic material, or a pair of silicon oxide and titanium oxide films of inorganic material. It is characterized by only Allows red light wavelengths to pass through.
  • the pixel unit 100 also includes a first anode electrical connection structure 71, a second anode electrical connection structure 72 and a third anode electrical connection structure 73, And all three are connected to the backplane 10 and electrically connected to the P-type contact layer of the corresponding device layer. That is, the first anode electrical connection structure 71 is electrically connected to the first P-type contact layer 42, the second anode electrical connection structure 72 is electrically connected to the second P-type contact layer 52, and the third anode electrical connection structure 73 is electrically connected to the third P-type contact layer 42. Contact layer 62 electrically connects.
  • the first anode electrical connection structure 71 includes a first partial structure 711 and a second partial structure 712 connected in sequence.
  • the first partial structure 711 is embedded in the first bonding layer 41 and the first P-type contact layer 42, and the first partial structure 711 is embedded in the first bonding layer 41 and the first P-type contact layer 42.
  • One end of the structure 711 is connected to the backplane 10 .
  • a portion of the second partial structure 712 is embedded in the first pixel layer 43 , and the second partial structure 712 is electrically connected to the first P-type contact layer 42 .
  • the end area of the second partial structure 712 is larger than the end area of the first partial structure 711 to form a first flange 713.
  • the first flange 713 is connected to the first P-type contact layer 42 connections.
  • the connection between the first anode electrical connection structure 71 and the second P-type contact layer 52 or the third P-type contact layer 62 can also form a flange structure to improve the connection between the first anode electrical connection structure 71 and each device layer. structural stability.
  • first device layer 40 and the second device layer are epitaxially formed by different compounds
  • first flange 713 and the first P-type contact layer 42 are electrically connected
  • the first anode is electrically connected.
  • Structure 71 is in an insulated state from the P-type contact layers of other device layers.
  • any two flanges provided in the anode electrical connection structure can be electrically connected to the corresponding P-type contact layer respectively.
  • the second anode electrical connection structure 72 includes a second flange 721 that is electrically connected to the second P-type contact layer 52
  • the third anode electrical connection structure 73 includes a third flange 731 that is in contact with the third P-type contact layer 52 .
  • Layer 62 is electrically connected.
  • the first N-type contact layer 44 , the second N-type contact layer 54 and the third N-type contact layer 64 are all convex structures, and the first N-type contact layer 44 is embedded in the second bonding layer 51 .
  • the N-type contact layer 54 is embedded in the third bonding layer 61 .
  • the first N-type contact layer 44 , the second N-type contact layer 54 and the third N-type contact layer 64 are located in the vertical direction of the same backplane 10 , that is, the third N-type contact layer 64 is located on the second N-type contact layer 44 .
  • the second N-type contact layer 54 is located directly above the first N-type contact layer 44 to facilitate the construction of the cathode electrical connection structure and reduce process difficulty.
  • the projection of the first N-type contact layer 44 , the second N-type contact layer 54 and the third N-type contact layer 64 on the backplane 10 is a semicircle with the same center, and from the first N-type contact layer 44 to the third N-type contact layer 64 with increasing radii.
  • the cathode electrical connection structure 30 includes a third partial structure 31 embedded in the second device layer 72 , and one end of the third partial structure 31 is connected to the first N-type contact layer connect.
  • the backplane 10 is not provided with a cathode, and the cathode is provided on the periphery or surface of the display unit.
  • the cathode electrical connection structure 30 also includes a fourth partial structure 32 .
  • One end of the fourth partial structure 32 is connected to the backplane 10 , and the other end passes through the first device layer 71 and the third partial structure 32 .
  • the fourth partial structure 32 is in an insulating state with the backplane 10 and the first device layer 71 .
  • the fourth partial structure 32 is only insulated from the first device layer 71 .
  • the cathode electrical connection structure 30 also includes a fifth partial structure 33 connected to the third partial structure 31 , and the fifth partial structure 33 is embedded in the third device layer 60 .
  • the end area of the fifth partial structure 33 is larger than the end area of the third partial structure 31 to form a fourth flange 34.
  • the fourth flange 4 and the second N contact layer 54 is connected.
  • the pixel unit 100 also includes a passivation layer 80, and the passivation layer 80 is made of transparent insulating material.
  • a portion of the passivation layer 80 is attached to the outer surface of the display unit 20 and the backplane 10 , a portion of the passivation layer 80 is attached between at least one anode electrical connection structure and the display unit 20 , and a portion of the passivation layer 80 is attached to the cathode electrical connection structure. between the connection structure 30 and the display unit 20 .
  • the passivation layer 80 is provided with at least one through hole, and at least one through hole is provided between any anode electrical connection structure and the corresponding P-type contact layer, and at least one through hole is also provided between the cathode electrical connection structure 30 and the corresponding P-type contact layer. between N-type contact layers.
  • this embodiment also provides a method of manufacturing a pixel unit.
  • the manufacturing method includes:
  • Any device layer includes a P-type contact layer, a pixel layer and an N-type contact layer stacked in sequence.
  • the P-type contact layer is located on the side of its corresponding device layer facing the backplane.
  • at least one device layer includes a first device layer, and at least one device layer includes a first device layer.
  • stacking at least one device layer vertically on the backplane in sequence to form a display unit includes:
  • the first N-type contact layer has a protruding structure.
  • At least one device layer also includes a second device layer and a third device layer.
  • the first compound semiconductor wafer has completed P-type ohmic contact.
  • the bonding material is preferably SiO 2 to achieve SiO 2 -SiO 2 bonding.
  • the first compound semiconductor wafer that completes the P-type ohmic contact is covered with a silicon oxide film with a flat surface.
  • the silicon oxide surface roughness Ra is ⁇ 7nm and the film thickness is 10nm to 10000nm.
  • the bonding force needs to be enhanced, it can be The surface is coated with a Si layer of 1 ⁇ 15nm.
  • step S1 also includes:
  • the first device layer uses the first compound semiconductor wafer (red light epitaxy)
  • the second device layer uses the second compound semiconductor wafer (green light epitaxy)
  • the third device layer uses the third compound semiconductor wafer (blue light epitaxy).
  • the compound of the first compound semiconductor wafer is AlGaInP red light system
  • the substrate is preferably N-GaAs
  • Table 1 the structure is shown in Table 1 below:
  • the compounds of the second compound semiconductor wafer and the third compound semiconductor wafer are InGaN system, and the substrates are Si and GaN respectively.
  • the corresponding structures are shown in Tables 2 and 3 below:
  • Step S3 specifically includes:
  • step S32 is performed.
  • the backplane is provided with a cathode pad, and the above-mentioned step S33 is performed, and the cathode electrical connection channel is extended to the backplane to facilitate the connection between the subsequently constructed cathode electrical connection structure and the cathode pad.
  • the cathode electrical connection structure is electrically connected to the N-type contact layer of any of the device layers, and any anode electrical connection structure is electrically connected to the P-type contact layer of the corresponding device layer.
  • step S4 includes:
  • this embodiment provides a pixel unit and a manufacturing method thereof, a micro display screen, and a discrete device.
  • the pixel unit includes a backplane, a display unit, a cathode electrical connection structure, and at least one anode electrical connection structure.
  • the display unit is located on the back panel.
  • the cathode electrical connection structure and at least one anode electrical connection structure are respectively embedded in the display unit from the side surface away from the back plate;
  • the display unit includes at least one device layer, and at least one device layer is stacked vertically in sequence, any one
  • the device layer includes a P-type contact layer, a pixel layer and an N-type contact layer stacked in sequence.
  • the P-type contact layer is located on the side of its device layer facing the backplane; any anode electrical connection structure and the P-type contact layer of the corresponding device layer Electrically connected, the cathode electrical connection structure is electrically connected to the N-type contact layer of any device layer; the pixel unit provided in this embodiment achieves color display by integrating at least two device layers vertically stacked sequentially on the backplane. Compared with the integrated pixel structure arranged in the horizontal direction, the pixel unit in this embodiment occupies less space in the horizontal direction, achieving ultra-high-density color Micro-LED display, thereby achieving a smaller display at the same resolution. screen size or higher resolution at the same screen size; and, this application achieves an increase in the area ratio of the light-emitting area by sharing the same negative electrical connection structure with multiple device layers in the vertical direction, reducing the impact of the size effect;
  • the first anode electrical connection structure includes a first partial structure and a second partial structure connected in sequence, a connection point between the first partial structure and the second partial structure, and an end area of the second partial structure is greater than an end area of the first partial structure to form
  • the first flange, the pixel unit also includes a passivation layer, part of the passivation layer is attached to the outer surface of the display unit and the backplane, part of the passivation layer is attached between at least one anode electrical connection structure and the display unit, part of the passivation layer
  • the chemical layer is attached between the cathode electrical connection structure and the display unit.
  • the anode electrical connection structure constructs a flange structure by changing the diameter to realize the anode electrical connection structure and the P-type contact layer, or the cathode electrical connection structure and the P-type contact layer. Electrical connection between N-type contact layers, thereby simplifying the structure and reducing process difficulty;
  • the manufacturing method of the pixel unit includes preparing a backplane; stacking at least one device layer vertically on the backplane in sequence to form a display unit, and any device layer includes a P-type contact layer stacked in sequence, The pixel layer and the N-type contact layer, the P-type contact layer is located on the side of the device layer facing the backplane; the cathode electrical connection channel and at least one anode electrical connection channel are constructed by etching inward from the surface of the side of the display unit away from the backplane ; The cathode electrical connection channel and at least one anode electrical connection channel are filled with metal to form a cathode electrical connection structure and at least one anode electrical connection structure; the cathode electrical connection structure is electrically connected to the N-type contact layer of any device layer, and any The anode electrical connection structure is electrically connected to the P-type contact layer of the corresponding device layer; the pixel manufacturing method in this embodiment adopts a stacking first and then patterning scheme
  • this embodiment further provides a microdisplay screen 200.
  • the microdisplay screen 200 includes:
  • the driving backplane 210 includes a driving circuit and an input and output interface 211.
  • the display area 220 is provided on the driving backplane 210 and includes at least two display units 20 as described in Embodiment 1.
  • the at least two display units 100 are arranged in an array.
  • the peripheral common cathode 230 is arranged around the circumference of the display area 220 , and the peripheral common cathode 230 is respectively connected to the cathode electrical connection structure of any display unit 100 .
  • the insulation layer 240 is provided on the surface of the display area 220 .
  • the transparent conductive layer 250 is provided on the outer surface of the insulating layer 240, and the insulating layer 240 is provided with at least one hollow.
  • the cathode electrical connection structure 30 is connected to the transparent conductive layer 250 through the hollow of the insulating layer 240; and, the transparent conductive layer 250 is connected to the periphery
  • the common cathode 230 is connected to realize the connection between each pixel unit and the cathode electrode.
  • the microdisplay 200 provided in this embodiment based on the technical effects of the pixel unit provided in Embodiment 1, realizes the structure of the cathode electrode by providing a transparent conductive layer, simplifying the etching steps in the pixel unit and At the same time, the impact on the device layer during the etching process is avoided, effectively improving the yield of pixel units and micro-displays.
  • this embodiment further provides a discrete device 300.
  • the discrete device 300 includes:
  • the device body 320 is provided on the discrete backplane 310, and the device body 320 includes at least two display units 20 as in Embodiment 1, and the at least two display units 20 are arranged in an array;
  • At least two pads include one cathode pad 330 and at least one anode pad. At least part of the cathode pad 330 and at least part of any anode pad are respectively embedded in the discrete backplane 310. Any anode is electrically
  • the connection structure is connected to the corresponding anode pad, and the cathode electrical connection structure 30 is connected to the corresponding cathode pad 330 .
  • At least one anode pad includes: a first anode pad 340 connected to the first device layer 40 , a second anode pad 350 connected to the second device layer 50 , and a third anode pad connected to the third device layer 60 .
  • the device body 320 is provided separately from the discrete device backplane 310 , and at least two bonding pads are provided separately from the discrete device backplane 310 .
  • the passivation layer 81 includes a fixing portion 81 , the fixing portion 81 is connected to the discrete device backplane 310 , and is used to connect the device body 320 to the discrete device backplane 310 .
  • the sacrificial layer 370 is pre-disposed between the discrete backplane 310 and the device body 320, the discrete backplane 310 and at least one pad, and then the sacrificial layer 370 is removed.
  • this embodiment also provides a manufacturing method of the discrete device, the manufacturing method includes:
  • a sacrificial layer on the discrete backplane with at least four cavities; the sacrificial layer uses a silicon oxynitride film and is formed on the surface of the discrete backplane through coating, thermal oxidation, wet oxidation, etc.
  • S103 Construct at least four pads on one side of the discrete backplane plated with the sacrificial layer. Part of each pad is embedded in a corresponding cavity.
  • the at least four pads include one cathode pad and at least three Anode pad.
  • the bonding pad in this embodiment is a metal bonding pad, which can be one or more alloys or laminates of gold, titanium, tungsten, aluminum, and platinum.
  • the preparation methods include thermal evaporation, sputtering, electroplating, or chemical plating.
  • the pad can be solid or hollow.
  • This step S20 includes:
  • S203 Passivate the outer surface of the device body and the discrete device backplane, the inner wall of the cathode electrical connection channel and at least one anode electrical connection channel to form a passivation layer, and open at least one through hole through patterned etching.
  • a through hole is provided between any anode electrical connection structure and the corresponding P-type contact layer, and at least one through hole is provided between the cathode electrical connection structure and the discrete device backplane.
  • the passivation layer covers part of the discrete backplane, and the passivation layer forms a fixed portion at the connection between the device body and the discrete backplane.
  • the fixed portion realizes the connection between the device main body and the discrete backplane.
  • the sacrificial layer is etched on one side surface of the discrete backplane that is not plated with the passivation layer to separate at least four pads from the discrete backplane; etching of the sacrificial layer and the discrete backplane
  • the rate ratio is greater than 10:1
  • the etching rate ratio of the sacrificial layer and the passivation layer is greater than 10:1.
  • the gap between the discrete device backplane and the device body after etching is 100 nm to 1000 nm, preferably 300 to 500 nm.
  • the discrete device in this embodiment is connected to an external circuit based on at least two pads. After the discrete device is packaged on the target backplane, it is electrically When connecting, metal welding such as eutectic can be avoided to avoid affecting the performance of the discrete device itself and simplify the process; and, in this embodiment, the device body is separated from the discrete backplane, and at least four pads are separated from the discrete backplane Setting;
  • the pixel-level discrete device also includes an isolation support structure.
  • the isolation support structure covers the device body and part of the discrete backplane.
  • the pixel discrete device achieves structural stability and stability under the separation setting of the device body and the backplane by setting the isolation support structure. It is convenient for later use, and the backplane of the discrete device can be recycled under this structure, effectively reducing costs.

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Abstract

本申请提供一种像素单元及其制作方法、微显示屏、分立器件，该像素单元包括背板、显示单元、阴极电气连接结构及至少一个阳极电气连接结构，显示单元包括至少一个器件层，至少一个器件层依次垂直堆叠，任一器件层包括依次堆叠的P型接触层、像素层及N型接触层，P型接触层位于其所属器件层朝向背板的一侧；任一阳极电气连接结构与相应器件层的P型接触层电连接，阴极电气连接结构与任一器件层的N型接触层分别电连接；本申请提供的像素单元通过在背板上依次垂直堆叠集成至少两层器件层的方式实现彩色化显示，相较于水平方向排布集成的像素结构，本申请中像素单元在水平方向上所占的空间较小，实现超高密度的彩色化显示。

Description

一种像素单元及其制作方法、微显示屏、分立器件 技术领域
本申请涉及半导体器件技术领域，尤其涉及一种像素单元及其制作方法、微显示屏、分立器件。
背景技术
Micro-LED显示相比现有的LCD、OLED等显示技术具备诸多优点，被普遍认为是下一代显示技术核心，在手表、电视、投影、虚拟现实、增强现实，混合现实等多领域具有很大的应用前景，但是这些应用需求在芯片制造、尺寸、结构、良率、驱动等方面都提出了新的需求，传统的LED制备方案难以匹配，需要进行高度整合才可能满足需求。
在Micro-LED领域，彩色化是一个非常大的挑战，目前主流的Micro-LED彩色化技术包括：三原色、色转换、棱镜合光等方案，其彩色化实现基本基于平面结构上三色，对于进一步压缩器件尺寸，进行超高密度的像素阵列显示存在一定挑战。
使用传统的LED芯片和显示制备方案目前还能兼容Mini LED，但是Micro-LED因为尺寸和厚度均在微米量级，较传统动辄几百、几千微米的LED量级差异较大，且在使用时涉及到的芯片数量巨大，难以使用传统方案作业。以手机屏幕为例，1080P分辨率的一块手机屏幕，拥有超过200万颗像素(1920*1080)，而每个像素由红、绿、蓝三颗子像素构成，即一块1080P分辨率的手机屏幕需要超过600万颗LED，以传统LED芯片而言，每秒钟转移一颗芯片，完成这样一块屏幕需要接近一年的时间，成本极其昂贵。
目前针对Micro-LED芯片，主流存在巨量转移和单片集成两种方案：巨量转移(Mass transfer)使用类传统方案的拾取和安置手段(Pick and place)，但不同区传统LED方案一次性拾取一颗或几颗，巨量转移一次性拾取大量的芯片进行转移；单片集成(Monolithic Integration)是指形成密集排列的LED矩阵区域或者整片晶圆的LED整列后，将金属触点对准键合 到驱动上的一种方案，具备更高密度的集成度。
目前关于实现彩色化Micro-LED显示芯片的方案主要有巨量转移集成、非对准键合的水平显示(如已公开中国专利CN110462850A)、对准键合的垂直显示。目前已公开的巨量转移集成、非对准键合的水平显示技术普遍存在空间浪费以及像素内光学串扰的问题。空间浪费体现在红绿蓝三色水平布局，显示像素密度损失。而对准键合垂直堆叠集成，对于对准要求极高，成本和代价昂贵，且对准精度难以保证，如部分文献中提到在像素尺寸增大或减小1μm时，在进行超小像素的制备时，对准偏差难以接受，并且因为是先制备单色器件，器件本身存在台阶差，在键合过程中容易因台阶差出现阵列裂纹或断开，影响良率。
因此，我们需要寻找一种具有较高像素密度的微小尺寸像素单元。
申请内容
本申请的目的在于提供一种像素单元及其制作方法、微显示屏、分立器件，其能实现超高密度的、微米量级的彩色化显示。
为实现上述申请目的，本申请第一方面提出一种像素单元，所述像素单元包括背板、显示单元、阴极电气连接结构及至少一个阳极电气连接结构，所述显示单元设于所述背板上，所述阴极电气连接结构及所述至少一个阳极电气连接结构分别自远离所述背板的一侧表面向内嵌设于所述显示单元中；
所述显示单元包括至少一个器件层，所述至少一个器件层依次垂直堆叠，任一所述器件层包括依次堆叠的P型接触层、像素层及N型接触层，所述P型接触层位于其所属器件层朝向所述背板的一侧；
任一所述阳极电气连接结构与相应所述器件层的P型接触层电连接，所述阴极电气连接结构与任一所述器件层的N型接触层分别电连接。
在一种较佳的实施方式中，任一所述阳极电气连接结构与所述背板连接；
所述至少一个阳极电气连接结构包括第一阳极电气连接结构，所述第一阳极电气连接结构包括依次连接的第一部分结构及第二部分结构；
所述至少一个器件层包括第一器件层，所述第一器件层包括依次堆叠 的第一键合层、第一P型接触层、第一像素层及第一N型接触层，所述第一P型接触层位于所述第一器件层靠近所述背板的一侧；
所述第一部分结构嵌设于所述第一键合层及所述第一P型接触层中，部分所述第二部分结构嵌设于所述第一像素层中，且所述第二部分结构与所述第一P型接触层电连接。
在一种较佳的实施方式中，所述第二部分结构的端面积大于所述第一部分结构的端面积，以在两者的连接处形成第一凸缘；
所述第一凸缘与所述第一P型接触层连接。
在一种较佳的实施方式中，所述至少一个阳极电气连接结构还包括第二阳极电气连接结构；
所述显示单元还包括第二器件层，所述第二器件层叠设于所述第一器件层远离所述背板的一侧表面，所述第二器件层包括依次堆叠的第二键合层、第二P型接触层、第二像素层及第二N型接触层，所述第二键合层与所述第一像素层连接；
所述第二阳极电气连接结构包括第二凸缘，所述第二凸缘与所述第二P型接触层连接。
在一种较佳的实施方式中，所述第二N型接触层设于所述第一N型接触层的正上方。
在一种较佳的实施方式中，所述第一N型接触层为凸起结构，所述第一N型接触层嵌设于所述第二键合层中。
在一种较佳的实施方式中，所述阴极电气连接结构包括第三部分结构，所述第三部分结构嵌设于所述第二器件层中，且所述第三部分结构一端与所述第一N型接触层连接。
在一种较佳的实施方式中，所述阴极电气连接结构还包括第四部分结构，所述第四部分结构一端与所述背板连接，另一端穿过所述第一器件层与所述第三部分结构连接。
在一种较佳的实施方式中，所述第二键合层包括第二键合层本体及功能层，所述功能层设于所述第二键合层本体及所述第一像素层之间。
在一种较佳的实施方式中，所述至少一个阳极电气连接结构还包括第三阳极电气连接结构；
所述显示单元还包括第三器件层，所述第三器件层叠设于所述第二器件层远离所述第一器件层的一侧表面，所述第三器件层包括依次堆叠的第三键合层、第三P型接触层、第三像素层及第三N型接触层，所述第三键合层与所述第二像素层连接；
所述第三阳极电气连接结构包括第三凸缘，所述第三凸缘与所述第三P型接触层连接。
在一种较佳的实施方式中，所述阴极电气连接结构还包括与所述第三部分结构连接的第五部分结构，所述第五部分结构嵌设于所述第三器件层中；
所述第五部分结构的端面积大于所述第三部分结构的端面积，以在两者的连接处形成第四凸缘；
所述第四凸缘与所述第二N型接触层连接。
在一种较佳的实施方式中，所述第二N型接触层为凸起结构，所述第二N型接触层嵌设于所述第三键合层中。
在一种较佳的实施方式中，所述第二键合层及所述第三键合层均采用透明材质。
在一种较佳的实施方式中，所述像素单元还包括钝化层，部分所述钝化层贴设于所述显示单元及所述背板的外表面，部分所述钝化层贴设于所述至少一个阳极电气连接结构与所述显示单元之间，部分所述钝化层贴设于所述阴极电气连接结构与所述显示单元之间。
在一种较佳的实施方式中，所述钝化层开设有至少一个通孔，所述至少一个通孔设于任一阳极电气连接结构与相应的P型接触层之间，以及，所述阴极电气连接结构与相应的N型接触层之间。
在一种较佳的实施方式中，所述钝化层采用透明绝缘材料。
在一种较佳的实施方式中，所述第一像素层为AlGaInP或InGaN红光化合物外延，所述第二像素层为InGaN绿光化合物外延，所述第三像素层为InGaN蓝光化合物外延。
第二方面，提供一种像素单元的制作方法，所述制作方法包括：
准备背板；
在所述背板上依次垂直堆叠至少一个器件层以形成显示单元，任一所 述器件层包括依次堆叠的P型接触层、像素层及N型接触层，所述P型接触层位于其所属器件层朝向所述背板的一侧；
自所述显示单元远离所述背板的一侧表面向内刻蚀构造阴极电气连接通道及至少一个阳极电气连接通道；
对所述阴极电气连接通道及所述至少一个阳极电气连接通道进行金属填充以形成阴极电气连接结构及至少一个阳极电气连接结构；所述阴极电气连接结构与任一所述器件层的N型接触层分别电连接，任一所述阳极电气连接结构与相应所述器件层的P型接触层电连接。
在一种较佳的实施方式中，所述至少一个器件层包括第一器件层，所述在所述背板上依次垂直堆叠至少一个器件层以形成显示单元，包括：
在所述背板表面、预先准备的第一化合物半导体晶圆的P型接触层表面分别镀键合材料并键合形成第一键合层；
去除所述第一化合物半导体晶圆的衬底并进行化合物半导体减薄露出第一N型接触层，所述第一N型接触层为凸起结构。
在一种较佳的实施方式中，所述至少一个器件层还包括第二器件层及第三器件层；在完成第一器件层后，所述在所述背板上依次垂直堆叠至少一个器件层以形成显示单元，还包括：
在所述第一器件层远离所述背板的一侧表面依次垂直堆叠第二器件层及第三器件层，以形成所述显示单元。
在一种较佳的实施方式中，所述自所述显示单元远离所述背板的一侧表面向内刻蚀构造阴极电气连接通道及至少一个阳极电气连接通道，包括：
采用图形化干法刻蚀自所述显示单元远离所述背板的一侧表面向内部逐层进行初步深刻蚀；
采用图形化湿法刻蚀对完成初步深刻蚀的所述显示单元进行深刻蚀，刻蚀至暴露背板以形成至少一个阳极电气连接通道，刻蚀至暴露相应的N型接触层以形成所述阴极电气连接通道。
在一种较佳的实施方式中，所述自所述显示单元远离所述背板的一侧表面向内刻蚀构造阴极电气连接通道及至少一个阳极电气连接通道，包括：
采用图形化干法刻蚀自所述显示单元远离所述背板的一侧表面向内部逐层进行初步深刻蚀；
采用图形化湿法刻蚀对完成初步深刻蚀的所述显示单元进行深刻蚀，刻蚀至暴露所述背板以形成所述阴极电气连接通道及至少一个阳极电气连接通道。
在一种较佳的实施方式中，所述对所述阴极电气连接通道及所述至少一个阳极电气连接通道进行金属填充以形成阴极电气连接结构及至少一个阳极电气连接结构，包括：
对所述显示单元及所述背板的外表面、所述阴极电气连接通道及所述至少一个阳极电气连接通道的内壁进行钝化形成钝化层，并通过图形化刻蚀的方式开设至少一个通孔，所述至少一个通孔设于任一阳极电气连接结构与相应的P型接触层之间，以及，所述至少一个通孔设于所述阴极电气连接结构与相应的N型接触层之间；
采用溅射、电镀、化镀或蒸镀对所述阴极电气连接通道及所述至少一个阳极电气连接通道进行金属填充以构造所述阴极电气连接结构及至少一个阳极电气连接结构。
第三方面，提供一种微显示屏，所述微显示屏包括：
驱动背板，所述驱动背板包括驱动电路及输入输出接口；
显示区域，所述显示区域设于所述驱动背板上，且所述显示区域包括至少两个第一方面任意一项所述的显示单元，至少两个所述显示单元呈阵列式排布；
外围共阴极，所述外围共阴极围设于所述显示区域周向，且所述外围共阴极与任一所述显示单元的阴极电气连接结构分别连接。
在一种较佳的实施方式中，所述背板集成有驱动电路；
对应于任一所述像素单元，所述驱动电路包括至少一个阳极，任一所述阳极电气连接结构与相应的阳极电连接。
在一种较佳的实施方式中，所述微显示屏还包括从内至外依次贴设在所述显示区域表面的绝缘层及透明导电层，所述透明导电层与所述外围共阴极连接；
所述绝缘层开设有至少一个镂空，所述阴极电气连接结构通过所述绝缘层的镂空与所述透明导电层连接。
第四方面，提供一种分立器件，所述分立器件包括：
分立器背板；
器件主体，所述器件主体设于所述分立器背板上，且所述器件主体包括至少两个如第一方面任意一项所述的显示单元，至少两个所述显示单元呈阵列式排布；
至少两个焊盘，包括一个阴极焊盘及至少一个阳极焊盘，任一所述阳极焊盘的至少部分及所述阴极焊盘的至少部分分别嵌设于所述分立器背板中，任一所述阳极电气连接结构与相应的阳极焊盘连接，所述阴极电气连接结构与相应的阴极焊盘连接。
与现有技术相比，本申请具有如下有益效果：
本申请提供一种像素单元及其制作方法、微显示屏、分立器件，该像素单元包括背板、显示单元、阴极电气连接结构及至少一个阳极电气连接结构，显示单元设于背板上，阴极电气连接结构及至少一个阳极电气连接结构分别自远离背板的一侧表面向内嵌设于显示单元中；显示单元包括至少一个器件层，至少一个器件层依次垂直堆叠，任一器件层包括依次堆叠的P型接触层、像素层及N型接触层，P型接触层位于其所属器件层朝向背板的一侧；任一阳极电气连接结构与相应器件层的P型接触层电连接，阴极电气连接结构与任一器件层的N型接触层分别电连接；本申请提供的像素单元通过在背板上依次垂直堆叠集成至少两层器件层的方式实现彩色化显示，相较于水平方向排布集成的像素结构，本申请中像素单元在水平方向上所占的空间较小，实现超高密度的彩色化Micro-LED显示，从而实现同分辨率下更小的显示屏尺寸或者同屏幕尺寸下更高的分辨率；以及，本申请通过垂直方向上的多个器件层共用同一负极电气连接结构的方式实现发光区域面积占比的提高，减小了尺寸效应影响；
进一步，第一阳极电气连接结构包括依次连接的第一部分结构及第二部分结构，第二部分结构的端面积大于第一部分结构的端面积，以在两者的连接处形成第一凸缘，像素单元还包括钝化层，部分钝化层贴设于显示单元及背板的外表面，部分钝化层贴设于至少一个阳极电气连接结构与显示单元之间，部分钝化层贴设于阴极电气连接结构与显示单元之间，本申请中的阳极电气连接结构通过直径变化构造凸缘结构，以实现阳极电气连 接结构与P型接触层，或阴极电气连接结构与N型接触层之间的电气连接，从而简化结构，降低工艺难度；
以及，本申请提供的像素单元的制作方法，其制作方法包括准备背板；在背板上依次垂直堆叠至少一个器件层以形成显示单元，任一器件层包括依次堆叠的P型接触层、像素层及N型接触层，P型接触层位于其所属器件层朝向背板的一侧；自显示单元远离背板的一侧表面向内刻蚀构造阴极电气连接通道及至少一个阳极电气连接通道；对阴极电气连接通道及至少一个阳极电气连接通道进行金属填充以形成阴极电气连接结构及至少一个阳极电气连接结构；阴极电气连接结构与任一器件层的N型接触层分别电连接，任一阳极电气连接结构与相应器件层的P型接触层电连接；本申请中的像素单元的制作方法采用先堆叠后图形化的方案，利用半导体工艺免去了对准键合的高昂成本，避免了对准精度偏差，在工艺上实现更小尺寸像素的堆叠，降低工艺难度，节省工艺成本；
需要说明的是，本申请仅需实现上述至少一种技术效果即可。
附图说明
图1是实施例1中像素单元的俯视图；
图2是图1中A-B截面的剖视图；
图3是实施例1、3的分立器件所包括的最小发光单元的俯视图；
图4是图3中C-D截面的剖视图；
图5是图3中包括牺牲层时C-D截面的剖视图；
图6是微显示屏的俯视图；
图7～9是实施例1中背板包括的三种示例性电路结构示意图；
图10是任意一层器件层的电路结构示意图。
附图标记：
100-像素单元，10-驱动背板，20-显示单元，30-阴极电气连接结构，31-第三部分结构，32-第四部分结构，33-第五部分结构，40-第一器件层，41-第一键合层，42-第一P型接触层，43-第一像素层，44-第一N型接触层，50-第二器件层，51-第二键合层，511-功能层，512-第二键合层本体，52-第二P型接触，53-第二像素层，54-第二N型接触层，60-第三器件层，61-第三键合层，62-第三P型接触层，63-第三像素层，64-第三N型接触层，71- 第一阳极电气连接结构，711-第一部分结构，712-第二部分结构，713-第一凸缘，72-第二阳极电气连接结构，721-第二凸缘，73-第三阳极电气连接结构，731-第三凸缘，80-钝化层，81-固定部，200-微显示屏，210-驱动背板，211-输入输出接口，220-显示区域，230-外围共阴极，240-绝缘层，250-透明导电层，300-分立器件，310-分立器背板，320-器件主体，330-阴极焊盘，340-第一阳极焊盘，350-第二阳极焊盘，360-第三阳极焊盘。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
实施例1
如图1、2所示，本实施例提供一种像素单元100，该像素单元可作为如图3～5所示分立器件300的最小发光单元，也可以作为如图6所示的微显示屏 200的最小发光单元。
参照图2所示，该像素单元100包括背板10、显示单元20、阴极电气连接结构30及至少一个阳极电气连接结构。其中，显示单元20设于背板10上，阴极电气连接结构30及至少一个阳极电气连接结构分别自远离背板10的一侧表面向内嵌设于显示单元20中。任一阳极电气连接结构与背板10连接。
显示单元20包括至少一个器件层，且至少一个器件层在垂直于背板10的方向上依次垂直堆叠，形成晶圆级垂直堆叠像素(Wafer Level Vertical Stack Pixel)，简称WLVSP。任一器件层包括依次堆叠的P型接触层、像素层及N型接触层，P型接触层位于其所属器件层朝向背板10的一侧。任一阳极电气连接结构与相应器件层的P型接触层电连接，阴极电气连接结构与任一器件层的N型接触层分别电连接。为此，作为优选的，本实施例中的像素单元包括地阳极电气连接结构的数量与器件层的数量相对应。
本实施例对于显示单元20所包括的器件层数量不作限制，可以为一层、两层、三层甚至更多。当器件层的数量不小于两层时，任意两层器件层所分别包括的发光化合物外延可以相同或不同。当任意两层器件层所包括的发光化合物外延相同时，实现相同颜色光源亮度的提升，或形成备用冗余器件层以提高像素单元的良率。当任意两层器件层所包括的发光化合物外延不同时，实现彩色化显示，如全彩显示，如红绿蓝三原色像素。
为了便于描述，本实施例以该像素单元100为红绿蓝三原色像素为例作进一步的示例性描述。显示单元20包括发出红光的第一器件层40、发出绿光的第二器件层50及发出蓝光的第三器件层60。
需要说明的是，本实施例中的任一器件层可以是四边形、六边形、八边形、圆形等常见图形或者图形的组合，本实施例对此不作进一步的限定。
具体的，背板10为无源背板或集成有驱动电路的有源背板。当该像素单元用于微显示屏时，该背板10优选为有源背板，驱动电路设有至少一个阳极，薄膜晶体管(TFT)、LTPS低温多晶硅、CMOS集成电路、高迁移率晶体管HEMT等一种或几种的有源驱动背板以及半有源驱动背板。如，选取CMOS集成电路背板，其在的R、G、B分别对应阳极表面设有顶部金属(Top metal)。CMOS集成电路背板的驱动电路的电路图如图7～9所示，其中，图8和图9分别为先堆叠两层红光器件层，再堆叠为绿光器件层及蓝 光器件层，两层红光器件层可以为并联或串联。每一器件层的电路可包含主动式、被动式或半被动式的控制电路，示例性电路如图10所示。需要说明的是，本实施例中的电路图仅为简单的示意图。本实施例中的至少一个阳极可以是排布于同一直线上、呈品字形排布或者阵列式排布，任一阳极位于驱动背板10的中间或者边缘，本实施例对此均不做限制。当该像素单元用于分立器件时，该背板优选为无源背板，背板优选采用PCB、蓝宝石、玻璃、Si等材料，无源背板通过下游封装工艺实现与电源的连接。
进一步如图2、4所示，第一器件层40包括依次堆叠的第一键合层41、第一P型接触层42、第一像素层43及第一N型接触层44，第一P型接触层42位于第一器件层40靠近背板10的一侧。第二器件层50叠设于第一器件层40远离背板10一侧表面，第二器件层50包括依次堆叠的第二键合层51、第二P型接触层52、第二像素层53及第二N型接触层54，第二键合层51与第一像素层43连接。第三器件层60叠设于第二器件层50远离第一器件层40的一侧表面，第三器件层60包括依次堆叠的第三键合层61、第三P型接触层62、第三像素层63及第三N型接触层64，第三键合层61与第二像素层53连接。
作为优选，第二键合层51及第三键合层61均采用透明键合材料，以便于光线的透出。透明键合材料可以为透明介电质，如SU8等有机物透明介电质，SiO 2、Si 3N 4、蓝宝石等无机物透明介电质，或者半导体透明材料，如ITO、GaAs、GaP、GaN等。
上述的任一P型接触层包括欧姆接触和肖特基接触，可以是ITO等透明导电材料，也可以是Au、Ni、Ag、Mg、Be、Zn等金属材料的叠层或者合金，优选ITO。N型接触层采用Cr、Al、Ni、Ti、Au、Ge、Au、ITO、ZnO等的一种或几种的堆叠及合金制成，如AuGeNiAu等。作为优选，任一P型接触层通过蒸镀、溅射等方式对第一化合物半导体晶圆进行ITO镀膜形成，且作为一种优选，ITO膜厚500nm，通过N 2环境下500℃高温退火形成欧姆接触。
作为一种优选，在N型接触层表面进行表面糙化处理，包括随机或规律分布的凹坑、锥突等结构。
优选的，第一像素层43为AlGaInP或InGaN红光化合物外延，第二像素层53为InGaN绿光化合物外延，第三像素层63为InGaN蓝光化合物外延。
作为一种优选，第二键合层51包括功能层511及第二键合层本体512，功能层511设于第二键合层本体512及第一像素层43之间。功能层511为光筛、布拉格反射层、ODR结构、接触电极中的至少一种。优选的，该功能层为滤光材料，设于第一N型接触层44上，可以是有机材料的有色胶，也可以是无机材料的氧化硅及氧化钛薄膜的谍对，其特点为仅允许红光波长穿过。
对应于第一器件层40、第二器件层50及第三器件层60，该像素单元100还包括第一阳极电气连接结构71、第二阳极电气连接结构72及第三阳极电气连接结构73，且三者均与背板10连接，且与相应器件层的P型接触层电连接。即，第一阳极电气连接结构71与第一P型接触层42电连接，第二阳极电气连接结构72与第二P型接触层52电连接，第三阳极电气连接结构73与第三P型接触层62电连接。
具体的，第一阳极电气连接结构71包括依次连接的第一部分结构711及第二部分结构712，第一部分结构711嵌设于第一键合层41及第一P型接触层42，且第一部分结构711一端与背板10连接。部分第二部分结构712嵌设于第一像素层43中，且第二部分结构712与第一P型接触层42电连接。第一部分结构711第二部分结构712的连接处，第二部分结构712的端面积大于第一部分结构711的端面积，以形成第一凸缘713，第一凸缘713与第一P型接触层42连接。当然，第一阳极电气连接结构71与第二P型接触层52或第三P型接触层62的连接处同样可以形成凸缘结构，以提高第一阳极电气连接结构71与每一器件层之间的结构稳定性。然而需要说明的是，在第一器件层40与第二器件层为不同的化合物外延前提下，当第一凸缘713与第一P型接触层42为电连接状态，则第一阳极电气连接结构71与其余器件层的P型接触层均为绝缘状态。当然，当任意两个器件层具有相同的化合物外延时，阳极电气连接结构所设置任意两个凸缘可以分别与相应的P型接触层电连接。同样的，第二阳极电气连接结构72包括第二凸缘721，其与第二P型接触层52电连接，第三阳极电气连接结构73包括第三凸缘731，其与第三P型接触层62电连接。
第一N型接触层44、第二N型接触层54及第三N型接触层64均为凸起结构，且第一N型接触层44嵌设于第二键合层51中，第二N型接触层54嵌设于 第三键合层61中。优选的，第一N型接触层44、第二N型接触层54及第三N型接触层64位于同一背板10的垂直方向上，即第三N型接触层64位于第二N型接触层54的正上方，第二N型接触层54位于第一N型接触层44的正上方，以便阴极电气连接结构的构造，降低工艺难度。进一步的，第一N型接触层44、第二N型接触层54及第三N型接触层64在背板10上的投影为具有同一圆心的半圆形，且从第一N型接触层44至第三N型接触层64的半径递增。
在一种具体的实施方式中，阴极电气连接结构30包括第三部分结构31，第三部分结构31嵌设于第二器件层72中，且第三部分结构31一端与第一N型接触层连接。该结构下，当该像素单元用于微显示屏时，背板10不设置阴极，阴极设于显示单元外围或表面。
在此基础上的另一可选实施方式中，阴极电气连接结构30还包括第四部分结构32，第四部分结构32一端与背板10连接，另一端穿过第一器件层71与第三部分结构31连接。当该像素单元100用于微显示屏时，第四部分结构32与背板10、第一器件层71均为绝缘状态。当该像素单元100用于分立器件时，第四部分结构32仅与第一器件层71相绝缘。
进一步的，阴极电气连接结构30还包括与第三部分结构31连接的第五部分结构33，第五部分结构33嵌设于第三器件层60中。第五部分结构33与第三部分结构31的连接处，第五部分结构33的端面积大于第三部分结构31的端面积，以形成第四凸缘34，第四凸缘4与第二N型接触层54连接。
在上述结构基础上，该像素单元100还包括钝化层80，钝化层80采用透明绝缘材料。部分钝化层80贴设于显示单元20及背板10的外表面，部分钝化层80贴设于至少一个阳极电气连接结构与显示单元20之间，部分钝化层80贴设于阴极电气连接结构30与显示单元20之间。钝化层80开设有至少一个通孔，至少一个通孔设于任一阳极电气连接结构与相应的P型接触层之间，以及，至少一个通孔还设于阴极电气连接结构30与相应的N型接触层之间。
对应于上述像素单元100，本实施例还提供一种像素单元的制作方法，该制作方法包括：
S1、准备背板。
S2、在背板上依次垂直堆叠至少一个器件层以形成显示单元。
任一器件层包括依次堆叠的P型接触层、像素层及N型接触层，P型接触层位于其所属器件层朝向背板的一侧。具体的，至少一个器件层包括第一器件层，至少一个器件层包括第一器件层。
进一步，在背板上依次垂直堆叠至少一个器件层以形成显示单元，包括：
S11、在背板表面、预先准备的第一化合物半导体晶圆的P型接触层表面分别镀键合材料并键合形成第一键合层；
S12、去除第一化合物半导体晶圆的衬底并进行化合物半导体减薄露出第一N型接触层，第一N型接触层为凸起结构。
进一步的，至少一个器件层还包括第二器件层及第三器件层。
上述，第一化合物半导体晶圆已完成P型欧姆接触。键合材料优选SiO 2，实现SiO 2-SiO 2键合。具体为，在完成P型欧姆接触的第一化合物半导体晶圆上覆盖表面平坦的氧化硅薄膜，其氧化硅表面粗糙度Ra＜7nm，膜厚10nm～10000nm，在需要增强键合力的时候可在表面镀膜1～15nm的Si层。
在完成第一器件层后，步骤S1还包括：
S13、在第一器件层远离背板的一侧表面依次垂直堆叠第二器件层及第三器件层，以形成显示单元。当然，第二器件层与第三器件层的堆叠方式与第一键合层堆叠方式一致，对此不作赘述。
上述，第一器件层采用第一化合物半导体晶圆(红光外延)，第二器件层采用第二化合物半导体晶圆(绿光外延)，第三器件层采用第三化合物半导体晶圆(蓝光外延)。
需要说明的是，第一化合物半导体晶圆的化合物为AlGaInP红光体系，衬底优选N-GaAs，结构如下表1所示：
表1
Layer name Material
P contact P-GaAs
MQW AlGaInP
N contact N-AlGaInP
Etch Stop N-AlGaInP
Substrate N-GaAs
第二化合物半导体晶圆及第三化合物半导体晶圆的化合物为InGaN体系，衬底分别为Si、GaN，相应的结构如下表2、3所示：
表2
Layer name Material
P contact P-GaAs
MQW InGaN&GaN
N contact GaN
Etch Stop AlN&GaN
Substrate Si
表3
Layer name Material
P contact P-GaN
MQW InGaN&GaN
N contact GaN
Etch Stop InGaN
Substrate GaN
S3、自所述显示单元远离所述背板的一侧表面向内刻蚀构造阴极电气连接通道及至少一个阳极电气连接通道。
步骤S3具体的包括：
S31、采用图形化干法刻蚀自所述显示单元远离所述背板的一侧表面向内部逐层进行初步深刻蚀；
S32、采用图形化湿法刻蚀对完成初步深刻蚀的显示单元进行深刻蚀，刻蚀至暴露背板以形成至少一个阳极电气连接通道，刻蚀至暴露相应的N型接触层以形成所述阴极电气连接通道。
S33、采用图形化湿法刻蚀对完成初步深刻蚀的显示单元进行深刻蚀，刻蚀至暴露所述背板以形成所述阴极电气连接通道及至少一个阳极电气连接通道。
上述，在完成S31之后，S32与S33择一执行。
需要说明的是，当用于制作微显示屏且在背板不设置相应阴极，则执行上述步骤S32。当用于制作分立器件时，背板设有阴极焊盘，则执行上述步骤S33，阴极电气连接通道延伸至背板，以便后续构造的阴极电气连接结构与阴极焊盘的连接。
S4、对阴极电气连接通道及至少一个阳极电气连接通道进行金属填充以形成阴极电气连接结构及至少一个阳极电气连接结构。
阴极电气连接结构与任一所述器件层的N型接触层分别电连接，任一阳极电气连接结构与相应器件层的P型接触层电连接。
具体的，步骤S4包括：
S41、对显示单元及背板的外表面、阴极电气连接通道及至少一个阳极电气连接通道的内壁进行钝化形成钝化层，并通过图形化刻蚀的方式开设至少一个通孔，至少一个通孔设于任一阳极电气连接结构与相应的P型接触层之间，以及，至少一个通孔设于阴极电气连接结构与相应的N型接触层之间。即，对应于上述步骤S33，当阴极电气连接通道延伸至背板时，在阴极电气连接通道对应的背板表面的钝化层开设有通孔。
S42、采用溅射、电镀、化镀或蒸镀对阴极电气连接通道及至少一个阳极电气连接通道进行金属填充以构造阴极电气连接结构及至少一个阳极电气连接结构。
综上，本实施例提供一种像素单元及其制作方法、微显示屏、分立器件，该像素单元包括背板、显示单元、阴极电气连接结构及至少一个阳极电气连接结构，显示单元设于背板上，阴极电气连接结构及至少一个阳极电气连接结构分别自远离背板的一侧表面向内嵌设于显示单元中；显示单元包括至少一个器件层，至少一个器件层依次垂直堆叠，任一器件层包括依次堆叠的P型接触层、像素层及N型接触层，P型接触层位于其所属器件层朝向背板的一侧；任一阳极电气连接结构与相应器件层的P型接触层电连接，阴极电气连接结构与任一器件层的N型接触层分别电连接；本实施例提供的像素单元通过在背板上依次垂直堆叠集成至少两层器件层的方式实现彩色化显示，相较于水平方向排布集成的像素结构，本实施例中像素单元在水平方向上所占的空间较小，实现超高密度的彩色化Micro-LED显示，从而实现同分辨率下更小的显示屏尺寸或者同屏幕尺寸下更高的分辨率；以及，本申请通过垂直方向上的多个器件层共用同一负极电气连接结构的方式实现发光区域面积占比的提高，减小了尺寸效应影响；
进一步，第一阳极电气连接结构包括依次连接的第一部分结构及第二部分结构，第一部分结构与第二部分结构的连接处，第二部分结构的端面积大于第一部分结构的端面积，以形成第一凸缘，像素单元还包括钝化层，部分钝化层贴设于显示单元及背板的外表面，部分钝化层贴设于至少一个阳极电气连接结构与显示单元之间，部分钝化层贴设于阴极电气连接结构与显示单元之间，本实施例中的阳极电气连接结构通过直径变化构造凸缘 结构，以实现阳极电气连接结构与P型接触层，或阴极电气连接结构与N型接触层之间的电气连接，从而简化结构，降低工艺难度；
以及，本实施例提供的像素单元的制作方法，其制作方法包括准备背板；在背板上依次垂直堆叠至少一个器件层以形成显示单元，任一器件层包括依次堆叠的P型接触层、像素层及N型接触层，P型接触层位于其所属器件层朝向背板的一侧；自显示单元远离背板的一侧表面向内刻蚀构造阴极电气连接通道及至少一个阳极电气连接通道；对阴极电气连接通道及至少一个阳极电气连接通道进行金属填充以形成阴极电气连接结构及至少一个阳极电气连接结构；阴极电气连接结构与任一器件层的N型接触层分别电连接，任一阳极电气连接结构与相应器件层的P型接触层电连接；本实施例中的像素制作方法采用先堆叠后图形化的方案，利用半导体工艺免去了对准键合的高昂成本，避免了对准精度偏差，在工艺上实现更小尺寸像素的堆叠，降低工艺难度，节省工艺成本；
需要说明的是，本实施例仅需实现上述至少一种技术效果即可。
实施例2
在实施例1基础上，本实施例进一步提供一种微显示屏200，如图2、6所示，该微显示屏200包括：
驱动背板210，其包括驱动电路及输入输出接口211。
显示区域220，其设于驱动背板210上，且显示区域包括至少两个如实施例1中所述的显示单元20，至少两个显示单元100呈阵列式排布。
外围共阴极230，外围共阴极230围设于显示区域220周向，且外围共阴极230与任一显示单元100的阴极电气连接结构分别连接。
绝缘层240，其设于显示区域220的表面。
透明导电层250，其设于绝缘层240外侧表面，且绝缘层240开设有至少一个镂空，阴极电气连接结构30通过绝缘层240的镂空与透明导电层250连接；以及，透明导电层250与外围共阴极230连接，以实现每一像素单元与阴极电极的连接。
本实施例提供的微显示屏200，在实施例1所提供的像素单元所具有的技术效果基础上，通过设置透明导电层的方式实现阴极电极的构造，简化了像素单元中的刻蚀步骤并同时避免了刻蚀过程中对器件层造成的影响， 有效提高像素单元及微显示屏的良率。
实施例3
如图3～5所示，在实施例1基础上，本实施例进一步提供一种分立器件300，该分立器件300包括：
分立器背板310；
器件主体320，器件主体320设于分立器背板310上，且器件主体320包括至少两个如实施例1中的显示单元20，至少两个显示单元20呈阵列式排布；
至少两个焊盘，包括一个阴极焊盘330及至少一个阳极焊盘，阴极焊盘330的至少部分、任一阳极焊盘的至少部分分别嵌设于分立器背板310中，任一阳极电气连接结构与相应的阳极焊盘连接，阴极电气连接结构30与相应的阴极焊盘330连接。
具体的，至少一个阳极焊盘包括：与第一器件层40连接的第一阳极焊盘340，与第二器件层50连接的第二阳极焊盘350，与第三器件层60连接的第三阳极焊盘360。
在一种优选的方案中，器件主体320与分立器件背板310分离设置，且至少两个焊盘与该分立器件背板310分离设置。作为优选，钝化层81包括固定部81没改固定部81，固定部81与分立器件背板310连接，用于将器件主体320与分立器背板310连接。具体的，该优选方式中，通过预先在分立器背板310和器件主体320、分立器背板310和至少一个焊盘之间预先设置牺牲层370，然后将该牺牲层370去除的方法实现。
对应于该分立器件，本实施例还提供一种分立器件的制作方法，该制作方法包括：
S10、准备分立器背板。具体包括：
S101、在预先准备的分立器背板上刻蚀形成至少四个空腔；
S102、在开设有至少四个空腔的分立器背板上镀牺牲层；牺牲层采用氮氧化硅膜，通过在分立器背板表面通过镀膜、热氧化、湿氧化等形成。
S103、在镀有牺牲层的分立器背板一侧构造至少四个焊盘，每一焊盘的部分嵌设于相应的空腔内，至少四个焊盘包括一个阴极焊盘及至少三个阳极焊盘。
本实施例中的焊盘采用金属焊盘，可以为金、钛、钨、铝、铂的一种或几种的合金或者叠层，制备的方式包括热蒸发、溅射、电镀或者化镀等，并且焊盘可以是实心的，也可以是空心的。
S20、在分立器背板上依次垂直堆叠至少一个器件层以形成显示单元并构造阴极电气连接结构及至少一个阳极电气连接结构。
该步骤S20包括：
S201、采用图形化干法刻蚀自显示单元远离分立器背板的一侧表面向内部逐层进行初步深刻蚀；
S202、采用图形化湿法刻蚀对完成初步深刻蚀的显示单元进行深刻蚀，刻蚀至暴露分立器背板以形成阴极电气连接通道及至少一个阳极电气连接通道。
S203、对器件主体及分立器件背板的外表面、阴极电气连接通道及至少一个阳极电气连接通道的内壁进行钝化形成钝化层，通过图形化刻蚀的方式开设至少一个通孔，至少一个通孔设于任一阳极电气连接结构与相应的P型接触层之间，以及，至少一个通孔设于阴极电气连接结构与分立器件背板之间。
需要说明的是，钝化层覆盖部分分立器背板，钝化层在器件主体与分立器背板的连接处形成固定部，该固定部实现器件主体与分立器背板之间的连接。
S30、去除牺牲层以获得分立器件。
具体的，在未镀设有钝化层的分立器背板的一侧表面对牺牲层进行刻蚀以使至少四个焊盘与分立器背板分离；牺牲层与分立器背板的刻蚀速率之比大于10:1，且牺牲层与钝化层的刻蚀速率之比大于10:1。且作为一种优选，刻蚀后分立器背板与器件主体之间的缝隙为100nm～1000nm，优选为300～500nm。
综上，在实施例1中像素单元所具有的技术效果基础上，本实施例中的分立器件是基于至少两个焊盘与外部电路连接的，在将该分立器件封装至目标背板进行电气连接时可规避共晶等金属焊接以避免对分立器件自身造成性能影响并简化工艺；以及，本实施例中器件主体与分立器背板分离设置，且至少四个焊盘与分立器背板分离设置；像素级分立器件还包括隔绝 支撑结构，隔绝支撑结构包覆器件主体及部分分立器背板，该像素分立器件通过设置隔绝支撑结构以实现器件主体与背板分离设置下的结构稳定性及后期使用时取用的便捷性，且该结构下分立器背板可循环使用，有效降低成本。
上述所有可选技术方案，可以采用任意结合形成本申请的可选实施例，即可将任意多个实施例进行组合，从而获得应对不同应用场景的需求，均在本申请的保护范围内，在此不再一一赘述。
需要说明的是，以上所述仅为本申请的较佳实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (27)

  1. 一种像素单元，其特征在于，所述像素单元包括背板、显示单元、阴极电气连接结构及至少一个阳极电气连接结构，所述显示单元设于所述背板上，所述阴极电气连接结构及所述至少一个阳极电气连接结构分别自远离所述背板的一侧表面向内嵌设于所述显示单元中；
    所述显示单元包括至少一个器件层，所述至少一个器件层依次垂直堆叠，任一所述器件层包括依次堆叠的P型接触层、像素层及N型接触层，所述P型接触层位于其所属器件层朝向所述背板的一侧；
    任一所述阳极电气连接结构与相应所述器件层的P型接触层电连接，所述阴极电气连接结构与任一所述器件层的N型接触层分别电连接。
  2. 如权利要求1所述的像素单元，其特征在于，任一所述阳极电气连接结构与所述背板连接；
    所述至少一个阳极电气连接结构包括第一阳极电气连接结构，所述第一阳极电气连接结构包括依次连接的第一部分结构及第二部分结构；
    所述至少一个器件层包括第一器件层，所述第一器件层包括依次堆叠的第一键合层、第一P型接触层、第一像素层及第一N型接触层，所述第一P型接触层位于所述第一器件层靠近所述背板的一侧；
    所述第一部分结构嵌设于所述第一键合层及所述第一P型接触层中，部分所述第二部分结构嵌设于所述第一像素层中，且所述第二部分结构与所述第一P型接触层电连接。
  3. 如权利要求2所述的像素单元，其特征在于，所述第二部分结构的端面积大于所述第一部分结构的端面积，以在两者的连接处形成第一凸缘；
    所述第一凸缘与所述第一P型接触层连接。
  4. 如权利要求2所述的像素单元，其特征在于，所述至少一个阳极电气连接结构还包括第二阳极电气连接结构；
    所述显示单元还包括第二器件层，所述第二器件层叠设于所述第一器件层远离所述背板的一侧表面，所述第二器件层包括依次堆叠的第二键合层、第二P型接触层、第二像素层及第二N型接触层，所述第二键合层与所述第一像素层连接；
    所述第二阳极电气连接结构包括第二凸缘，所述第二凸缘与所述第二P 型接触层连接。
  5. 如权利要求4所述的像素单元，其特征在于，所述第二N型接触层设于所述第一N型接触层的正上方。
  6. 如权利要求4所述的像素单元，其特征在于，所述第一N型接触层为凸起结构，所述第一N型接触层嵌设于所述第二键合层中。
  7. 如权利要求6所述的像素单元，其特征在于，所述阴极电气连接结构包括第三部分结构，所述第三部分结构嵌设于所述第二器件层中，且所述第三部分结构一端与所述第一N型接触层连接。
  8. 如权利要求7所述的像素单元，其特征在于，所述阴极电气连接结构还包括第四部分结构，所述第四部分结构一端与所述背板连接，另一端穿过所述第一器件层与所述第三部分结构连接。
  9. 如权利要求4所述的像素单元，其特征在于，所述第二键合层包括第二键合层本体及功能层，所述功能层设于所述第二键合层本体及所述第一像素层之间。
  10. 如权利要求7所述的像素单元，其特征在于，所述至少一个阳极电气连接结构还包括第三阳极电气连接结构；
    所述显示单元还包括第三器件层，所述第三器件层叠设于所述第二器件层远离所述第一器件层的一侧表面，所述第三器件层包括依次堆叠的第三键合层、第三P型接触层、第三像素层及第三N型接触层，所述第三键合层与所述第二像素层连接；
    所述第三阳极电气连接结构包括第三凸缘，所述第三凸缘与所述第三P型接触层连接。
  11. 如权利要求10所述的像素单元，其特征在于，所述阴极电气连接结构还包括与所述第三部分结构连接的第五部分结构，所述第五部分结构嵌设于所述第三器件层中；
    所述第五部分结构的端面积大于所述第三部分结构的端面积，以在两者的连接处形成第四凸缘；
    所述第四凸缘与所述第二N型接触层连接。
  12. 如权利要求11所述的像素单元，其特征在于，所述第二N型接触层为凸起结构，所述第二N型接触层嵌设于所述第三键合层中。
  13. 如权利要求12所述的像素单元，其特征在于，所述第二键合层及所述第三键合层均采用透明材质。
  14. 如权利要求1～13任意一项所述的像素单元，其特征在于，所述像素单元还包括钝化层，部分所述钝化层贴设于所述显示单元及所述背板的外表面，部分所述钝化层贴设于所述至少一个阳极电气连接结构与所述显示单元之间，部分所述钝化层贴设于所述阴极电气连接结构与所述显示单元之间。
  15. 如权利要求14所述的像素单元，其特征在于，所述钝化层开设有至少一个通孔，所述至少一个通孔设于任一阳极电气连接结构与相应的P型接触层之间，以及，所述阴极电气连接结构与相应的N型接触层之间。
  16. 如权利要求14所述的像素单元，其特征在于，所述钝化层采用透明绝缘材料。
  17. 如权利要求10～13、15、16任意一项所述的像素单元，其特征在于，所述第一像素层为AlGaInP或InGaN红光化合物外延，所述第二像素层为InGaN绿光化合物外延，所述第三像素层为InGaN蓝光化合物外延。
  18. 一种像素单元的制作方法，其特征在于，所述制作方法包括：
    准备背板；
    在所述背板上依次垂直堆叠至少一个器件层以形成显示单元，任一所述器件层包括依次堆叠的P型接触层、像素层及N型接触层，所述P型接触层位于其所属器件层朝向所述背板的一侧；
    自所述显示单元远离所述背板的一侧表面向内刻蚀构造阴极电气连接通道及至少一个阳极电气连接通道；
    对所述阴极电气连接通道及所述至少一个阳极电气连接通道进行金属填充以形成阴极电气连接结构及至少一个阳极电气连接结构；所述阴极电气连接结构与任一所述器件层的N型接触层分别电连接，任一所述阳极电气连接结构与相应所述器件层的P型接触层电连接。
  19. 如权利要求18所述的制作方法，其特征在于，所述至少一个器件层包括第一器件层，所述在所述背板上依次垂直堆叠至少一个器件层以形成显示单元，包括：
    在所述背板表面、预先准备的第一化合物半导体晶圆的P型接触层表面 分别镀键合材料并键合形成第一键合层；
    去除所述第一化合物半导体晶圆的衬底并进行化合物半导体减薄露出第一N型接触层，所述第一N型接触层为凸起结构。
  20. 如权利要求19所述的制作方法，其特征在于，所述至少一个器件层还包括第二器件层及第三器件层；在完成第一器件层后，所述在所述背板上依次垂直堆叠至少一个器件层以形成显示单元，还包括：
    在所述第一器件层远离所述背板的一侧表面依次垂直堆叠第二器件层及第三器件层，以形成所述显示单元。
  21. 如权利要求18所述的制作方法，其特征在于，所述自所述显示单元远离所述背板的一侧表面向内刻蚀构造阴极电气连接通道及至少一个阳极电气连接通道，包括：
    采用图形化干法刻蚀自所述显示单元远离所述背板的一侧表面向内部逐层进行初步深刻蚀；
    采用图形化湿法刻蚀对完成初步深刻蚀的所述显示单元进行深刻蚀，刻蚀至暴露背板以形成至少一个阳极电气连接通道，刻蚀至暴露相应的N型接触层以形成所述阴极电气连接通道。
  22. 如权利要求18所述的制作方法，其特征在于，所述自所述显示单元远离所述背板的一侧表面向内刻蚀构造阴极电气连接通道及至少一个阳极电气连接通道，包括：
    采用图形化干法刻蚀自所述显示单元远离所述背板的一侧表面向内部逐层进行初步深刻蚀；
    采用图形化湿法刻蚀对完成初步深刻蚀的所述显示单元进行深刻蚀，刻蚀至暴露所述背板以形成所述阴极电气连接通道及至少一个阳极电气连接通道。
  23. 如权利要求21或22所述的制作方法，其特征在于，所述对所述阴极电气连接通道及所述至少一个阳极电气连接通道进行金属填充以形成阴极电气连接结构及至少一个阳极电气连接结构，包括：
    对所述显示单元及所述背板的外表面、所述阴极电气连接通道及所述至少一个阳极电气连接通道的内壁进行钝化形成钝化层，并通过图形化刻蚀的方式开设至少一个通孔，所述至少一个通孔设于任一阳极电气连接结 构与相应的P型接触层之间，以及，所述至少一个通孔设于所述阴极电气连接结构与相应的N型接触层之间；
    采用溅射、电镀、化镀或蒸镀对所述阴极电气连接通道及所述至少一个阳极电气连接通道进行金属填充以构造所述阴极电气连接结构及至少一个阳极电气连接结构。
  24. 微显示屏，其特征在于，所述微显示屏包括：
    驱动背板，所述驱动背板包括驱动电路及输入输出接口；
    显示区域，所述显示区域设于所述驱动背板上，且所述显示区域包括至少两个如权利要求1～7、9～17任意一项所述的显示单元，至少两个所述显示单元呈阵列式排布；
    外围共阴极，所述外围共阴极围设于所述显示区域周向，且所述外围共阴极与任一所述显示单元的阴极电气连接结构分别连接。
  25. 如权利要求24所述的微显示屏，其特征在于，所述背板集成有驱动电路；
    对应于任一所述像素单元，所述驱动电路包括至少一个阳极，任一所述阳极电气连接结构与相应的阳极连接。
  26. 如权利要求25所述的微显示屏，其特征在于，所述微显示屏还包括从内至外依次贴设在所述显示区域表面的绝缘层及透明导电层，所述透明导电层与所述外围共阴极连接；
    所述绝缘层开设有至少一个镂空，所述阴极电气连接结构通过所述绝缘层的镂空与所述透明导电层连接。
  27. 分立器件，其特征在于，所述分立器件包括：
    分立器背板；
    器件主体，所述器件主体设于所述分立器背板上，且所述器件主体包括至少两个如权利要求1～17任意一项所述的显示单元，至少两个所述显示单元呈阵列式排布；
    至少两个焊盘，包括一个阴极焊盘及至少一个阳极焊盘，任一所述阳极焊盘的至少部分及所述阴极焊盘的至少部分分别嵌设于所述分立器背板中，任一所述阳极电气连接结构与相应的阳极焊盘连接，所述阴极电气连接结构与相应的阴极焊盘连接。
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