WO2024012233A1 - 半导体基板及其驱动方法、半导体显示装置 - Google Patents

半导体基板及其驱动方法、半导体显示装置 Download PDF

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Publication number
WO2024012233A1
WO2024012233A1 PCT/CN2023/104321 CN2023104321W WO2024012233A1 WO 2024012233 A1 WO2024012233 A1 WO 2024012233A1 CN 2023104321 W CN2023104321 W CN 2023104321W WO 2024012233 A1 WO2024012233 A1 WO 2024012233A1
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Prior art keywords
transistor
circuit
semiconductor substrate
layer
electrode
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PCT/CN2023/104321
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English (en)
French (fr)
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WO2024012233A9 (zh
Inventor
龙春平
许静波
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BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
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Application filed by BOE Technology Group Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US18/833,005 priority Critical patent/US12562117B2/en
Priority to EP23838725.2A priority patent/EP4510119A4/en
Publication of WO2024012233A1 publication Critical patent/WO2024012233A1/zh
Publication of WO2024012233A9 publication Critical patent/WO2024012233A9/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • Embodiments of the present disclosure relate to a semiconductor substrate, a driving method thereof, and a semiconductor display device.
  • semiconductor materials are often fabricated on a substrate to form a semiconductor substrate.
  • the semiconductor substrate can be a display panel or a light-emitting panel, etc.
  • a semiconductor transistor is provided on the semiconductor substrate.
  • the semiconductor transistor is made of semiconductor materials and can have two states: on and off. In addition, it can also have different on degrees in the on state.
  • Semiconductor substrates are often used in display devices as display panels.
  • OLED display devices are gradually gaining popularity due to their advantages such as wide viewing angle, high contrast, fast response speed, higher luminance and lower driving voltage than inorganic light-emitting display devices. widespread attention. Due to the above characteristics, organic light-emitting diodes (OLEDs) can be applied to devices with display functions such as mobile phones, monitors, laptops, digital cameras, instruments and meters.
  • Pixel circuits in OLED display devices generally adopt matrix driving methods, and are divided into active matrix (AM) driving and passive matrix (PM) driving according to whether switching components are introduced in each pixel unit.
  • the switching element may be a semiconductor transistor (such as a thin film transistor, etc.).
  • AMOLED integrates a set of thin film transistors and storage capacitors into the pixel circuit of each pixel. By driving and controlling the thin film transistors and storage capacitors, the current flowing through the OLED is controlled, so that the OLED can be controlled as needed. glow.
  • AMOLED requires small driving current, low power consumption, and longer life, and can meet the needs of large-size display with high resolution and multiple grayscales.
  • AMOLED is in visual It has obvious advantages in angle, color restoration, power consumption and response time, and is suitable for display devices with high information content and high resolution.
  • At least one embodiment of the present disclosure provides a semiconductor substrate, including an array substrate, wherein the array substrate includes a plurality of pixel units arranged in an array, each pixel unit including a pixel circuit and a light-emitting element; the pixel circuit includes a driving circuit , data writing circuit, storage circuit, sensing circuit and protection circuit; the driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control the driving current that drives the light-emitting element to emit light, the driving circuit The first terminal receives the first voltage of the first voltage terminal; the data writing circuit is connected to the control terminal of the driving circuit and is configured to write a data signal to the control terminal of the driving circuit in response to the first scan signal.
  • the first end of the storage circuit is connected to the control end of the drive circuit, the second end of the storage circuit is connected to the second end of the drive circuit, and the storage circuit is configured to store the data written the data signal written by the circuit;
  • the sensing circuit is connected to the second end of the driving circuit, and is configured to connect the second end of the driving circuit to the sensing signal line in response to the second scan signal;
  • the protection circuit includes a control end, a first end and a second end, the first end of the protection circuit is connected to the first end of the drive circuit, the control end of the protection circuit and the second end of the protection circuit terminals are connected to the second terminal of the driving circuit, the protection circuit is configured to prevent the static electricity generated by the sensing circuit from flowing to the light-emitting element, and jointly provide the driving current with the driving circuit;
  • the A first end of the light-emitting element is connected to a second end of the driving circuit, a second end of the light-emitting element receives a second voltage from a second voltage terminal,
  • the driving circuit includes a first transistor; the gate of the first transistor serves as the control terminal of the driving circuit, and the first electrode of the first transistor serves as The first terminal of the driving circuit and the second pole of the first transistor serve as the second terminal of the driving circuit.
  • the protection circuit includes a second transistor; the gate of the second transistor serves as the control terminal of the protection circuit, and the first electrode of the second transistor serves as The first terminal of the protection circuit and the second terminal of the second transistor serve as the second terminal of the protection circuit; the first terminal of the second transistor is connected to the first terminal of the first transistor; The gate of the second transistor is connected to the second electrode of the second transistor and connected to the second electrode of the first transistor.
  • the second transistor forms a diode connection.
  • the first transistor and the second transistor are both N-type thin film transistors or both are P-type thin film transistors.
  • the data writing circuit includes a third transistor; the gate of the third transistor is connected to the first scan line to receive the first scan signal, and the The first electrode of the third transistor is connected to the data line to receive the data signal, and the second electrode of the third transistor is connected to the control end of the driving circuit.
  • the sensing circuit includes a fourth transistor; the gate of the fourth transistor is connected to the second scan line to receive the second scan signal, and the gate of the fourth transistor is connected to the second scan line to receive the second scan signal.
  • the first pole of the four transistors is connected to the second end of the driving circuit, and the second pole of the fourth transistor is connected to the sensing signal line.
  • the storage circuit includes a storage capacitor; the first pole of the storage capacitor serves as the first end of the storage circuit, and the second pole of the storage capacitor serves as the The second terminal of the storage circuit.
  • the light-emitting element includes an organic light-emitting diode, the anode of the organic light-emitting diode serves as the first end of the light-emitting element, and the cathode of the organic light-emitting diode serves as the the second end of the light-emitting element.
  • a semiconductor substrate provided by an embodiment of the present disclosure further includes a reset circuit, wherein the reset circuit is connected to a control terminal of the drive circuit and is configured to apply a reset voltage to the control end of the drive circuit in response to a reset signal. end.
  • the reset circuit includes a fifth transistor; the gate of the fifth transistor is connected to the reset signal line to receive the reset signal, and the gate of the fifth transistor is connected to the reset signal line.
  • One pole is connected to the control terminal of the driving circuit, and the second pole of the fifth transistor is connected to the reset voltage terminal to receive the reset voltage.
  • the reset voltage terminal and the second voltage terminal are the same voltage terminal, and the reset voltage and the second voltage are the same voltage signal.
  • the channel width to length ratio of the first transistor ranges from 12.6:6 to 16.2:6.
  • the array substrate includes a substrate A substrate, a buffer layer, and a gate insulating layer; the first transistor includes an active layer; the buffer layer is provided on the base substrate, the active layer is provided on the buffer layer, and the gate insulating layer Disposed on the buffer layer and covering the active layer, the gate electrode of the first transistor is disposed on the gate insulating layer.
  • the array substrate further includes an interlayer insulating layer; the interlayer insulating layer is provided on the gate insulating layer and covers the gate of the first transistor, The first electrode of the first transistor and the second electrode of the first transistor are provided on the interlayer insulating layer.
  • the first electrode of the first transistor and the second electrode of the first transistor are disposed on the gate insulating layer, and the first electrode of the first transistor is The first electrode, the second electrode of the first transistor, and the gate electrode of the first transistor are located on the same layer.
  • the first electrode of the first transistor is connected to the active layer through at least a first via hole penetrating the gate insulating layer, and the first electrode of the first transistor is The second electrode is connected to the active layer through at least a second via hole penetrating the gate insulating layer.
  • the active layer includes at least one grooved area, and the grooved area penetrates the active layer in a direction perpendicular to the base substrate. hole.
  • the at least one grooved area includes a first grooved area and a second grooved area, and the first grooved area is adjacent to the first via hole, so The second grooved area is adjacent to the second via hole.
  • the first via hole exposes a part of the active layer, and a part of the buffer layer is exposed through the first grooved region; and/or the The second via hole exposes a portion of the active layer, and a portion of the buffer layer is exposed through the second grooved region.
  • the shapes of the first grooved area and the second grooved area are both rectangular.
  • the size of the first grooved area is the same as the size of the second grooved area.
  • the at least one grooved area is one grooved area
  • one of the first electrode of the first transistor and the second electrode of the first transistor is The source electrode of the first transistor, the first via hole and the second via hole are connected to the first crystal
  • the via hole adjacent to the source of the tube is the target via hole
  • the grooved area is adjacent to the target via hole.
  • the target via hole exposes a portion of the active layer, and a portion of the buffer layer is exposed through the grooved region.
  • the shape of the grooved area is rectangular.
  • the reference width of the active layer is Wd
  • the width of the grooved area is Wvia
  • the active layer is at the position of the grooved area.
  • the effective width is W1
  • the reference length of the active layer is Ld
  • the length of the grooved area is L1
  • the preset channel current of the first transistor is expressed as I1
  • the trench channel current of the first transistor is expressed as I2.
  • the value range of I2/I1 is 1 ⁇ 1.5.
  • the array substrate further includes a light-shielding layer disposed on the base substrate, and the buffer layer is disposed on the base substrate and covers
  • the light-shielding layer is made of metal, and at least part of the light-shielding layer is reused as the gate of the second transistor.
  • the first electrode of the first transistor is multiplexed as the first electrode of the second transistor, and the second electrode of the first transistor is multiplexed as the first electrode of the second transistor.
  • the second pole of the second transistor; the second pole of the second transistor is connected to the light-shielding layer through at least a third via hole that penetrates the buffer layer and the gate insulation layer.
  • the channel width of the second transistor is W3, the channel length of the second transistor is L3, the thickness of the buffer layer is dbuf, and the gate
  • the thickness of the insulating layer is dgi;
  • the channel current of the second transistor is Ie, the initial channel current of the first transistor is Id, and the initial channel current Id of the first transistor is equal to the first transistor.
  • the value range of Id/Ie is 0.5-1.
  • the third via hole has first and second sidewalls opposite to each other, the first sidewall is close to the active layer, and the third via hole has a first sidewall and a second sidewall that are opposite to each other.
  • the two side walls are away from the active layer, and the slope of the first side wall is different from the slope of the second side wall.
  • the slope of the first side wall is greater than the slope of the second side wall.
  • the array substrate further includes a gate metal layer and a passivation layer; the gate metal layer is provided on the gate insulating layer, and the gate electrode of the first transistor , the first electrode of the first transistor and the second electrode of the first transistor are both located on the gate metal layer, and the passivation layer is provided on the gate metal layer; the first terminal of the light-emitting element is an anode, and the anode is connected to a transfer portion located on the gate metal layer through a fourth via hole penetrating the passivation layer, and the transfer portion is connected to the light shielding layer and the light shielding layer through the third via hole.
  • the second terminal of the first transistor is connected.
  • the distance between the edges of the fourth via hole and the third via hole that are close to each other is das, and the third via hole is in the gate metal layer.
  • the aperture of the plane is ds,
  • das ds.
  • the distance between the edges of the holes is dgs
  • the aperture of the third via hole in the plane where the gate metal layer is located is ds
  • dgs ds.
  • the array substrate further includes a data line, the data line is used to transmit the data signal, and the data line is provided on the interlayer insulating layer, so The data line is located on the same layer as the first electrode of the first transistor and the second electrode of the first transistor.
  • the array substrate further includes a data line, the data line is used to transmit the data signal, the data line is provided on the gate insulating layer, and the The data line is located on the same layer as the gate electrode of the first transistor, the first electrode of the first transistor, and the second electrode of the first transistor.
  • the third transistor, the fourth transistor, the first scan line, and the second scan line are located on the same side of the first transistor.
  • the active layer is covered by the third
  • the exposed portion of one via hole and/or the second via hole is a conductive area formed by plasma doping.
  • one of the first electrode of the first transistor and the second electrode of the first transistor is the drain electrode of the first transistor
  • the first Among the via hole and the second via hole, the via hole adjacent to the drain electrode of the first transistor and the third via hole are the same via hole, and the drain electrode of the first transistor passes through the third via hole.
  • the via hole is connected to both the exposed portion of the active layer and the exposed portion of the light shielding layer.
  • the array substrate further includes a passivation layer and a planarization layer; one of the first electrode of the first transistor and the second electrode of the first transistor. is the drain electrode of the first transistor; the passivation layer and the planarization layer are stacked in sequence and are located on the drain electrode of the first transistor; the passivation layer and the planarization layer There is a fifth via hole in the transistor, and the fifth via hole exposes the drain electrode of the first transistor.
  • the fifth via hole includes a step located at an interface between the passivation layer and the planarization layer, and the width of the step is less than or equal to 1 ⁇ m.
  • the array substrate further includes a light-shielding layer disposed on the base substrate, and the buffer layer is disposed on the base substrate and covers The light-shielding layer, the material of the light-shielding layer is metal, the light-shielding layer is multiplexed as the gate of the second transistor; the orthographic projection of the fifth via hole in a direction perpendicular to the base substrate At least partially overlaps with the orthographic projection of the portion of the light shielding layer that is multiplexed as the gate of the second transistor in a direction perpendicular to the base substrate.
  • the sensing circuit includes a fourth transistor, the gate of the fourth transistor is connected to the second scan line to receive the second scan signal, and the gate of the fourth transistor is connected to the second scan line to receive the second scan signal.
  • the first pole of the four transistors is connected to the second end of the driving circuit, and the second pole of the fourth transistor is connected to the sensing signal line;
  • the light shielding layer is also multiplexed as the gate of the fourth transistor. pole, and multiplexed as the first voltage terminal;
  • the light-shielding layer is a double-layer metal structure.
  • At least one embodiment of the present disclosure further provides a semiconductor display device, including the semiconductor substrate described in any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure also provides a driving method for the semiconductor substrate according to any embodiment of the present disclosure, including: during the display stage, the driving circuit and the protection circuit jointly provide the driving current, to drive the light-emitting element to emit light; in the sensing stage, the sensing circuit A path is opened to connect the second end of the driving circuit to the sensing signal line, and the protection circuit is used to prevent static electricity generated by the sensing circuit from flowing to the light-emitting element.
  • Figure 1 is a schematic diagram of a display panel provided by some embodiments of the present disclosure.
  • Figure 2 is a schematic block diagram of a pixel circuit in a display panel provided by some embodiments of the present disclosure
  • Figure 3 is a circuit diagram of a specific implementation example of the pixel circuit shown in Figure 2;
  • Figure 4 is a timing diagram of the circuit structure shown in Figure 3;
  • Figure 5A is a schematic block diagram of another pixel circuit in a display panel provided by some embodiments of the present disclosure.
  • Figure 5B is a circuit diagram of a specific implementation example of the pixel circuit shown in Figure 5A;
  • Figure 6A is a schematic cross-sectional view of an array substrate in a display panel provided by some embodiments of the present disclosure
  • Figure 6B is a schematic cross-sectional view of another array substrate in a display panel provided by some embodiments of the present disclosure.
  • Figure 7 is a schematic cross-sectional view of an array substrate in another display panel provided by some embodiments of the present disclosure.
  • Figure 8 is a schematic plan view of an active layer in a display panel according to some embodiments of the present disclosure.
  • Figure 9A is a schematic cross-sectional view of line A-A’ in Figure 8.
  • Figure 9B is a schematic cross-sectional view of line B-B’ in Figure 8.
  • Figure 10 is a schematic diagram showing the dimensions of the active layer shown in Figure 8.
  • Figure 11 is a schematic plan view of an active layer in another display panel provided by some embodiments of the present disclosure.
  • Figure 12A is a schematic cross-sectional view of line C-C’ in Figure 11;
  • Figure 12B is a schematic cross-sectional view of line D-D’ in Figure 11;
  • FIGS. 13A to 13C are schematic diagrams of the etching process of an array substrate in a display panel according to some embodiments of the present disclosure
  • Figure 14 is a cross-sectional view of an array substrate in a display panel according to some embodiments of the present disclosure. picture;
  • Figure 15 is a schematic cross-sectional view of an array substrate in another display panel provided by some embodiments of the present disclosure.
  • Figure 16 is a schematic cross-sectional view of an array substrate in another display panel provided by some embodiments of the present disclosure.
  • 17A to 17F are plan layout views of various layer structures of an array substrate in a display panel according to some embodiments of the present disclosure.
  • Figure 18 is a schematic cross-sectional view of an array substrate in a display panel provided by some embodiments of the present disclosure.
  • Figure 19 is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • Figure 20 is a schematic block diagram of another display device provided by some embodiments of the present disclosure.
  • FIG. 21 is a schematic flowchart of a driving method for a display panel provided by some embodiments of the present disclosure.
  • the transistors in the pixel circuit are semiconductor transistors, using semiconductor materials (such as doped polycrystalline silicon, etc.).
  • semiconductor materials such as doped polycrystalline silicon, etc.
  • the process stability of the transistors in the pixel circuit becomes the main factor affecting the display screen.
  • the threshold voltage and mobility of the driving transistors between multiple pixels exist. The differences lead to different currents supplied to each pixel, causing the actual brightness of each pixel to deviate from the expected ideal brightness.
  • the brightness uniformity of the display screen will decrease, and even regional spots or patterns will occur.
  • factors such as the voltage drop (IR Drop) of the voltage source and OLED aging will also affect the brightness uniformity of the display. Therefore, compensation technology is needed to achieve the ideal brightness of the pixels.
  • external compensation can be used, that is, the current of the driving transistor is drawn out, and a circuit external to the pixel circuit is used to detect the current, thereby calculating the deviation and the value that needs to be compensated, thereby realizing compensation for the driving transistor.
  • a sensing transistor can be used to draw the current from the driving transistor. However, when the sensing transistor is turned on, static electricity is easily generated, which may damage the OLED device and affect the service life of the OLED device.
  • At least one embodiment of the present disclosure provides a semiconductor substrate, a driving method thereof, and a semiconductor display device.
  • the semiconductor substrate can reduce the probability of damage to organic light-emitting diode (OLED) devices, protect the OLED devices, and extend the service life of the OLED devices.
  • OLED organic light-emitting diode
  • the display panel is a specific example of a semiconductor substrate
  • the display panel is essentially a semiconductor substrate
  • the display panel described herein may refer to the semiconductor substrate. Therefore, although display panels and related features are described herein, they should be considered a description of semiconductor substrates and related features.
  • the display device including the display panel is also a semiconductor display device.
  • the display device described herein may refer to a semiconductor display device. Therefore, although the display device and its related features are described herein, it should be regarded as a reference to the semiconductor display device. Description of the device and its associated features.
  • At least one embodiment of the present disclosure provides a semiconductor substrate including an array substrate.
  • the array substrate includes a plurality of pixel units arranged in an array, and each pixel unit includes a pixel circuit and a light-emitting element.
  • Pixel circuits include drive circuits, data writing circuits, storage circuits, sensing circuits and protection circuits.
  • the driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control a driving current for driving the light-emitting element to emit light.
  • the first terminal of the driving circuit receives the first voltage of the first voltage terminal.
  • the data writing circuit is connected to the control terminal of the driving circuit and is configured to write the data signal to the control terminal of the driving circuit in response to the first scanning signal.
  • the first end of the storage circuit is connected to the control end of the drive circuit, and the storage circuit
  • the second end of the storage circuit is connected to the second end of the driving circuit, and the storage circuit is configured to store the data signal written by the data writing circuit.
  • the sensing circuit is connected to the second end of the driving circuit, and is configured to connect the second end of the driving circuit to the sensing signal line in response to the second scan signal.
  • the protection circuit includes a control end, a first end and a second end. The first end of the protection circuit is connected to the first end of the drive circuit. The control end of the protection circuit and the second end of the protection circuit are both connected to the second end of the drive circuit.
  • the protection circuit is configured to prevent static electricity generated by the sensing circuit from flowing to the light-emitting element, and jointly provide the driving current with the driving circuit.
  • the first end of the light-emitting element is connected to the second end of the driving circuit, the second end of the light-emitting element receives the second voltage from the second voltage terminal, and the light-emitting element is configured to emit light according to the driving current.
  • FIG. 1 is a schematic diagram of a display panel provided by some embodiments of the present disclosure.
  • the display panel 100 includes an array substrate 101 , and the array substrate 101 includes a plurality of pixel units P arranged in an array.
  • the display panel 100 may be an OLED display panel, a Quantum Dot Light-Emitting Diode (QLED) display panel, or other suitable display panels.
  • Each pixel unit includes a pixel circuit 20 and a light-emitting element L (not shown in FIG. 1 ).
  • Each pixel unit is connected to the corresponding first scanning line S1, second scanning line S2, data line Vdata, and sensing signal line Sen. .
  • FIG. 2 is a schematic block diagram of a pixel circuit in a display panel provided by some embodiments of the present disclosure.
  • each pixel unit includes a pixel circuit 20 and a light emitting element L.
  • the pixel circuit 20 includes a driving circuit 21, a data writing circuit 22, a storage circuit 23, a sensing circuit 24 and a protection circuit 25.
  • the driving circuit 21 includes a first terminal 211, a second terminal 212, and a control terminal 213, and is configured to control a driving current that drives the light-emitting element L to emit light.
  • the first terminal 211 of the driving circuit 21 receives the first voltage of the first voltage terminal VDD.
  • the control terminal 213 of the driving circuit 21 is connected to the first node N1, the first terminal 211 of the driving circuit 21 is connected to the first voltage terminal VDD (for example, high level) to receive the first voltage, and the second terminal 212 of the driving circuit 21 Connected to the second node N2.
  • the driving circuit 21 can provide a driving current to the light-emitting element L to drive the light-emitting element L to emit light, so that the light-emitting element L can emit light according to the required "grayscale".
  • the light-emitting element L can be an OLED, and its two ends are configured to be connected to the second node N2 and the second voltage terminal VSS (eg, ground) respectively.
  • VSS voltage terminal
  • the data writing circuit 22 is connected to the control terminal 213 (first node N1 ) of the driving circuit 21 and is configured to write a data signal to the control terminal 213 of the driving circuit 21 in response to the first scanning signal.
  • the data writing circuit 22 is connected to the data line Vdata, the first node N1 and the first scan line S1 respectively.
  • the first scan signal from the first scan line S1 is applied to the data writing circuit 22 to control whether the data writing circuit 22 is turned on.
  • the data writing circuit 22 can be turned on in response to the first scan signal, so that the data signal provided by the data line Vdata can be written into the control terminal 213 (first node N1) of the driving circuit 21, and then The data signal can be stored in the storage circuit 23, and the stored data signal will be used to generate a driving current for driving the light-emitting element L to emit light.
  • the first terminal 231 of the storage circuit 23 is connected to the control terminal 213 (first node N1) of the driving circuit 21, and the second terminal 232 of the storage circuit 23 is connected to the second terminal 212 (second node N2) of the driving circuit 21.
  • the storage circuit 23 is configured to store the data signal written by the data writing circuit 22 .
  • the storage circuit 23 can store the data signal and allow the stored data signal to control the driving circuit 21 .
  • the sensing circuit 24 is connected to the second end 212 (second node N2) of the driving circuit 21, and is configured to connect the second end 212 of the driving circuit 21 to the sensing signal line Sen in response to the second scanning signal.
  • the sensing circuit 24 is connected to the second node N2, the second scanning line S2, and the sensing signal line Sen respectively.
  • the second scan signal from the second scan line S2 is applied to the sensing circuit 24 to control whether the sensing circuit 24 is turned on.
  • the sensing signal line Sen may provide a second voltage (eg, a ground voltage) and may be switched to a floating state.
  • the sensing signal line Sen when writing detection data, the sensing signal line Sen provides a second voltage to ensure that the detection data is written correctly. Then the sensing signal line Sen is switched to a floating state, and the second end 212 of the driving circuit 21 is electrically connected to the sensing signal line Sen, so that the current flowing through the driving circuit 21 can be detected.
  • the current can be converted into a voltage signal through a separately configured detection circuit (for example, an operational amplifier, an analog-to-digital converter, etc.), and then converted into a digital signal and the resulting signal can be stored, and the signal can be further processed
  • the compensation data is obtained through algorithm processing, and then during the normal light-emitting phase of the pixel circuit, the compensation data obtained through algorithm processing is superimposed on the input display data to obtain compensated display data.
  • the compensated display data can be written into the circuit through data 22 is written to control the driving circuit 21, so that differences in display brightness uniformity caused by differences in threshold voltage and mobility of the transistors in the driving circuit 21 can be compensated.
  • the first terminal L01 of the light-emitting element L is connected to the second terminal 212 (second node N2) of the driving circuit 21 to receive the driving current, and the second terminal L02 of the light-emitting element L receives the second voltage of the second voltage terminal VSS,
  • the light-emitting element L is configured to emit light according to the drive current.
  • the protection circuit 25 includes a first terminal 251, a second terminal 252, and a control terminal 253.
  • the first terminal 251 is connected to the first terminal 211 of the driving circuit 21 .
  • the control terminal 253 of the protection circuit 25 and the second terminal 252 of the protection circuit 25 are both connected to the second terminal 212 (second node N2 ) of the driving circuit 21 .
  • the protection circuit 25 is configured to prevent static electricity generated by the sensing circuit 24 from flowing to the light emitting element L, and together with the driving circuit 21 provides a driving current.
  • the protection circuit 25 can be provided to play a protective role and prevent the static electricity generated by the sensing circuit 24 from flowing to The light-emitting element L is prevented from being damaged by the static electricity, thereby reducing the probability of damage to the light-emitting element L.
  • the protection circuit 25 has a positive feedback effect and can provide a driving current together with the driving circuit 21 .
  • FIG. 3 is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 2 .
  • the pixel circuit 20 includes first to fourth transistors T1 , T2 , T3 , and T4 and a storage capacitor C1 .
  • the pixel circuit 20 is connected to the light-emitting element L.
  • the first transistor T1 is used as a driving transistor, and the other transistors are used as switching transistors.
  • the light-emitting element L can be various types of OLEDs, such as top-emitting, bottom-emitting, double-sided emitting, etc., and can emit red light, green light, blue light, or white light, etc.
  • the embodiments of the present disclosure are not limited to this.
  • the driving circuit 21 may be implemented as a first transistor T1.
  • the gate electrode of the first transistor T1 serves as the control terminal 213 of the driving circuit 21 and is connected to the first node N1.
  • the first electrode of the first transistor T1 serves as the first terminal 211 of the driving circuit 21 and is connected to the first voltage terminal VDD.
  • the first transistor T1 The second pole of T1 serves as the second terminal 212 of the driving circuit 21 and is connected to the second node N2.
  • the driving circuit 21 may also be a circuit composed of other components.
  • the driving circuit 21 may have two groups of driving transistors.
  • the two groups of driving transistors may be configured according to specific requirements. Switch the situation.
  • the protection circuit 25 may be implemented as a second transistor T2.
  • the gate electrode of the second transistor T2 serves as the control terminal 253 of the protection circuit 25
  • the first electrode of the second transistor T2 serves as the first terminal 251 of the protection circuit 25
  • the second electrode of the second transistor T2 serves as the second terminal of the protection circuit 25 252.
  • the first electrode of the second transistor T2 is connected to the first electrode of the first transistor T1; the gate electrode of the second transistor T2 is connected to the second electrode of the second transistor T2, and is connected to the second electrode of the first transistor T1.
  • the second transistor T2 forms a diode connection, and the second transistor T2 is connected in parallel to the first transistor T1, which can effectively prevent the static electricity generated by the sensing circuit 24 from flowing to the light-emitting element L, and prevent the static electricity from damaging the light-emitting element L. , plays a protective role in the light-emitting element L, thereby reducing the probability of damage to the light-emitting element L and extending its service life.
  • both the first transistor T1 and the second transistor T2 are N-type thin The film transistor, or the first transistor T1 and the second transistor T2 are both P-type thin film transistors, that is, they can be the same type of transistors.
  • the data writing circuit 22 may be implemented as a third transistor T3.
  • the gate electrode of the third transistor T3 is connected to the first scan line S1 to receive the first scan signal, and the first electrode of the third transistor T3 is connected to the data line Vdata to receive the data signal.
  • the second electrode of the third transistor T3 is connected to the control terminal 213 (first node N1) of the driving circuit 21, that is, connected to the gate of the first transistor T1. It should be noted that the embodiments of the present disclosure are not limited thereto, and the data writing circuit 22 may also be a circuit composed of other components.
  • the sensing circuit 24 may be implemented as a fourth transistor T4.
  • the gate electrode of the fourth transistor T4 is connected to the second scan line S2 to receive the second scan signal.
  • the first electrode of the fourth transistor T4 is connected to the second terminal 212 (second node N2) of the driving circuit 21.
  • the fourth transistor T4 The second pole is connected to the sensing signal line Sen. It should be noted that the embodiments of the present disclosure are not limited thereto, and the sensing circuit 24 may also be a circuit composed of other components.
  • the storage circuit 23 may be implemented as a storage capacitor C1.
  • the first pole of the storage capacitor C1 is connected as the first terminal 231 of the storage circuit 23 and the first node N1, and the second pole of the storage capacitor C1 is connected as the second terminal 232 of the storage circuit 23 and the second node N2. It should be noted that the embodiments of the present disclosure are not limited thereto.
  • the storage circuit 23 may also be a circuit composed of other components.
  • the storage circuit 23 may include two capacitors connected in parallel/series with each other.
  • the light-emitting element L may be implemented as an organic light-emitting diode (OLED).
  • OLED organic light-emitting diode
  • the anode of the organic light-emitting diode is connected as the first terminal L01 and the second node N2 of the light-emitting element L and is configured to receive a driving current from the second terminal 212 of the driving circuit 21.
  • the cathode of the light-emitting diode is connected as the second terminal L02 of the light-emitting element L and the second voltage terminal VSS to receive the second voltage.
  • the cathodes of the light-emitting elements L in the pixel circuits 20 of each pixel unit can be electrically connected to the same voltage terminal, that is, the display panel adopts a common cathode connection method. .
  • the third transistor T3, the fourth transistor T4, the first scan line S1, and the second scan line S2 can be located on the same side of the first transistor T1, thereby facilitating wiring and having Conducive to increasing the opening ratio.
  • the first voltage terminal VDD in various embodiments of the present disclosure, for example, maintains an input DC high level signal, and the DC high level is called the first voltage;
  • the second voltage terminal VSS For example, the DC low level signal is kept input, and the DC low level is called the second voltage (which may be the ground voltage), and is lower than the first voltage.
  • the first voltage terminal VDD in various embodiments of the present disclosure, for example, maintains an input DC high level signal, and the DC high level is called the first voltage
  • the second voltage terminal VSS For example, the DC low level signal is kept input, and the DC low level is called the second voltage (which may be the ground voltage), and is lower than the first voltage.
  • FIG. 4 is a timing diagram of the circuit structure shown in FIG. 3 .
  • the following is a brief description of the sensing working principle of the pixel circuit 20 shown in FIG. 3 in conjunction with the signal timing diagram shown in FIG. 4 , and here, each transistor is an N-type transistor as an example.
  • the embodiment of the present disclosure Not limited to this.
  • the sensing stage includes two stages, namely the detection data writing stage P1 and the electrical detection stage P2.
  • Figure 4 shows the timing waveforms of each signal in each stage.
  • the first scanning signal (provided by the first scanning line S1) and the detection data signal (provided by the data line Vdata) are input to turn on the data writing circuit 22 and the driving circuit 21.
  • the data writing circuit 22 will detect The data signal is written into the driving circuit 21, the storage circuit 23 stores the detection data signal, and the sensing signal line Sen provides the second voltage.
  • the third transistor T3 is turned on by the high level of the first scan signal
  • the first transistor T1 is turned on by the high level of the first node N1
  • the fourth transistor T4 is turned on by the high level of the second scan signal.
  • a data writing path is formed, and the storage capacitor C1 is charged after the detection data signal passes through the third transistor T3.
  • the sensing signal line Sen provides the second voltage, that is, the level of the second node N2 is the second voltage.
  • the voltage information with the detection data signal is stored in the storage capacitor C1 for use in the next stage.
  • the fourth transistor T4 is turned off, and at this time, there is no need to provide the second voltage to the sensing signal line Sen.
  • the second scan signal (provided by the second scan line S2) is input to turn on the sensing circuit 24.
  • the sensing circuit 24 electrically connects the second end 212 of the driving circuit 21 to the sensing signal line Sen.
  • the test signal line Sen is in a floating state.
  • the third transistor T3 is turned on by the high level of the first scan signal
  • the first transistor T1 is turned on by the high level of the first node N1
  • the fourth transistor T4 is turned on by the high level of the second scan signal.
  • a current transmission path is formed, and the current flowing through the first transistor T1 is transmitted to the sensing signal line Sen through the fourth transistor T4, and is processed by the subsequent detection circuit.
  • the sensing signal line Sen is in a floating state. Since the resistance of the sensing signal line Sen is much smaller than the resistance of the light-emitting element L, there is no current or substantially no current in the light-emitting element L at this time, and the light-emitting element L does not emit light.
  • the electrical detection stage P2 After the electrical detection stage P2, through the processing of subsequent detection circuits (for example, operational amplifiers, analog-to-digital converters, etc.), the current flowing through the first transistor T1 is converted into a voltage signal, and then converted into a digital signal and the resulting The obtained signal is stored, and the signal is further processed by an algorithm to obtain compensation data. Then, during the normal light-emitting stage of the pixel circuit 20, the compensation data obtained by the algorithm processing is The data is superimposed on the input display data to obtain compensated display data. The compensated display data can be written through the data writing circuit 22 to control the driving circuit 21, so that the transistor (first transistor) in the driving circuit 21 can be compensated. Differences in display brightness uniformity caused by differences in threshold voltage and mobility of T1).
  • the subsequent detection circuit is not included in the pixel circuit 20 and can be implemented using a conventional circuit structure, so it will not be described in detail.
  • first scan signal (provided by the first scan line S1) and the second scan signal (provided by the second scan line S2) are the same signal (as shown in Figure 4), but Embodiments of the present disclosure are not limited thereto.
  • the first scanning signal and the second scanning signal may also be different signals, and their waveforms may be different from each other, which may be determined according to actual requirements.
  • the electrical detection phase P2 When the first scan signal and the second scan signal are the same signal, in the electrical detection phase P2, a valid detection data signal must still be maintained to prevent leakage of the storage capacitor C1 from affecting the turning on/off of the first transistor T1 degree, thereby avoiding affecting the accuracy of detection data.
  • the first scan signal and the second scan signal are different signals, in the electrical detection phase P2, if the first scan signal is not turned on, there is no need to maintain a valid detection data signal, and the storage capacitor C1 will not pass through at this time.
  • the third transistor T3 leaks electricity, so it does not affect the on/off degree of the first transistor T1 and does not affect the accuracy of the detection data.
  • FIG. 5A is a schematic block diagram of another pixel circuit in a display panel provided by some embodiments of the present disclosure.
  • the pixel circuit 20 may also include a reset circuit 26 , and other structures are substantially the same as the pixel circuit 20 shown in FIG. 2 .
  • the reset circuit 26 is connected to the control terminal 213 (the first node N1 ) of the driving circuit 21 and is configured to apply a reset voltage to the control terminal 213 of the driving circuit 21 and the first terminal 231 of the storage circuit 23 in response to the reset signal, thereby causing the second A node N1 and various components electrically connected thereto are reset.
  • the reset circuit 26 is connected to the first node N1, the reset voltage terminal Vr, and the reset signal line Rst respectively.
  • the reset circuit 26 may be turned on in response to the reset signal provided by the reset signal line Rst, so that the reset voltage provided by the reset voltage terminal Vr may be applied to the first node N1 , the first terminal 231 of the storage circuit 23 and the driving circuit 21
  • the control terminal 213 can thereby perform a reset operation on the storage circuit 23 and the driving circuit 21 to eliminate the influence of the previous light-emitting stage.
  • the reset voltage may be provided by an independent reset voltage terminal Vr, which is different from the second voltage terminal VSS.
  • the reset voltage terminal Vr and the second voltage terminal VSS are the same voltage terminal, and the reset voltage and the second voltage are the same voltage signal. That is, the reset voltage can be provided by the second voltage terminal VSS (at this time, the second voltage terminal VSS is multiplexed as the reset voltage terminal Vr, and the second voltage is multiplexed as the reset voltage). Accordingly, the reset circuit 26 is connected to The second voltage terminal VSS is not limited in the embodiments of the present disclosure.
  • the second voltage terminal VSS is a low voltage terminal (its voltage is lower than the voltage of the first voltage terminal VDD), such as a ground terminal.
  • FIG. 5B is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 5A.
  • the pixel circuit 20 shown in FIG. 5B is basically the same as the pixel circuit 20 shown in FIG. 3 , except that the pixel circuit 20 shown in FIG. 5B further includes a fifth transistor T5 to implement the reset circuit 26 .
  • the reset circuit 26 may be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the reset signal line Rst to receive the reset signal
  • the first electrode of the fifth transistor T5 is connected to the reset voltage terminal Vr to receive the reset voltage
  • the second electrode of the fifth transistor T5 is connected to the drive circuit 21
  • the control terminal 213 (first node N1) is connected, that is, connected to the gate of the first transistor T1.
  • the embodiments of the present disclosure are not limited thereto, and the reset circuit 26 may also be a circuit composed of other components.
  • the symbol Vdata can represent both a data line and a level of a data signal.
  • the symbol Rst can represent both the reset signal line and the level of the reset signal
  • the symbol VDD can represent both the first voltage terminal and the first voltage
  • the symbol VSS can represent both the second voltage terminal and the second voltage terminal.
  • Voltage the symbol S1 can represent both the first scan line and the level of the first scan signal
  • the symbol S2 can represent both the second scan line and the level of the second scan signal
  • the symbol Vr can represent the reset voltage terminal.
  • It can also represent the reset voltage
  • the symbol Sen can represent both the sensing signal line and the level of the signal transmitted on the sensing signal line.
  • first node N1 and the second node N2 do not represent actual existing components, but represent the meeting points of relevant electrical connections in the circuit diagram.
  • the pixel circuit 20 may also include other circuit structures with internal compensation functions.
  • the internal compensation function can be implemented through voltage compensation, current compensation or hybrid compensation.
  • the pixel circuit 20 with the internal compensation function can be, for example, a combination of a 4T1C or 4T2C circuit and a sensing circuit 24 .
  • the data writing circuit 22 and the internal compensation circuit cooperate to write a voltage value carrying the data signal and the threshold voltage information of the driving transistor (first transistor T1) in the driving circuit 21 into the drive circuit 21 control terminal 213 and stored through the storage circuit 23.
  • Specific examples of internal compensation circuits will not be described in detail here.
  • the pixel circuit 20 may also include a light emission control circuit and the like to achieve more comprehensive functions.
  • the transistors used in various embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so there can be no structural difference between the source and drain.
  • one of the poles is directly described as the first pole and the other pole is the second pole.
  • the transistors in the pixel circuit 20 shown in FIG. 3 and FIG. 5B are all N-type transistors.
  • the first electrode may be the source electrode
  • the second electrode may be the source electrode. drain.
  • the transistors in the pixel circuit 20 can also use only P-type transistors or a mixture of P-type transistors and N-type transistors. It is only necessary to simultaneously set the port polarity of the selected type of transistor according to the port polarity of the corresponding transistor in the embodiment of the present disclosure. Just connect accordingly.
  • IGZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Polysilicon
  • amorphous silicon such as hydrogenated non-crystalline silicon
  • the storage capacitor C1 can be a capacitor device manufactured through a process, for example, a capacitor device is realized by making special capacitor electrodes.
  • Each electrode of the capacitor can be formed through a metal layer or a semiconductor layer. (such as doped polysilicon), and the storage capacitor C1 can also be a parasitic capacitance between various devices, which can be realized by the transistor itself and other devices and circuits.
  • the connection method of the storage capacitor C1 is not limited to the method described above, and can also be other applicable connection methods, as long as the level written to the first node N1 can be stored.
  • the pixel circuit 20 provided by the embodiment of the present disclosure can reduce the probability of damage to the organic light-emitting diode (OLED) device, protect the OLED device, and extend the service life of the OLED device.
  • OLED organic light-emitting diode
  • the pixel circuit 20 also emits light in the display phase to display a picture.
  • the driving circuit 21 and the protection circuit 25 jointly provide a driving current to drive the light-emitting element L to emit light.
  • the basic working methods of the data writing circuit 22, the storage circuit 23, the driving circuit 21, and the light-emitting element L in the display stage please refer to Conventional design will not be described in detail here.
  • the second transistor T2 has a positive feedback function and provides a driving current together with the first transistor T1. Therefore, compared with the usual situation where only the driving transistor provides the driving current, the channel current of the first transistor T1 in the pixel circuit 20 provided by the embodiment of the present disclosure needs to be appropriately reduced, so that the first transistor T1 and the second The driving current provided by the transistors T2 together remains unchanged, so that the light-emitting element L displays the required gray scale.
  • the current-voltage curve characteristics of the first transistor T1 need to be adjusted. For example, this can be achieved by changing the channel width to length ratio of the first transistor T1. Assume that the channel width to length ratio of a common driving transistor is 18:6. For the first transistor T1 in the embodiment of the present disclosure, its channel The width-to-length ratio can be reduced to 16.5:6. Of course, embodiments of the present disclosure are not limited thereto. In other examples, the channel width to length ratio of the first transistor T1 may be reduced by 10% to 30% compared to the channel width to length ratio of a common driving transistor. For example, the channel width-to-length ratio of the first transistor T1 ranges from 12.6:6 to 16.2:6, thereby reducing the driving current flowing through the first transistor T1 and leaving room for the driving current generated by the second transistor T2 margin.
  • the channel width to length ratio of the first transistor T1 ranges from 12.6:6 to 16.2:6, thereby reducing the driving current flowing through the first transistor T1 and leaving room for the driving current generated by
  • FIG. 6A is a schematic cross-sectional view of an array substrate in a display panel according to some embodiments of the present disclosure.
  • the array substrate 101 includes a base substrate 111 , a buffer layer 112 , and a gate insulating layer 113 .
  • the first transistor T1 includes an active layer 1141 .
  • the buffer layer 112 is provided on the base substrate 111
  • the active layer 1141 is provided on the buffer layer 112
  • the gate insulating layer 113 is provided on the buffer layer 112 and covers the active layer 1141
  • the gate electrode 1142 of the first transistor T1 is provided on the gate on the insulating layer 113.
  • the array substrate 101 further includes an interlayer insulating layer 115 .
  • the interlayer insulating layer 115 is disposed on the gate insulating layer 113 and covers the gate electrode 1142 of the first transistor T1.
  • the first electrode 1143 of the first transistor T1 and the second electrode 1144 of the first transistor T1 are disposed on the interlayer insulating layer 115. . Therefore, the first transistor T1 forms a top-gate structure.
  • the first electrode 1143 and the second electrode 1144 of the first transistor T1 are located on the same layer.
  • the first electrode 1143 and the second electrode 1144 are located in a different film layer than the gate electrode 1142. film layer, thereby improving wiring flexibility.
  • the array substrate 101 also includes a data line Vdata, which is used to transmit data information. Number.
  • the data line Vdata is disposed on the interlayer insulating layer 115.
  • the data line Vdata is located on the same layer as the first electrode 1143 of the first transistor T1 and the second electrode 1144 of the first transistor T1, thereby reducing processes and improving manufacturing efficiency.
  • the first electrode 1143 of the first transistor T1 is connected to the active layer 1141 through at least the first via hole H1 penetrating the gate insulating layer 113
  • the second electrode 1144 of the first transistor T1 passes through at least the second through hole H1 penetrating the gate insulating layer 113
  • the via H2 is connected to the active layer 1141 .
  • the first via hole H1 penetrates the gate insulating layer 113 and the interlayer insulating layer 115
  • the second via hole H2 also penetrates the gate insulating layer 113 and the interlayer insulating layer 115 .
  • the portion of the active layer 1141 exposed by the first via hole H1 and/or the second via hole H2 is a conductive region formed by plasma doping.
  • the array substrate 101 further includes a light shielding layer 116 .
  • the light-shielding layer 116 is disposed on the base substrate 111
  • the buffer layer 112 is disposed on the base substrate 111 and covers the light-shielding layer 116 .
  • the light shielding layer 116 can prevent stray light from adversely affecting the active layer 1141 .
  • the material of the light-shielding layer 116 is metal.
  • the light-shielding layer 116 can have a double-layer metal structure to reduce resistance and improve impedance characteristics and electromagnetic compatibility characteristics.
  • the light-shielding layer 116 can also be a single-layer metal structure, a three-layer metal structure, or other applicable multi-layer metal structures, which can be determined according to actual needs, and the embodiments of the present disclosure are not limited to this.
  • the portion of the light shielding layer 116 that overlaps with the active layer of the second transistor T2 (not shown in FIG. 6A ) is multiplexed as the gate of the second transistor T2 , so that the first transistor T1 and the second transistor T2 form a vertical type double-gate transistor, thus improving the electrical characteristics and simplifying the manufacturing process.
  • the first electrode 1143 of the first transistor T1 is multiplexed as the first electrode of the second transistor T2, and the first electrode of the first transistor T1 is multiplexed.
  • the diode 1144 is multiplexed as the second pole of the second transistor T2. That is, the first electrode 1143 serves as both the first electrode of the first transistor T1 and the first electrode of the second transistor T2; the second electrode 1144 serves as both the second electrode of the first transistor T1 and the second transistor.
  • the second electrode of the second transistor T2 that is, the second electrode 1144 shown in FIG.
  • the sixthA is connected to the light-shielding layer 116 through at least the third via hole H3 that penetrates the buffer layer 112 and the gate insulation layer 113 .
  • the third via hole H3 penetrates the buffer layer 112 , the gate insulating layer 113 and the interlayer insulating layer 115 .
  • FIG. 6B is a schematic cross-sectional view of another array substrate in a display panel provided by some embodiments of the present disclosure.
  • the array substrate 101 includes a base substrate 111 , a buffer layer 112 , and a gate insulating layer 113 .
  • the first transistor T1 includes an active layer 1141 . Buffer layer 112 settings On the base substrate 111, the active layer 1141 is provided on the buffer layer 112, the gate insulating layer 113 is provided on the buffer layer 112 and covers the active layer 1141, and the gate electrode 1142 of the first transistor T1 is provided on the gate insulating layer 113. .
  • the first electrode 1143 of the first transistor T1 and the second electrode 1144 of the first transistor T1 are provided on the gate insulating layer 113.
  • the first electrode 1143 of the first transistor T1, the second electrode 1144 of the first transistor T1, and The gate 1142 of a transistor T1 is located on the same layer. Therefore, the first transistor T1 forms a top-gate structure, and the first electrode 1143, the second electrode 1144, and the gate electrode 1142 of the first transistor T1 are located on the same layer, such as the gate metal layer, thereby reducing the cost of the array substrate 101. Thickness, reducing the number of film layers to make the array substrate 101 light and thin.
  • the array substrate 101 also includes a data line Vdata, and the data line Vdata is used to transmit data signals.
  • the data line Vdata is disposed on the gate insulating layer 113.
  • the data line Vdata is located on the same layer as the gate electrode 1142 of the first transistor T1, the first electrode 1143 of the first transistor T1, and the second electrode 1144 of the first transistor T1, thereby reducing the number of processes. , improve preparation efficiency.
  • first electrode 1143, the second electrode 1144, and the gate electrode 1142 of the first transistor T1 are located on the same layer, the first electrode 1143, the second electrode 1144, and the gate electrode 1142 are separated from each other and are not on the same layer. direct connection to avoid short circuits.
  • the interlayer insulating layer 115 is not provided, other components of the film structure shown in FIG. 6B are basically the same as the film structure shown in FIG. 6A. For relevant descriptions, please refer to the relevant description above and will not be repeated here.
  • FIG. 7 is a schematic cross-sectional view of another array substrate in a display panel provided by some embodiments of the present disclosure.
  • one of the first electrode 1143 of the first transistor T1 and the second electrode 1144 of the first transistor T1 is the drain of the first transistor T1
  • the first via H1 and the first via H1 are Among the two via holes H2, the via hole adjacent to the drain of the first transistor T1 and the third via hole H3 are the same via hole.
  • the second electrode 1144 of the first transistor T1 is the drain
  • the via hole adjacent to the drain electrode is the second via hole H2
  • the second via hole H2 and the third via hole H3 are the same via hole.
  • the second via hole H2 and the third via hole H3 are connected with each other and together form one via hole.
  • the preparation process can be simplified.
  • the drain electrode of the first transistor T1 that is, the second electrode 1144
  • the third via hole H3 thereby realizing the circuit structure shown in FIG. 3 connection method.
  • other components of the film layer structure shown in Figure 7 are basically the same as the film layer structure shown in Figure 6A.
  • FIG. 8 is a schematic plan view of an active layer in a display panel according to some embodiments of the present disclosure.
  • the active layer 1141 includes at least one grooved region 117.
  • the region 117 is a hole penetrating the active layer 1141 in a direction perpendicular to the base substrate 111 .
  • the number of grooved areas 117 included in the active layer 1141 is 1, that is, the active layer 1141 includes one grooved area 117 .
  • One of the first pole 1143 of the first transistor T1 and the second pole 1144 of the first transistor T1 is the source of the first transistor T1, and the first via H1 and the second via H2 are connected to the source of the first transistor T1.
  • the very adjacent via hole is the target via hole, and the grooved area 117 is adjacent to the target via hole.
  • the first electrode 1143 of the first transistor T1 is the source electrode
  • the first via hole H1 is a via hole adjacent to the source electrode of the first transistor T1. Therefore, the first via hole H1 is a target via hole, and the first via hole H1 is a target via hole.
  • the groove area 117 is adjacent to the first via hole H1.
  • the grooved area 117 is rectangular in shape.
  • the shape of the grooved area 117 can also be any shape such as square, trapezoid, circle, ellipse, irregular polygon, etc., which can be determined according to actual needs. Embodiments of the present disclosure There are no restrictions on this.
  • Figure 9A is a schematic cross-sectional view along line A-A’ in Figure 8
  • Figure 9B is a schematic cross-sectional view along line B-B’ in Figure 8.
  • the grooved area 117 is adjacent to the first via hole H1, that is, the grooved area 117 is provided at an end of the active layer 1141 close to the first via hole H1.
  • the grooved area 117 is a hole penetrating the active layer 1141 in a direction perpendicular to the base substrate 111. That is, in the grooved area 117, the active layer 1141 is missing due to being dug. Elsewhere outside of trenched area 117, active layer 1141 is not trenched and is therefore continuous.
  • the target via (first via H1 ) exposes a portion of the active layer 1141 , and a portion of the buffer layer 112 is exposed through the grooved region 117 .
  • the light-shielding layer 116 is not shown. This is only for simplicity and does not constitute a limitation on the embodiments of the present disclosure.
  • the first transistor T1 can be reduced in size while maintaining the channel shape/width-to-length ratio of the first transistor T1.
  • the channel current of the transistor T1 causes the reduced current to be compensated by the second transistor T2 of the protection circuit 25 through positive feedback, so that the driving current provided by the first transistor T1 and the second transistor T2 together meets the expected magnitude. Since the channel shape/width-to-length ratio of the first transistor T1 remains unchanged, the degree of change in layout design can be minimized and the workload of layout design can be reduced.
  • FIG. 10 is a schematic diagram showing various dimensions of the active layer shown in FIG. 8 .
  • the reference width of the active layer 1141 is Wd
  • the reference width Wd is the width of the active layer when there is no groove and only the first transistor T1 provides a driving current.
  • the width of the grooved area 117 is Wvia
  • the effective width of the active layer 1141 at the grooved area 117 is W1
  • the reference length Ld is the length of the active layer in the case where there is no groove and only the driving current is provided by the first transistor T1.
  • the current integral calculation of the first transistor T1 (the first transistor T1 has been dug) can be calculated using the following formula:
  • ⁇ is the carrier mobility
  • Cgi is the dielectric constant of the gate insulating layer
  • Vgs is the gate-source voltage
  • Vth is the threshold voltage
  • Vds is the drain-source voltage.
  • these electrical parameters can be set to the same constant values for trenched and untroughed trench designs.
  • I and dy are independent variables in the integral calculation.
  • the integral calculation of the channel current of a transistor without a trench can be calculated using the following formula:
  • the preset channel current of the first transistor T1 is expressed as I1, and the preset channel current I1 is the channel current when there is no slot and only the first transistor T1 provides a driving current.
  • the trench channel current of the first transistor T1 is represented by I2, and the trench channel current I2 is the channel current of the first transistor T1 after trenching.
  • the trenching channel current I2 corresponds to the above formula (1-1)
  • the preset channel current I1 corresponds to the above formula (1-2). Therefore, according to the above formula (1-1) and formula (1-2), The ratio of I2 to I1 can be obtained, which satisfies the following formula:
  • the value range of I2/I1 is 1 to 1.5, that is, the ratio range of the above formula is 1 to 1.5, so that the current loss caused by forming the trench in the trench will not be too large, so that the current The loss is within 50%, so that the size of the grooved area 117 is not too large, thereby preventing the grooved area 117 from affecting the stability of the layer structure and the stability of the circuit characteristics.
  • the initial channel current of the first transistor T1 is expressed as Id.
  • the initial channel current Id of the first transistor T1 is equal to the trench channel current I2 of the first transistor T1. That is, the initial channel current Id of the first transistor T1 is equal to the situation when the first transistor T1 has been trenched. channel current below. Therefore, the initial channel current Id corresponds to the above formula (1-1).
  • the channel width of the second transistor T2 is W3, and the channel length of the second transistor T2 is L3.
  • the following formula can be used:
  • Cbuf is the capacitance of the gate insulating layer of the second transistor T2. Since the light shielding layer 116 is multiplexed as the gate of the second transistor T2, the capacitance Cbuf of the gate insulating layer of the second transistor T2 is the capacitance of the buffer layer 112. .
  • the thickness of the buffer layer 112 is dbuf
  • the channel current of the second transistor T2 is Ie.
  • Ie and Id satisfy the following formula:
  • the numerical range of Id/Ie is 0.5-1, that is, the ratio range of the above formula is 0.5-1, and the above ratio reaches at least 50%. Therefore, the driving current reduced by the first transistor T1 due to trenching can be supplemented by the second transistor T2 in parallel with the first transistor T1, thereby maintaining the charging characteristics unchanged.
  • the value range of I2/I1 is 1 to 1.5, and the value range of Id/Ie is 0.5 to 1. Therefore, the size of the trench formed in the channel of the first transistor T1 will not be too large and will not cause excessive current loss. , the current loss ratio is within 50%, and the parallel second transistor T2, as a vertical double-gate transistor of the first transistor T1, can supplement the current, and the ratio of Id/Ie reaches at least 50%. As a result, the entire circuit can achieve better electrical characteristics.
  • various parameters are measured.
  • each parameter is designed as follows.
  • W1 16.84 ⁇ m
  • Ld 31.43 ⁇ m
  • W2 12.19 ⁇ m
  • Wd 16.84 ⁇ m
  • L2 2.39 ⁇ m
  • Wvia 4.65 ⁇ m
  • W3 16.84 ⁇ m
  • L3 28 ⁇ m.
  • the display screen size is smaller than that of the above example, the area of a single OLED pixel unit (or sub-pixel) is smaller, and the effective display area of the organic light-emitting material is reduced so that the driving As the current decreases, the channel width-to-length ratio and channel area of the driving transistor (first transistor T1) also decreases.
  • the decrease in channel size causes the trench trench size (trench area size) to also decrease, and as Size reduction requires a corresponding increase in process yield (process size deviation and process size alignment) (for example, the same 2-micron deviation accounts for 1/15 of the 30-micron feature size, but accounts for 1/5 of the 10-micron feature size, so greater impact).
  • the proportion of the trench trench (grooved area) in the trench and the impact on current loss are reduced, and after the pixel becomes smaller, in order to ensure the aperture ratio, the light-shielding layer metal (light-shielding layer 116 complex
  • the area used as the gate electrode of the parallel-connected second transistor T2 is also reduced, so that the supplementary current of the parallel-connected second transistor T2 is also reduced accordingly. Therefore, the maximum and minimum value ranges are respectively set for the two current ratios I2/I1 and Id/Ie, which can adapt to different size display screens, different driving current requirements caused by different organic light-emitting materials, as well as different pixel sizes and different transistor sizes. design requirements.
  • Figure 11 is a schematic plan view of an active layer in another display panel provided by some embodiments of the present disclosure.
  • Figure 12A is a schematic cross-sectional view of line CC' in Figure 11.
  • Figure 12B is a schematic cross-sectional view of line D-D' in Figure 11.
  • the grooved area 117 includes two grooved areas, namely a first grooved area 1171 and a second grooved area 1172.
  • the first grooved area 1171 is adjacent to the first via hole H1
  • the second grooved area 1172 is adjacent to the second via hole H2.
  • grooved regions are provided on both the source and the drain of the first transistor T1 , so that the driving current provided by the first transistor T1 can be further reduced.
  • the first grooved area 1171 and the second grooved area 1172 are holes penetrating the active layer 1141 in a direction perpendicular to the base substrate 111 , that is, within the first grooved area 1171 and the second grooved area 1172 , the active layer 1141 is missing due to being trenched. At other locations than the first grooved area 1171 and the second grooved area 1172, the active layer 1141 is not grooved and is therefore continuous. It should be noted that in Figure 12A and Figure In 12B, the light-shielding layer 116 is not shown. This is only for simplicity and does not constitute a limitation on the embodiments of the present disclosure.
  • the first via hole H1 exposes a portion of the active layer 1141 and exposes a portion of the buffer layer 112 through the first grooved area 1171; and/or the second via hole H2 exposes a portion of the active layer 1141 and passes through the first grooved area 1171.
  • the two grooved areas 1172 expose a portion of the buffer layer 112 .
  • both the first grooved area 1171 and the second grooved area 1172 are rectangular in shape.
  • the shapes of the first grooved area 1171 and the second grooved area 1172 can also be any shape such as square, trapezoid, circle, ellipse, irregular polygon, etc., which can be based on actual conditions. It depends on the requirements, and the embodiments of the present disclosure do not limit this.
  • the shape of the first grooved area 1171 and the shape of the second grooved area 1172 may be the same or different.
  • the size of the first grooved area 1171 is the same as the size of the second grooved area 1172.
  • the same size can mean having the same shape and the same length of each side, or it can also mean the same area.
  • the embodiments of the present disclosure are not limited thereto, and the sizes of the first grooved area 1171 and the second grooved area 1172 may also be different from each other, for example, one of the first grooved area 1171 and the second grooved area 1172 is not limited to this.
  • the size of the area is larger, and the size of the other one of the first grooved area 1171 and the second grooved area 1172 is smaller, which can be determined according to actual needs, and the embodiment of the present disclosure does not limit this.
  • the first grooved area 1171 and the second grooved area 1172 can be arranged symmetrically, for example, both are axially symmetrical.
  • the channel shape/width-to-length ratio of the first transistor T1 can be maintained.
  • the channel current of the first transistor T1 is reduced, so that the reduced current is compensated by the second transistor T2 of the protection circuit 25 through positive feedback, so that the first transistor T1 and the second transistor T2 jointly provide a driving The current is as expected. Since the channel shape/width-to-length ratio of the first transistor T1 remains unchanged, the degree of change in layout design can be minimized and the workload of layout design can be reduced.
  • the current of the first transistor T1 can be further reduced.
  • the above calculation formula for the channel current of one grooved area is still applicable and will not be described again here.
  • FIG. 13A to 13C are schematic diagrams of an etching process of an array substrate in a display panel according to some embodiments of the present disclosure.
  • a part of the active layer 1141 can be etched, so that the active layer 1141 is disconnected at the via hole to form a grooved area, so that the active layer 1141 is located at the via hole. is partially disconnected, causing the via hole to expose a portion of the active layer 1141 and expose the buffer layer 112 a part of.
  • IGZO oxide is used as the material of the active layer 1141.
  • the gate metal layer GM is coated and patterned.
  • the gate metal layer GM is used to form structures such as the gate electrode 1142.
  • a self-alignment process is used to etch the entire surface of the gate insulating layer 113 to form a tail (GI Tail), and an IGZO conductorization process is performed.
  • GI Tail tail
  • an IGZO conductorization process is performed.
  • the IGZO is missing, thus forming a grooved area. It should be noted that this will not affect signal transmission.
  • FIG. 14 is a schematic cross-sectional view of an array substrate in a display panel according to some embodiments of the present disclosure.
  • the third via hole H3 has a first side wall H31 and a second side wall H32 opposite to each other.
  • the first side wall H31 is close to the active layer 1141 and the second side wall H32 is away from the active layer 1141 .
  • the slope of the first side wall H31 is different from the slope of the second side wall H32.
  • the slope of the first side wall H31 is greater than the slope of the second side wall H32.
  • the slope refers to the steepness and gentleness of the first side wall H31 and the second side wall H32, and may be the tangent value of the slope angle.
  • the slope angle of the first side wall H31 is a1
  • the slope angle of the second side wall H32 is a2
  • the slope of the first side wall H31 is greater than the second side wall H32 slope.
  • the third via H3 is to multiplex the second electrode of the second transistor T2 (the second electrode 1143 of the first transistor T1 can be multiplexed as the second electrode of the second transistor T2) with the gate of the second transistor T2.
  • the via holes are connected to the light-shielding layer 116 of the pole. Due to the different etching thicknesses on both sides, only the buffer layer 112 is over-etched on one side of the third via hole H3, making the slope steeper (that is, the slope of the first sidewall H31 is steeper), which is beneficial to increasing the balance gate metal layer GM.
  • the contact area with the light shielding layer 116 is to multiplex the second electrode of the second transistor T2 (the second electrode 1143 of the first transistor T1 can be multiplexed as the second electrode of the second transistor T2) with the gate of the second transistor T2.
  • the via holes are connected to the light-shielding layer 116 of the pole. Due to the different etching thicknesses on both sides, only the buffer layer 112 is over-
  • the buffer layer 112 and the gate insulating layer 113 are etched on the other side of the third via hole H3, so that the slope is smaller (that is, the slope of the second side wall H32 is smaller), which is beneficial to adhesion to the second side wall H32.
  • Metal material on the climb is etched on the other side of the third via hole H3, so that the slope is smaller (that is, the slope of the second side wall H32 is smaller), which is beneficial to adhesion to the second side wall H32.
  • Metal material on the climb is beneficial to adhesion to the second side wall H32.
  • FIG. 15 is a schematic cross-sectional view of an array substrate in another display panel provided by some embodiments of the present disclosure.
  • the array substrate 101 also includes a gate metal layer GM, a passivation layer 118 and a planarization layer 119 .
  • the gate metal layer GM is disposed on the gate insulating layer 113, and the passivation layer 118 and the planarization layer 119 are stacked in sequence.
  • the gate electrode 1142 of the first transistor T1 the first electrode 1143 of the first transistor T1, and the second electrode 1144 of the first transistor T1 are provided on the same layer, the gate electrode 1142, the first electrode 1144 of the first transistor T1
  • the first pole 1143 of the transistor T1 and the second pole 1144 of the first transistor T1 are located in the gate metal layer GM.
  • the gate electrode 1142 of the first transistor T1 is located on the gate metal. Layer GM.
  • the passivation layer 118 is provided on the gate metal layer GM.
  • the first end L01 of the light-emitting element L is an anode.
  • the anode is connected to the transfer part GMP located on the gate metal layer GM through the fourth via hole H4 that penetrates the passivation layer 118.
  • the transfer part GMP is connected to the light shielding part through the third via hole H3.
  • Layer 116 is connected to the second pole 1144 of the first transistor T1.
  • the distance between the edges of the fourth via hole H4 and the third via hole H3 that are close to each other is das.
  • the aperture of the third via hole H3 in the plane where the gate metal layer GM is located is ds. das and ds satisfy the following relationship:
  • das ds, that is, the distance between the edges of the fourth via hole H4 and the third via hole H3 that are close to each other is equal to the aperture of the third via hole H3 in the plane where the gate metal layer GM is located.
  • the distance between the edge of the second pole 1144 of the first transistor T1 away from the third via hole H3 and the edge of the second pole 1144 of the first transistor T1 close to the third via hole H3 is dgs
  • the third via hole The aperture of H3 in the plane of the gate metal layer GM is ds, and dgs and ds satisfy the following relationship:
  • dgs ds, that is, the edge of the second pole 1144 of the first transistor T1 away from the third via hole H3 and the edge of the second pole 1144 of the first transistor T1 close to the third via hole H3
  • the distance between the edges is equal to the aperture of the third via hole H3 in the plane where the gate metal layer GM is located.
  • the third via hole H3 By adjusting the distance dgs between the edge of the second pole 1144 of the first transistor T1 away from the third via hole H3 and the edge of the second pole 1144 of the first transistor T1 close to the third via hole H3, the third via hole H3
  • the aperture ds in the plane where the gate metal layer GM is located satisfies the above relationship, which is beneficial to reducing edge exposure unevenness due to uneven thickness during photolithography of the planarization layer 119, and can reduce similar process deviations.
  • FIG. 16 is a schematic cross-sectional view of an array substrate in another display panel provided by some embodiments of the present disclosure.
  • the array substrate 101 further includes a passivation layer 118 and a planarization layer 119 .
  • One of the first electrode 1143 of the first transistor T1 and the second electrode 1144 of the first transistor T1 is the drain electrode of the first transistor T1.
  • the second electrode 1144 of the first transistor T1 is the drain electrode.
  • the passivation layer 118 and the planarization layer 119 are stacked in sequence and are located on the drain electrode of the first transistor T1 (that is, located on the second electrode 1144 of the first transistor T1).
  • the passivation layer 118 and the planarization layer 119 have a fifth via hole H5.
  • the fifth via hole H5 penetrates the passivation layer 118 and the planarization layer 119, and the fifth via hole H5 exposes the drain of the first transistor T1.
  • the fifth via hole H5 includes a step located at the interface of the passivation layer 118 and the planarization layer 119 , and the width of the step is less than or equal to 1 ⁇ m.
  • the light-shielding layer 116 is disposed on the base substrate 111
  • the buffer layer 112 is disposed on the base substrate 111 and covers the light-shielding layer 116
  • the light-shielding layer 116 is made of metal
  • the light-shielding layer 116 is multiplexed as the gate of the second transistor T2 .
  • the orthographic projection of the fifth via hole H5 in the direction perpendicular to the base substrate 111 is at least partially the orthographic projection of the portion of the light shielding layer 116 that is multiplexed as the gate of the second transistor T2 in the direction perpendicular to the base substrate 111 overlap.
  • the portion of the light-shielding layer 116 that is multiplexed as the gate of the second transistor T2 is, for example, T2G shown in FIG.
  • the orthographic projections of the holes H5 in the direction perpendicular to the base substrate 111 at least partially overlap (for example, they may completely overlap or partially overlap).
  • the portion of the light-shielding layer 116 that is multiplexed as the gate of the second transistor T2 may be the portion of the light-shielding layer 116 that overlaps the active layer 1201 of the second transistor T2 in a direction perpendicular to the base substrate 111 .
  • the light shielding layer 116 is also multiplexed as the gate of the fourth transistor T4, and the light shielding layer 116 can also be multiplexed as the first voltage terminal VDD. It should be noted that the light-shielding layer 116 can be reused as any one or more of the gate electrode of the second transistor T2, the gate electrode of the fourth transistor T4, and the first voltage terminal VDD. This can be determined according to actual needs. The disclosed embodiments do not limit this.
  • the light-shielding layer 116 can only be reused as the gate of the second transistor T2; the light-shielding layer 116 can only be reused as the gate of the fourth transistor T4; the light-shielding layer 116 can only be reused as the first voltage terminal VDD;
  • the light layer 116 can be multiplexed as any two of the gate electrode of the second transistor T2, the gate electrode of the fourth transistor T4, and the first voltage terminal VDD; the light shielding layer 116 can be multiplexed as the gate electrode of the second transistor T2, the gate electrode of the fourth transistor T4, and the first voltage terminal VDD.
  • the gate of the four-transistor T4 and the first voltage terminal VDD are examples of the light-shielding layer 116.
  • the corresponding multiplexed part can be separated from other parts that cannot conduct the electrical signal of the multiplexed part through grooves, patterning, etc. according to the electrical connection relationship. This ensures the correctness of the electrical connections and the correctness of the electrical signals.
  • the material of the light-shielding layer 116 is metal.
  • the light-shielding layer 116 can have a double-layer metal structure to reduce resistance and improve impedance characteristics and electromagnetic compatibility characteristics.
  • the light-shielding layer 116 can also be a single-layer metal structure, a three-layer metal structure, or other applicable multi-layer metal structures, which can be determined according to actual needs, and the embodiments of the present disclosure are not limited to this.
  • 17A to 17F are plan layout views of various layer structures of an array substrate in a display panel according to some embodiments of the present disclosure. The process flow will be briefly described below with reference to Figures 17A to 17F.
  • the light-shielding layer 116 adopts a double-layer copper (Cu) structure, for example, and may also adopt molybdenum (Mo) and titanium/copper (Ti/Cu).
  • the thickness of the light shielding layer 116 is The light-shielding layer 116 is used to implement functions such as light-shielding and source-drain signal input.
  • the data line Vdata and the first voltage terminal VDD are both formed in the light-shielding layer 116, so the traditional SD film layer can be omitted, thereby reducing the number of film layers and processes.
  • a masking process for the active layer ACT is then performed. For example, using IGZO as the active layer ACT, its thickness is It should be noted that the active layers of all transistors are formed in this process, including the active layer 1141 of the first transistor T1 and the active layers of other transistors.
  • the gate metal layer GM is prepared. After the gate metal layer GM is formed, it can be connected to the light-shielding layer 116 through corresponding via holes. The data signal and the first voltage are transmitted from the corresponding multiplexing part in the light-shielding layer 116 to the corresponding part in the gate metal layer GM. After the gate metal layer GM is etched, the gate insulating layer 113 is etched and the corresponding portion of the active layer ACT is conductive. For example, the third transistor T3, the fourth transistor T4, the first scan line S1, and the second scan line S2 are located at the one on the same side of transistor T1.
  • the passivation layer 118 and the planarization layer 119 are prepared.
  • the passivation layer 118 and the planarization layer 119 can share a mask process and form a via hole Hc to facilitate the transmission of corresponding signals to the anode of the subsequently formed OLED.
  • the OLED anode (the first end L01 of the light-emitting element L) is prepared.
  • ITO indium tin oxide
  • film layers such as the buffer layer 112 is omitted.
  • it may also include processes for pixel units (R, G, B), pixel definition layer PDL and other film layers.
  • the array substrate requires a total of 10 masks.
  • At least one embodiment of the present disclosure also provides a semiconductor display device.
  • the semiconductor display device includes the semiconductor substrate (ie, display panel) provided by any embodiment of the present disclosure.
  • the semiconductor display device can reduce the probability of damage to an organic light-emitting diode (OLED) device, protect the OLED device, and extend the service life of the OLED device.
  • OLED organic light-emitting diode
  • FIG. 19 is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • the display device 30 includes a display panel 31 , and the display panel 31 is, for example, the display panel provided by any embodiment of the present disclosure, such as the display panel 100 described above.
  • the display device 30 may be an OLED display panel, an OLED TV, an OLED display, etc., or may be other applicable products or components with display functions, which are not limited in the embodiments of the present disclosure.
  • the display device 30 may be an OLED display panel, an OLED TV, an OLED display, etc., or may be other applicable products or components with display functions, which are not limited in the embodiments of the present disclosure.
  • FIG. 20 is a schematic block diagram of another display device provided by some embodiments of the present disclosure.
  • the display device 40 includes a display panel 4000, a gate driver 4010, a timing controller 4020, and a data driver 4030.
  • the display panel 4000 includes a plurality of pixel units P defined crosswise according to a plurality of scan lines GL and a plurality of data lines DL.
  • the display panel 4000 is, for example, a display panel provided by any embodiment of the present disclosure, such as the display panel 100 described above.
  • the plurality of scan lines GL include the aforementioned first scan line S1 and the second scan line S2, and the plurality of data lines DL include the aforementioned data line Vdata.
  • the gate driver 4010 is used to drive a plurality of scan lines GL; the data driver 4030 is used to drive a plurality of data lines DL; the timing controller 4020 is used to process the image data RGB input from outside the display device 40, and provide the processed data to the data driver 4030.
  • the image data RGB and the scan control signal GCS and the data control signal DCS are output to the gate driver 4010 and the data driver 4030 to control the gate driver 4010 and the data driver 4030 .
  • the gate driver 4010 can be implemented as a semiconductor chip, or can be integrated in the display panel 4000 to form a GOA circuit.
  • the data driver 4030 converts the digital image data RGB input from the timing controller 4020 into a data signal according to the plurality of data control signals DCS originating from the timing controller 4020 using the reference gamma voltage.
  • the data driver 4030 provides converted data signals to the plurality of data lines DL.
  • the data driver 4030 may be implemented as a semiconductor chip.
  • the timing controller 4020 processes the externally input image data RGB to match the size and resolution of the display panel 4000, and then provides the processed image data to the data driver 4030.
  • the timing controller 4020 uses synchronization signals (such as dot clock DCLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) input from outside the display device 40 to generate a plurality of scan control signals GCS and a plurality of data control signals DCS. .
  • the timing controller 4020 provides the generated scan control signal GCS and data control signal DCS to the gate driver 4010 and the data driver 4030 respectively for control of the gate driver 4010 and the data driver 4030.
  • the display device 40 may also include other components, such as a signal decoding circuit, a voltage conversion circuit, etc. These components may be, for example, existing conventional components, which will not be described in detail here.
  • the display panel 4000 can be applied to any product or component with a display function such as e-books, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, and navigators.
  • a display function such as e-books, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, and navigators.
  • At least one embodiment of the present disclosure also provides a driving method for driving the semiconductor substrate (ie, display panel) provided by any embodiment of the present disclosure.
  • This driving method can reduce the probability of damage to the organic light-emitting diode (OLED) device, protect the OLED device, and extend the service life of the OLED device.
  • OLED organic light-emitting diode
  • FIG. 21 is a schematic flowchart of a driving method for a display panel provided by some embodiments of the present disclosure. As shown in Figure 21, in some embodiments, the driving method includes the following operations.
  • Step S51 In the display stage, the driving circuit and the protection circuit jointly provide driving current to drive the light-emitting element to emit light;
  • Step S52 In the sensing stage, the sensing circuit is turned on to connect the second end of the driving circuit to the sensing signal line, and a protection circuit is used to prevent static electricity generated by the sensing circuit from flowing to the light-emitting element.

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Abstract

一种半导体基板、驱动方法、半导体显示装置（30，40）。半导体基板包括阵列基板(101)，阵列基板(101)包括像素单元(P)，每个像素单元(P)包括像素电路(20)和发光元件(L)。像素电路(20)包括驱动电路(21)、数据写入电路(22)、存储电路(23)、感测电路(24)和保护电路(25)。驱动电路(21)控制驱动发光元件(L)发光的驱动电流。数据写入电路(22)将数据信号写入驱动电路(21)。存储电路(23)存储数据信号。感测电路(24)配置为将驱动电路(21)的第二端(212)与感测信号线(Sen)连接。保护电路(25)的第一端(251)与驱动电路(21)的第一端(211)连接，保护电路(25)的控制端(253)和第二端(252)均与驱动电路(21)的第二端(212)连接。发光元件(L)配置为根据驱动电流发光。半导体基板可以降低有机发光二极管器件损伤几率。

Description

半导体基板及其驱动方法、半导体显示装置
本申请要求于2022年7月13日递交的中国专利申请第202210817753.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种半导体基板及其驱动方法、半导体显示装置。
背景技术
在半导体技术领域，半导体材料常被制作在基板上以构成半导体基板，半导体基板可以是显示面板或发光面板等。在半导体基板上，设置有半导体晶体管，半导体晶体管采用半导体材料制作且可以具有开启和截止两种状态，并且，在开启状态下还可以具有不同的开启程度。半导体基板常作为显示面板应用到显示装置中。
有机发光二极管(Organic Light-Emitting Diode，OLED)显示装置由于具有视角宽、对比度高、响应速度快以及相比于无机发光显示器件更高的发光亮度、更低的驱动电压等优势而逐渐受到人们的广泛关注。由于上述特点，有机发光二极管(OLED)可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
OLED显示装置中的像素电路一般采用矩阵驱动方式，根据每个像素单元中是否引入开关元器件分为有源矩阵(Active Matrix，AM)驱动和无源矩阵(Passive Matrix，PM)驱动。例如，开关元器件可以为半导体晶体管(例如薄膜晶体管等)。
PMOLED虽然工艺简单、成本较低，但因存在交叉串扰、高功耗、低寿命等缺点，不能满足高分辨率大尺寸显示的需求。相比之下，AMOLED在每一个像素的像素电路中都集成了一组薄膜晶体管和存储电容，通过对薄膜晶体管和存储电容的驱动控制，实现对流过OLED的电流的控制，从而使OLED根据需要发光。相比PMOLED，AMOLED所需驱动电流小、功耗低、寿命更长，可以满足高分辨率多灰度的大尺寸显示需求。同时，AMOLED在可视 角度、色彩的还原、功耗以及响应时间等方面具有明显的优势，适用于高信息含量、高分辨率的显示装置。
发明内容
本公开至少一个实施例提供一种半导体基板，包括阵列基板，其中，所述阵列基板包括多个阵列排布的像素单元，每个像素单元包括像素电路和发光元件；所述像素电路包括驱动电路、数据写入电路、存储电路、感测电路和保护电路；所述驱动电路包括控制端、第一端和第二端，且配置为控制驱动所述发光元件发光的驱动电流，所述驱动电路的第一端接收第一电压端的第一电压；所述数据写入电路与所述驱动电路的控制端连接，且配置为响应于第一扫描信号将数据信号写入所述驱动电路的控制端；所述存储电路的第一端与所述驱动电路的控制端连接，所述存储电路的第二端与所述驱动电路的第二端连接，所述存储电路配置为存储所述数据写入电路写入的所述数据信号；所述感测电路与所述驱动电路的第二端连接，且配置为响应于第二扫描信号将所述驱动电路的第二端与感测信号线连接；所述保护电路包括控制端、第一端和第二端，所述保护电路的第一端与所述驱动电路的第一端连接，所述保护电路的控制端和所述保护电路的第二端均与所述驱动电路的第二端连接，所述保护电路配置为阻止所述感测电路产生的静电流动至所述发光元件，并且与所述驱动电路共同提供所述驱动电流；所述发光元件的第一端与所述驱动电路的第二端连接，所述发光元件的第二端接收第二电压端的第二电压，所述发光元件配置为根据所述驱动电流发光。
例如，在本公开一实施例提供的半导体基板中，所述驱动电路包括第一晶体管；所述第一晶体管的栅极作为所述驱动电路的控制端，所述第一晶体管的第一极作为所述驱动电路的第一端，所述第一晶体管的第二极作为所述驱动电路的第二端。
例如，在本公开一实施例提供的半导体基板中，所述保护电路包括第二晶体管；所述第二晶体管的栅极作为所述保护电路的控制端，所述第二晶体管的第一极作为所述保护电路的第一端，所述第二晶体管的第二极作为所述保护电路的第二端；所述第二晶体管的第一极与所述第一晶体管的第一极连接；所述第二晶体管的栅极与所述第二晶体管的第二极连接，且连接至所述第一晶体管的第二极。
例如，在本公开一实施例提供的半导体基板中，所述第二晶体管构成二极管连接方式。
例如，在本公开一实施例提供的半导体基板中，所述第一晶体管与所述第二晶体管均为N型薄膜晶体管或者均为P型薄膜晶体管。
例如，在本公开一实施例提供的半导体基板中，所述数据写入电路包括第三晶体管；所述第三晶体管的栅极与第一扫描线连接以接收所述第一扫描信号，所述第三晶体管的第一极与数据线连接以接收所述数据信号，所述第三晶体管的第二极与所述驱动电路的控制端连接。
例如，在本公开一实施例提供的半导体基板中，所述感测电路包括第四晶体管；所述第四晶体管的栅极与第二扫描线连接以接收所述第二扫描信号，所述第四晶体管的第一极与所述驱动电路的第二端连接，所述第四晶体管的第二极与所述感测信号线连接。
例如，在本公开一实施例提供的半导体基板中，所述存储电路包括存储电容；所述存储电容的第一极作为所述存储电路的第一端，所述存储电容的第二极作为所述存储电路的第二端。
例如，在本公开一实施例提供的半导体基板中，所述发光元件包括有机发光二极管，所述有机发光二极管的阳极作为所述发光元件的第一端，所述有机发光二极管的阴极作为所述发光元件的第二端。
例如，本公开一实施例提供的半导体基板还包括复位电路，其中，所述复位电路与所述驱动电路的控制端连接，且配置为响应于复位信号将复位电压施加至所述驱动电路的控制端。
例如，在本公开一实施例提供的半导体基板中，所述复位电路包括第五晶体管；所述第五晶体管的栅极与复位信号线连接以接收所述复位信号，所述第五晶体管的第一极与所述驱动电路的控制端连接，所述第五晶体管的第二极与复位电压端连接以接收所述复位电压。
例如，在本公开一实施例提供的半导体基板中，所述复位电压端与所述第二电压端为同一个电压端，所述复位电压与所述第二电压为同一个电压信号。
例如，在本公开一实施例提供的半导体基板中，所述第一晶体管的沟道宽长比的范围是12.6:6至16.2:6。
例如，在本公开一实施例提供的半导体基板中，所述阵列基板包括衬底 基板、缓冲层、栅绝缘层；所述第一晶体管包括有源层；所述缓冲层设置在所述衬底基板上，所述有源层设置在所述缓冲层上，所述栅绝缘层设置在所述缓冲层上且覆盖所述有源层，所述第一晶体管的栅极设置在所述栅绝缘层上。
例如，在本公开一实施例提供的半导体基板中，所述阵列基板还包括层间绝缘层；所述层间绝缘层设置在所述栅绝缘层上且覆盖所述第一晶体管的栅极，所述第一晶体管的第一极和所述第一晶体管的第二极设置在所述层间绝缘层上。
例如，在本公开一实施例提供的半导体基板中，所述第一晶体管的第一极和所述第一晶体管的第二极设置在所述栅绝缘层上，所述第一晶体管的第一极、所述第一晶体管的第二极、所述第一晶体管的栅极位于同一层。
例如，在本公开一实施例提供的半导体基板中，所述第一晶体管的第一极通过至少贯穿所述栅绝缘层的第一过孔与所述有源层连接，所述第一晶体管的第二极通过至少贯穿所述栅绝缘层的第二过孔与所述有源层连接。
例如，在本公开一实施例提供的半导体基板中，所述有源层包括至少一个开槽区，所述开槽区是在垂直于所述衬底基板的方向上贯通所述有源层的孔。
例如，在本公开一实施例提供的半导体基板中，所述至少一个开槽区包括第一开槽区和第二开槽区，所述第一开槽区与所述第一过孔相邻，所述第二开槽区与所述第二过孔相邻。
例如，在本公开一实施例提供的半导体基板中，所述第一过孔暴露所述有源层的一部分，并且通过所述第一开槽区暴露所述缓冲层的一部分；和/或所述第二过孔暴露所述有源层的一部分，并且通过所述第二开槽区暴露所述缓冲层的一部分。
例如，在本公开一实施例提供的半导体基板中，所述第一开槽区和所述第二开槽区的形状均为矩形。
例如，在本公开一实施例提供的半导体基板中，所述第一开槽区的尺寸与所述第二开槽区的尺寸相同。
例如，在本公开一实施例提供的半导体基板中，所述至少一个开槽区为一个开槽区，所述第一晶体管的第一极和所述第一晶体管的第二极中的一个为所述第一晶体管的源极，所述第一过孔和所述第二过孔中与所述第一晶体 管的源极相邻的过孔为目标过孔，所述开槽区与所述目标过孔相邻。
例如，在本公开一实施例提供的半导体基板中，所述目标过孔暴露所述有源层的一部分，并且通过所述开槽区暴露所述缓冲层的一部分。
例如，在本公开一实施例提供的半导体基板中，所述开槽区的形状为矩形。
例如，在本公开一实施例提供的半导体基板中，所述有源层的参照宽度为Wd，所述开槽区的宽度为Wvia，所述有源层在所述开槽区的位置上的有效宽度为W1，所述有源层在未开槽的部位的有效宽度为W2，W2＝Wd，W1＝Wd-Wvia；所述有源层的参照长度为Ld，所述开槽区的长度为L1，所述有源层在未开槽的部位的有效长度为L2，Ld＝L1+L2。
例如，在本公开一实施例提供的半导体基板中，所述第一晶体管的预设沟道电流表示为I1，所述第一晶体管的挖槽沟道电流表示为I2，
例如，在本公开一实施例提供的半导体基板中，I2/I1的数值范围为1～1.5。
例如，在本公开一实施例提供的半导体基板中，所述阵列基板还包括遮光层，所述遮光层设置在所述衬底基板上，所述缓冲层设置在所述衬底基板上且覆盖所述遮光层，所述遮光层的材料为金属，所述遮光层的至少部分复用为所述第二晶体管的栅极。
例如，在本公开一实施例提供的半导体基板中，所述第一晶体管的第一极复用为所述第二晶体管的第一极，所述第一晶体管的第二极复用为所述第二晶体管的第二极；所述第二晶体管的第二极通过至少贯穿所述缓冲层、所述栅绝缘层的第三过孔与所述遮光层连接。
例如，在本公开一实施例提供的半导体基板中，所述第二晶体管的沟道宽度为W3，所述第二晶体管的沟道长度为L3，所述缓冲层的厚度为dbuf，所述栅绝缘层的厚度为dgi；所述第二晶体管的沟道电流为Ie，所述第一晶体管的初始沟道电流为Id，所述第一晶体管的初始沟道电流Id等于所述第一晶体管的挖槽沟道电流I2；
例如，在本公开一实施例提供的半导体基板中，Id/Ie的数值范围为0.5～1。
例如，在本公开一实施例提供的半导体基板中，所述第三过孔具有彼此相对的第一侧壁和第二侧壁，所述第一侧壁靠近所述有源层，所述第二侧壁远离所述有源层，所述第一侧壁的坡度与所述第二侧壁的坡度不同。
例如，在本公开一实施例提供的半导体基板中，所述第一侧壁的坡度大于所述第二侧壁的坡度。
例如，在本公开一实施例提供的半导体基板中，所述阵列基板还包括栅金属层和钝化层；所述栅金属层设置在所述栅绝缘层上，所述第一晶体管的栅极、所述第一晶体管的第一极、所述第一晶体管的第二极均位于所述栅金属层，所述钝化层设置在所述栅金属层上；所述发光元件的第一端为阳极，所述阳极通过贯穿所述钝化层的第四过孔与位于所述栅金属层的转接部连接，所述转接部通过所述第三过孔与所述遮光层和所述第一晶体管的第二极连接。
例如，在本公开一实施例提供的半导体基板中，所述第四过孔与所述第三过孔彼此靠近的边缘之间的距离为das，所述第三过孔在所述栅金属层所在平面的孔径为ds，
例如，在本公开一实施例提供的半导体基板中，das＝ds。
例如，在本公开一实施例提供的半导体基板中，所述第一晶体管的第二极的远离所述第三过孔的边缘与所述第一晶体管的第二极的靠近所述第三过孔的边缘之间的距离为dgs，所述第三过孔在所述栅金属层所在平面的孔径为ds，
例如，在本公开一实施例提供的半导体基板中，dgs＝ds。
例如，在本公开一实施例提供的半导体基板中，所述阵列基板还包括数据线，所述数据线用于传输所述数据信号，所述数据线设置在所述层间绝缘层上，所述数据线与所述第一晶体管的第一极和所述第一晶体管的第二极位于同一层。
例如，在本公开一实施例提供的半导体基板中，所述阵列基板还包括数据线，所述数据线用于传输所述数据信号，所述数据线设置在所述栅绝缘层上，所述数据线与所述第一晶体管的栅极、所述第一晶体管的第一极、所述第一晶体管的第二极位于同一层。
例如，在本公开一实施例提供的半导体基板中，所述第三晶体管、所述第四晶体管、所述第一扫描线、所述第二扫描线位于所述第一晶体管的同一侧。
例如，在本公开一实施例提供的半导体基板中，所述有源层中被所述第 一过孔和/或所述第二过孔暴露的部分为通过等离子体掺杂形成的导体化区域。
例如，在本公开一实施例提供的半导体基板中，所述第一晶体管的第一极和所述第一晶体管的第二极中的一个为所述第一晶体管的漏极，所述第一过孔和所述第二过孔中与所述第一晶体管的漏极相邻的过孔与所述第三过孔为同一个过孔，所述第一晶体管的漏极通过所述第三过孔与所述有源层暴露的部分、所述遮光层暴露的部分均连接。
例如，在本公开一实施例提供的半导体基板中，所述阵列基板还包括钝化层和平坦化层；所述第一晶体管的第一极和所述第一晶体管的第二极中的一个为所述第一晶体管的漏极；所述钝化层和所述平坦化层依序层叠设置，并且位于所述第一晶体管的漏极之上；所述钝化层和所述平坦化层中具有第五过孔，所述第五过孔暴露所述第一晶体管的漏极。
例如，在本公开一实施例提供的半导体基板中，所述第五过孔包括位于所述钝化层与所述平坦化层的交界面的台阶，所述台阶的宽度小于或等于1μm。
例如，在本公开一实施例提供的半导体基板中，所述阵列基板还包括遮光层，所述遮光层设置在所述衬底基板上，所述缓冲层设置在所述衬底基板上且覆盖所述遮光层，所述遮光层的材料为金属，所述遮光层复用为所述第二晶体管的栅极；所述第五过孔在垂直于所述衬底基板的方向上的正投影与所述遮光层中复用为所述第二晶体管的栅极的部分在垂直于所述衬底基板的方向上的正投影至少部分交叠。
例如，在本公开一实施例提供的半导体基板中，所述感测电路包括第四晶体管，所述第四晶体管的栅极与第二扫描线连接以接收所述第二扫描信号，所述第四晶体管的第一极与所述驱动电路的第二端连接，所述第四晶体管的第二极与所述感测信号线连接；所述遮光层还复用为所述第四晶体管的栅极，并且复用为所述第一电压端；所述遮光层为双层金属结构。
本公开至少一个实施例还提供一种半导体显示装置，包括本公开任一实施例所述的半导体基板。
本公开至少一个实施例还提供一种用于本公开任一实施例所述的半导体基板的驱动方法，包括：在显示阶段，使所述驱动电路和所述保护电路共同提供所述驱动电流，以驱动所述发光元件发光；在感测阶段，使所述感测电 路开启以将所述驱动电路的第二端与所述感测信号线连接，并且利用所述保护电路阻止所述感测电路产生的静电流动至所述发光元件。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一些实施例提供的一种显示面板的示意图；
图2为本公开一些实施例提供的一种显示面板中像素电路的示意框图；
图3为图2中所示的像素电路的一种具体实现示例的电路图；
图4为图3中所示的电路结构的时序图；
图5A为本公开一些实施例提供的另一种显示面板中像素电路的示意框图；
图5B为图5A中所示的像素电路的一种具体实现示例的电路图；
图6A为本公开一些实施例提供的一种显示面板中阵列基板的剖面示意图；
图6B为本公开一些实施例提供的另一种显示面板中阵列基板的剖面示意图；
图7为本公开一些实施例提供的另一种显示面板中阵列基板的剖面示意图；
图8为本公开一些实施例提供的一种显示面板中有源层的平面示意图；
图9A为图8中A-A’线的剖面示意图；
图9B为图8中B-B’线的剖面示意图；
图10为图8所示的有源层的各个尺寸的标注示意图；
图11为本公开一些实施例提供的另一种显示面板中有源层的平面示意图；
图12A为图11中C-C’线的剖面示意图；
图12B为图11中D-D’线的剖面示意图；
图13A至图13C为本公开一些实施例提供的一种显示面板中阵列基板的刻蚀工艺示意图；
图14为本公开一些实施例提供的一种显示面板中阵列基板的剖面示意 图；
图15为本公开一些实施例提供的另一种显示面板中阵列基板的剖面示意图；
图16为本公开一些实施例提供的另一种显示面板中阵列基板的剖面示意图；
图17A至图17F为本公开一些实施例提供的一种显示面板中阵列基板的各个层结构的平面布局图；
图18为本公开一些实施例提供的一种显示面板中阵列基板的剖面示意图；
图19为本公开一些实施例提供的一种显示装置的示意框图；
图20为本公开一些实施例提供的另一种显示装置的示意框图；
图21为本公开一些实施例提供的一种用于显示面板的驱动方法的流程示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
像素电路中的晶体管为半导体晶体管，采用半导体材料(例如掺杂多晶 硅等)制作。在将半导体基板作为显示面板的情形中，由于半导体工艺水平的限制，像素电路中的晶体管的工艺稳定性成为影响显示画面的主要因素，多个像素之间的驱动晶体管的阈值电压和迁移率存在差异，导致供给各个像素的电流不同，从而使各个像素的实际亮度与期望的理想亮度相比出现偏差，显示屏的亮度均一性会下降，甚至产生区域的斑点或图案。并且，电压源的压降(IR Drop)及OLED老化等因素也会影响显示屏的亮度均一性。因此，需要通过补偿技术来使像素的亮度达到理想值。
例如，可以采用外部补偿的方式，也即是，将驱动晶体管的电流引出，并利用像素电路外部的电路来检测该电流，从而计算出偏差以及需要补偿的数值，由此实现对驱动晶体管的补偿。例如可以采用感测晶体管来将驱动晶体管的电流引出。然而，当感测晶体管打开时，容易产生静电，从而可能损伤OLED器件，对OLED器件的使用寿命产生影响。
本公开至少一个实施例提供一种半导体基板及其驱动方法、半导体显示装置。该半导体基板可以降低有机发光二极管(OLED)器件损伤的几率，对OLED器件起保护作用，可以延长OLED器件的使用寿命。
需要注意的是，在本公开的说明中，显示面板是半导体基板的一个具体示例，显示面板本质上是半导体基板，本文中描述的显示面板可以指代半导体基板。因此，虽然本文中描述了显示面板及其相关特征，但是应当视为对半导体基板及其相关特征的描述。相应地，包括该显示面板的显示装置也为半导体显示装置，本文中描述的显示装置可以指代半导体显示装置，因此，虽然本文中描述了显示装置及其相关特征，但是应当视为对半导体显示装置及其相关特征的描述。
下面，将参考附图详细地说明本公开的实施例。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
本公开至少一个实施例提供一种半导体基板，该半导体基板包括阵列基板。阵列基板包括多个阵列排布的像素单元，每个像素单元包括像素电路和发光元件。像素电路包括驱动电路、数据写入电路、存储电路、感测电路和保护电路。驱动电路包括控制端、第一端和第二端，且配置为控制驱动发光元件发光的驱动电流，驱动电路的第一端接收第一电压端的第一电压。数据写入电路与驱动电路的控制端连接，且配置为响应于第一扫描信号将数据信号写入驱动电路的控制端。存储电路的第一端与驱动电路的控制端连接，存 储电路的第二端与驱动电路的第二端连接，存储电路配置为存储数据写入电路写入的数据信号。感测电路与驱动电路的第二端连接，且配置为响应于第二扫描信号将驱动电路的第二端与感测信号线连接。保护电路包括控制端、第一端和第二端，保护电路的第一端与驱动电路的第一端连接，保护电路的控制端和保护电路的第二端均与驱动电路的第二端连接，保护电路配置为阻止感测电路产生的静电流动至发光元件，并且与驱动电路共同提供驱动电流。发光元件的第一端与驱动电路的第二端连接，发光元件的第二端接收第二电压端的第二电压，发光元件配置为根据驱动电流发光。
图1为本公开一些实施例提供的一种显示面板的示意图。如图1所示，在一些实施例中，显示面板100包括阵列基板101，阵列基板101包括多个阵列排布的像素单元P。显示面板100可以是OLED显示面板、量子点发光二极管(Quantum Dot Light-Emitting Diode，QLED)显示面板或其他适用的显示面板。每个像素单元包括像素电路20和发光元件L(图1中未示出)，每个像素单元与对应的第一扫描线S1、第二扫描线S2、数据线Vdata、感测信号线Sen连接。
图2为本公开一些实施例提供的一种显示面板中像素电路的示意框图。如图2所示，在一些实施例中，每个像素单元包括像素电路20和发光元件L。像素电路20包括驱动电路21、数据写入电路22、存储电路23、感测电路24和保护电路25。
驱动电路21包括第一端211、第二端212、控制端213，且配置为控制驱动发光元件L发光的驱动电流。驱动电路21的第一端211接收第一电压端VDD的第一电压。驱动电路21的控制端213和第一节点N1连接，驱动电路21的第一端211连接到第一电压端VDD(例如，高电平)以接收第一电压，驱动电路21的第二端212和第二节点N2连接。例如，驱动电路21在工作时可以向发光元件L提供驱动电流以驱动发光元件L进行发光，且使得发光元件L可以根据需要的“灰度”发光。例如，发光元件L可以采用OLED，且配置为其两端分别和第二节点N2以及第二电压端VSS(例如，接地)连接，本公开的实施例包括但不限于此情形。
数据写入电路22与驱动电路21的控制端213(第一节点N1)连接，且配置为响应于第一扫描信号将数据信号写入驱动电路21的控制端213。例如，数据写入电路22分别和数据线Vdata、第一节点N1以及第一扫描线S1连接。 例如，来自第一扫描线S1的第一扫描信号被施加至数据写入电路22以控制数据写入电路22开启与否。例如，在数据写入阶段，数据写入电路22可以响应于第一扫描信号而开启，从而可以将数据线Vdata提供的数据信号写入驱动电路21的控制端213(第一节点N1)，然后可将数据信号存储在存储电路23中，该存储的数据信号将用于生成驱动发光元件L发光的驱动电流。
存储电路23的第一端231与驱动电路21的控制端213(第一节点N1)连接，存储电路23的第二端232与驱动电路21的第二端212(第二节点N2)连接。存储电路23配置为存储数据写入电路22写入的数据信号。例如，存储电路23可以存储该数据信号并使得存储的数据信号对驱动电路21进行控制。
感测电路24与驱动电路21的第二端212(第二节点N2)连接，且配置为响应于第二扫描信号将驱动电路21的第二端212与感测信号线Sen连接。例如，感测电路24分别和第二节点N2、第二扫描线S2、感测信号线Sen连接。例如，来自第二扫描线S2的第二扫描信号被施加至感测电路24以控制感测电路24开启与否。
例如，感测信号线Sen可以提供第二电压(例如，接地电压)并可切换为浮置状态。例如，在感测阶段，当进行检测数据写入时，感测信号线Sen提供第二电压，以保证检测数据正确写入。然后感测信号线Sen切换为浮置状态，驱动电路21的第二端212与感测信号线Sen电连接，从而可以检测流过驱动电路21的电流。
例如，可通过另行设置的检测电路(例如，运算放大器、模数转换器等)将该电流转换为电压信号，再将其转换为数字信号并将所得到的信号存储起来，该信号可以进一步经过算法处理得到补偿数据，之后在该像素电路的正常发光阶段，将算法处理得到的补偿数据叠加到输入的显示数据上以得到补偿后的显示数据，该补偿后的显示数据可以通过数据写入电路22写入以控制驱动电路21，从而可以补偿驱动电路21中的晶体管的阈值电压和迁移率等差异造成的显示亮度均一性的差异。
例如，发光元件L的第一端L01与驱动电路21的第二端212(第二节点N2)连接以接收驱动电流，发光元件L的第二端L02接收第二电压端VSS的第二电压，发光元件L配置为根据驱动电流发光。
保护电路25包括第一端251、第二端252、控制端253，保护电路25的 第一端251与驱动电路21的第一端211连接，保护电路25的控制端253和保护电路25的第二端252均与驱动电路21的第二端212(第二节点N2)连接。保护电路25配置为阻止感测电路24产生的静电流动至发光元件L，并且与驱动电路21共同提供驱动电流。
在本公开的实施例中，由于感测电路24开启时容易产生静电，该静电可能损伤发光元件L，因此通过设置保护电路25，可以起保护作用，能够阻止感测电路24产生的静电流动至发光元件L，防止该静电损伤发光元件L，从而降低发光元件L的损伤几率。此外，在发光元件L发光期间，保护电路25具有正反馈作用，可以与驱动电路21一起提供驱动电流。
图3为图2中所示的像素电路的一种具体实现示例的电路图。如图3所示，像素电路20包括第一至第四晶体管T1、T2、T3、T4以及包括存储电容C1，像素电路20与发光元件L连接。例如，第一晶体管T1被用作驱动晶体管，其他的晶体管被用作开关晶体管。例如，发光元件L可以为各种类型的OLED，例如顶发射、底发射、双侧发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
例如，如图3所示，驱动电路21可以实现为第一晶体管T1。第一晶体管T1的栅极作为驱动电路21的控制端213和第一节点N1连接，第一晶体管T1的第一极作为驱动电路21的第一端211和第一电压端VDD连接，第一晶体管T1的第二极作为驱动电路21的第二端212和第二节点N2连接。需要注意的是，本公开的实施例不限于此，驱动电路21也可以是由其他的组件组成的电路，例如，驱动电路21可以具有两组驱动晶体管，例如，该两组驱动晶体管可以根据具体情况进行切换。
保护电路25可以实现为第二晶体管T2。第二晶体管T2的栅极作为保护电路25的控制端253，第二晶体管T2的第一极作为保护电路25的第一端251，第二晶体管T2的第二极作为保护电路25的第二端252。第二晶体管T2的第一极与第一晶体管T1的第一极连接；第二晶体管T2的栅极与第二晶体管T2的第二极连接，且连接至第一晶体管T1的第二极。例如，第二晶体管T2构成二极管连接方式(diode connected)，将第二晶体管T2并联至第一晶体管T1，可以有效防止感测电路24产生的静电流动至发光元件L，防止该静电损伤发光元件L，对发光元件L起保护作用，从而可以降低发光元件L损伤的几率，延长其使用寿命。例如，第一晶体管T1与第二晶体管T2均为N型薄 膜晶体管，或者，第一晶体管T1与第二晶体管T2均为P型薄膜晶体管，也即是，两者可以为相同类型的晶体管。
数据写入电路22可以实现为第三晶体管T3。第三晶体管T3的栅极与第一扫描线S1连接以接收第一扫描信号，第三晶体管T3的第一极与数据线Vdata连接以接收数据信号。第三晶体管T3的第二极与驱动电路21的控制端213(第一节点N1)连接，也即与第一晶体管T1的栅极连接。需要注意的是，本公开的实施例不限于此，数据写入电路22也可以是由其他的组件组成的电路。
感测电路24可以实现为第四晶体管T4。第四晶体管T4的栅极与第二扫描线S2连接以接收第二扫描信号，第四晶体管T4的第一极与驱动电路21的第二端212(第二节点N2)连接，第四晶体管T4的第二极与感测信号线Sen连接。需要注意的是，本公开的实施例不限于此，感测电路24也可以是由其他的组件组成的电路。
存储电路23可以实现为存储电容C1。存储电容C1的第一极作为存储电路23的第一端231和第一节点N1连接，存储电容C1的第二极作为存储电路23的第二端232和第二节点N2连接。需要注意的是，本公开的实施例不限于此，存储电路23也可以是由其他的组件组成的电路，例如，存储电路23可以包括两个彼此并联/串联的电容。
发光元件L可以实现为有机发光二极管(OLED)，有机发光二极管的阳极作为发光元件L的第一端L01和第二节点N2连接且配置为从驱动电路21的第二端212接收驱动电流，有机发光二极管的阴极作为发光元件L的第二端L02和第二电压端VSS连接以接收第二电压。例如，在一个显示面板中，当像素电路20呈阵列排布时，各个像素单元的像素电路20中的发光元件L的阴极可以电连接到同一个电压端，即该显示面板采用共阴极连接方式。
例如，在对该像素电路20进行版图设计时，可以使第三晶体管T3、第四晶体管T4、第一扫描线S1、第二扫描线S2位于第一晶体管T1的同一侧，从而便于布线，有利于增大开口率。
需要说明的是，出于描述的目的，本公开的各实施例中的第一电压端VDD例如保持输入直流高电平信号，将该直流高电平称为第一电压；第二电压端VSS例如保持输入直流低电平信号，将该直流低电平称为第二电压(可为接地电压)，且低于第一电压。以下各实施例与此相同，不再赘述。
图4为图3中所示的电路结构的时序图。下面结合图4所示的信号时序图，对图3所示的像素电路20进行感测的工作原理进行简要说明，并且这里以各个晶体管为N型晶体管为例进行说明，但是本公开的实施例不限于此。
在感测操作中，向驱动电路21写入数据并采用感测电路24将驱动电路21的第二端212与感测信号线Sen电连接。如图4所示，感测阶段包括二个阶段，分别为检测数据写入阶段P1和电学检测阶段P2，图4中示出了每个阶段中各个信号的时序波形。
在检测数据写入阶段P1，输入第一扫描信号(第一扫描线S1提供)和检测数据信号(数据线Vdata提供)以开启数据写入电路22和驱动电路21，数据写入电路22将检测数据信号写入驱动电路21，存储电路23存储检测数据信号，感测信号线Sen提供第二电压。此时，第三晶体管T3被第一扫描信号的高电平导通，第一晶体管T1被第一节点N1的高电平导通，第四晶体管T4被第二扫描信号的高电平导通。由此，形成一条数据写入路径，检测数据信号经过第三晶体管T3后对存储电容C1进行充电。此时感测信号线Sen提供第二电压，即第二节点N2的电平为第二电压。经过检测数据写入阶段P1后，带有检测数据信号的电压信息储存在了存储电容C1中，以便于在下一个阶段使用。在其他示例中，当第二扫描信号为低电平时，第四晶体管T4截止，此时无需对感测信号线Sen提供第二电压。
在电学检测阶段P2，输入第二扫描信号(由第二扫描线S2提供)以开启感测电路24，感测电路24将驱动电路21的第二端212与感测信号线Sen电连接，感测信号线Sen为浮置状态。此时，第三晶体管T3被第一扫描信号的高电平导通，第一晶体管T1被第一节点N1的高电平导通，第四晶体管T4被第二扫描信号的高电平导通。由此，形成一条电流传输路径，流经第一晶体管T1的电流经过第四晶体管T4传输到感测信号线Sen，并经后续检测电路处理。此时，感测信号线Sen为浮置状态。由于感测信号线Sen的电阻远小于发光元件L的电阻，此时发光元件L中无电流或基本上无电流，发光元件L不发光。
经过电学检测阶段P2后，通过后续检测电路(例如，运算放大器、模数转换器等)的处理，流经第一晶体管T1的电流被转换为电压信号，再将其转换为数字信号并将所得到的信号存储起来，该信号进一步经过算法处理得到补偿数据，之后在该像素电路20的正常发光阶段，将算法处理得到的补偿数 据叠加到输入的显示数据上以得到补偿后的显示数据，该补偿后的显示数据可以通过数据写入电路22写入以控制驱动电路21，从而可以补偿驱动电路21中的晶体管(第一晶体管T1)的阈值电压和迁移率等差异造成的显示亮度均一性的差异。后续检测电路不包括在像素电路20中，并且可以采用常规的电路结构实现，因此不再详述。
需要注意的是，检测数据写入阶段P1和电学检测阶段P2之间有间隔时间Pt，间隔时间Pt的具体大小不受限制。例如，当间隔时间Pt＝0时，检测数据写入阶段P1和电学检测阶段P2的时序连接在一起。
需要说明的是，在该示例中，第一扫描信号(由第一扫描线S1提供)和第二扫描信号(由第二扫描线S2提供)为相同的信号(如图4所示)，但是本公开的实施例不限于此，第一扫描信号和第二扫描信号也可以为不同的信号，其波形可以彼此不同，这可以根据实际需求而定。
在第一扫描信号和第二扫描信号为同一个信号的情况下，在电学检测阶段P2中，仍然要保持有效的检测数据信号，以防止存储电容C1漏电而影响第一晶体管T1的开启/截止程度，进而避免影响检测数据的准确性。在第一扫描信号和第二扫描信号为不同信号的情况下，在电学检测阶段P2中，若第一扫描信号未开启，则可以无需保持有效的检测数据信号，此时存储电容C1不会通过第三晶体管T3漏电，因此不会影响第一晶体管T1的开启/截止程度，不会影响检测数据的准确性。
图5A为本公开一些实施例提供的另一种显示面板中像素电路的示意框图。在一些实施例中，如图5A所示，像素电路20还可以包括复位电路26，其他结构与图2中所示的像素电路20基本上相同。复位电路26与驱动电路21的控制端213(第一节点N1)连接，配置为响应于复位信号将复位电压施加至驱动电路21的控制端213以及存储电路23的第一端231，从而使得第一节点N1以及与之电连接的各个部件被复位。
例如，复位电路26分别和第一节点N1、复位电压端Vr、复位信号线Rst连接。例如，复位电路26可以响应于复位信号线Rst提供的复位信号而开启，从而可以将复位电压端Vr提供的复位电压施加至第一节点N1、存储电路23的第一端231以及驱动电路21的控制端213，从而可以对存储电路23和驱动电路21进行复位操作，消除之前的发光阶段的影响。复位电压可以由独立的复位电压端Vr提供，复位电压端Vr不同于第二电压端VSS。
例如，在另一些示例中，复位电压端Vr与第二电压端VSS为同一个电压端，复位电压与第二电压为同一个电压信号。也即是，复位电压可以由第二电压端VSS提供(此时第二电压端VSS复用为复位电压端Vr，第二电压复用为复位电压)，由此相应地，复位电路26连接到第二电压端VSS，本公开的实施例对此不作限制。例如，第二电压端VSS为低电压端(其电压低于第一电压端VDD的电压)，例如为接地端。
图5B为图5A中所示的像素电路的一种具体实现示例的电路图。图5B所示的像素电路20与图3所示的像素电路20基本上相同，区别在于图5B所示的像素电路20还包括第五晶体管T5以实现复位电路26。
例如，如图5B所示，更详细地，复位电路26可以实现为第五晶体管T5。第五晶体管T5的栅极与复位信号线Rst连接以接收复位信号，第五晶体管T5的第一极与复位电压端Vr连接以接收复位电压，第五晶体管T5的第二极与驱动电路21的控制端213(第一节点N1)连接，也即与第一晶体管T1的栅极连接。需要注意的是，本公开的实施例不限于此，复位电路26也可以是由其他的组件组成的电路。
需要说明的是，在本公开的各个实施例的描述中，符号Vdata既可以表示数据线又可以表示数据信号的电平。同样地，符号Rst既可以表示复位信号线又可以表示复位信号的电平，符号VDD既可以表示第一电压端又可以表示第一电压，符号VSS既可以表示第二电压端又可以表示第二电压，符号S1既可以表示第一扫描线又可以表示第一扫描信号的电平，符号S2既可以表示第二扫描线又可以表示第二扫描信号的电平，符号Vr既可以表示复位电压端又可以表示复位电压，符号Sen既可以表示感测信号线又可以表示感测信号线上传输的信号的电平。以下各实施例与此相同，不再赘述。
在本公开的说明中，第一节点N1和第二节点N2并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点。
需要说明的是，本公开各个实施例提供的像素电路20还可以包括其他具有内部补偿功能的电路结构。内部补偿功能可以通过电压补偿、电流补偿或混合补偿来实现，具有内部补偿功能的像素电路20例如可以为4T1C或4T2C等电路与感测电路24的结合。例如，在具有内部补偿功能的像素电路20中，数据写入电路22和内部补偿电路配合将携带有数据信号以及驱动电路21中的驱动晶体管(第一晶体管T1)的阈值电压信息的电压值写入到驱动电路21 的控制端213且通过存储电路23存储。对于具体的内部补偿电路的示例，这里不再详述。例如，像素电路20还可以包括发光控制电路等，以实现更全面的功能。
需要说明的是，本公开的各个实施例中采用的晶体管均可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的各个实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的各个实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，需要说明的是，图3和图5B中所示的像素电路20中的晶体管均是以N型晶体管为例进行说明的，此时，第一极可以是源极，第二极可以是漏极。像素电路20中的晶体管也可以仅采用P型晶体管或混合采用P型晶体管和N型晶体管，只需同时将选定类型的晶体管的端口极性按照本公开的实施例中的相应晶体管的端口极性相应连接即可。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
需要说明的是，本公开的各个实施例中，存储电容C1可以是通过工艺制程制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现，并且，存储电容C1也可以是各个器件之间的寄生电容，可以通过晶体管本身与其他器件、线路来实现。存储电容C1的连接方式不局限于上面描述的方式，也可以为其他适用的连接方式，只要能存储写入到第一节点N1的电平即可。
本公开的实施例提供的像素电路20可以降低有机发光二极管(OLED)器件损伤的几率，对OLED器件起保护作用，可以延长OLED器件的使用寿命。
在工作时，像素电路20除了在上述感测阶段中进行感测操作以外，还在显示阶段中进行发光以显示画面。在显示阶段中，使驱动电路21和保护电路25共同提供驱动电流，以驱动发光元件L发光。关于显示阶段中数据写入电路22、存储电路23、驱动电路21、发光元件L的基本工作方式，可以参考 常规设计，此处不再详述。
以图3所示的像素电路20为例，在驱动电流的流动路径中，不仅设置有第一晶体管T1，还设置有第二晶体管T2。第二晶体管T2具有正反馈作用，和第一晶体管T1一起提供驱动电流。因此，相比于通常的仅由驱动晶体管提供驱动电流的情形，本公开实施例提供的像素电路20中的第一晶体管T1的沟道电流需要适当减小，从而使得第一晶体管T1与第二晶体管T2共同提供的驱动电流保持不变，以使发光元件L显示所需要的灰阶。
例如，为了保持发光元件L(例如OLED)充电特性的一致性，需要调整第一晶体管T1的电流电压曲线特性。例如，可以通过改变第一晶体管T1的沟道宽长比来实现，假设通常的驱动晶体管的沟道宽长比为18：6，则对于本公开实施例中的第一晶体管T1，其沟道宽长比可以降低为16.5：6。当然，本公开的实施例不限于此，在其他示例中，第一晶体管T1的沟道宽长比相比于通常的驱动晶体管的沟道宽长比可以减小10％～30％。例如，第一晶体管T1的沟道宽长比的范围是12.6:6至16.2:6，由此可以减小流经第一晶体管T1的驱动电流，为第二晶体管T2所产生的驱动电流留出余量。
需要说明的是，上述数值范围仅为示例性的，而非限制性的，第一晶体管T1的沟道宽长比的数值范围还可以为其他具体数值，本公开的实施例对此不作限制，这可以根据实际需求而定。
图6A为本公开一些实施例提供的一种显示面板中阵列基板的剖面示意图。如图6A所示，在一些实施例中，阵列基板101包括衬底基板111、缓冲层112、栅绝缘层113。第一晶体管T1包括有源层1141。缓冲层112设置在衬底基板111上，有源层1141设置在缓冲层112上，栅绝缘层113设置在缓冲层112上且覆盖有源层1141，第一晶体管T1的栅极1142设置在栅绝缘层113上。
例如，阵列基板101还包括层间绝缘层115。层间绝缘层115设置在栅绝缘层113上且覆盖第一晶体管T1的栅极1142，第一晶体管T1的第一极1143和第一晶体管T1的第二极1144设置在层间绝缘层115上。由此，第一晶体管T1构成顶栅型结构，第一晶体管T1的第一极1143和第二极1144位于同一层，第一极1143和第二极1144所在的膜层不同于栅极1142所在的膜层，从而可以提高布线的灵活性。
例如，阵列基板101还包括数据线Vdata，数据线Vdata用于传输数据信 号。数据线Vdata设置在层间绝缘层115上，数据线Vdata与第一晶体管T1的第一极1143和第一晶体管T1的第二极1144位于同一层，从而减少工艺，提高制备效率。
例如，第一晶体管T1的第一极1143通过至少贯穿栅绝缘层113的第一过孔H1与有源层1141连接，第一晶体管T1的第二极1144通过至少贯穿栅绝缘层113的第二过孔H2与有源层1141连接。在该示例中，第一过孔H1贯穿栅绝缘层113和层间绝缘层115，第二过孔H2也贯穿栅绝缘层113和层间绝缘层115。例如，有源层1141中被第一过孔H1和/或第二过孔H2暴露的部分为通过等离子体掺杂形成的导体化区域。
例如，在一些示例中，阵列基板101还包括遮光层116。遮光层116设置在衬底基板111上，缓冲层112设置在衬底基板111上且覆盖遮光层116。遮光层116可以防止杂散光对有源层1141产生不利影响。例如，遮光层116的材料为金属，在一些示例中，遮光层116可以为双层金属结构，以降低电阻，还可以提高阻抗特性和电磁兼容特性。当然，遮光层116也可以为单层金属结构、三层金属结构或其他适用的多层金属结构，这可以根据实际需求而定，本公开的实施例对此不作限制。
例如，遮光层116的至少部分复用为第二晶体管T2的栅极。例如，遮光层116中与第二晶体管T2的有源层(图6A中未示出)重叠的部分复用为第二晶体管T2的栅极，从而使第一晶体管T1和第二晶体管T2形成垂直型双栅晶体管，由此提高电学特性，简化制备工艺。
例如，在遮光层116的至少部分复用为第二晶体管T2的栅极的情形中，第一晶体管T1的第一极1143复用为第二晶体管T2的第一极，第一晶体管T1的第二极1144复用为第二晶体管T2的第二极。也即是，第一极1143既作为第一晶体管T1的第一极，又作为第二晶体管T2的第一极；第二极1144既作为第一晶体管T1的第二极，又作为第二晶体管T2的第二极。第二晶体管T2的第二极(也即图6A中示出的第二极1144)通过至少贯穿缓冲层112、栅绝缘层113的第三过孔H3与遮光层116连接。在该示例中，第三过孔H3贯穿缓冲层112、栅绝缘层113和层间绝缘层115。
图6B为本公开一些实施例提供的另一种显示面板中阵列基板的剖面示意图。如图6B所示，在一些实施例中，阵列基板101包括衬底基板111、缓冲层112、栅绝缘层113。第一晶体管T1包括有源层1141。缓冲层112设置 在衬底基板111上，有源层1141设置在缓冲层112上，栅绝缘层113设置在缓冲层112上且覆盖有源层1141，第一晶体管T1的栅极1142设置在栅绝缘层113上。例如，第一晶体管T1的第一极1143和第一晶体管T1的第二极1144设置在栅绝缘层113上，第一晶体管T1的第一极1143、第一晶体管T1的第二极1144、第一晶体管T1的栅极1142位于同一层。由此，第一晶体管T1构成顶栅型结构，第一晶体管T1的第一极1143、第二极1144、栅极1142位于同一层，例如均位于栅金属层，从而可以减小阵列基板101的厚度，减少膜层数量，便于使阵列基板101轻薄化。
例如，阵列基板101还包括数据线Vdata，数据线Vdata用于传输数据信号。数据线Vdata设置在栅绝缘层113上，数据线Vdata与第一晶体管T1的栅极1142、第一晶体管T1的第一极1143、第一晶体管T1的第二极1144位于同一层，从而减少工艺，提高制备效率。
需要注意的是，虽然第一晶体管T1的第一极1143、第二极1144、栅极1142位于同一层，但是，第一极1143、第二极1144、栅极1142彼此分隔开，并未直接连接，从而避免短路。除了没有设置层间绝缘层115，图6B所示的膜层结构的其他部件与图6A所示的膜层结构基本相同，相关说明可参考上文相关描述，此处不再赘述。
图7为本公开一些实施例提供的另一种显示面板中阵列基板的剖面示意图。在一些实施例中，如图7所示，第一晶体管T1的第一极1143和第一晶体管T1的第二极1144中的一个为第一晶体管T1的漏极，第一过孔H1和第二过孔H2中与第一晶体管T1的漏极相邻的过孔与第三过孔H3为同一个过孔。在该示例中，第一晶体管T1的第二极1144为漏极，与该漏极相邻的过孔为第二过孔H2，第二过孔H2与第三过孔H3为同一个过孔，也即是，第二过孔H2与第三过孔H3彼此连通，共同成为一个过孔。由此，可以简化制备工艺。例如，第一晶体管T1的漏极(也即第二极1144)通过第三过孔H3与有源层1141暴露的部分、遮光层116暴露的部分均连接，从而实现图3所示的电路结构的连接方式。除了第二过孔H2与第三过孔H3的设置方式之外，图7所示的膜层结构的其他部件与图6A所示的膜层结构基本相同，相关说明可参考上文相关描述，此处不再赘述。
图8为本公开一些实施例提供的一种显示面板中有源层的平面示意图。在一些实施例中，如图8所示，有源层1141包括至少一个开槽区117，开槽 区117是在垂直于衬底基板111的方向上贯通有源层1141的孔。在图8所示的示例中，有源层1141包括的开槽区117的数量为1，也即是，有源层1141包括一个开槽区117。
第一晶体管T1的第一极1143和第一晶体管T1的第二极1144中的一个为第一晶体管T1的源极，第一过孔H1和第二过孔H2中与第一晶体管T1的源极相邻的过孔为目标过孔，开槽区117与目标过孔相邻。在该示例中，第一晶体管T1的第一极1143为源极，第一过孔H1是与第一晶体管T1的源极相邻的过孔，因此第一过孔H1为目标过孔，开槽区117与第一过孔H1相邻。
例如，开槽区117的形状为矩形。当然，本公开的实施例不限于此，开槽区117的形状还可以为正方形、梯形、圆形、椭圆形、不规则多边形等任意形状，这可以根据实际需求而定，本公开的实施例对此不作限制。
图9A为图8中A-A’线的剖面示意图，图9B为图8中B-B’线的剖面示意图。结合图8、图9A、图9B，开槽区117与第一过孔H1相邻，也即是，开槽区117设置在有源层1141靠近第一过孔H1的一端。开槽区117是在垂直于衬底基板111的方向上贯通有源层1141的孔，也即，在开槽区117内，有源层1141由于被挖槽而缺失。在开槽区117之外的其他位置，有源层1141未被挖槽因而是连续的。例如，目标过孔(第一过孔H1)暴露有源层1141的一部分，并且通过开槽区117暴露缓冲层112的一部分。需要说明的是，在图9A和图9B中，遮光层116未示出，这仅是为了简洁，并不构成对本公开实施例的限制。
通过在有源层1141设置开槽区117，使得有源层1141存在部分是断开的，从而可以在保持第一晶体管T1的沟道形状/宽长比不变的情况下，减小第一晶体管T1的沟道电流，使得减小的电流由保护电路25的第二晶体管T2通过正反馈补偿，以使第一晶体管T1和第二晶体管T2共同提供的驱动电流符合预期大小。由于第一晶体管T1的沟道形状/宽长比不变，因此可以尽量降低版图设计的改变程度，减少版图设计的工作量。
图10为图8所示的有源层的各个尺寸的标注示意图。如图10所示，有源层1141的参照宽度为Wd，参照宽度Wd为在未开槽且仅由第一晶体管T1提供驱动电流的情况下的有源层宽度。开槽区117的宽度为Wvia，有源层1141在开槽区117的位置上的有效宽度为W1，有源层1141在未开槽的部位的有效宽度为W2，W2＝Wd。例如，W1＝Wd-Wvia。有源层1141的参照长度为 Ld，参照长度Ld为在未开槽且仅由第一晶体管T1提供驱动电流的情况下的有源层长度。开槽区117的长度为L1，有源层117在未开槽的部位的有效长度为L2，Ld＝L1+L2。
例如，根据薄膜晶体管电流积分原理对第一晶体管T1(第一晶体管T1已经被挖槽)进行电流积分计算，可以采用如下公式计算：
其中，μ是载流子迁移率，Cgi是栅绝缘层介电常数，Vgs是栅源电压，Vth是阈值电压，Vds是漏源电压。例如，这些电学参数对于挖槽和未挖槽的沟道设计可以设定为相同的常数值。例如，I和dy是积分计算的自变量。
例如，对没有挖槽的晶体管(也即，第一晶体管T1在未挖槽时)的沟道电流进行积分计算，可以采用如下公式计算：
例如，第一晶体管T1的预设沟道电流表示为I1，预设沟道电流I1为在未开槽且仅由第一晶体管T1提供驱动电流的情况下的沟道电流。第一晶体管T1的挖槽沟道电流表示为I2，挖槽沟道电流I2为第一晶体管T1在挖槽之后的沟道电流。挖槽沟道电流I2对应于上述公式(1-1)，预设沟道电流I1对应于上述公式(1-2)，因此，根据上述公式(1-1)和公式(1-2)，可以得到I2与I1的比值，该比值满足如下公式：
例如，I2/I1的数值范围为1～1.5，也即是，上述公式的比值范围为1～1.5，由此可以使由于在沟道形成挖槽所导致的电流损失不至于过大，使得电流损失在50％以内，使开槽区117的尺寸不至于过大，从而避免开槽区117对层结构的稳定性、电路特性的稳定性产生影响。
例如，第一晶体管T1的初始沟道电流表示为Id。例如，第一晶体管T1的初始沟道电流Id等于第一晶体管T1的挖槽沟道电流I2，也即，第一晶体管T1的初始沟道电流Id等于在第一晶体管T1已被挖槽的情况下的沟道电流。因此，初始沟道电流Id对应于上述公式(1-1)。
例如，第二晶体管T2的沟道宽度为W3，第二晶体管T2的沟道长度为L3。对第二晶体管T2进行电流积分计算，可以采用如下公式计算：
其中，Cbuf是第二晶体管T2的栅绝缘层的电容，由于将遮光层116复用为第二晶体管T2的栅极，因此，第二晶体管T2的栅绝缘层的电容Cbuf为缓冲层112的电容。
例如，缓冲层112的厚度为dbuf，栅绝缘层113的厚度为dgi。由于使用氮化硅(SiN)作为第二晶体管T2的栅绝缘层，缓冲层112和栅绝缘层113都使用SiN，其介电常数相同，沟道单位面积相同，但是这些膜层的厚度不同，所以，根据电容计算公式C＝ε*Α/d(这里，ε表示介电常数，Α表示沟道单位面积，d表示厚度，C表示电容)可知，Cgi与Cbuf的比值等于它们的厚度的反比值，也即等于dbuf/dgi。
例如，第二晶体管T2的沟道电流为Ie，基于上述公式(1-1)和(1-3)以及关于电容比值的推导，Ie与Id满足如下公式：
例如，Id/Ie的数值范围为0.5～1，也即是，上述公式的比值范围为0.5～1，上述比值至少达到50％以上。由此，可以由与第一晶体管T1并联的第二晶体管T2补充第一晶体管T1由于挖槽而减少的驱动电流，从而保持充电特性不变。
例如，I2/I1的数值范围为1～1.5，Id/Ie的数值范围为0.5～1，从而在第一晶体管T1的沟道形成挖槽的尺寸不会太大，不会导致电流损失过大，电流损失比值在50％以内，并联的第二晶体管T2作为第一晶体管T1的垂直型双栅晶体管可以对电流进行补充，Id/Ie的比值至少达到50％以上。由此，可以使整个电路达到较好的电学特性。
例如，在一些示例中，测量得到各个参数。对于第一晶体管T1，W1＝27.7μm，L1＝Ld-L2＝35μm，Ld＝40μm，W2＝(10.7-4.4)μm＝6.3μm，Wd＝27.7μm，L2＝4.7μm，Wvia＝4.4μm。对于第二晶体管T2，W3＝27.7μm，L3＝28μm。栅绝缘层113的厚度dgi＝0.166μm，缓冲层112的厚度dbuf＝0.37μm。
计算得到：该数值在1～1.5的范围内。
计算得到：该数值在0.5～1的范围内。
例如，在另一些示例中，对各个参数进行如下设计。对于第一晶体管T1，W1＝16.84μm，L1＝Ld-L2＝29μm，Ld＝31.43μm，W2＝12.19μm，Wd＝16.84μm，L2＝2.39μm，Wvia＝4.65μm。对于第二晶体管T2，W3＝16.84μm，L3＝28μm。栅绝缘层113的厚度dgi＝0.166μm，缓冲层112的厚度dbuf＝0.37μm。
计算得到：该数值在1～1.5的范围内。
计算得到：该数值在0.5～1的范围内。
将该示例与上述示例进行比较可知，在该示例中，显示屏尺寸小于上述示例的显示屏尺寸，单个OLED像素单元(或子像素)的面积更小，有机发光材料的有效显示面积减少使得驱动电流降低，驱动晶体管(第一晶体管T1)的沟道宽长比和沟道面积也减小，沟道尺寸的减小使得沟道挖槽尺寸(开槽区尺寸)也减小，且随着尺寸减小对工艺良率(工艺尺寸偏差和工艺尺寸对准)要求相应提高(例如，同样的2微米偏差占30微米特征尺寸的1/15，而占10微米特征尺寸的1/5，所以影响更大)。因此，在本示例中降低了沟道挖槽(开槽区)在沟道中所占的比例以及对电流的损失影响，且像素变小后，为了保证开口率，遮光层金属(遮光层116复用为并联的第二晶体管T2的栅极)的面积也减小，使得并联的第二晶体管T2的补充电流也相应减小。因此，对于I2/I1和Id/Ie这两种电流比值分别设定最大值和最小值范围，可以适应不同尺寸显示屏、不同有机发光材料导致的不同驱动电流要求以及不同像素大小和不同晶体管尺寸的设计要求。
图11为本公开一些实施例提供的另一种显示面板中有源层的平面示意图，图12A为图11中C-C’线的剖面示意图，图12B为图11中D-D’线的剖面示意图。如图11、图12A、图12B所示，在一些实施例中，开槽区117包括2个开槽区，也即第一开槽区1171和第二开槽区1172。第一开槽区1171与第一过孔H1相邻，第二开槽区1172与第二过孔H2相邻。在该示例中，在第一晶体管T1的源极和漏极均设置有开槽区，从而可以进一步减小第一晶体管T1提供的驱动电流。
第一开槽区1171和第二开槽区1172是在垂直于衬底基板111的方向上贯通有源层1141的孔，也即，在第一开槽区1171和第二开槽区1172内，有源层1141由于被挖槽而缺失。在第一开槽区1171和第二开槽区1172之外的其他位置，有源层1141未被挖槽因而是连续的。需要说明的是，在图12A和图 12B中，遮光层116未示出，这仅是为了简洁，并不构成对本公开实施例的限制。
例如，第一过孔H1暴露有源层1141的一部分，并且通过第一开槽区1171暴露缓冲层112的一部分；并且/或者，第二过孔H2暴露有源层1141的一部分，并且通过第二开槽区1172暴露缓冲层112的一部分。在一些示例中，第一开槽区1171和第二开槽区1172的形状均为矩形。当然，本公开的实施例不限于此，第一开槽区1171和第二开槽区1172的形状还可以为正方形、梯形、圆形、椭圆形、不规则多边形等任意形状，这可以根据实际需求而定，本公开的实施例对此不作限制。第一开槽区1171的形状和第二开槽区1172的形状可以相同或不同。
例如，第一开槽区1171的尺寸与第二开槽区1172的尺寸相同。这里，尺寸相同可以指具有相同形状且各个边的长度相同，也可以指面积相同。当然，本公开的实施例不限于此，第一开槽区1171和第二开槽区1172的尺寸也可以彼此不同，例如第一开槽区1171和第二开槽区1172中的一个开槽区的尺寸较大，第一开槽区1171和第二开槽区1172中的另一个开槽区的尺寸较小，这可以根据实际需求而定，本公开的实施例对此不作限制。例如，第一开槽区1171和第二开槽区1172可以对称设置，例如两者为轴对称。
通过在有源层1141设置第一开槽区1171和第二开槽区1172，使得有源层1141存在部分是断开的，从而可以在保持第一晶体管T1的沟道形状/宽长比不变的情况下，减小第一晶体管T1的沟道电流，使得减小的电流由保护电路25的第二晶体管T2通过正反馈补偿，以使第一晶体管T1和第二晶体管T2共同提供的驱动电流符合预期大小。由于第一晶体管T1的沟道形状/宽长比不变，因此可以尽量降低版图设计的改变程度，减少版图设计的工作量。相比于仅设置一个开槽区的示例，在该示例中，通过设置两个开槽区(第一开槽区1171和第二开槽区1172)，可以进一步减小第一晶体管T1的电流。例如，对于具有两个开槽区的情形，上述针对一个开槽区的沟道电流的计算公式仍然适用，此处不再赘述。
图13A至图13C为本公开一些实施例提供的一种显示面板中阵列基板的刻蚀工艺示意图。通过图13A至图13C所示的工艺操作，可以将有源层1141刻蚀一部分，从而在过孔处使有源层1141断开，以形成开槽区，使有源层1141位于过孔处的部分断开，使过孔暴露有源层1141的一部分且暴露缓冲层112 的一部分。例如，使用IGZO氧化物作为有源层1141的材料。
如图13A所示，在栅绝缘层113掩模后，进行刻蚀工艺，可以在栅绝缘层113形式初始过孔HGI。同时，孔内的IGZO需要进行导体化工艺，以提高导电性能。此时作为有源层1141的IGZO未断开，有源层1141是连续的。由于需要将栅绝缘层113刻穿，此时的过刻蚀(Over Etch，OE)较大。如图13B所示，进行栅金属层GM的涂覆，并进行图案化处理。例如，栅金属层GM用于形成栅极1142等结构。使用自对准工艺对栅绝缘层113进行整面刻蚀，形成拖尾(GI Tail)，并进行IGZO导体化处理。如图13C所示，交叠区域由于IGZO受到2次刻蚀和2次导体化处理，IGZO发生缺失，从而形成开槽区，需要注意的是，这不会影响信号传输。
图14为本公开一些实施例提供的一种显示面板中阵列基板的剖面示意图。如图14所示，第三过孔H3具有彼此相对的第一侧壁H31和第二侧壁H32，第一侧壁H31靠近有源层1141，第二侧壁H32远离有源层1141。例如，第一侧壁H31的坡度与第二侧壁H32的坡度不同。在一些示例中，第一侧壁H31的坡度大于第二侧壁H32的坡度。这里，坡度是指第一侧壁H31和第二侧壁H32的陡缓程度，可以为坡角的正切值。例如，第一侧壁H31的坡角为a1，第二侧壁H32的坡角为a2，a1>a2，tan(a1)>tan(a2)，第一侧壁H31的坡度大于第二侧壁H32的坡度。
例如，第三过孔H3是将第二晶体管T2的第二极(第一晶体管T1的第二极1143可以复用为第二晶体管T2的第二极)与复用为第二晶体管T2的栅极的遮光层116连接的过孔。由于两侧的刻蚀厚度不同，第三过孔H3的一侧只有缓冲层112过刻蚀使得坡度更陡(也即第一侧壁H31的坡度更陡)，有利于增加平衡栅金属层GM和遮光层116的接触面积。第三过孔H3的另一侧存在缓冲层112和栅绝缘层113的刻蚀，使得坡度较小(也即第二侧壁H32的坡度较小)，从而有利于附着在第二侧壁H32上的金属材料爬坡。
图15为本公开一些实施例提供的另一种显示面板中阵列基板的剖面示意图。如图15所示，阵列基板101还包括栅金属层GM、钝化层118、平坦化层119。栅金属层GM设置在栅绝缘层113上，钝化层118和平坦化层119依序层叠设置。例如，在第一晶体管T1的栅极1142、第一晶体管T1的第一极1143、第一晶体管T1的第二极1144设置在同一层的情形中，第一晶体管T1的栅极1142、第一晶体管T1的第一极1143、第一晶体管T1的第二极1144 均位于栅金属层GM。例如，在第一晶体管T1的栅极1142、第一晶体管T1的第一极1143、第一晶体管T1的第二极1144设置在不同层的情形中，第一晶体管T1的栅极1142位于栅金属层GM。
例如，钝化层118设置在栅金属层GM上。发光元件L的第一端L01为阳极，该阳极通过贯穿钝化层118的第四过孔H4与位于栅金属层GM的转接部GMP连接，转接部GMP通过第三过孔H3与遮光层116和第一晶体管T1的第二极1144连接。
例如，第四过孔H4与第三过孔H3彼此靠近的边缘之间的距离为das，第三过孔H3在栅金属层GM所在平面的孔径为ds，das与ds满足如下关系：
例如，在一些示例中，das＝ds，也即是，第四过孔H4与第三过孔H3彼此靠近的边缘之间的距离等于第三过孔H3在栅金属层GM所在平面的孔径。
通过使第四过孔H4与第三过孔H3彼此靠近的边缘之间的距离das、第三过孔H3在栅金属层GM所在平面的孔径ds满足上述关系，有利于降低平坦化层119光刻时由于厚度不均匀导致的边沿曝光的不均匀性，可以降低类似的工艺偏差。
例如，第一晶体管T1的第二极1144的远离第三过孔H3的边缘与第一晶体管T1的第二极1144的靠近第三过孔H3的边缘之间的距离为dgs，第三过孔H3在栅金属层GM所在平面的孔径为ds，dgs与ds满足如下关系：
例如，在一些示例中，dgs＝ds，也即是，第一晶体管T1的第二极1144的远离第三过孔H3的边缘与第一晶体管T1的第二极1144的靠近第三过孔H3的边缘之间的距离等于第三过孔H3在栅金属层GM所在平面的孔径。
通过使第一晶体管T1的第二极1144的远离第三过孔H3的边缘与第一晶体管T1的第二极1144的靠近第三过孔H3的边缘之间的距离dgs、第三过孔H3在栅金属层GM所在平面的孔径ds满足上述关系，有利于降低平坦化层119光刻时由于厚度不均匀导致的边沿曝光的不均匀性，可以降低类似的工艺偏差。
例如，在一些示例中，第四过孔H4与第三过孔H3彼此靠近的边缘之间的距离das、第三过孔H3在栅金属层GM所在平面的孔径ds、第一晶体管 T1的第二极1144的远离第三过孔H3的边缘与第一晶体管T1的第二极1144的靠近第三过孔H3的边缘之间的距离dgs这三者均相等，也即是，das＝ds＝dgs。由此，可以更有效地降低平坦化层119光刻时由于厚度不均匀导致的边沿曝光的不均匀性。当然，本公开的实施例不限于此，也可以仅das＝ds，而dgs≠ds；或者，也可以仅dgs＝ds，而das≠ds。这可以根据实际需求而定，本公开的实施例对此不作限制。
图16为本公开一些实施例提供的另一种显示面板中阵列基板的剖面示意图。如图16所示，在一些示例中，阵列基板101还包括钝化层118和平坦化层119。第一晶体管T1的第一极1143和第一晶体管T1的第二极1144中的一个为第一晶体管T1的漏极，在该示例中，第一晶体管T1的第二极1144为漏极。钝化层118和平坦化层119依序层叠设置，并且位于第一晶体管T1的漏极之上(也即位于第一晶体管T1的第二极1144之上)。钝化层118和平坦化层119中具有第五过孔H5。第五过孔H5贯穿钝化层118和平坦化层119，第五过孔H5暴露第一晶体管T1的漏极。第五过孔H5包括位于钝化层118与平坦化层119的交界面的台阶，该台阶的宽度小于或等于1μm。
例如，遮光层116设置在衬底基板111上，缓冲层112设置在衬底基板111上且覆盖遮光层116，遮光层116的材料为金属，遮光层116复用为第二晶体管T2的栅极。第五过孔H5在垂直于衬底基板111的方向上的正投影与遮光层116中复用为第二晶体管T2的栅极的部分在垂直于衬底基板111的方向上的正投影至少部分交叠。在该示例中，遮光层116中复用为第二晶体管T2的栅极的部分例如为图16中所示的T2G，该部分在垂直于衬底基板111的方向上的正投影与第五过孔H5在垂直于衬底基板111的方向上的正投影至少部分交叠(例如可以全部交叠或部分交叠)。例如，遮光层116中复用为第二晶体管T2的栅极的部分可以是遮光层116中与第二晶体管T2的有源层1201在垂直于衬底基板111的方向上重叠的部分。
例如，在一些示例中，遮光层116还复用为第四晶体管T4的栅极，遮光层116还可以复用为第一电压端VDD。需要说明的是，遮光层116可以复用为第二晶体管T2的栅极、第四晶体管T4的栅极、第一电压端VDD中的任意一个或多个，这可以根据实际需求而定，本公开的实施例对此不作限制。例如，遮光层116可以仅复用为第二晶体管T2的栅极；遮光层116可以仅复用为第四晶体管T4的栅极；遮光层116可以仅复用为第一电压端VDD；遮 光层116可以复用为第二晶体管T2的栅极、第四晶体管T4的栅极、第一电压端VDD中的任意两个；遮光层116可以复用为第二晶体管T2的栅极、第四晶体管T4的栅极、第一电压端VDD这三者。
需要说明的是，在复用遮光层116时，根据电连接关系将对应的复用部分与其他不能传导该复用部分的电信号的部分通过槽、图案化等方式分隔开即可，由此确保电连接关系的正确性和电信号的正确性。
例如，遮光层116的材料为金属，在一些示例中，遮光层116可以为双层金属结构，以减小电阻，还可以提高阻抗特性和电磁兼容特性。当然，遮光层116也可以为单层金属结构、三层金属结构或其他适用的多层金属结构，这可以根据实际需求而定，本公开的实施例对此不作限制。
图17A至图17F为本公开一些实施例提供的一种显示面板中阵列基板的各个层结构的平面布局图。下面结合图17A至图17F对工艺流程进行简单说明。
如图17A所示，首先进行遮光层116的掩模工艺。遮光层116例如采用双层铜(Cu)结构，也可以采用钼(Mo)和钛/铜(Ti/Cu)。遮光层116的厚度为遮光层116用于实现遮光以及源漏信号输入等功能。例如，数据线Vdata、第一电压端VDD均形成在遮光层116中，因此可以省略传统的SD膜层，由此减少膜层数量，减少工艺。
如图17B所示，接着进行有源层ACT的掩模工艺。例如，采用IGZO作为有源层ACT，其厚度为需要说明的是，所有晶体管的有源层均在该工艺中形成，包括第一晶体管T1的有源层1141以及其他晶体管的有源层。
如图17C所示，在栅绝缘层113掩模之后，采用刻蚀工艺将栅绝缘层113刻穿，需要与遮光层116贯通的部位要将栅绝缘层113和缓冲层112均刻穿，从而形成前述的第一过孔H1、第二过孔H2、第三过孔H3等。由于有源层ACT(IGZO)的阻挡，缓冲层112中的过孔较小，该过孔用于连接栅金属层GM与遮光层116。
如图17D所示，进行栅金属层GM的制备。形成栅金属层GM后，可以通过对应的过孔与遮光层116连接。数据信号、第一电压均由遮光层116中对应的复用部分传入至栅金属层GM中对应的部分。进行栅金属层GM的刻蚀之后，进行栅绝缘层113的刻蚀以及有源层ACT中对应部分的导体化。例如，第三晶体管T3、第四晶体管T4、第一扫描线S1、第二扫描线S2位于第 一晶体管T1的同一侧。
如图17E所示，进行钝化层118和平坦化层119的制备。例如，钝化层118和平坦化层119可以共用一道掩模工艺，并形成过孔Hc，以便于将相应的信号传输至后续形成的OLED的阳极。
如图17F所示，进行OLED阳极(发光元件L的第一端L01)的制备。例如，采用氧化铟锡(Indium tin oxide，ITO)作为OLED的阳极的材料。
需要说明的是，上文描述了部分工艺，而非全部工艺，例如省略了针对缓冲层112等膜层的说明。例如，如图18所示，还可以包括针对像素单元(R、G、B)、像素界定层PDL等膜层的工艺，该阵列基板总计需要10道掩模(Mask)。
本公开至少一个实施例还提供一种半导体显示装置，该半导体显示装置包括本公开任一实施例提供的半导体基板(也即显示面板)。该半导体显示装置可以降低有机发光二极管(OLED)器件损伤的几率，对OLED器件起保护作用，可以延长OLED器件的使用寿命。
图19为本公开一些实施例提供的一种显示装置的示意框图。如图19所示，显示装置30包括显示面板31，显示面板31例如为本公开任一实施例提供的显示面板，例如为上文描述的显示面板100。例如，显示装置30可以为OLED显示面板、OLED电视、OLED显示器等，也可以为其他适用的具有显示功能的产品或部件，本公开的实施例对此不作限制。显示装置30的技术效果可以参考上述实施例中关于显示面板100的相应描述，这里不再赘述。
图20为本公开一些实施例提供的另一种显示装置的示意框图。如图20所示，显示装置40包括显示面板4000、栅极驱动器4010、定时控制器4020和数据驱动器4030。显示面板4000包括根据多条扫描线GL和多条数据线DL交叉限定的多个像素单元P。显示面板4000例如为本公开任一实施例提供的显示面板，例如为上文描述的显示面板100。多条扫描线GL包括前述的第一扫描线S1和第二扫描线S2，多条数据线DL包括前述的数据线Vdata。栅极驱动器4010用于驱动多条扫描线GL；数据驱动器4030用于驱动多条数据线DL；定时控制器4020用于处理从显示装置40外部输入的图像数据RGB，向数据驱动器4030提供处理的图像数据RGB以及向栅极驱动器4010和数据驱动器4030输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动器4010和数据驱动器4030进行控制。
例如，栅极驱动器4010可以实现为半导体芯片，也可以集成在显示面板4000中以构成GOA电路。
例如，数据驱动器4030使用参考伽玛电压根据源自定时控制器4020的多个数据控制信号DCS将从定时控制器4020输入的数字图像数据RGB转换成数据信号。数据驱动器4030向多条数据线DL提供转换的数据信号。例如，数据驱动器4030可以实现为半导体芯片。
例如，定时控制器4020对外部输入的图像数据RGB进行处理以匹配显示面板4000的大小和分辨率，然后向数据驱动器4030提供处理后的图像数据。定时控制器4020使用从显示装置40外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器4020分别向栅极驱动器4010和数据驱动器4030提供产生的扫描控制信号GCS和数据控制信号DCS，以用于栅极驱动器4010和数据驱动器4030的控制。
该显示装置40还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
例如，显示面板4000可以应用于电子书、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件中。
本公开至少一个实施例还提供一种驱动方法，用于驱动本公开任一实施例提供的半导体基板(也即显示面板)。利用该驱动方法，可以降低有机发光二极管(OLED)器件损伤的几率，对OLED器件起保护作用，可以延长OLED器件的使用寿命。
图21为本公开一些实施例提供的一种用于显示面板的驱动方法的流程示意图。如图21所示，在一些实施例中，该驱动方法包括如下操作。
步骤S51：在显示阶段，使驱动电路和保护电路共同提供驱动电流，以驱动发光元件发光；
步骤S52：在感测阶段，使感测电路开启以将驱动电路的第二端与感测信号线连接，并且利用保护电路阻止感测电路产生的静电流动至发光元件。
需要说明的是，关于该驱动方法的详细描述可以参考本公开的实施例中对于像素电路20的工作原理的描述，这里不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到本公开实施例涉及到的结构，其他结构 可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (50)

  1. 一种半导体基板，包括阵列基板，其中，所述阵列基板包括多个阵列排布的像素单元，每个像素单元包括像素电路和发光元件；
    所述像素电路包括驱动电路、数据写入电路、存储电路、感测电路和保护电路；
    所述驱动电路包括控制端、第一端和第二端，且配置为控制驱动所述发光元件发光的驱动电流，所述驱动电路的第一端接收第一电压端的第一电压；
    所述数据写入电路与所述驱动电路的控制端连接，且配置为响应于第一扫描信号将数据信号写入所述驱动电路的控制端；
    所述存储电路的第一端与所述驱动电路的控制端连接，所述存储电路的第二端与所述驱动电路的第二端连接，所述存储电路配置为存储所述数据写入电路写入的所述数据信号；
    所述感测电路与所述驱动电路的第二端连接，且配置为响应于第二扫描信号将所述驱动电路的第二端与感测信号线连接；
    所述保护电路包括控制端、第一端和第二端，所述保护电路的第一端与所述驱动电路的第一端连接，所述保护电路的控制端和所述保护电路的第二端均与所述驱动电路的第二端连接，所述保护电路配置为阻止所述感测电路产生的静电流动至所述发光元件，并且与所述驱动电路共同提供所述驱动电流；
    所述发光元件的第一端与所述驱动电路的第二端连接，所述发光元件的第二端接收第二电压端的第二电压，所述发光元件配置为根据所述驱动电流发光。
  2. 根据权利要求1所述的半导体基板，其中，所述驱动电路包括第一晶体管；
    所述第一晶体管的栅极作为所述驱动电路的控制端，所述第一晶体管的第一极作为所述驱动电路的第一端，所述第一晶体管的第二极作为所述驱动电路的第二端。
  3. 根据权利要求2所述的半导体基板，其中，所述保护电路包括第二晶体管；
    所述第二晶体管的栅极作为所述保护电路的控制端，所述第二晶体管的 第一极作为所述保护电路的第一端，所述第二晶体管的第二极作为所述保护电路的第二端；
    所述第二晶体管的第一极与所述第一晶体管的第一极连接；
    所述第二晶体管的栅极与所述第二晶体管的第二极连接，且连接至所述第一晶体管的第二极。
  4. 根据权利要求3所述的半导体基板，其中，所述第二晶体管构成二极管连接方式。
  5. 根据权利要求3所述的半导体基板，其中，所述第一晶体管与所述第二晶体管均为N型薄膜晶体管或者均为P型薄膜晶体管。
  6. 根据权利要求2-5任一项所述的半导体基板，其中，所述数据写入电路包括第三晶体管；
    所述第三晶体管的栅极与第一扫描线连接以接收所述第一扫描信号，所述第三晶体管的第一极与数据线连接以接收所述数据信号，所述第三晶体管的第二极与所述驱动电路的控制端连接。
  7. 根据权利要求6所述的半导体基板，其中，所述感测电路包括第四晶体管；
    所述第四晶体管的栅极与第二扫描线连接以接收所述第二扫描信号，所述第四晶体管的第一极与所述驱动电路的第二端连接，所述第四晶体管的第二极与所述感测信号线连接。
  8. 根据权利要求1-5任一项所述的半导体基板，其中，所述存储电路包括存储电容；
    所述存储电容的第一极作为所述存储电路的第一端，所述存储电容的第二极作为所述存储电路的第二端。
  9. 根据权利要求1-5任一项所述的半导体基板，其中，所述发光元件包括有机发光二极管，所述有机发光二极管的阳极作为所述发光元件的第一端，所述有机发光二极管的阴极作为所述发光元件的第二端。
  10. 根据权利要求1-5任一项所述的半导体基板，还包括复位电路，其中，
    所述复位电路与所述驱动电路的控制端连接，且配置为响应于复位信号将复位电压施加至所述驱动电路的控制端。
  11. 根据权利要求10所述的半导体基板，其中，所述复位电路包括第五 晶体管；
    所述第五晶体管的栅极与复位信号线连接以接收所述复位信号，所述第五晶体管的第一极与所述驱动电路的控制端连接，所述第五晶体管的第二极与复位电压端连接以接收所述复位电压。
  12. 根据权利要求11所述的半导体基板，其中，所述复位电压端与所述第二电压端为同一个电压端，所述复位电压与所述第二电压为同一个电压信号。
  13. 根据权利要求2-5任一项所述的半导体基板，其中，所述第一晶体管的沟道宽长比的范围是12.6:6至16.2:6。
  14. 根据权利要求3-5任一项所述的半导体基板，其中，所述阵列基板包括衬底基板、缓冲层、栅绝缘层；
    所述第一晶体管包括有源层；
    所述缓冲层设置在所述衬底基板上，所述有源层设置在所述缓冲层上，所述栅绝缘层设置在所述缓冲层上且覆盖所述有源层，所述第一晶体管的栅极设置在所述栅绝缘层上。
  15. 根据权利要求14所述的半导体基板，其中，所述阵列基板还包括层间绝缘层；
    所述层间绝缘层设置在所述栅绝缘层上且覆盖所述第一晶体管的栅极，所述第一晶体管的第一极和所述第一晶体管的第二极设置在所述层间绝缘层上。
  16. 根据权利要求14或15所述的半导体基板，其中，所述第一晶体管的第一极和所述第一晶体管的第二极设置在所述栅绝缘层上，所述第一晶体管的第一极、所述第一晶体管的第二极、所述第一晶体管的栅极位于同一层。
  17. 根据权利要求14-16任一项所述的半导体基板，其中，所述第一晶体管的第一极通过至少贯穿所述栅绝缘层的第一过孔与所述有源层连接，所述第一晶体管的第二极通过至少贯穿所述栅绝缘层的第二过孔与所述有源层连接。
  18. 根据权利要求17所述的半导体基板，其中，所述有源层包括至少一个开槽区，所述开槽区是在垂直于所述衬底基板的方向上贯通所述有源层的孔。
  19. 根据权利要求18所述的半导体基板，其中，所述至少一个开槽区包 括第一开槽区和第二开槽区，所述第一开槽区与所述第一过孔相邻，所述第二开槽区与所述第二过孔相邻。
  20. 根据权利要求19所述的半导体基板，其中，
    所述第一过孔暴露所述有源层的一部分，并且通过所述第一开槽区暴露所述缓冲层的一部分；和/或
    所述第二过孔暴露所述有源层的一部分，并且通过所述第二开槽区暴露所述缓冲层的一部分。
  21. 根据权利要求19或20所述的半导体基板，其中，所述第一开槽区和所述第二开槽区的形状均为矩形。
  22. 根据权利要求21所述的半导体基板，其中，所述第一开槽区的尺寸与所述第二开槽区的尺寸相同。
  23. 根据权利要求18所述的半导体基板，其中，所述至少一个开槽区为一个开槽区，
    所述第一晶体管的第一极和所述第一晶体管的第二极中的一个为所述第一晶体管的源极，所述第一过孔和所述第二过孔中与所述第一晶体管的源极相邻的过孔为目标过孔，
    所述开槽区与所述目标过孔相邻。
  24. 根据权利要求23所述的半导体基板，其中，所述目标过孔暴露所述有源层的一部分，并且通过所述开槽区暴露所述缓冲层的一部分。
  25. 根据权利要求23或24所述的半导体基板，其中，所述开槽区的形状为矩形。
  26. 根据权利要求25所述的半导体基板，其中，所述有源层的参照宽度为Wd，所述开槽区的宽度为Wvia，所述有源层在所述开槽区的位置上的有效宽度为W1，所述有源层在未开槽的部位的有效宽度为W2，W2＝Wd，W1＝Wd-Wvia；
    所述有源层的参照长度为Ld，所述开槽区的长度为L1，所述有源层在未开槽的部位的有效长度为L2，Ld＝L1+L2。
  27. 根据权利要求26所述的半导体基板，其中，所述第一晶体管的预设沟道电流表示为I1，所述第一晶体管的挖槽沟道电流表示为I2，
  28. 根据权利要求27所述的半导体基板，其中，I2/I1的数值范围为1～1.5。
  29. 根据权利要求27或28所述的半导体基板，其中，所述阵列基板还包括遮光层，
    所述遮光层设置在所述衬底基板上，所述缓冲层设置在所述衬底基板上且覆盖所述遮光层，所述遮光层的材料为金属，所述遮光层的至少部分复用为所述第二晶体管的栅极。
  30. 根据权利要求29所述的半导体基板，其中，所述第一晶体管的第一极复用为所述第二晶体管的第一极，所述第一晶体管的第二极复用为所述第二晶体管的第二极；
    所述第二晶体管的第二极通过至少贯穿所述缓冲层、所述栅绝缘层的第三过孔与所述遮光层连接。
  31. 根据权利要求30所述的半导体基板，其中，所述第二晶体管的沟道宽度为W3，所述第二晶体管的沟道长度为L3，所述缓冲层的厚度为dbuf，所述栅绝缘层的厚度为dgi；
    所述第二晶体管的沟道电流为Ie，所述第一晶体管的初始沟道电流为Id，所述第一晶体管的初始沟道电流Id等于所述第一晶体管的挖槽沟道电流I2；
  32. 根据权利要求31所述的半导体基板，其中，Id/Ie的数值范围为0.5～1。
  33. 根据权利要求30-32任一项所述的半导体基板，其中，所述第三过孔具有彼此相对的第一侧壁和第二侧壁，
    所述第一侧壁靠近所述有源层，所述第二侧壁远离所述有源层，
    所述第一侧壁的坡度与所述第二侧壁的坡度不同。
  34. 根据权利要求33所述的半导体基板，其中，所述第一侧壁的坡度大于所述第二侧壁的坡度。
  35. 根据权利要求33或34所述的半导体基板，其中，所述阵列基板还包括栅金属层和钝化层；
    所述栅金属层设置在所述栅绝缘层上，所述第一晶体管的栅极、所述第一晶体管的第一极、所述第一晶体管的第二极均位于所述栅金属层，所述钝化层设置在所述栅金属层上；
    所述发光元件的第一端为阳极，所述阳极通过贯穿所述钝化层的第四过孔与位于所述栅金属层的转接部连接，所述转接部通过所述第三过孔与所述遮光层和所述第一晶体管的第二极连接。
  36. 根据权利要求35所述的半导体基板，其中，所述第四过孔与所述第三过孔彼此靠近的边缘之间的距离为das，所述第三过孔在所述栅金属层所在平面的孔径为ds，
  37. 根据权利要求36所述的半导体基板，其中，das＝ds。
  38. 根据权利要求35所述的半导体基板，其中，所述第一晶体管的第二极的远离所述第三过孔的边缘与所述第一晶体管的第二极的靠近所述第三过孔的边缘之间的距离为dgs，所述第三过孔在所述栅金属层所在平面的孔径为ds，
  39. 根据权利要求38所述的半导体基板，其中，dgs＝ds。
  40. 根据权利要求15所述的半导体基板，其中，所述阵列基板还包括数据线，
    所述数据线用于传输所述数据信号，所述数据线设置在所述层间绝缘层上，所述数据线与所述第一晶体管的第一极和所述第一晶体管的第二极位于同一层。
  41. 根据权利要求16所述的半导体基板，其中，所述阵列基板还包括数据线，
    所述数据线用于传输所述数据信号，所述数据线设置在所述栅绝缘层上，所述数据线与所述第一晶体管的栅极、所述第一晶体管的第一极、所述第一晶体管的第二极位于同一层。
  42. 根据权利要求7所述的半导体基板，其中，所述第三晶体管、所述第四晶体管、所述第一扫描线、所述第二扫描线位于所述第一晶体管的同一侧。
  43. 根据权利要求20所述的半导体基板，其中，所述有源层中被所述第一过孔和/或所述第二过孔暴露的部分为通过等离子体掺杂形成的导体化区 域。
  44. 根据权利要求30所述的半导体基板，其中，所述第一晶体管的第一极和所述第一晶体管的第二极中的一个为所述第一晶体管的漏极，所述第一过孔和所述第二过孔中与所述第一晶体管的漏极相邻的过孔与所述第三过孔为同一个过孔，
    所述第一晶体管的漏极通过所述第三过孔与所述有源层暴露的部分、所述遮光层暴露的部分均连接。
  45. 根据权利要求14所述的半导体基板，其中，所述阵列基板还包括钝化层和平坦化层；
    所述第一晶体管的第一极和所述第一晶体管的第二极中的一个为所述第一晶体管的漏极；
    所述钝化层和所述平坦化层依序层叠设置，并且位于所述第一晶体管的漏极之上；
    所述钝化层和所述平坦化层中具有第五过孔，所述第五过孔暴露所述第一晶体管的漏极。
  46. 根据权利要求45所述的半导体基板，其中，所述第五过孔包括位于所述钝化层与所述平坦化层的交界面的台阶，所述台阶的宽度小于或等于1μm。
  47. 根据权利要求45所述的半导体基板，其中，所述阵列基板还包括遮光层，
    所述遮光层设置在所述衬底基板上，所述缓冲层设置在所述衬底基板上且覆盖所述遮光层，所述遮光层的材料为金属，所述遮光层复用为所述第二晶体管的栅极；
    所述第五过孔在垂直于所述衬底基板的方向上的正投影与所述遮光层中复用为所述第二晶体管的栅极的部分在垂直于所述衬底基板的方向上的正投影至少部分交叠。
  48. 根据权利要求47所述的半导体基板，其中，所述感测电路包括第四晶体管，所述第四晶体管的栅极与第二扫描线连接以接收所述第二扫描信号，所述第四晶体管的第一极与所述驱动电路的第二端连接，所述第四晶体管的第二极与所述感测信号线连接；
    所述遮光层还复用为所述第四晶体管的栅极，并且复用为所述第一电压 端；
    所述遮光层为双层金属结构。
  49. 一种半导体显示装置，包括如权利要求1-48任一项所述的半导体基板。
  50. 一种用于权利要求1-48任一项所述的半导体基板的驱动方法，包括：
    在显示阶段，使所述驱动电路和所述保护电路共同提供所述驱动电流，以驱动所述发光元件发光；
    在感测阶段，使所述感测电路开启以将所述驱动电路的第二端与所述感测信号线连接，并且利用所述保护电路阻止所述感测电路产生的静电流动至所述发光元件。
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