WO2024021201A1 - 车辆的节点地址分配方法、装置、车辆设备及存储介质 - Google Patents

车辆的节点地址分配方法、装置、车辆设备及存储介质 Download PDF

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Publication number
WO2024021201A1
WO2024021201A1 PCT/CN2022/113386 CN2022113386W WO2024021201A1 WO 2024021201 A1 WO2024021201 A1 WO 2024021201A1 CN 2022113386 W CN2022113386 W CN 2022113386W WO 2024021201 A1 WO2024021201 A1 WO 2024021201A1
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WO
WIPO (PCT)
Prior art keywords
node
address
addressing
addressing instruction
vehicle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2022/113386
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English (en)
French (fr)
Inventor
董武豪
刘坤
吴江才
康志文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhejiang Geely Holding Group Co Ltd
Geely Automobile Research Institute Ningbo Co Ltd
Original Assignee
Zhejiang Geely Holding Group Co Ltd
Geely Automobile Research Institute Ningbo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhejiang Geely Holding Group Co Ltd, Geely Automobile Research Institute Ningbo Co Ltd filed Critical Zhejiang Geely Holding Group Co Ltd
Priority to KR1020247042903A priority Critical patent/KR20250012656A/ko
Priority to JP2024568636A priority patent/JP7789960B2/ja
Priority to EP22952643.9A priority patent/EP4509364A4/en
Publication of WO2024021201A1 publication Critical patent/WO2024021201A1/zh
Priority to US19/015,701 priority patent/US20250150431A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L61/00—Network arrangements, protocols or services for addressing or naming
    • H04L61/50—Address allocation
    • H04L61/5038—Address allocation for local use, e.g. in LAN or USB networks, or in a controller area network [CAN]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60Q—ARRANGEMENT OF SIGNALLING OR LIGHTING DEVICES, THE MOUNTING OR SUPPORTING THEREOF OR CIRCUITS THEREFOR, FOR VEHICLES IN GENERAL
    • B60Q3/00—Arrangement of lighting devices for vehicle interiors; Lighting devices specially adapted for vehicle interiors
    • B60Q3/80—Circuits; Control arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40169—Flexible bus arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/12—Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60Q—ARRANGEMENT OF SIGNALLING OR LIGHTING DEVICES, THE MOUNTING OR SUPPORTING THEREOF OR CIRCUITS THEREFOR, FOR VEHICLES IN GENERAL
    • B60Q3/00—Arrangement of lighting devices for vehicle interiors; Lighting devices specially adapted for vehicle interiors
    • B60Q3/20—Arrangement of lighting devices for vehicle interiors; Lighting devices specially adapted for vehicle interiors for lighting specific fittings of passenger or driving compartments; mounted on specific fittings of passenger or driving compartments
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40208—Bus networks characterized by the use of a particular bus standard
    • H04L2012/40234—Local Interconnect Network LIN
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40267—Bus for use in transportation systems
    • H04L2012/40273—Bus for use in transportation systems the transportation system being a vehicle

Definitions

  • the present application generally relates to the field of vehicles, and specifically relates to a node address allocation method, device, vehicle equipment and storage medium for a vehicle.
  • Vehicle-mounted interior atmosphere lights are increasingly installed in home cars, and the use of multi-color RGB atmosphere lights is becoming more and more common.
  • the number of ambient lights arranged in the car is also gradually increasing.
  • Individual control of the ambient lights in certain areas requires assigning an address to each ambient light, and then individual control of each ambient light can be achieved based on the address of the ambient light.
  • this application provides a node address allocation method for vehicles, including:
  • the node set includes a plurality of nodes connected to the first bus of the vehicle;
  • the node is assigned an address according to its address.
  • obtaining the node whose address is currently to be allocated from the node set according to the first addressing mode includes:
  • the node to be processed is used as the node to which the current address is to be allocated;
  • the node to be processed is used as the node to which the current address is to be allocated.
  • the first addressing mode is one of the LSM addressing mode and the BSM addressing mode.
  • the method is based on the number of addressing instruction frames in the addressing instruction sequence, the address carried by the addressing instruction frame currently issued to the node, and the addressing instruction currently issued to the node.
  • the frame number of the frame is used to obtain the address of the node, including:
  • the address of the node is obtained according to the second difference.
  • the node is assigned an address according to its address.
  • the second addressing mode is one of the LSM addressing mode and the BSM addressing mode, and the second addressing mode is different from the first addressing mode.
  • this application provides a vehicle node address allocation device, including:
  • a node determination module configured to obtain the node currently to be assigned an address from a node set according to the first addressing mode, wherein the node set includes multiple nodes connected to the first bus of the vehicle;
  • the address determination module is configured to determine the address based on the number of addressing instruction frames in the addressing instruction sequence, the address carried by the addressing instruction frame currently issued to the node, and the address of the addressing instruction frame currently issued to the node. Frame number, get the address of the node;
  • An allocation module configured to allocate addresses to the nodes according to the addresses of the nodes.
  • address determination module is specifically used for:
  • the address of the node is obtained according to the second difference.
  • the present application provides a vehicle, which includes a node address allocation device of the vehicle.
  • the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor.
  • the processor executes the program, the embodiments of the present application are implemented.
  • the node address allocation method for the vehicle described in any one of the above.
  • the present application provides a computer-readable storage medium on which a computer program is stored.
  • the program is executed by a processor, the vehicle node address allocation method described in any one of the embodiments of the present application is implemented.
  • the vehicle node address allocation method based on the vehicle node address allocation method, device, vehicle equipment and storage medium of the present invention, by obtaining the number of addressing instruction frames in the addressing instruction sequence and the number of addressing instructions carried by the addressing instruction frame currently issued to the node.
  • the address of the node is obtained by the relationship between the address and the frame of the addressing instruction frame currently issued to the node. This method can achieve precise control over the allocation of node addresses, thereby meeting preset requirements.
  • Figure 1 is a flow chart of a vehicle node address allocation method provided by an embodiment of the present application
  • Figure 2 is an internal structure diagram of the MLX81 series chip node provided by the embodiment of the present application.
  • Figure 3 is a node connection block diagram of the BSM addressing mode provided by the embodiment of the present application.
  • Figure 4 is the addressing result of the BSM addressing mode provided by the embodiment of the present application.
  • Figure 5 is an internal structure diagram of the Indie Realplum chip node provided by the embodiment of this application.
  • Figure 6 is a node connection block diagram of the LSM addressing mode provided by the embodiment of the present application.
  • Figure 7 is the addressing result of the LSM addressing method provided by the embodiment of the present application.
  • Figure 8 is a structural block diagram of a vehicle node address allocation device provided by an embodiment of the present application.
  • Figure 9 is an internal structure diagram of an electronic device provided by an embodiment of the present application.
  • This application generally relates to the field of vehicles.
  • the following embodiments of this application exemplify a node address allocation method for vehicles.
  • This application provides a vehicle node address allocation method, including:
  • the node address to be allocated is obtained from the set of all nodes according to the selected addressing mode.
  • the set of nodes is all nodes connected by the bus of the current vehicle. For example, when the first bus of this vehicle is connected to 3 nodes, the node address to be allocated should also be 3.
  • the address of the node can be 0x10, 0x0F, 0x0E, and the total number of nodes can be represented by Max NAD.
  • obtaining the node whose address is currently to be allocated from the node set according to the first addressing mode includes:
  • the node to be processed is used as the node to which the current address is to be allocated;
  • the node to be processed is used as the node to which the current address is to be allocated.
  • Max NAD is first sent to allocate the largest NAD, and the allocation is in order from large to small, that is, the node search is performed from the first node to the last node in the set. If the node has not been assigned an address, this node will be left pending.
  • the processed node is the node that currently needs to be assigned an address. Or, search from the tail node in the set to the first node. If the node has not been assigned an address, the node to be processed is regarded as the node that currently needs to be assigned an address.
  • the BSM (Bus Shunt Method) addressing method uses a pull-up current source to determine the current value difference to identify the first LIN node at the far end, and responds to the NAD instructions to be allocated from far to near, that is, from the middle of the set
  • the tail node performs node search to the first node.
  • Indie Realplum chips use the LSM (LIN Switch Method) addressing method, which increases the number of slave nodes online by controlling the opening and closing of the LIN Switch. Starting from the first LIN node in the near segment, the back-end slave nodes are connected one by one from near to far. Respond to the NAD allocation instruction, that is, perform a node search from the first node to the last node in the set.
  • the addressing instructions at this time are shown in Table 1.
  • the first addressing mode is one of an LSM addressing mode and a BSM addressing mode.
  • existing automatic addressing mostly uses Melexis MLX81 series chips or Indie Realplum chips for communication and control through LIN.
  • the MLX81 series of chips adopts the BSM (Bus Shunt Method) addressing method, which uses the pull-up current source to determine the difference in current values to identify the first LIN node at the far end, and the NAD (Node address, node address) from far to near.
  • BSM Bus Shunt Method
  • the Indie Realplum chip uses the LSM (LIN Switch Method, LIN bus switching method) addressing method, that is, by controlling the opening and closing of the LIN Switch to increase the number of slave nodes online, starting from the first LIN node at the near end, Connect the back-end slave nodes one by one from near to far to respond to NAD allocation instructions.
  • LSM LIN Switch Method, LIN bus switching method
  • the pull-up current source is turned on
  • the constant current source is turned on;
  • the Indie Realplum chip uses the LSM addressing method.
  • the internal structure of the LIN node of the chip is shown in Figure 5.
  • the chip LSM addressing node connection diagram is shown in Figure 6.
  • the next LIN node is connected through the LIN switch inside the node, and then By judging whether the NAD is the initial value to identify whether an address has been assigned, and identifying nodes that have not been assigned NAD to overwrite the new NAD, the LIN bus can automatically assign addresses.
  • the steps are as follows:
  • All nodes turn off the LIN switch, and the first near-end node is online. After receiving the NAD command and performing new NAD coverage, this node closes the LIN switch and connects the second node;
  • the first node After receiving the NAD allocation instruction, the first node has stored the new NAD, the second node is the initial NAD, and the new NAD is covered. This node closes the LIN switch and connects the third node;
  • the address carried by the addressing instruction frame currently issued to the node, and the number of frames of the addressing instruction frame currently issued to the node obtain The address of the node.
  • the address of the node is obtained according to the number of addressing instruction frames in the current addressing sequence, the address carried by the addressing instruction, and the current number of addressing instruction frames.
  • the number of addresses can be expressed as Max NAD.
  • NAD is 0xX (Max NAD)
  • all nodes will store NAD as 0xX, where X is the number of addressing instruction frames in the addressing instruction sequence, and disconnect the LIN switch; all The LIN switch is disconnected.
  • NAD is 0x0(X-1).
  • This node stores NAD as 0x01 ⁇ Max NAD-(X-1) ⁇ .
  • close the LIN switch to connect the second node; the first node LIN switch is closed, and the first and second node at the near end are online at this time.
  • the NAD of the first node is 0x01
  • the NAD of the second node is 0xX.
  • NAD is 0x(X-2)
  • the second node closes the LIN switch and connects to the third node;
  • the LIN switch of the first and second nodes is closed.
  • the three near-end nodes are online.
  • the NAD of the first node is 0x01
  • the NAD of the second node is 0x02
  • the NAD of the third node is 0xX.
  • the command NAD is 0x(X-3), and the NAD of the node with NAD 0xX is corrected to 0x03 ⁇ Max NAD-(X-3) ⁇ .
  • the second node closes the LIN switch; until it is assigned to the last node, the remote node The two nodes are connected online.
  • the NAD is 0x01.
  • the NAD of the node with NAD 0xX is corrected to 0x(X-1).
  • this node closes the LIN switch.
  • the first remote node is online. This node NAD has been saved as 0xX.
  • the method is based on the number of addressing instruction frames in the addressing instruction sequence, the address carried by the addressing instruction frame currently issued to the node, and the addressing instruction currently issued to the node.
  • the frame number of the frame is used to obtain the address of the node, including:
  • the address of the node is obtained according to the second difference.
  • the calculated difference is 2, and the current difference is the first Difference;
  • the current difference is the second difference, and then based on the second difference, the address of the node is obtained: NAD 0x03 .
  • the node allocates addresses based on the node address, and the obtained addresses of each node are as shown in Figure 4, thereby achieving the same nodes in LSM and BSM addressing modes, thereby achieving compatible control.
  • the method further includes: obtaining the node whose address is currently to be allocated from the node set according to the second addressing mode;
  • the node is assigned an address according to its address.
  • the second addressing mode is used to obtain the node with the currently assigned address from the node set, and the address carried by the addressing instruction frame currently issued to the node is directly used as the node address. For example, if the node with the current address to be allocated is 3, the obtained node address is: 0x03.
  • the second addressing mode is one of an LSM addressing mode and a BSM addressing mode, and the second addressing mode is different from the first addressing mode.
  • the second addressing mode is the BSM addressing mode
  • the first addressing mode is the LSM addressing mode
  • the vehicle node address allocation method of the present invention by obtaining the number of addressing instruction frames in the addressing instruction sequence, the address carried by the addressing instruction frame currently issued to the node, and the address currently issued to the node.
  • the relationship number of the addressing instruction frame is used to obtain the address of the node. This method can achieve precise control over the allocation of node addresses to meet preset requirements.
  • the node address allocation device 200 for a vehicle includes: a node determination module 210 , an address determination module 220 , and an allocation module 230 , wherein:
  • the node determination module 210 is configured to obtain the node currently to be assigned an address from a node set according to the first addressing mode, where the node set includes multiple nodes connected to the first bus of the vehicle;
  • the address determination module 220 is configured to determine the address based on the number of addressing instruction frames in the addressing instruction sequence, the address carried by the addressing instruction frame currently issued to the node, and the addressing instruction frame currently issued to the node. The number of frames, get the address of the node;
  • the allocation module 230 is configured to allocate addresses to the nodes according to the addresses of the nodes.
  • the address determination module 220 is specifically used to:
  • the address of the node is obtained according to the second difference.
  • the vehicle node address allocation device of the present invention by obtaining the number of addressing instruction frames in the addressing instruction sequence, the address carried by the addressing instruction frame currently issued to the node, and the number of addressing instruction frames currently issued to the node.
  • the relationship number of the addressing instruction frame is used to obtain the address of the node. This method can achieve precise control over the allocation of node addresses to meet preset requirements.
  • each block in the flowchart or block diagrams may represent a module, segment, or portion of code that contains one or more components that implement the specified logical function(s). executable instructions.
  • the functions noted in the block may occur out of the order noted in the figures. For example, two connected blocks may actually execute substantially in parallel, and they may sometimes execute in reverse order, depending on the functionality involved.
  • each block of the block diagram and/or flowchart illustration, and combinations of blocks in the block diagram and/or flowchart illustration can be implemented by specialized hardware-based systems that perform the specified functions or operating instructions. Implemented, or may be implemented using a combination of dedicated hardware and computer instructions.
  • the above description is only a preferred embodiment of the present application and an explanation of the technical principles used.
  • Those skilled in the art should understand that the disclosure scope involved in this application is not limited to technical solutions composed of specific combinations of the above technical features, but should also cover solutions consisting of the above technical features or without departing from the foregoing disclosed concept.
  • Other technical solutions formed by any combination of their equivalent features For example, a technical solution is formed by replacing the above features with technical features with similar functions disclosed in this application (but not limited to).
  • the present application provides a vehicle that adopts a node address allocation device 200 of the vehicle.
  • the node address allocation device 200 of the vehicle includes: a node determination module 210 for selecting from a node according to a first addressing mode. Obtain the node whose address is currently to be allocated in the node set, wherein the node set includes multiple nodes connected to the first bus of the vehicle;
  • the address determination module 220 is configured to determine the address based on the number of addressing instruction frames in the addressing instruction sequence, the address carried by the addressing instruction frame currently issued to the node, and the addressing instruction frame currently issued to the node. The number of frames, get the address of the node;
  • the allocation module 230 is configured to allocate addresses to the nodes according to the addresses of the nodes.
  • the address determination module 220 is specifically used to:
  • the address of the node is obtained according to the second difference.
  • the vehicle of the present invention by obtaining the number of addressing instruction frames in the addressing instruction sequence, the address carried by the addressing instruction frame currently issued to the node, and the address carried by the addressing instruction frame currently issued to the node.
  • the relationship number is used to obtain the address of the node. This method can achieve precise control over the allocation of node addresses to meet preset requirements.
  • an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor.
  • the electronic device executes the computer program, it implements the following steps: according to the first addressing
  • the method obtains the node whose address is currently to be allocated from a node set, wherein the node set includes multiple nodes connected to the first bus of the vehicle; according to the number of addressing instruction frames in the addressing instruction sequence, the number of addresses currently issued to the The address of the node is obtained by using the address carried by the addressing instruction frame of the node and the frame number of the addressing instruction frame currently issued to the node; and allocating addresses to the node according to the address of the node.
  • the processor when the processor executes the computer program, the processor also implements the following steps: sequentially perform node search from the first node to the last node in the node set; when the first node to be processed without address allocation is found, Use the node to be processed as the node currently to be assigned an address; or, perform a node search from the tail node in the node set to the first node; when the first node to be processed that has not been assigned an address is found. , taking the node to be processed as the node to which the current address is to be allocated.
  • the processor when the processor executes the computer program, the processor further implements the following steps: obtaining the number of addressing instruction frames in the addressing instruction sequence and the number of addressing instruction frames currently issued to the node. the first difference between; obtain the second difference between the address carried by the addressing instruction frame currently issued to the node and the first difference; obtain the The address of the node.
  • the processor when the processor executes the computer program, the following steps are also implemented: obtaining the node whose address is currently to be allocated from the node set according to the second addressing mode; and according to the addressing instruction currently issued to the node in the addressing instruction sequence.
  • the address carried by the address instruction frame is obtained to obtain the address of the node; the address is assigned to the node according to the address of the node.
  • the electronic device may be a terminal device, and its internal structure diagram may be as shown in Figure 9.
  • the terminal device includes a processor, memory, communication interface, display screen and input device connected through a system bus.
  • the processor of the terminal device is used to provide computing and control capabilities.
  • the memory of the terminal device includes computer-readable storage media and internal memory.
  • the computer-readable storage medium stores an operating system and a computer program. This internal memory provides an environment for the execution of operating systems and computer programs in computer-readable storage media.
  • the communication interface of the terminal device is used for wired or wireless communication with external terminals.
  • the wireless mode can be implemented through WIFI, operator network, near field communication (NFC) or other technologies.
  • the computer program implements an application opening method when executed by the processor.
  • the display screen of the terminal device can be a liquid crystal display or a communication ink display screen.
  • the input device of the terminal device can be a touch layer covered on the display screen, or it can be a button, trackball or touch pad provided on the shell of the terminal device. , it can also be an external keyboard, trackpad or mouse, etc.
  • the electronic device of the present invention by obtaining the number of addressing instruction frames in the addressing instruction sequence, the address carried by the addressing instruction frame currently issued to the node, and the addressing instruction frame currently issued to the node The relationship number of the node is obtained. This method can achieve precise control over the allocation of node addresses to meet the preset requirements.
  • a computer-readable storage medium has a computer program stored thereon.
  • the computer program When the computer program is executed by a processor, the following steps are implemented: Obtain the node whose address is currently to be allocated from the node set according to the first addressing mode, Wherein, the node set includes multiple nodes connected to the first bus of the vehicle; according to the number of addressing instruction frames in the addressing instruction sequence, the address carried by the addressing instruction frame currently issued to the node, and the The address of the node is obtained based on the number of addressing instruction frames currently issued to the node; and address allocation is performed on the node based on the address of the node.
  • the processor when the processor executes the computer program, the processor also implements the following steps: sequentially perform node search from the first node to the last node in the node set; when the first node to be processed without address allocation is found, Use the node to be processed as the node currently to be assigned an address; or, perform a node search from the tail node in the node set to the first node; when the first node to be processed that has not been assigned an address is found. , taking the node to be processed as the node to which the current address is to be allocated.
  • the processor when the processor executes the computer program, the processor further implements the following steps: obtaining the number of addressing instruction frames in the addressing instruction sequence and the number of addressing instruction frames currently issued to the node. the first difference between; obtain the second difference between the address carried by the addressing instruction frame currently issued to the node and the first difference; obtain the The address of the node.
  • the processor when the processor executes the computer program, the following steps are also implemented: obtaining the node whose address is currently to be allocated from the node set according to the second addressing mode; and according to the addressing instruction currently issued to the node in the addressing instruction sequence.
  • the address carried by the address instruction frame is obtained to obtain the address of the node; the address is assigned to the node according to the address of the node.
  • the computer-readable storage medium of the present invention by obtaining the number of addressing instruction frames in the addressing instruction sequence, the address carried by the addressing instruction frame currently issued to the node, and the address carried by the addressing instruction frame currently issued to the node.
  • the address of the node is obtained by using the relationship number of the frame of the address instruction frame. This method can achieve precise control over the allocation of node addresses, thereby meeting the preset requirements.
  • Computer-readable memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc.
  • Volatile memory may include random access memory (Random Access Memory, RAM) or external cache memory.
  • RAM Random Access Memory
  • SRAM Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • “plurality” means two or more than two, unless otherwise explicitly and specifically limited.

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  • Arrangements Of Lighting Devices For Vehicle Interiors, Mounting And Supporting Thereof, Circuits Therefore (AREA)

Abstract

一种车辆的节点地址分配方法、装置、车辆设备及存储介质，其中，车辆的节点地址分配方法，包括：根据第一寻址方式从节点集合中获得当前待分配地址的节点，其中，所述节点集合包括与车辆的第一总线相连的多个节点（S101）；根据寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址以及所述当前下发给所述节点的寻址指令帧的帧数，得到所述节点的地址（S102）；根据所述节点的地址对所述节点进行地址分配（S103）。通过该方案进行节点分配，可以对节点地址的分配实现精确控制，进而满足预设需求。

Description

车辆的节点地址分配方法、装置、车辆设备及存储介质 技术领域
本申请一般涉及车辆领域，具体涉及一种车辆的节点地址分配方法、装置、车辆设备及存储介质。
背景技术
车载内饰氛围灯在家用汽车的配置率日益增高，多色RGB氛围灯的使用也越来越普遍，为了烘托整车的氛围感，车内布置的氛围灯数量也逐渐增加，为了实现对不同部位的氛围灯的单独控制，需要为每个氛围灯分配地址，进而可以根据氛围灯的地址实现每个氛围灯的单独控制。
现有技术中，由于氛围灯采用的芯片种类差别，氛围灯的地址分配手段即节点寻址方法的寻址原理也存在差异。例如采用MLX 81系列芯片时得到的节点地址结果和采用Indie Realplum芯片时得到的节点地址结果并不相同，进而不能实现节点控制方案的兼容。所以，现有方案需要对不同芯片的寻址方式开发多套方案进行适配，无法实现对需求的精确控制。
发明内容
鉴于现有技术中的上述缺陷或不足，期望提供一种车辆的节点地址分配方法、装置、车辆设备及存储介质。
一方面，本申请提供了一种车辆的节点地址分配方法，包括：
根据第一寻址方式从节点集合中获得当前待分配地址的节点，其中，所述节点集合包括与车辆的第一总线相连的多个节点；
根据寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址以及所述当前下发给所述节点的寻址指令帧的帧数，得到所述节点的地址；
根据所述节点的地址对所述节点进行地址分配。
进一步的，所述根据第一寻址方式从节点集合中获得当前待分配地址的节点，包括：
依次从所述节点集合中的首节点向尾结点进行节点查找；
当查找到首个未进行地址分配的待处理节点时，将所述待处理节点作为所述当前待分配地址的节点；
或者，
依次从所述节点集合中的尾节点向首结点进行节点查找；
当查找到首个未进行地址分配的待处理节点时，将所述待处理节点作为所述当前待分配地址的节点。
具体的，所述第一寻址方式为LSM寻址方式和BSM寻址方式中的一个。
在一些实施例中，所述根据寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址以及所述当前下发给所述节点的寻址指令帧的帧数，得到所述节点的地址，包括：
获得所述寻址指令序列中寻址指令帧的数量与所述当前下发给所述节点的寻址指令帧的帧数之间的第一差值；
获得所述当前下发给所述节点的寻址指令帧携带的地址与所述第一差值之间的第二差值；
根据所述第二差值得到所述节点的地址。
进一步的，还包括：
根据第二寻址方式从节点集合中获得当前待分配地址的节点；
根据寻址指令序列中当前下发给所述节点的寻址指令帧携带的地址，得到所述节点的地址；
根据所述节点的地址对所述节点进行地址分配。
具体的，所述第二寻址方式为LSM寻址方式和BSM寻址方式中的一个，且所述第二寻址方式与所述第一寻址方式不同。
第二方面，本申请提供了一种车辆的节点地址分配装置，包括：
节点确定模块，用于根据第一寻址方式从节点集合中获得当前待分配地址的节点，其中，所述节点集合包括与车辆的第一总线相连的多个节点；
地址确定模块，用于根据寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址以及所述当前下发给所述节点的寻址指令帧的帧数，得到所述节点的地址；
分配模块，用于根据所述节点的地址对所述节点进行地址分配。
进一步的，所述地址确定模块具体用于：
获得所述寻址指令序列中寻址指令帧的数量与所述当前下发给所述节点的寻址指令帧的帧数之间的第一差值；
获得所述当前下发给所述节点的寻址指令帧携带的地址与所述第一差值之间的第二差值；
根据所述第二差值得到所述节点的地址。
第三方面，本申请提供了一种车辆，该车辆包括车辆的节点地址分配装置。
第四方面，本申请提供了一种电子设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述程序时，实现本申请实施例中任一项所述的车辆的节点地址分配方法。
第五方面，本申请提供了一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现本申请实施例中任一所述的车辆的节点地址分配方法。
综上，基于本发明的车辆的节点地址分配方法、装置、车辆设备及存储介质，通过获取寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址、当前下发给节点的寻址指令帧的帧的关系数得到该节点的地址，该方法可以对节点地址的分配实现精确控制，进而满足预设需求。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显：
图1为本申请的实施例提供的一种车辆的节点地址分配方法的流程图；
图2为本申请的实施例提供的MLX81系列芯片节点内部结构图；
图3为本申请的实施例提供的BSM寻址方式的节点连接框图；
图4为本申请的实施例提供的BSM寻址方式的寻址结果；
图5为本申请的实施例提供的Indie Realplum芯片节点内部结构图；
图6为本申请的实施例提供的LSM寻址方式的节点连接框图；
图7为本申请的实施例提供的LSM寻址方式的寻址结果；
图8为本申请的实施例提供的车辆的节点地址分配装置的结构框图；
图9为本申请的实施例提供的电子设备的内部结构图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关发明，而非对该发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与发明相关的部分。
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
本申请一般涉及车辆领域中，本申请以下实施例示例性阐述车辆的节点地址分配方法。
详见图1，本申请提供了一种车辆的节点地址分配方法，包括：
S101，根据第一寻址方式从节点集合中获得当前待分配地址的节点，其中，所述节点 集合包括与车辆的第一总线相连的多个节点。
具体的，根据选择的寻址方式从所有节点的集合中获取待分配的节点地址，节点的集合为当前车辆的总线连接的所有节点。举例说明，当此车辆的第一总线连接3个节点时，待分配的节点地址也应当为3，该节点的地址可以为0x10、0x0F、0x0E，节点总数可以通过Max NAD表示。
在一些实施例中，所述根据第一寻址方式从节点集合中获得当前待分配地址的节点，包括：
依次从所述节点集合中的首节点向尾结点进行节点查找；
当查找到首个未进行地址分配的待处理节点时，将所述待处理节点作为所述当前待分配地址的节点；
或者，
依次从所述节点集合中的尾节点向首结点进行节点查找；
当查找到首个未进行地址分配的待处理节点时，将所述待处理节点作为所述当前待分配地址的节点。
具体的，先发送Max NAD来分配最大的NAD，并由大到小的顺序分配，即从集合的中的首节点向尾结点进行节点查找，若该节点未被分配地址，则将此待处理的节点作为当前需要分配地址的节点。或，从集合中的尾结点向首结点进行查找，若该节点未被分配地址，则将此待处理的节点作为当前需要分配地址的节点。
举例说明，BSM(Bus Shunt Method)寻址方式，即通过上拉电流源判断电流值差异来识别远端第一个LIN节点，由远及近对NAD待分配指令进行响应，即从集合的中的尾结点向首结点进行节点查找。Indie Realplum芯片则采用LSM(LIN Switch Method)寻址方式，即通过控制LIN Switch的开闭增加从节点在线数量，从近段第一个LIN节点开始，由近及远逐个接通后端从节点进行NAD分配指令响应，即从集合的中的首节点向尾结点进行节点查找，此时的寻址指令如表1所示。
表1
Figure PCTCN2022113386-appb-000001
Figure PCTCN2022113386-appb-000002
在一些实施例中，所述第一寻址方式为LSM寻址方式和BSM寻址方式中的一个。
具体的，举例说明，现有的自动寻址多采用Melexis MLX81系列芯片或Indie Realplum芯片通过LIN进行通讯进行控制。MLX81系列芯片采用BSM(Bus Shunt Method，总线分流法)寻址方式，即通过上拉电流源判断电流值差异来识别远端第一个LIN节点，由远及近对NAD(Node address，节点地址)分配指令进行响应；Indie Realplum芯片则采用LSM(LIN Switch Method，LIN总线切换方法)寻址方式，即通过控制LIN Switch的开闭增加从节点在线数量，从近端第一个LIN节点开始，由近及远逐个接通后端从节点进行NAD分配指令响应。
MLX81系列芯片内部结构如图2所示，通过闭合恒流源和上拉电流源来实现电流检测，可以实现LIN总线BSM自动分配地址，主要步骤如下：
1.将上拉电流源(Pull up current generator)和恒流源(Rslave)关闭；
2.测试电流值，测试电流偏移量；
3.上拉电流源开启；
4.测试此时电流值，作为预选择测量，电流值小于预设电流值的节点进入最终测量，该预设电流值为：1.2mA；
5.恒流源打开；
6.测试此时电流值，为最终测量值；
7.关闭上拉电流源和恒流源
此时，所有LIN节点通过菊花链形式串行连接，连接方式如图3所示。在测试电流值时，上拉电源打开，进行预测量，测试电流值如果大于预设电流值，则该节点不是最后一个节点，需要关闭上拉电流源。当电流值小于预设电流值的节点进入最终测量，然后打开恒流源测试，测试此时电流值，判断电流是否大于预设电流值，当此时电流值小于预设值时则为最后一个节点，进行NAD地址分配。该预设电流值为：1.2mA。采用BSM方式进行寻址后，节点地址如图4所示。
Indie Realplum芯片采用LSM的寻址方式，该芯片LIN节点的内部结构如图5所示，芯片LSM寻址节点连接图如图6所示，通过节点内部的LIN switch接通下一个LIN节点，然后通过判断NAD是否为初始值来识别是否分配过地址，识别出未分配过NAD的节点进行新NAD的覆盖，可以实现LIN总线自动分配地址，步骤如下：
1.所有节点断开LIN switch，近端第一个节点在线，在收到NAD指令后，进行新NAD覆盖后，此节点闭合LIN switch接通第二个节点；
2.收到NAD分配指令后，第一个节点已存储新的NAD，第二个节点为初始NAD，进行新NAD覆盖，此节点闭合LIN switch接通第三个节点；
3.为所有节点分配NAD。采用LSM的寻址方式进行寻址后，节点地址如图7所示。
S102，根据寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址以及所述当前下发给所述节点的寻址指令帧的帧数，得到所述节点的地址。
具体的，根据当前寻址序列中的寻址指令帧数量、该寻址指令携带的地址和当前的寻址指令帧数得到节点的地址。寻址数量可以用Max NAD表示。
举例说明，收到第一帧NAD分配指令NAD为0xX(Max NAD)，所有节点将NAD存为0xX，在此X为寻址指令序列中寻址指令帧的数量，并断开LIN switch；所有LIN switch断开，此时仅近端第一个节点在线，收到第二帧NAD分配指令NAD为0x0(X-1)，此节点将NAD存为0x01{Max NAD-(X-1)}，并闭合LIN switch,连接第二个节点；第一个节点LIN switch闭合，此时近端第一个第二个节点在线，第一个节点NAD为0x01，第二个节点NAD为0xX,在收到NAD分配指令NAD为0x(X-2)，将NAD为0xX的节点NAD修正为0x02{Max NAD-(X-2)},同时第二个节点闭合LIN switch，连接第三个节点；第一个、第二个节点LIN switch闭合，此时近端三个节点在线，第一个节点NAD为0x01，第二个节点NAD为0x02,第三个节点NAD为0xX,在收到NAD分配指令NAD为0x(X-3)，将NAD为0xX的节点NAD修正为0x03{Max NAD-(X-3)},同时第二个节点闭合LIN switch；直至分配至最后一个节点，远端第二个节点接通在线，在收到NAD分配指令NAD为0x01，将NAD为0xX的节点NAD修正为0x(X-1)，同时此节点闭合LIN switch，远端第一个节点在线，此节点NAD已存为0xX。
在一些实施例中，所述根据寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址以及所述当前下发给所述节点的寻址指令帧的帧数，得到所述节点的地址，包括：
获得所述寻址指令序列中寻址指令帧的数量与所述当前下发给所述节点的寻址指令帧的帧数之间的第一差值；
获得所述当前下发给所述节点的寻址指令帧携带的地址与所述第一差值之间的第二差 值；
根据所述第二差值得到所述节点的地址。
具体的，举例说明，当寻址指令序列中寻址指令帧的数量为5，当前下发给所述节点的寻址指令帧的帧数3，计算差值为2，当前差值为第一差值；根据寻址指令帧携带的地址5与第一差值2，计算差值为3，当前差值为第二差值，进而根据第二差值，获得该节点的地址为：NAD 0x03。
S103，根据所述节点的地址对所述节点进行地址分配。
具体的，基于该节点地址节点进行地址的分配，得到的各个节点的地址如图4所示，从而实现LSM和BSM寻址方式的节点相同，进而实现兼容控制。
在一些实施例中，还包括：根据第二寻址方式从节点集合中获得当前待分配地址的节点；
根据寻址指令序列中当前下发给所述节点的寻址指令帧携带的地址，得到所述节点的地址；
根据所述节点的地址对所述节点进行地址分配。
具体的，采用第二寻址方式从节点的集合中获取当前分配的地址的节点，直接根据指当前下发给所述节点的寻址指令帧携带的地址，作为节点的地址。举例说明，若当前待分配的地址的节点为3，则获得的节点的地址为：0x03。
在一些实施例中，所述第二寻址方式为LSM寻址方式和BSM寻址方式中的一个，且所述第二寻址方式与所述第一寻址方式不同。
具体的，当第一寻址方式为LSM寻址方式时，第二寻址方式为BSM寻址方式；当第二寻址方式为BSM寻址方式时，第一寻址方式为LSM寻址方式，采用第一寻址方式和第二寻址方式的对应，从而得到两种寻址方式得到的NAD一致，从而实现兼容性控制。
综上，基于本发明的车辆的节点地址分配方法，通过获取寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址、当前下发给节点的寻址指令帧的关系数得到该节点的地址，该方法可以对节点地址的分配实现精确控制，进而满足预设需求。
进一步参考图8，示出了根据本申请实施例的车辆的节点地址分配装置的示意图，车辆的节点地址分配装置200包括：节点确定模块210、地址确定模块220、分配模块230，其中：
节点确定模块210，用于根据第一寻址方式从节点集合中获得当前待分配地址的节点，其中，所述节点集合包括与车辆的第一总线相连的多个节点；
地址确定模块220，用于根据寻址指令序列中寻址指令帧的数量、当前下发给所述节点 的寻址指令帧携带的地址以及所述当前下发给所述节点的寻址指令帧的帧数，得到所述节点的地址；
分配模块230，用于根据所述节点的地址对所述节点进行地址分配。
在一些实施例中，所述地址确定模块220具体用于：
获得所述寻址指令序列中寻址指令帧的数量与所述当前下发给所述节点的寻址指令帧的帧数之间的第一差值；
获得所述当前下发给所述节点的寻址指令帧携带的地址与所述第一差值之间的第二差值；
根据所述第二差值得到所述节点的地址。
综上，基于本发明的车辆的节点地址分配装置，通过获取寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址、当前下发给节点的寻址指令帧的关系数得到该节点的地址，该方法可以对节点地址的分配实现精确控制，进而满足预设需求。
在上文详细描述中提及的若干模块或者单元，这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
附图中的流程图和框图，图示了按照本申请各种实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作指令。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段、或代码的一部分，前述模块、程序段、或代码的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。也应当注意，在有些作为替换的实现中，方框中所标注的功能也可以不同于附图中所标注的顺序发生。例如，两个连接表示的方框实际上可以基本并行地执行，他们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合，可以用执行规定的功能或操作指令的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本申请中所涉及的公开范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离前述公开构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其他技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。
在一个实施例中，本申请提供了一种车辆，该车辆采用车辆的节点地址分配装置200，该车辆的节点地址分配装置200，包括：节点确定模块210，用于根据第一寻址方式从节点 集合中获得当前待分配地址的节点，其中，所述节点集合包括与车辆的第一总线相连的多个节点；
地址确定模块220，用于根据寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址以及所述当前下发给所述节点的寻址指令帧的帧数，得到所述节点的地址；
分配模块230，用于根据所述节点的地址对所述节点进行地址分配。
在一些实施例中，所述地址确定模块220具体用于：
获得所述寻址指令序列中寻址指令帧的数量与所述当前下发给所述节点的寻址指令帧的帧数之间的第一差值；
获得所述当前下发给所述节点的寻址指令帧携带的地址与所述第一差值之间的第二差值；
根据所述第二差值得到所述节点的地址。
综上，基于本发明的车辆，通过获取寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址、当前下发给节点的寻址指令帧的关系数得到该节点的地址，该方法可以对节点地址的分配实现精确控制，进而满足预设需求。
在一个实施例中，提供了一种电子设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，该电子设备执行计算机程序时实现以下步骤：根据第一寻址方式从节点集合中获得当前待分配地址的节点，其中，所述节点集合包括与车辆的第一总线相连的多个节点；根据寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址以及所述当前下发给所述节点的寻址指令帧的帧数，得到所述节点的地址；根据所述节点的地址对所述节点进行地址分配。
在一个实施例中，处理器执行计算机程序时还实现以下步骤：依次从所述节点集合中的首节点向尾结点进行节点查找；当查找到首个未进行地址分配的待处理节点时，将所述待处理节点作为所述当前待分配地址的节点；或者，依次从所述节点集合中的尾节点向首结点进行节点查找；当查找到首个未进行地址分配的待处理节点时，将所述待处理节点作为所述当前待分配地址的节点。
在一个实施例中，处理器执行计算机程序时还实现以下步骤：获得所述寻址指令序列中寻址指令帧的数量与所述当前下发给所述节点的寻址指令帧的帧数之间的第一差值；获得所述当前下发给所述节点的寻址指令帧携带的地址与所述第一差值之间的第二差值；根据所述第二差值得到所述节点的地址。
在一个实施例中，处理器执行计算机程序时还实现以下步骤：根据第二寻址方式从节点集合中获得当前待分配地址的节点；根据寻址指令序列中当前下发给所述节点的寻址指 令帧携带的地址，得到所述节点的地址；根据所述节点的地址对所述节点进行地址分配。
该电子设备可以是终端设备，其内部结构图可以如图9所示。该终端设备包括通过系统总线连接的处理器、存储器、通信接口、显示屏和输入装置。其中，该终端设备的处理器用于提供计算和控制能力。该终端设备的存储器包括计算机可读存储介质、内存储器。该计算机可读存储介质存储有操作系统和计算机程序。该内存储器为计算机可读存储介质中的操作系统和计算机程序的运行提供环境。该终端设备的通信接口用于与外部的终端进行有线或无线方式的通信，无线方式可通过WIFI、运营商网络、近场通信(NFC)或其他技术实现。该计算机程序被处理器执行时以实现一种应用打开方法。该终端设备的显示屏可以是液晶显示屏或者通讯墨水显示屏，该终端设备的输入装置可以是显示屏上覆盖的触摸层，也可以是终端设备外壳上设置的按键、轨迹球或触控板，还可以是外接的键盘、触控板或鼠标等。
综上，基于本发明的电子设备，通过获取寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址、当前下发给节点的寻址指令帧的关系数得到该节点的地址，该方法可以对节点地址的分配实现精确控制，进而满足预设需求。
在一个实施例中，一种计算机可读存储介质，其上存储有计算机程序，计算机程序被处理器执行时实现以下步骤：根据第一寻址方式从节点集合中获得当前待分配地址的节点，其中，所述节点集合包括与车辆的第一总线相连的多个节点；根据寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址以及所述当前下发给所述节点的寻址指令帧的帧数，得到所述节点的地址；根据所述节点的地址对所述节点进行地址分配。
在一个实施例中，处理器执行计算机程序时还实现以下步骤：依次从所述节点集合中的首节点向尾结点进行节点查找；当查找到首个未进行地址分配的待处理节点时，将所述待处理节点作为所述当前待分配地址的节点；或者，依次从所述节点集合中的尾节点向首结点进行节点查找；当查找到首个未进行地址分配的待处理节点时，将所述待处理节点作为所述当前待分配地址的节点。
在一个实施例中，处理器执行计算机程序时还实现以下步骤：获得所述寻址指令序列中寻址指令帧的数量与所述当前下发给所述节点的寻址指令帧的帧数之间的第一差值；获得所述当前下发给所述节点的寻址指令帧携带的地址与所述第一差值之间的第二差值；根据所述第二差值得到所述节点的地址。
在一个实施例中，处理器执行计算机程序时还实现以下步骤：根据第二寻址方式从节点集合中获得当前待分配地址的节点；根据寻址指令序列中当前下发给所述节点的寻址指令帧携带的地址，得到所述节点的地址；根据所述节点的地址对所述节点进行地址分配。
综上，基于本发明的计算机可读存储介质，通过获取寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址、当前下发给节点的寻址指令帧的帧的关系数得到该节点的地址，该方法可以对节点地址的分配实现精确控制，进而满足预设需求。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于计算机可读存储介质中，该计算机程序在执行时，可包括如上述各方法的实施例的流程。其中，本申请所提供的各实施例中所使用的对存储器、数据库或其它介质的任何引用，均可包括计算机可读存储介质和计算机不可读存储介质的至少一种。计算机可读存储器可包括只读存储器(Read-Only Memory，ROM)、磁带、软盘、闪存或光存储器等。易失性存储器可包括随机存取存储器(Random Access Memory，RAM)或者外部高速缓冲存储器。作为说明而非局限，RAM以多种形式可得，比如静态随机存取存储器(Static Random Access Memory，SRAM)和动态随机存取存储器(Dynamic Random Access Memory，DRAM)等。
需要理解的是，术语“长度”、“宽度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
除非另有定义，本文中所使用的技术和科学术语与本发明的技术领域的技术人员通常理解的含义相同。本文中使用的术语只是为了描述具体的实施目的，不是旨在限制本发明。本文中出现的诸如“设置”等术语既可以表示一个部件直接附接至另一个部件，也可以表示一个部件通过中间件附接至另一个部件。本文中在一个实施方式中描述的特征可以单独地或与其它特征结合地应用于另一个实施方式，除非该特征在该另一个实施方式中不适用或是另有说明。
本发明已经通过上述实施方式进行了说明，但应当理解的是，上述实施方式只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施方式范围内。本领域技术人员可以理解的是，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。

Claims (11)

  1. 一种车辆的节点地址分配方法，其特征在于，包括：
    根据第一寻址方式从节点集合中获得当前待分配地址的节点，其中，所述节点集合包括与车辆的第一总线相连的多个节点；
    根据寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址以及所述当前下发给所述节点的寻址指令帧的帧数，得到所述节点的地址；
    根据所述节点的地址对所述节点进行地址分配。
  2. 根据权利要求1所述的节点地址分配方法，其特征在于，所述根据第一寻址方式从节点集合中获得当前待分配地址的节点，包括：
    依次从所述节点集合中的首节点向尾结点进行节点查找；
    当查找到首个未进行地址分配的待处理节点时，将所述待处理节点作为所述当前待分配地址的节点；
    或者，
    依次从所述节点集合中的尾节点向首结点进行节点查找；
    当查找到首个未进行地址分配的待处理节点时，将所述待处理节点作为所述当前待分配地址的节点。
  3. 根据权利要求2所述的节点地址分配方法，其特征在于，所述第一寻址方式为LSM寻址方式和BSM寻址方式中的一个。
  4. 根据权利要求1-3任一项所述的节点地址分配方法，其特征在于，所述根据寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址以及所述当前下发给所述节点的寻址指令帧的帧数，得到所述节点的地址，包括：
    获得所述寻址指令序列中寻址指令帧的数量与所述当前下发给所述节点的寻址指令帧的帧数之间的第一差值；
    获得所述当前下发给所述节点的寻址指令帧携带的地址与所述第一差值之间的第二差值；
    根据所述第二差值得到所述节点的地址。
  5. 根据权利要求1所述的节点地址分配方法，其特征在于，还包括：
    根据第二寻址方式从节点集合中获得当前待分配地址的节点；
    根据寻址指令序列中当前下发给所述节点的寻址指令帧携带的地址，得到所述节点的地址；
    根据所述节点的地址对所述节点进行地址分配。
  6. 根据权利要求5所述的节点地址分配方法，其特征在于，所述第二寻址方式为LSM寻址方式和BSM寻址方式中的一个，且所述第二寻址方式与所述第一寻址方式不同。
  7. 一种车辆的节点地址分配装置，其特征在于，包括：
    节点确定模块，用于根据第一寻址方式从节点集合中获得当前待分配地址的节点，其中，所述节点集合包括与车辆的第一总线相连的多个节点；
    地址确定模块，用于根据寻址指令序列中寻址指令帧的数量、当前下发给所述节点的寻址指令帧携带的地址以及所述当前下发给所述节点的寻址指令帧的帧数，得到所述节点的地址；
    分配模块，用于根据所述节点的地址对所述节点进行地址分配。
  8. 根据权利要求7所述的车辆的节点地址分配装置，其特征在于，所述地址确定模块具体用于：
    获得所述寻址指令序列中寻址指令帧的数量与所述当前下发给所述节点的寻址指令帧的帧数之间的第一差值；
    获得所述当前下发给所述节点的寻址指令帧携带的地址与所述第一差值之间的第二差值；
    根据所述第二差值得到所述节点的地址。
  9. 一种车辆，其特征在于，包括：根据权利要求7或8所述的车辆的节点地址分配装置。
  10. 一种电子设备，其特征在于，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，其特征在于，所述处理器执行所述程序时，实现根据权利要求1-6任一项所述的车辆的节点地址分配方法。
  11. 一种计算机可读存储介质，其上存储有计算机程序，其特征在于，该程序被处理器执行时实现根据权利要求1-6中任一所述的车辆的节点地址分配方法。
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