WO2024021977A1 - 沟槽栅功率mosfet及其制造方法 - Google Patents

沟槽栅功率mosfet及其制造方法 Download PDF

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Publication number
WO2024021977A1
WO2024021977A1 PCT/CN2023/103303 CN2023103303W WO2024021977A1 WO 2024021977 A1 WO2024021977 A1 WO 2024021977A1 CN 2023103303 W CN2023103303 W CN 2023103303W WO 2024021977 A1 WO2024021977 A1 WO 2024021977A1
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Prior art keywords
trench
epitaxial layer
power mosfet
pillar
body region
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PCT/CN2023/103303
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English (en)
French (fr)
Inventor
张永熙
陈伟
黄海涛
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Inventchip Technology Co Ltd
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Inventchip Technology Co Ltd
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Priority to KR1020247039203A priority Critical patent/KR102813923B1/ko
Priority to EP23845190.0A priority patent/EP4528818A4/en
Priority to JP2024552149A priority patent/JP7793809B2/ja
Priority to US18/869,453 priority patent/US12356679B2/en
Publication of WO2024021977A1 publication Critical patent/WO2024021977A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H10D62/054—Forming charge compensation regions, e.g. superjunctions by high energy implantations in bulk semiconductor bodies, e.g. forming pillars
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H10P30/2042—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors into crystalline silicon carbide
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H10P30/221—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks characterised by the angle between the ion beam and the mask
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    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface

Definitions

  • the present application relates to the field of semiconductors, and in particular to a trench gate power MOSFET and a manufacturing method thereof.
  • the most important performance parameter of the power MOSFET is the characteristic on-resistance Rsp.
  • the on-resistance between the drain and the source is proportional to the power consumed by the power MOSFET device. Under the same breakdown voltage, for devices with the same on-resistance, the smaller the characteristic on-resistance, the smaller the chip area, and the lower the parasitic capacitance of the power MOSFET, thereby reducing the switching of the power MOSFET during the power conversion process. loss.
  • Power devices with trench gate and super junction structures have lower on-resistance, resulting in lower switching losses and faster switching speeds, and have become one of the most widely used power switching devices currently.
  • the current manufacturing cost of power devices with trench gate and super junction structures is high and process control is difficult.
  • the present invention provides a trench gate power MOSFET and a manufacturing method thereof.
  • the present invention provides a trench gate power MOSFET.
  • the trench gate power MOSFET is formed in a wafer and includes:
  • a substrate the substrate being a substrate of a wide bandgap semiconductor material of a first conductivity type
  • An epitaxial layer, the epitaxial layer is grown on the substrate and has the first conductivity type
  • a trench is formed by etching in the body region, and the length direction of the trench is parallel to the crystallographic direction with the most obvious channel effect among all the crystallographic directions of the wafer, on the surface of the wafer. projection;
  • a second conductive type pillar acts by moving the first ions along the channel of the wide bandgap semiconductor material.
  • the bottom region of the trench should be formed by injecting the most obvious crystallographic direction.
  • the bottom region of the trench is located below the trench and connected to the bottom of the trench.
  • the longitudinal depth of the second conductive type pillar Not less than 50% of the thickness of the epitaxial layer located in the bottom region of the trench;
  • a trench gate is formed by filling a filler into the trench.
  • the power trench gate power MOSFET further includes: a connector having the second conductivity type between the second conductivity type pillar and the body region, One end of the connecting body is electrically connected to the body region, and the other end of the connecting body is electrically connected to the second conductive type pillar.
  • the power trench gate power MOSFET further includes: a drain located under the substrate, a gate located on the central axis of the body region, and a gate located on the central axis of the body region. The sources on both sides of the pole.
  • the power trench gate power MOSFET further includes: the epitaxial layer is a single epitaxial layer.
  • the power trench gate power MOSFET further includes: the epitaxial layer includes a first epitaxial layer and a second epitaxial layer, and the first epitaxial layer is located on the second epitaxial layer. below the layer; the thickness of the first epitaxial layer is less than the thickness of the second epitaxial layer; the doping concentration of the first epitaxial layer is less than the doping concentration of the second epitaxial layer; the bottom of the trench And the second conductive type pillar is located in the second epitaxial layer, and the longitudinal depth of the second conductive type pillar is not less than 50% of the thickness of the second epitaxial layer located in the bottom region of the trench.
  • the power trench gate power MOSFET further includes: the wide bandgap semiconductor material is silicon carbide.
  • the power trench gate power MOSFET further includes: the silicon carbide includes 4H-SIC or 6H-SIC.
  • the power trench gate power MOSFET further includes: a ratio of the depth of the trench to the width of the trench ranges from 1:1 to 5:1.
  • the power trench gate power MOSFET further includes: an oxide is formed on the inner surface of the trench.
  • the power trench gate power MOSFET further includes: the filler includes polysilicon.
  • the power trench gate power MOSFET further includes: the first ions include aluminum ions, and the first ions are injected in at least two times, that is, with a first dose and The first energy, the second dose, and the second energy are injected into the bottom region of the trench along the C-axis direction of the silicon carbide crystal.
  • the present invention also provides a method for manufacturing a trench gate power MOSFET, which generates the trench gate power MOSFET in a wafer, including:
  • a trench is formed in the body region by etching, and the length direction of the trench is parallel to the projection of the crystallographic direction with the most obvious channel effect among all the crystallographic directions of the wafer on the wafer surface;
  • the above manufacturing method further includes: forming a trench in the body region by etching, including injecting first ions into the body region and the epitaxial layer, To form a connector having the second conductivity type, one end of the connector is electrically connected to the body region, the other end of the connector is electrically connected to the second conductivity type column, and the connector has The depth is greater than or equal to the depth of the trench.
  • the above manufacturing method further includes: the wide bandgap semiconductor material is silicon carbide; and the crystallographic direction of the wide bandgap semiconductor material with the most obvious channel effect is selected to be silicon carbide.
  • the C-axis direction of the crystal is silicon carbide.
  • the above manufacturing method further includes: the silicon carbide includes 4H-SIC or 6H-SIC.
  • the manufacturing method further includes: injecting first ions into the bottom region of the trench along the crystallographic direction of the wide bandgap semiconductor material with the most obvious channel effect.
  • the steps include:
  • the first ions are implanted into the bottom region of the trench along the C-axis direction of the silicon carbide crystal with a first dose, a first energy and a second dose, and a second energy respectively.
  • the manufacturing method further includes: the first dose is 5E13 to 5E14 atoms per square centimeter, the first energy is 500kev to 1500kev; the second dose is 5E12 to 5E13 atoms per square centimeter, and the second energy is 50 kev to 300 kev.
  • the above manufacturing method further includes: the epitaxial layer includes a first epitaxial layer and a second epitaxial layer, wherein the wide band gap semiconductor substrate having the The first epitaxial layer of a first conductivity type, and the second epitaxial layer of the first conductivity type is grown on the first epitaxial layer.
  • the manufacturing method further includes: the thickness of the first epitaxial layer is smaller than the thickness of the second epitaxial layer; doping of the first epitaxial layer The concentration is smaller than the doping concentration of the second epitaxial layer.
  • the manufacturing method further includes: the bottom of the trench and the second conductive type pillar are located in the second epitaxial layer, and the second conductive type pillar is The longitudinal depth is not less than 50% of the thickness of the second epitaxial layer located in the bottom region of the trench.
  • the manufacturing method further includes: a ratio of the depth of the trench to the width of the trench ranges from 1:1 to 5:1.
  • the above manufacturing method further includes: the step of filling the trench with a filler, including:
  • a filler is filled into the trench.
  • the above manufacturing method further includes: the filler includes polysilicon.
  • the above manufacturing method further includes: the first ions include aluminum ions.
  • the trench gate power MOSFET of the present invention introduces a second conductive type pillar, such as a deep P pillar, under the trench, which not only protects the bottom of the trench, As the p-pillar at the super junction, it can also play a role in charge balancing. At the same time, the characteristic on-resistance Rsp is reduced, which can reduce the chip area and the parasitic capacitance of the power MOSFET, as well as the switching loss of the power MOSFET during the power conversion process.
  • the deep P-pillar is formed by high-energy ion implantation.
  • the manufacturing method of the present invention carries out ion implantation along the specific crystallographic direction of the semiconductor material (in the case of silicon carbide wafer, implantation along its c-axis), using the channel of the crystal Effect, under the same injection depth, the injection energy range From tens of Kev to more than a thousand Kev, the injection energy can be greatly reduced compared to existing technologies, thereby significantly reducing manufacturing costs and making the manufacturing process easier to control.
  • the length direction of the trench is set parallel to the projection of the above-mentioned specific crystal orientation on the wafer surface, so that a symmetrical P-pillar structure can be formed.
  • the structure of the super junction requires a symmetrical P-pillar structure. An asymmetric structure will cause uneven electric field distribution, which will easily cause local breakdown of the MOSFET device and reduce the voltage resistance of the device.
  • Figure 1 shows a schematic structural diagram of a planar structure power MOSFET produced by traditional technology.
  • Figure 2 shows a schematic structural diagram of a trench power MOSFET produced by traditional processes.
  • Figure 3 shows a schematic structural diagram of a trench power MOSFET from Infineon.
  • Figure 4 shows a schematic structural diagram of a trench power MOSFET from ROHM.
  • Figure 5 shows a schematic diagram of the angular relationship between common silicon carbide crystals and the surface of the silicon carbide wafer in the silicon carbide wafer.
  • Figure 6 shows a schematic structural diagram of a trench-type power MOSFET with non-axisymmetric P-pillars obtained by performing ion implantation along the C-axis when the silicon carbide wafer is cut in the direction shown in Figure 5.
  • FIG. 7 illustrates a cross-sectional schematic diagram of a trench gate power MOSFET structure according to some embodiments of the present application.
  • Figure 8a shows a three-dimensional schematic diagram of the schematic diagram shown in Figure 7 when viewed from above at 45°, according to some embodiments of the present application.
  • Figure 8b shows a schematic diagram of the mask pattern during the manufacturing process of the P-pillar connector in Figure 8a.
  • Figure 8c shows another schematic diagram of a P-pillar connector according to other embodiments of the present application.
  • Figure 9a shows the arrangement direction of the trench of a trench gate power MOSFET according to some embodiments of the present application.
  • Figure 9b shows a groove arrangement direction according to the prior art.
  • Figure 10 shows a schematic diagram of the relationship between the C-axis of the silicon carbide crystal and the coordinate system of the wafer surface in a trench gate power MOSFET structure according to some embodiments of the present application.
  • FIG. 11 shows a flow chart of a method of manufacturing a trench gate power MOSFET according to some embodiments of the present application.
  • Illustrative embodiments of the present application include, but are not limited to, trench gate power MOSFETs and methods of fabricating the same.
  • first, second, third, etc. may be used in this application to describe various information, the information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other.
  • first information may also be called second information, and similarly, the second information may also be called first information.
  • word “if” as used herein may be interpreted as "when” or “when” or “in response to determining.”
  • FIG. 1 shows a schematic structural diagram (cross-sectional view) of a planar structure MOSFET produced by a traditional process.
  • the MOSFET shown in Figure 1 includes a heavily doped N-type substrate 101, a lightly doped N-type epitaxial layer 102 formed on the substrate 101, and a P-type body region 103 formed on the epitaxial layer 102.
  • the gate, source and drain of planar MOSFETs are all on the same plane so they can be integrated on a plane, but there are major limitations on their size and their performance is not good enough.
  • FIG. 2 shows a schematic structural diagram (cross-sectional view) of a trench-type MOSFET produced by a traditional process.
  • the MOSFET shown in FIG. 2 includes a heavily doped N-type substrate 201, a lightly doped N-type epitaxial layer 202 formed on the substrate 201, and a P-type body region 203 formed on the epitaxial layer 202.
  • the trench-type MOSFET shown in Figure 2 does not have a JFET area, and the vertical trenches on the trench sidewalls can make the trench spacing smaller.
  • the critical electric field of wide bandgap semiconductors such as silicon carbide is 10 times that of silicon, the electric field intensity in the bottom area of the trench is larger. This high electric field in the semiconductor can cause high electric fields on the trench oxide, causing device reliability issues.
  • FIG. 3 shows a schematic structural diagram (cross-sectional view) of a trench-type MOSFET from Infineon.
  • the MOSFET shown in Figure 3 includes a heavily doped N-type substrate 301, a lightly doped N-type epitaxial layer 302 formed on the substrate 301, and a P-type body region 303 formed on the epitaxial layer 302.
  • the trench 304 etched in the P-type body region 303, the gate oxide film 306 grown on the inner wall of the trench 304, and the polysilicon 305 deposited on the gate oxide film 306.
  • the trench-type MOSFET shown in FIG. 2 the trench-type MOSFET shown in FIG.
  • the longitudinal depth of the P-type region is greater than the longitudinal depth of the P-type body region.
  • FIG. 4 shows a schematic structural diagram (cross-sectional view) of a trench type MOSFET from ROHM.
  • the MOSFET shown in Figure 4 includes a heavily doped N-type substrate 401, a lightly doped N-type epitaxial layer 402 formed on the substrate 401, and a P-type body region 403 formed on the epitaxial layer 402.
  • the trench 406 etched in the P-type body region 403, the gate oxide film 407 grown on the inner wall of the trench 406, and the polysilicon 408 deposited on the gate oxide film 407.
  • the trench-type MOSFET shown in FIG. 2 the trench-type MOSFET shown in FIG.
  • first P-type region 404 and a second P-type region 405 that are heavily doped below the trench 406.
  • the first P-type region 404 and the second P-type region 405 are located on both sides of the trench 406 respectively, and the longitudinal depths of the first P-type region 404 and the second P-type region 405 are less than The longitudinal depth of the P-type body region.
  • the trench-type MOSFET structure shown in Figures 3 and 4 has high manufacturing costs and difficult process control.
  • R N+ is the resistance of the N+ diffusion area in the source region. Due to the high doping concentration of the N+ region, the resistance is very small. Therefore, this part of the resistance can be ignored compared with other resistances that make up the source-drain on-resistance Rds(on). .
  • R CH is the trench resistance, that is, the trench resistance under the gate.
  • R CH is an important parameter that makes up the source-drain on-resistance Rds (on) . Changes in the trench width-to-length ratio, gate oxide thickness, and gate voltage can all affect Changes in R CH .
  • R D is the drift region resistance, that is, the resistance of the epitaxial layer.
  • the epitaxial layer is a high-resistance layer grown on the substrate to withstand high voltage. Under the action of external voltage, carriers drift in the drift region. For high-voltage MOSFET devices, the drift resistance determines the source-drain conduction. Resistor Rds (on) is the most important factor. Therefore, reducing the drift region resistance R D can reduce the source-drain on-resistance Rds (on) .
  • R sub is the wafer substrate resistance, which can be reduced through processes such as backside thinning.
  • the characteristic on-resistance Rsp source-drain on-resistance Rds(on)*effective area of the chip, for the same source-drain on-resistance Rds(on), the smaller the characteristic on-resistance Rsp is , the smaller the effective area of the chip, the lower the parasitic capacitance of the power MOSFET, which can reduce the switching loss of the power MOSFET during the power conversion process.
  • Figure 5 shows a schematic diagram of the angular relationship between common silicon carbide crystals and the surface of the silicon carbide wafer in silicon carbide wafers, that is, the angular relationship between microscopic crystals and macroscopic wafers.
  • the figure shows the X direction of the wafer surface and the Y direction perpendicular to the wafer surface (i.e. the normal direction), as well as the two mutually perpendicular crystal directions [0001] of the silicon carbide (4H-SiC) crystal and direction.
  • crystals are structures composed of a large number of microscopic material units (atoms, ions, molecules, etc.) arranged in an orderly manner according to certain rules. Therefore, crystals usually have specific shapes.
  • the crystal structure of the crystal can be defined.
  • Axis crystallographic direction, crystallographic plane.
  • silicon carbide (4H-SiC) crystal defines at least two crystal directions as shown in the figure: C-axis direction (i.e., [0001] direction) and direction.
  • C-axis direction i.e., [0001] direction
  • direction i.e., [0001] direction
  • the crystal direction as shown in Figure 5 is usually selected when cutting wafers, that is, the axis of the crystal (C-axis) is normal to the wafer surface.
  • one crystallographic direction of the crystal that is The projection of the direction on the wafer surface coincides with the X direction of the wafer.
  • this angle is ignored, and the orientation and mirror surface of the crystal are directly used to refer to the direction of the wafer surface.
  • FIG. 6 shows a schematic structural diagram (cross-section) of a conventional trench-type power MOSFET that performs ion implantation along the C-axis to obtain non-axisymmetric P-pillars when the silicon carbide wafer is cut in the direction shown in Figure 5. picture).
  • the trench-type power MOSFET shown in the figure includes a substrate 01, an epitaxial layer 02 formed on the substrate 01 by a process such as epitaxial growth, a P-type body region 04 formed on the epitaxial layer 02, and a penetrating P The body region 04 extends deep into the trench 00 in the epitaxial layer 02 .
  • the P pillar is located below the trench 00, buried in the epitaxial layer 02, and is usually formed by ion implantation.
  • the crystallographic direction with the most obvious channel effect is usually selected as the direction of ion implantation.
  • the direction of the C axis is the crystallographic direction with the most obvious channel effect.
  • the C axis of silicon carbide is not perpendicular to the surface of the wafer. That is to say, in the structure shown in Figure 6, the P pillar 11 formed by ion implantation cannot be perpendicular to the surface of the wafer. . That is to say, in the cross-sectional view of a unit cell as shown in FIG. 6 , the P-pillar 11 cannot be symmetrical about the central axis of the unit cell.
  • the present invention proposes a new trench gate power MOSFET structure, which will be described below in conjunction with Figures 7 and 8a and 8b.
  • 7 illustrates a cross-sectional schematic diagram of a trench gate power MOSFET structure according to some embodiments of the present application.
  • Figure 8a shows a schematic three-dimensional view of the MOSFET shown in Figure 7 when viewed from above at 45°, according to some embodiments of the present application.
  • Figure 8b shows a schematic diagram of the mask pattern during the manufacturing process of the P-pillar connector 505 in Figure 8a.
  • the trench gate power MOSFET provided by the present invention includes a power MOSFET having a trench gate and a super junction (or quasi-super junction) structure.
  • a power MOSFET having a trench gate and a super junction (or quasi-super junction) structure.
  • the wide bandgap semiconductor substrate as silicon carbide material
  • the first conductivity type as N type
  • the second conductivity type as P type
  • the second conductivity type column as P column
  • the first ion as aluminum ion as an example
  • the structure and formation process of a trench gate power MOSFET are described in detail.
  • the substrate 501 is a substrate having a wide bandgap semiconductor of the first conductivity type.
  • substrate 501 may be a heavily doped N-type silicon carbide substrate.
  • the first epitaxial layer 502 is located below the second epitaxial layer 503 , the thickness of the first epitaxial layer 502 is less than the thickness of the second epitaxial layer 503 , and the doping concentration of the first epitaxial layer 502 is less than the doping concentration of the second epitaxial layer 503 . impurity concentration.
  • the N-type doping concentration of the first epitaxial layer 502 is between 1E14atoms/cm 2 (atoms per square centimeter) and 2E16atoms/cm 2 , and the thickness of the first epitaxial layer 502 is between 0.2 ⁇ m and 40 ⁇ m. time; the N-type doping concentration of the second epitaxial layer 503 is between 2E15atoms/cm 2 and 2E17atoms/cm 2 , and the thickness of the second epitaxial layer 503 is between 2 ⁇ m and 200 ⁇ m. It can be understood that the thickness and doping concentration of the first epitaxial layer 502 and the thickness and doping concentration of the second epitaxial layer 503 can be determined according to the required withstand voltage rating of the device. In this embodiment, two epitaxial layers with different doping concentrations can be used to form a quasi-super junction device and enhance avalanche endurance.
  • the wide bandgap semiconductor substrate is silicon carbide material, and Non-restrictive.
  • the wide bandgap semiconductor substrate can also be other wide bandgap semiconductor materials, such as gallium nitride, aluminum nitride, etc.
  • the difference in selecting different substrate materials is that based on the different crystal orientations of different wafers (bodies), different trench arrangement directions and ion implantation directions are selected.
  • the doped impurities of the N-type doped first epitaxial layer 502 and the second epitaxial layer 503 can be nitrogen or phosphorus, or other N-type impurities.
  • the P body region 504 is located above the second epitaxial layer 503. It can be formed by injecting ions of a conductive type different from those of the substrate 501, the first epitaxial layer 502 and the second epitaxial layer 503, such as P-type ions, into the upper end of the second epitaxial layer 503. to form.
  • the P-pillar connector 505 is formed in the P body region 504 (P body region) and the second epitaxial layer 503 through an ion implantation process. Specifically, a mask pattern 5051 indicating the P-pillar connector 505 is first formed on the upper surface of the P body region 504 through a photolithography mask process, as shown in FIG. 8b. The mask pattern is symmetrical about the central axis of the upper surface of the P-body region 504 (see Figure 8b). Then, P-type impurities are implanted in this region toward the P body region 504 and the second epitaxial layer 503 through an ion implantation process, thereby forming a columnar P-pillar connector 505.
  • the P-pillar connector 505 connects the P-pillar 511 to the P-body region 504, so that the P-pillar 511 generated in subsequent steps is electrically connected to the P-body region 504, and will not be electrically floating in any working state. . That is to say, the depth of the P-pillar connector 505 needs to start from the upper surface of the P body region 504 and go deep into the second epitaxial layer 503. In this way, after the trench gate power MOSFET is processed, it is buried in the second epitaxial layer 503. Only the P-pillar 511 in the vertical direction (referring to the vertical direction in Figures 7 and 8a and 8b) can be electrically connected to the lateral (referring to the lateral direction in Figures 7 and 8a and 8b) P-body region 504. connect.
  • Ions are continued to be implanted above the P body region 504 (including the P pillar connector 505) to form an ohmic contact resistance portion.
  • N-type heavily doped impurities are injected into the middle section of the P body region 504, that is, the part including the P pillar connector 505, to obtain the N-type heavily doped region 506, which is the part marked S in Figure 7, to facilitate the formation of Lower source ohmic contact resistance.
  • P-type heavily doped impurities are injected at both ends of the P body region 504, that is, at the position connected to both ends of the N-type heavily doped region 506, to obtain the first P-type heavily doped region 507 and the first P-type heavily doped region 507.
  • the two P-type heavily doped regions 508 facilitate the formation of a lower ohmic contact resistance of the P body (ie, the P body region 504 ).
  • a hard mask layer pattern 5002 for processing the trench 500 is formed on both sides of the central axis of the surface of the P body region 504 .
  • This mask pattern is not continuous along the central axis, but is consistent with the aforementioned P pillar.
  • the mask patterns 5051 of the connector 505 are complementary.
  • the P body region 504 and part of the second epitaxial layer 503 under the hard mask layer pattern 5002 of the trench 500 are etched away to form the trench 500, and the P pillar is connected
  • the P-pillar connector 505 under the mask pattern 5051 of the body 505 is retained as a conductor for electrical connection between the P-pillar 511 and the P-body region 504 .
  • the composition of the hard mask layer may be silicon dioxide or nickel. It is understood that in other embodiments, the hard mask layer
  • the components can be other elements or compounds.
  • the bottom 5001 of the trench 500 is located in the second epitaxial layer 503 .
  • the ratio of the depth and width of the trench 500 may range from 1:1 to 5:1.
  • the width of the trench 500 is 0.4 ⁇ m and the depth is 1.2 ⁇ m.
  • the ratio of trench 500 depth to width is 3:1. It can be understood that in the illustrated embodiment, the width and depth of the trench 500 are exemplary and not limiting. In other embodiments of the present application, the width and depth of the trench 500 may be other values.
  • the first pattern 72 and the second pattern 72' in Figures 9a and 9b are used to illustrate the positional relationship between the trench and the wafer 71.
  • the shaded portion is used to illustrate the trench 500, especially the relationship between the length direction of the trench 500 and the crystal plane of the wafer 71.
  • the surface of wafer 71 shows multiple crystallographic directions (shown in square brackets) and crystal planes (shown in round brackets). According to the above description, it can be seen that the axial direction of the silicon carbide wafer surface and the silicon carbide crystal are not at right angles.
  • Figure The directions of the wafer surface in the illustration are actually the projection of the crystallographic directions of the silicon carbide crystal on the wafer surface. In order to facilitate description in the industry, the directions of the wafer surface are usually directly referred to by the crystallographic directions of the crystals.
  • trenches 500 can be etched on one wafer 71, and the directions of these trenches are the same.
  • trenches are etched in the direction shown in Figure 9b by default, that is, the length direction of the trench is perpendicular to the crystal plane.
  • the second graph 72' in Figure 9b As shown in the second graph 72' in Figure 9b.
  • such a groove direction is the fundamental reason for the appearance of the parallelogram P-pillar shown in Figure 6.
  • the present invention adjusts the default trench arrangement direction within the row so that the length direction of the trench is parallel to the projection of a selected crystallographic direction of the wafer (body) on the wafer surface. Because the C-axis is not only the crystallographic direction with obvious channel effect, but also the crystallographic direction with the smallest deviation angle from the wafer normal under the current SiC wafer manufacturing method, the trench setting direction in this application must ensure that the length direction of the trench is consistent with the C-axis and The plane formed by the wafer normal is parallel, so that the implantation along the C-axis will not cause a shielding effect due to the influence of the trench sidewalls and the mask.
  • the selected crystal orientation is the crystal orientation with the most obvious channel effect among all crystal orientations of the wafer, that is, the direction with the deepest depth that can be achieved during ion implantation.
  • the projection direction of the C-axis on the wafer surface is selected. This change is conducive to the formation of symmetrical P-pillars during subsequent ion implantation.
  • symmetrical P-pillars 511 are formed when ions are implanted along the C-axis (outside through the paper).
  • Figure 10 please refer to the description of Figure 10 below.
  • aluminum ions e.g., Al-27
  • a first energy of 500kev to 1500kev a first dose of 5E13atoms/cm 2 to 5E14atoms/cm 2
  • a second energy of 50kev to 300kev a second dose of 5E12atoms/cm 2 to 5E13atoms/cm 2
  • the C-axis direction (for 4H-SIC, the angle between the direction of ion implantation and the normal direction of the 4H-SIC wafer is 4 degrees) is injected into the bottom area of the trench 500 to achieve uniform depth doping in silicon carbide.
  • P-pillar 511 is formed.
  • the depth of the P pillar 511 is not less than 50% of the thickness of the second epitaxial layer 503 located under the bottom of the trench 500, the P pillar 511 is located in the second epitaxial layer 503, the P pillar 511 and the N-type lightly doped third
  • the two epitaxial layers 503 form a quasi-super junction structure.
  • the P-pillar 511 and the P-body region 504 are connected in the width direction.
  • the P-pillar connector 505 can also be implemented by injecting ions into the sidewalls of the trench 500 after the trench 500 is etched.
  • the trench 500 is etched continuously along the central axis of the unit cell, instead of being intermittent etching as shown in Figure 8b. The etching depth penetrates the P body region 504 and reaches the second epitaxial layer 503 .
  • ions are implanted into the side walls of the trench 500 to form P-pillar connectors 505 with a certain thickness on both side walls.
  • the depth of the set of P-pillar connectors 505 is at least the same as the depth of the trench 500, so that it can be connected with the subsequently generated P-pillar 511 (the P-pillar 511 is generated at the bottom of the trench 500 through an ion implantation process, and is consistent with the bottom of the trench 500). connection) to achieve electrical connection.
  • the P-pillar connector 505 is generated in the P-body region 504, the P-body region 504 and the P-pillar 511 can be effectively electrically connected through the P-pillar connector 505.
  • Figure 10 shows a schematic diagram of the XYZ coordinate system of the upper surface of the wafer, in which the X direction and the Y direction are parallel to the wafer surface, and the Z direction is perpendicular to the wafer surface.
  • multiple crystal directions and crystal planes of silicon carbide crystals are also shown in Figure 10.
  • the orientation diagram of the crystal is slightly deflected to show the angle between the crystal and the wafer.
  • the region can form can only be a non-axisymmetric P-column that is approximately a parallelogram.
  • the preferred solution for P-pillars is a symmetrical (axially symmetric) pattern.
  • P-pillars with a parallelogram cross-section bring many hidden dangers and can easily lead to device breakdown and failure.
  • the present invention turns the default groove direction in the industry by 90°, so that the length direction of the groove is as shown in Figure 9a, that is, the length direction of the groove is parallel to the X-axis.
  • ions implanted along the C-axis can be understood as along the Y-axis (i.e., perpendicular to the Cy direction of the wafer) and along the X-axis (i.e., parallel to the wafer's Cy direction).
  • x direction are injected separately in both directions.
  • the X direction is the length direction of the trench. Injecting ions along this direction will not affect the cross-sectional shape of the P pillar 511 in the width direction of the trench 500 .
  • the range of ion implantation does not exceed the expected range.
  • the P-pillar 511 can form a symmetrical approximately rectangular structure. Compared with the prior art shown in Figure 9b, this The invention can improve the stability and reliability of trench-type MOSFETs.
  • the trench type MOSFET of the present application can improve the withstand voltage capability.
  • a sufficiently deep P pillar 511 can increase the doping concentration of the second epitaxial layer 503 and reduce the drift region resistance RD , thereby reducing the on-resistance Rds (on) .
  • the above-mentioned injection times of aluminum ions (such as Al-27) into silicon carbide are exemplary and not limiting. In other embodiments of the present application, the injection times can be adjusted as needed.
  • the depth of injection selects the number of injections, the corresponding energy and dose.
  • the injection of aluminum ions (such as Al-27) from the C-axis direction of the 4H-SIC wafer here is exemplary and not limiting.
  • other conductive types can be P-type ions are injected into the second epitaxial layer along the crystallographic direction of other wide-bandgap semiconductors to utilize the crystal trench effect to achieve a deeper implantation depth with lower implantation energy.
  • the ions implanted in the second epitaxial layer 503 are activated through high-temperature annealing, and silicon dioxide is formed on the inner surface of the trench 500.
  • Polysilicon is then deposited into the trench 500 to form a polysilicon gate, and a second layer of silicon dioxide is grown on the polysilicon gate.
  • the structure of the trench-gate quasi-superjunction power MOSFET finally formed in this application is shown in Figure 7.
  • Embodiments of the present application also provide a power MOSFET (not shown) with a trench gate super junction structure. Its structure and preparation method are similar to the power MOSFET with a trench gate quasi super junction structure. Compared with the power MOSFET with a trench gate quasi super junction structure, The only difference between the junction structure power MOSFET and the trench gate super junction structure MOSFET is that during the preparation process, only a single layer of epitaxy is required, and the depth of the p-pillar formed therein must be no less than the area below the bottom of the trench. 50% of the thickness of the epitaxial layer, the P pillar and the epitaxial layer form a super junction structure. Please refer to the above for detailed description and will not be repeated here.
  • Figure 11 shows a schematic flow chart of a manufacturing method of a trench gate power MOSFET according to some embodiments of the present application. Specifically, as shown in Figure 11, the manufacturing method of a trench gate power MOSFET of the present application includes:
  • the material of the wide bandgap semiconductor substrate can be silicon carbide, gallium nitride, aluminum nitride, diamond, etc. Can be produced in a wide range through epitaxial growth process
  • An epitaxial layer is formed on the bandgap semiconductor substrate.
  • the epitaxial layer of the first conductivity type is an epitaxial layer doped with elements of the first conductivity type.
  • the first conductive type element may be nitrogen, phosphorus and other elements, so that the epitaxial layer is an N-type semiconductor (free electrons are multi-characters and holes are minority carriers).
  • the first conductive type element may be a trivalent element such as boron or aluminum, so that the epitaxial layer is a P-type semiconductor (holes are majority carriers and free electrons are minority carriers). It can be understood that whether the first conductivity type is P type or N type can be selected according to actual needs, and is not limited here.
  • the body region of the second conductivity type is a body region doped with elements of the second conductivity type.
  • the second conductivity type is different from the first conductivity type. For example, if the first conductivity type is N type, then the second conductivity type is P type; if the first conductivity type is P type, then the second conductivity type is N type. It can be understood that the first conductivity type and the second conductivity type can be determined according to actual needs, and are not limited here.
  • a second conductivity type element may be implanted into the epitaxial layer through an ion implantation process to form a body region of the second conductivity type.
  • the ion implantation direction can be matched with the direction of the trench.
  • the matching may include that the ion implantation direction is perpendicular to the bottom surface of the trench, or may include that the ion implantation direction may be decomposed into: a direction perpendicular to the bottom surface of the trench and a direction parallel to the length of the trench. Based on the ion implantation direction, the crystallographic direction with the most obvious channel effect is usually selected.
  • the trench can be set arbitrarily on the wafer surface, and the ion implantation direction can always enter vertically.
  • the bottom of the trench if the crystallographic direction with the most obvious channel effect is not perpendicular to the wafer surface, the crystallographic direction with the most obvious channel effect can be decomposed into the X direction parallel to the wafer surface and the Y direction perpendicular to the wafer surface.
  • the length direction of the groove can be set to a direction parallel to the X direction.
  • the length direction of the trench is set perpendicular to the crystal plane of the wafer 71 as shown in FIG. 9a direction, that is, the length direction of the trench is parallel to the crystallographic direction (or more accurately, parallel to the crystallographic direction projection on the wafer) without setting it in the orientation shown in Figure 9b.
  • a P pillar connector 505 may be formed between the bottom 5001 of the trench 500 and the P body region 504 by ion implantation.
  • the P-pillar connector 505 is formed first. This can be understood with reference to Figures 8a and 8b.
  • a mask pattern 5051 of the P-pillar connector 505 as shown in the figure is prepared on both sides of the central axis (shown in Figure 8b) of the upper surface of the P-body region 504. region, and then in this region, P-type ions are implanted into the P body region 504 and the second epitaxial layer 503 to obtain the P-pillar connector 505.
  • the depth of ion implantation should be greater than the depth of trench 500, that is, the depth should reach the area of P pillar 511, so that the electrical connection between P body area 504 and P pillar 511 to be processed later can be achieved through P pillar connector 505. .
  • a trench 500 is formed in the P body region 504 and the second epitaxial layer 503 through an etching process according to the area of the hard mask layer pattern 5002 for processing trenches shown in FIG. 8b, and the depth and width of the trench can be controlled. .
  • the position of the mask pattern 5051 of the P-pillar connector 505 shown in FIG. 8b can be located at any position on the central axis, or, in a unit cell, there can be multiple, Similar settings will not be described here.
  • the body region may be etched by dry etching technology to form trenches. In some embodiments, the body region may be etched by wet etching technology to form trenches. It can be understood that dry etching or wet etching can be selected to form the trench according to the actual situation, which is not limited here.
  • P-type ion implantation can also be added on the side wall near the P pillar connector 505, so that the P pillar connector 505 and the P body The regions 504 are fully connected, so that an effective P-type connection can be formed to avoid electrical floating of the P-pillar 511 that will be processed later.
  • the first P-type heavily doped region 507, the second P-type heavily doped region 508 and the N-type heavily doped region 506 can also be formed on both sides of the central axis of the device surface.
  • a mask is used to circle the area of the P-pillar connector 505 (refer to FIG. 8a ), and then an ion implantation process is performed, thereby forming the P-pillar connector 505 in the P body region 504 and the second epitaxial layer 503 .
  • the P-pillar connector 505 is formed. This can be understood with reference to Figures 8a and 8c. Compared with the above-mentioned situation where the trench 500 is intermittent, a continuous trench 500 can be obtained by forming the P-pillar connector 505 later. That is, in the embodiment shown in FIG. 8c, there is no P-pillar connector spanning the trench 500, which can slightly reduce the complexity of trench etching.
  • a trench 500 as shown in the figure is etched in the P body region 504 and the second epitaxial layer 503 according to conventional processes, and then in the trench 500 Ion implantation is performed on the sidewalls on both sides to form a P ion heavily doped region with a certain thickness on the sidewalls to form a set of P-pillar connectors 505.
  • the P-pillar connector manufactured by the previous method is embedded into both side walls of the trench 500 .
  • the connection between the P pillar connector 505 and the bottom of the trench 500 can be further downward. Ion implantation is performed so that the P-pillar connector 505 and the P-pillar 511 to be processed later can be electrically connected more reliably.
  • the P-pillar is preferably symmetrical in shape, while asymmetrical P-pillar is not conducive to reducing the electric field intensity in the super junction, and excessive electric field intensity can easily lead to device breakdown. Therefore, this application breaks industry habits and A trench is etched in the x direction (see Figure 10). It can be seen from the description of FIG. 7 and FIGS. 8a, 8b, and 8c that the P-pillar 511 is a rectangular structure disposed below the trench 500 and matching the shape and size of the trench 500.
  • the first ions Inject the first ions into the bottom area of the trench along the crystallographic direction of the wide bandgap semiconductor material to form a second conductive type column.
  • the bottom area of the trench is located below the trench and connected to the bottom of the trench.
  • the crystal The direction should be selected so that the implantation of the first ions can fully utilize the crystal trench effect (908). In this way, when the first ions are injected along the crystal direction of the semiconductor, due to the trench effect, the range of the first ions is significantly increased compared to when injected in random directions or along the normal direction of the wafer, and has a stronger penetrating effect, thus The energy of the first ion implantation can be greatly reduced and the manufacturing cost can be reduced.
  • the wide bandgap semiconductor material is a hexagonal wide bandgap semiconductor material (such as silicon carbide, gallium nitride, etc.), and the crystal orientation refers to the vertical crystal plane (i.e., C axis direction).
  • the wide bandgap semiconductor material is silicon carbide, and the crystallographic direction of the wide bandgap semiconductor material is selected to be the C-axis direction of silicon carbide, where the C-axis direction forms a certain angle with the normal direction of the silicon carbide wafer. .
  • the wide bandgap semiconductor material is 4H-SIC or 6H-SiC
  • the angle between its C-axis direction and the normal direction of the 4H-SIC or 6H-SiC wafer is 4 degrees. It can be understood that for other types of silicon carbide wafers, the angle between the corresponding C-axis direction and the corresponding normal direction of the wafer can be other values, which are not limited here.
  • the longitudinal depth of the second conductive type pillar is at least not less than 50% of the thickness of the epitaxial layer located in the bottom region of the trench.
  • the epitaxial layer is a single epitaxial layer, and the longitudinal depth of the second conductivity type pillar is at least not less than 50% of the thickness of the epitaxial layer located in the bottom region of the trench.
  • the epitaxial layer includes a first epitaxial layer and a second epitaxial layer, the first epitaxial layer is located below the second epitaxial layer; the bottom of the trench and the second conductive type pillar are located in the second epitaxial layer, and the The longitudinal depth of the second conductive type pillar is at least not less than 50% of the thickness of the second epitaxial layer located in the bottom region of the trench.
  • filler 910
  • the inner surface of the trench may be formed After forming an oxide (such as silicon dioxide), a filler is filled into the trench. Wherein, filling the filler into the trench may be polysilicon deposition into the trench.
  • TCAD a semiconductor process/device simulation tool
  • TCAD a semiconductor process/device simulation tool
  • the characteristic on-resistance Rsp can reach 0.2 ohms per square centimeter.
  • the characteristic on-resistance Rsp of the device is corrected to 0.896 ohm square centimeter, and the breakdown voltage of the device is 950V (the rated voltage is 750V or 650V).
  • Silicon carbide super junction MOSFET has a typical static output capacitance Coss curve. When the source-drain voltage Vds increases, the static output capacitance Coss decreases significantly.
  • the power MOSFET with trench gate and super junction (or quasi-super junction) structure prepared by the power MOSFET preparation method of the present application has trench gate and super junction (or quasi-super junction) structure. Under the same breakdown voltage, MOSFETs with quasi-superjunction structure can have thinner epitaxial layers, lower characteristic on-resistance, and high device stability.

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Abstract

本申请公开了一种沟槽栅功率MOSFET，包括：衬底，是具有第一导电类型的宽禁带半导体的衬底；外延层，在衬底上生长，且具有第一导电类型；体区，在外延层上形成，且具有第二导电类型；沟槽，在体区内刻蚀形成，沟槽的长度方向平行于晶圆的所有晶向中一个选定的晶向在晶圆表面的投影；第二导电类型柱，通过将第一离子沿宽禁带半导体材料的晶向注入沟槽的底部区域而形成，沟槽的底部区域位于沟槽下方且与沟槽底部相接，第二导电类型柱的纵向深度至少不小于位于沟槽的底部区域的外延层的厚度的50％；以及通过向沟槽中填入填充物而形成的沟槽栅。本发明的优点在于，可以提高沟槽型的MOSFET的电流能力和可靠性。

Description

沟槽栅功率MOSFET及其制造方法 技术领域
本申请涉及半导体领域，特别涉及一种沟槽栅功率MOSFET及其制造方法。
背景技术
半导体器件例如功率MOSFET等已被广泛应用于汽车电子、开关电源及工业控制等领域。为了不断提高功率转换效率和功率密度，设计高效的功率MOSFET等功率开关器件至关重要。功率MOSFET最重要的性能参数是特征导通电阻Rsp，漏极与源极间导通电阻的大小与功率MOSFET器件消耗的功率成正比。在相同的击穿电压下，对于相同导通电阻的器件，特征导通电阻越小，那么芯片面积也越小，功率MOSFET的寄生电容越低，从而降低了功率MOSFET在功率转换过程中的开关损耗。沟槽栅和超级结结构的功率器件具有更低的导通电阻，从而有更低开关损耗及更快的开关速度，成为目前被广泛应用的功率开关器件之一。然而目前沟槽栅和超级结结构的功率器件制造成本高，过程控制难度大。
发明内容
为了解决现有技术中的上述问题，本发明提供了一种沟槽栅功率MOSFET及其制造方法。
第一方面，本发明提供了一种沟槽栅功率MOSFET，所述沟槽栅功率MOSFET形成于一个晶圆中，包括：
衬底，所述衬底是具有第一导电类型的宽禁带半导体材料的衬底；
外延层，所述外延层在所述衬底上生长，且具有所述第一导电类型；
体区，所述体区在所述外延层上形成，且具有第二导电类型；
沟槽，所述沟槽在所述体区内刻蚀形成，所述沟槽的长度方向平行于所述晶圆的所有晶向中沟道效应最明显的晶向在所述晶圆表面的投影；
第二导电类型柱，所述第二导电类型柱通过将第一离子沿宽禁带半导体材料的沟道效 应最明显的晶向注入所述沟槽的底部区域而形成，所述沟槽的底部区域位于所述沟槽下方且与所述沟槽底部相接，所述第二导电类型柱的纵向深度不小于位于所述沟槽的底部区域的所述外延层的厚度的50％；
沟槽栅，所述沟槽栅通过向所述沟槽中填入填充物而形成。
在上述第一方面的一种可能的实现中，上述功率沟槽栅功率MOSFET还包括：所述第二导电类型柱与所述体区之间还包括具有所述第二导电类型的连接体，所述连接体一端与所述体区电连接，所述连接体的另一端与所述第二导电类型柱电连接。
在上述第一方面的一种可能的实现中，上述功率沟槽栅功率MOSFET还包括：位于所述衬底下方的漏极、位于所述体区的中轴线上的栅极、位于所述栅极两侧的源极。
在上述第一方面的一种可能的实现中，上述功率沟槽栅功率MOSFET还包括：所述外延层为单外延层。
在上述第一方面的一种可能的实现中，上述功率沟槽栅功率MOSFET还包括：所述外延层包括第一外延层和第二外延层，所述第一外延层位于所述第二外延层的下方；所述第一外延层的厚度小于所述第二外延层的厚度；所述第一外延层的掺杂浓度小于所述第二外延层的掺杂浓度；所述沟槽的底部及所述第二导电类型柱位于所述第二外延层内，所述第二导电类型柱的纵向深度不小于位于所述沟槽的底部区域的所述第二外延层的厚度的50％。
在上述第一方面的一种可能的实现中，上述功率沟槽栅功率MOSFET还包括：所述宽禁带半导体材料为碳化硅。
在上述第一方面的一种可能的实现中，上述功率沟槽栅功率MOSFET还包括：所述碳化硅包括4H-SIC或6H-SIC。
在上述第一方面的一种可能的实现中，上述功率沟槽栅功率MOSFET还包括：所述沟槽的深度和所述沟槽的宽度的比值范围为1:1至5:1。
在上述第一方面的一种可能的实现中，上述功率沟槽栅功率MOSFET还包括：所述沟槽的内表面形成有氧化物。
在上述第一方面的一种可能的实现中，上述功率沟槽栅功率MOSFET还包括：所述填充物包括多晶硅。
在上述第一方面的一种可能的实现中，上述功率沟槽栅功率MOSFET还包括：所述第一离子包括铝离子，所述第一离子至少分两次注入，即分别以第一剂量、第一能量及第二剂量、第二能量沿所述碳化硅晶体的C轴方向注入所述沟槽的底部区域。
第二方面，本发明还提供了一种沟槽栅功率MOSFET的制造方法，在晶圆中生成所述沟槽栅功率MOSFET，包括：
在宽禁带半导体衬底上生长具有第一导电类型的外延层；
在所述外延层上形成具有第二导电类型的体区；
在所述体区内通过刻蚀形成沟槽，所述沟槽的长度方向平行于所述晶圆的所有晶向中沟道效应最明显的晶向在晶圆表面的投影；
将第一离子沿宽禁带半导体材料的沟道效应最明显的晶向注入所述沟槽的底部区域，以形成第二导电类型柱，所述沟槽的底部区域位于所述沟槽下方且与所述沟槽的底部相接，并且所述第二导电类型柱的纵向深度不小于位于所述沟槽的底部区域的所述外延层的厚度的50％；
向所述沟槽中填入填充物填充所述沟槽。
在上述第二方面的一种可能的实现中，上述制造方法还包括：所述在所述体区内通过刻蚀形成沟槽，包括向所述体区和所述外延层注入第一离子，以形成具有所述第二导电类型的连接体，所述连接体一端与所述体区电连接，所述连接体的另一端与所述第二导电类型柱电连接，并且所述连接体的深度大于等于所述沟槽的深度。
在上述第二方面的一种可能的实现中，上述制造方法还包括：所述宽禁带半导体材料为碳化硅；所述宽禁带半导体材料的沟道效应最明显的晶向选取为碳化硅晶体的C轴方向。
在上述第二方面的一种可能的实现中，上述制造方法还包括：所述碳化硅包括4H-SIC或6H-SIC。
在上述第二方面的一种可能的实现中，上述制造方法还包括：所述将第一离子沿所述宽禁带半导体材料的沟道效应最明显的晶向注入所述沟槽的底部区域的步骤，包括：
将所述第一离子至少分两次注入，即分别以第一剂量、第一能量及第二剂量、第二能量沿所述碳化硅晶体的C轴方向注入所述沟槽的底部区域。
在上述第二方面的一种可能的实现中，上述制造方法还包括：所述第一剂量为5E13至5E14原子数每平方厘米，所述第一能量为500kev至1500kev；所述第二剂量为5E12至5E13原子数每平方厘米，所述第二能量为50kev至300kev。
在上述第二方面的一种可能的实现中，上述制造方法还包括：所述外延层包括第一外延层和第二外延层，其中，在所述宽禁带半导体衬底上生长具有所述第一导电类型的所述第一外延层，在所述第一外延层上生长具有所述第一导电类型的所述第而外延层。
在上述第二方面的一种可能的实现中，上述制造方法还包括：其特征在于，所述第一外延层的厚度小于所述第二外延层的厚度；所述第一外延层的掺杂浓度小于所述第二外延层的掺杂浓度。
在上述第二方面的一种可能的实现中，上述制造方法还包括：所述沟槽的底部及所述第二导电类型柱位于所述第二外延层内，所述第二导电类型柱的纵向深度不小于位于所述沟槽的底部区域的所述第二外延层的厚度的50％。
在上述第二方面的一种可能的实现中，上述制造方法还包括：所述沟槽的深度和所述沟槽的宽度的比值范围为1:1至5:1。
在上述第二方面的一种可能的实现中，上述制造方法还包括：所述向所述沟槽中填入填充物填充所述沟槽的步骤，包括：
在所述沟槽的内表面形成氧化物后，向所述沟槽内填入填充物。
在上述第二方面的一种可能的实现中，上述制造方法还包括：所述填充物包括多晶硅。
在上述第二方面的一种可能的实现中，上述制造方法还包括：所述第一离子包括铝离子。
与现有技术的沟槽型超级结MOSFET相比，本发明的沟槽栅功率MOSFET在沟槽下引入了第二导电类型柱，例如深P柱，既起到对沟槽底部的保护作用，作为超级结处的p柱，又能起到电荷平衡作用。同时，特征导通电阻Rsp得以降低，从而可以降低芯片面积和功率MOSFET的寄生电容，以及功率MOSFET在功率转换过程中的开关损耗。
根据本发明的制造方法，深P柱由高能离子注入形成。不同于现有技术中沿晶圆法向进行离子注入，本发明的制造方法中沿半导体材料的特定晶向进行离子注入(碳化硅晶圆情况下沿其c轴注入)，利用晶体的沟道效应，在同样的注入深度的情况下，注入能量范围 在数十Kev到一千多Kev，相比现有技术可以大大降低注入能量，从而得以大幅降低制造成本，制造程序也更容易控制。
此外，本发明中，沟槽的长度方向设置为与上述特定晶向在晶圆表面的投影相平行，从而能够形成对称的P柱结构。如本领域技术人员所知，超级结的结构需要对称的P柱结构，不对称的结构会引起电场分布不均匀，从而容易引起MOSFET器件的局部击穿，降低器件的耐压能力。
附图说明
图1示出了传统工艺生产的一种平面结构的功率MOSFET的结构示意图。
图2示出了传统工艺生产的一种沟槽型的功率MOSFET的结构示意图。
图3示出了英飞凌公司的一种沟槽型的功率MOSFET的结构示意图。
图4示出了罗姆公司的一种沟槽型的功率MOSFET的结构示意图。
图5示出了碳化硅晶圆中，常见的碳化硅晶体与碳化硅晶圆表面的角度关系示意图。
图6示出了按图5所示方向切割碳化硅晶圆的情况下，现有的沿C轴进行离子注入，从而得到非轴对称的P柱的沟槽型的功率MOSFET的结构示意图。
图7根据本申请的一些实施例，示出了一种沟槽栅功率MOSFET结构的横剖面的示意图。
图8a根据本申请的一些实施例，示出了图7所示的示意图的45°俯视时的立体示意图。
图8b示出了图8a中的P柱连接体在制造过程中的掩膜图形的示意图。
图8c根据本申请的另一些实施例，示出了另一种P柱连接体示意图。
图9a根据本申请的一些实施例，示出了一种沟槽栅功率MOSFET的沟槽的设置方向。
图9b根据现有技术，示出了一种沟槽的设置方向。
图10根据本申请的一些实施例，示出了一种沟槽栅功率MOSFET结构中的碳化硅晶体的C轴与晶圆表面的坐标系之间的关系示意图。
图11根据本申请的一些实施例，示出了一种沟槽栅功率MOSFET的制造方法的流程图。
具体实施方式
本申请的说明性实施例包括但不限于沟槽栅功率MOSFET及其制造方法。
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。
应当理解，尽管在本申请可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本申请范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。
下面将结合附图对本申请的实施例作进一步地详细描述。
图1示出了传统工艺生产的一种平面结构的MOSFET的结构示意图(剖面图)。图1所示的MOSFET包括重掺杂的N型衬底101，形成于衬底101之上的轻掺杂的N型外延层102，形成于外延层102之上的P型体区103，位于P型体区103内的源极104及位于P型体区103上的多晶硅栅极105。平面型的MOSFET，其栅极、源极和漏极均在同一位面因此可以集成于平面，但是对其尺寸会有较大的限制，并且性能不够好。
图2示出了传统工艺生产的一种沟槽型的MOSFET的结构示意图(剖面图)。图2所示的MOSFET包括重掺杂的N型衬底201，形成于衬底201之上的轻掺杂的N型外延层202，形成于外延层202之上的P型体区203，位于P型体区203内的源极204，在P型体区203内蚀刻的沟槽205，在沟槽205内壁生长的栅氧化膜206及在栅氧化膜206上淀积的多晶硅207。与图1所示的平面结构的MOSFET相比，图2所示的沟槽型的MOSFET没有JFET区域，沟槽侧壁上的垂直沟槽可以使沟槽间距变小。但是由于碳化硅等宽禁带半导体的临界电场是硅的10倍，沟槽底部区域的电场强度较大。半导体中的这种高电场会导致沟槽氧化物上产生高电场，从而导致器件的可靠性问题。
图3示出了英飞凌公司的一种沟槽型的MOSFET的结构示意图(剖面图)。图3所示的MOSFET包括重掺杂的N型衬底301，形成于衬底301之上的轻掺杂的N型外延层302，形成于外延层302之上的P型体区303，在P型体区303内蚀刻的沟槽304，在沟槽304内壁生长的栅氧化膜306及在栅氧化膜306上淀积的多晶硅305。与图2所示的沟槽型的MOSFET相比，图3所示的沟槽型的MOSFET还包括在沟槽304下方重掺杂的第一P型区域307和第二P型区域308，以减轻沟槽304底部的高电场，该P型区域的纵向深度大于P型体区的纵向深度。
图4示出了罗姆公司的一种沟槽型的MOSFET的结构示意图(剖面图)。图4所示的MOSFET包括重掺杂的N型衬底401，形成于衬底401之上的轻掺杂的N型外延层402，形成于外延层402之上的P型体区403，在P型体区403内蚀刻的沟槽406，在沟槽406内壁生长的栅氧化膜407及在栅氧化膜407上淀积的多晶硅408。与图2所示的沟槽型的MOSFET相比，图4所示的沟槽型的MOSFET还包括在沟槽406下方重掺杂的第一P型区域404和第二P型区域405，以减轻沟槽406底部的高电场，第一P型区域404及第二P型区域405分别位于沟槽406的两侧，且第一P型区域404及第二P型区域405的纵向深度小于其所在的P型体区的纵向深度。但如图3和图4所示的沟槽型的MOSFET结构制造成本高，过程控制难度大。
对于沟槽型MOSFET器件，其源漏导通电阻Rds(on)由以下几部分组成：
Rds(on)＝RN++RCH+RD+Rsub
其中，RN+为源区N+扩散区电阻，由于N+区掺杂浓度高，所以电阻很小，因此这一部分电阻相对于组成源漏导通电阻Rds(on)的其它电阻而言是可以忽略的。
RCH为沟槽电阻，即栅极下沟槽电阻，RCH是组成源漏导通电阻Rds(on)的重要参数，沟槽宽长比、栅氧厚度和栅极电压的变化都能够影响RCH的变化。
RD为漂移区电阻，即外延层的电阻。外延层是在衬底上生长的一层高阻层，以承受高压，在外界电压的作用下，载流子在漂移区中作漂移运动，对于高压MOSFET器件，漂移电阻是决定源漏导通电阻Rds(on)最为重要的因素。因此，降低漂移区电阻RD则可以使得源漏导通电阻Rds(on)降低。
Rsub为晶圆衬底电阻，这个阻值可以通过背面减薄等工艺过程来降低。
在相同的击穿电压下，由于特征导通电阻Rsp＝源漏导通电阻Rds(on)*芯片的有效面积，对于相同的源漏导通电阻Rds(on)，特征导通电阻Rsp越小，芯片的有效面积越小，进而使得功率MOSFET的寄生电容越低，从而可以降低功率MOSFET在功率转换过程中的开关损耗。
图5示出了碳化硅晶圆中，常见的碳化硅晶体与碳化硅晶圆表面的角度关系示意图，即微观的晶体与宏观的晶圆之间的角度关系。图中示出了晶圆表面的的X方向和垂直于晶圆表面的Y方向(即法线方向)，以及碳化硅(4H-SiC)晶体的两个相互垂直的晶向[0001]方向和方向。众所周知，晶体从微观角度来看，是由大量微观物质单位(原子、离子、分子等)按一定规则有序排列的结构，因此，晶体通常具有特定形状，根据形状的不同，可以定义晶体的晶轴、晶向、晶面。例如，碳化硅(4H-SiC)晶体至少定义了如图所示的两个晶向：C轴方向(即[0001]方向)和方向。在半导体行业中，为了使生产过程中的晶体生长更为稳固，通常在切割晶圆的时候，选择如图5所示的晶体方向，即晶体的轴向(C轴)与晶圆表面的法线方向(Y向)之间存在一夹角，通常，该夹角为4°，并且，晶体的一个晶向，即方向在晶圆表面的投影与晶圆的X方向重合。然而，在生产实践中，有时为了便捷，也会忽略该夹角，直接以晶体的晶向和镜面来指代晶圆表面的方向等。
图6示出了按图5所示方向切割碳化硅晶圆的情况下，现有的沿C轴进行离子注入，从而得到非轴对称的P柱的沟槽型的功率MOSFET的结构示意图(剖面图)。图示的沟槽型的功率MOSFET包括衬底01，在衬底01之上通过外延生长之类的工艺形成的外延层02，在外延层02上形成的P型体区04，以及穿透P型体区04，深入到外延层02中的沟槽00。 P柱位于沟槽00的下方，埋于外延层02中，通常是通过离子注入的方式来形成的。为了利用沟道效应，通常会选用沟道效应最明显的晶向作为离子注入的方向。在碳化硅(4H-SiC)晶体中，C轴的方向是沟道效应最明显的晶向。根据图5的示意可知，碳化硅的C轴并非是垂直于晶圆的表面的，也就是说，在图6所示的结构中，通过离子注入形成的P柱11也不能与晶圆表面垂直。也就是说，在如图6所示的一个元包(unit cell)的剖面图中，P柱11不能关于该元包的中轴线对称。作为本领域中的一个常识，本领域的技术人员应知，在图6所示的剖面中，当P柱的形状为轴对称的图形时，MOSFET器件的性能最佳。然而按现有技术进行离子注入所能得到的P柱11的剖面如图6所示，为平行四边形，其关于元包的中轴线不对称，这容易导致MOSFET器件的击穿电压偏低。
为了解决上述的缺陷，本发明提出了一种新的沟槽栅功率MOSFET的结构，以下结合图7和图8a、8b来说明。图7根据本申请的一些实施例，示出了一种沟槽栅功率MOSFET结构的横剖面的示意图。图8a根据本申请的一些实施例，示出了图7所示的MOSFET的45°俯视时的立体示意图。图8b示出了图8a中的P柱连接体505在制造过程中的掩膜图形的示意图。
需要说明的是，本发明提供的沟槽栅功率MOSFET包括具有沟槽栅和超级结(或准超级结)结构的功率MOSFET。下面以宽禁带半导体衬底为碳化硅材料、第一导电类型为N型、第二导电类型为P型、第二导电类型柱为P柱、第一离子为铝离子为例，对本申请的具有沟槽栅功率MOSFET的结构以及形成过程进行具体说明。
如图7所示，衬底501是具有第一导电类型的宽禁带半导体的衬底。例如，衬底501可以是重掺杂的N型碳化硅衬底。在衬底501上方依次是通过外延生长工艺生长的轻掺杂的N型第一外延层502和第二外延层503。其中，第一外延层502位于第二外延层503的下方，第一外延层502的厚度小于第二外延层503的厚度，并且第一外延层502的掺杂浓度小于第二外延层503的掺杂浓度。在一个实施例中，第一外延层502的N型掺杂浓度在1E14atoms/cm2(原子数每平方厘米)至2E16atoms/cm2之间，第一外延层502的厚度在0.2μm至40μm之间；第二外延层503的N型掺杂浓度在2E15atoms/cm2至2E17atoms/cm2之间，第二外延层503的厚度在2μm至200μm之间。可以理解第一外延层502的厚度、掺杂浓度及第二外延层503的厚度、掺杂浓度可以根据器件所需的耐压额定值确定。本实施例中，采用两个掺杂浓度不同的外延层可以形成准超级结器件，增强雪崩耐量。
可以理解，在图7所示的实施例中，宽禁带半导体衬底为碳化硅材料是示例性的，并 非限制性的。在本申请其他实施例中，宽禁带半导体衬底还可以为其他宽禁带半导体材料，例如氮化镓、氮化铝等。而对于本发明来说，选择不同衬底材料的差别在于，基于不同晶圆(体)的晶向的不同，而选择不同的沟槽设置方向和离子注入方向。
可以理解，N型掺杂的第一外延层502和第二外延层503的掺杂的杂质可以为氮或磷，也可以为其他N型杂质。
P体区504位于在第二外延层503上方，可以通过在第二外延层503上端注入与衬底501、第一外延层502和第二外延层503不同的导电类型的离子，例如P型离子来形成。
P柱连接体505通过离子注入的工艺在P体区504(P体区)和第二外延层503内形成。具体的，首先通过光刻掩模工艺在P体区504上表面形成提示P柱连接体505的掩模图形5051，如图8b所示。该掩模图形关于P体区504上表面的中轴线(参见图8b所示)对称。然后通过离子注入工艺在该区域内向P体区504和第二外延层503方向注入P型杂质，从而形成柱状的P柱连接体505。该P柱连接体505实现P柱511到的P体区504连接，从而使得将在后续步骤种生成的P柱511与P体区504实现电连接，并且在任何工作状态都不会电学浮空。也就是说，P柱连接体505的深度需要从P体区504的上表面开始一直深入到第二外延层503中，这样，当沟槽栅功率MOSFET加工完成后，埋于第二外延层503中的P柱511才能通过竖向(指图7和图8a、8b中的竖向)的P柱连接体505与横向(指图7和图8a、8b中的横向)的P体区504电连接。
在P体区504(包括P柱连接体505)的上方继续注入离子，以形成欧姆接触电阻部分。例如，在P体区504的中间段，即包括P柱连接体505的部分注入N型重掺杂杂质，得到N型重掺杂区506，即图7中标注为S的部分，以利形成较低的源欧姆接触电阻。又如，在P体区504的两端，即与N型重掺杂区506的两端相连接的位置处，注入P型重掺杂杂质，得到第一P型重掺杂区507和第二P型重掺杂区508，以利形成较低的P体(即P体区504)欧姆接触电阻。
结合图8b所示，在P体区504表面的中轴线两侧形成用于加工沟槽500的硬掩模层图形5002，该掩膜图形沿中轴线方向不连续，而是与前述的P柱连接体505的掩模图形5051互补。当后续根据该硬掩模图形进行刻蚀后，沟槽500的硬掩模层图形5002下的P体区504和部分第二外延层503被刻蚀掉，形成沟槽500，而P柱连接体505的掩模图形5051下的P柱连接体505被保留，作为P柱511与P体区504之间电连接的导体。在一些实施例中，硬掩模层的成分可以为二氧化硅或镍。可以理解，在其他实施例中，硬掩模层 的成分可以为其他元素或化合物。
具体的，如图8a所示，沟槽500的底部5001位于第二外延层503内。沟槽500的深度和宽度的比值范围可以为1:1至5:1，例如，沟槽500的宽度为0.4μm，深度为1.2μm。在一些实施例中，沟槽500的深度和宽度的比值为3:1。可以理解，在图示实施例中，沟槽500的宽度和深度是示例性的，并非限制性的，在本申请的其他实施例中，沟槽500的宽度和深度可以为其他值。
以下结合图9a、9b来进一步说明沟槽500的方向问题。
图9a、9b中的第一图形72和第二图形72’用来说明沟槽与晶圆71的位置关系。第一图形72、第二图形72’中，阴影部分用来示意沟槽500，尤其是用来示意沟槽500的长度方向与晶圆71的晶面之间的关系。晶圆71表面示意了多个晶向(方括号所示)和晶面(圆括号所示)，根据上文的说明可知，碳化硅晶圆表面与碳化硅晶体的轴向并非直角关系，图示中的晶圆表面的各方向实际是碳化硅晶体各晶向在晶圆表面的投影，行业内为了便于叙述，通常直接用晶体的各晶向来指称晶圆表面的各方向。
一个晶圆71上可以刻蚀出很多沟槽500，这些沟槽的方向都是相同的。现有技术中，默认如图9b所示的方向来刻蚀沟槽，即沟槽的长度方向垂直于晶面如图9b中的第二图形72’所示。经过本发明的研究人员的分析，这样的沟槽方向是导致图6所示的平行四边形的P柱出现的根本原因。
因此，本发明调整了行内默认的沟槽设置方向，使得沟槽的长度方向与晶圆(体)的一个选定的晶向在晶圆表面的投影相平行。因为C轴既是沟道效应明显的晶向，也是目前SiC晶圆制作方法下跟晶圆法线偏角最小的晶向，本申请的沟槽设置方向要确保沟槽的长度方向跟C轴和晶圆法线形成的平面是平行的，这样沿C轴的注入才不会由于沟槽侧壁以及掩模的影响造成屏蔽效应(shielding effect)。具体而言，根据本申请的实施例，选定的晶向是晶圆所有晶向中沟道效应最明显的晶向，也就是离子注入时可达到的最深深度的方向。例如如图9a中的第一图形72所示，选择C轴在晶圆表面的投影方向。这一改变有利于后续进行离子注入时形成对称的P柱，例如图9a中沿C轴(穿透纸面向外)注入离子时形成对称的P柱511。具体的分析，可参看后文关于图10的说明。
回到图8a。按图中所示的离子注入方向，也就是碳化硅的C轴方向向沟槽500的底部注入离子，可以得到剖面图形对称的P柱511。在一些实施例中，将铝离子(例如Al-27) 以第一能量为500kev至1500kev、第一剂量为5E13atoms/cm2至5E14atoms/cm2，及第二能量为50kev至300kev、第二剂量为5E12atoms/cm2至5E13atoms/cm2，沿着碳化硅的C轴方向(对于4H-SIC，离子注入的方向和4H-SIC晶圆的法线方向的夹角为4度)注入沟槽500的底部区域，实现碳化硅里的深度均匀掺杂，以形成P柱511。由于沟槽效应，可以使得铝离子注入足够深的深度，获得足够深的P柱511，大大降低离子注入的次数和注入能量，降低制造成本。其中，P柱511的深度不小于位于沟槽500的底部之下第二外延层503的厚度的50％，P柱511位于第二外延层503内，P柱511和N型轻掺杂的第二外延层503形成准超级结结构。使得P柱511和P体区504实现宽度方向上的连接。
在另外一个实施例中，P柱连接体505也可以在沟槽500刻蚀完成后，向沟槽500的侧壁注入离子来实现。参考图8c，沟槽500沿元包(unit cell)的中轴线连续刻蚀，而不是如图8b所示的断续的刻蚀。刻蚀的深度穿透P体区504达到第二外延层503中。形成沟槽500后，在沟槽500的侧壁上向侧壁内部进行离子注入，从而在两侧壁上形成具有一定厚度的P柱连接体505。该组P柱连接体505的深度至少与沟槽500的深度相同，从而可以与后续生成的P柱511(P柱511通过离子注入的工艺生成于沟槽500的底部，与沟槽500的底部连接)实现电连接。同时，因为P柱连接体505的一部分生成于P体区504中，因此，通过P柱连接体505可以有效地使P体区504和P柱511实现电连接。
图10示出了晶圆上表面的XYZ坐标系的示意，其中，X方向和Y方向与晶圆表面平行，Z方向垂直于晶圆表面。同时，图10中还示出了碳化硅晶体的多个晶向和晶面。其中，晶体的方向示意图略有偏转，以示晶体与晶圆之间存在夹角。结合图5所示的碳化硅晶圆的切割方式可知，碳化硅的晶面与XY平面平行，晶向在晶圆表面的投影x与X轴平行，C轴在YZ平面上的投影Cy与Y轴平行。如前所述，晶体与晶圆之间存在夹角，该夹角约为4°。由于存在该夹角，当沟槽的长度方向垂直于XY平面时，即沟槽的长度方向平行于Z轴时(如图9b所示)，沿C轴注入沟槽底部的离子在沟槽底部区域能够形成的只能是近似于平行四边形的非轴对称的P柱。如前所述，P柱的优选方案是对称(轴对称)图形，剖面为平行四边形的P柱带来较多隐患，容易导致器件击穿、失效等情况。
本发明将行业内默认的沟槽方向转了90°，使得沟槽的长度方向如图9a所示，即沟槽长度方向与X轴平行。根据以上的分析可知，沿C轴注入的离子可以理解为沿Y轴(即垂直于晶圆的Cy方向)和沿X轴(即平行于晶圆的x方向)两个方向分别注入。 其中，X方向是沟槽的长度方向，沿这个方向注入离子不会影响P柱511在沟槽500的宽度方向上的剖面形状。因此，本实施例中，离子注入的范围没有超出预计的范围，从图8a所示的剖面来看，P柱511可以形成对称的近似于矩形结构，相对图9b所示的现有技术，本发明可以提高沟槽型的MOSFET的稳定性和可靠性。
相对于图1所示传统工艺生产的平面结构的MOSFET，本申请的沟槽型的MOSFET可以提高耐压能力。并且，足够深的P柱511可以使得第二外延层503的掺杂浓度提高，降低漂移区电阻RD，从而降低导通电阻Rds(on)。
可以理解，上述将铝离子(例如Al-27)注入碳化硅中的注入次数、对应的能量和剂量的数值是示例性的，并非限制性的，在本申请的其他实施例中，可以根据需要注入的深度选择注入的次数、对应的能量和剂量。
可以理解，此处将铝离子(例如Al-27)从4H-SIC晶圆的C轴方向注入是示例性的，并非限制性的，在本申请的其他实施例中，可以将其他导电类型为P型的离子沿着其他宽禁带半导体的晶向注入第二外延层，以利用晶体沟槽效应，以较低的注入能量实现较深的注入深度。
此后，再经过高温退火激活第二外延层503中注入的离子、在沟槽500的内表面形成二氧化硅后，再向沟槽500内淀积多晶硅，形成多晶硅栅、在多晶硅栅上生长二氧化硅绝缘层515、以及常规的欧姆接触工艺、金属化工艺等步骤，形成电极(源极S和栅极G)。本申请最终形成的沟槽栅准超级结结构的功率MOSFET的结构如图7所示。
本申请实施例还提供一种沟槽栅超级结结构的功率MOSFET(未图示)，其结构和制备方法和上述沟槽栅准超级结结构的功率MOSFET类似，相比较于沟槽栅准超级结结构的功率MOSFET，区别仅在于：沟槽栅超级结结构的MOSFET在制备过程中，只需要单层外延，并且，其中所形成的p柱的深度要不小于位于沟槽的底部以下区域的该外延层厚度的50％，则P柱和该外延层形成超级结结构。详细描述请参见上文，在此不再赘述。
图11根据本申请的一些实施例，示出了一种沟槽栅功率MOSFET的制造方法的流程示意图，具体地，如图11所示，本申请的沟槽栅功率MOSFET的制造方法包括：
1)在宽禁带半导体衬底上生长具有第一导电类型的外延层(902)。其中，宽禁带半导体衬底的材料可以为碳化硅、氮化镓、氮化铝、金刚石等。可以通过外延生成工艺在宽 禁带半导体衬底上形成外延层。第一导电类型的外延层为掺杂有第一导电类型元素的外延层。在一些实施例中，第一导电类型元素可以为氮、磷等元素，使得外延层为N型半导体(自由电子为多字，空穴为少子)。在一些实施例中，第一导电类型元素可以为硼、铝等三价元素，使得外延层为P型半导体(空穴为多子，自由电子为少子)。可以理解，第一导电类型为P型还是N型可以根据实际需要进行选择，在此不做限定。
2)在外延层上形成具有第二导电类型的体区(904)。其中，第二导电类型的体区为掺杂有第二导电类型元素的体区。第二导电类型与第一导电类型不同，例如第一导电类型为N型，则第二导电类型为P型；若第一导电类型为P型，则第二导电类型为N型。可以理解，第一导电类型和第二导电类型可以根据实际需要进行确定，在此不做限定。
在一些实施例中，可以通过离子注入工艺向外延层注入第二导电类型元素，以形成第二导电类型的体区。
3)在体区内通过刻蚀形成沟槽(906)。为了在后续的注入离子以得到剖面对称的第二导电类型柱，可以使离子注入方向与沟槽的方向相匹配。所述匹配可以包括离子注入方向垂直于沟槽的底面，也可以包括离子注入方向可以分解为：垂直于沟槽底面的方向和平行于沟槽的长度方向。基于离子注入方向通常都选择沟道效应最明显的晶向，若该沟道效应最明显的晶向垂直于晶圆表面，则沟槽可以在晶圆表面任意设置，离子注入方向始终可以垂直进入沟槽的底部；若该沟道效应最明显的晶向不垂直于晶圆表面，则该沟道效应最明显的晶向可以分解为平行于晶圆表面的X方向和垂直于晶圆表面Y方向，沟槽的长度方向可以设置为与所述X方向相平行的的方向。
例如，在一些实施例中，沟槽的长度方向设置为如图9a所示的垂直于晶圆71的晶面的方向，即沟槽的长度方向平行于晶向(或者更准确的说，平行于晶向 在晶圆上的投影)，而不设置为如图9b中所示的方向。并且，为了使后续形成的P柱511与P体区504保持电连接，在沟槽500的底部5001和P体区504之间还可通过离子注入的方式形成P柱连接体505。
形成P柱连接体505有两种方式。
其一，先形成P柱连接体505。可参考图8a、8b所示来理解。在形成具有第二导电类 型的体区，例如P体区504后，在P体区504的上表面的中轴线(图8b所示)的两侧制备出如图所示的P柱连接体505的掩模图形5051的区域，然后在该区域内，向P体区504及第二外延层503中注入P型离子，以得到P柱连接体505。离子注入的深度要大于沟槽500的深度，即深度要达到P柱511的区域中，从而可以通过P柱连接体505实现P体区504与后续将加工出来的P柱511之间的电连接。然后按图8b所示的用于加工沟槽的硬掩模层图形5002的区域通过蚀刻工艺在P体区504及第二外延层503中形成沟槽500，并且可以控制沟槽的深度和宽度。本领域技术人员可以理解，图8b中所示的P柱连接体505的掩模图形5051的位置可以位于中轴线的任何位置，或者，在一个元包(unit cell)中，可以出现多个，类似的设置在此处不多赘述。
在一些实施例中，可以通过干式刻蚀技术对体区进行刻蚀以形成沟槽。在一些实施例中，可以通过湿刻技术对体区进行刻蚀以形成沟槽。可以理解，可以根据实际情况选择采用干刻还是湿刻的方式刻蚀形成沟槽，在此不做限定。
进一步地，为了保证P体区504与P柱511之间的有效的电连接，还可以在P柱连接体505附近的侧壁上增加P型离子注入，从而使得P柱连接体505与P体区504充分连接，从而可以形成有效的P-型连接，避免后续将加工出来的P柱511的电学浮空。
在另一些实施例中，也可以在进一步形成第一P型重掺杂区507和第二P型重掺杂区508和N型重掺杂区506之后，才在器件表面的中轴线两侧用掩模的方式圈出P柱连接体505的区域(参考图8a)，然后进行离子注入工艺，从而在P体区504和第二外延层503中形成P柱连接体505。
其二，后形成P柱连接体505。可参考图8a、8c所示来理解。相对于上述的沟槽500是断续的情况，后形成P柱连接体505可以得到连续的沟槽500。即图8c所示的实施例中，没有横亘在沟槽500中的P柱连接体，可以稍微降低沟槽刻蚀的复杂度。在形成具有第二导电类型的体区，例如P体区504后，按常规工艺在P体区504及第二外延层503中刻蚀出如图所示的沟槽500，然后在沟槽500的两侧的侧壁上进行离子注入，在侧壁上形成一定厚度的P离子重掺杂区域，以形成一组P柱连接体505。换个角度来说，可以理解为将通过前一方法制造的P柱连接体嵌入到沟槽500的两侧壁中。同理，为了保证P体区504与P柱511之间的有效的电连接，可以在P柱连接体505与沟槽500底部的连接处还向下 进行离子注入，以使得P柱连接体505与后续将加工出来的P柱511可以更可靠的电连接。
由于本领域公知，P柱优选为对称形状，而非对称的P柱不利于减小超级结中的电场强度，而电场强度过大容易导致器件击穿。因此，本申请打破行业习惯，在x方向(参考图10所示)上刻蚀沟槽。结合图7及图8a、8b、8c的说明可知，P柱511是设置在沟槽500下方的、与沟槽500的形状和尺寸相匹配的矩形结构。只有当沟槽500的长度方向与方向相平行时，碳化硅(4H-SiC)的C轴方向在晶圆表面的投影才是x方向，进而在执行后续的离子注入的步骤时，得到的P柱的横剖面才是对称的类矩形，而不是如一些现有技术那样得到横剖面为类平行四边形的P柱。
4)将第一离子沿宽禁带半导体材料的晶向注入沟槽的底部区域，形成第二导电类型柱，沟槽的底部区域位于沟槽下方且与沟槽的底部相接，所述晶向的选取应使得第一离子的注入能够充分利用晶体沟槽效应(908)。如此，当第一离子沿着半导体的晶向注入时，由于沟槽效应，使得第一离子的射程比随机方向或沿晶圆法向射入时显著增加，具有更强的穿透作用，从而可以大大降低第一离子注入的能量，降低制造成本。在一些实施例中，宽禁带半导体材料为六方晶系宽禁带半导体材料(例如碳化硅、氮化镓等)，晶向是指六方晶系宽禁带半导体材料的垂直晶面(即C轴方向)。在一些实施例中，宽禁带半导体材料为碳化硅，则宽禁带半导体材料的晶向选取为碳化硅的C轴方向，其中C轴方向与碳化硅晶圆的法线方向呈一定夹角。在一些实施例中，宽禁带半导体材料为4H-SIC或6H-SiC，则其C轴方向与4H-SIC或6H-SiC晶圆的法线方向的夹角为4度。可以理解，对于其他类型的碳化硅晶圆，则对应的C轴方向与对应的晶圆的法线方向的夹角可以为其他数值，在此不做限定。
其中，第二导电类型柱的纵向深度至少不小于位于沟槽的底部区域的外延层的厚度的50％。在一些实施例中，外延层为单外延层，第二导电类型柱的纵向深度至少不小于位于沟槽的底部区域的外延层的厚度的50％。在一些实施例中，外延层包括第一外延层和第二外延层，第一外延层位于第二外延层的下方；沟槽的底部及第二导电类型柱位于第二外延层内，且第二导电类型柱的纵向深度至少不小于位于沟槽的底部区域的第二外延层的厚度的50％。
5)向沟槽中填入填充物填充沟槽(910)。在一些实施例中，可以在沟槽的内表面形 成氧化物(例如二氧化硅)后，向沟槽内填入填充物。其中，向沟槽内填入填充物可以为向沟槽内进行多晶硅淀积。
在一个实施例中，采用TCAD(一种半导体工艺/器件模拟工具)设计间距为2.4um的沟槽碳化硅MOSFET，特征导通电阻Rsp可达0.2欧姆每平方厘米。考虑沟槽迁移率和碳化硅衬底厚度(假设碳化硅衬底厚度为180um)，将器件的特征导通电阻Rsp修正为0.896欧姆平方厘米，器件的击穿电压为950V(额定电压为750V或650V)备。碳化硅超级结MOSFET具有典型的静态输出电容Coss曲线，当源漏电压Vds增大时，静态输出电容Coss显著减小，该特性使得对静态输出电容Coss的曲线积分Qoss更小(有利于软开关)，且使得静态输出电容Coss产生的功耗更小(有利于硬开关)。相比较于相关技术中的传统工艺制备的碳化硅器件或硅器件，本申请具有沟槽栅和超级结(或准超级结)结构的功率MOSFET制备方法制备的具有沟槽栅和超级结(或准超级结)结构的MOSFET在相同的击穿电压下，可以有更薄的外延层，更低的特征导通电阻，且器件稳定性高。
另外，在一个对比实验例中，以将P型杂质Al-27注入到2e16cm-3的碳化硅外延层中为例，将功率MOSFET的现有技术常规工艺与本申请的方法进行实验比对。在杂质总剂量选取为1E14每平方厘米的情况下，以本发明的制造方法，在500Kev的能量条件下注入Al-27，而以现有技术制造方法则在3.3Mev的能量条件下进行注入。两者相比较，本发明的技术方案所能所达到的第二导电类型柱的深度更深。可见，本发明的制造方法能够以低得多的注入能量实现现有技术下高能量条件下的注入深度，在低注入能量状况下的制造过程控制更为容易。
需要说明的是，在本专利的示例和说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
虽然通过参照本申请的某些优选实施例，已经对本申请进行了图示和描述，但本领域的普通技术人员应该明白，可以在形式上和细节上对其作各种改变，而不偏离本申请的精 神和范围。

Claims (17)

  1. 一种沟槽栅功率MOSFET，其特征在于，所述沟槽栅功率MOSFET形成于一个晶圆中，包括：
    衬底，所述衬底是具有第一导电类型的宽禁带半导体材料的衬底；
    外延层，所述外延层在所述衬底上生长，且具有所述第一导电类型；
    体区，所述体区在所述外延层上形成，且具有第二导电类型；
    沟槽，所述沟槽在所述体区内刻蚀形成，所述沟槽的长度方向平行于所述晶圆的所有晶向中沟道效应最明显的晶向在所述晶圆表面的投影；
    第二导电类型柱，所述第二导电类型柱通过将第一离子沿宽禁带半导体材料的所述沟道效应最明显的晶向注入所述沟槽的底部区域而形成，所述沟槽的底部区域位于所述沟槽下方且与所述沟槽底部相接，所述第二导电类型柱的纵向深度不小于位于所述沟槽的底部区域的所述外延层的厚度的50％；
    沟槽栅，所述沟槽栅通过向所述沟槽中填入填充物而形成。
  2. 根据权利要求1所述的沟槽栅功率MOSFET，其特征在于，所述第二导电类型柱与所述体区之间还包括具有所述第二导电类型的连接体，所述连接体一端与所述体区电连接，所述连接体的另一端与所述第二导电类型柱电连接。
  3. 根据权利要求1所述的沟槽栅功率MOSFET，其特征在于，还包括：位于所述衬底下方的漏极、位于所述体区的中轴线上的栅极、位于所述栅极两侧的源极。
  4. 根据权利要求1所述的沟槽栅功率MOSFET，其特征在于，所述外延层为单外延层。
  5. 根据权利要求1所述的沟槽栅功率MOSFET，其特征在于，所述外延层包括第一外延层和第二外延层，所述第一外延层位于所述第二外延层的下方；所述第一外延层的厚度小于所述第二外延层的厚度；所述第一外延层的掺杂浓度小于所述第二外延层的掺杂浓度；所述沟槽的底部及所述第二导电类型柱位于所述第二外延层内，所述第二导电类型柱的纵向深度不小于位于所述沟槽的底部区域的所述第二外延层的厚度的50％。
  6. 根据权利要求4或5所述的沟槽栅功率MOSFET，其特征在于，所述宽禁带半导 体材料为碳化硅。
  7. 根据权利要求1所述的沟槽栅功率MOSFET，其特征在于，所述沟槽的深度和所述沟槽的宽度的比值范围为1:1至5:1。
  8. 根据权利要求6所述的沟槽栅功率MOSFET，其特征在于，所述第一离子包括铝离子，所述第一离子至少分两次注入，即分别以第一剂量、第一能量及第二剂量、第二能量沿所述碳化硅晶体的C轴方向注入所述沟槽的底部区域。
  9. 一种沟槽栅功率MOSFET的制造方法，其特征在于，在晶圆中生成所述沟槽栅功率MOSFET，包括：
    在宽禁带半导体材料衬底上生长具有第一导电类型的外延层；
    在所述外延层上形成具有第二导电类型的体区；
    在所述体区内通过刻蚀形成沟槽，所述沟槽的长度方向平行于所述晶圆的所有晶向中沟道效应最明显的晶向在所述晶圆表面的投影；
    将第一离子沿宽禁带半导体材料的所述沟道效应最明显的晶向注入所述沟槽的底部区域，以形成第二导电类型柱，所述沟槽的底部区域位于所述沟槽下方且与所述沟槽的底部相接，并且所述第二导电类型柱的纵向深度不小于位于所述沟槽的底部区域的所述外延层的厚度的50％；
    向所述沟槽中填入填充物填充所述沟槽。
  10. 根据权利要求9所述的制造方法，其特征在于，还包括，向所述体区和所述外延层注入第一离子，以形成具有所述第二导电类型的连接体，所述连接体一端与所述体区电连接，所述连接体的另一端与所述第二导电类型柱电连接，并且所述连接体的深度大于等于所述沟槽的深度。
  11. 根据权利要求9所述的制造方法，其特征在于，所述宽禁带半导体材料为碳化硅；所述沟道效应最明显的晶向为碳化硅晶体的C轴。
  12. 根据权利要求11所述的制造方法，其特征在于，所述将第一离子沿所述沟道效应最明显的晶向注入所述沟槽的底部区域的步骤，包括：
    将所述第一离子至少分两次注入，即分别以第一剂量、第一能量及第二剂量、第二能 量沿所述碳化硅晶体的C轴方向注入所述沟槽的底部区域。
  13. 根据权利要求12所述的制造方法，其特征在于，所述第一剂量为5E13至5E14原子数每平方厘米，所述第一能量为500kev至1500kev；所述第二剂量为5E12至5E13原子数每平方厘米，所述第二能量为50kev至300kev。
  14. 根据权利要求9所述的制造方法，其特征在于，所述外延层包括第一外延层和第二外延层，其中，在所述宽禁带半导体材料衬底上生长具有所述第一导电类型的所述第一外延层，在所述第一外延层上生长具有所述第一导电类型的所述第二外延层。
  15. 根据权利要求14所述的制造方法，其特征在于，所述第一外延层的厚度小于所述第二外延层的厚度；所述第一外延层的掺杂浓度小于所述第二外延层的掺杂浓度。
  16. 根据权利要求14所述的制造方法，其特征在于，所述沟槽的底部及所述第二导电类型柱位于所述第二外延层内，所述第二导电类型柱的纵向深度不小于位于所述沟槽的底部区域的所述第二外延层的厚度的50％。
  17. 根据权利要求9所述的制造方法，其特征在于，所述沟槽的深度和所述沟槽的宽度的比值范围为1:1至5:1。
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