WO2024031286A1 - 一种数据处理方法、装置及设备 - Google Patents

一种数据处理方法、装置及设备 Download PDF

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Publication number
WO2024031286A1
WO2024031286A1 PCT/CN2022/110968 CN2022110968W WO2024031286A1 WO 2024031286 A1 WO2024031286 A1 WO 2024031286A1 CN 2022110968 W CN2022110968 W CN 2022110968W WO 2024031286 A1 WO2024031286 A1 WO 2024031286A1
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Prior art keywords
data
segment
matrix
encoded data
encoded
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English (en)
French (fr)
Inventor
童佳杰
张华滋
王献斌
李榕
王俊
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to EP22954266.7A priority Critical patent/EP4564684A4/en
Priority to JP2025507233A priority patent/JP2025529715A/ja
Priority to CN202280098384.8A priority patent/CN119547333A/zh
Priority to PCT/CN2022/110968 priority patent/WO2024031286A1/zh
Publication of WO2024031286A1 publication Critical patent/WO2024031286A1/zh
Priority to US19/047,769 priority patent/US20250183919A1/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/45—Soft decoding, i.e. using symbol reliability information
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/611—Specific encoding aspects, e.g. encoding by means of decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing

Definitions

  • the present application relates to the field of communication technology, and in particular, to a data processing method, device and equipment.
  • Polar code is a channel coding scheme that can be strictly proven to "reach" Shannon channel capacity. It has the characteristics of good performance and low complexity, and can be applied to the fifth generation (the 5th generation, 5G) communications. systems and future communication systems. Polar code is a linear block code that generates encoded data through the encoding matrix. The current encoding matrix of Polar codes determines that the device needs to receive complete data to be encoded or data to be decoded before it can start encoding or decoding.
  • This application provides a data processing method, device and equipment, which can realize stream encoding and/or stream decoding by designing a new Polar code encoding matrix.
  • this application provides a first data processing method, which can be executed by a terminal device or a network device.
  • the terminal device obtains the information bit sequence, encodes the information bit sequence according to the encoding matrix G, obtains encoded data, and then sends the encoded data.
  • the coding matrix G is expressed as:
  • the coding matrix G is a matrix of size (m ⁇ 2n) ⁇ (m ⁇ 2n), m and n are positive integers, the matrix G N′ is a Polar generating matrix of size 2 n ⁇ 2 n , and the matrix O is a size of 2 n ⁇ 2 n all-zero matrix.
  • a new Polar code encoding matrix G is designed.
  • the terminal device uses the encoding matrix G to encode the information bits to be encoded, it can receive a part of the information bits during the encoding process and then encode the part of the information bits. Encoding and sending the encoded data, that is, implementing stream encoding, helps reduce the size of the encoder and cache in the terminal device.
  • the encoding matrix is used to encode the information bits to be encoded to obtain encoded data, which is beneficial to realizing stream decoding.
  • the information bit sequence includes m segments, and the Polar generating matrix of each segment is G N′ .
  • the information bit sequence can also be divided into m segments, and each segment is subjected to a modular square operation with the matrix G N′ .
  • the number of information bits in m segments is k 0 , k 1 ,..., k m-1 , where k 0 is less than k m-1 , and k 0 ⁇ k 1 ⁇ ... ⁇ k m-1 .
  • the number of information bits in the i-th segment is k i , and i satisfies 0 ⁇ i ⁇ m-1.
  • the number of information bits in each segment is different and changes according to a certain number.
  • m pieces of cached data are obtained, wherein the jth piece of cached data is obtained by encoding the jth segment of the information bit sequence using the matrix G N′ , j satisfies 0 ⁇ j ⁇ m -1;
  • the encoded data includes m segments, in which the 0th segment of encoded data is the m-1th cache data, the i-th segment of encoded data is obtained by XORing the jth cached data and the m-1th cached data, i Satisfies 1 ⁇ i ⁇ m-1, j satisfies 0 ⁇ j ⁇ m-2.
  • the m-1th piece of buffered data is first sent, and then the i-th piece of coded data is sent in sequence, 1 ⁇ i ⁇ m-1.
  • the encoded data is sent in the set order.
  • elementary column transformation is performed on the coding matrix G.
  • the transformed coding matrix And the information bit sequence is encoded according to the transformed encoding matrix G′ to obtain encoded data.
  • elementary column transformation is performed on the coding matrix G, so that when the terminal device uses the transformed coding matrix G′ to encode the information bits to be encoded, stream coding can also be achieved, which is beneficial to reducing the load of the encoder and cache in the terminal device. size.
  • the number of information bits in m segments is k 0 , k 1 ,..., k m-1 , k 1 is less than k 0 , and k 1 ⁇ ... ⁇ k m -1 ⁇ k 0 .
  • the number of information bits in the i-th segment is k i , and i satisfies 0 ⁇ i ⁇ m-1.
  • the encoder is based on the encoded data corresponding to the k 0 information bits received first, The remaining m-1 segments are encoded separately, which is beneficial to realizing stream encoding.
  • the encoded data includes m segments, wherein the 0th segment of encoded data is obtained by encoding the 0th segment of the information bit sequence according to the matrix G N′ ; the i-th segment of encoded data is obtained by encoding the 0th segment of the information bit sequence according to the matrix G N′ G N′ is obtained by encoding the i-th segment of the information bit sequence and then XORing it with the 0-th segment of coded data.
  • the encoded data corresponding to the m segments is also divided into m segments.
  • the 0th segment of encoded data is cached, and the 0th segment of encoded data is XORed with the remaining m-1 segments of encoded data (for example, information interleaving), thereby achieving the purpose of supporting stream encoding.
  • this application provides a second data processing method, which can be executed by a terminal device or a network device.
  • the terminal device taking the terminal device as the execution subject and the terminal device as the encoding side as an example, the terminal device obtains the information bit sequence, which includes m segments, and uses the Polar generation matrix G N′ of each segment to generate Process in segments to obtain m pieces of cached data, in which the matrix G N′ is a Polar generating matrix with a size of 2 n ⁇ 2 n . Then based on m copies of cached data, the encoded data is obtained and sent.
  • the encoded data includes m segments, in which the 0th segment of encoded data is the m-1th cache data, the i-th segment of encoded data is obtained by XORing the jth cached data and the m-1th cached data, i Satisfies 1 ⁇ i ⁇ m-1, j satisfies 0 ⁇ j ⁇ m-2.
  • the terminal device divides the information bit sequence to be encoded into m segments, and uses a Polar generation matrix of size 2 n ⁇ 2 n for each segment to perform encoding and information interleaving, and the encoded data is interleaved and sent , which is conducive to implementing stream decoding.
  • the number of information bits in m segments is k 0 , k 1 ,..., k m-1 , where k 0 is less than k m-1 , and k 0 ⁇ k 1 ⁇ ... ⁇ k m-1 .
  • the number of information bits in the i-th segment is k i , and i satisfies 0 ⁇ i ⁇ m-1.
  • the terminal device can encode the information bit sequence according to the encoding matrix G to obtain encoded data.
  • the coding matrix G is a matrix of size (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), m and n are positive integers, the matrix G N′ is a Polar generating matrix of size 2 n ⁇ 2 n , and the matrix O is the size is a 2 n ⁇ 2 n all-zero matrix.
  • a coding matrix based on the Polar generating matrix is designed, which is similar to constructing a coupling matrix of the Polar generating matrix, which is beneficial to realizing stream decoding under the coding matrix G.
  • this application provides a third data processing method, which can be executed by a terminal device or a network device.
  • the terminal device obtains the information bit sequence, which includes m segments, and uses the Polar generation matrix G N′ of each segment to generate Processing is performed in segments, and the encoded data is obtained and sent.
  • the matrix G N′ is a Polar generating matrix with a size of 2 n ⁇ 2 n .
  • the encoded data includes m segments.
  • the 0th segment of encoded data is the encoding of the 0th segment of the information bit sequence according to the matrix G N′. Obtained; the i-th segment of coded data is obtained by encoding the i-th segment of the information bit sequence according to the matrix G N′ , and then XORing it with the 0-th segment of coded data.
  • the terminal device divides the information bit sequence to be encoded into m segments, and uses a Polar generating matrix of size 2 n ⁇ 2 n for each segment for encoding and information interleaving, which can support the encoding process. After receiving a part of the information, the part of the information can be encoded and sent (that is, to achieve the purpose of supporting stream encoding), reducing the size of the encoder and cache.
  • the number of information bits in m segments is k 0 , k 1 ,..., k m-1 , k 1 is less than k 0 , and k 1 ⁇ ... ⁇ k m -1 ⁇ k 0 .
  • the number of information bits in the i-th segment is k i , and i satisfies 0 ⁇ i ⁇ m-1.
  • the terminal device can encode the information bit sequence according to the encoding matrix G′ to obtain encoded data.
  • the coding matrix G′ is a matrix of size (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), m and n are positive integers, the matrix G N′ is a Polar generating matrix of size 2 n ⁇ 2 n , and the matrix O is An all-zero matrix of size 2 n ⁇ 2 n .
  • a coding matrix based on the Polar generating matrix is designed, which is similar to constructing a coupling matrix of the Polar generating matrix, which is beneficial to realizing stream coding under the coding matrix G′.
  • the methods described in the first to third aspects above can also be executed by network devices.
  • the network device is the encoding side and the terminal device is the decoding side.
  • this application provides a fourth data processing method, which can be executed by a terminal device or a network device.
  • the network device receives the encoded data and decodes the encoded data to obtain the decoded data.
  • the coded data is obtained by coding the information bit sequence according to the coding matrix G.
  • the coding matrix G is a matrix of size (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), m and n are positive integers, the matrix G N′ is a Polar generating matrix of size 2 n ⁇ 2 n , and the matrix O is the size is a 2 n ⁇ 2 n all-zero matrix.
  • the encoded data is obtained based on a brand-new Polar code encoding matrix G designed in this application, after the decoding side receives the encoded data, it can support the decoding process after receiving part of the information. Partial information is decoded, reducing the size of the decoder.
  • the information bit sequence includes m segments, and the Polar generating matrix of each segment is G N′ .
  • the network device obtains the tag data corresponding to the 0th segment of encoded data and the tag data corresponding to the 1st segment of encoded data, and combines the tag data corresponding to the 0th segment of encoded data with the tags corresponding to the 1st segment of encoded data.
  • the 0th segment of encoded data includes the last N′ columns of the encoding matrix G, or the 0th segment of encoded data includes the elementary equation of the first (m-1) ⁇ 2 n columns and the last 2 n columns of the encoding matrix G.
  • the first N′ columns of the coding matrix G′ are obtained.
  • the first segment of encoded data includes the first N′ columns of the encoding matrix G, or the first segment of encoded data includes the first N′+1 columns to N′*2 columns of the encoding matrix G′.
  • the network device decodes the first received segment 0 encoded data and its adjacent segment 1 encoded data, thereby realizing stream decoding and enhancing the segment 0 encoded data to facilitate subsequent decoding.
  • stream decoding is implemented based on the enhanced 0th segment encoded data.
  • the network device continues to obtain the marked data corresponding to the q-th section of coded data, where q is 2 ⁇ q ⁇ m-1, and combines the marked data corresponding to the q-th section of coded data with the enhanced Perform F operation on the marked data corresponding to segment 0 encoded data to obtain the marked data corresponding to the qth segment encoded data after the F operation.
  • Decoded data corresponding to segment encoded data is enhanced based on the mark data corresponding to the qth segment coded data and the decoded data corresponding to the qth segment coded data.
  • the same method is used for decoding the second segment of coded data to the m-1th segment of coded data. Moreover, as the decoding proceeds, the mark data corresponding to the 0th segment of encoded data is continuously enhanced, which is beneficial to the implementation of stream decoding.
  • the method described in the fourth aspect above can also be executed by a terminal device.
  • the network device is the encoding side and the terminal device is the decoding side.
  • inventions of the present application provide a data processing device.
  • the data processing device may be a terminal device, a device in the terminal device, or a device that can be used in conjunction with the terminal device.
  • the data processing device may include performing the methods/operations/steps/actions described in any one of the first aspect to the third aspect, and any possible implementation manner of the first aspect to the third aspect.
  • the corresponding module can be a hardware circuit, a software, or a hardware circuit combined with software.
  • the data processing device may include a processing unit and a communication unit.
  • the terminal device For a specific description of the methods/operations/steps/actions performed by the terminal device, please refer to the corresponding descriptions in any one of the above-mentioned first to third aspects, and any possible implementation manner from the first to third aspects. Herein No further details will be given. It can be understood that the data processing device can also achieve the effects that can be achieved in the first to third aspects.
  • inventions of the present application provide a data processing device.
  • the data processing device may be a network device, a device in the network device, or a device that can be used in conjunction with the network device.
  • the data processing device may include a module that performs one-to-one correspondence with the methods/operations/steps/actions described in the fourth aspect and any one of the possible implementations of the fourth aspect.
  • the module may be hardware.
  • the circuit can also be software, or it can be implemented by hardware circuit combined with software.
  • the data processing device may include a processing unit and a communication unit.
  • embodiments of the present application provide a communication device.
  • the communication device is composed of an input-output interface and a logic circuit.
  • the input-output interface is used to input or output data;
  • the logic circuit is as in the first aspect to the third aspect. aspect, and the method in any possible implementation manner from the first aspect to the third aspect processes the data and obtains the processed data.
  • inventions of the present application provide a communication device.
  • the communication device is composed of an input-output interface and a logic circuit.
  • the input-output interface is used to input or output data; the logic circuit is as described in the fourth aspect and the fourth aspect.
  • the method in any possible implementation manner processes the data and obtains the processed data.
  • embodiments of the present application provide a terminal device, including: a processor.
  • the processor is coupled to a memory.
  • the memory is used to store instructions.
  • the terminal device implements the first aspect. to the fourth aspect, or the method in any possible implementation of the first aspect to the fourth aspect.
  • embodiments of the present application provide a network device, including: a processor, the processor is coupled to a memory, and the memory is used to store instructions.
  • the network device implements the first aspect. to the fourth aspect, or the method in any possible implementation of the first aspect to the fourth aspect.
  • embodiments of the present application provide a communication system, which includes a sending end and a receiving end.
  • the sending end is used to implement the functions of the method in any of the above first to third aspects and any possible implementation of the first to third aspects.
  • the receiving end is configured to implement the functions of the above-mentioned fourth aspect and the method in any possible implementation manner of the fourth aspect.
  • the communication system may include the data processing device as described in the fifth and sixth aspects, or may include the communication device as described in the seventh and eighth aspects, or may include the data processing device as described in the ninth and sixth aspects. Equipment described in ten aspects.
  • embodiments of the present application further provide a computer-readable storage medium. Instructions are stored on the computer-readable storage medium. When the instructions are run on a computer, they cause the computer to execute the first to fourth aspects. aspect, and the method in any possible implementation manner of the first to fourth aspects.
  • inventions of the present application provide a chip system.
  • the chip system includes a processor and may also include a memory, for implementing any one of the above first to fourth aspects, and the first to fourth aspects. functions in the method in possible implementations.
  • the chip system can be composed of chips or include chips and other discrete devices.
  • embodiments of the present application further provide a computer program product, including instructions that, when the instructions are run on a computer, cause the computer to execute the first to fourth aspects, and the first to fourth aspects. method in any possible embodiment.
  • Figure 1 is a schematic diagram of a communication system provided by this application.
  • Figure 2 is a schematic diagram of an 8 ⁇ 8 polar code encoding
  • Figure 3 is a schematic flow chart of a data processing method provided by this application.
  • Figure 4 is a schematic diagram of stream coding that supports stream decoding provided by this application.
  • FIG. 5 is a schematic diagram of a stream encoding provided by this application.
  • FIG. 6 is a schematic flow chart of another data processing method provided by this application.
  • FIG. 7 is a schematic diagram of stream decoding provided by this application.
  • Figure 8 is a performance analysis diagram of the data processing method provided by this application.
  • Figure 9 is a schematic diagram of a device provided by this application.
  • Figure 10 is a schematic diagram of a communication device provided by this application.
  • A/B can mean A or B;
  • and/or can be used to describe the existence of three relationships between related objects.
  • a and/or B can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural.
  • words such as “first” and “second” may be used to distinguish technical features with the same or similar functions. The words “first”, “second” and other words do not limit the quantity and execution order, and the words “first” and “second” do not limit the number and execution order.
  • This application provides a data processing method, which constructs a brand-new encoding matrix of Polar code, and processes the information bits to be encoded through the encoding matrix, thereby realizing stream encoding and/or stream decoding of Polar code.
  • This data processing method can be applied to communication systems.
  • the system architecture is shown in Figure 1. Wherein, the communication system includes network equipment and terminal equipment, and the network equipment can provide communication services to the terminal equipment.
  • the communication systems mentioned in this application include but are not limited to: narrowband-Internet of things (NB-IoT), global system for mobile communications (GSM), enhanced data rate GSM evolution system (enhanced data rate for GSM evolution, EDGE), wideband code division multiple access system (wideband code division multiple access, WCDMA), code division multiple access 2000 system (code division multiple access, CDMA2000), time division synchronous code division multiple access system (
  • NB-IoT narrowband-Internet of things
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • EDGE enhanced data rate GSM evolution system
  • WCDMA wideband code division multiple access
  • the network device may be a device that can communicate with the terminal device.
  • Network devices can be base stations, relay stations, or access points.
  • the base station can be a base transceiver station (BTS) in the global system for mobile communication (GSM) system or code division multiple access (CDMA) network, or it can be a broadband
  • the 3G base station NodeB in the code division multiple access (wideband code division multiple access, WC DMA) system can also be the evolutionary NodeB (referred to as eNB or eNodeB) in the long term evolution (long term evolution, LTE) system.
  • the network device may also be a satellite in a satellite communications system.
  • the network device can also be a wireless controller in a cloud radio access network (CRAN) scenario.
  • CRAN cloud radio access network
  • the network device may also be a network device in a 5G network or a network device in a future evolved public land mobile network (public land mobile network, PLMN) network (such as gNodeB).
  • Network devices can also be wearable devices, drones, or devices in the Internet of Vehicles (such as vehicle to everything (V2X)), or communication devices in device-to-device (D2D) communication. Or network equipment used in future communication systems.
  • V2X vehicle to everything
  • D2D device-to-device
  • the terminal device can be a user equipment (UE), an access terminal, a terminal unit, a terminal station, a mobile station, a mobile station, a remote station, a remote terminal, a mobile device, a terminal, a wireless communication device, a terminal agent or a terminal.
  • UE user equipment
  • an access terminal a terminal unit
  • a terminal station a mobile station
  • a mobile station a mobile station
  • a remote station a remote terminal
  • a mobile device a terminal
  • a wireless communication device a terminal agent or a terminal.
  • the access terminal may be a cellular phone, a cordless phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA), or a device with wireless communications Functional handheld devices, computing devices or other processing devices connected to wireless modems, wearable devices, drones, V2X devices, D2D devices, terminal devices in 5G networks, terminal devices in future evolved PLMN networks or in the future Terminal equipment in communication systems, etc.
  • SIP session initiation protocol
  • WLL wireless local loop
  • PDA personal digital assistant
  • this application is a coding scheme, which can be used for dedicated network equipment or general equipment, network equipment, various terminal equipment, etc.
  • This application can be implemented through a dedicated chip (such as an application specific integrated circuit (ASIC)), a programmable chip (such as a field programmable gate array (FPGA)), or software ( program code in memory), this application does not limit it.
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • Polar code is a channel coding scheme that can be strictly proven to achieve channel capacity. Polar code has the characteristics of high performance, low complexity, and flexible matching method. Currently, Polar codes have been identified as the uplink and/or downlink control channel coding scheme for the fifth generation ( 5th generation, 5G) control channel enhanced mobile broadband (eMBB) scenario.
  • 5G fifth generation
  • eMBB enhanced mobile broadband
  • Figure 2 is a schematic diagram of an 8 ⁇ 8 polar code encoding, in which the bits to be encoded are sorted according to their respective reliability and arranged in different positions in the block to be encoded.
  • bits with higher reliability are set as information bits (data)
  • bits with lower reliability are set as fixed bits (frozen).
  • the value of the fixed bit is usually set to 0 and is known to both the sender and the receiver during actual transmission.
  • u 7 , u 6 , u 5 , and u 3 are the four bits with the highest reliability, which are set as information bits respectively;
  • u 4 , u 2 , u 1 , and u 0 are the four bits with the lowest reliability.
  • a coding matrix G provided by this application:
  • G is a matrix with a size of (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), m and n are positive integers, and the matrix G N′ is a Polar generating matrix with a size of 2 n ⁇ 2 n , expressed as
  • the matrix O is an all-zero matrix of size 2 n ⁇ 2 n .
  • each element in the matrix is a 2 n ⁇ 2 n matrix
  • each element in the diagonal of the matrix is a matrix G N′
  • each element in the base of the matrix is the matrix G N′
  • the elements except the diagonal and the base are all the matrix O.
  • the coding matrix G′ can be obtained.
  • the coding matrix G' is a matrix with a size of (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), m and n are positive integers, and the matrix G N' is a matrix with a size of 2 n ⁇
  • the Polar generating matrix of 2 n is expressed as
  • the matrix O is an all-zero matrix with a size of 2 n ⁇ 2 n
  • F operation is the basic decoding operation of Polar code, and is processed using the predefined F function (f-function).
  • the inputs of the F function are L 0 and L 1 , and the F function can be simplified as:
  • sig is a sign operation. If the immediate value is greater than 0, the return value is 0, otherwise the return value is 1.
  • abs is an absolute value operation. For example, assume that there are encoded data x 0 and x m-1 with length N', perform F operation on x 0 and x m-1 , compare the signs of x 0 and x m-1 , and if they are consistent, the immediate value The value is 1, otherwise the value is -1.
  • G operation is the basic decoding operation of Polar code, and is processed using the predefined G function (g-function).
  • FIG. 3 is a schematic flow chart of a data processing method provided by this application.
  • This data processing method can be executed by a terminal device or a network device. It mainly performs the encoding process, including the following steps:
  • the information bit sequence includes multiple information bits to be encoded.
  • the information bit sequence can be expressed as ⁇ a 0 , a 1 , a 2 ,..., a k-1 ⁇ , and one element in the information bit sequence represents a bit to be encoded.
  • bits to be encoded in this application may also include cyclic redundancy check (cyclic redundancy check, CRC) bits and/or parity check (parity check, PC) bits, which may also involve Operations such as scrambling on some bits or even all bits are not related to the essence of the solution of this application, so they are all described in terms of bits to be encoded, and will not be described again here.
  • CRC cyclic redundancy check
  • PC parity check
  • S102 Encode the information bit sequence according to the encoding matrix G to obtain encoded data.
  • the description of the coding matrix G can refer to the relevant concepts mentioned above, and will not be described again here.
  • u N is an information bit sequence. Modulo square multiplication of u N and the coding matrix G is performed to obtain the coded data x N .
  • the length of x N is m ⁇ 2 n .
  • the information bit sequence can be divided into m segments, that is, the information bit sequence includes m segments, and the Polar generating matrix of each segment is G N′ .
  • the length of each segment is 2 n
  • each segment can be subjected to modular square operation with the Polar generating matrix G N' of size 2 n ⁇ 2 n , and information is interleaved between segments.
  • Get encoded data is used to encode the information bit sequence to obtain encoded data, including two situations:
  • Case 1 The number of information bits in m segments is k 0 ,k 1 ,...,k m-1 , k 0 is less than k m-1 , and k 0 ⁇ k 1 ⁇ ... ⁇ k m -1 .
  • k 0 is the number of information bits in the 0th segment
  • k 1 is the number of information bits in the 1st segment
  • k m-1 is the number of information bits in the m-1 segment.
  • the number of information bits is less than the number of information bits in the m-1th segment
  • the number of information bits in the m-1th segment is the largest (that is, the last segment contains the most information bits).
  • the encoding process includes the following steps:
  • the jth piece of cached data is obtained by encoding the jth segment of the information bit sequence using the matrix G N′ , and the j satisfies 0 ⁇ j ⁇ m-1;
  • the encoded data consists of m segments
  • the 0th segment of encoded data is the m-1th cache data
  • the i-th piece of coded data is obtained by XORing the j-th cache data and the m-1th cache data, i satisfies 1 ⁇ i ⁇ m-1, and j satisfies 0 ⁇ j ⁇ m-2.
  • the terminal device first uses the matrix G N' to perform a modular square operation on each segment of the information bit sequence to obtain m cached data, and then uses the m-1th cached data to compare it with the first m-2 cached data.
  • the data is XORed (such as modulo two addition) to obtain the encoded data.
  • Case 2 The number of information bits in m segments is k 0 ,k 1 ,...,k m-1 , k 1 is less than k 0 , and k 1 ⁇ ... ⁇ k m-1 ⁇ k 0 .
  • k 0 is the number of information bits in the 0th segment
  • k 1 is the number of information bits in the 1st segment
  • k m-1 is the number of information bits in the m-1 segment.
  • the number of information bits is greater than the number of information bits in the 1st segment, and the number of information bits in the 0th segment is the largest (that is, the 1st segment includes the most bits of information).
  • the encoded data includes m segments, where the 0th segment of encoded data is obtained by encoding the 0th segment of the information bit sequence according to the matrix G N′ ; the i-th segment of encoded data is obtained by encoding the 0th segment of the information bit sequence according to the matrix G N ′ is obtained by encoding the i-th segment of the information bit sequence and then XORing it with the 0th segment of coded data.
  • the terminal device first uses the matrix G N′ to perform a modular square operation on the 0th segment in the information bit sequence to obtain the 0th segment coded data, and then uses the matrix G N′ to perform the modular square operation on the 1st segment in the information bit sequence.
  • the segment performs modular square multiplication operation, and performs XOR processing (such as modular double addition operation) on the operation result and the 0th segment encoded data to obtain the 1st segment encoded data, and so on until the m-1 segment encoded data is obtained.
  • the above encoding process can be regarded as a stream encoding process, that is, the encoder can receive the data to be encoded and at the same time encode and send the received data to be encoded.
  • the coding matrix G′ corresponding to the coding process described in case 2 is obtained by performing elementary column transformation on the coding matrix G, where the coding matrix That is to say, using the encoding process described in case 2 to encode the information bit sequence is similar to using the encoding matrix G to encode the information bit sequence.
  • the encoding principle is similar.
  • the encoding process described in S102 can implement stream encoding (for example, situation 2 described in S102), after the terminal device completes encoding a piece of encoded data, it can send the piece of encoded data without waiting for all the information bit sequences in the sequence. After the bit encoding is completed, all the encoded data is sent. If the encoding process described in S102 is designed to implement stream decoding (for example, case 1 described in S102), the terminal device sends all the encoded data after all bits in the information bit sequence are encoded.
  • stream decoding for example, case 1 described in S102
  • the data processing method provided by this application designs a new Polar code encoding matrix G.
  • the terminal device uses this encoding matrix G to encode the information bits to be encoded, it can receive a part of the information bits during the encoding process. Encoding this part of the information bits and sending the encoded data means stream encoding is achieved, which is beneficial to reducing the size of the encoder and cache in the terminal device.
  • the encoding matrix is used to encode the information bits to be encoded to obtain encoded data, which is beneficial to realizing stream decoding.
  • Figure 4 is a schematic diagram of stream coding that supports stream decoding provided by this application.
  • the information bit sequence can be expressed as ⁇ a 0 , a 1 , a 2 ,..., a k-1 ⁇ , and one element in the information bit sequence represents a bit to be encoded.
  • the information bit sequence is divided into m sub-sections, and k i information bits are allocated to each sub-section.
  • Figure 5 is a schematic diagram of stream coding provided by this application.
  • the information bit sequence can be expressed as ⁇ a 0 , a 1 , a 2 ,..., a k-1 ⁇ , and one element in the information bit sequence represents a bit to be encoded.
  • the information bit sequence is divided into m sub-sections, and k i information bits are allocated to each sub-section.
  • Figure 6 is a schematic flow chart of another data processing method provided by this application.
  • the data processing method can be executed by the terminal device or by the network device. It can be understood that when the terminal device performs the data processing method described in the third part here, that is, the terminal device is the decoding side, then the network device performs the data processing method described in the second part, that is, the network device is the encoding side. . When executing the decoding process, the following steps are included:
  • the coded data is obtained by coding the information bit sequence according to the coding matrix G.
  • the encoded data may be obtained by encoding the information bit sequence based on the coding matrix G, or may be obtained by encoding the information bit sequence based on the method described in case 1 in S102.
  • the process of decoding the encoded data is a stream decoding process.
  • the terminal device can first decode the received 0th segment of encoded data and the 1st segment of encoded data, that is, receive a part of it during the decoding process. After receiving the information, the part of the information can be decoded. Specifically, the following steps can be included:
  • S14 Enhance the mark data corresponding to the 0th segment of encoded data based on the mark data corresponding to the 1st segment of encoded data and the decoded data corresponding to the 1st segment of encoded data.
  • the labeled data corresponding to the 0th segment of encoded data is the log likelihood ratio (LLR) of the 0th segment of encoded data
  • the labeled data corresponding to the 1st segment of encoded data is the LLR of the 1st segment of encoded data.
  • the method of performing Polar code decoding on the mark data corresponding to the first segment of encoded data after the F operation can refer to the existing Polar code decoding method, which is not limited in this application.
  • the LLR of the 0th segment of encoded data, the LLR of the 1st segment of encoded data and the decoded data corresponding to the 1st segment of encoded data are used as the input of the G function, thereby realizing the enhancement of the marked data corresponding to the 0th segment of encoded data, which is beneficial to In the subsequent decoding process, stream decoding is implemented based on the enhanced 0th segment encoded data.
  • the description of the G function refers to the previous description and will not be repeated here.
  • the tag data corresponding to the 0th segment of coded data may be the likelihood probability of the 0th segment of coded data
  • the tag data corresponding to the 1st segment of coded data may be the likelihood probability of the 1st segment of coded data.
  • the above step s12 will become: perform probability operation on the mark data corresponding to the 0th segment coded data and the mark data corresponding to the 1st segment coded data to obtain the 1st segment coded data corresponding to the probability domain. Label data. It can be understood that the subsequent processing flow is still performed according to s13 and s14, and the marked data corresponding to the 0th segment of encoded data can be enhanced.
  • the processing method is similar to the above-mentioned s11 ⁇ s14, and may include the following steps:
  • the mark data corresponding to the second segment of encoded data obtains the mark data corresponding to the second segment of encoded data, and perform an F operation on the mark data corresponding to the second segment of encoded data and the mark data corresponding to the enhanced segment 0 encoded data to obtain the second segment of encoded data after the F operation.
  • the mark data corresponding to the data perform Polar code decoding on the mark data corresponding to the second segment of encoded data after the F operation, and obtain the decoded data corresponding to the second segment of encoded data.
  • the decoded data corresponding to the 2-section coded data performs a second enhancement on the marked data corresponding to the enhanced 0-section coded data, and the marked data corresponding to the 0-section coded data after the secondary enhancement are obtained.
  • the data processing method provided by this application can support decoding a part of the information after receiving it during the decoding process, that is, realizing stream decoding, which can reduce the decoding cost. size of the processor, thereby reducing the overhead on the decoding side.
  • Figure 7 is a schematic diagram of stream decoding provided by this application.
  • the 0th segment of encoded data is the m-1th cache data, then the 0th segment of encoded data is marked as and cache. in, for LLR sending data, That is what is described in the third subsection of the second part of the previous article. as send.
  • the second segment of encoded data is the first buffered data, then the second segment of encoded data is marked as After, with Perform F operation to get right Perform ordinary Polar code decoding to obtain decoded data right Perform G operation to obtain the twice enhanced
  • the decoded data can be obtained using the same method
  • multiple enhancements can be obtained as the decoding proceeds.
  • multiple enhanced Perform ordinary polar code decoding to obtain decoded data The stream decoding process is completed.
  • FIG 8 is a performance analysis diagram of the data processing method provided by this application.
  • the abscissa of the performance analysis diagram is EsN0, which represents The ratio of each symbol energy to the noise power spectral density; the ordinate is the block error rate (BLER), which is used to measure system performance testing.
  • BLER block error rate
  • the solid line, the first dotted line and the second dotted line form a group, which can be used to compare the same information bit sequence, using decoders of different sizes and the same decoding method, or using the same
  • the difference in decoding performance depends on the size of the decoder and different decoding methods.
  • the first group the solid line with diamond symbols, the first type of dotted line and the second type of dotted line are the decoding performance comparison of the first group.
  • the decoding method is Existing Polar code decoding or use the stream decoding provided by this application.
  • the second group the solid line with square symbols, the first dotted line and the second dotted line are the second group of decoding performance comparisons.
  • the decoding method is Existing Polar code decoding or use the stream decoding provided by this application.
  • the third group the solid lines with asterisks, the first dotted line and the second dotted line respectively represent the decoding performance comparison of the second group.
  • the decoding method is Existing Polar code decoding or use the stream decoding provided by this application.
  • the device or equipment provided by this application may include a hardware structure and/or a software module to realize the above functions in the form of a hardware structure, a software module, or a hardware structure plus a software module. Whether one of the above functions is performed as a hardware structure, a software module, or a hardware structure plus a software module depends on the specific application and design constraints of the technical solution.
  • the division of modules in this application is schematic and is only a logical function division. In actual implementation, there may be other division methods.
  • each functional module in various embodiments of the present application can be integrated into a processor, or can exist physically alone, or two or more modules can be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or software function modules.
  • FIG 9 is a schematic diagram of a device provided by this application.
  • the device may include modules that perform one-to-one correspondence with the methods/operations/steps/actions described in the method embodiments corresponding to Figures 3 to 7.
  • the module may be a hardware circuit, software, or hardware.
  • the circuit is combined with software implementation.
  • the device may be called a data processing device or a communication device.
  • the device includes a communication unit 901 and a processing unit 902. It is used to implement the method executed by the terminal device or the network device in the previous embodiment.
  • the processing unit 902 is configured to obtain an information bit sequence, and encode the information bit sequence according to the encoding matrix G to obtain encoded data.
  • the coding matrix G is a matrix of size (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), m and n are positive integers, matrix G N′ is a Polar generating matrix of size 2 n ⁇ 2 n , and matrix O is a size of 2 n ⁇ 2 n all-zero matrix.
  • the communication unit 901 is used to send encoded data.
  • the information bit sequence includes m segments, and the Polar generating matrix of each segment is G N′ .
  • the number of information bits in m segments is k 0 , k 1 ,..., k m-1 , where k 0 is less than k m-1 , and k 0 ⁇ k 1 ⁇ ... ⁇ k m-1 .
  • the number of information bits of the i-th segment is k i , and i satisfies 0 ⁇ i ⁇ m-1.
  • the processing unit 902 is used to obtain m cached data, where the jth cached data is obtained by encoding the jth segment of the information bit sequence using the matrix G N′ , j satisfies 0 ⁇ j ⁇ m-1; the encoded data includes m segments, in which the 0th segment of encoded data is the m-1th cache data, and the i-th segment of encoded data is the XOR processing of the jth cached data and the m-1th cached data. Obtained, i satisfies 1 ⁇ i ⁇ m-1, and j satisfies 0 ⁇ j ⁇ m-2.
  • the communication unit 901 is configured to first send the m-1th piece of buffered data, and then send the i-th piece of coded data in sequence, 1 ⁇ i ⁇ m-1.
  • the processing unit 902 is used to perform elementary column transformation on the coding matrix G.
  • the transformed coding matrix And the information bit sequence is encoded according to the transformed encoding matrix G′ to obtain encoded data.
  • the number of information bits in m segments is k 0 ,k 1 ,...,k m-1 , k 1 is less than k 0 , and k 1 ⁇ ... ⁇ k m-1 ⁇ k 0 .
  • the encoded data includes m segments, wherein the 0th segment encoded data is obtained by encoding the 0th segment of the information bit sequence according to the matrix G N ′; the i-th segment encoded data is obtained by encoding the information bit sequence according to the matrix G N′ It is obtained after the i-th segment of the information bit sequence is encoded and then XORed with the 0th segment of encoded data.
  • the data processing method implemented by this device designs a new Polar code encoding matrix G.
  • the terminal device uses this encoding matrix G to encode the information bits to be encoded, it can receive a part of the information bits during the encoding process. This part of the information bits are encoded and the encoded data is sent, that is, stream encoding is implemented, which is beneficial to reducing the size of the encoder and buffer in the terminal device.
  • the encoding matrix is used to encode the information bits to be encoded to obtain encoded data, which is beneficial to realizing stream decoding.
  • the processing unit 902 is used to obtain an information bit sequence.
  • the information bit sequence includes m segments, and uses the Polar generating matrix G N′ of each segment to process each segment, obtaining m cached data, where the matrix G N′ is a Polar generating matrix with a size of 2 n ⁇ 2 n .
  • the processing unit 902 is also used to obtain encoded data based on m pieces of cached data.
  • the encoded data includes m segments, in which the 0th segment of encoded data is the m-1th cache data, and the i-th segment of encoded data is obtained by XORing the jth cached data and the m-1th cached data. , i satisfies 1 ⁇ i ⁇ m-1, and j satisfies 0 ⁇ j ⁇ m-2.
  • the communication unit 901 is used to send encoded data.
  • the number of information bits in m segments is k 0 , k 1 ,..., k m-1 , where k 0 is less than k m-1 , and k 0 ⁇ k 1 ⁇ ... ⁇ k m-1 .
  • the number of information bits of the i-th segment is k i , and i satisfies 0 ⁇ i ⁇ m-1.
  • the processing unit 902 is configured to encode the information bit sequence according to the encoding matrix G to obtain encoded data.
  • the coding matrix G is a matrix of size (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), m and n are positive integers, the matrix G N′ is a Polar generating matrix of size 2 n ⁇ 2 n , and the matrix O is the size is a 2 n ⁇ 2 n all-zero matrix.
  • the data processing method implemented by the device divides the information bit sequence to be encoded into m segments, and uses a Polar generating matrix of size 2 n ⁇ 2 n for each segment for encoding and information interleaving, and the encoded data Interleaved transmission is beneficial to stream decoding.
  • the processing unit 902 is used to obtain an information bit sequence, which includes m segments, and uses the Polar generating matrix G N′ of each segment to process each segment, obtaining Encode data.
  • the matrix G N′ is a Polar generating matrix with a size of 2 n ⁇ 2 n .
  • the encoded data includes m segments.
  • the 0th segment of encoded data is the encoding of the 0th segment of the information bit sequence according to the matrix G N′. Obtained; the i-th segment of coded data is obtained by encoding the i-th segment of the information bit sequence according to the matrix G N′ , and then XORing it with the 0-th segment of coded data.
  • the communication unit 901 is used to send encoded data.
  • the number of information bits in m segments is k 0 ,k 1 ,...,k m-1 , k 1 is less than k 0 , and k 1 ⁇ ... ⁇ k m-1 ⁇ k 0 .
  • the number of information bits of the i-th segment is k i , and i satisfies 0 ⁇ i ⁇ m-1.
  • the processing unit 902 is configured to encode the information bit sequence according to the encoding matrix G′ to obtain encoded data.
  • the coding matrix G′ is a matrix of size (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), m and n are positive integers, the matrix G N′ is a Polar generating matrix of size 2 n ⁇ 2 n , and the matrix O is An all-zero matrix of size 2 n ⁇ 2 n .
  • the data processing method implemented by the device divides the information bit sequence to be encoded into m segments, and uses a Polar generating matrix of size 2 n ⁇ 2 n for each segment for encoding and information interleaving, which can support coding After receiving part of the information during the process, the part of the information can be encoded and sent (that is, to achieve the purpose of supporting stream encoding), reducing the size of the encoder and cache.
  • the communication unit 901 is configured to receive encoded data
  • the processing unit 902 is configured to decode the encoded data to obtain decoded data.
  • the coded data is obtained by coding the information bit sequence according to the coding matrix G.
  • the coding matrix G is a matrix of size (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), m and n are positive integers, the matrix G N′ is a Polar generating matrix of size 2n ⁇ 2n, and the matrix O is a size of 2 n ⁇ 2 n all-zero matrix.
  • the processing unit 902 is configured to obtain the mark data corresponding to the 0th segment of coded data and the mark data corresponding to the 1st segment of coded data, and combine the mark data corresponding to the 0th segment of coded data with the mark data corresponding to the 1st segment of coded data.
  • Perform F operation to obtain the marked data corresponding to the first segment of encoded data after the F operation; and perform Polar code decoding on the marked data corresponding to the first segment of encoded data after the F operation to obtain the decoded data corresponding to the first segment of encoded data.
  • data and then enhance the mark data corresponding to the 0th segment of encoded data based on the mark data corresponding to the 1st segment of encoded data and the decoded data corresponding to the 1st segment of encoded data.
  • the processing unit 902 is used to obtain the marked data corresponding to the q-th segment of coded data, where q is 2 ⁇ q ⁇ m-1, and compare the marked data corresponding to the q-th segment of coded data with the enhanced 0th segment.
  • Perform F operation on the marked data corresponding to the encoded data to obtain the marked data corresponding to the q-th segment of encoded data after the F operation.
  • the decoded data corresponding to the data is enhanced based on the mark data corresponding to the qth segment coded data and the decoded data corresponding to the qth segment coded data.
  • the data processing method implemented by the device can support decoding part of the information after receiving it during the decoding process, thereby reducing the size of the decoder.
  • FIG. 9 is a schematic diagram of a communication device provided by this application, used to implement the data processing method in the above method embodiment.
  • the communication device 1000 may also be a chip system. It can be understood that the communication device 1000 may be, for example, a terminal device or a network device.
  • the communication device 1000 includes a communication interface 1001 and a processor 1002.
  • the communication interface 1001 may be, for example, a transceiver, an interface, a bus, a circuit, or a device capable of implementing transceiver functions.
  • the communication interface 1001 is used to communicate with other devices through a transmission medium, so that the device 1000 can communicate with other devices.
  • the processor 1002 is configured to perform processing-related operations.
  • the processor 1002 is configured to obtain an information bit sequence, and encode the information bit sequence according to the encoding matrix G to obtain encoded data.
  • the coding matrix G is a matrix of size (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), m and n are positive integers, matrix G N′ is a Polar generating matrix of size 2 n ⁇ 2 n , and matrix O is a size of 2 n ⁇ 2 n all-zero matrix.
  • Communication interface 1001 is used to send encoded data.
  • the data processing method implemented by this communication device designs a new Polar code encoding matrix G.
  • the terminal device uses this encoding matrix G to encode the information bits to be encoded, it can receive a part of the information bits during the encoding process. Encoding this part of the information bits and sending the encoded data means stream encoding is achieved, which is beneficial to reducing the size of the encoder and cache in the terminal device.
  • the encoding matrix is used to encode the information bits to be encoded to obtain encoded data, which is beneficial to realizing stream decoding.
  • the processor 1002 is used to obtain an information bit sequence, which includes m segments, and uses the Polar generating matrix G N′ of each segment to process each segment, obtaining m cached data, where the matrix G N′ is a Polar generating matrix with a size of 2 n ⁇ 2 n .
  • the processor 1002 is also used to obtain encoded data based on m pieces of cached data.
  • the encoded data includes m segments, in which the 0th segment of encoded data is the m-1th cache data, and the i-th segment of encoded data is obtained by XORing the jth cached data and the m-1th cached data. , i satisfies 1 ⁇ i ⁇ m-1, and j satisfies 0 ⁇ j ⁇ m-2.
  • Communication interface 1001 is used to send encoded data.
  • the data processing method implemented by the communication device divides the information bit sequence to be encoded into m segments, and uses a Polar generating matrix of size 2 n ⁇ 2 n for each segment for encoding and information interleaving, and after encoding Data is interleaved and sent, which is conducive to stream decoding.
  • the processor 1002 is used to obtain an information bit sequence, which includes m segments, and uses the Polar generating matrix G N′ of each segment to process each segment, obtaining Encode data.
  • the matrix G N′ is a Polar generating matrix with a size of 2 n ⁇ 2 n .
  • the encoded data includes m segments.
  • the 0th segment of encoded data is the encoding of the 0th segment of the information bit sequence according to the matrix G N′. Obtained; the i-th segment of coded data is obtained by encoding the i-th segment of the information bit sequence according to the matrix G N′ , and then XORing it with the 0-th segment of coded data.
  • Communication interface 1001 is used to send encoded data.
  • the data processing method implemented by the communication device divides the information bit sequence to be encoded into m segments, and uses a Polar generating matrix of size 2 n ⁇ 2 n for each segment for encoding and information interleaving, which can support After receiving a part of the information during the encoding process, the part of the information can be encoded and sent (that is, to achieve the purpose of supporting stream encoding), reducing the size of the encoder and cache.
  • the communication interface 1001 is used to receive encoded data
  • the processor 1002 is used to decode the encoded data to obtain decoded data.
  • the coded data is obtained by coding the information bit sequence according to the coding matrix G.
  • the coding matrix G is a matrix of size (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), m and n are positive integers, the matrix G N′ is a Polar generating matrix of size 2 n ⁇ 2 n , and the matrix O is the size is a 2 n ⁇ 2 n all-zero matrix.
  • the data processing method implemented by the communication device can support decoding part of the information after receiving it during the decoding process, thereby reducing the size of the decoder.
  • the communication device 1000 may also include at least one memory 1003 for storing program instructions and/or data.
  • the memory is coupled to the processor. Coupling in this application is an indirect coupling or communication connection between devices, units or modules, which may be electrical, mechanical or other forms, and is used for information interaction between devices, units or modules.
  • the processor may operate in conjunction with the memory.
  • the processor may execute program instructions stored in memory.
  • the at least one memory and processor are integrated together.
  • the bus 1004 is represented by a thick line in FIG. 10 .
  • the connection methods between other components are only schematically illustrated and are not limiting.
  • the bus can be divided into address bus, data bus, control bus, etc. For ease of presentation, only one thick line is used in Figure 10, but it does not mean that there is only one bus or one type of bus.
  • the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component that can implement or execute the present application.
  • a general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in this application can be directly implemented by a hardware processor, or executed by a combination of hardware and software modules in the processor.
  • the memory may be a non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), etc., or it may be a volatile memory (volatile memory), such as a random access memory.
  • Get memory random-access memory, RAM.
  • Memory is, but is not limited to, any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.
  • the memory in this application can also be a circuit or any other device capable of realizing a storage function, used to store program instructions and/or data.
  • the present application provides a communication device.
  • the communication device is composed of an input and output interface and a logic circuit.
  • the input and output interface is used to input or output data; the logic circuit follows the method in the embodiment corresponding to Figure 3 to Figure 7 Process the data and obtain the processed data.
  • the present application provides a communication device.
  • the communication device is composed of an input and output interface and a logic circuit.
  • the input and output interface is used to input or output data; the logic circuit follows the method in the embodiment corresponding to Figure 3 to Figure 7 Process the data and obtain the processed data.
  • This application provides a communication system, which includes a terminal device and a network device in the embodiments corresponding to Figures 3 to 7.
  • This application provides a computer-readable storage medium.
  • the computer-readable storage medium stores programs or instructions.
  • the program or instruction is run on the computer, the computer is caused to execute the data processing method in the embodiment corresponding to FIG. 3 to FIG. 7 .
  • the computer program product includes instructions.
  • the instructions When the instructions are run on the computer, the computer is caused to execute the data processing method in the embodiment corresponding to FIG. 3 to FIG. 7 .
  • the present application provides a chip or chip system.
  • the chip or chip system includes at least one processor and an interface.
  • the interface and the at least one processor are interconnected through lines.
  • the at least one processor is used to run computer programs or instructions to execute the tasks shown in Figure 3 to Figure 7 corresponds to the data processing method in the embodiment.
  • the interface in the chip can be an input/output interface, a pin or a circuit, etc.
  • the above-mentioned chip system can be a system on chip (SOC), or a baseband chip, etc., where the baseband chip can include a processor, a channel encoder, a digital signal processor, a modem, an interface module, etc.
  • SOC system on chip
  • baseband chip can include a processor, a channel encoder, a digital signal processor, a modem, an interface module, etc.
  • the chip or chip system described above in this application further includes at least one memory, and instructions are stored in the at least one memory.
  • the memory can be a storage unit inside the chip, such as a register, a cache, etc., or it can be a storage unit of the chip (such as a read-only memory, a random access memory, etc.).
  • the technical solutions provided in this application can be implemented in whole or in part through software, hardware, firmware, or any combination thereof.
  • software When implemented using software, it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded and executed on a computer, the processes or functions described in this application are generated in whole or in part.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable devices.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another, e.g., the computer instructions may be transferred from a website, computer, server, or data center Transmission to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means.
  • the computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more available media integrated.
  • the available media may be magnetic media (eg, floppy disk, hard disk, tape), optical media (eg, digital video disc (digital video disc, DVD)), or semiconductor media, etc.
  • the embodiments may refer to each other, for example, the methods and/or terms between the method embodiments may refer to each other, for example, the functions and/or terms between the device embodiments may refer to each other. References may be made to each other, for example functions and/or terms between apparatus embodiments and method embodiments may be referenced to each other.

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Abstract

本申请提供一种数据处理方法、装置及设备，该方法设计了一种全新的Polar码编码矩阵G，当终端设备采用该编码矩阵G对待编码的信息比特进行编码时，可以在编码过程中接收一部分信息比特之后就可以对该部分信息比特进行编码并发送编码数据，也即是实现了流编码，有利于降低终端设备中编码器和缓存的大小。并且，采用该编码矩阵对待编码的信息比特进行编码得到编码数据，有利于实现流译码，降低译码器的大小。

Description

一种数据处理方法、装置及设备 技术领域
本申请涉及通信技术领域，尤其涉及一种数据处理方法、装置及设备。
背景技术
极化码(Polar code)是一种能够被严格证明“达到”香农信道容量的信道编码方案，具有性能好，复杂度低等特点，可以应用于第五代(the 5 th generation，5G)通信系统以及未来通信系统中。Polar码是一种线性块码，通过编码矩阵，可以生成编码后的数据。目前Polar码的编码矩阵决定了设备需要收到完整的待编码数据或者待译码数据后，才能开始编码或者译码。
发明内容
本申请提供一种数据处理方法、装置及设备，该方法通过设计一种全新的Polar码编码矩阵，可以实现流编码和/或流译码。
第一方面，本申请提供第一种数据处理方法，该数据处理方法可以由终端设备或网络设备所执行。其中，以终端设备为执行主体，且终端设备为编码侧为例，终端设备获取信息比特序列，并根据编码矩阵G对所述信息比特序列进行编码，得到编码数据，再发送编码数据。其中，编码矩阵G表示为：
Figure PCTCN2022110968-appb-000001
编码矩阵G为大小为(m×2n)×(m×2n)的矩阵，m和n为正整数，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，矩阵O为大小为2 n×2 n的全零矩阵。
该方法中，设计了一种全新的Polar码编码矩阵G，当终端设备采用该编码矩阵G对待编码的信息比特进行编码时，可以在编码过程中接收一部分信息比特之后就可以对该部分信息比特进行编码并发送编码数据，也即是实现了流编码，有利于降低终端设备中编码器和缓存的大小。并且，采用该编码矩阵对待编码的信息比特进行编码得到编码数据，有利于实现流译码。
一种可能的实施方式中，信息比特序列包括m个分段，每一个分段的Polar生成矩阵为G N′。
该方法中，也可以将信息比特序列分成m个分段，将每一个分段与矩阵G N′进行模二乘运算。
一种可能的实施方式中，m个分段中的信息比特个数为k 0,k 1,...,k m-1，其中，k 0小于k m-1，且k 0≤k 1≤...≤k m-1。
一种可能的实施方式中，第i个分段的信息比特个数为k i，所述i满足0≤i≤m-1。
该方法中，每一个分段的信息比特个数是不相同的，并且按照一定的数量规律变化。
一种可能的实施方式中，获取m份缓存数据，其中，第j份缓存数据为采用矩阵G N′对信息比特序列的第j个分段进行编码后得到的，j满足0≤j≤m-1；
编码数据包括m段，其中，第0段编码数据为第m-1份缓存数据，第i段编码数据为将 第j份缓存数据与第m-1份缓存数据进行异或处理得到的，i满足1≤i≤m-1，j满足0≤j≤m-2。
一种可能的实施方式中，首先发送第m-1份缓存数据，再依次发送第i段编码数据，1≤i≤m-1。
该方法中，将m个分段中的信息比特转换为m份缓存数据后，并按照设置的顺序发送编码数据。
一种可能的实施方式中，对编码矩阵G进行初等列变换，变换后的编码矩阵
Figure PCTCN2022110968-appb-000002
并根据变换后的编码矩阵G′对信息比特序列进行编码，得到编码数据。
该方法中，对编码矩阵G进行初等列变换，使得终端设备采用变换后的编码矩阵G′对待编码的信息比特进行编码时，也可以实现流编码，有利于降低终端设备中编码器和缓存的大小。
一种可能的实施方式中，m个分段中的信息比特个数为k 0,k 1,...,k m-1，k 1小于k 0，且k 1≤...≤k m-1≤k 0。
一种可能的实施方式中，第i个分段的信息比特个数为k i，所述i满足0≤i≤m-1。
该方法中，每一个分段包含的信息比特个数是不相同的。假设最先收到的k 0个信息比特是个数最多的(也即是第0个分段的信息比特个数最多)，编码器基于最先收到的k 0个信息比特对应的编码数据，对其余的m-1个分段分别进行编码处理，有利于实现流编码。
一种可能的实施方式中，编码数据包括m段，其中，第0段编码数据为根据矩阵G N′对信息比特序列的第0个分段进行编码得到的；第i段编码数据为根据矩阵G N′对信息比特序列的第i个分段进行编码后，再与第0段编码数据进行异或处理，得到的。
该方法中，由于将信息比特序列分成m个分段，则m个分段对应的编码数据也分成m段。该编码方式中将第0段编码数据进行缓存，并将第0段编码数据分别与其余m-1段编码数据进行异或处理(例如进行信息交织)，从而达到支持流编码的目的。
第二方面，本申请提供第二种数据处理方法，该数据处理方法可以由终端设备或网络设备所执行。其中，以终端设备为执行主体，且终端设备为编码侧为例，终端设备获取信息比特序列，信息比特序列包括m个分段，并采用每一个分段的Polar生成矩阵G N′对每一个分段进行处理，得到m份缓存数据，其中，矩阵G N′为大小为2 n×2 n的Polar生成矩阵。再基于m份缓存数据，得到并发送编码数据。编码数据包括m段，其中，第0段编码数据为第m-1份缓存数据，第i段编码数据为将第j份缓存数据与第m-1份缓存数据进行异或处理得到的，i满足1≤i≤m-1，j满足0≤j≤m-2。
该方法中，终端设备将待编码的信息比特序列划分为m个分段，并针对每一个分段采用大小为2 n×2 n的Polar生成矩阵进行编码以及信息交织，并且编码后数据交织发送，有利于实现流译码。
一种可能的实施方式中，m个分段中的信息比特个数为k 0,k 1,...,k m-1，其中，k 0小于k m-1，且k 0≤k 1≤...≤k m-1。
一种可能的实施方式中，第i个分段的信息比特个数为k i，所述i满足0≤i≤m-1。
一种可能的实施方式中，终端设备可以根据编码矩阵G对信息比特序列进行编码，得到 编码数据。其中，编码矩阵
Figure PCTCN2022110968-appb-000003
编码矩阵G为大小为(m×2 n)×(m×2 n)的矩阵，m和n为正整数，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，矩阵O为大小为2 n×2 n的全零矩阵。
该方法中，设计了一种基于Polar生成矩阵的编码矩阵，类似于构造了一种Polar生成矩阵的耦合矩阵，在编码矩阵G下有利于实现流译码。
第三方面，本申请提供第三种数据处理方法，该数据处理方法可以由终端设备或网络设备所执行。其中，以终端设备为执行主体，且终端设备为编码侧为例，终端设备获取信息比特序列，信息比特序列包括m个分段，并采用每一个分段的Polar生成矩阵G N′对每一个分段进行处理，得到并发送编码数据。其中，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，编码数据包括m段，第0段编码数据为根据矩阵G N′对所述信息比特序列的第0个分段进行编码得到的；第i段编码数据为根据矩阵G N′对所述信息比特序列的第i个分段进行编码后，再与第0段编码数据进行异或处理，得到的。
该方法中，终端设备将待编码的信息比特序列划分为m个分段，并针对每一个分段采用大小为2 n×2 n的Polar生成矩阵进行编码以及信息交织，可以支持在编码过程中接收一部分信息后就可以对该部分信息进行编码并发送(也即是达到支持流编码的目的)，降低编码器以及缓存的大小。
一种可能的实施方式中，m个分段中的信息比特个数为k 0,k 1,...,k m-1，k 1小于k 0，且k 1≤...≤k m-1≤k 0。
一种可能的实施方式中，第i个分段的信息比特个数为k i，所述i满足0≤i≤m-1。
一种可能的实施方式中，终端设备可以根据编码矩阵G′对信息比特序列进行编码，得到编码数据。其中，编码矩阵
Figure PCTCN2022110968-appb-000004
编码矩阵G′为大小为(m×2 n)×(m×2 n)的矩阵，m和n为正整数，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，矩阵O为大小为2 n×2 n的全零矩阵。
该方法中，设计了一种基于Polar生成矩阵的编码矩阵，类似于构造了一种Polar生成矩阵的耦合矩阵，在编码矩阵G′下有利于实现流编码。
需要注意的是，上述第一方面至第三方面中所述的方法，也可以通过网络设备所执行。在这种情况下，网络设备为编码侧，终端设备为译码侧。
第四方面，本申请提供第四种数据处理方法，该数据处理方法可以由终端设备或网络设备所执行。其中，以网络设备为执行主体，且网络设备为译码侧为例，网络设备接收编码数据，并对编码数据进行译码，得到译码数据。其中，编码数据是根据编码矩阵G对信息比特序列进行编码得到的，编码矩阵
Figure PCTCN2022110968-appb-000005
编码矩阵G为大小为(m×2 n)×(m×2 n)的矩阵，m和n为正整数，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，矩 阵O为大小为2 n×2 n的全零矩阵。
该方法中，由于编码数据是基于本申请设计的一种全新的Polar码编码矩阵G得到的，则译码侧接收该编码数据后，可以支持在译码过程中接收一部分信息后就能对该部分信息进行译码，降低译码器的大小。
一种可能的实施方式中，信息比特序列包括m个分段，每一个分段的Polar生成矩阵为G N′。
一种可能的实施方式中，网络设备获取第0段编码数据对应的标记数据和第1段编码数据对应的标记数据，将第0段编码数据对应的标记数据和第1段编码数据对应的标记数据进行F运算，得到F运算后的第1段编码数据对应的标记数据；并对F运算后的第1段编码数据对应的标记数据进行Polar码译码，得到第1段编码数据对应的译码数据；再根据第1段编码数据对应的标记数据和第1段编码数据对应的译码数据对第0段编码数据对应的标记数据进行增强。需要注意的是，第0段编码数据包括编码矩阵G的最后N′列，或者，第0段编码数据包括将编码矩阵G的前(m-1)×2 n列和后2 n列做初等列变换后，得到的编码矩阵G′的前N′列。第1段编码数据包括编码矩阵G的前N′列，或者，第1段编码数据包括编码矩阵G′的前N′+1列至N′*2列。
该方法中，网络设备基于首次接收的第0段编码数据及其相邻的第1段编码数据进行译码，从而实现了流译码，并且对第0段编码数据进行增强，有利于后续译码过程中基于增强后的第0段编码数据实现流译码。
一种可能的实施方式中，网络设备继续获取第q段编码数据对应的标记数据，其中，q为2≤q≤m-1，并将第q段编码数据对应的标记数据与增强后的第0段编码数据对应的标记数据进行F运算，得到F运算后的第q段编码数据对应的标记数据，对F运算后的第q段编码数据对应的标记数据进行Polar码译码，得到第q段编码数据对应的译码数据。并且，根据第q段编码数据对应的标记数据和第q段编码数据对应的译码数据对增强后的第0段编码数据对应的标记数据进行增强。
该方法中，对于第2段编码数据直至第m-1段编码数据，都采用相同的方法进行译码。并且，随着译码的进行不断增强第0段编码数据对应的标记数据，有利于实现流译码。
需要注意的是，上述第四方面中所述的方法，也可以通过终端设备所执行。在这种情况下，网络设备为编码侧，终端设备为译码侧。
第五方面，本申请实施例提供一种数据处理装置，该数据处理装置可以是终端设备，也可以是终端设备中的装置，或者是能够和终端设备匹配使用的装置。一种设计中，该数据处理装置可以包括执行如第一方面至第三方面，和第一方面至第三方面中任一种可能的实施方式中描述的方法/操作/步骤/动作所一一对应的模块，该模块可以是硬件电路，也可以是软件，也可以是硬件电路结合软件实现。一种设计中，该数据处理装置可以包括处理单元和通信单元。
其中，对终端设备执行的方法/操作/步骤/动作的具体描述可以参考上述第一方面到第三方面，和第一方面至第三方面中任一种可能的实施方式中对应的描述，此处不再赘述。可以理解的是，该数据处理装置也可以实现如第一方面到第三方面中可以实现的效果。
第六方面，本申请实施例提供一种数据处理装置，该数据处理装置可以是网络设备，也可以是网络设备中的装置，或者是能够和网络设备匹配使用的装置。一种设计中，该数据处理装置可以包括执行如第四方面和第四方面中任一种可能的实施方式中描述的方法/操作/步骤/动作所一一对应的模块，该模块可以是硬件电路，也可以是软件，也可以是硬件电路结合 软件实现。一种设计中，该数据处理装置可以包括处理单元和通信单元。
其中，对网络设备执行的方法的具体描述可以参考上述第四方面和第四方面中任一种可能的实施方式中对应的描述，此处不再赘述。可以理解的是，该数据处理装置也可以实现如第四方面中可以实现的效果。
第七方面，本申请实施例提供一种通信装置，该通信装置由输入输出接口和逻辑电路组成，所述输入输出接口用于输入或输出数据；所述逻辑电路按照如第一方面到第三方面，和第一方面至第三方面中任一种可能的实施方式中的方法对数据进行处理，获取处理后的数据。
第八方面，本申请实施例提供一种通信装置，该通信装置由输入输出接口和逻辑电路组成，所述输入输出接口用于输入或输出数据；所述逻辑电路按照如第四方面和第四方面任一种可能的实施方式中的方法对数据进行处理，获取处理后的数据。
第九方面，本申请实施例提供一种终端设备，包括：处理器，该处理器与存储器耦合，该存储器用于存储指令，当指令被处理器执行时，使得该终端设备实现上述第一方面至第四方面，或第一方面至第四方面任一种可能的实施方式中的方法。
第十方面，本申请实施例提供一种网络设备，包括：处理器，该处理器与存储器耦合，该存储器用于存储指令，当指令被处理器执行时，使得该网络设备实现上述第一方面至第四方面，或第一方面至第四方面任一种可能的实施方式中的方法。
第十一方面，本申请实施例提供一种通信系统，该通信系统包括发送端和接收端。其中，发送端用于实现上述第一方面至第三方面，和第一方面至第三方面任一种可能的实施方式中的方法中的功能。接收端用于实现上述第四方面，和第四方面任一种可能的实施方式中的方法中的功能。可选的，该通信系统可以包括如第五方面和第六方面中描述的数据处理装置，或者可以包括如第七方面和第八方面中描述的通信装置，或者可以包括如第九方面和第十方面中描述的设备。
第十二方面，本申请实施例中还提供一种计算机可读存储介质，所述计算机可读存储介质上存储指令，当所述指令在计算机上运行时，使得计算机执行第一方面至第四方面，和第一方面至第四方面任一种可能的实施方式中的方法。
第十三方面，本申请实施例提供了一种芯片系统，该芯片系统包括处理器，还可以包括存储器，用于实现上述第一方面至第四方面，和第一方面至第四方面任一种可能的实施方式中的方法中的功能。该芯片系统可以由芯片构成，也可以包含芯片和其他分立器件。
第十四方面，本申请实施例中还提供一种计算机程序产品，包括指令，当所述指令在计算机上运行时，使得计算机执行第一方面至第四方面，和第一方面至第四方面任一种可能的实施方式中的方法。
附图说明
图1为本申请提供的一种通信系统的示意图；
图2为一种8×8的polar码编码示意图；
图3为本申请提供的一种数据处理方法的流程示意图；
图4为本申请提供的一种支持流译码的流编码的示意图；
图5为本申请提供的一种流编码的示意图；
图6为本申请提供的另一种数据处理方法的流程示意图；
图7为本申请提供的一种流译码的示意图；
图8为本申请提供的数据处理方法的性能分析图；
图9为本申请提供的一种装置的示意图；
图10为本申请提供的一种通信设备的示意图。
具体实施方式
在本申请中，“/”可以表示前后关联的对象是一种“或”的关系，例如，A/B可以表示A或B；“和/或”可以用于描述关联对象存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况，其中A，B可以是单数或者复数。为了便于描述本申请的技术方案，在本申请中，可以采用“第一”、“第二”等字样对功能相同或相似的技术特征进行区分。该“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。在本申请中，“示例性的”或者“例如”等词用于表示例子、例证或说明，被描述为“示例性的”或者“例如”的任何或设计方案不应被解释为比其它或设计方案更优选或更具优势。使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念，便于理解。
下面将结合本申请中的附图，对本申请中的技术方案进行描述。
本申请提供了一种数据处理方法，该方法构造了一个全新的Polar码的编码矩阵，通过该编码矩阵对待编码的信息比特进行处理，从而实现Polar码的流编码和/或流译码。该数据处理方法可以应用于通信系统中，系统架构如图1所示。其中，该通信系统包括网络设备和终端设备，网络设备可以向终端设备提供通信服务。
本申请提及的通信系统包括但不限于：窄带物联网系统(narrow band-Internet of things，NB-IoT)、全球移动通信系统(global system for mobile communications，GSM)、增强型数据速率GSM演进系统(enhanced data rate for GSM evolution，EDGE)、宽带码分多址系统(wideband code division multiple access，WCDMA)、码分多址2000系统(code division multiple access，CDMA2000)、时分同步码分多址系统(time division-synchronization code division multiple access，TD-SCDMA)，长期演进系统(long term evolution，LTE)以及5G移动通信系统的三大应用场景增强移动宽带(enhanced mobility broad band，eMBB)，超高可靠与低时延通信(ultra-reliable and low latency communications，URLLC)和增强型机器类通信(enhanced machine-type communication，eMTC)以及未来的通信系统(例如6G/7G等)。
其中，网络设备可以是能和终端设备进行通信的设备。网络设备可以是基站、中继站或接入点。其中，基站可以是全球移动通信(global system for mobile communication，GSM)系统或码分多址(code division multiple access，CDMA)网络中的基站收发台(base transc eiver station，BTS)，也可以是宽带码分多址(wideband code division multiple access，WC DMA)系统中的3G基站NodeB，还可以是长期演进(long term evolution，LTE)系统中的evolutional NodeB(简称为eNB或eNodeB)。网络设备还可以是卫星通信系统中的卫星。网络设备还可以是云无线接入网络(cloud radio access network，CRAN)场景下的无线控制器。网络设备还可以是5G网络中的网络设备或者未来演进的共用陆地移动网(public land mobil e network，PLMN)网络中的网络设备(例如gNodeB)。网络设备还可以是可穿戴设备、无人机，或者车联网中的设备(例如车联万物设备(vehicle to everything，V2X))，或者设备间(device to device，D2D)通信中的通信设备，或者应用于未来的通信系统中的网络设备。
其中，终端设备可以是用户设备(user equipment，UE)、接入终端、终端单元、终端站、移动站、移动台、远方站、远程终端、移动设备、终端、无线通信设备、终端代理或终端装置等。接入终端可以是蜂窝电话、无绳电话、会话启动协议(session initiation protocol，SIP) 电话、无线本地环路(wireless local loop，WLL)站、个人数字处理(personal digital assistant，PDA)、具有无线通信功能的手持设备、计算设备或连接到无线调制解调器的其它处理设备、可穿戴设备、无人机、V2X设备、D2D设备，5G网络中的终端设备、未来演进的PLMN网络中的终端设备或未来的通信系统中的终端设备等。
可以理解的是，本申请为编码方案，可以用于专用网设备或者通用设备，可以用于网络设备，也可以用于各种终端设备等。本申请可以通过专用芯片(例如专用集成电路(application specific integrated circuit，ASIC)实现，也可以通过可编程芯片(例如现场可编程逻辑门阵列(field programmable gate array，FPGA)实现，还可以通过软件(存储器中程序代码)实现，本申请不作限定。
一、本申请的相关概念
1、Polar码：
Polar码是一种能够被严格证明达到信道容量的信道编码方案，Polar码具有高性能，低复杂度，匹配方式灵活等特点。目前Polar码已经被确定为第五代移动通信(the 5 th generation，5G)控制信道增强移动宽带(enhanced mobile broadband，eMBB)场景的上行和/或下行控制信道编码方案。
例如，图2为一种8×8的polar码编码示意图，其中，待编码比特按照各自的可靠度进行排序，依次排列在待编码块中的不同位置。通常来说，可靠度较高的比特被设置为信息比特(data)，可靠度较低的比特被设置为固定比特(frozen)。固定比特的值通常设置为0，在实际传输中发送端和接收端都已知。如图2所示，u 7,u 6,u 5,u 3为可靠度靠前的四位比特，分别设置为信息比特；u 4,u 2,u 1,u 0为可靠度靠后的四位比特，分别设置为固定比特。
其中，Polar码是一种线性块码。其生成矩阵为G N，其编码过程为
Figure PCTCN2022110968-appb-000006
其中，
Figure PCTCN2022110968-appb-000007
是一个二进制的行矢量，长度为N(即码长)。G N是一个N×N的矩阵，且
Figure PCTCN2022110968-appb-000008
其中，
Figure PCTCN2022110968-appb-000009
定义为log 2(N)个矩阵F 2的克罗内克(Kronecker)乘积。例如，当N＝4时，log 2(N)＝log 2(4)＝2，则
Figure PCTCN2022110968-appb-000010
当N＝8时，log 2(N)＝log 2(8)＝3，则
Figure PCTCN2022110968-appb-000011
因此，标准的Polar码的母码长度N＝2 n，n为正整数。
2、本申请提供的一种编码矩阵G：
本申请提供的编码矩阵
Figure PCTCN2022110968-appb-000012
其中，G为大小为(m×2 n)×(m×2 n)的矩阵，m和n为正整数，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，表示为
Figure PCTCN2022110968-appb-000013
矩阵O为大小为2 n×2 n的全零矩阵。
也就是说，如果将该编码矩阵G视为一个m×m的矩阵，矩阵中的每一个元素均为一个2 n×2 n的矩阵，矩阵的对角线中各元素均为矩阵G N′，矩阵的底边中各元素均为矩阵G N′，除对角线和底边之外的元素均为矩阵O。
其中，该编码矩阵G的母码长度N′＝m×2 n。可以理解的是，当m＝1或者m＝2时，该编码矩阵G和普通Polar码的编码矩阵相同。当m≥3时，编码矩阵
Figure PCTCN2022110968-appb-000014
3、本申请提供的另一种编码矩阵G′：
针对编码矩阵G进行初等列变换，可以得到变换后的编码矩阵
Figure PCTCN2022110968-appb-000015
可以理解的是，将编码矩阵G的前(m-1)×2 n列和后2 n列做初等列变换，可以得到编码矩阵G′。其中，与编码矩阵G相同的是，编码矩阵G′为大小为(m×2 n)×(m×2 n)的矩阵，m和n为正整数，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，表示为
Figure PCTCN2022110968-appb-000016
矩阵O为大小为2 n×2 n的全零矩阵，该编码矩阵G′的母码长度N′＝m×2 n。
4、F运算：
F运算为Polar码的译码基本运算，采用预定义的F函数(f-function)进行处理。其中，F函数的输入为L 0和L 1，且F函数可以简化为：
f(L 0,L 1)＝(sig(L 0)∧sig(L 1)？-1:1)*(abs(L 0)>abs(L 1)？abs(L 1):abs(L 0))，
其中，sig为取符号操作，如果立即数大于0，返回值为0，否则返回值为1。abs为取绝对值操作。例如，假设有长度均为N′的编码数据x 0和x m-1，对x 0和x m-1进行F运算，比较x 0和x m-1的符号，若两者一致则立即数的取值为1，否则取值为-1。
5、G运算：
G运算为Polar码的译码基本运算，采用预定义的G函数(g-function)进行处理。其中，G函数的输入为L 0、L 1和反馈值B，且G函数为：g(L 0,L 1,B)＝(B＝＝0)？L 1+L 0:L 1-L 0。
二、本申请提供的实现流编码的数据处理方法
1、采用编码矩阵G实现流编码的流程：
图3为本申请提供的一种数据处理方法的流程示意图。该数据处理方法可以由终端设备所执行，也可以由网络设备所执行，主要执行编码的流程，包括以下步骤：
S101，获取信息比特序列。
其中，信息比特序列包括多个待编码的信息比特。例如，信息比特序列可以表示为 {a 0,a 1,a 2,...,a k-1}，该信息比特序列中的一个元素表示一个待编码比特。可以理解的是，该信息比特序列的长度可能不为指定码长(例如长度不为m×2 n)，可以对该信息比特序列进行处理(例如在信息比特序列中插入冻结位)，使得对该信息比特序列进行编码后得到的编码数据的长度为N′＝m×2 n。
还可以理解的是，本申请中的待编码比特还可以包括循环冗余校验(cyclic redundancy check，CRC)比特和/或奇偶校验(parity check，PC)比特，同时可能还涉及到对其中某些比特甚至全部比特进行加扰等操作，由于与本申请的方案实质不相关，所以均以待编码比特统一予以陈述，此处不再赘述。
S102，根据编码矩阵G对信息比特序列进行编码，得到编码数据。
其中，对编码矩阵G的描述可以参考前文的相关概念，此处不再赘述。下面通过一个示例对编码过程进行描述。假设信息比特序列为u＝{a 0,a 1,a 2,...,a k-1}，编码过程可以表示为：
Figure PCTCN2022110968-appb-000017
其中，u N为信息比特序列，将u N与编码矩阵G进行模二乘，得到编码数据x N，x N的长度为m×2 n。
一种可能的实施方式中，可以将信息比特序列划分为m个分段，也即是信息比特序列包括m个分段，每一个分段的Polar生成矩阵为G N′。其中，每一个分段的长度为2 n，则每一个分段都可以与大小为2 n×2 n的Polar生成矩阵G N′进行模二乘运算，并且分段之间进行信息交织，可以得到编码数据。具体来说，采用该实施方式对信息比特序列进行编码，得到编码数据，包括两种情况：
情况一：m个分段中的信息比特个数为k 0,k 1,...,k m-1，k 0小于k m-1，且k 0≤k 1≤...≤k m-1。
其中，k 0为第0个分段中的信息比特个数，k 1为第1个分段中的信息比特个数，以此类推，k m-1为第m-1个分段中的信息比特个数。并且，第0个分段中的信息比特个数小于第m-1个分段中的信息比特个数，第m-1个分段中的信息比特个数最多(也即是最后一个分段包括了最多的信息比特)。在这种情况下，编码过程包括以下步骤：
获取m份缓存数据，其中，第j份缓存数据为采用矩阵G N′对信息比特序列的第j个分段进行编码后得到的，所述j满足0≤j≤m-1；
编码数据包括m段，
其中，第0段编码数据为第m-1份缓存数据，
第i段编码数据为将第j份缓存数据与第m-1份缓存数据进行异或处理得到的，i满足1≤i≤m-1，j满足0≤j≤m-2。
例如，终端设备首先采用矩阵G N′对信息比特序列中的每一个分段分别进行模二乘运算，得到m份缓存数据，然后采用第m-1份缓存数据分别与前m-2份缓存数据进行异或处理(例如模二加运算)，得到编码数据。
可以理解的是，采用情况一中描述的编码过程对信息比特序列进行编码，与采用编码矩阵G对信息比特序列进行编码，编码原理是类似的。
情况二：m个分段中的信息比特个数为k 0,k 1,...,k m-1，k 1小于k 0，且k 1≤...≤k m-1≤k 0。
其中，k 0为第0个分段中的信息比特个数，k 1为第1个分段中的信息比特个数，以此类推，k m-1为第m-1个分段中的信息比特个数。并且，第0个分段中的信息比特个数大于第1 个分段中的信息比特个数，第0个分段中的信息比特个数最多(也即是第1个分段包括了最多的信息比特)。在这种情况下，编码数据包括m段，其中，第0段编码数据为根据矩阵G N′对信息比特序列的第0个分段进行编码得到的；第i段编码数据为根据矩阵G N′对信息比特序列的第i个分段进行编码后，再与第0段编码数据进行异或处理，得到的。
例如，终端设备首先采用矩阵G N′对信息比特序列中的第0个分段进行模二乘运算，得到第0段编码数据，再采用矩阵G N′对信息比特序列中的第1个分段进行模二乘运算，并且将运算结果与第0段编码数据进行异或处理(例如模二加运算)，得到第1段编码数据，以此类推，直至得到第m-1段编码数据。可以理解的是，上述编码的过程可以视为一种流编码的过程，也即是编码器可以一边接收待编码的数据，一边将已接收的待编码的数据进行编码后并发送。
可选的，情况二中描述的编码过程所对应的编码矩阵G′为对编码矩阵G进行初等列变换得到的，其中，编码矩阵
Figure PCTCN2022110968-appb-000018
也就是说，采用情况二中描述的编码过程对信息比特序列进行编码，与采用编码矩阵G对信息比特序列进行编码，编码原理是类似的。
S103，发送编码数据。
其中，若S102中描述的编码流程可以实现流编码(例如S102中描述的情况二)，终端设备在编码完成一段编码数据后，就可以发送该段编码数据，而不用等待信息比特序列中的全部比特编码完成后再发送全部编码数据。若S102中描述的编码流程是为了实现流译码而设计的(例如S102中描述的情况一)，终端设备在信息比特序列中的全部比特编码完成后再发送全部编码数据。
可见，本申请提供的数据处理方法设计了一种全新的Polar码编码矩阵G，当终端设备采用该编码矩阵G对待编码的信息比特进行编码时，可以在编码过程中接收一部分信息比特之后就可以对该部分信息比特进行编码并发送编码数据，也即是实现了流编码，有利于降低终端设备中编码器和缓存的大小。并且，采用该编码矩阵对待编码的信息比特进行编码得到编码数据，有利于实现流译码。
2、支持流译码的流编码过程
图4为本申请提供的一种支持流译码的流编码的示意图。其中，信息比特序列可以表示为{a 0,a 1,a 2,...,a k-1}，该信息比特序列中的一个元素表示一个待编码比特。将该信息比特序列分为m个子段，每一个子段中分配k i个信息比特。将最先收到的k 0个信息比特
Figure PCTCN2022110968-appb-000019
插入冻结位后得到
Figure PCTCN2022110968-appb-000020
再将
Figure PCTCN2022110968-appb-000021
与矩阵G N′进行模二乘运算，得到
Figure PCTCN2022110968-appb-000022
将
Figure PCTCN2022110968-appb-000023
保留至缓存中。采用针对k 0个信息比特同样的处理流程，可以得到
Figure PCTCN2022110968-appb-000024
并将
Figure PCTCN2022110968-appb-000025
保留至缓存中。
应注意，发送
Figure PCTCN2022110968-appb-000026
时的顺序为：
首先，将
Figure PCTCN2022110968-appb-000027
作为
Figure PCTCN2022110968-appb-000028
发送；
然后，将
Figure PCTCN2022110968-appb-000029
和
Figure PCTCN2022110968-appb-000030
进行异或后得到并发送
Figure PCTCN2022110968-appb-000031
其次，将
Figure PCTCN2022110968-appb-000032
和
Figure PCTCN2022110968-appb-000033
进行异或后得到并发送
Figure PCTCN2022110968-appb-000034
以此类推，将
Figure PCTCN2022110968-appb-000035
和
Figure PCTCN2022110968-appb-000036
进行异或后得到并发送
Figure PCTCN2022110968-appb-000037
当按照上述顺序发送完成后，流编码过程完成。
3、支持流编码的流程
图5为本申请提供的一种流编码的示意图。其中，信息比特序列可以表示为{a 0,a 1,a 2,...,a k-1}，该信息比特序列中的一个元素表示一个待编码比特。将该信息比特序列分为m个子段，每一个子段中分配k i个信息比特。将最先收到的k 0个信息比特
Figure PCTCN2022110968-appb-000038
插入冻结位后得到
Figure PCTCN2022110968-appb-000039
再将
Figure PCTCN2022110968-appb-000040
与矩阵G N′进行模二乘运算，得到
Figure PCTCN2022110968-appb-000041
将
Figure PCTCN2022110968-appb-000042
保留一份至缓存中，并将
Figure PCTCN2022110968-appb-000043
作为
Figure PCTCN2022110968-appb-000044
发送。
将接下来收到的k 1个信息比特
Figure PCTCN2022110968-appb-000045
插入冻结位后得到
Figure PCTCN2022110968-appb-000046
再将
Figure PCTCN2022110968-appb-000047
与矩阵G N′进行模二乘运算，得到
Figure PCTCN2022110968-appb-000048
从缓存中获取
Figure PCTCN2022110968-appb-000049
将
Figure PCTCN2022110968-appb-000050
和
Figure PCTCN2022110968-appb-000051
进行异或后得到
Figure PCTCN2022110968-appb-000052
发送
Figure PCTCN2022110968-appb-000053
采用针对k 1个信息比特同样的处理流程，可以得到并发送
Figure PCTCN2022110968-appb-000054
在发送完成
Figure PCTCN2022110968-appb-000055
后，删除缓存
Figure PCTCN2022110968-appb-000056
流编码过程完成。
三、本申请提供的实现流译码的数据处理方法
1、流译码的流程
图6为本申请提供的另一种数据处理方法的流程示意图。该数据处理方法可以由终端设备所执行，也可以由网络设备所执行。可以理解的是，当终端设备执行此处第三部分描述的数据处理方法时，即终端设备为译码侧，则网络设备执行前述第二部分中描述的数据处理方法，即网络设备为编码侧。当执行译码的流程时，包括以下步骤：
S201，接收编码数据，编码数据是根据编码矩阵G对信息比特序列进行编码得到的。
其中，对编码矩阵G、编码数据、以及根据编码矩阵G对信息比特序列进行编码的描述参考前文第二部分中对应的描述，此处不再赘述。例如，为了支持流译码，编码数据可以是基于编码矩阵G对信息比特序列进行编码得到的，也可以是基于S102中情况一中描述的方式对信息比特序列进行编码得到的。
S202，对编码数据进行译码，得到译码数据。
其中，对编码数据进行译码的过程为流译码流程，终端设备可以先对接收到的第0段编码数据和第1段编码数据进行译码，也即是，在译码过程中接收一部分信息后就能对该部分信息进行译码。具体来说，可以包括以下步骤：
s11，获取第0段编码数据对应的标记数据和第1段编码数据对应的标记数据；
s12，将第0段编码数据对应的标记数据和第1段编码数据对应的标记数据进行F运算，得到F运算后的第1段编码数据对应的标记数据；
s13，对F运算后的第1段编码数据对应的标记数据进行Polar码译码，得到第1段编码数据对应的译码数据；
s14，根据第1段编码数据对应的标记数据和第1段编码数据对应的译码数据对第0段编码数据对应的标记数据进行增强。
其中，第0段编码数据对应的标记数据为第0段编码数据的对数似然比(log likelihood ratio，LLR)，第1段编码数据对应的标记数据为第1段编码数据的LLR。将第0段编码数据的LLR和第1段编码数据的LLR作为F函数的输入，得到F运算后的第1段编码数据对应的标记数据。其中，对F函数的描述参考前文的描述，此处不再赘述。
其中，对F运算后的第1段编码数据对应的标记数据进行Polar码译码的方法可以参考现有的Polar码译码方式，本申请不作限定。将第0段编码数据的LLR、第1段编码数据的LLR和第1段编码数据对应的译码数据作为G函数的输入，从而实现对第0段编码数据对应 的标记数据进行增强，有利于后续译码过程中基于增强后的第0段编码数据实现流译码。其中，对G函数的描述参考前文的描述，此处不再赘述。
一种可能的实施方式中，第0段编码数据对应的标记数据可以为第0段编码数据的似然概率，第1段编码数据对应的标记数据可以为第1段编码数据的似然概率。在这种情况下，上述步骤s12将变为：将第0段编码数据对应的标记数据和第1段编码数据对应的标记数据进行概率运算，得到在概率域中的第1段编码数据对应的标记数据。可以理解的是，后续的处理流程仍然按照s13和s14执行，可以实现对第0段编码数据对应的标记数据进行增强。
进一步，针对后续接收的每一段编码数据，处理方式与上述s11～s14是类似的，可以包括以下步骤：
s15，获取第q段编码数据对应的标记数据，q为2≤q≤m-1，
s16，将第q段编码数据对应的标记数据与增强后的第0段编码数据对应的标记数据进行F运算，得到F运算后的第q段编码数据对应的标记数据；
s17，对F运算后的第q段编码数据对应的标记数据进行Polar码译码，得到第q段编码数据对应的译码数据；
s18，根据第q段编码数据对应的标记数据和第q段编码数据对应的译码数据对增强后的第0段编码数据对应的标记数据进行增强。
例如，获取第2段编码数据对应的标记数据，并将第2段编码数据对应的标记数据与增强后的第0段编码数据对应的标记数据进行F运算，得到F运算后的第2段编码数据对应的标记数据；对F运算后的第2段编码数据对应的标记数据进行Polar码译码，得到第2段编码数据对应的译码数据，根据第2段编码数据对应的标记数据和第2段编码数据对应的译码数据对增强后的第0段编码数据对应的标记数据进行二次增强，得到二次增强后的第0段编码数据对应的标记数据。上述步骤的具体实施方式，可以参考s11～s14对应的具体实施方式，此处不再赘述。
可见，本申请提供的数据处理方法在接收该编码数据后，可以支持在译码过程中接收一部分信息后就能对该部分信息进行译码，也即是实现了流译码，可以降低译码器的大小，从而降低译码侧的开销。
2、一种流译码流程的具体示例
图7为本申请提供的一种流译码的示意图。当接收第0段编码数据(长度为N′＝2 n)时，根据前文实施例中的描述，第0段编码数据为第m-1份缓存数据，则将第0段编码数据标记为
Figure PCTCN2022110968-appb-000057
后并缓存。其中，
Figure PCTCN2022110968-appb-000058
为
Figure PCTCN2022110968-appb-000059
发送数据的LLR，
Figure PCTCN2022110968-appb-000060
即为前文第二部分第三小节中描述的将
Figure PCTCN2022110968-appb-000061
作为
Figure PCTCN2022110968-appb-000062
发送。
当接收第1段编码数据(长度为N′＝2 n)时，第1段编码数据为第0份缓存数据，则将第1段编码数据标记为
Figure PCTCN2022110968-appb-000063
后，与
Figure PCTCN2022110968-appb-000064
进行F运算(例如采用Polar码定义的f-function)，得到
Figure PCTCN2022110968-appb-000065
对
Figure PCTCN2022110968-appb-000066
进行普通Polar码译码得到译码数据
Figure PCTCN2022110968-appb-000067
对
Figure PCTCN2022110968-appb-000068
进行G运算(例如采用Polar码定义的g-function)，得到增强的
Figure PCTCN2022110968-appb-000069
当接收第2段编码数据(长度为N′＝2 n)时，第2段编码数据为第1份缓存数据，则将第2段编码数据标记为
Figure PCTCN2022110968-appb-000070
后，与
Figure PCTCN2022110968-appb-000071
进行F运算，得到
Figure PCTCN2022110968-appb-000072
对
Figure PCTCN2022110968-appb-000073
进行普通Polar码译码得到译码数据
Figure PCTCN2022110968-appb-000074
对
Figure PCTCN2022110968-appb-000075
进行G运算，得到二次增强的
Figure PCTCN2022110968-appb-000076
可以理解的是，采用同样的方法可以得到译码数据
Figure PCTCN2022110968-appb-000077
同时随着译码的进行可以得到多次增强的
Figure PCTCN2022110968-appb-000078
最后对多次增强的
Figure PCTCN2022110968-appb-000079
进行普通polar码译码得到译码数据
Figure PCTCN2022110968-appb-000080
流译码过程完成。
四、本申请提供的数据处理方法的性能分析
图8为本申请提供的数据处理方法的性能分析图。该性能分析图是采用码长为N′＝{128,512,2048}，码率R＝1/8的仿真译码器得到的译码性能示意图，其中，该性能分析图的横坐标为EsN0，表示每个符号能量与噪声功率谱密度的比值；纵坐标为误块率(block error rate，BLER)，用来衡量系统性能测试。可以理解的是，采用前文第三部分中描述的流译码的流程，译码器只需要接收两段编码数据(也即是N′×2的LLR)就可以开始译码，因此译码器的大小可以设计为N′×2。
其中，实线、第一种虚线和第二种虚线三种线型为一组，可以用于对比相同的信息比特序列下，采用不同大小的译码器和相同的译码方式，或者采用相同大小的译码器和不同的译码方式时，译码性能的区别。
第一组：分别带有菱形符号的实线、第一种虚线和第二种虚线为第一组译码性能对比。其中，假设信息比特序列中信息比特个数为K＝64，则发送长度E＝K/R＝64/(1/8)＝512；假设译码器大小为256或512，译码方式为采用现有的Polar码译码或者采用本申请提供的流译码。例如，带有菱形符号的第一种虚线表示发送长度E＝512，译码器大小为512，信息比特个数为K＝64，且采用现有的Polar码译码时的译码性能；带有菱形符号的实线表示发送长度E＝512，译码器大小为256，信息比特个数为K＝64，且采用流译码时的译码性能；带有菱形符号的第二种虚线表示发送长度E＝512，译码器大小为256，信息比特个数为K＝64，且采用现有的Polar码译码时的译码性能。对第一组进行比较可见，在相同的EsN0的情况下，流译码的译码性能比译码器更大(也即是码长更长)的普通Polar码的译码性能差一点，但是流译码的译码侧采用更小的译码器，显著降低了译码侧的开销。在相同的EsN0和相同译码器大小的情况下，流译码的译码性能优于普通Polar码的译码性能。
第二组：分别带有正方形符号的实线、第一种虚线和第二种虚线为第二组译码性能对比。其中，假设信息比特序列中信息比特个数为K＝256，则发送长度E＝K/R＝256/(1/8)＝2048；假设译码器大小为1024或2048，译码方式为采用现有的Polar码译码或者采用本申请提供的流译码。例如，带有正方形符号的第一种虚线表示发送长度E＝2048，译码器大小为2048，信息比特个数为K＝256，且采用现有的Polar码译码时的译码性能；带有正方形符号的实线表示发送长度E＝2048，译码器大小为1024，信息比特个数为K＝256，且采用流译码时的译码性能；带有正方形符号的第二种虚线表示发送长度E＝2048，译码器大小为2048，信息比特个数为K＝256，且采用现有的Polar码译码时的译码性能。对第二组进行比较可见，在相同的EsN0的情况下，流译码的译码性能比译码器更大(也即是码长更长)的普通Polar码的译码性能差一点，但是流译码的译码侧采用更小的译码器，显著降低了译码侧的开销。在相同的EsN0和相同译码器大小的情况下，流译码的译码性能优于普通Polar码的译码性能。
第三组：分别带有星号的实线、第一种虚线和第二种虚线为第二组译码性能对比。其中，假设信息比特序列中信息比特个数为K＝1024，则发送长度E＝K/R＝1024/(1/8)＝8192；假设译码器大小为4096或8192，译码方式为采用现有的Polar码译码或者采用本申请提供的流译码。例如，带有正方形符号的第一种虚线表示发送长度E＝8192，译码器大小为8192，信息比特个数为K＝1024，且采用现有的Polar码译码时的译码性能；带有星号的实线表示发送长度E＝8192，译码器大小为4096，信息比特个数为K＝1024，且采用流译码时的译码性能；带有星号的第二种虚线表示发送长度E＝8192，译码器大小为8192，信息比特个数为K＝1024，且采用现有的Polar码译码时的译码性能。对第三组进行比较可见，在相同的EsN0的情况下， 流译码的译码性能比译码器更大(也即是码长更长)的普通Polar码的译码性能差一点，但是流译码的译码侧采用更小的译码器，显著降低了译码侧的开销。在相同的EsN0和相同译码器大小的情况下，流译码的译码性能优于普通Polar码的译码性能。
为了实现本申请提供的方法中的各功能，本申请提供的装置或设备可以包括硬件结构和/或软件模块，以硬件结构、软件模块、或硬件结构加软件模块的形式来实现上述各功能。上述各功能中的某个功能以硬件结构、软件模块、还是硬件结构加软件模块的方式来执行，取决于技术方案的特定应用和设计约束条件。本申请中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。另外，在本申请各个实施例中的各功能模块可以集成在一个处理器中，也可以是单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
图9为本申请提供的一种装置的示意图。该装置可以包括执行如图3至图7对应的方法实施例中所描述的方法/操作/步骤/动作所一一对应的模块，该模块可以是硬件电路，也可以是软件，也可以是硬件电路结合软件实现。例如，该装置可以称为数据处理装置，也可以称为通信装置。
该装置包括通信单元901和处理单元902。用于实现前述实施例中终端设备或者网络设备所执行的方法。
一种可能的实施方式中，处理单元902用于获取信息比特序列，并根据编码矩阵G对所述信息比特序列进行编码，得到编码数据。其中，编码矩阵
Figure PCTCN2022110968-appb-000081
G为大小为(m×2 n)×(m×2 n)的矩阵，m和n为正整数，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，矩阵O为大小为2 n×2 n的全零矩阵。通信单元901用于发送编码数据。
可选的，信息比特序列包括m个分段，每一个分段的Polar生成矩阵为G N′。
可选的，m个分段中的信息比特个数为k 0,k 1,...,k m-1，其中，k 0小于k m-1，且k 0≤k 1≤...≤k m-1。
可选的，第i个分段的信息比特个数为k i，所述i满足0≤i≤m-1。
可选的，处理单元902用于获取m份缓存数据，其中，第j份缓存数据为采用矩阵G N′对信息比特序列的第j个分段进行编码后得到的，j满足0≤j≤m-1；编码数据包括m段，其中，第0段编码数据为第m-1份缓存数据，第i段编码数据为将第j份缓存数据与第m-1份缓存数据进行异或处理得到的，i满足1≤i≤m-1，j满足0≤j≤m-2。
可选的，通信单元901用于首先发送第m-1份缓存数据，再依次发送第i段编码数据，1≤i≤m-1。
可选的，处理单元902用于对编码矩阵G进行初等列变换，变换后的编码矩阵
Figure PCTCN2022110968-appb-000082
并根据变换后的编码矩阵G′对信息比特序列进行编码，得到编码数据。
可选的，m个分段中的信息比特个数为k 0,k 1,...,k m-1，k 1小于k 0，且k 1≤...≤k m-1≤k 0。
可选的，编码数据包括m段，其中，第0段编码数据为根据矩阵G N′对信息比特序列的第0个分段进行编码得到的；第i段编码数据为根据矩阵G N′对信息比特序列的第i个分段进行编码后，再与第0段编码数据进行异或处理，得到的。
该实施方式中通信单元901和处理单元902的具体执行流程还可以参考图3至图7对应的方法实施例中的描述，此处不再赘述。该装置所实现的数据处理方法设计了一种全新的Polar码编码矩阵G，当终端设备采用该编码矩阵G对待编码的信息比特进行编码时，可以在编码过程中接收一部分信息比特之后就可以对该部分信息比特进行编码并发送编码数据，也即是实现了流编码，有利于降低终端设备中编码器和缓存的大小。并且，采用该编码矩阵对待编码的信息比特进行编码得到编码数据，有利于实现流译码。
另一种可能的实施方式中，处理单元902用于获取信息比特序列，信息比特序列包括m个分段，并采用每一个分段的Polar生成矩阵G N′对每一个分段进行处理，得到m份缓存数据，其中，矩阵G N′为大小为2 n×2 n的Polar生成矩阵。处理单元902还用于基于m份缓存数据，得到编码数据。编码数据包括m段，其中，第0段编码数据为第m-1份缓存数据，第i段编码数据为将第j份缓存数据与所述第m-1份缓存数据进行异或处理得到的，i满足1≤i≤m-1，所述j满足0≤j≤m-2。通信单元901用于发送编码数据。
可选的，m个分段中的信息比特个数为k 0,k 1,...,k m-1，其中，k 0小于k m-1，且k 0≤k 1≤...≤k m-1。
可选的，第i个分段的信息比特个数为k i，所述i满足0≤i≤m-1。
可选的，处理单元902用于根据编码矩阵G对信息比特序列进行编码，得到编码数据。其中，编码矩阵
Figure PCTCN2022110968-appb-000083
编码矩阵G为大小为(m×2 n)×(m×2 n)的矩阵，m和n为正整数，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，矩阵O为大小为2 n×2 n的全零矩阵。
该实施方式中通信单元901和处理单元902的具体执行流程还可以参考图3至图7对应的方法实施例中的描述，此处不再赘述。该装置所实现的数据处理方法将待编码的信息比特序列划分为m个分段，并针对每一个分段采用大小为2 n×2 n的Polar生成矩阵进行编码以及信息交织，并且编码后数据交织发送，有利于实现流译码。
另一种可能的实施方式中，处理单元902用于获取信息比特序列，信息比特序列包括m个分段，并采用每一个分段的Polar生成矩阵G N′对每一个分段进行处理，得到编码数据。其中，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，编码数据包括m段，第0段编码数据为根据矩阵G N′对所述信息比特序列的第0个分段进行编码得到的；第i段编码数据为根据矩阵G N′对所述信息比特序列的第i个分段进行编码后，再与第0段编码数据进行异或处理，得到的。通信单元901用于发送编码数据。
可选的，m个分段中的信息比特个数为k 0,k 1,...,k m-1，k 1小于k 0，且k 1≤...≤k m-1≤k 0。
可选的，第i个分段的信息比特个数为k i，所述i满足0≤i≤m-1。
可选的，处理单元902用于根据编码矩阵G′对信息比特序列进行编码，得到编码数据。 其中，编码矩阵
Figure PCTCN2022110968-appb-000084
编码矩阵G′为大小为(m×2 n)×(m×2 n)的矩阵，m和n为正整数，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，矩阵O为大小为2 n×2 n的全零矩阵。
该实施方式中通信单元901和处理单元902的具体执行流程还可以参考图3至图7对应的方法实施例中的描述，此处不再赘述。该装置所实现的数据处理方法将待编码的信息比特序列划分为m个分段，并针对每一个分段采用大小为2 n×2 n的Polar生成矩阵进行编码以及信息交织，可以支持在编码过程中接收一部分信息后就可以对该部分信息进行编码并发送(也即是达到支持流编码的目的)，降低编码器以及缓存的大小。
另一种可能的实施方式中，通信单元901用于接收编码数据，处理单元902用于对编码数据进行译码，得到译码数据。其中，编码数据是根据编码矩阵G对信息比特序列进行编码得到的，编码矩阵
Figure PCTCN2022110968-appb-000085
编码矩阵G为大小为(m×2 n)×(m×2 n)的矩阵，m和n为正整数，矩阵G N′为大小为2n×2n的Polar生成矩阵，矩阵O为大小为2 n×2 n的全零矩阵。
可选的，处理单元902用于获取第0段编码数据对应的标记数据和第1段编码数据对应的标记数据，将第0段编码数据对应的标记数据和第1段编码数据对应的标记数据进行F运算，得到F运算后的第1段编码数据对应的标记数据；并对F运算后的第1段编码数据对应的标记数据进行Polar码译码，得到第1段编码数据对应的译码数据；再根据第1段编码数据对应的标记数据和第1段编码数据对应的译码数据对第0段编码数据对应的标记数据进行增强。
可选的，处理单元902用于获取第q段编码数据对应的标记数据，其中，q为2≤q≤m-1，并将第q段编码数据对应的标记数据与增强后的第0段编码数据对应的标记数据进行F运算，得到F运算后的第q段编码数据对应的标记数据，对F运算后的第q段编码数据对应的标记数据进行Polar码译码，得到第q段编码数据对应的译码数据。并且，根据第q段编码数据对应的标记数据和第q段编码数据对应的译码数据对增强后的第0段编码数据对应的标记数据进行增强。
该实施方式中通信单元901和处理单元902的具体执行流程还可以参考图3至图7对应的方法实施例中的描述，此处不再赘述。该装置所实现的数据处理方法可以支持在译码过程中接收一部分信息后就能对该部分信息进行译码，降低译码器的大小。
下面对包括图9所示的多个功能单元的设备进行描述。本申请所述的设备包括图9所示的多个功能单元。图10为本申请提供的一种通信设备的示意图，用于实现上述方法实施例中的数据处理方法。该通信设备1000也可以是芯片系统。可以理解的是，该通信设备1000例如可以是终端设备，也可以是网络设备。
其中，通信设备1000包括通信接口1001和处理器1002。通信接口1001例如可以是收发器、接口、总线、电路或者能够实现收发功能的装置。其中，通信接口1001用于通过传输介质和其它设备进行通信，从而用于设备1000可以和其它设备进行通信。处理器1002用于 执行处理相关的操作。
一种可能的实施方式中，处理器1002用于获取信息比特序列，并根据编码矩阵G对所述信息比特序列进行编码，得到编码数据。其中，编码矩阵
Figure PCTCN2022110968-appb-000086
G为大小为(m×2 n)×(m×2 n)的矩阵，m和n为正整数，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，矩阵O为大小为2 n×2 n的全零矩阵。通信接口1001用于发送编码数据。
该实施方式中通信接口1001和处理器1002的具体执行流程还可以参考第一方面以及图3至图7对应的方法实施例中的描述，此处不再赘述。该通信设备所实现的数据处理方法设计了一种全新的Polar码编码矩阵G，当终端设备采用该编码矩阵G对待编码的信息比特进行编码时，可以在编码过程中接收一部分信息比特之后就可以对该部分信息比特进行编码并发送编码数据，也即是实现了流编码，有利于降低终端设备中编码器和缓存的大小。并且，采用该编码矩阵对待编码的信息比特进行编码得到编码数据，有利于实现流译码。
另一种可能的实施方式中，处理器1002用于获取信息比特序列，信息比特序列包括m个分段，并采用每一个分段的Polar生成矩阵G N′对每一个分段进行处理，得到m份缓存数据，其中，矩阵G N′为大小为2 n×2 n的Polar生成矩阵。处理器1002还用于基于m份缓存数据，得到编码数据。编码数据包括m段，其中，第0段编码数据为第m-1份缓存数据，第i段编码数据为将第j份缓存数据与所述第m-1份缓存数据进行异或处理得到的，i满足1≤i≤m-1，所述j满足0≤j≤m-2。通信接口1001用于发送编码数据。
该实施方式中通信接口1001和处理器1002的具体执行流程还可以参考第二方面以及图3至图7对应的方法实施例中的描述，此处不再赘述。该通信设备所实现的数据处理方法将待编码的信息比特序列划分为m个分段，并针对每一个分段采用大小为2 n×2 n的Polar生成矩阵进行编码以及信息交织，并且编码后数据交织发送，有利于实现流译码。
另一种可能的实施方式中，处理器1002用于获取信息比特序列，信息比特序列包括m个分段，并采用每一个分段的Polar生成矩阵G N′对每一个分段进行处理，得到编码数据。其中，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，编码数据包括m段，第0段编码数据为根据矩阵G N′对所述信息比特序列的第0个分段进行编码得到的；第i段编码数据为根据矩阵G N′对所述信息比特序列的第i个分段进行编码后，再与第0段编码数据进行异或处理，得到的。通信接口1001用于发送编码数据。
该实施方式中通信接口1001和处理器1002的具体执行流程还可以参考第三方面以及图3至图7对应的方法实施例中的描述，此处不再赘述。该通信设备所实现的数据处理方法将待编码的信息比特序列划分为m个分段，并针对每一个分段采用大小为2 n×2 n的Polar生成矩阵进行编码以及信息交织，可以支持在编码过程中接收一部分信息后就可以对该部分信息进行编码并发送(也即是达到支持流编码的目的)，降低编码器以及缓存的大小。
另一种可能的实施方式中，通信接口1001用于接收编码数据，处理器1002用于对编码数据进行译码，得到译码数据。其中，编码数据是根据编码矩阵G对信息比特序列进行编码得到的，编码矩阵
Figure PCTCN2022110968-appb-000087
编码矩阵G为大小为(m×2 n)×(m×2 n)的矩阵， m和n为正整数，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，矩阵O为大小为2 n×2 n的全零矩阵。
该实施方式中通信接口1001和处理器1002的具体执行流程还可以参考第四方面以及图3至图7对应的方法实施例中的描述，此处不再赘述。该通信设备所实现的数据处理方法可以支持在译码过程中接收一部分信息后就能对该部分信息进行译码，降低译码器的大小。
可选的，该通信设备1000还可以包括至少一个存储器1003，用于存储程序指令和/或数据。一种实施方式中，存储器和处理器耦合。本申请中的耦合是装置、单元或模块之间的间接耦合或通信连接，可以是电性，机械或其它的形式，用于装置、单元或模块之间的信息交互。处理器可能和存储器协同操作。处理器可能执行存储器中存储的程序指令。所述至少一个存储器和处理器集成在一起。
本申请中不限定上述通信接口、处理器以及存储器之间的具体连接介质。例如，存储器、处理器以及通信接口之间通过总线连接，总线1004在图10中以粗线表示，其它部件之间的连接方式，仅是进行示意性说明，并不引以为限。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，图10中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
在本申请中，处理器可以是通用处理器、数字信号处理器、专用集成电路、现场可编程门阵列或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件，可以实现或者执行本申请中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本申请所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。
在本申请中，存储器可以是非易失性存储器，比如硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)等，还可以是易失性存储器(volatile memory)，例如随机存取存储器(random-access memory，RAM)。存储器是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。本申请中的存储器还可以是电路或者其它任意能够实现存储功能的装置，用于存储程序指令和/或数据。
本申请提供一种通信装置，该通信装置由输入输出接口和逻辑电路组成，所述输入输出接口用于输入或输出数据；所述逻辑电路按照如图3至图7对应的实施例中的方法对数据进行处理，获取处理后的数据。
本申请提供一种通信装置，该通信装置由输入输出接口和逻辑电路组成，所述输入输出接口用于输入或输出数据；所述逻辑电路按照如图3至图7对应的实施例中的方法对数据进行处理，获取处理后的数据。
本申请提供一种通信系统，该通信系统包括如图3至图7对应的实施例中的终端设备和网络设备。
本申请提供一种计算机可读存储介质。该计算机可读存储介质存储有程序或指令。当所述程序或指令在计算机上运行时，使得计算机执行如图3至图7对应的实施例中的数据处理方法。
本申请中提供一种计算机程序产品。该计算机程序产品包括指令。当所述指令在计算机上运行时，使得计算机执行如图3至图7对应的实施例中的数据处理方法。
本申请提供一种芯片或者芯片系统，该芯片或者芯片系统包括至少一个处理器和接口，接口和至少一个处理器通过线路互联，至少一个处理器用于运行计算机程序或指令，以执行如图3至图7对应的实施例中的数据处理方法。
其中，芯片中的接口可以为输入/输出接口、管脚或电路等。
上述芯片系统可以是片上系统(system on chip，SOC)，也可以是基带芯片等，其中基带芯片可以包括处理器、信道编码器、数字信号处理器、调制解调器和接口模块等。
在一种实现方式中，本申请中上述描述的芯片或者芯片系统还包括至少一个存储器，该至少一个存储器中存储有指令。该存储器可以为芯片内部的存储单元，例如，寄存器、缓存等，也可以是该芯片的存储单元(例如，只读存储器、随机存取存储器等)。
本申请提供的技术方案可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、网络设备、终端设备或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(digital subscriber line，DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机可以存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，数字视频光盘(digital video disc，DVD))、或者半导体介质等。
在本申请中，在无逻辑矛盾的前提下，各实施例之间可以相互引用，例如方法实施例之间的方法和/或术语可以相互引用，例如装置实施例之间的功能和/或术语可以相互引用，例如装置实施例和方法实施例之间的功能和/或术语可以相互引用。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (27)

  1. 一种数据处理方法，其特征在于，包括：
    获取信息比特序列；
    根据编码矩阵G对所述信息比特序列进行编码，得到编码数据；
    所述编码矩阵
    Figure PCTCN2022110968-appb-100001
    所述G为大小为(m×2 n)×(m×2 n)的矩阵，所述m和所述n为正整数，
    所述矩阵G N′为大小为2 n×2 n的Polar生成矩阵，
    所述矩阵O为大小为2 n×2 n的全零矩阵；
    发送所述编码数据。
  2. 根据权利要求1所述的方法，其特征在于，
    所述信息比特序列包括m个分段，每一个分段的Polar生成矩阵为G N′。
  3. 根据权利要求2所述的方法，其特征在于，
    所述m个分段中的信息比特个数为k 0,k 1,...,k m-1，
    所述k 0小于所述k m-1，且k 0≤k 1≤...≤k m-1。
  4. 根据权利要求2或3所述的方法，其特征在于，
    第i个分段的信息比特数量为k i，所述i满足0≤i≤m-1。
  5. 根据权利要求4所述的方法，其特征在于，所述根据编码矩阵G对所述信息比特序列进行编码，得到编码数据，包括：
    获取m份缓存数据，其中，第j份缓存数据为采用所述矩阵G N′对所述信息比特序列的第j个分段进行编码后得到的，所述j满足0≤j≤m-1；
    所述编码数据包括m段，
    其中，第0段编码数据为第m-1份缓存数据，
    第i段编码数据为将第j份缓存数据与所述第m-1份缓存数据进行异或处理得到的，所述i满足1≤i≤m-1，所述j满足0≤j≤m-2。
  6. 根据权利要求2至5任一项所述的方法，其特征在于，所述发送所述编码数据，包括：
    发送所述第m-1份缓存数据，
    再依次发送所述第i段编码数据，所述i满足1≤i≤m-1。
  7. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    对所述编码矩阵G进行初等列变换，变换后的编码矩阵
    Figure PCTCN2022110968-appb-100002
    根据变换后的编码矩阵G′对所述信息比特序列进行编码，得到编码数据。
  8. 根据权利要求2或7所述的方法，其特征在于，
    所述m个分段中的信息比特个数为k 0,k 1,...,k m-1，
    所述k 1小于所述k 0，且k 1≤...≤k m-1≤k 0。
  9. 根据权利要求8所述的方法，其特征在于，
    所述编码数据包括m段，
    其中，第0段编码数据为根据所述矩阵G N′对所述信息比特序列的第0个分段进行编码得到的；
    第i段编码数据为根据所述矩阵G N′对所述信息比特序列的第i个分段进行编码后，再与所述第0段编码数据进行异或处理，得到的。
  10. 一种数据处理方法，其特征在于，包括：
    接收编码数据，所述编码数据是根据编码矩阵G对信息比特序列进行编码得到的，
    所述编码矩阵
    Figure PCTCN2022110968-appb-100003
    所述编码矩阵G为大小为(m×2 n) ×(m×2 n)的矩阵，所述m和所述n为正整数，
    所述矩阵G N′为大小为2 n×2 n的Polar生成矩阵，
    所述矩阵O为大小为2 n×2 n的全零矩阵；
    对所述编码数据进行译码，得到译码数据。
  11. 根据权利要求10所述的方法，其特征在于，
    所述信息比特序列包括m个分段，每一个分段的Polar生成矩阵为G N′。
  12. 根据权利要求10或11所述的方法，其特征在于，所述对所述编码数据进行译码，得到译码数据，包括：
    获取第0段编码数据对应的标记数据和第1段编码数据对应的标记数据，
    将所述第0段编码数据对应的标记数据和所述第1段编码数据对应的标记数据进行F运算，得到F运算后的第1段编码数据对应的标记数据，
    对F运算后的第1段编码数据对应的标记数据进行Polar码译码，得到第1段编码数据对应的译码数据；
    根据所述第1段编码数据对应的标记数据和所述第1段编码数据对应的译码数据对所述第0段编码数据对应的标记数据进行增强。
  13. 根据权利要求12所述的方法，其特征在于，所述方法还包括：
    获取第q段编码数据对应的标记数据，所述q为2≤q≤m-1；
    将所述第q段编码数据对应的标记数据与增强后的第0段编码数据对应的标记数据进行F运算，得到F运算后的第q段编码数据对应的标记数据；
    对F运算后的第q段编码数据对应的标记数据进行Polar码译码，得到第q段编码数据对应的译码数据；
    根据所述第q段编码数据对应的标记数据和所述第q段编码数据对应的译码数据对所述增强后的第0段编码数据对应的标记数据进行增强。
  14. 一种数据处理方法，其特征在于，包括：
    获取信息比特序列，信息比特序列包括m个分段；
    采用每一个分段的Polar生成矩阵G N′对每一个分段进行处理，得到m份缓存数据，
    其中，矩阵G N′为大小为2 n×2 n的Polar生成矩阵；
    基于m份缓存数据，得到编码数据，
    发送所述编码数据，
    其中，编码数据包括m段，其中，第0段编码数据为第m-1份缓存数据，第i段编码数 据为将第j份缓存数据与第m-1份缓存数据进行异或处理得到的，所述i满足1≤i≤m-1，所述j满足0≤j≤m-2。
  15. 根据权利要求14所述的方法，其特征在于，
    所述m个分段中的信息比特个数为k 0,k 1,...,k m-1，
    所述k 0小于所述k m-1，且k 0≤k 1≤...≤k m-1。
  16. 根据权利要求15所述的方法，其特征在于，
    第i个分段的信息比特数量为k i，所述i满足0≤i≤m-1。
  17. 根据权利要求14至16任一项所述的方法，其特征在于，所述得到编码数据，包括：
    根据编码矩阵
    Figure PCTCN2022110968-appb-100004
    对信息比特序列进行编码，得到编码数据，
    所述G为大小为(m×2 n)×(m×2 n)的矩阵，所述m和所述n为正整数，
    所述矩阵G N′为大小为2 n×2 n的Polar生成矩阵，
    所述矩阵O为大小为2 n×2 n的全零矩阵。
  18. 一种数据处理方法，其特征在于，包括：
    获取信息比特序列，信息比特序列包括m个分段，
    采用每一个分段的Polar生成矩阵G N′对每一个分段进行处理，得到编码数据；
    发送所述编码数据；
    其中，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，
    所述编码数据包括m段，第0段编码数据为根据所述矩阵G N′对所述信息比特序列的第0个分段进行编码得到的；第i段编码数据为根据矩阵G N′对所述信息比特序列的第i个分段进行编码后，再与第0段编码数据进行异或处理，得到的。
  19. 根据权利要求18所述的方法，其特征在于，
    所述m个分段中的信息比特个数为k 0,k 1,...,k m-1，
    所述k 1小于所述k 0，且k 1≤...≤k m-1≤k 0。
  20. 根据权利要求18或19所述的方法，其特征在于，所述得到编码数据，包括：
    根据编码矩阵
    Figure PCTCN2022110968-appb-100005
    对信息比特序列进行编码，得到编码数据，
    所述G′为大小为(m×2 n)×(m×2 n)的矩阵，所述m和所述n为正整数，
    所述矩阵G N′为大小为2 n×2 n的Polar生成矩阵，
    所述矩阵O为大小为2 n×2 n的全零矩阵。
  21. 一种数据处理装置，其特征在于，包括用于执行如权利要求1至20中任一项所述的方法所采用的单元或模块。
  22. 一种通信设备，其特征在于，包括：存储器和处理器；
    所述存储器，用于存储指令；
    所述处理器，用于执行所述指令，使得如权利要求1至20中任一项所述的方法被执行。
  23. 一种通信系统，其特征在于，包括：
    发送端，用于执行如权利要求1至9或者14至17或者18至20中任一项所述的方法；
    接收端，用于执行如权利要求10至13中任一项所述的方法。
  24. 一种芯片，其特征在于，包括处理器和接口；
    所述处理器用于读取指令以执行权利要求1至20中任一项所述的方法。
  25. 一种通信装置，其特征在于，所述通信装置由输入输出接口和逻辑电路组成，所述输入输出接口用于输入或输出数据；所述逻辑电路按照如权利要求1至9或者14至17或者18至20中任一项所述的方法对数据进行处理，获取处理后的数据。
  26. 一种通信装置，其特征在于，所述通信装置由输入输出接口和逻辑电路组成，所述输入输出接口用于输入或输出数据；所述逻辑电路按照如权利要求10至13中任一项所述的方法对数据进行处理，获取处理后的数据。
  27. 一种计算机可读存储介质，其特征在于，包括程序或指令，当所述程序或指令在计算机上运行时，如权利要求1至20中任一项所述的方法被执行。
PCT/CN2022/110968 2022-08-08 2022-08-08 一种数据处理方法、装置及设备 Ceased WO2024031286A1 (zh)

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