WO2024045975A1 - 印刷电路板、电子设备及印刷电路板制备方法 - Google Patents

印刷电路板、电子设备及印刷电路板制备方法 Download PDF

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Publication number
WO2024045975A1
WO2024045975A1 PCT/CN2023/110088 CN2023110088W WO2024045975A1 WO 2024045975 A1 WO2024045975 A1 WO 2024045975A1 CN 2023110088 W CN2023110088 W CN 2023110088W WO 2024045975 A1 WO2024045975 A1 WO 2024045975A1
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WO
WIPO (PCT)
Prior art keywords
printed circuit
circuit board
layer structure
dielectric layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/110088
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English (en)
French (fr)
Other versions
WO2024045975A9 (zh
Inventor
谢剑
魏仲民
任晓瀛
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ZTE Corp
Original Assignee
ZTE Corp
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Filing date
Publication date
Application filed by ZTE Corp filed Critical ZTE Corp
Priority to EP23859010.3A priority Critical patent/EP4565011A4/en
Priority to US19/107,074 priority patent/US20260075714A1/en
Publication of WO2024045975A1 publication Critical patent/WO2024045975A1/zh
Anticipated expiration legal-status Critical
Publication of WO2024045975A9 publication Critical patent/WO2024045975A9/zh
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0047—Drilling of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09618—Via fence, i.e. one-dimensional array of vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0207—Partly drilling through substrate until a controlled depth, e.g. with end-point detection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Definitions

  • the present disclosure relates to the technical field of printed circuits, and specifically to printed circuit boards, electronic equipment and printed circuit board preparation methods.
  • PCB Print Circuit Board, printed circuit board 112Gbps rate products have begun to be commercialized, and 224Gbps rate products are under research.
  • SI Signal Integrity, signal integrity
  • Bandwidth printed circuit board
  • an embodiment of the present disclosure provides a printed circuit board, including a layer structure body, a transmission line for transmitting signals, and at least two metallized holes penetrating the layer structure body, the transmission line being located in the layer structure body. , and the two ends of the transmission line are connected to two The hole walls of the metallized holes are directly connected.
  • an embodiment of the present disclosure also provides an electronic device, including the printed circuit board as mentioned above.
  • embodiments of the present disclosure also provide a printed circuit board preparation method, which is used to prepare the printed circuit board as mentioned above, including: performing printed circuit board signal simulation, and determining the target area of the printed circuit board according to the simulation results,
  • the target area is an area where signal integrity performance parameters do not meet preset conditions; and a printed circuit board is prepared, and the metallized holes are located in the target area.
  • Figure 1 is a schematic cross-sectional structural diagram of a printed circuit board provided by an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of the connection between metalized holes and transmission lines provided by an embodiment of the present disclosure
  • Figure 3 is a top view of a printed circuit board provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic diagram comparing the insertion loss effect of a printed circuit board in the related art and a printed circuit board provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram comparing the return loss effects of a printed circuit board in the related art and a printed circuit board provided by an embodiment of the present disclosure.
  • Embodiments described herein may be described with reference to plan and/or cross-sectional illustrations, with the aid of idealized schematic illustrations of the present disclosure. Accordingly, example illustrations may be modified based on manufacturing techniques and/or tolerances. Therefore, the embodiments are not limited to those shown in the drawings but include modifications of configurations formed based on the manufacturing process. Accordingly, the regions illustrated in the drawings are of a schematic nature, and the shapes of the regions shown in the figures are illustrative of the specific shapes of the regions of the element, but are not limiting.
  • metallized holes are connected to transmission lines, and the transmission lines inside the PCB board are introduced into the outer layer of the PCB board through the metallized holes, thereby being connected to chip pins or connector pins to form a complete signal transmission path.
  • the signal transmission direction is: signal input end (can be chip end) ⁇ metallized hole ⁇ external pad ⁇ transmission line ⁇ via pad ⁇ metallized hole ⁇ signal output end.
  • the metallized holes and transmission lines are connected through via pads, which may affect impedance continuity and signal integrity, causing problems such as large signal loss.
  • Embodiments of the present disclosure provide a printed circuit board and a printed circuit board preparation method. By removing the via pad inside the PCB board, the metallized holes are directly connected to the transmission line, thereby achieving impedance continuity of signal transmission, thereby improving the signal Integrity.
  • Figure 1 is a schematic cross-sectional structural diagram of a printed circuit board provided by an embodiment of the present disclosure.
  • Figure 2 is a schematic diagram of the connection between a metallized hole and a transmission line provided by an embodiment of the present disclosure.
  • Figure 3 is a top view of a printed circuit board provided by an embodiment of the present disclosure.
  • a printed circuit board provided by an embodiment of the present disclosure includes a layer structure body, a transmission line 1 for transmitting signals, and at least two metallized holes 2 penetrating the layer structure body.
  • the transmission line 1 is located in the layer structure. Inside the body, the two ends of the transmission line 1 are directly connected to the hole walls of the two metallized holes 2 respectively.
  • the metallized holes 2 are located in the BGA (Ball Grid Array) area and/or the connector area of the layer structure body, and the metallized holes 2 are located in the BGA (Ball Grid Array) area and/or the connector area.
  • the spacing is equal.
  • Metalized hole 2 is formed by drilling The structure body is rotated at high speed to form a hole structure, and metal is formed on the hole structure through electroplating or chemical plating to obtain metallized hole 2.
  • the metal of metallized hole 2 is copper.
  • the transmission line 1 may be made of metallic copper, may be formed by etching a copper-containing core plate, or may be a copper circuit. It should be noted that the transmission line 1 and the metalized hole 2 are in a circuit loop.
  • the layer structure body can be a single-layer structure or a multi-layer structure.
  • a single-layer structure is a single-layer PCB board
  • a multi-layer structure is a multi-layer PCB board.
  • a multi-layer structure body is used as an example for explanation.
  • the printed circuit board is a multi-layer board.
  • the printed circuit board provided by the embodiment of the present disclosure includes a layer structure body, a transmission line 1 for transmitting signals, and at least two metallized holes 2 penetrating the layer structure body.
  • the transmission line 1 is located in the layer structure body, and both ends of the transmission line 1 They are directly connected to the hole walls of the two metallized holes 2 respectively; in the embodiment of the present disclosure, the via pad located inside the layer structure body is removed, and the transmission line 1 is directly connected to the hole walls of the metallized holes 2, which can reduce the impedance mismatch. properties as well as signal insertion loss and return loss, improving signal integrity.
  • the two ends of the transmission line 1 are respectively connected to the outer walls of the two metallized holes 2 through electroplating.
  • the connection position between the metallized hole 2 and the transmission line 1 that is, increasing the width of the transmission line 1 at this location ( (dimensions along the up and down direction in Figure 3), the increased width is determined based on process level capabilities. Therefore, in some embodiments, the width of both ends of the transmission line 1 is greater than the width of the portion of the transmission line 1 that is not connected to the two metallized holes 2 .
  • the printed circuit board also includes pads 3 , the number of pads 3 is the same as the number of metallized holes 2 , and the pads 3 are located on the first side of the layer structure body. On the surface, the pads 3 are electrically connected to the signal input end or the signal output end of the printed circuit board. Each pad 3 covers each metallized hole 2 and is connected to the hole wall of each metallized hole 2 respectively. The material of pad 3 is usually copper.
  • the printed circuit board is a multi-layer board.
  • the layer structure body includes a first layer structure 41 and at least one second layer structure 42, each second layer structure 42 and The first layer structure 41 is stacked, and the transmission line 1 is located in the first layer structure 41, the first layer structure 41 and the second layer structure 42 may be core boards.
  • a second layer structure 42 is taken as an example for description.
  • the second layer structure 42 is located on the side of the first layer structure 41 adjacent to the pad 3, and the first surface of the layer structure body is the second layer structure 42 away from the first layer structure 41 s surface.
  • the second layer structure 42 includes a stacked third dielectric layer 421 and a fourth dielectric layer 422 , and the fourth dielectric layer 422 is located on a side of the third dielectric layer 421 away from the pad 3 .
  • the first layer structure 41 includes a stacked first dielectric layer 411 and a second dielectric layer 412. The first dielectric layer 411 is located on a side of the second dielectric layer 412 adjacent to the pad 3.
  • the printed circuit board is a single-layer board.
  • the layer structure body includes a first layer structure
  • the first layer structure includes a first dielectric layer and a second dielectric layer that are stacked.
  • the first surface of the layer structure body is the surface of the first dielectric layer away from the second dielectric layer, and the transmission line is located in the second dielectric layer. That is to say, compared to a multi-layer printed circuit board, a single-layer printed circuit board lacks the second layer structure 42 and only has the first layer structure 41 .
  • the printed circuit board further includes a fifth dielectric layer 5 .
  • the fifth dielectric layer 5 is located on the side of the layer structure body away from the pad 3 .
  • the fifth dielectric layer 5 is provided with back drilling holes 6 penetrating through the fifth dielectric layer 5 at positions corresponding to each metallization hole 2 , and each back drilling hole 6 is connected to each metallization hole 2 .
  • each media layer is usually composed of resin, glass fiber, filler and other components.
  • the signal is transmitted through the metallized via-hole through-layer connection transmission line. If the metallized via-hole is input on the first layer of the four-layer printed circuit board and is output on the third layer of the printed circuit board through the metallized via-hole, then the metallized via is on The stub (i.e., hole copper) between the third and fourth layers of the printed circuit board causes signal loss.
  • the stub i.e., hole copper
  • the back drilling 6 can be used to remove excess hole copper of the metallized hole 2 on the side of the second dielectric layer 412 away from the pad 3, thereby reducing signal loss. consumption and improve signal transmission quality.
  • the disclosed embodiments only consider the signal integrity and designability from the perspective of pad design, and solve the problem of through-hole signal distortion that cannot be achieved with high performance in the existing technology.
  • An embodiment of the present disclosure also provides an electronic device, which includes the printed circuit board as mentioned above.
  • Embodiments of the present disclosure also provide a printed circuit board preparation method for preparing the printed circuit board as described above.
  • the printed circuit board preparation method includes the following steps S11 and S12.
  • Step S11 perform printed circuit board signal simulation, and determine the target area of the printed circuit board based on the simulation results.
  • the target area is the area where the signal integrity performance parameters do not meet the preset conditions. It should be noted that the target area is the BGA area of the printed circuit board. and/or part or all of the connector area.
  • the simulation results show that there are discontinuities in the metallized hole impedance, and the signal integrity performance parameters do not meet the preset condition area.
  • signal integrity performance parameters include insertion loss and/or return loss.
  • Step S12 Prepare a printed circuit board with metallized holes located in the target area.
  • EDA electronic design automation
  • the output is a light-painted file in a common format, usable with a suffix recognized by PCB manufacturers.
  • Inner core board graphics transfer production The inner core board is subjected to processes such as film pasting, exposure, and development to complete the transfer of the inner layer graphics and form the transmission line pattern on the inner core board.
  • the prepreg and the prepared inner core board are laminated to form a multi-layer PCB board.
  • Drill holes Mechanical drilling is performed according to normal design requirements, and the drilling tool diameter is the designed drilling diameter to obtain back drilling.
  • the target area with large signal loss is determined through signal simulation.
  • the via pad located inside the layer structure body is removed, and the connection between the transmission line 1 and the metalized hole 2 is The direct connection of the hole walls can reduce impedance mismatch, signal insertion loss and return loss, and improve signal integrity.
  • FIG. 4 is a schematic diagram comparing the insertion loss effects of a printed circuit board in the related art and a printed circuit board provided by an embodiment of the present disclosure.
  • FIG. 5 is an echo of a printed circuit board in the related art and a printed circuit board provided by an embodiment of the present disclosure. Comparison diagram of loss effect. The test experimental effects of the embodiments of the present disclosure will be described below with reference to Figures 4 and 5.
  • the thick solid line curve at the bottom of the figure is the signal insertion loss curve of the PCB board with 4 mil via pads in the related art
  • the thin solid line curve at the top is the PCB of the embodiment of the present disclosure.
  • the x-axis is the frequency and the y-axis is the insertion loss. It can be seen from Figure 4 that when the frequency is higher, the signal insertion loss curve of the PCB board according to the embodiment of the present disclosure is closer to 0, and the signal loss is smaller.
  • the light curve in the figure is the signal return loss curve of the PCB board with 4mil via pad in the related art
  • the dark curve is the signal return loss curve of the PCB board according to the embodiment of the present disclosure.
  • Wave loss curve, in Figure 5, the x-axis is frequency and the y-axis is return loss. As can be seen from Figure 5, when the frequency is higher, the signal return loss of the related art PCB board is closer to 0, and the signal loss is greater.
  • the printed circuit board of the embodiment of the present disclosure will not increase the complexity and difficulty of the printed circuit board preparation process, and can also improve the impedance matching, reduce the impedance mismatch factor at the input end and the output end, and greatly improve the signal integrity of the metallized hole. , reducing signal loss and solving the problem of taking into account the signal integrity and designability of metallized holes under high-speed transmission requirements.
  • the disclosed embodiments are suitable for high-rate printed circuit board design products, especially for wired products and wireless products with a rate of 224Gbps and above. They can be applied to printed circuit boards with a design rate of 224Gbps and above, or to printed circuit boards with a design rate that does not reach 224Gbps. , but requires a printed circuit board with low signal loss.
  • Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).
  • computer storage media includes volatile and nonvolatile media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. removable, removable and non-removable media.
  • Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disk (DVD) or other optical disk storage, magnetic cassettes, tapes, disk storage or other magnetic storage devices, or may Any other medium used to store the desired information and that can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules, or other means such as carrier waves or other transmissions. other data in a modulated data signal, such as a transmission mechanism, and may include any information delivery medium.
  • Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a general illustrative sense only and not for purpose of limitation. In some instances, it will be apparent to those skilled in the art that, unless expressly stated otherwise, features, characteristics, and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and/or elements described in other embodiments. /or used in combination of components. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the present disclosure as set forth in the appended claims.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Structure Of Printed Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

一种电子设备、印刷电路板和一种印刷电路板制备方法，印刷电路板包括层结构本体、用于传输信号的传输线（1）和至少两个贯穿层结构本体的金属化孔（2），传输线（1）位于层结构本体内，且传输线（1）的两端分别与两个金属化孔（2）的孔壁直接连接。

Description

印刷电路板、电子设备及印刷电路板制备方法
相关申请的交叉引用
本申请要求于2022年8月29日提交的中国专利申请NO.202211038535.9的优先权，该中国专利申请的内容通过引用的方式整体合并于此。
技术领域
本公开涉及印刷电路技术领域，具体涉及印刷电路板、电子设备及印刷电路板制备方法。
背景技术
PCB(Printed Circuit Board，印刷电路板)的112Gbps速率产品已开始商用化，224Gbps速率产品正在研究，遇到了较大的技术难题是：如何提升系统的SI(Signal Integrity，信号完整性)性能及提高带宽，印刷电路板作为系统中的重要组成部分，很大程度上决定了系统性能。
如何降低印刷电路板的无源损耗是当前印刷电路板技术领域的研究热点，金属化孔属于无源通道重要的一部分。目前，在相关技术中，金属化孔与传输线连接，通过金属化孔将PCB板内部的传输线引入外层，从而与芯片引脚或连接器引脚等相连，形成完整的信号传输路径。相关技术中的PCB板信号传输完整性较差，存在信号损耗大等问题。
公开内容
一方面，本公开实施例提供一种印刷电路板，包括层结构本体、用于传输信号的传输线和至少两个贯穿所述层结构本体的金属化孔，所述传输线位于所述层结构本体内，且所述传输线的两端分别与两个 所述金属化孔的孔壁直接连接。
又一方面，本公开实施例还提供一种电子设备，包括如前所述的印刷电路板。
又一方面，本公开实施例还提供一种印刷电路板制备方法，用于制备如前所述的印刷电路板，包括：进行印刷电路板信号仿真，根据仿真结果确定印刷电路板的目标区域，所述目标区域为信号完整性能参数不符合预设条件的区域；以及制备印刷电路板，所述金属化孔位于所述目标区域。
附图说明
图1为本公开实施例提供的印刷电路板的剖面结构示意图；
图2为本公开实施例提供的金属化孔与传输线的连接示意图；
图3为本公开实施例提供的印刷电路板的俯视图；
图4为相关技术中的印刷电路板与本公开实施例提供的印刷电路板的插入损耗效果对比示意图；以及
图5为相关技术中的印刷电路板与本公开实施例提供的印刷电路板的回波损耗效果对比示意图。
具体实施方式
在下文中将参考附图更充分地描述示例实施例，但是所述示例实施例可以以不同形式来体现，且本公开不应当被解释为限于本文阐述的实施例。提供这些实施例的目的在于使本公开更加透彻和完整，并使本领域技术人员充分理解本公开的范围。
如本文所使用的，术语“和/或”包括一个或多个相关列举条目的任何和所有组合。
本文所使用的术语仅用于描述特定实施例，且不限制本公开。如本文所使用的，单数形式“一个”和“该”也包括复数形式，除非上下文另外清楚指出。还将理解的是，当本说明书中使用术语“包括”和/或“由……制成”时，指定存在特定特征、整体、步骤、操作、元件和/或组件，但不排除存在或可添加一个或多个其他特征、整体、 步骤、操作、元件、组件和/或其群组。
本文所述实施例可借助本公开的理想示意图而参考平面图和/或截面图进行描述。因此，可根据制造技术和/或容限来修改示例图示。因此，实施例不限于附图中所示的实施例，而是包括基于制造工艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了元件的区的具体形状，但并不是限制性的。
除非另外限定，否则本文所用的所有术语(包括技术术语和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本文明确如此限定。
在相关技术中，金属化孔与传输线连接，通过金属化孔将PCB板内部的传输线引入PCB板的外层，从而与芯片引脚或连接器引脚等相连，形成完整的信号传输路径。信号传输方向为：信号输入端(可以是芯片端)→金属化孔→外部焊盘→传输线→过孔焊盘→金属化孔→信号输出端。该金属化孔与传输线连接方案中，金属化孔与传输线之间通过过孔焊盘相连，可能会影响阻抗连续性和信号完整性，造成信号损耗大等问题。
本公开实施例提供一种印刷电路板及一种印刷电路板制备方法，通过去除PCB板内部的过孔焊盘，使金属化孔与传输线直接相连，实现信号传输的阻抗连续性，从而提高信号完整性。
图1为本公开实施例提供的印刷电路板的剖面结构示意图，图2为本公开实施例提供的金属化孔与传输线的连接示意图，图3为本公开实施例提供的印刷电路板的俯视图，结合图1至图3所示，本公开实施例提供的印刷电路板，包括层结构本体、用于传输信号的传输线1和至少两个贯穿层结构本体的金属化孔2，传输线1位于层结构本体内，且传输线1的两端分别与两个金属化孔2的孔壁直接连接。
在本公开实施例提供的印刷电路板中，金属化孔2位于层结构本体的BGA(Ball Grid Array，球状引脚栅格阵列)区域和/或连接器区域，各个金属化孔2之间的间距相等。金属化孔2由钻刀在层结 构本体上高速旋转形成孔结构，并经过电镀或化学镀方式在孔结构上形成金属从而得到金属化孔2，一般金属化孔2的金属为铜。传输线1可以由金属铜制备形成，可以利用含铜芯板蚀刻形成，也可以是铜线路。需要说明的是，传输线1与金属化孔2在一个电路回路中。
层结构本体可以是单层结构，也可以是多层结构，单层结构即为单层PCB板，多层结构即为多层PCB板。在本公开实施例提供的印刷电路板中，如图1所示，以多层结构的层结构本体为例进行说明，该印刷电路板为多层板。
本公开实施例提供的印刷电路板，包括层结构本体、用于传输信号的传输线1和至少两个贯穿层结构本体的金属化孔2，传输线1位于层结构本体内，且传输线1的两端分别与两个金属化孔2的孔壁直接连接；本公开实施例去除了位于层结构本体内部的过孔焊盘，传输线1与金属化孔2的孔壁直接连接，可以减少阻抗的不匹配性以及信号的插入损耗和回波损耗，提高信号完整性。
在一些实施方式中，传输线1的两端分别与两个金属化孔2的外壁通过电镀方式连接。
为了防止在电镀过程中出现金属化孔2位置的化学反应速度快于其它位置导致的断裂问题，可以对金属化孔2与传输线1的连接位置进行额外补偿，即增加该位置传输线1的宽度(沿图3中上下方向的尺寸)，增加的宽度大小依据工艺水平能力决定。因此，在一些实施方式中，传输线1两端的宽度大于传输线1未与两个金属化孔2相连接部分的宽度。
在一些实施方式中，结合图1和图2所示，所述印刷电路板还包括焊盘3，焊盘3的数量与金属化孔2的数量相同，焊盘3位于层结构本体的第一表面，焊盘3与印刷电路板的信号输入端或信号输出端电连接，每个焊盘3分别覆盖每个金属化孔2，并分别与每个金属化孔2的孔壁连接。焊盘3的材料通常为铜材料。
在一些实施方式中，所述印刷电路板为多层板，相应的，如图1所示，层结构本体包括第一层结构41和至少一个第二层结构42，各第二层结构42与第一层结构41层叠设置，传输线1位于第一层结构 41内，第一层结构41和第二层结构42可以是芯板。在本公开实施例提供的印刷电路板中，以一个第二层结构42为例进行说明。在图1所示的印刷电路板中，第二层结构42位于第一层结构41邻近焊盘3的一侧，层结构本体的第一表面即为第二层结构42远离第一层结构41的表面。
在一些实施方式中，第二层结构42包括层叠设置的第三介质层421和第四介质层422，第四介质层422位于第三介质层421远离焊盘3的一侧。第一层结构41包括层叠设置的第一介质层411和第二介质层412，第一介质层411位于第二介质层412邻近焊盘3的一侧。
在一些实施方式中，所述印刷电路板为单层板，相应的，层结构本体包括第一层结构，第一层结构包括层叠设置的第一介质层和第二介质层，在这种情况下，层结构本体的第一表面为第一介质层远离第二介质层的表面，传输线位于第二介质层内。也就是说，单层板的印刷电路板相对于多层板的印刷电路板，缺少第二层结构42，只有第一层结构41。
在一些实施方式中，如图1所示，所述印刷电路板还包括第五介质层5，第五介质层5位于层结构本体远离焊盘3的一侧。第五介质层5与各金属化孔2对应的位置设置有贯穿第五介质层5的背钻孔6，各背钻孔6与各金属化孔2连通。
在一些实施方式中，各介质层通常由树脂、玻璃纤维、填料等成分组成。
信号传输线在同一线宽、同一平面布线，其阻抗不会发生变化，这就能保证信号无差别地传输，减少信号反射，最大限度的保证信号质量。但是传输线穿层传输之后阻抗就会发生变化，反射加大，信号损耗增加，传输的信号质量变差。信号经过金属化过孔穿层连接传输线进行传输，如果金属化过孔在四层印刷电路板的第一层输入，经过金属化过孔在印刷电路板的第三层输出，那么金属化孔在印刷电路板的第三层和第四层之间的残端(即孔铜)导致信号发生损耗。因此，在本公开实施例提供的印刷电路板中，利用背钻孔6可以去除金属化孔2在第二介质层412远离焊盘3一侧多余的孔铜，从而降低信号损 耗，提升信号传输质量。
本公开实施例仅从焊盘的设计角度出发，实现了兼顾信号完整性和可设计加工性，解决了现有技术无法实现高性能的过孔信号失真问题。
本公开实施例还提供一种电子设备，所述电子设备包括如前所述的印刷电路板。
本公开实施例还提供一种印刷电路板制备方法，用于制备如前所述的印刷电路板，所述印刷电路板制备方法包括以下步骤S11和S12。
步骤S11，进行印刷电路板信号仿真，根据仿真结果确定印刷电路板的目标区域，目标区域为信号完整性能参数不符合预设条件的区域，需要说明的是，目标区域为印刷电路板的BGA区域和/或连接器区域的部分或全部。
在本步骤中，根据设计要求，对印刷电路板进行信号仿真，定位信号损耗较大的目标区域，例如，仿真结果显示的金属化孔阻抗存在不连续点、且信号完整性能参数不符合预设条件的区域。
在一些实施方式中，信号完整性能参数包括插入损耗和/或回波损耗。
步骤S12，制备印刷电路板，金属化孔位于目标区域。
需要说明的是，针对目标区域，可以先采用减小金属化孔的孔径、调整传输线的线宽等方式降低信号损耗，在上述方式不起作用的情况下，再去除位于层结构本体内部的过孔焊盘，将传输线1与金属化孔2的孔壁直接连接。
在制备印刷电路板过程中，先制作光绘GERBER资料，使用电子设计自动化(EDA)软件进行设计。
1、制作网络布局图。按照设计原理图，对各个电子元器件进行布局。
2、进行网络连线。使用连线方式把各个元器件连接起来，形成整个网络结构图。
3、制作无焊盘资料。在设置金属化孔的BGA区域和/或连接器 区域，进行过孔焊盘优化，删除过孔焊盘或将过孔焊盘的大小调整为金属化孔的孔径。
4、输出光绘文件。输出为通用格式的光绘文件，可用于印刷电路板制造商可识别的后缀。
在完成光绘GERBER资料后，制备无过孔焊盘的印刷电路板。
1、在PCB设计资料中，找到无焊盘的信号孔。
2、内层芯板图形转移制作。对内层芯板进行贴膜、曝光、显影等流程，完成内层图形转移，在内层芯板上形成传输线的图形。
3、压合。把半固化片和制作好的内层芯板进行叠合层压，形成多层PCB板。
4、钻孔。按照正常设计要求进行机械钻孔，钻孔刀径为设计钻孔孔径，得到背钻孔。
本公开实施例的印刷电路板制备方法，通过信号仿真确定出信号损耗较大的目标区域，在目标区域内，去除位于层结构本体内部的过孔焊盘，将传输线1与金属化孔2的孔壁直接连接，可以减少阻抗的不匹配性以及信号的插入损耗和回波损耗，提高信号完整性。
需要说明的是，也可以不针对目标区域去除位于层结构本体内部的焊盘，而是整个印刷电路板均不再设置位于层结构本体内部的过孔焊盘，实现整个印刷电路板整体无过孔焊盘的设计。图4为相关技术中的印刷电路板与本公开实施例提供的印刷电路板的插入损耗效果对比示意图，图5为相关技术中的印刷电路板与本公开实施例提供的印刷电路板的回波损耗效果对比示意图。以下结合图4和图5对本公开实施例的测试实验效果进行说明。
如图4所示，图中下方的粗实线曲线为相关技术中4密尔(mil)过孔焊盘的PCB板的信号插入损耗曲线，上方的细实线曲线为本公开实施例的PCB板的信号插入损耗曲线，图4中x轴为频率，y轴为插入损耗。从图4中可以看出，当频率较高时，本公开实施例的PCB板的信号插入损耗曲线更接近0，信号损耗更小。
如图5所示，图中浅色曲线为相关技术中4mil过孔焊盘的PCB板的信号回波损耗曲线，深色曲线为本公开实施例的PCB板的信号回 波损耗曲线，图5中x轴为频率，y轴为回波损耗。从图5中可以看出，当频率较高时，相关技术的PCB板的信号回波损耗更接近0，信号损耗更大。
本公开实施例的印刷电路板，不会增加印刷电路板制备工艺的复杂度和难度，还可以提高阻抗匹配性，使输入端和输出端减少阻抗不匹配因子，大幅提升金属化孔信号完整性，降低信号损耗，解决了高速率传输要求下，兼顾金属化孔的信号完整性和可设计加工性的问题。
本公开实施例适用于高速率的印刷电路板设计产品，尤其适合224Gbps速率及以上的有线产品和无线产品，可以应用于设计速率达到224Gbps及以上的印刷电路板，或者应用于设计速率未达到224Gbps、但要求信号损耗低的印刷电路板。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些物理组件或所有物理组件可以被实施为由处理器(如中央处理器、数字信号处理器或微处理器)执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传 输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
本文已经公开了示例实施例，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则与特定实施例相描述的特征、特性和/或元素可单独使用，或可与结合其他实施例描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离由所附的权利要求阐明的本公开的范围的情况下，可进行各种形式和细节上的改变。

Claims (10)

  1. 一种印刷电路板，包括层结构本体、用于传输信号的传输线和至少两个贯穿所述层结构本体的金属化孔，所述传输线位于所述层结构本体内，且所述传输线的两端分别与两个所述金属化孔的孔壁直接连接。
  2. 如权利要求1所述的印刷电路板，其中，所述传输线的两端分别与两个所述金属化孔的外壁通过电镀方式连接。
  3. 如权利要求1所述的印刷电路板，还包括与所述金属化孔的数量相同的焊盘，所述焊盘位于所述层结构本体的第一表面，所述焊盘与所述印刷电路板的信号输入端或信号输出端电连接，各所述焊盘分别覆盖各所述金属化孔，并分别与各所述金属化孔的孔壁连接。
  4. 如权利要求3所述的印刷电路板，其中，所述层结构本体包括第一层结构，所述第一层结构包括层叠设置的第一介质层和第二介质层，所述第一表面为所述第一介质层远离所述第二介质层的表面，所述传输线位于所述第二介质层内。
  5. 如权利要求3所述的印刷电路板，其中，所述层结构本体包括第一层结构和至少一个第二层结构，各所述第二层结构与所述第一层结构层叠设置，所述第一表面为所述第二层结构远离所述第一层结构的表面，所述传输线位于所述第一层结构内。
  6. 如权利要求5所述的印刷电路板，其中，所述第二层结构包括层叠设置的第三介质层和第四介质层，所述第四介质层位于所述第三介质层远离所述焊盘的一侧；
    所述第一层结构包括层叠设置的第一介质层和第二介质层，所述第一介质层位于所述第二介质层邻近所述焊盘的一侧。
  7. 如权利要求4或5所述的印刷电路板，还包括第五介质层，所述第五介质层位于所述层结构本体远离所述焊盘的一侧；
    所述第五介质层与各所述金属化孔对应的位置设置有贯穿所述第五介质层的背钻孔，各所述背钻孔与各所述金属化孔连通。
  8. 一种电子设备，包括如权利要求1至7中任一项所述的印刷电路板。
  9. 一种印刷电路板制备方法，用于制备如权利要求1至7中任一项所述的印刷电路板，包括：
    进行印刷电路板信号仿真，根据仿真结果确定印刷电路板的目标区域，所述目标区域为信号完整性能参数不符合预设条件的区域；以及
    制备印刷电路板，其中，所述金属化孔位于所述目标区域。
  10. 如权利要求9所述的方法，其中，所述信号完整性能参数包括插入损耗或回波损耗中的至少一者。
PCT/CN2023/110088 2022-08-29 2023-07-31 印刷电路板、电子设备及印刷电路板制备方法 Ceased WO2024045975A1 (zh)

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