WO2024046047A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2024046047A1
WO2024046047A1 PCT/CN2023/111616 CN2023111616W WO2024046047A1 WO 2024046047 A1 WO2024046047 A1 WO 2024046047A1 CN 2023111616 W CN2023111616 W CN 2023111616W WO 2024046047 A1 WO2024046047 A1 WO 2024046047A1
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WO
WIPO (PCT)
Prior art keywords
line
pixel driving
transfer line
display area
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/111616
Other languages
English (en)
French (fr)
Inventor
李德
李正坤
龙跃
张波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to JP2024544803A priority Critical patent/JP2025527384A/ja
Priority to EP23859082.2A priority patent/EP4465360A4/en
Priority to KR1020247025195A priority patent/KR20250054024A/ko
Publication of WO2024046047A1 publication Critical patent/WO2024046047A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/57—Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • the under-screen camera design is to set up a transparent display area in the display area of the display panel.
  • This transparent display area can be displayed and may allow light to pass through; the transparent display area of the display panel is equipped with cameras and other photosensitive devices, so as to achieve a better It has a large screen-to-body ratio and can also realize functions such as camera and face recognition.
  • the display substrate includes a substrate substrate, a plurality of pixel drive circuits, a plurality of data lines and a plurality of anode connection lines; the substrate substrate includes a transparent display area and a normal display area surrounding the transparent display area; the multiple pixel drive circuits are located in the normal display area.
  • the area is arranged in an array along the first direction and the second direction to form a plurality of pixel driving rows and a plurality of pixel driving columns, each pixel driving row extends along the first direction, and each pixel driving column extends along the second direction; a plurality of data lines Extending along the second direction and configured to provide data signals to a plurality of pixel driving columns;
  • the normal display area includes a first light-emitting element
  • the transparent display area includes a second light-emitting element
  • the plurality of pixel driving columns includes a plurality of first pixel driving columns and a plurality of second pixel driving columns, the pixel driving circuits in the first pixel driving columns are connected to the first light-emitting elements, and part of the pixel driving circuits in the second pixel driving columns are connected to the second light-emitting elements through a plurality of anode connection lines
  • the display substrate also includes a first transfer line and a second transfer line.
  • the first transfer line extends along the first direction
  • the second transfer line extends along the second direction.
  • the first transfer line and the second transfer line are arranged in different layers.
  • the wiring and the second adapter wire are connected to the cathode of the first light-emitting element and are configured to transmit the first power supply voltage; the first adapter wire and the second adapter wire are connected through the first via hole connection structure.
  • the orthographic projection of the first via hole connection structure on the base substrate does not overlap with the orthographic projection of the plurality of anode connection lines on the base substrate.
  • the display substrate can reduce the load of the signal line used to transmit the first power supply voltage on the premise of realizing the design of the under-screen camera, thereby improving the display quality.
  • the display substrate can also reduce the risk of disconnection of the anode connection line.
  • At least one embodiment of the present disclosure provides a display substrate, which includes: a substrate substrate including a transparent display area and a normal display area surrounding the transparent display area; a plurality of pixel driving circuits located in the normal display area and along a first One direction and a second direction array are arranged to form a plurality of pixel driving rows and a plurality of pixel driving columns, each of the pixel driving rows extending along the first direction, and each of the pixel driving columns extending along the second direction; a plurality of data lines extending along the second direction and configured to provide data signals to the plurality of pixel driving columns; a plurality of anode connection lines, the normal display area including a first light-emitting element, and the transparent display area including a second light emitting element, the plurality of pixel driving columns including a plurality of first pixel driving columns and a plurality of second pixel driving columns, the pixel driving circuit in the first pixel driving column and the first light emitting
  • the elements are connected, and part of the pixel driving
  • the first transfer line extends along the first direction
  • the second transfer line extends along the second direction
  • the first transfer line and the second transfer line are arranged in different layers
  • the adapter wire and the second adapter wire are connected to the cathode of the first light-emitting element and are configured to transmit the first power supply voltage;
  • the first adapter wire and the second adapter wire are connected through a first via hole connection structure,
  • the orthographic projection of the first via hole connection structure on the base substrate does not overlap with the orthographic projection of the plurality of anode connection lines on the base substrate.
  • the display substrate further includes a third transfer line and a fourth transfer line, and the third transfer line and the fourth transfer line are located in the normal display area,
  • the third adapter cable extends along the first direction
  • the fourth adapter cable extends along the second direction
  • one end of the third adapter cable is connected to the data line
  • the third adapter cable extends along the second direction. The other end is connected to the fourth adapter cable.
  • the third transfer line and the first transfer line are arranged on the same layer.
  • the fourth transfer line and the second transfer line are arranged on the same layer.
  • the display substrate further includes: a connecting line segment, which is arranged on the same layer as the third connecting line and is insulated from each other.
  • the connecting line segment and the third connecting line are insulated from each other. They all overlap with virtual straight lines extending along the first direction, and the connecting line segments connect a plurality of second transfer lines arranged along the first direction.
  • the second transfer line and the fourth transfer line are both connected to a virtual straight line extending along the second direction. Overlapping and insulated from each other.
  • the normal display area includes a first sub-display area and a second sub-display area arranged in the first direction, located in the first sub-display area.
  • the data line at the edge is connected to the fourth adapter line located at the first sub-display area through the third adapter line, and the data line located at the edge of the second sub-display area is connected through the third adapter line.
  • the third switch wire is connected to the fourth switch wire located in the second sub-display area.
  • two first pixel driving columns are provided between two adjacent second pixel driving columns.
  • the plurality of data lines include a first data line and a second data line
  • the first data line is connected to the first pixel driving column and in the The transparent display area is disconnected and forms a first sub-data line segment and a second sub-data line segment.
  • the second data line is connected to the second pixel driving column and includes a third sub-data line segment and a fourth sub-data line segment.
  • the orthographic projection of the third sub-data line segment on the reference straight line extending in the second direction covers the orthographic projection of the transparent display area on the reference straight line.
  • the display substrate also includes a fifth transfer line and a sixth transfer line.
  • the fifth transfer line is located on the first side of the transparent display area in the second direction
  • the sixth transfer line is located on the second side of the transparent display area in the second direction
  • the first sub-data line is connected to the third sub-data line segment through the fifth adapter line
  • the second sub-data line is connected to the third sub-data line segment through the sixth adapter line.
  • the fifth transfer line and the sixth transfer line are arranged on the same layer as the first transfer line.
  • the fourth sub-data line segment is connected to the first transfer line through a second via hole connection structure.
  • the substrate substrate further includes a peripheral area surrounding the normal display area, and the fifth transfer line is located in the peripheral area.
  • the display substrate further includes: a plurality of power supply lines extending along the second direction and configured to provide a second power supply voltage to the plurality of pixel driving columns; and a first conductive structure arranged on the same layer as the plurality of power lines, where the first conductive structure
  • the orthographic projection on the base substrate overlaps the orthographic projection of the pixel driving circuit in the second pixel driving column that is not connected to the anode connection line on the base substrate, and the first conductive structure and The first transfer wire is connected through a third via hole connection structure.
  • each of the pixel driving circuits includes a second conductive structure, which is arranged on the same layer as the first transfer line; the anode is not connected to the second pixel driving column.
  • the second conductive structure in the pixel driving circuit of the connection line is connected to the second transfer line through a fourth via hole connection structure.
  • the substrate substrate further includes a peripheral area surrounding the normal display area, the display substrate further includes a power supply voltage line located in the peripheral area, and the power supply The voltage line is configured to transmit a first power supply voltage; at least one of the first transfer line and the second transfer line extends to the peripheral area and is electrically connected to the power supply voltage line.
  • At least one embodiment of the present disclosure also provides a display device, which includes any of the above display substrates.
  • Figure 1 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of the connection between a first transfer line and a second transfer line in a display substrate according to an embodiment of the present disclosure
  • Figure 3 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic diagram of a stacking of a display substrate according to an embodiment of the present disclosure.
  • FIG. 7A is a schematic diagram of the stacking of another display substrate according to an embodiment of the present disclosure.
  • FIG. 7B is a schematic diagram of another display substrate stacking according to an embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of a display device provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic diagram of a stacking of a display substrate according to an embodiment of the present disclosure.
  • FIG. 10 is an equivalent schematic diagram of a pixel driving circuit in a display substrate according to an embodiment of the present disclosure.
  • 11-16 are schematic diagrams of multiple film layers in a display substrate according to an embodiment of the present disclosure.
  • a pixel unit includes a pixel driving circuit and a light-emitting element connected to the pixel driving circuit, and the pixel driving circuit is usually opaque. Therefore, in the design of under-screen cameras, the transparent display area of the display substrate can achieve a transparent display function by removing the pixel driving circuit and retaining the light-emitting elements, that is, it can display and allow light to pass through. In this technical solution, the pixel driving circuit corresponding to the light-emitting element in the transparent display area needs to be arranged in the normal display area outside the transparent display area.
  • the display area of a typical display substrate includes a plurality of signal lines for driving pixel units in the display substrate to perform light-emitting display, and these signal lines require external driving circuits or driving chips for driving. Therefore, the display substrate also includes a lead area and a binding area located in the peripheral area.
  • the lead area includes multiple leads, and the binding area is used for binding with external drive circuits or drive chips; at this time, multiple leads can be connected with multiple
  • the signal lines are connected and extended to the binding area to be bound to the external driver circuit or driver chip.
  • the leads of signal lines such as data lines can be arranged in the display area to reduce the size of the lead area (Fan-out area) to achieve a narrow bezel design.
  • the display substrate includes a substrate substrate, a plurality of pixel drive circuits, a plurality of data lines and a plurality of anode connection lines; the substrate substrate includes a transparent display area and a normal display area surrounding the transparent display area; the multiple pixel drive circuits are located in the normal display area.
  • the area is arranged in an array along the first direction and the second direction to form a plurality of pixel driving rows and a plurality of pixel driving columns, each pixel driving row extends along the first direction, and each pixel driving column extends along the second direction; a plurality of data lines Extending along the second direction and configured to provide data signals to a plurality of pixel driving columns;
  • the normal display area includes a first light-emitting element
  • the transparent display area includes a second light-emitting element
  • the plurality of pixel driving columns includes a plurality of first pixel driving columns and a plurality of second pixel driving columns, the pixel driving circuits in the first pixel driving columns are connected to the first light-emitting elements, and part of the pixel driving circuits in the second pixel driving columns are connected to the second light-emitting elements through a plurality of anode connection lines
  • the display substrate also includes a first transfer line and a second transfer line.
  • the first transfer line extends along the first direction, and the second transfer line extends along the second direction.
  • the first transfer line and the second transfer line are arranged in different layers.
  • the wiring and the second transfer wire are connected to the cathode of the first light-emitting element and are configured to transmit the first power supply voltage; the first transfer wire and the second transfer wire are connected through a first via-hole connection structure, and the first via-hole connection structure is at
  • the orthographic projection on the base substrate does not overlap with the orthographic projections of the plurality of anode connection lines on the base substrate.
  • the display substrate can reduce the load of the signal line used to transmit the first power supply voltage on the premise of realizing the design of the under-screen camera, thereby improving the display quality.
  • the display substrate can also reduce the risk of disconnection of the anode connection line.
  • FIG. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • the display substrate 100 includes a base substrate 110 , a plurality of pixel driving circuits 120 , a plurality of data lines 130 and a plurality of anode connection lines 140 ;
  • the base substrate 110 includes a transparent display area 112 and a surrounding transparent display area.
  • the normal display area 114 of 112; the transparent display area 112 and the normal display area 114 may constitute a display area for luminous display.
  • a plurality of pixel driving circuits 120 are located in the normal display area 114 and are arranged in an array along the first direction Extending, each pixel driving column 220 extends along the second direction Y; the plurality of data lines 130 extends along the second direction Y and is configured to provide data signals to the plurality of pixel driving columns 220 .
  • the normal display area 114 includes a first light-emitting element 151
  • the transparent display area 112 includes a second light-emitting element 152
  • the plurality of pixel driving columns 220 includes a plurality of first pixel driving columns 220A and a plurality of second pixel driving columns.
  • Column 220B; the pixel driving circuit 120 in the first pixel driving column 220A and the A light-emitting element 151 is connected, for example, the first light-emitting element 151 and the pixel driving circuit 120 are overlapped and directly connected through a via connection structure; some of the pixel driving circuits 120 in the second pixel driving column 220B are connected through a plurality of anode connection lines.
  • FIG. 1 only shows one first light-emitting element and two second light-emitting elements; embodiments of the present disclosure include but Not limited to this, each pixel driving circuit in the first pixel driving column can be provided with a corresponding first light-emitting element, and the transparent display area can be provided with multiple second light-emitting elements according to required parameters such as brightness, resolution, transmittance, etc. .
  • the display substrate 100 further includes a first transfer line 171 and a second transfer line 172 .
  • the first transfer line 171 extends along the first direction X
  • the second transfer line 172 extends along the second direction Y.
  • the first transfer line 171 extends along the second direction Y.
  • the wiring 171 and the second switching wire 172 are arranged in different layers.
  • the first switching wire 171 and the second switching wire 172 are connected to the cathode of the first light-emitting element 151 and are configured to transmit a first power supply voltage, such as a VSS voltage;
  • the wiring 171 and the second transfer line 172 are connected through the first via hole connection structure V1.
  • the orthographic projection of the first via hole connection structure V1 on the base substrate 110 and the orthogonal projection of the plurality of anode connection lines 140 on the base substrate 110 No overlap.
  • the orthographic projection of the first via hole connection structure V1 on the base substrate 110 does not overlap with the orthographic projection of the plurality of anode connection lines 140 on the base substrate 110 .
  • the display substrate since the display substrate includes a transparent display area, the transparent display area can be correspondingly provided with photosensitive devices such as cameras, so that the display substrate can realize an under-screen camera (Full Display with Camera, FDC) design. .
  • the display substrate since the first transfer line and the second transfer line for transmitting the first power supply voltage are connected through the first via hole connection structure, the display substrate can reduce the load of the first transfer line and the second transfer line, so that the entire display The uniformity of the first power voltage signal on the substrate is relatively high, thereby improving display quality.
  • the display substrate can also avoid the first through hole connection structure
  • the formed concave structure causes the risk of disconnection of the anode connecting wire.
  • the base substrate 110 may be made of transparent materials such as glass, plastic, quartz, or silicon-based semiconductor materials.
  • the embodiments of the present disclosure include but are not limited to this, and the material of the substrate may also be other suitable materials.
  • Figure 2 shows the connection between the first transfer line and the second transfer line in a display substrate according to an embodiment of the present disclosure.
  • Connection diagram As shown in Figure 2, an insulating flat layer 180 is provided between the first transfer wire 171 and the second transfer wire 172; at this time, the first via connection structure V1 includes a first via H1 located in the flat layer 180, The first via hole H1 exposes part of the first transfer wire 171; a part of the second transfer wire 172 is located in the first via hole H1 and connected to the first transfer wire 171.
  • an insulating layer 191 is also provided on the side of the second transfer line 172 away from the flat layer 180 ; due to the existence of the first via connection structure V1 , the position of the insulating layer 191 corresponding to the first via connection structure V1 will be different. If a recessed structure is formed and the anode connection line overlaps with the first via hole connection structure, the risk of the anode connection line being disconnected at the location of the recessed structure will easily occur, thus making it impossible for the second element located in the transparent display area to emit light. .
  • the display substrate since the orthographic projection of the first via hole connection structure on the substrate does not overlap with the orthographic projection of the plurality of anode connection lines on the substrate, the display substrate can also be used The risk of disconnection of the anode connection line caused by the recessed structure formed by the first via connection structure is avoided, and the product yield is improved.
  • the flat layer 180 may include one of an organic flat layer and an inorganic flat layer or a stack thereof; the material of the organic flat layer may be at least one of polyimide, resin, and acrylic; the material of the inorganic flat layer may be It is at least one of silicon oxide, silicon nitride or silicon oxynitride.
  • the material of the passivation layer may be at least one of silicon oxide, silicon nitride or silicon oxynitride.
  • the embodiments of the present disclosure include but are not limited to this, and the flat layer can also be made of other materials.
  • the material of the insulating layer 191 may be one or more of silicon oxide, silicon nitride, and silicon oxynitride.
  • the material of the gate insulating layer can also be other materials.
  • the substrate substrate 110 further includes a peripheral area 118 surrounding the normal display area 114 ; the display substrate 100 further includes a power supply voltage line 260 located in the peripheral area 118 , the power supply voltage line 260 being configured to The first supply voltage is transmitted. At least one of the first transfer line 171 and the second transfer line 172 extends to the peripheral area 118 and is electrically connected to the power supply voltage line 260 .
  • a plurality of first transfer lines 171 and a plurality of second transfer lines 172 can form a grid structure through a plurality of first via connection structures V1 , thereby further reducing the load and improving the overall display.
  • the uniformity of the first power supply voltage on the substrate thereby improves display quality.
  • the display substrate 100 further includes a third transfer line 173 and a fourth transfer line 174 ; both the third transfer line 173 and the fourth transfer line 174 are located in the normal display area 114 ;
  • the wiring 173 extends along the first direction X, and the fourth switching wire 174 extends along the second direction Y; one end of the third switching wire 173 is connected to the data line 130 , and the other end of the third switching wire 173 is connected to the fourth switching wire 174 . Therefore, the display substrate can arrange the leads of the data lines in the normal display area to reduce the number of leads. area (Fan-out area) size, and even eliminate the lead area to achieve narrow bezel design.
  • the display substrate 100 further includes a peripheral area 118 surrounding the normal display area 114 .
  • the fourth transfer line 174 extends from the normal display area 114 to the peripheral area 118 to lead out the data line 130 through the third transfer line 173 .
  • the fourth transfer line can be directly extended to the peripheral area and connected to a driver IC that provides data signals; of course, embodiments of the present disclosure include but are not limited to this, and the fourth transfer line can also be extended to the peripheral area by changing layers. And connected to the driver IC that provides data signals, and the position of layer change can be outside the normal display area.
  • the third patch cord 173 is arranged on the same layer as the first patch cord 171 . It should be noted that the above-mentioned “same layer arrangement" means that the third transfer line and the first transfer line are formed from the same conductive layer through the same patterning process.
  • the fourth patch cord 174 and the second patch cord 172 are arranged on the same layer. It should be noted that the above-mentioned “same layer arrangement" means that the fourth transfer line and the second transfer line are formed from the same conductive layer through the same patterning process.
  • the third adapter line 173 and the first adapter line 171 may be arranged on the same layer, the first adapter line 171 is used to transmit the first power supply voltage, and the third adapter line 173 is used to transmit data signals.
  • the fourth adapter line 174 and the second adapter line 172 can be arranged on the same layer, the second adapter line 172 is used to transmit the first power supply voltage, and the fourth adapter line 174 is used to transmit data signals.
  • the display substrate 100 further includes a connecting line segment 179 , the connecting line segment 179 and the third connecting line 173 are arranged on the same layer and are insulated from each other; the connecting line segment 179 and the third connecting line 173 are both along the first The straight lines extending in the direction X overlap, and the connecting line segments 179 connect the plurality of second transfer lines 172 arranged along the first direction X. Since the third adapter line is used to connect the data line to the corresponding fourth adapter line, it cannot extend from one edge of the normal display area to the other edge.
  • the connecting line segment in the first direction, if there is a third adapter line in some areas of the normal display area and there is no third adapter line in some areas, it will easily cause the third adapter line to be seen by the user without the display substrate being lit. , affecting the display quality.
  • the connecting line segment in the display substrate, by arranging the connecting line segment so that the connecting line segment and the third connecting line are substantially located on a straight line extending along the first direction X, the display substrate can prevent the third connecting line from being noticed by the user.
  • the connecting line segment can also further reduce the overall load of the first patch cord and the second patch cord.
  • FIG. 3 is a schematic plan view of another display substrate according to an embodiment of the present disclosure.
  • the third adapter line 173 can be located in the M-shaped area as shown in FIG. 3 .
  • the connecting line segment 179 and the third adapter line 173 can have the same light reflectivity. ,from This prevents the third adapter cable from being noticed by users.
  • the third transfer line can also be located in a V-shaped area, a W-shaped area, a triangular area, etc. in the normal display area, and the embodiments of the present disclosure are not limited here.
  • the connecting line segments 179 and the third transfer line 173 are arranged on the same layer and are arranged at intervals in the first direction. That is to say, the connection line segment 179 and the third transfer line 173 can be formed from the same conductive layer through the same patterning process, so that the connection line segment 179 and the third transfer line 173 can have the same light reflectivity, thereby preventing the third transfer line from being The user notices.
  • the distance between the connection line segment 179 and the third transfer line 173 in the first direction is smaller than the size of one pixel driving circuit 130 in the first direction, thereby preventing the distance from being perceived by the user.
  • the size of the above-mentioned pixel driving circuit in the first direction may be the size of the orthogonal projection of each film layer on the base substrate in the pixel driving circuit in the first direction, or may be the size of the pixel driving circuit in the first direction. The size of the orthographic projection of the source layer on the base substrate in the first direction.
  • the orthographic projection of the space between the connection line segment and the third transfer line on the base substrate may overlap with the orthographic projection of the anode of the light-emitting element on the base substrate to further make the space invisible to the user. to further improve display quality.
  • the width of the connecting line segment 179 in the second direction is equal to the width of the third patch cord 173 in the second direction, thereby further preventing the third patch cord from being noticed by the user.
  • the second transfer line 172 and the fourth transfer line 174 both overlap with a virtual straight line extending along the second direction Y and are insulated from each other. Therefore, by causing the second transfer line and the fourth transfer line to be approximately located on a virtual straight line extending along the second direction, the display substrate can prevent the second transfer line and the fourth transfer line from being noticed by the user.
  • the second transfer line 172 and the fourth transfer line 174 are arranged on the same layer and spaced apart in the first direction. That is to say, the second transfer line 172 and the fourth transfer line 174 can be formed from the same conductive layer through the same patterning process, so that the second transfer line 172 and the fourth transfer line 174 can have the same light reflectivity, thereby avoiding the second transfer line 172 and the fourth transfer line 174.
  • the second patch cord and the fourth patch cord are perceived by the user.
  • the distance between the second transfer line 172 and the fourth transfer line 174 in the second direction is smaller than the size of one pixel driving circuit 130 in the second direction, thereby preventing the distance from being blocked by the user. Noticed.
  • the width of the second patch cord 172 in the first direction is equal to the width of the fourth patch cord 174 in the first direction, thereby further avoiding the second patch cord and the fourth patch cord. perceived by the user.
  • the normal display area 114 includes a first sub-display area 114A and a second sub-display area 114B arranged in a first direction, and the data line 130 is located at an edge of the first sub-display area 114A.
  • the third transfer line 173 is connected to the fourth transfer line 174 located in the first sub-display area 114A.
  • the data line 130 located at the edge of the second sub-display area 114B is connected to the second sub-display area 114B through the third transfer line 173 .
  • the fourth adapter line 174 is connected. With this arrangement, the display substrate can gather the leads of the data lines in the normal display area to realize the function of the leads.
  • first sub-display area and second sub-display area may not be provided, and the data line at the edge of the normal display area may be connected to the third sub-display area located in the normal display area through a third adapter line.
  • Four-wire cable connection may be provided.
  • one second pixel driving column 220B is inserted into every three first pixel driving columns 220A, that is, two first pixel driving columns 220B are provided between two adjacent second pixel driving columns 220B.
  • Pixel drive column 220A a first pixel driving column
  • One second pixel driving column can also be inserted into every two first pixel driving columns, and one second pixel driving column can be inserted into every four first pixel driving columns; that is, That is, one first pixel driving column, three first pixel driving columns, or four first pixel driving columns are arranged between two adjacent second pixel driving columns.
  • one second pixel driving column is inserted for every N first pixel driving columns, and the value of N ranges from 2 to 10.
  • FIG. 4 is a schematic plan view of another display substrate according to an embodiment of the present disclosure.
  • the plurality of data lines 130 include a first data line 131 and a second data line 132 .
  • the first data line 131 is connected to the first pixel driving column 220A and is disconnected and formed in the transparent display area 112
  • the second data line 132 is connected to the second pixel driving column 220B and includes a third sub-data line segment 132A and a fourth sub-data line segment 132B.
  • the third sub-data line segment 132A The orthographic projection on the reference straight line extending in the second direction Y covers the orthographic projection of the transparent display area 112 on the reference straight line. That is to say, the first data line 131 is disconnected by the transparent display area 112 and forms a first sub-data line segment 131A and a second sub-data line segment 131B.
  • the second data line 132 is between the transparent display area 112 and the normal display area 114. It is disconnected at the lower junction position and forms a third sub-data line segment 132A and a fourth sub-data line segment 132B.
  • FIG. 3 only shows part of the signal lines and signal line segments.
  • the fourth sub-data line segment 132B since the fourth sub-data line segment 132B does not need to drive the light-emitting element, the fourth sub-data line segment 132B does not need to be loaded with data signals. At this time, the fourth sub-data line segment 132 can be connected to the first adapter line 171 Electrically connected and loaded with the first power supply voltage to reduce the load of the first adapter line 171 .
  • the display substrate 100 further includes a fifth transfer line 175 and a sixth transfer line 176 .
  • the fifth transfer line 175 is located on the first side of the transparent display area 112 in the second direction.
  • the sixth transfer line 176 is located on the second side of the transparent display area 112 in the second direction.
  • the first sub-data line 131A passes through the fifth transfer line.
  • the wiring 175 is connected to the third sub-data line segment 132A, and the second sub-data line 131B is connected to the third sub-data line segment 132A through the sixth switching line 176 . Therefore, the display substrate can connect the first sub-data line and the second sub-data line separated by the transparent display area through the fifth transfer line and the sixth transfer line to realize signal transmission.
  • the third sub-data line can be used as a data line of the pixel driving circuit corresponding to the second light-emitting element in the transparent display area, and the first sub-data line, the third sub-data line and the second sub-data line are connected to each other to provide the display Light-emitting elements located in the same column in the substrate provide data signals.
  • the fifth transfer line 175 and the sixth transfer line 176 are provided on the same layer as the first transfer line 171 , thereby making better use of the conductive film layer on the display substrate.
  • the fifth adapter line 175 , the sixth adapter line 176 and the first adapter line 171 are made to have the same reflectivity of light, thereby preventing the fifth adapter line 175 , the sixth adapter line 176 and the first adapter line 171 from being noticed by the user.
  • embodiments of the present disclosure include but are not limited to this, and the fifth transfer line and the sixth transfer line can also be provided on other conductive layers.
  • the sixth transfer line 176 and the first transfer line 171 may both overlap with a virtual straight line extending along the first direction X, so that the sixth transfer line 176 and the first transfer line 171 may be further avoided.
  • the first patch cord 171 is perceived by the user.
  • the width of the sixth transfer line 176 in the second direction Y is equal to the width of the first transfer line 171 in the second direction Y, so that the sixth transfer line 176 can be further avoided. Wiring 176 and first patch cord 171 are visible to the user.
  • the fourth sub-data line segment 132B is connected to the first transfer line 171 through the second via connection structure V2. Since the pixel driving circuit 120 corresponding to the fourth sub-data line segment 132B is not actually used to drive the light-emitting element and is a dummy pixel driving circuit (Dummy Pixel Driving Circuit), the fourth sub-data line 132B does not need to transmit data signals. At this time, the fourth sub-data line segment is connected to the first adapter line through the second via hole connection structure. The fourth sub-data line segment can also be used to further reduce the load of the first adapter line and the second adapter line and improve the display quality. It should be noted that the specific structure of the second via hole connection structure can be referred to the first via hole connection structure, and will not be described again here.
  • the base substrate 110 further includes a peripheral area 118 surrounding the normal display area 114 , and the fifth transfer line 175 is located in the peripheral area 118 . Therefore, the display substrate can use the space in the peripheral area to arrange the fifth transfer line, thereby improving the space utilization of the display substrate and reducing the number of signal lines in the display area.
  • the fifth patch cord 175 and the sixth patch cord 176 may be arranged on the same layer.
  • the embodiments of the present disclosure include but are not limited to this. Since there are fewer various signal lines in the peripheral area, the fifth transfer line and the sixth transfer line can also be arranged in different layers and made of other conductive layers.
  • the second sub-data line segment 131B can also be transferred to the fourth transfer line 174 through the third transfer line 173 , and the fourth transfer line 174 extends from the normal display area 114 to the peripheral area.
  • FIG. 5 is a schematic plan view of another display substrate according to an embodiment of the present disclosure.
  • the display substrate 100 includes a base substrate 110, a plurality of pixel driving circuits 120, a plurality of data lines 130 and a plurality of anode connection lines 140;
  • the base substrate 110 includes a transparent display area 112 and a surrounding transparent display area.
  • the normal display area 114 of 112; the transparent display area 112 and the normal display area 114 may constitute a display area for luminous display.
  • a plurality of pixel driving circuits 120 are located in the normal display area 114 and are arranged in an array along the first direction Extending, each pixel driving column 220 extends along the second direction Y; the plurality of data lines 130 extends along the second direction Y and is configured to provide data signals to the plurality of pixel driving columns 220 .
  • the normal display area 114 includes a first light-emitting element 151
  • the transparent display area 112 includes a second light-emitting element 152
  • the plurality of pixel driving columns 220 includes a plurality of first pixel driving columns 220A and a plurality of second pixel driving columns.
  • the pixel driving circuit 120 in the first pixel driving column 220A is connected to the first light-emitting element 151, for example, the first light-emitting element 151 and the pixel driving circuit 120 are overlapped and directly connected through a via connection structure; the second Some of the pixel driving circuits 120 in the pixel driving column 220B are connected to the second light-emitting elements 152 through a plurality of anode connection lines 140, so that some of the pixel driving circuits 120 located in the normal display area 114 can drive the second pixel driving circuits 120 located in the transparent display area 112.
  • the light-emitting element 152 emits light. It should be noted that the sizes of the first light-emitting element and the second light-emitting element are only illustrative, and the size of the first light-emitting element may be smaller than the size of the second light-emitting element.
  • the display substrate 100 further includes a first transfer line 171 and a second transfer line 172 .
  • the first transfer line 171 extends along the first direction X
  • the second transfer line 172 extends along the second direction Y.
  • the first transfer line 171 extends along the second direction Y.
  • the wiring 171 and the second switching wire 172 are arranged in different layers.
  • the first switching wire 171 and the second switching wire 172 are connected to the cathode of the first light-emitting element 151 and are configured to transmit a first power supply voltage, such as VSS; the first switching wire 171 and the second transfer line 172 are connected through the first via hole connection structure V1.
  • the orthographic projection of the first via hole connection structure V1 on the base substrate 110 is different from the orthographic projection of the plurality of anode connection lines 140 on the base substrate 110. overlap.
  • the display substrate since the display substrate includes a transparent display area, the transparent display area can be correspondingly provided with photosensitive devices such as cameras, so that the display substrate can realize an under-screen camera (Full Display with Camera, FDC) design. .
  • the display substrate since the first transfer line and the second transfer line for transmitting the first power supply voltage are connected through the first via hole connection structure, the display substrate can reduce the load of the first transfer line and the second transfer line, so that the entire display The uniformity of the first power voltage signal on the substrate is relatively high, thereby improving display quality.
  • the display substrate can also avoid the first through hole connection structure
  • the formed concave structure causes the risk of disconnection of the anode connecting wire.
  • the display substrate 100 further includes a plurality of power lines 160 and a first conductive structure 251 ; the plurality of power lines 160 extend along the second direction and are configured to drive the columns 220 to a plurality of pixels.
  • a second power supply voltage is provided, such as VDD; the first conductive structure 251 is arranged on the same layer as the plurality of power lines 160; the orthographic projection of the first conductive structure 251 on the base substrate 110 is connected to the unconnected anode in the second pixel driving column 220B.
  • the orthographic projections of the pixel driving circuit 120 of the line 140 on the base substrate 110 overlap, and the first conductive structure 251 and the first transfer line 171 are connected through the third via connection structure V3.
  • the parts of these pixel driving circuits corresponding to the power lines, that is, the first conductive structure can be used to transmit the second A power supply voltage, thereby further reducing the load on the first adapter line and the second adapter line and improving the display quality.
  • the plurality of power lines 160 include a first power line 161 and a second power line 162 ; the first power line 161 is provided corresponding to the first pixel driving column 220A and is configured to provide the first power line 161 to the first pixel driving column 220A.
  • the pixel driving circuit 120 in a pixel driving column 220A provides the second power supply voltage.
  • the first power line may be electrically connected to the anode of the first light-emitting element, or the anode of the first light-emitting element may be configured to load the second power voltage through the pixel driving circuit.
  • the orthographic projection of the second power line 162 on the reference straight line extending along the second direction covers the orthographic projection of the transparent display area 112 on the reference straight line.
  • the orthographic projection of the second power line 162 on the base substrate 110 overlaps the orthographic projection of the at least one anode connection line 140 on the base substrate 110 .
  • part of the first power line 161 is also divided into two sub-first power line segments by the transparent display area 112 .
  • the length of the second power line 162 is less than that of the first power line 161 the length of Formed by the same patterning process. Since the pixel driving circuit corresponding to the first conductive structure is not actually used to drive the light-emitting element and is a dummy pixel driving circuit, the first conductive structure does not need to transmit the second power supply voltage. At this time, the first conductive structure can be used to transmit the first power supply voltage, thereby further reducing the load on the first adapter line and the second adapter line and improving the display quality.
  • the width of the second power line 162 in the first direction is equal to the width of the first conductive structure 251 in the first direction.
  • the power line 160 is located on the base substrate 110
  • the first transfer line 171 may be located on a side of the power line 160 away from the base substrate 110
  • the second transfer line 172 may be located on the first transfer line 170 .
  • the wiring 171 is on a side away from the base substrate 110 .
  • the anode connection line 140 may be located on a side of the second transfer line 172 away from the base substrate 110 .
  • the power line 160 may be located on the first conductive layer or the first source-drain metal layer on the base substrate 110; the first transfer line 171, the third transfer line 173, the connection line segment 179, the fifth transfer line 175 and The sixth transfer line 176 may be located on the first conductive layer away from the second conductive layer or the second source-drain metal layer of the base substrate 110; the second transfer line 172 and the fourth transfer line 174 may be located on the second conductive layer away from the first conductive layer.
  • the third conductive layer or the third source and drain metal layer on one side of the layer.
  • the first conductive layer, the second conductive layer and the third conductive layer can be made of metal materials; the anode connection line can be made of transparent conductive oxide.
  • FIG. 6 is a schematic diagram of a stacking of a display substrate according to an embodiment of the present disclosure. As shown in FIG. 6 , part of the pixel driving circuit 120 located in the normal display area 114 is connected to a plurality of anode connection lines 140 , and the plurality of anode connection lines 140 extend from the normal display area 114 to the transparent display area 112 , to provide a driving voltage for the second light-emitting element in the transparent display area 112 .
  • FIG. 7A is a stacking schematic diagram of another display substrate provided by an embodiment of the present disclosure
  • FIG. 7B is a stacking schematic diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 7A shows a schematic stacking diagram of a region provided with anode connecting lines. For the sake of clarity, the anode connecting lines are omitted
  • FIG. 7B shows a stacking diagram of a region provided with anode connecting lines and a region without anode connecting lines. Schematic diagram.
  • the first transfer line 171 and the second transfer line 172 are not connected through a via connection structure; while in the area where the anode connection line 140 is not provided, area, the first transfer line 171 and the second transfer line 172 are connected through the first via connection structure V1. That is to say, the first transfer line 171 and the second transfer line 172 are connected through the first via hole connection structure V1, and the orthographic projection of the first via hole connection structure V1 on the base substrate 110 and the plurality of anode connection lines 140 are on the substrate.
  • the orthographic projections on the base substrate 110 do not overlap. Therefore, the display substrate can also avoid the risk of disconnection of the anode connection line caused by the recessed structure formed by the first via hole connection structure.
  • each pixel driving circuit 120 includes a second conductive structure 252 ; the second conductive structure 252 is arranged on the same layer as the first transfer line 171 ; the pixel driving circuit in the second pixel driving column 220B is not connected to the anode connection line 140 The second conductive structure 252 in 120 is connected to the second transfer line 172 through the fourth via connection structure V4.
  • the second conductive structures in these pixel driving circuits can be used to transmit the first power supply voltage, thereby The load on the first adapter line and the second adapter line is further reduced, and the display quality is improved.
  • FIG. 8 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the display device 300 includes the above-mentioned display substrate 100 .
  • the display device can achieve narrow bezel design and under-screen camera design.
  • the display device also reduces the load of the first power supply voltage and improves display quality.
  • the display device can be any product or component with a display function, such as a smartphone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or the like.
  • a display function such as a smartphone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or the like.
  • FIG. 9 is a stacking schematic diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 10 is an equivalent schematic diagram of a pixel driving circuit in a display substrate provided by an embodiment of the present disclosure
  • FIGS. 11 to 16 are schematic diagrams of a display substrate provided by an embodiment of the present disclosure.
  • the embodiment provides a schematic diagram of multiple film layers in a display substrate.
  • the display substrate 100 includes a base substrate 110 , a semiconductor layer 410 , a first gate layer 420 , a second gate layer 430 , a first conductive layer 440 , a second conductive layer 450 and a third conductive layer 450 .
  • the semiconductor layer 410 , the first gate layer 420 , the second gate layer 430 , the first conductive layer 440 , the second conductive layer 450 and the third conductive layer 460 are sequentially arranged in a direction perpendicular to the base substrate 110 .
  • an insulating layer such as a gate insulating layer, is provided between any two of the semiconductor layer, the first gate layer, the second gate layer, the first conductive layer, the second conductive layer and the third conductive layer. , interlayer insulation layer or passivation layer, etc., which will not be described again here.
  • the pixel driving circuit may adopt a 7T1C structure, that is, a circuit structure including seven transistors and a storage capacitor.
  • a 7T1C structure that is, a circuit structure including seven transistors and a storage capacitor.
  • embodiments of the present disclosure include, but are not limited to
  • the pixel driving circuit can also adopt other types of circuit structures, such as 8T1C, 8T2C, etc.
  • the pixel driving circuit 120 includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 and a seventh transistor T7 .
  • Storage capacitor Cst As shown in FIGS. 9 and 10 , the pixel driving circuit 120 includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 and a seventh transistor T7 .
  • the drain of the first transistor T1 , the drain of the second transistor T2 and the gate of the first transistor T1 are connected to the first node N1 , the source of the third transistor T3 , the drain of the fourth transistor T4 and the sixth transistor T6
  • the drain of is connected to the second node N2, the drain of the third transistor T3, the source of the fifth transistor T5 and the source of the second transistor T2 are connected to the third node, the drain of the fifth transistor T5 and the seventh transistor
  • the drain of T7 is connected to the anode of the light-emitting element (such as the above-mentioned first light-emitting element or the second light-emitting element); the first electrode plate CE1 of the storage capacitor Cst and the gate of the third transistor T3 are connected to the first node N1, and the storage
  • the second electrode plate CE2 of the capacitor Cst is connected to the source of the sixth transistor T6 and is configured to be connected to a power line.
  • the semiconductor layer 410 includes a first unit 411 , a second unit 412 , a third unit 413 , a fourth unit 414 , a fifth unit 415 , a sixth unit 416 and a seventh unit 416 .
  • the first unit 411 includes a first channel region C1 and a first source region S1 and a first drain region D1 located on both sides of the first channel region C1.
  • the second unit 412 includes a second channel region C2 and a first drain region S1 located on both sides of the first channel region C1.
  • the second source region S2 and the second drain region D2 on both sides of the second channel region C2.
  • the third unit 413 includes a third channel region C3 and a third source region S3 located on both sides of the third channel region C3. and a third drain region D3.
  • the fourth unit 414 includes a fourth channel region C4 and a fourth source region S4 and a fourth drain region D4 located on both sides of the fourth channel region C4.
  • the fifth unit 415 includes a The fifth channel region C5 and the fifth source region S5 and the fifth drain region S5 located on both sides of the fifth channel region C5.
  • the sixth unit 416 includes a sixth channel region C6 and a fifth channel region C6 located on both sides of the sixth channel region C6.
  • the seventh unit 417 includes a seventh channel region C7 and a seventh source region S7 and a seventh drain region located on both sides of the seventh channel region C7. D7.
  • the semiconductor layer may be made of silicon-based semiconductor material, such as polysilicon.
  • the embodiments of the present disclosure include but are not limited to this.
  • the semiconductor layer may also use other semiconductor materials such as oxide semiconductor materials.
  • each of the above-mentioned channel regions may be an undoped part of the semiconductor layer, and each of the source and drain regions may be doped parts of the semiconductor layer.
  • the above-mentioned first unit 411 is the active layer of the first transistor T1
  • the above-mentioned second unit 412 is the active layer of the second transistor T2
  • the above-mentioned third unit 413 is the active layer of the third transistor T3.
  • the above-mentioned fourth unit 414 is the active layer of the fourth transistor T4
  • the above-mentioned fifth unit 415 is the active layer of the fifth transistor T5
  • the above-mentioned sixth unit Unit 416 is the active layer of the sixth transistor T6
  • the above-mentioned seventh unit 417 is the active layer of the seventh transistor T7.
  • the first drain region D1 and the second drain region D2 are connected, the second source region S2, the third drain region D3 and the fifth source region S5 are connected, and the fourth drain region D4, the third source region S3 and the sixth drain region D6 are connected, and the fifth drain region D5 and the seventh drain region D7 are connected.
  • the first gate layer 420 includes a reset signal line 421 extending along the first direction, a gate line 422 extending along the first direction, a first electrode block CE1 and a first electrode block CE1 extending along the first direction.
  • the lighting control line 423 is shown in FIG. 12 .
  • the reset signal line 421 overlaps the seventh channel region C7 and the first channel region C1 of the semiconductor layer 410, so that the reset signal line 421 overlaps the seventh channel region C7 and the first channel region C1.
  • the overlapping portions of a channel region C1 can respectively serve as the gate electrode of the seventh transistor T7 and the gate electrode of the first transistor T1.
  • the gate line 422 overlaps the second channel region C2 and the fourth channel region C4 of the semiconductor layer 410, so that the overlapping portions of the gate line 422 and the second channel region C2 and the fourth channel region C4 can respectively serve as the third channel region C2 and the fourth channel region C4.
  • the light-emitting control line 423 overlaps the fifth channel region C5 and the sixth channel region C6, so that the overlapping portions of the light-emitting control line 423 and the fifth channel region C5 and the sixth channel region C6 can respectively serve as fifth transistors.
  • the first electrode block CE1 overlaps the third channel region C3, so that the first electrode block CE1 can serve as the gate of the third transistor T3.
  • the reset signal line 421 , the gate line 422 and the light-emitting control line 423 all extend generally along the first direction; the reset signal line 421 , the gate line 422 , the first electrode block CE1 and the light-emitting control line 423 extend along the The first direction is vertical and the second direction is set in sequence.
  • the second gate layer 430 includes a first initialization signal line 431 , a second initialization signal line 432 and a second electrode block CE2 extending along the first direction.
  • the first initialization signal line 431, the second initialization signal line 432 and the second electrode block CE2 are sequentially arranged along the second direction.
  • the first initialization signal line 431 is electrically connected to the first source region S1 and the seventh source region S7, thereby providing an initialization signal to the first transistor T1 and the seventh transistor T7.
  • the orthographic projection of the second electrode block CE2 on the base substrate 110 at least partially overlaps with the orthographic projection of the first electrode block CE1 on the base substrate 110 to form a storage capacitor Cst.
  • the second electrode block CE2 includes an opening OP, and the orthographic projection of the opening OP on the base substrate 110 overlaps with the orthographic projection of the first electrode layer CE1 on the base substrate 110 to expose part of the first electrode block CE1 .
  • the first conductive layer 440 includes an electrical conductor extending along the second direction.
  • the first transfer block 441 is connected to the fifth drain region D5 of the fifth transistor T5, and is configured to be connected to the anode of the subsequently formed light-emitting element, thereby converting the driving signal (for example, the power supply voltage) is transmitted from the fifth source region D5 of the fifth transistor T5 to the anode of the light emitting element.
  • the driving signal For example, the power supply voltage
  • one end of the second transfer block 442 is connected to the first drain region D1 of the first transistor T1 , and the other end of the second transfer block 442 can pass through the opening OP and be connected to the third The gate electrode of the transistor T3, that is, the first electrode block CE1 is connected.
  • the second transition block can also be regarded as a node connection block of the first node N1.
  • one end of the third transfer block 443 is connected to the seventh source region D7 of the seventh transistor T7 , and the other end of the third transfer block 443 is connected to the first initialization signal line 431 , thereby connecting the first initialization signal line 431 to the source of the seventh transistor T7.
  • the fourth transfer block 444 is connected to the fourth source region S4 of the fourth transistor T4, and is configured to be connected to a subsequently formed data line, thereby transmitting the data signal to the fourth transistor T4.
  • one end of the fifth transfer block 445 is connected to the sixth source region S6 of the sixth transistor T6 , and the other end of the fifth transfer block 445 is connected to the second initialization signal line 432 , thereby connecting the second initialization signal line 432 to the source of the sixth transistor T6.
  • the second conductive layer 450 includes the above-mentioned first transfer line 171 and the second conductive structure 252 ;
  • the first transfer line 171 includes a main body portion 171A extending along the first direction and a main body portion 171A extending from the main body portion 171A.
  • 171A has a first extension part 171B and a second extension part 171C extending in the second direction;
  • the first extension part 171B is configured to be electrically connected to the subsequently formed second transfer line 172 and is also where the first connection via structure is located.
  • the second extension portion 171C is located only in the second pixel driving column 220B and is configured to be electrically connected to the subsequently formed fourth sub-data line segment 132B.
  • the second conductive structure 252 in the first pixel driving column 220A may be electrically connected to the power line 160 , while the pixel driving circuit 120 in the second pixel driving column 220B that is not connected to the anode connection line 140
  • the second conductive structure 252 is connected to the second transfer line 172 through the fourth via connection structure V4.
  • the orthographic projection of the second conductive structure 252 on the base substrate 110 overlaps the orthographic projection of the second transfer block 442 on the base substrate 110 , so that the first node The voltage on N1 is more stable.
  • the orthographic projection of the second conductive structure 252 on the base substrate 110 overlaps with the orthographic projection of the second patch line 172 on the base substrate.
  • the third conductive layer 460 includes the data line 130 , the second transfer line 172 and the connection electrode 461 .
  • the data line 130 is electrically connected to the fourth transfer block 444
  • the second transfer line 172 is electrically connected to the first transfer line 171
  • the connection electrode 461 is electrically connected to the first transfer block 441.
  • a working mode of the pixel driving circuit shown in FIG. 10 will be schematically described below.
  • the reset signal is transmitted to the reset signal line 421 and the seventh transistor T7 is turned on, the residual current flowing through the anode of each light-emitting element is discharged through the seventh transistor T7, so that the current flowing through the anode of each light-emitting element can be suppressed. Luminescence caused by residual current.
  • the reset signal is transmitted to the reset signal line 421
  • the first initialization signal is transmitted to the first initialization signal line 431
  • the second initialization signal is transmitted to the second initialization signal line 432, the first transistor T1 and the seventh transistor T7 are turned on.
  • the first initialization signal initializes the anode of each light-emitting element through the seventh transistor T7
  • the second initialization signal initializes the gate of the third thin transistor T3 and the first electrode block CE1 of the storage capacitor Cst through the first transistor T1.
  • the initialization of the gate of the third thin transistor T3 may cause the third transistor T3 to be turned on.
  • both the second transistor T2 and the fourth transistor T4 are turned on, and the data line 130 passes to the third transistor T2 and the fourth transistor T4.
  • Data voltage Vd is applied to the gate of transistor T3.
  • the voltage applied to the gate of the third thin transistor T3 is the compensation voltage Vd+Vth, and the compensation voltage applied to the gate of the third transistor T3 is also applied to the first electrode block CE1 of the storage capacitor Cst.
  • the power supply line 160 applies the driving voltage Vel to the second electrode block CE2 of the storage capacitor Cst, and applies the compensation voltage Vd+Vth to the first electrode block CE1, so that the voltages between them are equal to the voltages respectively applied to the two electrodes of the storage capacitor Cst.
  • the charge corresponding to the difference is stored in the storage capacitor Cst, and the third transistor T3 is turned on for a predetermined time.
  • both the sixth transistor T6 and the fifth transistor T5 are turned on, so that the power supply line 160 applies the driving voltage Vel to the source of the sixth transistor T6.
  • the driving voltage Vel When passing through the third transistor T3 turned on by the storage capacitor Cst, the voltage of the drain of the third transistor T3 is Vel, and the voltage of the gate of the third transistor T3 is Vd+Vth, which can make the third transistor T3 in saturation. state, so that the third transistor T3 generates the driving current Ids; then, the driving current Id is applied to the anode of the light-emitting element through the fifth transistor T5, so that the light-emitting element emits light.
  • the first conductive layer may be a first source-drain metal layer
  • the second conductive layer may be a second source-drain metal layer
  • the third conductive layer may be a third source-drain metal layer.

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Abstract

一种显示基板(100)和显示装置(300)。在显示基板(100)中，多条数据线(130)被配置为向多个像素驱动列(220)提供数据信号；多个像素驱动列(220)包括多个第一像素驱动列(220A)和多个第二像素驱动列(220B)，第一像素驱动列(220A)中的像素驱动电路(120)与正常显示区(114)的第一发光元件(151)相连，第二像素驱动列(220B)中的部分像素驱动电路(120)通过多条阳极连接线(140)与透明显示区(112)的第二发光元件(152)相连；显示基板(100)还包括第一转接线(171)和第二转接线(172)，第一转接线(171)和第二转接线(172)与第一发光元件(151)的阴极相连，并传输第一电源电压；第一转接线(171)和第二转接线(172)通过第一过孔连接结构(V1)相连，第一过孔连接结构(V1)在衬底基板(110)上的正投影与多条阳极连接线(140)在衬底基板(110)上的正投影不交叠。由此，显示基板(100)可改善显示画质，并且还可降低阳极连接线(140)的断线风险。

Description

显示基板和显示装置
本申请要求于2022年08月31日递交的中国专利申请202211059440.5号的优先权，在此全文引用上述PCT申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板和显示装置。
背景技术
随着显示技术的不断发展，人们对于智能手机等电子产品的屏占比的要求也越来越高。因此，屏下摄像头设计(Full Display with Camera，FDC)逐渐成为各大厂商的研究热点。
屏下摄像头设计是在显示面板的显示区中设置透明显示区，该透明显示区既可进行显示，又可能允许光线透过；该显示面板的透明显示区设置摄像头等感光器件，从而可实现较大的屏占比，同时还能实现摄像、人脸识别等功能。
发明内容
在实现屏下摄像头设计和窄边框的基础上，为进一步降低电源电压(VSS)的负载并改善画质，本公开实施例提供一种显示基板和显示装置。该显示基板包括衬底基板、多个像素驱动电路、多条数据线和多条阳极连接线；衬底基板包括透明显示区和围绕透明显示区的正常显示区；多个像素驱动电路位于正常显示区且沿第一方向和第二方向阵列设置以形成多个像素驱动行和多个像素驱动列，各像素驱动行沿第一方向延伸，各像素驱动列沿第二方向延伸；多条数据线沿第二方向延伸并被配置为向多个像素驱动列提供数据信号；正常显示区包括第一发光元件，透明显示区包括第二发光元件，多个像素驱动列包括多个第一像素驱动列和多个第二像素驱动列，第一像素驱动列中的像素驱动电路与第一发光元件相连，第二像素驱动列中的部分像素驱动电路通过多条阳极连接线与第二发光元件相连；显示基板还包括第一转接线和第二转接线，第一转接线沿第一方向延伸，第二转接线沿第二方向延伸，第一转接线和第二转接线异层设置，第一转接线和第二转接线与所述第一发光元件的阴极相连，并被配置为传输第一电源电压；第一转接线和第二转接线通过第一过孔连接结构相 连，第一过孔连接结构在衬底基板上的正投影与多条阳极连接线在衬底基板上的正投影不交叠。由此，该显示基板在实现屏下摄像头设计的前提下，可降低用于传输第一电源电压的信号线的负载，从而改善显示画质。另一方面，该显示基板还可降低阳极连接线的断线风险。
本公开至少一个实施例提供一种显示基板，其包括：衬底基板，包括透明显示区和围绕所述透明显示区的正常显示区；多个像素驱动电路，位于所述正常显示区且沿第一方向和第二方向阵列设置以形成多个像素驱动行和多个像素驱动列，各所述像素驱动行沿所述第一方向延伸，各所述像素驱动列沿所述第二方向延伸；多条数据线，沿所述第二方向延伸并被配置为向所述多个像素驱动列提供数据信号；多条阳极连接线，所述正常显示区包括第一发光元件，所述透明显示区包括第二发光元件，所述多个像素驱动列包括多个第一像素驱动列和多个第二像素驱动列，所述第一像素驱动列中的所述像素驱动电路与所述第一发光元件相连，所述第二像素驱动列中的部分所述像素驱动电路通过所述多条阳极连接线与所述第二发光元件相连；所述显示基板还包括第一转接线和第二转接线，所述第一转接线沿所述第一方向延伸，所述第二转接线沿所述第二方向延伸，所述第一转接线和所述第二转接线异层设置，所述第一转接线和所述第二转接线与第一发光元件的阴极相连，并被配置为传输第一电源电压；所述第一转接线和所述第二转接线通过第一过孔连接结构相连，所述第一过孔连接结构在所述衬底基板上的正投影与所述多条阳极连接线在所述衬底基板上的正投影不交叠。
例如，在本公开一实施例提供的显示基板中，所述显示基板还包括第三转接线和第四转接线，所述第三转接线和所述第四转接线位于所述正常显示区，所述第三转接线沿所述第一方向延伸，所述第四转接线沿所述第二方向延伸，所述第三转接线的一端与所述数据线相连，所述第三转接线的另一端与所述第四转接线相连。
例如，在本公开一实施例提供的显示基板中，所述第三转接线与所述第一转接线同层设置。
例如，在本公开一实施例提供的显示基板中，所述第四转接线与所述第二转接线同层设置。
例如，在本公开一实施例提供的显示基板中，该显示基板还包括：连接线段，与所述第三转接线同层设置且相互绝缘，所述连接线段与所述第三转接线 均与沿所述第一方向延伸的虚拟直线交叠，所述连接线段将沿所述第一方向排列的多条所述第二转接线相连。
例如，在本公开一实施例提供的显示基板中，在至少一个所述像素驱动列之中，所述第二转接线与所述第四转接线均与沿所述第二方向延伸的虚拟直线交叠，且相互绝缘。
例如，在本公开一实施例提供的显示基板中，所述正常显示区包括在所述第一方向上排列的第一子显示区和第二子显示区，位于所述第一子显示区的边缘的所述数据线通过所述第三转接线与位于所述第一子显示区的所述第四转接线相连，位于所述第二子显示区的边缘的所述数据线通过所述第三转接线与位于所述第二子显示区的所述第四转接线相连。
例如，在本公开一实施例提供的显示基板中，两个相邻的所述第二像素驱动列之间设置有两个所述第一像素驱动列。
例如，在本公开一实施例提供的显示基板中，所述多条数据线包括第一数据线和第二数据线，所述第一数据线与所述第一像素驱动列相连并在所述透明显示区断开并形成第一子数据线段和第二子数据线段，所述第二数据线与所述第二像素驱动列相连，并包括第三子数据线段和第四子数据线段，所述第三子数据线段在沿第二方向上延伸的参考直线上的正投影覆盖所述透明显示区在所述参考直线上的正投影，所述显示基板还包括第五转接线和第六转接线，所述第五转接线位于所述透明显示区在所述第二方向上的第一侧，所述第六转接线位于所述透明显示区在所述第二方向上的第二侧，所述第一子数据线通过所述第五转接线与所述第三子数据线段相连，所述第二子数据线通过所述第六转接线与所述第三子数据线段相连。
例如，在本公开一实施例提供的显示基板中，所述第五转接线和所述第六转接线与所述第一转接线同层设置。
例如，在本公开一实施例提供的显示基板中，所述第四子数据线段通过第二过孔连接结构与所述第一转接线相连。
例如，在本公开一实施例提供的显示基板中，所述衬底基板还包括围绕所述正常显示区的周边区，所述第五转接线位于所述周边区。
例如，在本公开一实施例提供的显示基板中，该显示基板还包括：多条电源线，沿所述第二方向延伸并被配置为向所述多个像素驱动列提供第二电源电压；以及第一导电结构，与所述多条电源线同层设置，所述第一导电结构在所 述衬底基板上的正投影与所述第二像素驱动列中未连接所述阳极连接线的所述像素驱动电路在所述衬底基板上的正投影交叠，所述第一导电结构与所述第一转接线通过第三过孔连接结构相连。
例如，在本公开一实施例提供的显示基板中，各所述像素驱动电路包括第二导电结构，与所述第一转接线同层设置；所述第二像素驱动列中未连接所述阳极连接线的所述像素驱动电路中的所述第二导电结构通过第四过孔连接结构与所述第二转接线相连。
例如，在本公开一实施例提供的显示基板中，所述衬底基板还包括围绕所述正常显示区的周边区，所述显示基板还包括位于所述周边区的电源电压线，所述电源电压线被配置为传输第一电源电压；所述第一转接线和所述第二转接线中的至少之一延伸至所述周边区与所述电源电压线电性相连。
本公开至少一个实施例还提供一种显示装置，其包括上述任一项的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一实施例提供的一种显示基板的平面示意图；
图2为本公开一实施例提供的一种显示基板中第一转接线和第二转接线连接的示意图；
图3为本公开一实施例提供的另一种显示基板的平面示意图；
图4为本公开一实施例提供的另一种显示基板的平面示意图；
图5为本公开一实施例提供的另一种显示基板的平面示意图；
图6为本公开一实施例提供的一种显示基板的层叠示意图；
图7A为本公开一实施例提供的另一种显示基板的层叠示意图；
图7B为本公开一实施例提供的另一种显示基板的层叠示意图；
图8为本公开一实施例提供的一种显示装置的示意图；
图9为本公开一实施例提供的一种显示基板的层叠示意图；
图10为本公开一实施例提供的一种显示基板中像素驱动电路的等效示意图；以及
图11-16为本公开一实施例提供的一种显示基板中多个膜层的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
通常，像素单元包括像素驱动电路和与像素驱动电路相连的发光元件，而像素驱动电路通常不透光。因此，在屏下摄像头设计中，显示基板的透明显示区可通过将像素驱动电路去掉，发光元件保留的方式来实现透明显示功能，即：既可进行显示，又可能允许光线透过的功能。在这种技术方案中，透明显示区中的发光元件对应的像素驱动电路需要设置在透明显示区之外的正常显示区中。
另一方面，通常的显示基板的显示区包括多条用于驱动显示基板中的像素单元进行发光显示的多条信号线，而这些信号线需要外接的驱动电路或驱动芯片进行驱动。因此，显示基板还包括位于周边区的引线区和绑定区，引线区包括多条引线，绑定区用于与外接的驱动电路或驱动芯片进行绑定；此时，多条引线可与多条信号线相连并延伸至绑定区，从而与外接的驱动电路或驱动芯片绑定。显然，显示基板的周边区中引线区和绑定区的存在势必会影响采用该显示基板的显示基板的边框宽度，特别是下边框的宽度。因此，为了窄化显示装置的下边框，可通过将数据线等信号线的引线设置在显示区来减少引线区(Fan-out区)的尺寸，以实现窄边框设计。
在以上技术方案的基础上，为进一步降低电源电压(VSS)的负载并改善 画质，本公开实施例提供一种显示基板和显示装置。该显示基板包括衬底基板、多个像素驱动电路、多条数据线和多条阳极连接线；衬底基板包括透明显示区和围绕透明显示区的正常显示区；多个像素驱动电路位于正常显示区且沿第一方向和第二方向阵列设置以形成多个像素驱动行和多个像素驱动列，各像素驱动行沿第一方向延伸，各像素驱动列沿第二方向延伸；多条数据线沿第二方向延伸并被配置为向多个像素驱动列提供数据信号；正常显示区包括第一发光元件，透明显示区包括第二发光元件，多个像素驱动列包括多个第一像素驱动列和多个第二像素驱动列，第一像素驱动列中的像素驱动电路与第一发光元件相连，第二像素驱动列中的部分像素驱动电路通过多条阳极连接线与第二发光元件相连；显示基板还包括第一转接线和第二转接线，第一转接线沿第一方向延伸，第二转接线沿第二方向延伸，第一转接线和第二转接线异层设置，第一转接线和第二转接线与第一发光元件的阴极相连，并被配置为传输第一电源电压；第一转接线和第二转接线通过第一过孔连接结构相连，第一过孔连接结构在衬底基板上的正投影与多条阳极连接线在衬底基板上的正投影不交叠。由此，该显示基板在实现屏下摄像头设计的前提下，可降低用于传输第一电源电压的信号线的负载，从而改善显示画质。另一方面，该显示基板还可降低阳极连接线的断线风险。
下面，结合附图对本公开实施例提供的显示基板和显示装置进行详细的说明。
本公开一实施例提供一种显示基板。图1为本公开一实施例提供的一种显示基板的平面示意图。如图1所示，该显示基板100包括衬底基板110、多个像素驱动电路120、多条数据线130和多条阳极连接线140；衬底基板110包括透明显示区112和围绕透明显示区112的正常显示区114；透明显示区112和正常显示区114可组成用于发光显示的显示区。多个像素驱动电路120位于正常显示区114且沿第一方向X和第二方向Y阵列设置以形成多个像素驱动行210和多个像素驱动列220，各像素驱动行210沿第一方向X延伸，各像素驱动列220沿第二方向Y延伸；多条数据线130沿第二方向Y延伸并被配置为向多个像素驱动列220提供数据信号。
如图1所示，正常显示区114包括第一发光元件151，透明显示区112包括第二发光元件152，多个像素驱动列220包括多个第一像素驱动列220A和多个第二像素驱动列220B；第一像素驱动列220A中的像素驱动电路120与第 一发光元件151相连，例如将第一发光元件151和像素驱动电路120交叠设置，并通过过孔连接结构直接相连；第二像素驱动列220B中的部分像素驱动电路120通过多条阳极连接线140与第二发光元件152相连，从而使得位于正常显示区114的部分像素驱动电路120可驱动位于透明显示区112中的第二发光元件152进行发光。需要说明的是，为了清楚地示出第一发光元件下方的像素驱动电路和各种信号线，图1仅示出了一个第一发光元件和两个第二发光元件；本公开实施例包括但不限于此，第一像素驱动列中的每个像素驱动电路可对应设置一个第一发光元件，而透明显示区可根据需要的亮度、分辨率、透过率等参数设置多个第二发光元件。
如图1所示，显示基板100还包括第一转接线171和第二转接线172，第一转接线171沿第一方向X延伸，第二转接线172沿第二方向Y延伸，第一转接线171和第二转接线172异层设置，第一转接线171和第二转接线172与第一发光元件151的阴极相连，并被配置为传输第一电源电压，例如VSS电压；第一转接线171和第二转接线172通过第一过孔连接结构V1相连，第一过孔连接结构V1在衬底基板110上的正投影与多条阳极连接线140在衬底基板110上的正投影不交叠。例如，如图1中线框290所示，第一过孔连接结构V1在衬底基板110上的正投影与多条阳极连接线140在衬底基板110上的正投影不交叠。
在本公开实施例提供的显示基板中，由于该显示基板包括透明显示区，透明显示区可对应设置摄像头等感光器件，由此该显示基板可实现屏下摄像头(Full Display with Camera，FDC)设计。另外，由于用于传输第一电源电压的第一转接线和第二转接线通过第一过孔连接结构相连，因此该显示基板可降低第一转接线和第二转接线的负载，使得整个显示基板上的第一电源电压信号的均一性较高，从而可改善显示画质。另一方面，由于第一过孔连接结构在衬底基板上的正投影与多条阳极连接线在衬底基板上的正投影不交叠，因此该显示基板还可避免第一过孔连接结构形成的凹陷结构造成的阳极连接线的断线风险。
例如，衬底基板110的材料可为玻璃、塑料、石英等透明材料，也可为硅基半导体材料。当然，本公开实施例包括但不限于此，衬底基板的材料也可为其他合适的材料。
图2为本公开一实施例提供的一种显示基板中第一转接线和第二转接线连 接的示意图。如图2所示，第一转接线171和第二转接线172之间设置有绝缘的平坦层180；此时，第一过孔连接结构V1包括位于平坦层180中的第一过孔H1，第一过孔H1暴露部分第一转接线171；第二转接线172的一部分位于第一过孔H1并与第一转接线171相连。
如图2所示，第二转接线172远离平坦层180的一侧还设置有绝缘层191；由于第一过孔连接结构V1的存在，绝缘层191对应第一过孔连接结构V1的位置会形成凹陷结构，若将阳极连接线与第一过孔连接结构交叠，则容易导致阳极连接线在凹陷结构所在的位置发生断线风险，从而使得位于透明显示区中的第二元件无法发光显示。在本公开实施例提供的显示基板中，由于第一过孔连接结构在衬底基板上的正投影与多条阳极连接线在衬底基板上的正投影不交叠，因此该显示基板还可避免第一过孔连接结构形成的凹陷结构造成的阳极连接线的断线风险，并提高产品良率。
例如，平坦层180可包括有机平坦层和无机平坦层中的一种或者它们的叠层；有机平坦层的材料可采用聚酰亚胺、树脂和丙烯酸中至少一种；无机平坦层的材料可为氧化硅、氮化硅或氮氧化硅中的至少一种。钝化层的材料可为氧化硅、氮化硅或氮氧化硅中的至少一种。当然，本公开实施例包括但不限于此，平坦层也可采用其他材料制作。
例如，绝缘层191的材料可为氧化硅、氮化硅、氮氧化硅中的一种或多种。当然，本公开实施例包括但不限于此，栅极绝缘层的材料也可为其他材料。
在一些示例中，如图1所示，衬底基板110还包括围绕正常显示区114的周边区118；显示基板100还包括位于周边区118的电源电压线260，该电源电压线260被配置为传输第一电源电压。第一转接线171和第二转接线172中的至少之一延伸至周边区118与电源电压线260电性相连。
在一些示例中，如图1所示，多条第一转接线171和多条第二转接线172可通过多个第一过孔连接结构V1形成网格结构，从而进一步降低负载，提高整个显示基板上第一电源电压的均一性，从而提高显示品质。
在一些示例中，如图1所示，该显示基板100还包括第三转接线173和第四转接线174；第三转接线173和第四转接线174均位于正常显示区114；第三转接线173沿第一方向X延伸，第四转接线174沿第二方向Y延伸；第三转接线173的一端与数据线130相连，第三转接线173的另一端与第四转接线174相连。由此，该显示基板可将数据线的引线设置在正常显示区来减小引线 区(Fan-out区)的尺寸，甚至取消引线区来实现窄边框设计。
在一些示例中，如图1所示，该显示基板100还包括周边区118，围绕正常显示区114。第四转接线174从正常显示区114延伸至周边区118，以通过第三转接线173将数据线130引出。需要说明的是，第四转接线可直接延伸至周边区并与提供数据信号的驱动IC连接；当然，本公开实施例包括但不限于此，第四转接线也可通过换层延伸到周边区并与提供数据信号的驱动IC连接，并且换层的位置可以在正常显示区之外。
在一些示例中，如图1所示，第三转接线173与第一转接线171同层设置。需要说明的是，上述的“同层设置”是指第三转接线和第一转接线由同一导电层经过同一图案化工艺形成。
在一些示例中，如图1所示，第四转接线174与第二转接线172同层设置。需要说明的是，上述的“同层设置”是指第四转接线和第二转接线由同一导电层经过同一图案化工艺形成。
在一些示例中，虽然第三转接线173与第一转接线171可以同层设置，但是第一转接线171用于传输第一电源电压，而第三转接线173用于传输数据信号。同样地，虽然第四转接线174与第二转接线172可以同层设置，但是第二转接线172用于传输第一电源电压，而第四转接线174用于传输数据信号。
在一些示例中，如图1所示，该显示基板100还包括连接线段179，连接线段179与第三转接线173同层设置且相互绝缘；连接线段179与第三转接线173均沿第一方向X延伸的直线交叠，连接线段179将沿第一方向X排列的多条第二转接线172相连。由于第三转接线是用于将数据线与对应的第四转接线相连，因此不能从正常显示区的一个边缘延伸至另一个边缘。此时，在第一方向上，若正常显示区的部分区域存在第三转接线，部分区域不存在第三转接线则容易导致第三转接线在显示基板不点亮的情况下被用户看到，影响显示品质。然而，在该显示基板中，通过设置连接线段，并使得连接线段与第三转接线大致位于沿第一方向X延伸的直线上，该显示基板可避免第三转接线被用户察觉到。另一方面，连接线段也可进一步降低第一转接线和第二转接线的整体负载。
图3为本公开一实施例提供的另一种显示基板的平面示意图。如图3所示，第三转接线173可位于如图3所示的M形区域内，通过设置上述的连接线段179，从而可使得连接线段179和第三转接线173具有相同的光线反射率，从 而避免第三转接线被用户察觉到。需要说明的是，第三转接线也可位于在正常显示区中V形区域、W形区域、三角形区域等，本公开实施例在此不作限制。
在一些示例中，如图1所示，连接线段179与第三转接线173同层设置，且在第一方向上间隔设置。也就是说，连接线段179和第三转接线173可由同一导电层经过同一图案化工艺形成，从而可使得连接线段179和第三转接线173具有相同的光线反射率，从而避免第三转接线被用户察觉到。
在一些示例中，如图1所示，连接线段179和第三转接线173在第一方向上的间距小于一个像素驱动电路130在第一方向上的尺寸，从而可避免该间隔被用户察觉到。需要说明的是，上述的像素驱动电路在第一方向上的尺寸可为像素驱动电路中各膜层在衬底基板上的正投影在第一方向上的尺寸，也可为像素驱动电路中有源层在衬底基板上的正投影在第一方向上的尺寸。
在一些示例中，连接线段和第三转接线之间的间隔在衬底基板上的正投影可与发光元件的阳极在衬底基板上的正投影交叠，以进一步使得该间隔无法被用户察觉到，从而进一步提高显示品质。
在一些示例中，如图1所示，连接线段179在第二方向上的宽度与第三转接线173在第二方向上的宽度相等，从而进一步避免第三转接线被用户察觉到。
在一些示例中，如图1所示，在至少一个像素驱动列220之中，第二转接线172与第四转接线174均与沿第二方向Y延伸的虚拟直线交叠，且相互绝缘。由此，通过使得第二转接线与第四转接线大致位于沿第二方向延伸的虚拟直线上，该显示基板可避免第二转接线和第四转接线被用户察觉到。
在一些示例中，如图1所示，在至少一个像素驱动列220之中，第二转接线172与第四转接线174同层设置，且在第一方向上间隔设置。也就是说，第二转接线172与第四转接线174可由同一导电层经过同一图案化工艺形成，从而可使得第二转接线172与第四转接线174具有相同的光线反射率，从而避免第二转接线和第四转接线被用户察觉到。
在一些示例中，如图1所示，第二转接线172与第四转接线174在第二方向上的间距小于一个像素驱动电路130在第二方向上的尺寸，从而可避免该间隔被用户察觉到。
在一些示例中，如图1所示，第二转接线172在第一方向上的宽度与第四转接线174在第一方向上的宽度相等，从而进一步避免第二转接线和第四转接线被用户察觉到。
在一些示例中，如图1所示，正常显示区114包括在第一方向上排列的第一子显示区114A和第二子显示区114B，位于第一子显示区114A的边缘的数据线130通过第三转接线173与位于第一子显示区114A的第四转接线174相连，位于第二子显示区114B的边缘的数据线130通过第三转接线173与位于第二子显示区114B的第四转接线174相连。如此设置，该显示基板可在正常显示区中将数据线的引线集中起来，实现引线的功能。当然，本公开实施例包括但不限于此，也可不设置上述的第一子显示区和第二子显示区，将正常显示区的边缘的数据线通过第三转接线与位于正常显示区的第四转接线相连。
在一些示例中，如图1所示，每三个第一像素驱动列220A插入一个第二像素驱动列220B，也即两个相邻的第二像素驱动列220B之间设置有两个第一像素驱动列220A。当然，本公开实施例包括但不限于此，也可每两个第一像素驱动列插入一个第二像素驱动列，每四个第一像素驱动列插入一个第二像素驱动列；也就是说，也即两个相邻的第二像素驱动列之间设置有一个第一像素驱动列、三个第一像素驱动列或四个第一像素驱动列。
在一些示例中，每N个第一像素驱动列插入一个第二像素驱动列，N的取值范围为2-10。
图4为本公开一实施例提供的另一种显示基板的平面示意图。如图1和图4所示，多条数据线130包括第一数据线131和第二数据线132，第一数据线131与第一像素驱动列220A相连并在透明显示区112断开并形成第一子数据线段131A和第二子数据线段131B，第二数据线132与第二像素驱动列220B相连，并包括第三子数据线段132A和第四子数据线段132B，第三子数据线段132A在沿第二方向Y上延伸的参考直线上的正投影覆盖透明显示区112在参考直线上的正投影。也就是说，第一数据线131被透明显示区112断开，并形成第一子数据线段131A和第二子数据线段131B，第二数据线132在对应透明显示区112和正常显示区114的下交界位置处断开，并形成第三子数据线段132A和第四子数据线段132B。需要说明的是，为了清楚地示出上述各信号线或信号线段之间的连接关系，图3仅示出了部分信号线和信号线段。
如图1和图4所示，由于第四子数据线段132B不用驱动发光元件，因此第四子数据线段132B上可不用加载数据信号，此时第四子数据线段132可与第一转接线171电性相连并加载第一电源电压，以降低第一转接线171的负载。
如图1和图4所示，显示基板100还包括第五转接线175和第六转接线176， 第五转接线175位于透明显示区112在第二方向上的第一侧，第六转接线176位于透明显示区112在第二方向上的第二侧，第一子数据线131A通过第五转接线175与第三子数据线段132A相连，第二子数据线131B通过第六转接线176与第三子数据线段132A相连。由此，该显示基板可将通过第五转接线和第六转接线将被透明显示区隔开的第一子数据线和第二子数据线相连，以实现信号的传输。并且，第三子数据线可作为透明显示区中的第二发光元件对应的像素驱动电路的数据线，第一子数据线、第三子数据线和第二子数据线相互连接从而为该显示基板中位于同一列的发光元件提供数据信号。
在一些示例中，如图1和图4所示，第五转接线175和第六转接线176与第一转接线171同层设置，从而在更好地利用显示基板上的导电膜层的同时使得第五转接线175、第六转接线176和第一转接线171对于光线的反射率相同，避免第五转接线175、第六转接线176和第一转接线171被用户察觉到。当然，本公开实施例包括但不限于此，第五转接线和第六转接线也可设置在其他导电层。
在一些示例中，如图1和图4所示，第六转接线176与第一转接线171可均与沿第一方向X延伸的虚拟直线交叠，从而可进一步避免第六转接线176和第一转接线171被用户察觉到。
在一些示例中，如图1和图4所示，第六转接线176在第二方向Y上的宽度与第一转接线171在第二方向Y上的宽度相等，从而可进一步避免第六转接线176和第一转接线171被用户察觉到。
在一些示例中，如图1和图4所示，第四子数据线段132B通过第二过孔连接结构V2与第一转接线171相连。由于第四子数据线段132B对应的像素驱动电路120不用实际用于驱动发光元件，为虚设的像素驱动电路(Dummy Pixel Driving Circuit)，因此第四子数据线132B不用传输数据信号。此时，第四子数据线段通过第二过孔连接结构与第一转接线相连，第四子数据线段也可用于进一步降低第一转接线和第二转接线的负载，提高显示品质。需要说明的是，第二过孔连接结构的具体结构可参见第一过孔连接结构，在此不再赘述。
在一些示例中，如图1和图4所示，衬底基板110还包括围绕正常显示区114的周边区118，第五转接线175位于周边区118。由此，该显示基板可利用周边区的空间来设置第五转接线，从而可提高显示基板的空间利用率，并降低显示区中信号线的数量。
在一些示例中，如图1和图4所示，第五转接线175和第六转接线176可同层设置。然而，本公开实施例包括但不限于此，由于周边区的各种信号线较少，第五转接线与第六转接线也可不同层设置，而是采用其他导电层制作。
在一些示例中，如图4所示，第二子数据线段131B也可通过第三转接线173转接到第四转接线174，第四转接线174再从正常显示区114延伸至周边区。
图5为本公开一实施例提供的另一种显示基板的平面示意图。如图5所示，该显示基板100包括衬底基板110、多个像素驱动电路120、多条数据线130和多条阳极连接线140；衬底基板110包括透明显示区112和围绕透明显示区112的正常显示区114；透明显示区112和正常显示区114可组成用于发光显示的显示区。多个像素驱动电路120位于正常显示区114且沿第一方向X和第二方向Y阵列设置以形成多个像素驱动行210和多个像素驱动列220，各像素驱动行210沿第一方向X延伸，各像素驱动列220沿第二方向Y延伸；多条数据线130沿第二方向Y延伸并被配置为向多个像素驱动列220提供数据信号。
如图5所示，正常显示区114包括第一发光元件151，透明显示区112包括第二发光元件152，多个像素驱动列220包括多个第一像素驱动列220A和多个第二像素驱动列220B；第一像素驱动列220A中的像素驱动电路120与第一发光元件151相连，例如将第一发光元件151和像素驱动电路120交叠设置，并通过过孔连接结构直接相连；第二像素驱动列220B中的部分像素驱动电路120通过多条阳极连接线140与第二发光元件152相连，从而使得位于正常显示区114的部分像素驱动电路120可驱动位于透明显示区112中的第二发光元件152进行发光。需要说明的是，第一发光元件和第二发光元件的尺寸仅为示意性的，第一发光元件的尺寸可小于第二发光元件的尺寸。
如图5所示，显示基板100还包括第一转接线171和第二转接线172，第一转接线171沿第一方向X延伸，第二转接线172沿第二方向Y延伸，第一转接线171和第二转接线172异层设置，第一转接线171和第二转接线172与第一发光元件151的阴极相连，并被配置为传输第一电源电压，例如VSS；第一转接线171和第二转接线172通过第一过孔连接结构V1相连，第一过孔连接结构V1在衬底基板110上的正投影与多条阳极连接线140在衬底基板110上的正投影不交叠。
在本公开实施例提供的显示基板中，由于该显示基板包括透明显示区，透明显示区可对应设置摄像头等感光器件，由此该显示基板可实现屏下摄像头(Full Display with Camera，FDC)设计。另外，由于用于传输第一电源电压的第一转接线和第二转接线通过第一过孔连接结构相连，因此该显示基板可降低第一转接线和第二转接线的负载，使得整个显示基板上的第一电源电压信号的均一性较高，从而可改善显示画质。另一方面，由于第一过孔连接结构在衬底基板上的正投影与多条阳极连接线在衬底基板上的正投影不交叠，因此该显示基板还可避免第一过孔连接结构形成的凹陷结构造成的阳极连接线的断线风险。
在一些示例中，如图5所示，该显示基板100还包括多条电源线160和第一导电结构251；多条电源线160沿第二方向延伸并被配置为向多个像素驱动列220提供第二电源电压，例如VDD；第一导电结构251与多条电源线160同层设置；第一导电结构251在衬底基板110上的正投影与第二像素驱动列220B中未连接阳极连接线140的像素驱动电路120在衬底基板110上的正投影交叠，第一导电结构251与第一转接线171通过第三过孔连接结构V3相连。由于第二像素驱动列220B中未连接阳极连接线140的像素驱动电路120并不需要实际驱动发光元件进行发光显示，因此这些像素驱动电路对应电源线的部分，即第一导电结构可用于传输第一电源电压，从而进一步降低第一转接线和第二转接线的负载，提高显示品质。
在一些示例中，如图5所示，多条电源线160包括第一电源线161和第二电源线162；第一电源线161与第一像素驱动列220A对应设置，并被配置为向第一像素驱动列220A中的像素驱动电路120提供第二电源电压。需要说明的是，第一电源线可与第一发光元件的阳极电性相连，或者第一发光元件的阳极被配置为通过像素驱动电路加载第二电源电压。
在一些示例中，如图5所示，第二电源线162在沿第二方向延伸的参考直线上的正投影覆盖透明显示区112在该参考直线上的正投影。
在一些示例中，第二电源线162在衬底基板110上的正投影与至少一条阳极连接线140在衬底基板110上的正投影交叠。
在一些示例中，如图5所示，部分第一电源线161也被透明显示区112分为两个子第一电源线段。
在一些示例中，如图5所示，第二电源线162的长度小于第一电源线161 的长度；第二电源线162和第一导电结构251可均与沿第二方向Y延伸的虚拟直线交叠；第二电源线162和第一导电结构251同层设置，即由同一导电层经过同一图案化工艺形成。由于第一导电结构对应的像素驱动电路不用实际用于驱动发光元件，为虚设的像素驱动电路(Dummy Pixel Driving Circuit)，因此第一导电结构不用传输第二电源电压。此时，第一导电结构可用于传输第一电源电压，从而进一步降低第一转接线和第二转接线的负载，提高显示品质。
在一些示例中，如图5所示，第二电源线162在第一方向上的宽度和第一导电结构251在第一方向上的宽度相等。
在一些示例中，如图5所示，电源线160位于衬底基板110上，第一转接线171可位于电源线160远离衬底基板110的一侧，第二转接线172可位于第一转接线171远离衬底基板110的一侧。
在一些示例中，如图5所示，阳极连接线140可位于第二转接线172远离衬底基板110的一侧。
在一些示例中，电源线160可位于衬底基板110上的第一导电层或第一源漏金属层；第一转接线171、第三转接线173、连接线段179、第五转接线175和第六转接线176可位于第一导电层远离衬底基板110的第二导电层或第二源漏金属层；第二转接线172和第四转接线174可位于第二导电层远离第一导电层的一侧的第三导电层或第三源漏金属层。
在一些示例中，第一导电层、第二导电层和第三导电层可采用金属材料制作；阳极连接线可采用透明导电氧化物制作。
图6为本公开一实施例提供的一种显示基板的层叠示意图。如图6所示，如图6所示，位于正常显示区114中的部分像素驱动电路120与多条阳极连接线140相连，多条阳极连接线140从正常显示区114延伸至透明显示区112，以为透明显示区112中的第二发光元件提供驱动电压。
图7A为本公开一实施例提供的另一种显示基板的层叠示意图；图7B为本公开一实施例提供的另一种显示基板的层叠示意图。图7A示出的是设置有阳极连接线的区域的层叠示意图，为了清楚起见，将阳极连接线省略；图7B示出的是设置有阳极连接线的区域和没有设置阳极连接线的区域的层叠示意图。
如图7A和图7B所示，在设置有阳极连接线140的区域，第一转接线171和第二转接线172不通过过孔连接结构相连；而在没有设置阳极连接线140的 区域，第一转接线171和第二转接线172通过第一过孔连接结构V1相连。也就是说，第一转接线171和第二转接线172通过第一过孔连接结构V1相连，第一过孔连接结构V1在衬底基板110上的正投影与多条阳极连接线140在衬底基板110上的正投影不交叠。由此，该显示基板还可避免第一过孔连接结构形成的凹陷结构造成的阳极连接线的断线风险。
如图7B所示，各像素驱动电路120包括第二导电结构252；第二导电结构252与第一转接线171同层设置；第二像素驱动列220B中未连接阳极连接线140的像素驱动电路120中的第二导电结构252通过第四过孔连接结构V4与第二转接线172相连。由于第二像素驱动列220B中未连接阳极连接线140的像素驱动电路120并不需要实际驱动发光元件进行发光显示，因此这些像素驱动电路中的第二导电结构可用于传输第一电源电压，从而进一步降低第一转接线和第二转接线的负载，提高显示品质。
本公开一实施例还提供一种显示装置。图8为本公开一实施例提供的一种显示装置的示意图。如图8所示，该显示装置300包括上述的显示基板100。由此，该显示装置可实现窄边框设计和屏下摄像头设计。另外，该显示装置还降低第一电源电压的负载，提高显示品质。
例如，在一些示例中，该显示装置可以为智能手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开一实施例提供一种显示基板。图9为本公开一实施例提供的一种显示基板的层叠示意图；图10为本公开一实施例提供的一种显示基板中像素驱动电路的等效示意图；图11-图16为本公开一实施例提供的一种显示基板中多个膜层的示意图。
如图9-图16所示，该显示基板100包括衬底基板110、半导体层410、第一栅极层420、第二栅极层430、第一导电层440、第二导电层450和第三导电层460。半导体层410、第一栅极层420、第二栅极层430、第一导电层440、第二导电层450和第三导电层460沿垂直于衬底基板110的方向上依次设置。需要说明的是，半导体层、第一栅极层、第二栅极层、第一导电层、第二导电层和第三导电层中任意两者之间设置有绝缘层，例如栅极绝缘层、层间绝缘层或钝化层等，在此不再赘述。
在本公开实施例提供的显示基板中，像素驱动电路可采用7T1C结构，即包括七个晶体管和一个存储电容的电路结构。当然，本公开实施例包括但不限 于此，像素驱动电路也可采用其他类型的电路结构，例如8T1C、8T2C等。
下面，结合图9-图16以像素驱动电路采用7T1C结构为例对本公开实施例提供的显示基板的多个膜层进行详细的说明。
如图9和图10所示，该像素驱动电路120包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7和存储电容Cst。第一晶体管T1的漏极、第二晶体管T2的漏极和第一晶体管T1的栅极连接至第一节点N1，第三晶体管T3的源极、第四晶体管T4的漏极和第六晶体管T6的漏极连接至第二节点N2，第三晶体管T3的漏极、第五晶体管T5的源极和第二晶体管T2的源极连接至第三节点，第五晶体管T5的漏极和第七晶体管T7的漏极与发光元件(例如上述的第一发光元件或第二发光元件)的阳极相连；存储电容Cst的第一电极板CE1与第三晶体管T3的栅极连接至第一节点N1，存储电容Cst的第二电极板CE2与第六晶体管T6的源极相连并被配置为电源线相连。
在一些示例中，如图9和图11所示，半导体层410包括第一单元411、第二单元412、第三单元413、第四单元414、第五单元415、第六单元416和第七单元417。第一单元411包括第一沟道区C1和位于第一沟道区C1两侧的第一源极区S1和第一漏极区D1，第二单元412包括第二沟道区C2和位于第二沟道区C2两侧的第二源极区S2和第二漏极区D2，第三单元413包括第三沟道区C3和位于第三沟道区C3两侧的第三源极区S3和第三漏极区D3，第四单元414包括第四沟道区C4和位于第四沟道区C4两侧的第四源极区S4和第四漏极区D4，第五单元415包括第五沟道区C5和位于第五沟道区C5两侧的第五源极区S5和第五漏极区S5，第六单元416包括第六沟道区C6和位于第六沟道区C6两侧的第六源极区S6和第六漏极区D6，第七单元417包括第七沟道区C7和位于第七沟道区C7两侧的第七源极区S7和第七漏极区D7。
例如，半导体层可采用硅基半导体材料，例如多晶硅。当然，本公开实施例包括但不限于此，半导体层还可采用氧化物半导体材料等其他半导体材料。
需要说明的是，上述的各个沟道区可为半导体层未被掺杂的部分，而各个源极区和漏极区可为半导体被掺杂的部分。另外，上述的第一单元411为第一晶体管T1的有源层，上述的第二单元412为第二晶体管T2的有源层，上述的第三单元413为第三晶体管T3的有源层，上述的第四单元414为第四晶体管T4的有源层，上述的第五单元415为第五晶体管T5的有源层，上述的第六单 元416为第六晶体管T6的有源层，上述的第七单元417为第七晶体管T7的有源层。
例如，如图11所示，第一漏极区D1和第二漏极区D2相连，第二源极区S2、第三漏极区D3和第五源极区S5相连，第四漏极区D4、第三源极区S3和第六漏极区D6相连，第五漏极区D5和第七漏极区D7相连。
在一些示例中，如图12所示，第一栅极层420包括沿第一方向延伸的复位信号线421、沿第一方向延伸的栅线422、第一电极块CE1和沿第一方向延伸的发光控制线423。
例如，如图9-图16所示，复位信号线421与半导体层410的第七沟道区C7和第一沟道区C1交叠，使得复位信号线421与第七沟道区C7和第一沟道区C1交叠的部分可分别作为第七晶体管T7的栅极和第一晶体管T1的栅极。栅线422与半导体层410的第二沟道区C2和第四沟道区C4交叠，使得栅线422与第二沟道区C2和第四沟道区C4交叠的部分可分别作为第二晶体管T2的栅极和第四晶体管T4的栅极。发光控制线423与第五沟道区C5和第六沟道区C6交叠，使得发光控制线423与第五沟道区C5和第六沟道区C6交叠的部分可分别作为第五晶体管T5的栅极和第六晶体管T6的栅极。第一电极块CE1与第三沟道区C3交叠，以使得第一电极块CE1可作为第三晶体管T3的栅极。
例如，如图12所示，复位信号线421、栅线422和发光控制线423均大致沿第一方向延伸；复位信号线421、栅线422、第一电极块CE1和发光控制线423沿与第一方向垂直的第二方向依次设置。
在一些示例中，如图13所示，第二栅极层430包括沿第一方向延伸的第一初始化信号线431、第二初始化信号线432和第二电极块CE2。第一初始化信号线431、第二初始化信号线432和第二电极块CE2沿第二方向依次设置。
例如，如图9-图16所示，第一初始化信号线431与第一源极区S1和第七源极区S7电性相连，从而向第一晶体管T1和第七晶体管T7提供初始化信号。第二电极块CE2在衬底基板110上的正投影与第一电极块CE1在衬底基板110上的正投影至少部分重叠，形成存储电容Cst。
例如，如图13所示，第二电极块CE2包括开口OP，开口OP在衬底基板110上的正投影与第一电极层CE1在衬底基板110上的正投影交叠，以暴露部分第一电极层CE1。
在一些示例中，如图14所示，第一导电层440包括沿第二方向延伸的电 源线160、第一转接块441、第二转接块442、第三转接块443、第四转接块444和第五转接块445。
例如，如图9-图16所示，第一转接块441与第五晶体管T5的第五漏极区D5相连，并被配置为与后续形成的发光元件的阳极相连，从而将驱动信号(例如，电源电压)从第五晶体管T5的第五源极区D5传输到发光元件的阳极。
例如，如图9-图16所示，第二转接块442的一端与第一晶体管T1的第一漏极区D1相连，第二转接块442的另一端可穿过开口OP与第三晶体管T3的栅极，即第一电极块CE1相连。此时，第二转接块也可视为第一节点N1的节点连接块。
例如，如图9-图16所示，第三转接块443的一端与第七晶体管T7的第七源极区D7相连，第三转接块443的另一端与第一初始化信号线431相连，从而可将第一初始化信号线431与第七晶体管T7的源极相连。
例如，如图9-图16所示，第四转接块444与第四晶体管T4的第四源极区S4相连，并被配置为与后续形成的数据线相连，从而将数据信号传输到第四晶体管T4的第四源极区S4。
例如，如图9-图16所示，第五转接块445的一端与第六晶体管T6的第六源极区S6相连，第五转接块445的另一端与第二初始化信号线432相连，从而可将第二初始化信号线432与第六晶体管T6的源极相连。
在一些示例中，如图15所示，第二导电层450包括上述的第一转接线171和第二导电结构252；第一转接线171包括沿第一方向延伸的主体部171A和从主体部171A沿第二方向延伸的第一延伸部171B和第二延伸部171C；第一延伸部171B被配置为与后续形成的第二转接线172电性相连，也是第一连接过孔结构所在的位置。第二延伸部171C仅位于第二像素驱动列220B，并被配置为与后续形成的第四子数据线段132B电性相连。
例如，如图15所示，第一像素驱动列220A中的第二导电结构252可与电源线160电性相连，而第二像素驱动列220B中未连接阳极连接线140的像素驱动电路120中的第二导电结构252通过第四过孔连接结构V4与第二转接线172相连。
例如，如图9和图15所示，第二导电结构252在衬底基板110上的正投影与第二转接块442在衬底基板110上的正投影交叠，从而可使得第一节点N1上的电压更加稳定。
例如，如图9和图15所示，第二导电结构252在衬底基板110上的正投影与第二转接线172在衬底基板上的正投影交叠。
在一些示例中，如图16所示，第三导电层460包括数据线130、第二转接线172和连接电极461。数据线130与第四转接块444电性相连，第二转接线172与第一转接线171电性相连，连接电极461与第一转接块441电性相连。
下面将对图10所示的像素驱动电路的一种工作方式进行示意性描述。首先，当向复位信号线421传输复位信号并使得第七晶体管T7导通时，流经各个发光元件的阳极的剩余电流通过第七晶体管T7放电，从而可抑制由于流经各个发光元件的阳极的剩余电流导致的发光。然后，当向复位信号线421传输复位信号，向第一初始化信号线431传输第一初始化信号，并向第二初始化信号线432传输第二初始化信号时，第一晶体管T1和第七晶体管T7导通，第一初始化信号通过第七晶体管T7将各个发光元件的阳极初始化，第二初始化信号通过第一晶体管T1将第三薄晶体管T3的栅极和存储电容Cst的第一电极块CE1初始化。并且第三薄晶体管T3的栅极的初始化可使得第三晶体管T3导通。
随后，当向栅线422传输栅极信号并向数据线130传输数据信号时，第二晶体管T2和第四晶体管T4都导通，数据线130通过第二晶体管T2和第四晶体管T4向第三晶体管T3的栅极施加数据电压Vd。此时，施加到第三薄晶体管T3的栅极的电压是补偿电压Vd+Vth，并且施加到第三晶体管T3的栅极的补偿电压也被施加到存储电容Cst的第一电极块CE1。
随后，电源线160向存储电容Cst的第二电极块CE2施加驱动电压Vel，向第一电极块CE1施加补偿电压Vd+Vth，使得与分别施加到存储电容Cst的两个电极的电压之间的差对应的电荷存储在存储电容Cst中，第三晶体管T3导通达到预定时间。
随后，当向发光控制线423施加发射控制信号时，第六晶体管T6和第五晶体管T5都导通，使得电源线160向第六晶体管T6的源极施加驱动电压Vel，此时，驱动电压Vel穿过由存储电容Cst导通的第三晶体管T3时，第三晶体管T3的漏极的电压为Vel，第三晶体管T3的栅极的电压为Vd+Vth，这样可以使第三晶体管T3处于饱和状态，从而使第三晶体管T3产生驱动电流Ids；然后，驱动电流Id通过第五晶体管T5施加到发光元件的阳极，使得发光元件进行发光。
需要说明的是，上述的驱动电路的工作方式仅仅是该驱动电路的一种可能 的驱动方式，本公开实施例包括但不限于此。
在一些示例中，第一导电层可为第一源漏金属层，第二导电层可为第二源漏金属层，第三导电层可为第三源漏金属层。
有以下几点需要说明：
(1)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开同一实施例及不同实施例中的特征可以相互组合。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (16)

  1. 一种显示基板，包括：
    衬底基板，包括透明显示区和围绕所述透明显示区的正常显示区；
    多个像素驱动电路，位于所述正常显示区且沿第一方向和第二方向阵列设置以形成多个像素驱动行和多个像素驱动列，各所述像素驱动行沿所述第一方向延伸，各所述像素驱动列沿所述第二方向延伸；
    多条数据线，沿所述第二方向延伸并被配置为向所述多个像素驱动列提供数据信号；
    多条阳极连接线，
    其中，所述正常显示区包括第一发光元件，所述透明显示区包括第二发光元件，所述多个像素驱动列包括多个第一像素驱动列和多个第二像素驱动列，所述第一像素驱动列中的所述像素驱动电路与所述第一发光元件相连，所述第二像素驱动列中的部分所述像素驱动电路通过所述多条阳极连接线与所述第二发光元件相连；
    所述显示基板还包括第一转接线和第二转接线，所述第一转接线沿所述第一方向延伸，所述第二转接线沿所述第二方向延伸，所述第一转接线和所述第二转接线异层设置，所述第一转接线和所述第二转接线与所述第一发光元件的阴极相连，并被配置为传输第一电源电压，
    所述第一转接线和所述第二转接线通过第一过孔连接结构相连，所述第一过孔连接结构在所述衬底基板上的正投影与所述多条阳极连接线在所述衬底基板上的正投影不交叠。
  2. 根据权利要求1所述的显示基板，其中，所述显示基板还包括第三转接线和第四转接线，所述第三转接线和所述第四转接线位于所述正常显示区，所述第三转接线沿所述第一方向延伸，所述第四转接线沿所述第二方向延伸，
    所述第三转接线的一端与所述数据线相连，所述第三转接线的另一端与所述第四转接线相连。
  3. 根据权利要求2所述的显示基板，其中，所述第三转接线与所述第一转接线同层设置。
  4. 根据权利要求2所述的显示基板，其中，所述第四转接线与所述第二转接线同层设置。
  5. 根据权利要求2所述的显示基板，还包括：
    连接线段，与所述第三转接线同层设置且相互绝缘，
    其中，所述连接线段与所述第三转接线均与沿所述第一方向延伸的虚拟直线交叠，所述连接线段将沿所述第一方向排列的多条所述第二转接线相连。
  6. 根据权利要求2所述的显示基板，其中，在至少一个所述像素驱动列之中，所述第二转接线与所述第四转接线均与沿所述第二方向延伸的虚拟直线交叠，且相互绝缘。
  7. 根据权利要求2-6中任一项所述的显示基板，其中，所述正常显示区包括在所述第一方向上排列的第一子显示区和第二子显示区，位于所述第一子显示区的边缘的所述数据线通过所述第三转接线与位于所述第一子显示区的所述第四转接线相连，位于所述第二子显示区的边缘的所述数据线通过所述第三转接线与位于所述第二子显示区的所述第四转接线相连。
  8. 根据权利要求1-7中任一项所述的显示基板，其中，两个相邻的所述第二像素驱动列之间设置有两个所述第一像素驱动列。
  9. 根据权利要求1-8中任一项所述的显示基板，其中，所述多条数据线包括第一数据线和第二数据线，所述第一数据线与所述第一像素驱动列相连并在所述透明显示区断开并形成第一子数据线段和第二子数据线段，所述第二数据线与所述第二像素驱动列相连，并包括第三子数据线段和第四子数据线段，所述第三子数据线段在沿第二方向上延伸的参考直线上的正投影覆盖所述透明显示区在所述参考直线上的正投影，
    所述显示基板还包括第五转接线和第六转接线，所述第五转接线位于所述透明显示区在所述第二方向上的第一侧，所述第六转接线位于所述透明显示区在所述第二方向上的第二侧，所述第一子数据线通过所述第五转接线与所述第三子数据线段相连，所述第二子数据线通过所述第六转接线与所述第三子数据线段相连。
  10. 根据权利要求9所述的显示基板，其中，所述第五转接线和所述第六转接线与所述第一转接线同层设置。
  11. 根据权利要求9所述的显示基板，其中，所述第四子数据线段通过第二过孔连接结构与所述第一转接线相连。
  12. 根据权利要求9所述的显示基板，其中，所述衬底基板还包括围绕所述正常显示区的周边区，所述第五转接线位于所述周边区。
  13. 根据权利要求1-12中任一项所述的显示基板，还包括：
    多条电源线，沿所述第二方向延伸并被配置为向所述多个像素驱动列提供第二电源电压；以及
    第一导电结构，与所述多条电源线同层设置，
    其中，所述第一导电结构在所述衬底基板上的正投影与所述第二像素驱动列中未连接所述阳极连接线的所述像素驱动电路在所述衬底基板上的正投影交叠，所述第一导电结构与所述第一转接线通过第三过孔连接结构相连。
  14. 根据权利要求1-13中任一项所述的显示基板，其中，各所述像素驱动电路包括第二导电结构，与所述第一转接线同层设置；
    所述第二像素驱动列中未连接所述阳极连接线的所述像素驱动电路中的所述第二导电结构通过第四过孔连接结构与所述第二转接线相连。
  15. 根据权利要求1-14中任一项所述的显示基板，其中，所述衬底基板还包括围绕所述正常显示区的周边区，所述显示基板还包括位于所述周边区的电源电压线，所述电源电压线被配置为传输第一电源电压；
    所述第一转接线和所述第二转接线中的至少之一延伸至所述周边区与所述电源电压线电性相连。
  16. 一种显示装置，包括根据权利要求1-15中任一项所述的显示基板。
PCT/CN2023/111616 2022-08-31 2023-08-08 显示基板和显示装置 Ceased WO2024046047A1 (zh)

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