WO2024066424A1 - 太阳电池及其制备方法 - Google Patents

太阳电池及其制备方法 Download PDF

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Publication number
WO2024066424A1
WO2024066424A1 PCT/CN2023/097010 CN2023097010W WO2024066424A1 WO 2024066424 A1 WO2024066424 A1 WO 2024066424A1 CN 2023097010 W CN2023097010 W CN 2023097010W WO 2024066424 A1 WO2024066424 A1 WO 2024066424A1
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Prior art keywords
phosphorus
wafer substrate
doped
film layer
boron
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English (en)
French (fr)
Inventor
范建彬
孟夏杰
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Tongwei Solar Chengdu Co Ltd
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Tongwei Solar Chengdu Co Ltd
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Priority to EP23869677.7A priority Critical patent/EP4489082A4/en
Priority to AU2023349665A priority patent/AU2023349665B2/en
Priority to US18/852,924 priority patent/US20250234671A1/en
Publication of WO2024066424A1 publication Critical patent/WO2024066424A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H10F71/1221—The active layers comprising only Group IV materials comprising polycrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/12—Active materials
    • H10F77/122—Active materials comprising only Group IV materials
    • H10F77/1223—Active materials comprising only Group IV materials characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H10F77/219—Arrangements for electrodes of back-contact photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/30—Coatings
    • H10F77/306—Coatings for devices having potential barriers
    • H10F77/311—Coatings for devices having potential barriers for photovoltaic cells
    • H10F77/315—Coatings for devices having potential barriers for photovoltaic cells the coatings being antireflective or having enhancing optical properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • H10F77/703—Surface textures, e.g. pyramid structures of the semiconductor bodies, e.g. textured active layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the technical field of solar cells, and in particular to a solar cell and a method for preparing the same.
  • PERC cells Passivated Emitter and Rear Cell
  • TOPCon cells Tel Oxide Passivated Contact solar cell
  • IBC cells Interdigitated Back Contact
  • the front of the battery needs to be prepared into a velvet surface, while the back is a polished structure.
  • the conventional practice is to first polish all of it in a wet tank, and then design a mask layer as a barrier layer on the back of the battery, and then enter the wet tank to achieve a velvet surface on the front and a polished structure on the back.
  • the back needs to be grooved or patterned, and a mask structure is also required.
  • the mask layer used in the traditional solar cell production process has the problem of insufficient corrosion resistance, resulting in a shorter time window for processes such as texturing or de-plating, affecting the yield of the cell.
  • a method for preparing a solar cell comprising the following steps:
  • the solar cell substrate comprising an area A that needs to be subjected to a first treatment and an area B that does not need to be subjected to the first treatment;
  • the first treatment includes one or more of a texturing treatment, an etching treatment and a de-plating treatment.
  • the solar cell substrate is a silicon wafer substrate
  • the region A includes the front side of the silicon wafer substrate and a partial region on the back side of the silicon wafer substrate
  • the region B is the portion of the back side of the silicon wafer substrate that does not belong to the region A
  • the first treatment includes performing a texturing treatment on the region A on the front side of the silicon wafer substrate using a texturing solution, and performing an etching treatment on the region A on the back side of the silicon wafer substrate.
  • forming a phosphorus-boron co-doped silicon oxide layer on the region B comprises the following steps:
  • the back side of the silicon wafer substrate is patterned to remove part of the phosphorus-boron co-doped silicon oxide layer; wherein the back side region of the silicon wafer substrate corresponding to the remaining phosphorus-boron co-doped silicon oxide layer is the region B.
  • forming a phosphorus-boron co-doped silicon oxide layer on the back side of the silicon wafer substrate comprises the following steps:
  • the silicon wafer substrate is annealed to convert the phosphorus-doped amorphous silicon film layer into a phosphorus-doped polysilicon film layer, and to allow the boron-doped silicon oxide layer to absorb phosphorus to form the phosphorus-boron co-doped silicon oxide layer.
  • the phosphorus-doped amorphous silicon film layer and the boron-doped silicon oxide layer are sequentially formed on the back side of the silicon wafer substrate by plasma enhanced chemical vapor deposition.
  • forming the phosphorus-doped amorphous silicon film layer comprises the following steps:
  • the phosphorus-doped amorphous silicon film layer is deposited on the back of the silicon wafer substrate by a plasma enhanced chemical vapor deposition method using a reaction gas containing phosphine and silane, and the phosphorus-doped amorphous silicon film layer is deposited on the back of the silicon wafer substrate by a plasma enhanced chemical vapor deposition method.
  • the flow rate of phosphine in the reaction gas is gradually increased.
  • forming the boron-doped silicon oxide layer comprises the following steps:
  • the boron-doped silicon oxide layer is deposited on the back of the silicon wafer substrate by plasma enhanced chemical vapor deposition using a reaction gas containing a boron source and silane, and during the deposition of the boron-doped silicon oxide layer, the flow rate of the boron source in the reaction gas is made lower than 1/3 of the flow rate of the silane.
  • the temperature of the annealing treatment is 800° C. to 950° C.
  • the time of the annealing treatment is 15 min to 60 min.
  • forming a phosphorus-boron co-doped silicon oxide layer on the back side of the silicon wafer substrate comprises the following steps:
  • Boron is diffused on the surface of the phosphorus-doped silicon oxide layer to form the phosphorus-boron co-doped silicon oxide layer.
  • the graphical processing comprises the following steps:
  • the back side of the silicon wafer substrate is processed by using a green laser or an ultraviolet laser to remove part of the phosphorus-boron co-doped silicon oxide layer.
  • the preparation method before forming the phosphorus-doped amorphous silicon film layer on the back side of the silicon wafer substrate, the preparation method further comprises the following steps:
  • An ultra-thin silicon oxide layer is formed on the back of the silicon wafer substrate by plasma enhanced chemical vapor deposition, and the thickness of the ultra-thin silicon oxide layer is 1nm to 3nm.
  • the preparation method further comprises the following steps:
  • a first electrode is prepared on the region A on the back side of the silicon wafer substrate, and a second electrode is prepared on the region B on the back side of the silicon wafer substrate.
  • the preparation method further comprises depositing a first aluminum oxide film layer and a second aluminum oxide film layer on the front and back sides of the silicon wafer substrate, respectively. step.
  • the preparation method after depositing the first aluminum oxide film layer and the second aluminum oxide film layer and before preparing the first electrode and the second electrode, the preparation method also includes the steps of depositing a first anti-reflection film layer and a second anti-reflection film layer on the first aluminum oxide film layer and the second aluminum oxide film layer, respectively.
  • the solar cell substrate is a silicon wafer substrate with a wrap-around coating on the front side; the region A includes the front side of the silicon wafer substrate, and the region B includes the back side of the silicon wafer substrate; and the first treatment is to perform a de-wrapping treatment on the region A.
  • forming a phosphorus-boron co-doped silicon oxide layer on the region B comprises the following steps:
  • the silicon wafer substrate is annealed to convert the phosphorus-doped amorphous silicon film layer into a phosphorus-doped polysilicon film layer, and to allow the boron-doped silicon oxide layer to absorb phosphorus to form the phosphorus-boron co-doped silicon oxide layer.
  • the phosphorus-doped amorphous silicon film layer and the boron-doped silicon oxide layer are sequentially formed on the back side of the silicon wafer substrate by plasma enhanced chemical vapor deposition.
  • forming the phosphorus-doped amorphous silicon film layer comprises the following steps:
  • the phosphorus-doped amorphous silicon film layer is deposited on the back of the silicon wafer substrate by plasma enhanced chemical vapor deposition using reaction gas containing phosphine and silane, and the flow rate of phosphine in the reaction gas is gradually increased during the deposition of the phosphorus-doped amorphous silicon film layer.
  • forming the boron-doped silicon oxide layer comprises the following steps:
  • the boron-doped silicon oxide layer is deposited on the back of the silicon wafer substrate by plasma enhanced chemical vapor deposition using a reaction gas containing a boron source and silane, and during the deposition of the boron-doped silicon oxide layer, the flow rate of the boron source in the reaction gas is made lower than 1/3 of the flow rate of the silane.
  • the temperature of the annealing treatment is 800° C. to 950° C.
  • the time of the annealing treatment is 15 min to 60 min.
  • forming a phosphorus-boron co-doped silicon oxide layer on the region B comprises the following steps:
  • Boron is diffused on the surface of the phosphorus-doped silicon oxide layer to form the phosphorus-boron co-doped silicon oxide layer.
  • a solar cell is provided.
  • the solar cell is prepared by the method for preparing a solar cell according to the first aspect of the present application.
  • the solar cell comprises a silicon wafer substrate, an ultra-thin silicon oxide layer, a phosphorus-doped polysilicon film layer, a first electrode and a second electrode;
  • the back side of the silicon wafer substrate has an n-type doped region and a p-type region, the ultra-thin silicon oxide layer and the phosphorus-doped polysilicon film layer are stacked in sequence in the n-type doped region on the back side of the silicon wafer substrate; the first electrode is arranged in the p-type region and in contact with the silicon wafer substrate; the second electrode is arranged in the n-type doped region and in contact with the phosphorus-doped polysilicon film layer.
  • the solar cell further comprises a first aluminum oxide film layer, a first anti-reflection film layer, a second aluminum oxide film layer and a second anti-reflection film layer;
  • the first aluminum oxide film layer and the first anti-reflection film layer are stacked in sequence on the front side of the silicon wafer substrate; the second aluminum oxide film layer is arranged on the surface of the phosphorus-doped polysilicon film layer in the n-type doping area away from the ultra-thin silicon oxide layer and the surface of the silicon wafer substrate in the p-type area; the second anti-reflection film layer is arranged on the surface of the second aluminum oxide film layer away from the silicon wafer substrate; the first electrode passes through the second anti-reflection film layer and the second aluminum oxide film layer to contact the silicon wafer substrate; the second electrode passes through the second anti-reflection film layer and the second aluminum oxide film layer to contact the phosphorus-doped polysilicon film layer.
  • the phosphorus-boron co-doped silicon oxide layer By forming a phosphorus-boron co-doped silicon oxide layer as a mask layer on area B of the solar cell substrate that does not need to be subjected to the first treatment, the phosphorus-boron co-doped silicon oxide layer has super corrosion resistance.
  • the phosphorus-boron co-doped silicon oxide layer can play a good blocking role on area B, thereby providing a sufficiently long time window for the first treatment process of area A (such as texturing, etching, de-plating, etc.), which is beneficial to improving the yield of solar cells.
  • FIG1 is a schematic diagram of a silicon wafer substrate used in an embodiment of the present application.
  • FIG2 is a schematic diagram of forming a phosphorus-boron co-doped silicon oxide layer on a silicon wafer substrate according to an embodiment of the present application
  • FIG3 is a schematic diagram of a silicon wafer substrate after patterning is performed on the back side of the silicon wafer substrate according to an embodiment of the present application;
  • FIG4 is a schematic diagram of texturing the front side of a silicon wafer substrate and etching a patterned area according to an embodiment of the present application
  • FIG5 is a schematic diagram of a patterned area after patterning a hole in an embodiment of the present application.
  • FIG6 is a schematic diagram of the structure of a solar cell prepared in one embodiment of the present application.
  • FIG. 7 is a schematic diagram of the back side of a solar cell prepared in an embodiment of the present application.
  • Silicon wafer substrate 2-1. Ultra-thin silicon oxide layer; 2-2. Phosphorus-doped polysilicon film layer; 4. Phosphorus-boron co-doped silicon oxide layer; 5. Patterned area; 6. First aluminum oxide film layer; 7. Second aluminum oxide film layer; 8. First anti-reflection film layer; 9. Second anti-reflection film layer; 10. Electrode contact area; 11. First electrode; 12. Second electrode; 100. Back contact solar cell.
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as “first” and “second” may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality” is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
  • the terms “installed”, “connected”, “connected”, “fixed” and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined.
  • installed can be a fixed connection, a detachable connection, or an integral connection
  • it can be a mechanical connection or an electrical connection
  • it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined.
  • the specific meanings of the above terms in this application can be understood according to specific circumstances.
  • an embodiment of the present application provides a method for preparing a back-contact solar cell 100 , and the method comprises the following steps S1 to S9:
  • Step S1 De-damage treatment, polishing treatment and cleaning treatment are performed on the silicon wafer substrate 1 (solar cell substrate) in sequence.
  • the structure of the silicon wafer substrate 1 is shown in FIG1 .
  • a solution containing KOH is used to remove damage on a silicon wafer substrate 1 at 60°C; then, a solution containing KOH is used to polish the silicon wafer substrate 1 at 75°C, so that the reflectivity of the polished silicon wafer substrate 1 is 30%; and then, a mixed solution containing hydrofluoric acid and hydrochloric acid is used to clean the silicon wafer substrate 1, clean it with deionized water, and dry it.
  • the silicon wafer substrate 1 is specifically a p-type silicon substrate. In some other embodiments, the silicon wafer substrate 1 may also be an n-type silicon substrate.
  • Step S2 PECVD (Plasma Enhanced Chemical Vapor Deposition) is used to sequentially deposit an ultra-thin silicon oxide layer 2-1, a phosphorus-doped amorphous silicon film layer and a boron-doped silicon oxide layer on the back side of the silicon wafer substrate 1.
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • the flow rate of phosphine is lower than the flow rate of silane; and in the initial stage of depositing the phosphorus-doped amorphous silicon film, a low flow rate of phosphine and a high flow rate of silane are introduced, and after the phosphorus-doped amorphous silicon film is deposited to 10nm to 30nm, the flow rate of phosphine is increased, and the flow rate of silane remains unchanged during the deposition process.
  • a smaller composite can be formed near the surface of the silicon wafer substrate 1; and at the phosphorus-doped amorphous silicon film, the surface of the silicon wafer substrate 1 is formed.
  • a larger phosphorus concentration is formed on the side of the layer away from the silicon wafer substrate 1, thereby enhancing field passivation and being beneficial to the formation of a boron-phosphorus co-doped layer.
  • a boron source and silane are used as reaction gases, and the flow rate of the boron source is controlled to be less than 1/3 of the flow rate of silane.
  • Boron doping can form borophosphorus glass with phosphorus to provide strong corrosion resistance.
  • the boron content needs to be controlled at a low level so that the boron does not enter the silicon body to a large extent and cause carrier recombination.
  • the thickness of the ultra-thin silicon oxide layer 2-1 is 0.5nm to 3nm, preferably 2nm; the thickness of the phosphorus-doped amorphous silicon film layer is 30nm to 300nm, preferably 100nm to 150nm; the thickness of the boron-doped silicon oxide layer is 10nm to 100nm, preferably 20nm to 50nm.
  • the temperature for depositing the ultra-thin silicon oxide layer 2-1, the phosphorus-doped amorphous silicon film layer and the boron-doped silicon oxide layer is 200°C to 500°C, preferably 450°C.
  • Step S3 annealing the silicon wafer substrate 1.
  • the silicon wafer substrate 1 after annealing is shown in FIG2.
  • the amorphous silicon a-Si deposited by PECVD can be transformed into polycrystalline Poly, and the grains can be grown larger; at the same time, the loose boron-doped silicon oxide layer grown by PECVD can be made dense, and its alkali resistance can be enhanced.
  • the deposited boron-doped silicon oxide layer will absorb a portion of phosphorus from the phosphorus-doped polysilicon film layer 2-2 (formed after the phosphorus-doped amorphous silicon film layer is transformed), and form a phosphorus-boron co-doped silicon oxide layer 4 with boron atoms, greatly enhancing the corrosion resistance of silicon oxide.
  • the annealing temperature is 800° C. to 950° C., preferably 850° C. to 920° C.; the annealing time is 15 min to 60 min, preferably 45 min.
  • Step S4 patterning the back side of the silicon wafer substrate 1 to remove part of the phosphorus-boron co-doped silicon oxide layer 4, forming a patterned region 5 free of the phosphorus-boron co-doped silicon oxide layer 4.
  • the back side structure of the silicon wafer substrate 1 after patterning is shown in FIG3 .
  • the back side of the silicon wafer substrate 1 is patterned using green light or ultraviolet laser to remove the phosphorus-boron co-doped silicon oxide layer 4 in a part of the back side of the silicon wafer substrate 1, thereby forming a patterned area 5, so that the p/n region of the solar cell is partially spatially isolated.
  • the width of the patterned area 5 is 300 ⁇ m to 500 ⁇ m.
  • the above-mentioned patterned area 5 and the front side of the silicon wafer substrate 1 are area A, which needs to be processed.
  • the back of the silicon wafer substrate 1 is provided with a phosphorus-boron co-doped silicon oxide layer 4 after the patterning process, and the area B is the surface protected by the phosphorus-boron co-doped silicon oxide layer 4 mask, which does not need to be processed by texturing/etching.
  • Step S5 texturing the front side of the silicon wafer substrate 1 and etching the patterned area 5 on the back side of the silicon wafer substrate 1.
  • the silicon wafer substrate 1 after texturing and etching is shown in FIG4 .
  • a solution containing KOH or NaOH and a texturing additive are used to process the silicon wafer substrate 1 at a temperature of 70°C to 85°C, so that the front side of the silicon wafer substrate 1 is texturized to form a texturing structure, and at the same time, the patterned area 5 on the back side of the silicon wafer substrate 1 is etched to remove the residual polysilicon in the patterned area 5, thereby exposing the back side of the silicon wafer substrate 1 in the patterned area 5.
  • the phosphorus-boron co-doped silicon oxide layer 4 covering the area B can be removed by using a solution containing HF. After the phosphorus-boron co-doped silicon oxide layer 4 is removed, the silicon wafer substrate 1 is cleaned.
  • Step S6 depositing a first aluminum oxide film layer 6 and a second aluminum oxide film layer 7 on the front side and the back side of the silicon wafer substrate 1 respectively.
  • an ALD (Atomic layer deposition) device is used to simultaneously coat the front and back sides of the silicon wafer substrate 1 in a single-insert manner, thereby forming a first aluminum oxide film layer 6 on the front side of the silicon wafer substrate 1 and a second aluminum oxide film layer 7 on the back side of the silicon wafer substrate 1.
  • the first aluminum oxide film layer 6 and the second aluminum oxide film layer 7 play a passivation role.
  • the thickness of the first aluminum oxide film layer 6 is 2nm to 25nm, and the thickness of the second aluminum oxide film layer 7 is 2 ⁇ m to 25 ⁇ m.
  • Step S7 depositing a first anti-reflection film layer 8 and a second anti-reflection film layer 9 on the first aluminum oxide film layer 6 and the second aluminum oxide film layer 7 respectively.
  • a first anti-reflection film layer 8 is deposited on the first aluminum oxide film layer 6 on the front side of the silicon wafer substrate 1 by using the PECVD method
  • a second anti-reflection film layer 9 is deposited on the second aluminum oxide film layer 7 on the back side of the silicon wafer substrate 1 by using the PECVD method.
  • the first anti-reflection film layer 8 and the second anti-reflection film layer 9 are independently one or more of silicon nitride, silicon oxynitride, and silicon oxide.
  • the thickness of the first anti-reflection film layer 8 is 60nm to 150nm
  • the thickness of the second anti-reflection film layer 9 is 100nm to 200nm.
  • the thickness is 50nm ⁇ 150nm.
  • Step S8 Use laser to perform patterning and opening in the patterned area 5 on the back side of the silicon wafer substrate 1 to form an electrode contact area 10.
  • the back side of the silicon wafer substrate 1 after patterning and opening is shown in FIG5 .
  • a laser is used to perform patterned openings in the patterned area 5 according to a predetermined pattern, and the second aluminum oxide film layer 7 and the second anti-reflection film layer 9 in the opening area are removed, thereby forming an electrode contact area 10 of the p-type region.
  • the shape of the opening area may be a dotted line or a dotted distribution, and the width of the opening is 30 ⁇ m to 50 ⁇ m.
  • Step S9 forming a first electrode 11 in the electrode contact area 10 , and forming a second electrode 12 in an area other than the patterned area 5 on the back side of the silicon wafer substrate 1 .
  • an electrode paste layer containing a conductive component is printed in the electrode contact area 10 by screen printing to form a first electrode 11, and the first electrode 11 is in contact with the silicon wafer substrate 1; a burn-through electrode paste layer containing a conductive component is printed on the back side of the silicon wafer substrate 1 except for the patterned area 5 (i.e., the area where the phosphorus-doped polysilicon layer is provided) by screen printing to form a second electrode 12, and the burn-through effect of the electrode paste is utilized to make the second electrode 12 in contact with the phosphorus-doped polysilicon layer.
  • the patterned area 5 i.e., the area where the phosphorus-doped polysilicon layer is provided
  • the width of the first electrode 11 is 50 ⁇ m to 200 ⁇ m; the width of the second electrode 12 is 10 ⁇ m to 50 ⁇ m.
  • the preparation method of the solar cell of the present application deposits a phosphorus-doped amorphous silicon film layer and a boron-doped silicon oxide layer on the back side of a silicon wafer substrate 1, and anneals the silicon wafer substrate 1, so that a portion of the phosphorus in the phosphorus-doped polycrystalline silicon film layer 2-2 is absorbed by the boron-doped silicon oxide layer, and forms a phosphorus-boron co-doped silicon oxide layer 4 with boron atoms, thereby greatly enhancing the corrosion resistance of silicon oxide; using the phosphorus-boron co-doped silicon oxide layer 4 as a mask layer can greatly extend the process time window of the subsequent texturing/etching steps, thereby improving the cell yield.
  • An embodiment of the present application provides another method for preparing a back-contact solar cell 100 .
  • the steps of the preparation method are basically the same as those of the preparation method of the above embodiment, except that the specific method for forming the phosphorus-boron co-doped silicon oxide layer 4 is different.
  • a phosphorus-doped amorphous silicon film layer is first formed on the back side of the silicon wafer substrate 1; a phosphorus-doped amorphous silicon film layer is first formed on the back side of the silicon wafer substrate 1 by LPCVD (Low Pressure Chemical Vapor Deposition)
  • a phosphorus-doped silicon oxide layer is formed on the surface of the phosphorus-doped amorphous silicon film layer facing away from the silicon wafer substrate 1; boron is diffused on the surface of the phosphorus-doped silicon oxide layer to form a phosphorus-boron co-doped silicon oxide layer 4.
  • the phosphorus-boron co-doped silicon oxide layer 4 formed by this embodiment also has good corrosion resistance, can also extend the processing time window, and improve the battery yield.
  • the preparation method of the phosphorus-boron co-doped silicon oxide layer 4 is not limited to the above two methods. In addition to the above two methods, any preparation method that can form a phosphorus-boron co-doped silicon oxide layer 4 with good corrosion resistance is acceptable.
  • An embodiment of the present application provides a method for removing a wrap-around coating on a solar cell substrate.
  • the solar cell substrate is a silicon wafer substrate 1 having a wrap-around layer on the front side; region A of the solar cell substrate is the front side of the solar cell substrate; and region B of the solar cell substrate is the back side of the solar cell substrate.
  • a phosphorus-boron co-doped silicon oxide layer 4 is firstly provided on region B of the solar cell substrate as a mask layer, and then the solar cell is subjected to a wrap-around treatment using an acid or alkaline solution to remove the wrap-around layer on the front side of the solar cell substrate.
  • the phosphorus-boron co-doped silicon oxide layer 4 on region B can play a blocking role and provide a longer time window for the wrap-around process, thereby improving the cell yield.
  • the solar cell substrate is a silicon wafer substrate 1
  • a coating layer is deposited on the back side of the silicon wafer substrate 1 and the coating layer is coated around the front side of the silicon wafer substrate 1 .
  • the back contact solar cell 100 comprises a p-type silicon wafer substrate 1, a first aluminum oxide film layer 6 is provided on the front side of the silicon wafer substrate 1 (i.e., the upper surface of the silicon wafer substrate 1 in the figure), and a first anti-reflection film layer 8 is provided on the first aluminum oxide film layer 6.
  • the thickness of the first aluminum oxide film layer 6 is 2nm to 25nm
  • the thickness of the first anti-reflection film layer 8 is 60nm to 150nm
  • the first anti-reflection film layer 8 is one or a combination of silicon nitride, silicon oxynitride, and silicon oxide.
  • n-type doped region composed of an ultra-thin silicon oxide layer 2-1 and a phosphorus-doped polysilicon film layer 2-2 arranged in sequence.
  • a p-type region is formed on the back side of the silicon wafer substrate 1 except for the n-type doped region.
  • the thickness of the ultra-thin silicon oxide layer 2-1 is 0.5nm to 3nm
  • the thickness of the phosphorus-doped polysilicon film layer 2-2 is 30nm to 300nm
  • the width of the n-type doped region is 600 ⁇ m to 1200 ⁇ m
  • the p-type region is 100 ⁇ m to 150 ⁇ m.
  • the width of the molded area is 300 ⁇ m to 500 ⁇ m.
  • a second aluminum oxide film layer 7 is also provided on the back side of the silicon wafer substrate 1 on the n-type doping region and the p-type region, and a second anti-reflection film layer 9 is provided on the second aluminum oxide film layer 7.
  • the thickness of the second aluminum oxide film layer 7 is 2 ⁇ m to 25 ⁇ m
  • the thickness of the second anti-reflection film layer 9 is 50 nm to 150 nm
  • the second anti-reflection film layer 9 is a composite film layer of one or more of silicon nitride, silicon oxynitride, and silicon oxide.
  • a first electrode 11 is arranged in the p-type region, and the first electrode 11 passes through the second aluminum oxide film layer 7 and the second anti-reflection film layer 9 to contact the silicon wafer substrate 1; a second electrode 12 is arranged on the back of the silicon wafer substrate 1 in the range corresponding to the n-type doping region, and the second electrode 12 passes through the second aluminum oxide film layer 7 and the second anti-reflection film layer 9 to contact the phosphorus-doped polysilicon film layer 2-2.
  • the first electrode 11 is an aluminum grid line electrode, and the width of the first electrode 11 is 50 ⁇ m to 200 ⁇ m; the second electrode 12 is a silver grid line electrode, and the width of the second electrode 12 is 10 ⁇ m to 50 ⁇ m.

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  • Photovoltaic Devices (AREA)

Abstract

本申请提供了一种太阳电池及其制备方法，太阳电池的制备方法包括如下步骤：提供太阳电池基片，太阳电池基片包括需要进行第一处理的区域A和无需进行第一处理的区域B；在区域B上形成磷硼共掺杂氧化硅层；对区域A进行第一处理；其中，第一处理包括制绒处理、刻蚀处理和去绕镀处理中的一种或多种。该太阳电池的制备方法通过在太阳电池基片不需要进行第一处理的区域B上形成磷硼共掺杂氧化硅层作为掩膜层，在对太阳电池基片的区域A进行第一处理时，该磷硼共掺杂氧化硅层可以对区域B起到良好的阻挡作用，从而为区域A的第一处理工序提供足够长的时间窗口，有利于提高太阳电池的良率。

Description

太阳电池及其制备方法
本申请要求于2022年09月29日提交中国专利局、申请号为2022111996364、发明名称为“太阳电池及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及太阳电池技术领域，特别是涉及一种太阳电池及其制备方法。
背景技术
在制备晶硅太阳电池如PERC电池(Passivated Emitter and Rear Cell)、TOPCon电池(Tunnel Oxide Passivated Contact solar cell)、IBC电池(Interdigitated Back Contact)时，通常采用多道工序形成复杂的电池结构以提高太阳电池的转换效率。
然而，由于设备以及现有工艺本身的局限性，通常很难一步得到需要的电池结构。如在一些电池设计中，电池正面需要制备成绒面，而背面则是抛光结构。常规的做法是先在湿法槽全部抛光，然后通过设计一种掩膜层在电池背面作为阻挡层，再进入湿法槽实现正面绒面，背面抛光的结构。在一些背接触电池中，背面需要进行沟槽或图形化设计，同样也需要用到掩膜结构。此外，在一些太阳电池的制备过程中在硅片背面沉积膜层时会在硅片的正面形成绕镀层，同样需要在背面设置掩膜层再将正面的绕镀层去除。
传统的太阳电池生产工艺中所采用的掩膜层存在耐腐蚀性能不够的问题，导致制绒或去绕镀等处理的时间窗口较短，影响电池的良率。
发明内容
基于此，有必要提供一种掩膜层耐腐蚀性较好、能够延长制绒或去绕镀等处理时间窗口、提高电池良率的太阳电池及其制备方法。
根据本申请的第一方面，提供了一种太阳电池的制备方法，包括如下步骤：
提供太阳电池基片，所述太阳电池基片包括需要进行第一处理的区域A和无需进行所述第一处理的区域B；
在所述区域B上形成磷硼共掺杂氧化硅层；以及
对所述区域A进行所述第一处理；
其中，所述第一处理包括制绒处理、刻蚀处理和去绕镀处理中的一种或多种。
在任意的实施方式中，所述太阳电池基片为硅片衬底，所述区域A包括所述硅片衬底正面以及所述硅片衬底背面的部分区域，所述区域B为所述硅片衬底背面不属于所述区域A的部分；所述第一处理包括利用制绒药液对所述硅片衬底正面的所述区域A进行制绒处理，并对所述硅片衬底背面的所述区域A进行刻蚀处理。
在任意的实施方式中，在所述区域B上形成磷硼共掺杂氧化硅层，包括如下步骤：
在所述硅片衬底背面形成磷硼共掺杂氧化硅层；以及
对所述硅片衬底背面进行图形化处理，以去除部分的所述磷硼共掺杂氧化硅层；其中，剩余的所述磷硼共掺杂氧化硅层所对应的硅片衬底背面区域即为所述区域B。
在任意的实施方式中，在所述硅片衬底背面形成磷硼共掺杂氧化硅层，包括如下步骤：
在所述硅片衬底背面依次形成磷掺杂非晶硅膜层和硼掺杂氧化硅层；以及
对所述硅片衬底进行退火处理，以使所述磷掺杂非晶硅膜层转化为磷掺杂多晶硅膜层，并使所述硼掺杂氧化硅层吸收磷元素形成所述磷硼共掺杂氧化硅层。
在任意的实施方式中，通过等离子体增强化学气相沉积法在所述硅片衬底背面依次形成所述磷掺杂非晶硅膜层和所述硼掺杂氧化硅层。
在任意的实施方式中，形成所述磷掺杂非晶硅膜层，包括如下步骤：
采用含有磷烷和硅烷的反应气体，通过等离子体增强化学气相沉积法在所述硅片衬底背面沉积所述磷掺杂非晶硅膜层，且在沉积所述磷掺杂非 晶硅膜层过程中使所述反应气体中磷烷的流量逐渐增大。
在任意的实施方式中，形成所述硼掺杂氧化硅层，包括如下步骤：
采用含有硼源和硅烷的反应气体，通过等离子体增强化学气相沉积法在所述硅片衬底背面沉积所述硼掺杂氧化硅层，且在沉积所述硼掺杂氧化硅层过程中使所述反应气体中硼源流量低于硅烷流量的1/3。
在任意的实施方式中，所述退火处理的温度为800℃～950℃，所述退火处理的时间为15min～60min。
在任意的实施方式中，在所述硅片衬底背面形成磷硼共掺杂氧化硅层，包括如下步骤：
通过低压化学气相沉积法在所述硅片衬底背面形成磷掺杂氧化硅层；以及
在所述磷掺杂氧化硅层的表面进行硼扩散，形成所述磷硼共掺杂氧化硅层。
在任意的实施方式中，所述图形化处理，包括如下步骤：
采用绿光激光或紫外激光对所述硅片衬底背面进行处理，以去除部分的所述磷硼共掺杂氧化硅层。
在任意的实施方式中，在所述硅片衬底背面形成所述磷掺杂非晶硅膜层之前，所述制备方法还包括如下步骤：
通过等离子体增强化学气相沉积法在所述硅片衬底背面形成超薄氧化硅层，所述超薄氧化硅层的厚度为1nm～3nm。
在任意的实施方式中，在对所述区域A进行所述第一处理之后，所述制备方法还包括如下步骤：
采用含有HF的溶液去除所述区域B上的所述磷硼共掺杂氧化硅层；以及
在所述硅片衬底背面的所述区域A上制备第一电极，在所述硅片衬底背面的所述区域B上制备第二电极。
在任意的实施方式中，在去除所述区域B上的所述磷硼共掺杂氧化硅层之后，且在制备所述第一电极和所述第二电极之前，所述制备方法还包括在所述硅片衬底正面和背面分别沉积第一氧化铝膜层和第二氧化铝膜层的 步骤。
在任意的实施方式中，在沉积所述第一氧化铝膜层和所述第二氧化铝膜层之后，且在制备所述第一电极和所述第二电极之前，所述制备方法还包括在所述第一氧化铝膜层和所述第二氧化铝膜层上分别沉积第一减反射膜层和第二减反射膜层的步骤。
在任意的实施方式中，所述太阳电池基片为正面具有绕镀层的硅片衬底；所述区域A包括所述硅片衬底的正面，所述区域B包括所述硅片衬底的背面；所述第一处理为对所述区域A进行去绕镀处理。
在任意的实施方式中，在所述区域B上形成磷硼共掺杂氧化硅层，包括如下步骤：
在所述硅片衬底背面依次形成磷掺杂非晶硅膜层和硼掺杂氧化硅层；以及
对所述硅片衬底进行退火处理，以使所述磷掺杂非晶硅膜层转化为磷掺杂多晶硅膜层，并使所述硼掺杂氧化硅层吸收磷元素形成所述磷硼共掺杂氧化硅层。
在任意的实施方式中，通过等离子体增强化学气相沉积法在所述硅片衬底背面依次形成所述磷掺杂非晶硅膜层和所述硼掺杂氧化硅层。
在任意的实施方式中，形成所述磷掺杂非晶硅膜层，包括如下步骤：
采用含有磷烷和硅烷的反应气体，通过等离子体增强化学气相沉积法在所述硅片衬底背面沉积所述磷掺杂非晶硅膜层，且在沉积所述磷掺杂非晶硅膜层过程中使所述反应气体中磷烷的流量逐渐增大。
在任意的实施方式中，形成所述硼掺杂氧化硅层，包括如下步骤：
采用含有硼源和硅烷的反应气体，通过等离子体增强化学气相沉积法在所述硅片衬底背面沉积所述硼掺杂氧化硅层，且在沉积所述硼掺杂氧化硅层过程中使所述反应气体中硼源流量低于硅烷流量的1/3。
在任意的实施方式中，所述退火处理的温度为800℃～950℃，所述退火处理的时间为15min～60min。
在任意的实施方式中，在所述区域B上形成磷硼共掺杂氧化硅层，包括如下步骤：
通过低压化学气相沉积法在所述硅片衬底背面形成磷掺杂氧化硅层；以及
在所述磷掺杂氧化硅层的表面进行硼扩散，形成所述磷硼共掺杂氧化硅层。
根据本申请的第二方面，提供了一种太阳电池，所述太阳电池通过本申请第一方面的太阳电池的制备方法制备得到。
在任意的实施方式中，太阳电池包括硅片衬底、超薄氧化硅层、磷掺杂多晶硅膜层、第一电极和第二电极；
所述硅片衬底背面具有n型掺杂区和p型区域，所述超薄氧化硅层和所述磷掺杂多晶硅膜层依次层叠设置于所述硅片衬底背面的所述n型掺杂区内；所述第一电极设于所述p型区域内且与所述硅片衬底相接触；所述第二电极设于所述n型掺杂区内且与所述磷掺杂多晶硅膜层相接触。
在任意的实施方式中，太阳电池还包括第一氧化铝膜层、第一减反射膜层、第二氧化铝膜层和第二减反射膜层；
所述第一氧化铝膜层和所述第一减反射膜层依次层叠设置于所述硅片衬底正面；所述第二氧化铝膜层设于所述n型掺杂区内的所述磷掺杂多晶硅膜层背离所述超薄氧化硅层的表面以及所述p型区域内的所述硅片衬底表面；所述第二减反射膜层设于所述第二氧化铝膜层背离所述硅片衬底的表面；所述第一电极穿过所述第二减反射膜层和所述第二氧化铝膜层与所述硅片衬底相接触；所述第二电极穿过所述第二减反射膜层和所述第二氧化铝膜层与所述磷掺杂多晶硅膜层相接触。
通过在太阳电池基片不需要进行第一处理的区域B上形成磷硼共掺杂氧化硅层作为掩膜层，该磷硼共掺杂氧化硅层具有超强的耐腐蚀能力，在对太阳电池基片的区域A进行第一处理时，该磷硼共掺杂氧化硅层可以对区域B起到良好的阻挡作用，从而为区域A的第一处理工序(如制绒、刻蚀、去绕镀等)提供足够长的时间窗口，有利于提高太阳电池的良率。
附图说明
为了更好地描述和说明本申请的实施例和/或示例，可以参考一幅或多 幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的申请、目前描述的实施例和/或示例以及目前理解的这些申请的最佳模式中的任何一者的范围的限制。
图1为本申请一实施例使用的硅片衬底的示意图；
图2为本申请一实施例在硅片衬底上形成磷硼共掺杂氧化硅层后的示意图；
图3为本申请一实施例在硅片衬底背面进行图形化处理后的示意图；
图4为本申请一实施例对硅片衬底正面进行制绒、图形化区域进行刻蚀后的示意图；
图5为本申请一实施例对图形化区域进行图形化开孔后的示意图；
图6为本申请一实施例所制备的太阳电池的结构示意图；
图7为本申请一实施例所制备的太阳电池的背面示意图。
附图标记说明：
1、硅片衬底；2-1、超薄氧化硅层；2-2、磷掺杂多晶硅膜层；4、磷硼
共掺杂氧化硅层；5、图形化区域；6、第一氧化铝膜层；7、第二氧化铝膜层；8、第一减反射膜层；9、第二减反射膜层；10、电极接触区；11、第一电极；12、第二电极；100、背接触太阳电池。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面对本申请的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本申请。但是本申请能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似改进，因此本申请不受下面公开的具体实施例的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
在本申请中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
请参阅图1至图5，本申请一实施方式提供了一种背接触太阳电池100的制备方法，该制备方法包括如下步骤S1至步骤S9：
步骤S1：对硅片衬底1(太阳电池基片)依次进行去损伤处理、抛光处理和清洗处理。硅片衬底1的结构如图1所示。
在其中一个具体示例中，使用含有KOH的溶液在60℃下对硅片衬底1进行去损伤处理；然后使用含有KOH的溶液在75℃下对硅片衬底1进行抛光处理，使抛光后的硅片衬底1的反射率为30％；再使用含有氢氟酸和盐酸的混合溶液对硅片衬底1进行清洗、去离子水清洗和烘干。
在该实施方式中，硅片衬底1具体为p型硅衬底。在其他一些实施方式中，硅片衬底1也可以采用n型硅衬底。
步骤S2：采用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)依次在硅片衬底1的背面沉积形成超薄氧化硅层2-1、磷掺杂非晶硅膜层和硼掺杂氧化硅层。
在其中一些实施例中，在沉积磷掺杂非晶硅膜层时，以磷烷和硅烷作为反应气体，磷烷的流量低于硅烷的流量；且在沉积磷掺杂非晶硅膜层的初始阶段通入低流量的磷烷和高流量的硅烷，在磷掺杂非晶硅膜层沉积到10nm～30nm之后再增大磷烷的流量，沉积过程中硅烷的流量保持不变。由此，可以在靠近硅片衬底1表面的地方形成较小的复合；而在磷掺杂非晶硅膜 层远离硅片衬底1的一侧形成较大的磷浓度，从而能够增强场钝化，并且有利于生成硼磷共掺杂层。
在其中一些实施例中，在沉积硼掺杂氧化硅层时，以硼源和硅烷为反应气体，且控制硼源的流量低于硅烷流量的1/3。通过硼掺杂可以与磷形成硼磷玻璃，来提供较强的耐腐蚀能力。沉积硼掺杂氧化硅层时硼的含量需要控制在较低的水准，以使硼不会大幅进入硅本体中而引起载流子的复合。
在其中一些实施例中，超薄氧化硅层2-1的厚度为0.5nm～3nm，优选为2nm；磷掺杂非晶硅膜层的厚度为30nm～300nm，优选为100nm～150nm；硼掺杂氧化硅层的厚度为10nm～100nm，优选为20nm～50nm。沉积形成上述的超薄氧化硅层2-1、磷掺杂非晶硅膜层和硼掺杂氧化硅层的温度为200℃～500℃，优选为450℃。
步骤S3：对硅片衬底1进行退火处理。退火处理后的硅片衬底1如图2所示。
通过对硅片衬底1进行退火处理，可以使PECVD沉积的非晶硅a-Si向多晶Poly转化，并使晶粒生长变大；同时可以使PECVD生长的疏松的硼掺杂氧化硅层变得致密，增强其耐碱性。退火过程中，沉积的硼掺杂氧化硅层会从磷掺杂多晶硅膜层2-2(磷掺杂非晶硅膜层转化后形成)中吸收一部分磷，并与硼原子形成磷硼共掺杂氧化硅层4，极大地增强氧化硅的耐腐蚀能力。
在其中一些实施例中，上述退火处理的温度为800℃～950℃，优选为850℃～920℃；退火处理的时间为15min～60min，优选为45min。
步骤S4：对硅片衬底1的背面进行图形化处理，以去除部分的所述磷硼共掺杂氧化硅层4，形成不含磷硼共掺杂氧化硅层4的图形化区域5。图形化处理后的硅片衬底1背面结构如图3所示。
在其中一些实施例中，使用绿光或紫外激光对硅片衬底1的背面进行图形化处理，去除掉硅片衬底1背面上部分区域的磷硼共掺杂氧化硅层4，从而形成图形化区域5，使太阳电池的p/n区局部空间隔离。图形化区域5的宽度为300μm～500μm。
上述的图形化区域5和硅片衬底1的正面为区域A，该区域A需要进 行制绒/刻蚀处理；而经过图形化处理之后硅片衬底1背面设有磷硼共掺杂氧化硅层4的区域则为区域B，该区域B为被磷硼共掺杂氧化硅层4掩膜保护的表面，其不需要进行制绒/刻蚀处理。
步骤S5：对硅片衬底1的正面进行制绒处理、对硅片衬底1背面的图形化区域5进行刻蚀处理。制绒和刻蚀处理后的硅片衬底1如图4所示。
在其中一些实施例中，采用含有KOH或者NaOH的溶液并配合制绒添加剂，在70℃～85℃温度下对硅片衬底1进行处理，实现硅片衬底1正面制绒形成绒面结构的同时，对硅片衬底1背面的图形化区域5进行刻蚀处理，去除图形化区域5内残留的多晶硅，从而使图形化区域5内的硅片衬底1背面暴露出来。在制绒/刻蚀处理过程中，由于硅片衬底1的区域B有磷硼共掺杂氧化硅层4的保护，其上的多晶硅层不会被上述制绒药液腐蚀破坏。
在制绒/刻蚀处理完成后，采用含有HF的溶液即可去除掉区域B上覆盖的磷硼共掺杂氧化硅层4，去除磷硼共掺杂氧化硅层4之后，对硅片衬底1进行清洗。
步骤S6：在硅片衬底1的正面和背面分别沉积第一氧化铝膜层6和第二氧化铝膜层7。
在其中一些实施例中，使用ALD(Atomic layer deposition，原子层沉积)设备单插的方式在硅片衬底1的正面和背面同时镀膜，从而在硅片衬底1的正面形成第一氧化铝膜层6，在硅片衬底1的背面形成第二氧化铝膜层7。该第一氧化铝膜层6和第二氧化铝膜层7起到钝化作用。第一氧化铝膜层6的厚度为2nm～25nm，第二氧化铝膜层7的厚度为2μm～25μm。
步骤S7：在第一氧化铝膜层6和第二氧化铝膜层7上分别沉积第一减反射膜层8和第二减反射膜层9。
在其中一些实施例中，利用PECVD法在硅片衬底1正面的第一氧化铝膜层6上沉积第一减反射膜层8，利用PECVD法在硅片衬底1背面的第二氧化铝膜层7上沉积第二减反射膜层9。其中，第一减反射膜层8和第二减反射膜层9各自独立地为氮化硅、氮氧化硅、氧化硅中的一种或几种的组合膜层。第一减反射膜层8的厚度为60nm～150nm，第二减反射膜层9的 厚度为50nm～150nm。
步骤S8：利用激光对硅片衬底1背面的图形化区域5进行图形化开孔，形成电极接触区10。图形化开孔后的硅片衬底1背面如图5所示。
具体地，利用激光按照预定的图案在图形化区域5进行图形化开孔，去除开孔区域内的第二氧化铝膜层7和第二减反射膜层9，从而作为p型区域的电极接触区10。
在其中一些实施例中，开孔区域的形状可以呈虚线型或者点状分布，开孔的宽度为30μm～50μm。
步骤S9：在电极接触区10制作第一电极11，并在硅片衬底1背面除图形化区域5以外的区域制作第二电极12。
在其中一些实施例中，采用丝网印刷的方式在电极接触区10内印刷包含导电成分的电极浆料层，形成第一电极11，该第一电极11与硅片衬底1相接触；采用丝网印刷的方式在硅片衬底1背面除图形化区域5以外的区域(即设有磷掺杂多晶硅层的区域)印刷包含导电成分的烧穿型的电极浆料层，形成第二电极12，并利用电极浆料的烧穿作用使第二电极12与磷掺杂多晶硅层相接触。
在其中一些实施例中，上述第一电极11的宽度为50μm～200μm；第二电极12的宽度为10μm～50μm。
本申请的太阳电池的制备方法，通过在硅片衬底1的背面沉积磷掺杂非晶硅膜层和硼掺杂氧化硅层，并对硅片衬底1进行退火处理，使磷掺杂多晶硅膜层2-2中的一部分磷被硼掺杂氧化硅层吸收，并与硼原子形成磷硼共掺杂氧化硅层4，极大地增强氧化硅的耐腐蚀能力；采用该磷硼共掺杂氧化硅层4作为掩膜层，可以大大地延长后续制绒/刻蚀步骤的工艺时间窗口，提高电池良率。
本申请一实施方式提供了另一种背接触太阳电池100的制备方法，该制备方法与上述实施方式的制备方法的步骤基本相同，区别在于：形成磷硼共掺杂氧化硅层4的具体方法不同。
在本实施方式中，先在硅片衬底1的背面形成磷掺杂非晶硅膜层；通过LPCVD(Low Pressure Chemical Vapor Deposition，低压化学气相沉积法) 在磷掺杂非晶硅膜层背离硅片衬底1的表面形成磷掺杂氧化硅层；在磷掺杂氧化硅层的表面进行硼扩散，形成磷硼共掺杂氧化硅层4。采用本实施方式形成的磷硼共掺杂氧化硅层4同样具有良好的耐腐蚀能力，同样能够延长处理工艺时间窗口，提高电池良率。
可以理解，磷硼共掺杂氧化硅层4的制备方法并不限于上述两种方式，除上述两种方式以外，只要能够形成耐腐蚀性能良好的磷硼共掺杂氧化硅层4的制备方法均是可以的。
本申请一实施方式提供了一种去除太阳电池基片上的绕镀层的方法。
在其中一些实施例中，太阳电池基片为正面具有绕镀层的硅片衬底1；太阳电池基片的区域A为该太阳电池基片的正面；太阳电池基片的区域B为该太阳电池基片的背面。在去除该太阳电池基片正面的绕镀层时，先在太阳电池基片的区域B上设置磷硼共掺杂氧化硅层4作为掩膜层，然后利用酸或碱溶液对太阳电池进行去绕镀处理，去除太阳电池基片正面的绕镀层。在去绕镀处理过程中，区域B上的磷硼共掺杂氧化硅层4可以起到阻挡作用，并为去绕镀工艺提供较长的时间窗口，从而提高电池良率。
在其中一些实施例中，该太阳电池基片为硅片衬底1，在该硅片衬底1的背面沉积有镀层且该镀层绕镀到硅片衬底1的正面。
下面结合附图，对本申请制备的背接触太阳电池100的结构进行说明。
如图6和图7所示，该背接触太阳电池100包括p型的硅片衬底1，在硅片衬底1的正面(即图中硅片衬底1的上表面)设有第一氧化铝膜层6，在该第一氧化铝膜层6上设有第一减反射膜层8。第一氧化铝膜层6的厚度为2nm～25nm，第一减反射膜层8的厚度为60nm～150nm，第一减反射膜层8为氮化硅、氮氧化硅、氧化硅中的一种或几种的组合膜层。
在硅片衬底1的背面(即图中硅片衬底1的下表面)设有由依次设置的超薄氧化硅层2-1和磷掺杂多晶硅膜层2-2组成的n型掺杂区。在硅片衬底1的背面除该n型掺杂区以外的部分形成p型区域，在该p型区域内没有超薄氧化硅层2-1和磷掺杂多晶硅膜层2-2，且n型掺杂区与p型区域交错排列。其中，超薄氧化硅层2-1的厚度为0.5nm～3nm，磷掺杂多晶硅膜层2-2的厚度为30nm～300nm，n型掺杂区的宽度为600μm～1200μm，p 型区域的宽度为300μm～500μm。
在硅片衬底1的背面于n型掺杂区和p型区域上还设有第二氧化铝膜层7，在该第二氧化铝膜层7上设有第二减反射膜层9。其中，第二氧化铝膜层7的厚度为2μm～25μm，第二减反射膜层9的厚度为50nm～150nm，第二减反射膜层9为氮化硅、氮氧化硅、氧化硅中的一种或几种的组合膜层。
在p型区域内设置有第一电极11，该第一电极11穿过第二氧化铝膜层7和第二减反射膜层9与硅片衬底1相接触；在硅片衬底1背面对应于n型掺杂区范围内设置有第二电极12，该第二电极12穿过第二氧化铝膜层7和第二减反射膜层9与磷掺杂多晶硅膜层2-2相接触。其中，第一电极11为铝栅线电极，第一电极11的宽度为50μm～200μm；第二电极12为银栅线电极，第二电极12的宽度为10μm～50μm。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准，说明书及附图可以用于解释权利要求的内容。

Claims (24)

  1. 一种太阳电池的制备方法，其特征在于，包括如下步骤：
    提供太阳电池基片，所述太阳电池基片包括需要进行第一处理的区域A和无需进行所述第一处理的区域B；
    在所述区域B上形成磷硼共掺杂氧化硅层；以及
    对所述区域A进行所述第一处理；
    其中，所述第一处理包括制绒处理、刻蚀处理和去绕镀处理中的一种或多种。
  2. 根据权利要求1所述的太阳电池的制备方法，其特征在于，所述太阳电池基片为硅片衬底，所述区域A包括所述硅片衬底正面以及所述硅片衬底背面的部分区域，所述区域B为所述硅片衬底背面不属于所述区域A的部分；所述第一处理包括利用制绒药液对所述硅片衬底正面的所述区域A进行制绒处理，并对所述硅片衬底背面的所述区域A进行刻蚀处理。
  3. 根据权利要求2所述的太阳电池的制备方法，其特征在于，在所述区域B上形成磷硼共掺杂氧化硅层，包括如下步骤：
    在所述硅片衬底背面形成磷硼共掺杂氧化硅层；以及
    对所述硅片衬底背面进行图形化处理，以去除部分的所述磷硼共掺杂氧化硅层；其中，剩余的所述磷硼共掺杂氧化硅层所对应的硅片衬底背面区域即为所述区域B。
  4. 根据权利要求3所述的太阳电池的制备方法，其特征在于，在所述硅片衬底背面形成磷硼共掺杂氧化硅层，包括如下步骤：
    在所述硅片衬底背面依次形成磷掺杂非晶硅膜层和硼掺杂氧化硅层；以及
    对所述硅片衬底进行退火处理，以使所述磷掺杂非晶硅膜层转化为磷掺杂多晶硅膜层，并使所述硼掺杂氧化硅层吸收磷元素形成所述磷硼共掺杂氧化硅层。
  5. 根据权利要求4所述的太阳电池的制备方法，其特征在于，通过等离子体增强化学气相沉积法在所述硅片衬底背面依次形成所述磷掺杂非晶硅 膜层和所述硼掺杂氧化硅层。
  6. 根据权利要求4或5所述的太阳电池的制备方法，其特征在于，形成所述磷掺杂非晶硅膜层，包括如下步骤：
    采用含有磷烷和硅烷的反应气体，通过等离子体增强化学气相沉积法在所述硅片衬底背面沉积所述磷掺杂非晶硅膜层，且在沉积所述磷掺杂非晶硅膜层过程中使所述反应气体中磷烷的流量逐渐增大。
  7. 根据权利要求4至6中任一项所述的太阳电池的制备方法，其特征在于，形成所述硼掺杂氧化硅层，包括如下步骤：
    采用含有硼源和硅烷的反应气体，通过等离子体增强化学气相沉积法在所述硅片衬底背面沉积所述硼掺杂氧化硅层，且在沉积所述硼掺杂氧化硅层过程中使所述反应气体中硼源流量低于硅烷流量的1/3。
  8. 根据权利要求4至7中任一项所述的太阳电池的制备方法，其特征在于，所述退火处理的温度为800℃～950℃，所述退火处理的时间为15min～60min。
  9. 根据权利要求3所述的太阳电池的制备方法，其特征在于，在所述硅片衬底背面形成磷硼共掺杂氧化硅层，包括如下步骤：
    通过低压化学气相沉积法在所述硅片衬底背面形成磷掺杂氧化硅层；以及
    在所述磷掺杂氧化硅层的表面进行硼扩散，形成所述磷硼共掺杂氧化硅层。
  10. 根据权利要求3至9中任一项所述的太阳电池的制备方法，其特征在于，所述图形化处理，包括如下步骤：
    采用绿光激光或紫外激光对所述硅片衬底背面进行处理，以去除部分的所述磷硼共掺杂氧化硅层。
  11. 根据权利要求4至8中任一项所述的太阳电池的制备方法，其特征在于，在所述硅片衬底背面形成所述磷掺杂非晶硅膜层之前，所述制备方法还包括如下步骤：
    通过等离子体增强化学气相沉积法在所述硅片衬底背面形成超薄氧化硅层，所述超薄氧化硅层的厚度为1nm～3nm。
  12. 根据权利要求2至11中任一项所述的太阳电池的制备方法，其特征在于，在对所述区域A进行所述第一处理之后，所述制备方法还包括如下步骤：
    采用含有HF的溶液去除所述区域B上的所述磷硼共掺杂氧化硅层；以及
    在所述硅片衬底背面的所述区域A上制备第一电极，在所述硅片衬底背面的所述区域B上制备第二电极。
  13. 根据权利要求12所述的太阳电池的制备方法，其特征在于，在去除所述区域B上的所述磷硼共掺杂氧化硅层之后，且在制备所述第一电极和所述第二电极之前，所述制备方法还包括在所述硅片衬底正面和背面分别沉积第一氧化铝膜层和第二氧化铝膜层的步骤。
  14. 根据权利要求13所述的太阳电池的制备方法，其特征在于，在沉积所述第一氧化铝膜层和所述第二氧化铝膜层之后，且在制备所述第一电极和所述第二电极之前，所述制备方法还包括在所述第一氧化铝膜层和所述第二氧化铝膜层上分别沉积第一减反射膜层和第二减反射膜层的步骤。
  15. 根据权利要求1所述的太阳电池的制备方法，其特征在于，所述太阳电池基片为正面具有绕镀层的硅片衬底；所述区域A包括所述硅片衬底的正面，所述区域B包括所述硅片衬底的背面；所述第一处理为对所述区域A进行去绕镀处理。
  16. 根据权利要求15所述的太阳电池的制备方法，其特征在于，在所述区域B上形成磷硼共掺杂氧化硅层，包括如下步骤：
    在所述硅片衬底背面依次形成磷掺杂非晶硅膜层和硼掺杂氧化硅层；以及
    对所述硅片衬底进行退火处理，以使所述磷掺杂非晶硅膜层转化为磷掺杂多晶硅膜层，并使所述硼掺杂氧化硅层吸收磷元素形成所述磷硼共掺杂氧化硅层。
  17. 根据权利要求16所述的太阳电池的制备方法，其特征在于，通过等离子体增强化学气相沉积法在所述硅片衬底背面依次形成所述磷掺杂非晶硅膜层和所述硼掺杂氧化硅层。
  18. 根据权利要求16或17所述的太阳电池的制备方法，其特征在于，形成所述磷掺杂非晶硅膜层，包括如下步骤：
    采用含有磷烷和硅烷的反应气体，通过等离子体增强化学气相沉积法在所述硅片衬底背面沉积所述磷掺杂非晶硅膜层，且在沉积所述磷掺杂非晶硅膜层过程中使所述反应气体中磷烷的流量逐渐增大。
  19. 根据权利要求16至18中任一项所述的太阳电池的制备方法，其特征在于，形成所述硼掺杂氧化硅层，包括如下步骤：
    采用含有硼源和硅烷的反应气体，通过等离子体增强化学气相沉积法在所述硅片衬底背面沉积所述硼掺杂氧化硅层，且在沉积所述硼掺杂氧化硅层过程中使所述反应气体中硼源流量低于硅烷流量的1/3。
  20. 根据权利要求16至19中任一项所述的太阳电池的制备方法，其特征在于，所述退火处理的温度为800℃～950℃，所述退火处理的时间为15min～60min。
  21. 根据权利要求15所述的太阳电池的制备方法，其特征在于，在所述区域B上形成磷硼共掺杂氧化硅层，包括如下步骤：
    通过低压化学气相沉积法在所述硅片衬底背面形成磷掺杂氧化硅层；以及
    在所述磷掺杂氧化硅层的表面进行硼扩散，形成所述磷硼共掺杂氧化硅层。
  22. 一种太阳电池，其特征在于，所述太阳电池通过权利要求1至14中任一项所述的制备方法制备得到。
  23. 根据权利要求22所述的太阳电池，其特征在于，所述太阳电池包括硅片衬底、超薄氧化硅层、磷掺杂多晶硅膜层、第一电极和第二电极；
    所述硅片衬底背面具有n型掺杂区和p型区域，所述超薄氧化硅层和所述磷掺杂多晶硅膜层依次层叠设置于所述硅片衬底背面的所述n型掺杂区内；所述第一电极设于所述p型区域内且与所述硅片衬底相接触；所述第二电极设于所述n型掺杂区内且与所述磷掺杂多晶硅膜层相接触。
  24. 根据权利要求23所述的太阳电池，其特征在于，所述太阳电池还包括第一氧化铝膜层、第一减反射膜层、第二氧化铝膜层和第二减反射膜层；
    所述第一氧化铝膜层和所述第一减反射膜层依次层叠设置于所述硅片衬底正面；所述第二氧化铝膜层设于所述n型掺杂区内的所述磷掺杂多晶硅膜层背离所述超薄氧化硅层的表面以及所述p型区域内的所述硅片衬底表面；所述第二减反射膜层设于所述第二氧化铝膜层背离所述硅片衬底的表面；所述第一电极穿过所述第二减反射膜层和所述第二氧化铝膜层与所述硅片衬底相接触；所述第二电极穿过所述第二减反射膜层和所述第二氧化铝膜层与所述磷掺杂多晶硅膜层相接触。
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