WO2024073903A1 - 控制电路、控制方法以及半导体存储器 - Google Patents

控制电路、控制方法以及半导体存储器 Download PDF

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Publication number
WO2024073903A1
WO2024073903A1 PCT/CN2022/126383 CN2022126383W WO2024073903A1 WO 2024073903 A1 WO2024073903 A1 WO 2024073903A1 CN 2022126383 W CN2022126383 W CN 2022126383W WO 2024073903 A1 WO2024073903 A1 WO 2024073903A1
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Prior art keywords
signal
module
ecs
counting
command
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English (en)
French (fr)
Inventor
黄泽群
孙凯
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CXMT Corp
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CXMT Corp
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Priority to EP22961260.1A priority Critical patent/EP4498372A4/en
Publication of WO2024073903A1 publication Critical patent/WO2024073903A1/zh
Priority to US18/945,561 priority patent/US12613773B2/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4062—Parity or ECC in refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G11C29/16—Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the technical field of integrated circuits, and in particular to a control circuit, a control method, and a semiconductor memory.
  • DDR double data rate
  • ECS Error Check and Scrub
  • DRAM Dynamic Random Access Memory
  • ECS Error Check and Scrub
  • MPC Multi-Purpose Command
  • automatic ECS operation does not have an MPC command, but requires the use of Refresh and Self-Refresh commands to generate ECS commands in order to detect erroneous information and perform internal read and write error detection and repair at the same time.
  • the Self-Refresh command lacks an external clock, resulting in the inability to accurately count through refresh commands such as Refresh and Self-Refresh, which may cause errors in the generation of ECS commands and affect the performance of the memory.
  • Embodiments of the present disclosure provide a control circuit, a control method, and a semiconductor memory.
  • an embodiment of the present disclosure provides a control circuit, the control circuit comprising a timing control module and a command control module, wherein an output end of the timing control module is connected to an input end of the command control module, wherein:
  • the timing control module is configured to receive the first clock signal, count according to the first clock signal, generate an error check and clear ECS identification signal, and send the ECS identification signal to the command control module; wherein, when the count value meets a preset condition, the ECS identification signal is in a valid state;
  • the command control module is configured to receive the ECS identification signal, and when the ECS identification signal is in a valid state, obtain the refresh command signal, and generate the ECS command signal according to the refresh command signal.
  • the timing control module is further configured to stop counting when the ECS identification signal is in a valid state
  • the command control module is further configured to generate a reset signal after generating an ECS command signal according to a refresh command signal, and send the reset signal to the timing control module.
  • the timing control module restarts counting and controls the ECS identification signal to be in an invalid state.
  • the command control module is further configured to output the received refresh command signal as an internal refresh signal when the ECS identification signal is in an invalid state.
  • the timing control module includes a counting module and a decoding module, and the output end of the counting module is connected to the input end of the decoding module, wherein:
  • a counting module configured to receive a first clock signal, count according to the first clock signal, and generate a counting signal, wherein the counting signal is used to represent a counting value
  • the decoding module is configured to receive the counting signal, decode the counting signal, and obtain a target counting signal; wherein, when the counting value meets a preset condition, the target counting signal is put into a valid state.
  • the counting module includes an asynchronous binary counter, wherein: the asynchronous binary counter includes a plurality of triggers cascaded in sequence, the input end of each stage of the trigger is connected to its own second output end, and the second output end of each stage of the trigger is connected to the clock end of the next stage of the trigger, and the clock end of the first stage of the trigger is connected to the first clock signal.
  • the counting module includes a synchronous binary counter, wherein: the synchronous binary counter includes a plurality of triggers cascaded in sequence, and clock terminals of the plurality of triggers are all connected to the first clock signal.
  • the timing control module also includes a latch module, and the latch module is connected to the output end of the decoding module, wherein: the latch module is configured to receive a target counting signal, and when the target counting signal is in a valid state, latch the target counting signal to generate an ECS identification signal in a valid state.
  • the timing control module further includes an automatic pulse module and a latch module, and the input end of the automatic pulse module is connected to the output end of the decoding module, and the output end of the automatic pulse module is connected to the set end of the latch module, wherein:
  • An automatic pulse module is configured to generate a set signal according to a target count signal; wherein when the target count signal is in a valid state, the set signal is in a valid state;
  • the latch module is configured to receive a set signal and, when the set signal is in a valid state, generate an ECS identification signal in a valid state according to the set signal.
  • the automatic pulse module includes a delayed inverting module and a first AND gate, and the first input end of the first AND gate and the input end of the delayed inverting module are both connected to the output end of the decoding module, the second input end of the first AND gate is connected to the output end of the delayed inverting module, and the output end of the first AND gate is connected to the set end of the latch module as the output end of the automatic pulse module, wherein:
  • a delay inversion module is configured to delay and invert the target counting signal to obtain a target counting inversion signal
  • the first AND gate is used to perform an AND logic operation on the target count inversion signal and the target count signal to obtain a set signal.
  • the command control module includes a sampling module, a first delay module and a logic processing module, wherein:
  • a sampling module is configured to receive a refresh command signal and an ECS identification signal, and perform sampling processing on the ECS identification signal according to the refresh command signal to obtain a sampling signal;
  • a first delay module is configured to delay the refresh command signal to obtain a delayed refresh signal
  • the logic processing module is configured to perform logic operations on the sampling signal and the delayed refresh signal, and when the sampling signal is in a valid state, select to output an ECS command signal for performing an ECS operation; and when the sampling signal is in an invalid state, select to output an internal refresh signal for performing a refresh operation; wherein, when the ECS identification signal is in a valid state, the sampling signal is in a valid state; when the ECS identification signal is in an invalid state, the sampling signal is in an invalid state.
  • the logic processing module includes a first logic module and a second logic module, wherein:
  • a first logic module is configured to perform a first logic operation on the sampling signal and the delayed refresh signal when the sampling signal is in a valid state, and output an ECS command signal;
  • the second logic module is configured to perform a second logic operation on the sampling signal and the delayed refresh signal when the sampling signal is in an invalid state, and output an internal refresh signal.
  • the first logic module includes a first NAND gate and a first NOT gate, and the first input end of the first NAND gate is connected to the output end of the sampling module, the second input end of the first NAND gate is connected to the output end of the first delay module, and the output end of the first NAND gate is connected to the input end of the first NOT gate, wherein:
  • a first NAND gate used for performing a NAND logic operation on the sampling signal and the delayed refresh signal when the sampling signal is in a valid state, to obtain a first intermediate signal
  • the first NOT gate is used to perform a NOT logic operation on the first intermediate signal to obtain an ECS command signal.
  • the second logic module includes a second NAND gate, a second NOT gate, and a third NOT gate, and the first input terminal of the second NAND gate is connected to the output terminal of the second NOT gate, the second input terminal of the second NAND gate is connected to the output terminal of the first delay module, and the output terminal of the second NAND gate is connected to the input terminal of the third NOT gate, wherein:
  • the second NOT gate is used to perform a NOT logic operation on the sampling signal when the sampling signal is in an invalid state to obtain a second intermediate signal
  • a second NAND gate is used for performing a NAND logic operation on the second intermediate signal and the delayed refresh signal to obtain a third intermediate signal;
  • the third NOT gate is used for performing a NOT logic operation on the third intermediate signal to obtain an internal refresh signal.
  • the delay time of the first delay module is greater than the sum of the delay times of the sampling module and the second NOT gate.
  • the command control module also includes a second delay module, wherein: the second delay module is configured to delay processing of the ECS command signal, generate a reset signal, and send the reset signal to the reset end of the latch module, so that the counting module restarts counting and controls the ECS identification signal to be in an invalid state.
  • control circuit further includes a clock generating circuit, wherein: the clock generating circuit is used to generate a first clock signal.
  • the clock generation circuit includes an oscillation module and a frequency division module, wherein:
  • An oscillation module configured to output a second clock signal of a preset frequency
  • the frequency division module is configured to perform n-division processing on the second clock signal to obtain a first clock signal; wherein the frequency of the first clock signal is one nth of a preset frequency, and n is an integer greater than zero.
  • the refresh command signal includes at least one of the following: a refresh signal and a self-refresh signal.
  • an embodiment of the present disclosure provides a control method, the method comprising:
  • the first clock signal is received through the timing control module, and counting is performed according to the first clock signal to generate an ECS identification signal, and the ECS identification signal is sent to the command control module; wherein, when the count value meets the preset condition, the ECS identification signal is in a valid state;
  • the ECS identification signal is received through the command control module, and when the ECS identification signal is in a valid state, a refresh command signal is acquired, and an ECS command signal is generated according to the refresh command signal.
  • an embodiment of the present disclosure provides a semiconductor memory, which includes a control circuit as described in any one of the first aspects.
  • the semiconductor memory includes a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the disclosed embodiment provides a control circuit, a control method and a semiconductor memory, wherein the control circuit includes a timing control module and a command control module, and the output end of the timing control module is connected to the input end of the command control module, wherein the timing control module is configured to receive a first clock signal, count according to the first clock signal, generate an ECS identification signal, and send the ECS identification signal to the command control module; wherein when the count value meets a preset condition, the ECS identification signal is in a valid state; the command control module is configured to receive the ECS identification signal, and when the ECS identification signal is in a valid state, obtain a refresh command signal, and generate an ECS command signal according to the refresh command signal.
  • the first clock signal is used to count, and only when the count value meets the preset condition, the ECS identification signal is in a valid state, and then the refresh command signal is obtained, so as to generate an ECS command signal for performing an ECS operation; thereby, not only can the technical problem that the ECS command signal cannot be generated by means of a self-refresh command in the related art be solved, but also based on the interval time of the ECS operation planned by the timing control module, the ECS command signal can be accurately generated, thereby ensuring that all error checks and clearing are completed in 24 hours, and ultimately improving the performance of the memory.
  • FIG1 is a schematic diagram of a signal timing of an ECS mode
  • FIG2 is a schematic diagram of a structure of a control circuit provided in an embodiment of the present disclosure.
  • FIG3 is a second schematic diagram of a structure of a control circuit provided in an embodiment of the present disclosure.
  • FIG4 is a third schematic diagram of a structure of a control circuit provided in an embodiment of the present disclosure.
  • FIG5 is a schematic diagram of the structure of an asynchronous binary counter provided by an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of the structure of a synchronous binary counter provided in an embodiment of the present disclosure.
  • FIG7 is a fourth schematic diagram of the structure of a control circuit provided in an embodiment of the present disclosure.
  • FIG8 is a fifth structural diagram of a control circuit provided in an embodiment of the present disclosure.
  • FIG9 is a sixth schematic diagram of a structure of a control circuit provided in an embodiment of the present disclosure.
  • FIG10 is a seventh schematic diagram of a structure of a control circuit provided in an embodiment of the present disclosure.
  • FIG11 is a schematic diagram of a signal timing sequence of a control circuit provided by an embodiment of the present disclosure.
  • FIG12 is a flow chart of a control method provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that “first ⁇ second ⁇ third” can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • DDR5 5th generation DDR standard (DDR5 Specification, DDR5SPEC);
  • Multi-Purpose Command (MPC)
  • ECS Error Check and Scrub
  • DDR5 DRAM it is necessary to perform a complete ECS operation on DRAM at least once within 24 hours, so the time of ECS operation needs to be planned.
  • the disclosed embodiment needs to perform error checking on all rows (Row), columns (Column, Col), storage blocks (Bank, BA), and storage groups (Bank Group, BG) in DRAM, so multiple ECS operations need to be performed within 24 hours, and the average interval time is tECSint, which is about 0.644 milliseconds for 16 Gigabyte (Gb) memory as an example.
  • the interval time is the minimum time to complete the entire 16Gb memory ECS operation within 24 hours, and the specific calculation method is 24 hours ⁇ 60 minutes/hour ⁇ 60 seconds/minute/2 ⁇ (3+2+16+6).
  • 2 ⁇ 3 is the number of BGs
  • 2 ⁇ 2 is the number of Banks in each BG
  • 2 ⁇ 16 is the number of Rows in a Bank
  • 2 ⁇ 6 is the number of operations that need to access (Access) all Cols on a Row.
  • FIG1 shows a signal timing diagram of an ECS mode (ECS Mode).
  • CK_t and CK_c represent a pair of complementary clock signals
  • CA[13:0] represents a command address signal
  • CMD represents a command signal
  • CS0 represents a low-level effective chip select signal
  • valid represents a valid command address
  • DES represents an invalid command.
  • the command signal at this time is an MPC command
  • the corresponding command address is OP00001100.
  • the normal mode is switched to enter the ECS mode (ECS Mode Entry). After a delay time (such as tMPC Delay), it is then in the ECS mode.
  • the order of the self-generated command signals inside the DRAM is the activation signal (Active, ACT), the read signal (Read, RD), the write signal (Write, WR) and the precharge signal (Precharge, PRE), tRCD represents the interval time between ACT and RD, WL represents the interval time between RD and WR, tWR represents the interval time between WR and PRE, and tRP represents the precharge time. That is to say, DDR5SPEC stipulates that the minimum time for each ECS operation is tECSc.
  • an ECS operation needs to perform internal read and write error detection modification on a Col corresponding to a Row in a Bank in a BG, so it is necessary to self-generate an internal command ACT-RD-WR-PRE, and the timing tRCD, WL, tWR is met between each adjacent command, so that the internal operation of executing an ECS command can be completed within tECSc.
  • Table 1 shows the interval time regulations for ECS operations under different memories.
  • the ECS mode can be divided into an automatic ECS operation mode and a manual ECS operation mode.
  • the MPC command sent by the memory controller (Controller) is used to generate the ECS command signal;
  • the ECS command signal can be generated by refresh or self-refresh.
  • a specific MPC command can generate an ECS operation, there is no MPC command in the automatic ECS operation mode, so it is necessary to use refresh and self-refresh to generate the ECS command for the automatic ECS operation. Since it is necessary to complete a complete error check and clearing of the DRAM within 24 hours, a timing control module is required to plan the interval time of the ECS operation in the automatic ECS operation mode.
  • the embodiment of the present disclosure can be to obtain the refresh command and the self-refresh command by counting to generate the ECS command for the automatic ECS operation, so as to ensure that the error check and clearing of all storage arrays (Full Array) in the DRAM are completed within 24 hours.
  • the embodiment of the present disclosure needs to use a signal of a natural frequency as the clock signal of the counting module.
  • next refresh command when the count meets the preset conditions, the next refresh command will be obtained to generate an ECS command as an automatic ECS operation.
  • an embodiment of the present disclosure provides a control circuit, which uses the first clock signal to count after receiving a first clock signal, and only when the count value meets a preset condition, the ECS identification signal is in a valid state, and then a refresh command signal is obtained to generate an ECS command signal for performing an ECS operation; thereby, not only can the technical problem of being unable to generate an ECS command signal with the help of a self-refresh command in the related art be solved, but also the ECS command signal can be accurately generated, thereby ensuring that all error checks and clearing are completed within 24 hours, and ultimately improving the performance of the memory.
  • the control circuit 20 may include a timing control module 201 and a command control module 202, and the output end of the timing control module 201 is connected to the input end of the command control module 202, wherein:
  • the timing control module 201 is configured to receive the first clock signal, count according to the first clock signal, generate an ECS identification signal, and send the ECS identification signal to the command control module 202; wherein, when the count value meets a preset condition, the ECS identification signal is in a valid state;
  • the command control module 202 is configured to receive the ECS identification signal, and when the ECS identification signal is in a valid state, obtain the refresh command signal, and generate the ECS command signal according to the refresh command signal.
  • control circuit 20 can be applied to relevant circuits for performing ECS operations, and specifically can be a circuit applicable to all automatic ECS operations.
  • the automatic ECS operation mode by planning the interval time for generating the ECS command signal, a complete error check and clearing of the memory can be performed at least once within 24 hours.
  • the timing control module 201 is required to plan the interval time of the ECS operation in the automatic ECS operation mode to ensure that all error checks and clearing are completed within 24 hours. That is, the timing control module 201 counts the received first clock signal, and when the count value meets the preset condition, the ECS identification signal is in a valid state, and the command control module 202 will obtain the refresh command signal at this time to generate an ECS command signal for performing the ECS operation.
  • the refresh command signal obtained at this time is a refresh command signal that appears after the count value meets the preset condition; therefore, compared with the moment when the count value meets the preset condition, the refresh command signal obtained at this time specifically refers to the refresh command signal that appears at the next moment, which can also be referred to as the next refresh command signal.
  • the interval time of the ECS operation is planned according to whether the count value meets the preset condition, which can ensure that all error checks and clearing are completed within 24 hours.
  • the refresh command signal here may include at least one of the following: a refresh signal and a self-refresh signal.
  • the refresh signal (or referred to as a “refresh command”) may be represented by REFab
  • the self-refresh signal (or referred to as a “self-refresh command”) may be represented by Self_REF.
  • DDR5SPEC stipulates that the automatic ECS operation needs to plan and generate ECS command signals in refresh and self-refresh to detect error information and perform internal read and write error detection and repair at the same time. Since it is necessary to count the number of refreshes and self-refreshes when generating automatic ECS operation commands with the help of refresh command signals, but there is no external clock during self-refresh; therefore, the first clock signal of the embodiment of the present disclosure can be a signal with an inherent frequency as a counting clock signal, thereby solving the technical problem in the related art that the ECS command signal cannot be generated with the help of self-refresh.
  • control circuit 20 may further include a clock generating circuit 203, wherein:
  • the clock generating circuit 203 is configured to generate a first clock signal.
  • the clock generating circuit 203 may include an oscillating module 2031 and a frequency dividing module 2032, wherein:
  • An oscillating module 2031 is configured to generate a second clock signal of a preset frequency
  • the frequency division module 2032 is configured to perform n-division processing on the second clock signal to obtain the first clock signal.
  • the frequency of the first clock signal is one nth of the preset frequency, where n is an integer greater than zero.
  • the oscillation module 2031 may be an oscillator (OSC), such as a ring oscillator (Ring OSC), a crystal oscillator (Crystal OSC), etc.
  • OSC oscillator
  • the oscillation module 2031 is a Ring OSC, which is configured to generate a second clock signal with a fixed frequency; then the second clock signal is divided by the frequency division module 2032 to obtain a first clock signal for counting.
  • the second clock signal can be represented by OSC_CLK
  • the first clock signal can be represented by ECS_CLK.
  • Ring OSC can be used to generate a fixed frequency OSC_CLK signal. Assuming that the clock frequency is 1818 kHz, the corresponding clock period is 550 nanoseconds (ns); then after frequency division, the output clock frequency is 227kHz ECS_CLK signal, and the corresponding clock period is 4.4 microseconds (us). In this way, since the control circuit 20 includes a clock generating circuit 203, the required first clock signal can be generated, thereby solving the technical problem of no external clock during self-refresh.
  • the timing control module 201 is further configured to stop counting when the ECS identification signal is in a valid state
  • the command control module 202 is further configured to generate a reset signal after generating an ECS command signal according to the refresh command signal, and send the reset signal to the timing control module 201. In response to the reset signal, the timing control module 201 restarts counting and controls the ECS identification signal to be in an invalid state.
  • the ECS identification signal can be represented by ECS_Flag
  • the reset signal can be represented by RESET.
  • ECS_Flag can be in a valid state or in an invalid state.
  • the timing control module 201 will generate an ECS_Flag signal in a valid state after a period of time, which is used to generate an ECS command signal; then a RESET signal will be generated and sent to the timing control module 201, so that the ECS_Flag signal is in an invalid state, and the timing control module 201 restarts counting.
  • the command control module 202 is further configured to output the received refresh command signal as an internal refresh signal when the ECS identification signal is in an invalid state.
  • the level value of the ECS identification signal may include a first value and a second value, wherein the first value may be a logic 1 indicating a high level, and the second value may be a logic 0 indicating a low level; or the first value may be a logic 0 indicating a low level, and the second value may be a logic 1 indicating a high level, and there is no limitation on this.
  • the level value of the ECS identification signal is logic 1
  • the ECS command signal can be represented by ECS_CMD
  • the internal refresh signal can be represented by REF_NEW.
  • the timing control module 201 may include a counting module 2011 and a decoding module 2012, and the output end of the counting module 2011 is connected to the input end of the decoding module 2012, wherein:
  • the counting module 2011 is configured to receive a first clock signal, count according to the first clock signal, and generate a counting signal, where the counting signal is used to represent a counting value;
  • the decoding module 2012 is configured to receive the counting signal, decode the counting signal, and obtain a target counting signal; wherein, when the counting value meets a preset condition, the target counting signal is put into a valid state.
  • the counting signal can be represented by Code ⁇ N:0>, and the target counting signal can be represented by ECS_CNT.
  • the counting signal is not just one signal, but represents a group of signals.
  • the counting signal can include N+1 bits, each of which corresponds to a signal, specifically: Code ⁇ 0>, Code ⁇ 1>, Code ⁇ 2>, ..., Code ⁇ N>; wherein the value of N is associated with the number of triggers in the counting module 2011.
  • the value of N is equal to 7.
  • the counting signal can include a number of bits, and there is a corresponding relationship between the number of bits and the number of triggers; these several bits can be used to represent the count value, and the number of triggers can determine the upper limit of the count value. Exemplarily, if the number of flip-flops here is eight, the counting signal may include eight bits, such as Code ⁇ 7:0>; at this time, the counting value range corresponding to the counting signal Code ⁇ 7:0> is 00000000-11111111.
  • the level value of the ECS_CNT signal may also include a first value and a second value.
  • the first value is a logic 1 indicating a high level and the second value is a logic 0 indicating a low level
  • the level value of the ECS_CNT signal is a logic 1
  • the counting module 2011 may include an asynchronous binary counter, wherein:
  • the asynchronous binary counter includes a plurality of triggers cascaded in sequence, wherein the input terminal (D) of each stage of the trigger is connected to its own second output terminal (Q not), and the second output terminal (Q not) of each stage of the trigger is connected to the clock terminal (CK) of the next stage of the trigger, and the clock terminal (CK) of the first stage of the trigger is connected to the first clock signal.
  • the counting module 2011 includes eight flip-flops.
  • the flip-flop may be a D-type flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF).
  • DFF Data Flip-Flop or Delay Flip-Flop
  • the D-type flip-flop is an information storage device with a memory function and two stable states. It is the most basic logic unit constituting a variety of sequential circuits and an important unit circuit in digital logic circuits.
  • the D-type flip-flop has two stable states, namely "0" and "1". Under the action of the signal received at the clock end of the flip-flop, it can flip from one stable state to another stable state.
  • the trigger may include an input terminal (D), a clock terminal (CK), a first output terminal (Q), and a second output terminal (Q is negative, represented by /Q), and may even include a reset terminal (RST).
  • the first output terminal (Q) of each level of trigger is used to output the corresponding bit in the counting signal, which may be: Code ⁇ 0>, Code ⁇ 1>, Code ⁇ 2>, ..., Code ⁇ 7>; and the reset terminal (RST) of each level of trigger is used to receive a RESET signal, which can realize the reset and clearing operation of the counting module 2011, and then restart the counting.
  • the counting module 2011 may include a synchronous binary counter, wherein:
  • the synchronous binary counter may include a plurality of counting submodules cascaded in sequence, and each counting submodule includes a trigger, and a clock end of each trigger is connected to the first clock signal, wherein:
  • a plurality of counting submodules are configured to receive a first clock signal, perform clock sampling processing through triggers contained in each of them, and output a counting signal; wherein the counting signal includes a plurality of bits, and there is a corresponding relationship between the plurality of counting submodules and the plurality of bits contained in the counting signal.
  • the synchronous binary counter may include a plurality of triggers cascaded in sequence, and the clock ends of the plurality of triggers are all connected to the first clock signal.
  • the first counting submodule may include a first trigger, an input terminal (D) of the first trigger is connected to a second output terminal (/Q) of the first trigger, a clock terminal (CK) of the first trigger is used to receive a first clock signal, and a first output terminal (Q) of the first trigger is used to output a first counting signal, and the first counting signal is the 0th bit in the counting signal;
  • the second counting submodule may include a second trigger and a second XOR gate, wherein the first input terminal of the second XOR gate is connected to the first output terminal (Q) of the first trigger, the second input terminal of the second XOR gate is connected to the first output terminal (Q) of the second trigger, the output terminal of the second XOR gate is connected to the input terminal (D) of the second trigger, the clock terminal (CK) of the second trigger is used to receive the first clock signal, and the first output terminal (Q) of the second trigger is used to output a second counting signal, and the second counting signal is the first bit in the counting signal;
  • the i-th counting submodule may include an i-th trigger, an i-th NAND gate, an i-th NOT gate and an i-th XOR gate, wherein the first input terminal of the i-th NAND gate is connected to the first output terminal (Q) of the i-1-th trigger, the second input terminal of the i-th NAND gate is connected to the first input terminal of the i-1-th XOR gate, the output terminal of the i-th NAND gate is connected to the input terminal of the i-th NAND gate, the output terminal of the i-th NOT gate is connected to the first input terminal of the i-th XOR gate, the second input terminal of the i-th XOR gate is connected to the first output terminal (Q) of the i-th trigger, the output terminal of the i-th XOR gate is connected to the input terminal (D) of the i-th trigger, the clock terminal (CK) of the i-th trigger is used to receive a first clock signal, and
  • the counting module 2011 may include eight counting submodules cascaded in sequence, and each counting submodule includes at least one trigger.
  • the eight counting submodules are specifically: a first counting submodule a, a second counting submodule b, a third counting submodule c, a fourth counting submodule d, a fifth counting submodule e, a sixth counting submodule f, a seventh counting submodule g, and an eighth counting submodule h.
  • the first counting submodule a may include a first trigger a1, and the first counting signal output by the first counting submodule a is represented by Code ⁇ 0>, which corresponds to the 0th bit of the counting signal;
  • the second counting submodule b may include a second trigger b1 and a second XOR gate b2, and the second counting signal output by the second counting submodule b is represented by Code ⁇ 1>, which corresponds to the 1st bit of the counting signal;
  • the third counting submodule c may include a third trigger c1, a third NAND gate c2, a third NOR gate c3, and a third XOR gate c4, and the third counting signal output by the third counting submodule c is represented by Code ⁇ 2>.
  • the fourth counting submodule d may include a fourth trigger d1, a fourth NAND gate d2, a fourth NOT gate d3 and a fourth XOR gate d4, and the fourth counting signal output by the fourth counting submodule d is represented by Code ⁇ 3>, which corresponds to the third bit of the counting signal; and so on, for the eighth counting submodule h, the eighth counting submodule h may include an eighth trigger h1, an eighth NAND gate h2, an eighth NOT gate h3 and an eighth XOR gate h4, and the eighth counting signal output by the eighth counting submodule h is represented by Code ⁇ 7>, which corresponds to the seventh bit of the counting signal.
  • the eight counting submodules are configured to receive the first clock signal, perform clock sampling processing through the triggers contained in each, and output a counting signal including eight bits, and there is a corresponding relationship between the eight counting submodules and the eight bits contained in the counting signal.
  • the first counting submodule is configured to output the 0th bit Code ⁇ 0> of the counting signal
  • the second counting submodule is configured to output the 1st bit Code ⁇ 1> of the counting signal
  • the third counting submodule is configured to output the 2nd bit Code ⁇ 2> of the counting signal
  • ... and the eighth counting submodule is configured to output the 7th bit Code ⁇ 7> of the counting signal.
  • the circuit implementation of the former is simple, but the use of an asynchronous binary counter will cause the output delay of each level of the counter, which will cause an erroneous decoding process before the count changes at the last level, which may affect the next count; while the circuit implementation of the latter is relatively complex, but the use of a synchronous binary counter can align the output of each level, ensuring that there is no erroneous decoding process in the counter output, thereby reducing the impact of the counter delay on the ECS_Flag signal.
  • the timing control module 201 may further include a latch module 2013, and the latch module 2013 is connected to the output end of the decoding module 2012, wherein:
  • the latch module 2013 is configured to receive the target counting signal, and when the target counting signal is in a valid state, latch the target counting signal to generate an ECS identification signal in a valid state.
  • a latch module 2013 is introduced.
  • a target count signal can be generated, and the target count signal will generate an ECS_Flag signal after passing through the latch module 2013.
  • the ECS_Flag signal is in a valid state, the next refresh command signal is stolen to generate an ECS_CMD signal, and the corresponding stolen refresh command will disappear.
  • the refresh operation will not be performed, but the ECS operation will be performed according to the ECS_CMD signal to ensure that all error checks and clearing are completed in 24 hours.
  • the timing control module 201 may further include a latch module 2013 and an automatic pulse module 2014, and the input end of the automatic pulse module 2014 is connected to the output end of the decoding module 2012, and the output end of the automatic pulse module 2014 is connected to the set end (SET) of the latch module 2013, wherein:
  • the automatic pulse module 2014 is configured to generate a set signal according to the target count signal; wherein when the target count signal is in a valid state, the set signal is in a valid state;
  • the latch module 2013 is configured to receive a set signal, and when the set signal is in a valid state, generate an ECS identification signal in a valid state according to the set signal.
  • the latch module described in the embodiment of the present disclosure may be an SR latch (SR Latch), and the SR latch may be composed of two two-input NAND gates.
  • the SR latch includes a set terminal, a reset terminal and an output terminal. Among them, the set terminal of the SR latch is used to receive a set signal, the reset terminal of the SR latch is used to receive a reset signal, and the output terminal of the SR latch is used to output an ECS identification signal.
  • the set signal can be in a valid state; if the target count signal is in an invalid state, the set signal can be in an invalid state. Only when the set signal is in a valid state can an ECS identification signal in a valid state be generated.
  • the set signal can be represented by SET, wherein the level value of the SET signal can also include a first value and a second value.
  • the first value is a logic 1 indicating a high level and the second value is a logic 0 indicating a low level
  • the level value of the SET signal is a logic 1
  • it is determined that the SET signal is in a valid state; otherwise, if the level value of the SET signal is a logic 0, it is determined that the SET signal is in an invalid state.
  • the automatic pulse module 2014 may include a signal generating module and a first AND gate, wherein a first input terminal of the first AND gate is connected to an output terminal of the decoding module 2012, a second input terminal of the first AND gate is connected to an output terminal of the signal generating module, and an output terminal of the first AND gate (as an output terminal of the automatic pulse module 2014) is connected to a set terminal (SET) of the latch module 2013, wherein:
  • a signal generating module configured to generate a target counting inverted signal; wherein the target counting inverted signal has a delay and inverted relationship with the target counting signal;
  • the first AND gate is used to perform an AND logic operation on the target count inversion signal and the target count signal to obtain a set signal.
  • the target count inversion signal generated by the signal generating module has a delayed and inverted relationship with the target count signal; in other words, the target count signal can also be delayed and inverted to obtain the target count inversion signal, and then the target count inversion signal and the target count signal are ANDed, so as to obtain the SET signal.
  • Auto Pulse is a smaller pulse signal formed by performing AND logic on the target count signal and the target count inversion signal obtained after delayed inversion of the target count signal, and this is used as the SET signal of the latch module 2013 to generate the ECS_Flag signal, so as to steal the next refresh command signal to generate the ECS_CMD signal when the ECS_Flag signal is in a valid state.
  • the automatic pulse module 2014 may include a delayed inverting module 221 and a first AND gate 222, and the first input end of the first AND gate 222 and the input end of the delayed inverting module 221 are both connected to the output end of the decoding module 2012, the second input end of the first AND gate 222 is connected to the output end of the delayed inverting module 221, and the output end of the first AND gate 222 (as the output end of the automatic pulse module 2014) is connected to the set end (SET) of the latch module 2013, wherein:
  • the delay inversion module 221 is configured to delay and invert the target counting signal to obtain a target counting inversion signal
  • the first AND gate 222 is used to perform an AND logic operation on the target count inversion signal and the target count signal to obtain a set signal.
  • the set signal is a high-level valid pulse signal.
  • the pulse width of the set signal is wider; if the delay time of the delayed inverting module to the target count signal is shorter, the pulse width of the set signal is narrower.
  • the size of the pulse width has a corresponding relationship with the delay time of the delayed inverting module to the target count signal.
  • the delay inversion module can be composed of a delay module and an inversion module connected in series, and the inversion module can be an inverter, a NOT gate, etc., so as to achieve delay and inversion effects on the target counting signal.
  • the automatic pulse module 2014 in addition to being composed of a delayed inverting module and an AND gate, the automatic pulse module 2014 can also be composed of a delayed inverting module and an NOR gate, wherein the input end of the delayed inverting module is used to receive the target count signal, the output end of the delayed inverting module is connected to the first input end of the NOR gate, the second input end of the NOR gate is used to receive the target count signal, and the output end of the NOR gate is used to output a set signal; or, the automatic pulse module 2014 can also be composed of a delayed inverting module, an OR gate and a NOR gate, wherein the input end of the delayed inverting module is used to receive the target count signal, the output end of the delayed inverting module is connected to the first input end of the OR gate, the second input end of the OR gate is used to receive the target count signal, the output end of the OR gate is connected to the input end of the NOR gate, and the output
  • the command control module 202 may include a sampling module 2021, a first delay module 2022 and a logic processing module 2023, wherein:
  • the sampling module 2021 is configured to receive a refresh command signal and an ECS identification signal, and perform sampling processing on the ECS identification signal according to the refresh command signal to obtain a sampling signal;
  • a first delay module 2022 is configured to delay the refresh command signal to obtain a delayed refresh signal
  • the logic processing module 2023 is configured to perform logic operations on the sampling signal and the delayed refresh signal, and when the sampling signal is in a valid state, select to output an ECS command signal for performing an ECS operation; and when the sampling signal is in an invalid state, select to output an internal refresh signal for performing a refresh operation.
  • the sampling signal when the ECS identification signal is in a valid state, the sampling signal is in a valid state; when the ECS identification signal is in an invalid state, the sampling signal is in an invalid state.
  • the level value of the sampling signal may also include a first value and a second value. Exemplarily, when the first value is a logic 1 indicating a high level and the second value is a logic 0 indicating a low level, if the level value of the sampling signal is a logic 1, it is determined that the sampling signal is in a valid state; otherwise, if the level value of the sampling signal is a logic 0, it is determined that the sampling signal is in an invalid state.
  • the sampling module 2021 may be a D-type flip-flop.
  • the input terminal (D) of the D-type flip-flop is used to receive the ECS identification signal
  • the clock terminal (CK) of the D-type flip-flop is used to receive the refresh command signal
  • the output terminal (Q) of the D-type flip-flop is used to output the sampling signal.
  • the logic processing module 2023 includes a first logic module U1 and a second logic module U2 , wherein:
  • the first logic module U1 is configured to perform a first logic operation on the sampling signal and the delayed refresh signal when the sampling signal is in a valid state, and output an ECS command signal to perform an ECS operation;
  • the second logic module U2 is configured to perform a second logic operation on the sampling signal and the delayed refresh signal when the sampling signal is in an invalid state, and output an internal refresh signal to perform a refresh operation.
  • whether to select the first logic module U1 to output the ECS command signal in a valid state or to select the second logic module U2 to output the internal refresh signal in a valid state can be determined according to the valid state of the sampling signal. Specifically, if the ECS command signal is output, the refresh operation will not be performed, and the ECS operation will be performed to ensure that all error checks and clearing are completed within 24 hours; if the internal refresh signal is output, the refresh operation is not affected, but the ECS operation will not be performed at this time.
  • the first logic module U1 includes a first NAND gate 231 and a first NOT gate 232, and a first input end of the first NAND gate 231 is connected to an output end of the sampling module 2021, a second input end of the first NAND gate 231 is connected to an output end of the first delay module 2022, and an output end of the first NAND gate 231 is connected to an input end of the first NOT gate 232, wherein:
  • a first NAND gate 231 is used to perform a NAND logic operation on the sampling signal and the delayed refresh signal to obtain a first intermediate signal when the sampling signal is in a valid state;
  • the first NOT gate 232 is used to perform a NOT logic operation on the first intermediate signal to obtain an ECS command signal.
  • the first logic module U1 when the sampling signal is in a valid state, the first logic module U1 can generate an ECS command signal, which is specifically generated by stealing the next refresh command REFab/Self_REF, and the stolen refresh command will disappear.
  • the second logic module U2 may include a second NOT gate 233, a second NAND gate 234 and a third NOT gate 235, and the input end of the second NOT gate 233 is connected to the output end of the sampling module 2021, the first input end of the second NAND gate 234 is connected to the output end of the second NOT gate 233, the second input end of the second NAND gate 234 is connected to the output end of the first delay module 2022, and the output end of the second NAND gate 234 is connected to the input end of the third NOT gate 235, wherein:
  • the second NOT gate 233 is used to perform a NOT logic operation on the sampling signal when the sampling signal is in an invalid state to obtain a second intermediate signal;
  • the third NOT gate 235 is used for performing a NOT logic operation on the third intermediate signal to obtain an internal refresh signal.
  • an internal refresh signal when the sampling signal is in an invalid state, an internal refresh signal can be obtained through the second logic module U2. Specifically, the refresh command REFab/Self_REF is directly output as an internal refresh signal. At this time, the refresh command will not be stolen to generate an ECS command signal, and the refresh operation will not be affected.
  • the delay time of the first delay module is greater than the sum of the delay times of the sampling module and the second NOT gate.
  • the delay time of the first delay module 2022 needs to be greater than the sum of the delay times of the sampling module 2021 and the second NOT gate 233.
  • the first delay module 2022 needs to make the delayed refresh signal later than the second intermediate signal after the sampling signal is inverted.
  • the ECS_Flag signal is in a valid state (i.e., logic 1)
  • the output of the sampling module 2021 is also logic 1
  • the output of the refresh command REFab/Self_REF can be blocked through the second NOT gate 233 (whose output is logic 0); however, there is a delay in both the sampling module 2021 and the second NOT gate 233.
  • the refresh command REFab/Self_REF reaches the second NAND gate 234 earlier than the output of the second NOT gate 233 (the output when the level value of the ECS_Flag signal is logic 1), the refresh command REFab/Self_REF cannot be blocked at this time; therefore, the refresh command REFab/Self_REF needs to be delayed by the first delay module 2022 so that the delayed refresh command REFab/Self_REF reaches the second NAND gate 234 slightly later than the output of the second NOT gate 233.
  • the command control module 202 may further include a second delay module 2024, wherein:
  • the second delay module 2024 is configured to perform delay processing on the ECS command signal to generate a reset signal.
  • a reset signal is sent to the timing control module 201, so that the timing control module 201 restarts counting and controls the ECS identification signal to be in an invalid state.
  • the reset signal is sent to the reset end of the latch module 2013 and the reset end of the counting module 2011, so that the counting module 2011 restarts counting and controls the ECS identification signal to be in an invalid state.
  • the ECS command signal is used as the reset signal of the latch module 2013 after delay, which can ensure the width of the ECS_Flag signal, thereby ensuring that the refresh command REFab/Self_REF can be stolen to generate the ECS command signal when the ECS_Flag signal is valid; in this way, according to the control circuit, the technical problem that when the count value meets the preset condition, the next refresh command is far away from the count completion moment, resulting in the inability to generate the ECS command with the help of this refresh command can also be solved.
  • the embodiment of the present disclosure provides a control circuit, which can be applied to the relevant circuits for performing ECS operations in DRAM, specifically, a circuit capable of realizing ECS command planning and generation in the automatic ECS operation mode.
  • the control circuit only when the count value meets the preset conditions, the ECS identification signal is in a valid state, and then the refresh command signal is obtained to generate an ECS command signal for performing the ECS operation; in this way, not only can the technical problem that the ECS command signal cannot be generated by means of the self-refresh command in the related art be solved, but also the technical problem that the next refresh command is far away from the count completion time when the count value meets the preset conditions and the ECS command cannot be generated by means of this refresh command can be solved according to the control circuit, so that the interval time of the ECS operation can be better planned, and all error checks and clearing can be ensured to be completed within 24 hours.
  • the ECS mode allows the DRAM to read and modify the detected error codewords internally, and write the corrected data back to the storage array, while recording the error counting results.
  • the ECS mode includes two operation modes, namely the automatic ECS operation mode and the manual ECS operation mode.
  • the first mode register signal MR14 OP[7] can be used to select.
  • the ECS command can be implemented with the help of the refresh command REFab/Self_REF; when the manual ECS operation mode is selected, the MPC command is required, and the second mode register signal MR15 OP[3] can also determine whether to perform manual ECS operation during self-refresh.
  • the value of the first mode register signal MR14 OP[7] is 1, then it is determined that the manual ECS operation mode is selected; if the value of the first mode register signal MR14 OP[7] is 0, then it is determined that the automatic ECS operation mode is selected.
  • the ECS operation in the manual ECS operation mode, if the value of the second mode register signal MR15 OP[3] is 1, it is determined that the ECS operation is performed during self-refresh; if the value of the second mode register signal MR15 OP[3] is 0, it is determined that the ECS operation is not performed during self-refresh.
  • the control circuit 20 may include a ring oscillator 901, a frequency divider 902, a timing control module 903, and a command control module 904.
  • the second clock signal output by the ring oscillator 901 may be represented by OSC_CLK.
  • OSC_CLK After the OSC_CLK signal is divided by the frequency divider 902, the first clock signal output may be represented by ECS_CLK.
  • ECS_CLK After the ECS_CLK signal is counted by the timing control module 903, when the count value meets the preset condition, the generated ECS_Flag signal is in a valid state.
  • the ECS_Flag signal is sent to the command control module 904, in which the refresh command REFab/Self_REF received at the next moment may be obtained, and the ECS_CMD signal may be generated according to the refresh command REFab/Self_REF.
  • the first mode register signal MR14 OP[7] may also be received to determine whether to select the automatic ECS operation mode or the manual ECS operation mode.
  • the timing control module 903 and the command control module 904 here are implemented for the automatic ECS operation mode.
  • the automatic ECS operation mode is selected, which is also the default mode of DDR5 DRAM. Since DRAM requires at least one Full Array complete error check and clearing within 24 hours, the timing control module 903 is required to plan the interval time of ECS operation in the automatic ECS operation mode to ensure that the Full Array complete error check and clearing is completed within 24 hours. In order to solve the problems of no external clock in self-refresh and how to plan the interval time of ECS operation.
  • the embodiment of the present disclosure can use a ring oscillator 901 to generate a fixed frequency OSC_CLK signal (with a period of 550ns), and then output the ECS_CLK signal through a divider 902 as a clock signal for counting in the timing control module 903 (with a period of 4.4us).
  • the timing control module 903 will generate a valid ECS_Flag signal after each fixed time period and stop counting.
  • the ECS_Flag signal will be transmitted to the command control module 904 of the automatic ECS operation, in which the next refresh command of REFab or Self_REF will be stolen to generate the ECS_CMD signal, and the corresponding stolen refresh command will disappear, and then a RESET signal will be generated to the timing control module 903 to reset its ECS_Flag signal to an invalid value, and at the same time, the timing control module 903 will restart counting.
  • the refresh command will not be stolen and will be directly output as the REF_NEW signal, and the refresh operation at this time will not be affected.
  • the control circuit 20 may include a counting module 101, a decoding module 102, an automatic pulse module 103, a latch module 104, a sampling module 105, a first delay module 106, a first NAND gate 107, a first NOT gate 108, a second NOT gate 109, a second NAND gate 110, a third NOT gate 111 and a second delay module 112.
  • the counting module 101 may include a plurality of D-type flip-flops, and its internal structure is shown in FIG. 5 or FIG.
  • the counting module 101 outputs a Code ⁇ N:0> signal, and then the Code ⁇ N:0> signal is decoded by the decoding module 102 to obtain an ECS_CNT signal;
  • the ECS_CNT signal can generate a SET signal after passing through the automatic pulse module 103, and the SET signal is a high-level effective pulse signal;
  • the input end of the latch module 104 is used to receive the SET signal, the reset end of the latch module 104 is used to receive the RESET signal, and the output end of the latch module 104 is used to output the ECS_Flag signal signal;
  • the sampling module 105 samples the ECS_Flag signal to obtain a sampling signal; for the sampling signal, if the sampling signal is in a valid state, the ECS_CMD signal can be output through the logic operation of the first delay module 106, the first NAND gate 107 and the first NOT gate 108; if the sampling signal is in an invalid state, the REF_NEW signal can be output through the logic operation of the first delay
  • the latch module 104 can be an SR-type latch
  • the sampling module 105 can be a D-type flip-flop.
  • the timing control module is composed of a counting module 101, a decoding module 102, an automatic pulse module 103 and a latch module 104
  • the command control module is composed of a sampling module 105, a first delay module 106, a first NAND gate 107, a first NOT gate 108, a second NOT gate 109, a second NAND gate 110, a third NOT gate 111 and a second delay module 112.
  • the ECS_CLK signal is used as the clock signal of the counting module 101, and the counting module 101 outputs the Code ⁇ N:0> signal, which generates the ECS_CNT signal (satisfying the counting value condition) through the decoding module 102, and then generates a valid ECS_Flag signal and stops the timing counting.
  • the ECS_Flag signal will be transmitted to the command control module, and then the output signal can be changed in the command control module, and the next refresh command REFab or self-refresh command Self_REF is used to generate and output the ECS_CMD signal instead of outputting the original refresh command.
  • the module After the ECS_CMD signal is generated, the module will also generate a RESET signal to the timing control module to reset its ECS_Flag signal to an invalid value, and at the same time, the timing control module will restart counting.
  • FIG. 11 a signal timing diagram of a control circuit 20 provided by an embodiment of the present disclosure is shown. As shown in FIG. 11 , it is a signal timing waveform diagram generated by the automatic ECS operation mode. Taking counting 146 times as an example, it can be seen that when the counting module outputs Code ⁇ 7:0> as 10010010, it indicates that counting 146 is completed. At the time t1 when the counting is completed, a valid ECS_CNT signal is generated; but there is no refresh command during this period.
  • the ECS_Flag signal changes from a low level state to a high level state; during the period when the ECS_Flag signal is at a high level, the refresh command REFab/Self_REF can be stolen according to the valid ECS_Flag signal, thereby generating an ECS command; then at the time t2, according to the high level state of the RESET signal, the ECS_Flag signal can be changed from a high level state to a low level state.
  • the ECS_Flag signal is a high-level valid pulse signal, and the pulse width can ensure that the refresh command REFab/Self_REF can be stolen under the valid ECS_Flag signal to generate an ECS command.
  • the ECS_Flag signal is generated through the latch of the latch module, and when ECS_Flag is a valid value, the next refresh command REFab/Self_REF is stolen to generate the ECS_CMD signal.
  • the stolen refresh command will disappear, and the counting module will stop working when the ECS_Flag signal is a valid value; when ECS_Flag is an invalid value, the refresh command will not be affected, and it will be directly output as the REF_NEW signal, and the counter will count again.
  • the control circuit 20 can be applied to all automatic ECS operations. Specifically, the control circuit can not only solve the technical problem that the ECS command signal cannot be generated by means of the self-refresh command in the related art, but also after the control circuit generates the ECS command signal, the ECS command signal is delayed and processed as the reset signal of the latch module, which can ensure the width of the ECS_Flag signal, thereby ensuring that the refresh command REFab/Self_REF is stolen to generate the ECS command signal when the ECS_Flag signal is valid, thus solving the technical problem that when the count value meets the preset conditions, the next refresh command is far away from the count completion time, which makes it impossible to generate the ECS command with the help of this refresh command; in addition, based on the interval time of the ECS operation planned by the timing control module, the ECS command signal can also be accurately generated, thereby ensuring that all error checks and clearing are completed in 24 hours, and ultimately improving the performance of the memory.
  • FIG12 a schematic diagram of a control method provided by an embodiment of the present disclosure is shown. As shown in FIG12, the process may include:
  • S1201 Receive a first clock signal through a timing control module, count according to the first clock signal, generate an ECS identification signal, and send the ECS identification signal to a command control module; wherein, when the count value meets a preset condition, the ECS identification signal is in a valid state.
  • S1202 receiving an ECS identification signal through a command control module, and when the ECS identification signal is in a valid state, acquiring a refresh command signal, and generating an ECS command signal according to the refresh command signal.
  • control method can be applied to the control circuit 20 described in any of the above embodiments or a semiconductor memory integrated with the control circuit.
  • the control circuit 20 can include a timing control module and a command control module, and the output end of the timing control module is connected to the input end of the command control module.
  • the timing control module when the ECS identification signal is in a valid state, the timing control module can also stop counting. Accordingly, in some embodiments, the method can also include:
  • a reset signal is generated by the command control module and sent to the timing control module.
  • the timing control module restarts counting and controls the ECS identification signal to be in an invalid state.
  • the method may further include: when the ECS identification signal is in an invalid state, outputting the received refresh command signal as an internal refresh signal through the command control module.
  • the timing control module may include a counting module and a decoding module. Accordingly, in some embodiments, for S1201, the method may further include:
  • the counting signal is received by the decoding module, and the counting signal is decoded to obtain a target counting signal; wherein, when the counting value meets a preset condition, the target counting signal is put into a valid state.
  • the counting module includes an asynchronous binary counter, wherein: the asynchronous binary counter includes a plurality of triggers cascaded in sequence, the input terminal (D) of each stage of the trigger is connected to its own second output terminal (/Q), and the second output terminal (/Q) of each stage of the trigger is connected to the clock terminal (CK) of the next stage of the trigger, and the clock terminal of the first stage of the trigger is connected to the first clock signal.
  • the counting module includes a synchronous binary counter, wherein: the synchronous binary counter includes a plurality of triggers cascaded in sequence, and clock ends of the plurality of triggers are all connected to the first clock signal.
  • the target count signal is used to generate an ECS identification signal.
  • the timing control module may also include a latch module. Accordingly, in some embodiments, the method may also include:
  • the target counting signal is received through the latch module, and when the target counting signal is in a valid state, the target counting signal is latched to generate an ECS identification signal in a valid state.
  • timing control module may further include an automatic pulse module and a latch module. Accordingly, in some embodiments, the method may further include:
  • the target counting signal is received through the automatic pulse module, and a set signal is generated according to the target counting signal; wherein when the target counting signal is in a valid state, the set signal is in a valid state;
  • the latch module receives a set signal, and when the set signal is in a valid state, generates an ECS identification signal in a valid state according to the set signal.
  • the automatic pulse module can include a delayed inversion module and a first AND gate. Accordingly, in some embodiments, the method can also include:
  • the target counting signal is delayed and inverted by a delay inversion module to obtain a target counting inversion signal
  • the target count inversion signal and the target count signal are subjected to an AND logic operation through the first AND gate to obtain a set signal.
  • command control module may include a sampling module, a first delay module and a logic processing module. Accordingly, in some embodiments, for S1201, the method may also include:
  • sampling signal and the delayed refresh signal are subjected to logical operations through the logic processing module.
  • the sampling signal is in a valid state
  • the ECS command signal for executing the ECS operation is selected to be output
  • the sampling signal is in an invalid state
  • the internal refresh signal for executing the refresh operation is selected to be output.
  • the sampling signal when the ECS identification signal is in a valid state, the sampling signal is in a valid state; when the ECS identification signal is in an invalid state, the sampling signal is in an invalid state.
  • the logic processing module may include a first logic module and a second logic module. Accordingly, in some embodiments, the method may also include:
  • a second logic operation is performed on the sampling signal and the delayed refresh signal through the second logic module to output an internal refresh signal.
  • the first logic module may include a first NAND gate and a first NOT gate. Accordingly, in some embodiments, the method may further include:
  • a first NAND gate When the sampling signal is in a valid state, a first NAND gate performs a NAND logic operation on the sampling signal and the delayed refresh signal to obtain a first intermediate signal;
  • a NOT logic operation is performed on the first intermediate signal through a first NOT gate to obtain an ECS command signal.
  • the second logic module includes a second NOT gate, a second NAND gate and a third NOT gate. Accordingly, in some embodiments, the method may further include:
  • a third NOT gate performs a NOT logic operation on the third intermediate signal to obtain an internal refresh signal.
  • the delay time of the first delay module is greater than the sum of the delay times of the sampling module and the second NOT gate.
  • command control module may further include a second delay module. Accordingly, in some embodiments, the method may further include:
  • the ECS command signal is delayed by the second delay module to generate a reset signal, and the reset signal is sent to the reset terminal (RST) of the latch module, so that the counting module restarts counting and controls the ECS identification signal to be in an invalid state.
  • control circuit can also include a clock generation circuit. Accordingly, in some embodiments, the method can also include: generating a first clock signal by the clock generation circuit.
  • the clock generation circuit may include an oscillation module and a frequency division module. Accordingly, in some embodiments, the method may also include:
  • the second clock signal is frequency-divided by n through the frequency-division module to obtain the first clock signal.
  • the frequency of the first clock signal is one nth of the preset frequency, where n is an integer greater than zero.
  • the refresh command signal includes at least one of the following: a refresh signal and a self-refresh signal.
  • the disclosed embodiment provides a control method, according to which the interval time of ECS operation can be planned, and ECS command signals can be accurately generated, thereby ensuring that all error checks and clearing are completed within 24 hours, ultimately improving the performance of the memory.
  • Fig. 13 a schematic diagram of the composition structure of a semiconductor memory provided by an embodiment of the present disclosure is shown.
  • the semiconductor memory 130 at least includes the control circuit 20 described in any one of the above embodiments.
  • the semiconductor memory 130 may include DRAM.
  • DRAM may not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, etc., but may also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, etc., without any limitation here.
  • the semiconductor memory 130 it mainly involves the circuit design of automatic error checking and clearing in integrated circuit design, and in particular, in the DRAM DDR5 chip, it is necessary to perform a complete error check and clearing of the DRAM at least once every 24 hours.
  • the DDR5 technical specification states that the automatic ECS operation mode needs to plan and generate ECS commands in Refresh and Self-Refresh to detect erroneous information and perform internal read and write error detection and repair.
  • the embodiment of the present disclosure can be used for related circuits that perform error checking and clearing functions in DRAM DDR5 chips, but is not limited to this scope.
  • Other command planning and generation circuits and counting timing control circuits can adopt the circuit design of the embodiment of the present disclosure.
  • the first clock signal after receiving the first clock signal, the first clock signal is used to count, and only when the count value meets the preset condition, the ECS identification signal is in a valid state, and then the refresh command signal is obtained to generate an ECS command signal for performing the ECS operation; thereby not only can the technical problem of being unable to generate the ECS command signal with the help of self-refresh in the related technology be solved, but also according to the control circuit, the technical problem of being unable to generate the ECS command with the help of this refresh command when the count value meets the preset condition is also solved.
  • the ECS command signal can also be accurately generated, thereby ensuring that all error checks and clearing are completed within 24 hours, thereby ultimately improving the performance of the memory.
  • the embodiment of the present disclosure uses the first clock signal to count, and only when the count value meets the preset condition, the ECS identification signal is in a valid state, and then the refresh command signal is obtained to generate an ECS command signal for performing the ECS operation; thereby, not only can the technical problem of being unable to generate the ECS command signal with the help of the self-refresh command in the related art be solved, but also the interval time of the ECS operation is planned based on the timing control module, and the ECS command signal can be accurately generated, thereby ensuring that all error checks and clearing are completed within 24 hours, and ultimately improving the performance of the memory.

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Abstract

本公开实施例提供了一种控制电路、控制方法以及半导体存储器，该控制电路包括时序控制模块和命令控制模块，且时序控制模块的输出端与命令控制模块的输入端连接；时序控制模块，配置为接收第一时钟信号，根据第一时钟信号进行计数，生成错误检查与清除ECS标识信号，并将ECS标识信号发送给命令控制模块；其中，在计数值满足预设条件时，使ECS标识信号处于有效状态；命令控制模块，配置为接收ECS标识信号，以及在ECS标识信号处于有效状态时，获取刷新命令信号，并根据刷新命令信号产生ECS命令信号。

Description

控制电路、控制方法以及半导体存储器
相关申请的交叉引用
本公开基于申请号为202211219790.3、申请日为2022年10月08日、发明名称为“控制电路、控制方法以及半导体存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及集成电路技术领域，尤其涉及一种控制电路、控制方法以及半导体存储器。
背景技术
随着半导体技术的不断发展，人们在制造和使用计算机等设备时，对数据的传输速度提出了越来越高的要求。为了获得更快的数据传输速度，应运而生了一系列数据可以双倍速率(Double Data Rate，DDR)传输的存储器等器件。
以动态随机存取存储器(Dynamic Random Access Memory，DRAM)为例，需要在至少每24小时对DRAM进行一次完整的错误检查与清除(Error Check and Scrub，ECS)。ECS包括自动和手动两种操作模式。其中，手动ECS操作需要多用途命令(Multi-Purpose Command，MPC)，自动ECS操作没有MPC命令，但是需要借助刷新(Refresh)命令和自刷新(Self-Refresh)命令来产生ECS命令，以便检测错误的信息并同时执行内部读写检错和修复。然而，对于自动ECS操作来说，Self-Refresh命令缺少外部时钟，导致无法通过Refresh和Self-Refresh等刷新命令进行准确计数，使得ECS命令的产生可能出现错误，影响了存储器的性能。
发明内容
本公开实施例提供了一种控制电路、控制方法以及半导体存储器。
第一方面，本公开实施例提供了一种控制电路，该控制电路包括时序控制模块和命令控制模块，且时序控制模块的输出端与命令控制模块的输入端连接，其中：
时序控制模块，配置为接收第一时钟信号，根据第一时钟信号进行计数，生成错误检查与清除ECS标识信号，并将ECS标识信号发送给命令控制模块；其中，在计数值满足预设条件时，使ECS标识信号处于有效状态；
命令控制模块，配置为接收ECS标识信号，以及在ECS标识信号处于有效状态时，获取刷新命令信号，并根据刷新命令信号产生ECS命令信号。
在一些实施例中，时序控制模块，还配置为在ECS标识信号处于有效状态时，停止计数；
命令控制模块，还配置为在根据刷新命令信号产生ECS命令信号之后生成复位信号，将复位信号发送给时序控制模块，响应于复位信号，时序控制模块重新开始计数并且控制ECS标识信号处于无效状态。
在一些实施例中，命令控制模块，还配置为在ECS标识信号处于无效状态时，将所接收到的刷新命令信号输出为内部刷新信号。
在一些实施例中，时序控制模块包括计数模块和译码模块，且计数模块的输出端与译码模块的输入端连接，其中：
计数模块，配置为接收第一时钟信号，根据第一时钟信号进行计数，生成计数信号，计数信号用于表征计数值；
译码模块，配置为接收计数信号，对计数信号进行译码处理，得到目标计数信号；其中，在计数值满足预设条件时，使目标计数信号处于有效状态。
在一些实施例中，计数模块包括异步二进制计数器，其中：异步二进制计数器包括若干个依次级联的触发器，每一级触发器的输入端与其自身的第二输出端连接，且每一级触发器的第二输出端与下一级触发器的时钟端连接，第一级触发器的时钟端与第一时钟信号连接。
在一些实施例中，计数模块包括同步二进制计数器，其中：同步二进制计数器包括若干个依次级联的触发器，且若干个触发器的时钟端均与第一时钟信号连接。
在一些实施例中，时序控制模块还包括锁存模块，且锁存模块与译码模块的输出端连接，其中：锁存模块，配置为接收目标计数信号，以及在目标计数信号处于有效状态时，对目标计数信号进行锁存处理，生成处于有效状态的ECS标识信号。
在一些实施例中，时序控制模块还包括自动脉冲模块和锁存模块，且自动脉冲模块的输入端与译码模块的输出端连接，自动脉冲模块的输出端与锁存模块的置位端连接，其中：
自动脉冲模块，配置为根据目标计数信号生成置位信号；其中，在目标计数信号处于有效状态时，使置位信号处于有效状态；
锁存模块，配置为接收置位信号，以及在置位信号处于有效状态时，根据置位信号生成处于有效状态的ECS标识信号。
在一些实施例中，自动脉冲模块包括延迟反相模块和第一与门，且第一与门的第一输入端和延迟反相模块的输入端均与译码模块的输出端连接，第一与门的第二输入端与延迟反相模块的输出端连接，第一与门的输出端作为自动脉冲模块的输出端与锁存模块的置位端连接，其中：
延迟反相模块，配置为对目标计数信号进行延迟及反相处理，得到目标计数反相信号；
第一与门，用于对目标计数反相信号和目标计数信号进行与逻辑运算，得到置位信号。
在一些实施例中，命令控制模块包括采样模块、第一延迟模块和逻辑处理模块，其中：
采样模块，配置为接收刷新命令信号和ECS标识信号，根据刷新命令信号对ECS标识信号进行采样处理，得到采样信号；
第一延迟模块，配置为对刷新命令信号进行延迟处理，得到延迟刷新信号；
逻辑处理模块，配置为对采样信号和延迟刷新信号进行逻辑运算，在采样信号处于有效状态时，选择输出用于执行ECS操作的ECS命令信号；以及在采样信号处于无效状态时，选择输出用于执行刷新操作的内部刷新信号；其中，在ECS标识信号处于有效状态时，使采样信号处于有效状态；在ECS标识信号处于无效状态时，使采样信号处于无效状态。
在一些实施例中，逻辑处理模块包括第一逻辑模块和第二逻辑模块，其中：
第一逻辑模块，配置为在采样信号处于有效状态时，对采样信号和延迟刷新信号进行第一逻辑运算，输出ECS命令信号；
第二逻辑模块，配置为在采样信号处于无效状态时，对采样信号和延迟刷新信号进行第二逻辑运算，输出内部刷新信号。
在一些实施例中，第一逻辑模块包括第一与非门和第一非门，且第一与非门的第一输入端与采样模块的输出端连接，第一与非门的第二输入端与第一延迟模块的输出端连接，第一与非门的输出端与第一非门的输入端连接，其中：
第一与非门，用于在采样信号处于有效状态时，对采样信号和延迟刷新信号进行与非逻辑运算，得到第一中间信号；
第一非门，用于对第一中间信号进行非逻辑运算，得到ECS命令信号。
在一些实施例中，第二逻辑模块包括第二与非门、第二非门和第三非门，且第二与非门的第一输入端与第二非门的输出端连接，第二与非门的第二输入端与第一延迟模块的输出端连接，第二与非门的输出端与第三非门的输入端连接，其中：
第二非门，用于在采样信号处于无效状态时，对采样信号进行非逻辑运算，得到第二中间信号；
第二与非门，用于对第二中间信号和延迟刷新信号进行与非逻辑运算，得到第三中间信号；
第三非门，用于对第三中间信号进行非逻辑运算，得到内部刷新信号。
在一些实施例中，第一延迟模块的延迟时间大于采样模块与第二非门的延迟时间之和。
在一些实施例中，命令控制模块还包括第二延迟模块，其中：第二延迟模块，配置为对ECS命令信号进行延迟处理，生成复位信号，并将复位信号发送给锁存模块的复位端，使计数模块重新开始计数并且控制ECS标识信号处于无效状态。
在一些实施例中，控制电路还包括时钟产生电路，其中：时钟产生电路，用于产生第一时钟信号。
在一些实施例中，时钟产生电路包括振荡模块和分频模块，其中：
振荡模块，配置为输出预设频率的第二时钟信号；
分频模块，配置为对第二时钟信号进行n分频处理，得到第一时钟信号；其中，第一时钟信号的频率为预设频率的n分之一，n为大于零的整数。
在一些实施例中，刷新命令信号包括下述至少之一：刷新信号和自刷新信号。
第二方面，本公开实施例提供了一种控制方法，该方法包括：
通过时序控制模块接收第一时钟信号，以及根据第一时钟信号进行计数，生成ECS标识信号，并将ECS标识信号发送给命令控制模块；其中，在计数值满足预设条件时，使ECS标识信号处于有效状态；
通过命令控制模块接收ECS标识信号，以及在ECS标识信号处于有效状态时，获取刷新命令信号，并根据刷新命令信号产生ECS命令信号。
第三方面，本公开实施例提供了一种半导体存储器，该半导体存储器包括如第一方面中任一项所述的控制电路。
在一些实施例中，所述半导体存储器包括动态随机存取存储器DRAM。
本公开实施例提供了一种控制电路、控制方法以及半导体存储器，该控制电路包括时序控制模块和命令控制模块，且时序控制模块的输出端与命令控制模块的输入端连接，其中，时序控制模块，配置为接收第一时钟信号，根据第一时钟信号进行计数，生成ECS标识信号，并将ECS标识信号发送给命令控制模块；其中，在计数值满足预设条件时，使ECS标识信号处于有效状态；命令控制模块，配置为接收ECS标识信号，以及在ECS标识信号处于有效状态时，获取刷新命令信号，并根据刷新命令信号产生ECS命令信号。这样，在接收第一时钟信号之后，利用第一时钟信号进行计数，只有在计数值满足预设条件时，使得ECS标识信号处于有效状态，然后获取刷新命令信号，以此产生用于执行ECS操作的ECS命令信号；从而不仅可以解决相关技术中无法借助自刷新命令来生成ECS命令信号的技术问题，而且基于时序控制模块规划ECS操作的间隔时间，还可以准确地产生ECS命令信号，进而能够确保24小时完成所有的错误检查与清除，最终提升存储器的性能。
附图说明
图1为一种ECS模式的信号时序示意图；
图2为本公开实施例提供的一种控制电路的组成结构示意图一；
图3为本公开实施例提供的一种控制电路的组成结构示意图二；
图4为本公开实施例提供的一种控制电路的组成结构示意图三；
图5为本公开实施例提供的一种异步二进制计数器的组成结构示意图；
图6为本公开实施例提供的一种同步二进制计数器的组成结构示意图；
图7为本公开实施例提供的一种控制电路的组成结构示意图四；
图8为本公开实施例提供的一种控制电路的组成结构示意图五；
图9为本公开实施例提供的一种控制电路的组成结构示意图六；
图10为本公开实施例提供的一种控制电路的组成结构示意图七；
图11为本公开实施例提供的一种控制电路的信号时序示意图；
图12为本公开实施例提供的一种控制方法的流程示意图；
图13为本公开实施例提供的一种半导体存储器的组成结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅用于解释相关公开，而非对该公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关公开相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通 常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅仅是区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
对本公开实施例进行进一步详细说明之前，先对本公开实施例中涉及的名词和术语进行说明，本公开实施例中涉及的名词和术语适用于如下的解释：
动态随机存取存储器(Dynamic Random Access Memory，DRAM)；
同步动态随机存取存储器(Synchronous Dynamic Random Access Memory，SDRAM)；
双倍速率(Double Data Rate，DDR)；
第5代DDR标准(DDR5 Specification，DDR5SPEC)；
多用途命令(Multi-Purpose Command，MPC)；
错误检查与清除(Error Check and Scrub，ECS)。
以DDR5 DRAM为例，需要至少在24小时内对DRAM进行一次完整的ECS操作，因此需要规划好ECS操作的时间。为了实现对DRAM进行完整的错误检查与清除，本公开实施例需要对DRAM中所有行(Row)、列(Column，Col)、存储块(Bank，BA)、存储组(Bank Group，BG)均进行错误检查，所以在24小时内需要执行多次ECS操作，平均的间隔时间为tECSint，以16吉字节(Gigabyte，Gb)内存为例大约是0.644毫秒。其中，该间隔时间是24小时内完成整个16Gb内存ECS操作的最小时间，具体计算方式为24小时×60分钟/小时×60秒/分钟/2^(3+2+16+6)。其中，2^3为BG个数，2^2为每个BG中Bank个数，2^16为一个Bank内Row的数目，2^6为一个Row上需要访问(Access)所有Col的操作次数。图1示出了一种ECS模式(ECS Mode)的信号时序示意图。如图1所示，CK_t与CK_c表示一对互补的时钟信号，CA[13:0]表示命令地址信号，CMD表示命令信号，CS0表示低电平有效的片选信号，valid表示有效命令地址，DES表示无效命令。其中，在t0时刻，这时候的命令信号为MPC命令，对应的命令地址为OP00001100，此时将由常规模式(Normal Mode)切换到进入ECS模式(ECS Mode Entry)。在经过一段延迟时间(如tMPC Delay)之后，然后处于ECS模式。对于ECS模式而言，在执行一次ECS操作时，DRAM内部自产生命令信号的顺序为激活信号(Active，ACT)、读信号(Read，RD)、写信号(Write，WR)和预充电信号(Precharge，PRE)，tRCD表示ACT到RD之间的间隔时间，WL表示RD到WR之间的间隔时间，tWR表示WR到PRE之间的间隔时间，tRP表示预充电时间。也就是说，DDR5SPEC规定每次执行ECS操作的最小时间为tECSc，在此时间段内，一个ECS操作需要对某个BG中的某个Bank中的某个Row对应的某个Col进行内部读写检错修改，因此需要自产生内部命令ACT-RD-WR-PRE，每相邻两个命令之间满足时序tRCD、WL、tWR，从而使得执行一次ECS命令的内部操作能够在tECSc内完成。示例性地，表1示出了在不同内存下ECS操作的间隔时间规定。
表1
配置 8Gb 16Gb
x4、x8、x16 1.287毫秒 0.644毫秒
可以理解地，ECS模式可以分为自动ECS操作模式和手动ECS操作模式。其中，在手动ECS操作模式下，利用内存控制器(Controller)发送的MPC命令来产生ECS命令信号；在自动ECS操作模式下，可以利用刷新或自刷新来产生ECS命令信号。虽然特定的MPC命令可以产生ECS操作，但在自动ECS操作模式下没有MPC命令，因此需要借助刷新和自刷新来产生自动ECS操作的ECS命令。由于需要在24小时内对DRAM完成一次完整的错误检查与清除，在自动ECS操作模式下就需要时序控制模块来规划ECS操作的间隔时间，本公开实施例可以是通过计数方式获取刷新命令和自刷新命令来产生自动ECS操作的ECS命令，以确保24小时内完成DRAM中所有存储阵列(Full Array)的错误检查与清除。然而，在借助刷新命令产生ECS命令信号时需要计数刷新命令和自刷新命令的个数，但是由于在自刷新时外部没有时钟，本公开实施例需要采用固有 频率的信号作为计数模块的时钟信号。
另外，当计数满足预设条件时会获取下一个刷新命令来产生作为自动ECS操作的ECS命令，但如果下一个刷新命令距离计数完成时刻存在有一段时间，将会造成无法借助这个刷新命令来生成ECS命令信号。因此，如何偷取下一个刷新命令作为自动ECS操作的ECS命令是本公开实施例所需解决的技术问题。
基于此，本公开实施例提供了一种控制电路，在接收第一时钟信号之后，利用第一时钟信号进行计数，只有在计数值满足预设条件时，使得ECS标识信号处于有效状态，然后获取刷新命令信号，以此产生用于执行ECS操作的ECS命令信号；从而不仅可以解决相关技术中无法借助自刷新命令来生成ECS命令信号的技术问题，而且还可以准确地产生ECS命令信号，进而能够确保24小时完成所有的错误检查与清除，最终提升存储器的性能。
下面将结合附图对本公开各实施例进行详细说明。
本公开的一实施例中，参见图2，其示出了本公开实施例提供的一种控制电路20的组成结构示意图。如图2所示，该控制电路20可以包括时序控制模块201和命令控制模块202，且时序控制模块201的输出端与命令控制模块202的输入端连接，其中：
时序控制模块201，配置为接收第一时钟信号，根据第一时钟信号进行计数，生成ECS标识信号，并将ECS标识信号发送给命令控制模块202；其中，在计数值满足预设条件时，使ECS标识信号处于有效状态；
命令控制模块202，配置为接收ECS标识信号，以及在ECS标识信号处于有效状态时，获取刷新命令信号，并根据刷新命令信号产生ECS命令信号。
需要说明的是，在本公开实施例中，该控制电路20可以应用于执行ECS操作的相关电路，具体可以是适用于所有自动ECS操作的电路。在自动ECS操作模式下，通过规划ECS命令信号产生的间隔时间，使得至少在24小时内能够对存储器进行一次完整的错误检查与清除。
还需要说明的是，在本公开实施例中，以DDR5 DRAM为例，由于DRAM要求至少在24小时内进行一次完整的错误检查与清除，那么在自动ECS操作模式下就需要时序控制模块201规划ECS操作的间隔时间，以确保24小时内完成所有的错误检查与清除。也就是说，时序控制模块201对接收到的第一时钟信号进行计数，并且在计数值满足预设条件时，使得ECS标识信号处于有效状态，此时命令控制模块202会获取刷新命令信号，以此产生用于执行ECS操作的ECS命令信号。需要注意的是，这时候获取的刷新命令信号是在计数值满足预设条件之后出现的刷新命令信号；因此，与计数值满足预设条件的时刻相比，这时候获取的刷新命令信号具体是指下一时刻出现的刷新命令信号，也可简称为下一个刷新命令信号。如此，根据计数值是否满足预设条件来规划ECS操作的间隔时间，能够确保24小时完成所有的错误检查与清除。在一些实施例中，这里的刷新命令信号可以包括下述至少之一：刷新信号和自刷新信号。在本公开实施例中，刷新信号(或称为“刷新命令”)可以用REFab表示，自刷新信号(或称为“自刷新命令”)可以用Self_REF表示。
需要说明的是，在自动ECS操作模式下，DDR5SPEC中规定自动ECS操作需要在刷新和自刷新中规划并产生ECS命令信号，用来检测错误信息并同时执行内部读写检错和修复。由于借助刷新命令信号生成自动ECS操作命令时需要计数刷新和自刷新的个数，但是在自刷新时外部没有时钟；因此，本公开实施例的第一时钟信号可以是采用固有频率的信号作为计数的时钟信号，从而解决了相关技术中无法借助自刷新来生成ECS命令信号的技术问题。
在一些实施例中，对于第一时钟信号而言，在图2所示控制电路20的基础上，参见图3，控制电路20还可以包括时钟产生电路203，其中：
时钟产生电路203，配置为产生第一时钟信号。
在一种具体的实施例中，参见图3，时钟产生电路203可以包括振荡模块2031和分频模块2032，其中：
振荡模块2031，配置为产生预设频率的第二时钟信号；
分频模块2032，配置为对第二时钟信号进行n分频处理，得到第一时钟信号。
需要说明的是，在本公开实施例中，第一时钟信号的频率为预设频率的n分之一，n为大于零的整数。
还需要说明的是，在本公开实施例中，振荡模块2031可以是振荡器(Oscillator，OSC)，例 如环形振荡器(Ring OSC)、晶体振荡器(Crystal OSC)等。在这里，振荡模块2031为Ring OSC，配置为产生固定频率的第二时钟信号；然后通过分频模块2032对第二时钟信号进行分频处理，可以得到用于计数的第一时钟信号。其中，第二时钟信号可以用OSC_CLK表示，第一时钟信号可以用ECS_CLK表示。
示例性地，可以采用Ring OSC产生固定频率的OSC_CLK信号，假定时钟频率为1818千赫兹(kHz)，对应的时钟周期为550纳秒(nanosecond，ns)；那么在经过分频处理之后，输出时钟频率为227kHz的ECS_CLK信号，其对应的时钟周期为4.4微秒(microsecond，us)。这样，由于控制电路20中包括有时钟产生电路203，可以产生所需的第一时钟信号，从而解决了在自刷新时没有外部时钟的技术问题。
进一步地，对于时序控制模块201和命令控制模块202而言，在一些实施例中，时序控制模块201，还配置为在ECS标识信号处于有效状态时，停止计数；
命令控制模块202，还配置为在根据刷新命令信号产生ECS命令信号之后生成复位信号，将复位信号发送给时序控制模块201，响应于复位信号，时序控制模块201重新开始计数并且控制ECS标识信号处于无效状态。
需要说明的是，在本公开实施例中，ECS标识信号可以用ECS_Flag表示，复位信号可以用RESET表示。在这里，ECS_Flag可以是处于有效状态，也可以是处于无效状态。其中，时序控制模块201会在每间隔一段时间之后产生处于有效状态的ECS_Flag信号，用于产生ECS命令信号；然后还会再产生一个RESET信号发送给时序控制模块201，使ECS_Flag信号处于无效状态，同时使时序控制模块201重新开始计数。
在一些实施例中，命令控制模块202，还配置为在ECS标识信号处于无效状态时，将所接收到的刷新命令信号输出为内部刷新信号。
具体来说，ECS标识信号的电平值可以包括第一值和第二值。其中，第一值可以为指示高电平的逻辑1，第二值可以为指示低电平的逻辑0；或者，第一值可以为指示低电平的逻辑0，第二值可以为指示高电平的逻辑1，对此并不作任何限定。
示例性地，如果ECS标识信号的电平值为逻辑1，那么可以确定ECS标识信号处于有效状态；否则，如果ECS标识信号的电平值为逻辑0，那么可以确定ECS标识信号处于无效状态。
还需要说明的是，在本公开实施例中，如果ECS标识信号处于有效状态，那么可以偷取下一时刻接收到的刷新命令信号，并根据该刷新命令信号产生ECS命令信号，同时对应被偷取的刷新命令信号会消失，以执行ECS操作；如果ECS标识信号处于无效状态，那么刷新命令信号不会被偷取，直接输出为内部刷新信号，以执行刷新操作。其中，ECS命令信号可以用ECS_CMD表示，内部刷新信号可以用REF_NEW表示。
在一些实施例中，对于时序控制模块201而言，在图2所示控制电路20的基础上，参见图4，时序控制模块201可以包括计数模块2011和译码模块2012，且计数模块2011的输出端与译码模块2012的输入端连接，其中：
计数模块2011，配置为接收第一时钟信号，根据第一时钟信号进行计数，生成计数信号，计数信号用于表征计数值；
译码模块2012，配置为接收计数信号，对计数信号进行译码处理，得到目标计数信号；其中，在计数值满足预设条件时，使目标计数信号处于有效状态。
需要说明的是，在图4中，计数信号可以用Code<N:0>表示，目标计数信号可以用ECS_CNT表示。其中，计数信号并不是仅为一个信号，其代表一组信号。在这里，计数信号可以包括N+1个比特位，每一个比特位各自对应一个信号，具体可以为：Code<0>、Code<1>、Code<2>、…、Code<N>；其中，N的取值与计数模块2011中的触发器数量具有关联关系。
示例性地，假定计数模块2011中的触发器数量为八个，那么N的取值等于7。以16Gb的内存配置为例，为了满足24小时内对DRAM完成一次完整的错误检查与清除，ECS操作的时间间隔为644us，第一时钟信号的周期为4.4us，那么需要计数大约644/4.4＝146次时表示一次计数完成。也就是说，根据第一时钟信号进行计数，可以得到用于表征计数值的计数信号Code<7:0>；其中，只有在计数信号Code<7:0>满足10010010，即计数值达到146(这里，2^1+2^4+2^7＝146)时，ECS_CNT信号处于有效状态，此时可以产生处于有效状态的ECS标识信号。需要注意的是，计数信号可以包括若干个比特位，而且比特位数量与触发器数量之间具有对应关系；这若干个比特 位可以用来表征计数值，且触发器数量能够决定计数值的上限值。示例性地，若这里的触发器数量为八个，则计数信号可以包括八个比特位，如Code<7:0>；此时计数信号Code<7:0>对应的计数值范围是00000000～11111111。
还需要说明的是，在本公开实施例中，ECS_CNT信号的电平值也可以包括第一值和第二值。示例性地，在第一值为指示高电平的逻辑1，第二值为指示低电平的逻辑0的情况下，若ECS_CNT信号的电平值为逻辑1，则确定ECS_CNT信号处于有效状态；否则，若ECS_CNT信号的电平值为逻辑0，则确定ECS_CNT信号处于无效状态。
进一步地，对于计数模块2011而言，在一种可能的实施例中，计数模块2011可以包括异步二进制计数器，其中：
异步二进制计数器包括若干个依次级联的触发器，每一级触发器的输入端(D)与其自身的第二输出端(Q非)连接，且每一级触发器的第二输出端(Q非)与下一级触发器的时钟端(CK)连接，第一级触发器的时钟端(CK)与第一时钟信号连接。
在本公开实施例中，以图5所示的异步二进制计数器为例，该计数模块2011包括八个触发器。在这里，触发器可以为D型触发器(Data Flip-Flop或Delay Flip-Flop，DFF)，D型触发器是一个具有记忆功能的、具有两个稳定状态的信息存储器件，是构成多种时序电路的最基本逻辑单元，也是数字逻辑电路中一种重要的单元电路。D型触发器具有两个稳定状态，即“0”和“1”，在该触发器的时钟端所接收的信号作用下，可以从一个稳定状态翻转到另一个稳定状态。
在本公开实施例中，触发器可以包括输入端(D)、时钟端(CK)、第一输出端(Q)和第二输出端(Q非，用/Q表示)，甚至也可以包括复位端(RST)。在这里，每一级触发器的第一输出端(Q)用于输出计数信号中的对应比特位，具体可以为：Code<0>、Code<1>、Code<2>、…、Code<7>；而每一级触发器的复位端(RST)用于接收RESET信号，可以实现计数模块2011的复位清零操作，进而重新开始计数。
进一步地，对于计数模块2011而言，在另一种可能的实施例中，计数模块2011可以包括同步二进制计数器，其中：
同步二进制计数器可以包括若干个依次级联的计数子模块，且每个计数子模块均包括触发器，每个触发器的时钟端均与第一时钟信号连接，其中：
若干个计数子模块，配置为接收第一时钟信号，通过各自包含的触发器进行时钟采样处理，输出计数信号；其中，计数信号包括若干个比特位，且若干个计数子模块与计数信号包含的若干个比特位之间具有对应关系。
简单来说，在本公开实施例中，同步二进制计数器可以包括若干个依次级联的触发器，且这若干个触发器的时钟端均与第一时钟信号连接。
进一步地，在一些实施例中，对于同步二进制计数器而言，在若干个计数子模块中，具体如下：
第一个计数子模块可以包括第一触发器，第一触发器的输入端(D)与第一触发器的第二输出端(/Q)连接，第一触发器的时钟端(CK)用于接收第一时钟信号，且第一触发器的第一输出端(Q)用于输出第一计数信号，且第一计数信号是计数信号中的第0比特位；
第二个计数子模块可以包括第二触发器和第二异或门，第二异或门的第一输入端与第一触发器的第一输出端(Q)连接，第二异或门的第二输入端与第二触发器的第一输出端(Q)连接，第二异或门的输出端与第二触发器的输入端(D)连接，第二触发器的时钟端(CK)用于接收第一时钟信号，且第二触发器的第一输出端(Q)用于输出第二计数信号，且第二计数信号是计数信号中的第1比特位；
第i个计数子模块可以包括第i触发器、第i与非门、第i非门和第i异或门，第i与非门的第一输入端与第i-1触发器的第一输出端(Q)连接，第i与非门的第二输入端与第i-1异或门的第一输入端连接，第i与非门的输出端与第i非门的输入端连接，第i非门的输出端与第i异或门的第一输入端连接，第i异或门的第二输入端与第i触发器的第一输出端(Q)连接，第i异或门的输出端与第i触发器的输入端(D)连接，第i触发器的时钟端(CK)用于接收第一时钟信号，且第i触发器的第一输出端(Q)用于输出第i计数信号，且第i计数信号是计数信号中的第i-1比特位；其中，i为大于或等于3且小于或等于M的整数，M为正整数。
在本公开实施例中，以图6所示的同步二进制计数器为例，该计数模块2011可以包括八个依 次级联的计数子模块，且每个计数子模块均至少包括一个触发器。其中，这八个计数子模块具体为：第一个计数子模块a、第二个计数子模块b、第三个计数子模块c、第四个计数子模块d、第五个计数子模块e、第六个计数子模块f、第七个计数子模块g、第八个计数子模块h。具体地，第一个计数子模块a可以包括第一触发器a1，第一个计数子模块a输出的第一计数信号用Code<0>表示，其对应为计数信号的第0个比特位；第二个计数子模块b可以包括第二触发器b1和第二异或门b2，第二个计数子模块b输出的第二计数信号用Code<1>表示，其对应为计数信号的第1个比特位；第三个计数子模块c可以包括第三触发器c1、第三与非门c2、第三非门c3和第三异或门c4，第三个计数子模块c输出的第三计数信号用Code<2>表示，其对应为计数信号的第2个比特位；第四个计数子模块d可以包括第四触发器d1、第四与非门d2、第四非门d3和第四异或门d4，第四个计数子模块d输出的第四计数信号用Code<3>表示，其对应为计数信号的第3个比特位；以此类推，对于第八个计数子模块h而言，第八个计数子模块h可以包括第八触发器h1、第八与非门h2、第八非门h3和第八异或门h4，第八个计数子模块h输出的第八计数信号用Code<7>表示，其对应为计数信号的第7个比特位。这样，这八个计数子模块，配置为接收第一时钟信号，通过各自包含的触发器进行时钟采样处理，输出包括八个比特位的计数信号，而且这八个计数子模块与计数信号包含的八个比特位之间具有对应关系。示例性地，第一个计数子模块配置为输出计数信号的第0个比特位Code<0>，第二个计数子模块配置为输出计数信号的第1个比特位Code<1>，第三个计数子模块配置为输出计数信号的第2个比特位Code<2>，…，第八个计数子模块配置为输出计数信号的第7个比特位Code<7>。
也就是说，对于计数模块2011而言，其可以是异步二进制计数器，也可以是同步二进制计数器。其中，前者的电路实现简单，但是采用异步二进制计数器会导致计数器每一级的输出延迟，进而会导致计数在最后一级变化之前出现错误译码过程，从而有可能影响下一次计数；而后者的电路实现相对复杂，但是采用同步二进制计数器可以使每一级的输出对齐，保证计数器输出没有错误的译码过程，从而减少计数器延迟对ECS_Flag信号产生的影响。
进一步地，在一些实施例中，对于时序控制模块201而言，在图2所示控制电路20的基础上，参见图4，该时序控制模块201还可以包括锁存模块2013，且锁存模块2013与译码模块2012的输出端连接，其中：
锁存模块2013，配置为接收目标计数信号，以及在目标计数信号处于有效状态时，对目标计数信号进行锁存处理，生成处于有效状态的ECS标识信号。
需要说明的是，在本公开实施例中，这里引入了锁存模块2013。其中，当计数完成时可以产生目标计数信号，而目标计数信号经过锁存模块2013后会产生ECS_Flag信号，在ECS_Flag信号处于有效状态时偷取下一个刷新命令信号来产生ECS_CMD信号，同时对应被偷取的刷新命令会消失，在这期间也就不会执行刷新操作，而是根据ECS_CMD信号来执行ECS操作，以确保24小时完成所有的错误检查与清除。
进一步地，在一些实施例中，对于时序控制模块201而言，在图2所示控制电路20的基础上，参见图7，时序控制模块201还可以包括锁存模块2013和自动脉冲模块2014，且自动脉冲模块2014的输入端与译码模块2012的输出端连接，自动脉冲模块2014的输出端与锁存模块2013的置位端(SET)连接，其中：
自动脉冲模块2014，配置为根据目标计数信号生成置位信号；其中，在目标计数信号处于有效状态时，使置位信号处于有效状态；
锁存模块2013，配置为接收置位信号，以及在置位信号处于有效状态时，根据置位信号生成处于有效状态的ECS标识信号。
需要说明的是，本公开实施例所述的锁存模块可以是SR型锁存器(SR Latch)，且SR型锁存器可以是由两个二输入与非门组成的。另外，在本公开实施例中，SR型锁存器包括置位端、复位端和输出端。其中，SR型锁存器的置位端用于接收置位信号，SR型锁存器的复位端用于接收复位信号，SR型锁存器的输出端用于输出ECS标识信号。
还需要说明的是，在本公开实施例中，若目标计数信号处于有效状态，则可以使置位信号处于有效状态；若目标计数信号处于无效状态，则可以使置位信号处于无效状态。其中，只有置位信号处于有效状态时，才可以产生处于有效状态的ECS标识信号。
还需要说明的是，在本公开实施例中，置位信号可以用SET表示，其中，SET信号的电平值 也可以包括第一值和第二值。示例性地，在第一值为指示高电平的逻辑1，第二值为指示低电平的逻辑0的情况下，若SET信号的电平值为逻辑1，则确定SET信号处于有效状态；否则，若SET信号的电平值为逻辑0，则确定SET信号处于无效状态。
进一步地，对于自动脉冲模块2014而言，在一些实施例中，自动脉冲模块2014可以包括信号产生模块和第一与门，第一与门的第一输入端与译码模块2012的输出端连接，第一与门的第二输入端与信号产生模块的输出端连接，第一与门的输出端(作为自动脉冲模块2014的输出端)与锁存模块2013的置位端(SET)连接，其中：
信号产生模块，配置为产生目标计数反相信号；其中，目标计数反相信号与目标计数信号之间具有延迟及反相关系；
第一与门，用于对目标计数反相信号和目标计数信号进行与逻辑运算，得到置位信号。
需要说明的是，在本公开实施例中，信号产生模块所产生的目标计数反相信号与目标计数信号之间具有延迟及反相关系；换句话说，这里也可以是对目标计数信号进行延迟反相处理，得到目标计数反相信号，然后再对目标计数反相信号和目标计数信号进行与逻辑运算，从而能够得到SET信号。
也就是说，在本公开实施例中，对于自动脉冲(Auto Pulse)模块而言，Auto Pulse是目标计数信号经过延迟反相后得到的目标计数反相信号再和目标计数信号进行与逻辑所形成的一个较小的脉冲信号，以此作为锁存模块2013的SET信号来产生ECS_Flag信号，以便在ECS_Flag信号处于有效状态时偷取下一个刷新命令信号来产生ECS_CMD信号。
在一种具体的实施例中，参见图7，自动脉冲模块2014可以包括延迟反相模块221和第一与门222，且第一与门222的第一输入端和延迟反相模块221的输入端均与译码模块2012的输出端连接，第一与门222的第二输入端与延迟反相模块221的输出端连接，第一与门222的输出端(作为自动脉冲模块2014的输出端)与锁存模块2013的置位端(SET)连接，其中：
延迟反相模块221，配置为对目标计数信号进行延迟及反相处理，得到目标计数反相信号；
第一与门222，用于对目标计数反相信号和目标计数信号进行与逻辑运算，得到置位信号。
需要说明的是，在本公开实施例中，置位信号为高电平有效的脉冲信号。其中，如果延迟反相模块对目标计数信号的延迟时间越大，那么置位信号的脉冲宽度越宽；如果延迟反相模块对目标计数信号的延迟时间越小，那么置位信号的脉冲宽度越窄。也就是说，脉冲宽度的大小与延迟反相模块对目标计数信号的延迟时间具有对应关系。
还需要说明的是，在本公开实施例中，延迟反相模块可以是由延迟模块和反相模块串联构成的，反相模块可以是反相器、非门等，从而对目标计数信号能够实现延迟及反相作用。
还需要说明的是，在本公开实施例中，对于自动脉冲模块2014而言，除了可以是由延迟反相模块和一个与门组成之外，自动脉冲模块2014还可以是延迟反相模块和一个或非门组成，其中，延迟反相模块的输入端用于接收目标计数信号，延迟反相模块的输出端和或非门的第一输入端连接，或非门的第二输入端用于接收目标计数信号，或非门的输出端用于输出置位信号；或者，自动脉冲模块2014还可以是延迟反相模块、一个或门和一个非门组成，其中，延迟反相模块的输入端用于接收目标计数信号，延迟反相模块的输出端和或门的第一输入端连接，或门的第二输入端用于接收目标计数信号，或门的输出端与非门的输入端连接，该非门的输出端用于输出置位信号；自动脉冲模块2014甚至也可以是其他逻辑器件组合，只要能够产生一个较小的脉冲信号即可，其内部结构并不作任何限定。
进一步地，在一些实施例中，对于命令控制模块202而言，在图2所示控制电路20的基础上，参见图8，该命令控制模块202可以包括采样模块2021、第一延迟模块2022和逻辑处理模块2023，其中：
采样模块2021，配置为接收刷新命令信号和ECS标识信号，根据刷新命令信号对ECS标识信号进行采样处理，得到采样信号；
第一延迟模块2022，配置为对刷新命令信号进行延迟处理，得到延迟刷新信号；
逻辑处理模块2023，配置为对采样信号和延迟刷新信号进行逻辑运算，在采样信号处于有效状态时，选择输出用于执行ECS操作的ECS命令信号；以及在采样信号处于无效状态时，选择输出用于执行刷新操作的内部刷新信号。
需要说明的是，在本公开实施例中，在ECS标识信号处于有效状态时，使采样信号处于有效 状态；在ECS标识信号处于无效状态时，使采样信号处于无效状态。其中，采样信号的电平值也可以包括第一值和第二值。示例性地，在第一值为指示高电平的逻辑1，第二值为指示低电平的逻辑0的情况下，若采样信号的电平值为逻辑1，则确定采样信号处于有效状态；否则，若采样信号的电平值为逻辑0，则确定采样信号处于无效状态。
还需要说明的是，在本公开实施例中，采样模块2021可以为D型触发器。在这里，该D型触发器的输入端(D)用于接收ECS标识信号，该D型触发器的时钟端(CK)用于接收刷新命令信号，该D型触发器的输出端(Q)用于输出采样信号。
进一步地，在一些实施例中，在图2所示控制电路20的基础上，参见图8，逻辑处理模块2023包括第一逻辑模块U1和第二逻辑模块U2，其中：
第一逻辑模块U1，配置为在采样信号处于有效状态时，对采样信号和延迟刷新信号进行第一逻辑运算，输出ECS命令信号，以执行ECS操作；
第二逻辑模块U2，配置为在采样信号处于无效状态时，对采样信号和延迟刷新信号进行第二逻辑运算，输出内部刷新信号，以执行刷新操作。
还需要说明的是，在本公开实施例中，可以根据采样信号的有效状态与否来确定是选择第一逻辑模块U1来输出处于有效状态的ECS命令信号，还是选择第二逻辑模块U2来输出处于有效状态的内部刷新信号。具体地，如果输出ECS命令信号，那么就不会再执行刷新操作，这时候会通过执行ECS操作来确保24小时完成所有的错误检查与清除；如果输出内部刷新信号，那么刷新操作不受影响，但是这时候不会执行ECS操作。
在一种可能的实施例中，如图8所示，第一逻辑模块U1包括第一与非门231和第一非门232，且第一与非门231的第一输入端与采样模块2021的输出端连接，第一与非门231的第二输入端与第一延迟模块2022的输出端连接，第一与非门231的输出端与第一非门232的输入端连接，其中：
第一与非门231，用于在采样信号处于有效状态时，对采样信号和延迟刷新信号进行与非逻辑运算，得到第一中间信号；
第一非门232，用于对第一中间信号进行非逻辑运算，得到ECS命令信号。
在本公开实施例中，在采样信号处于有效状态时，通过第一逻辑模块U1可以产生ECS命令信号，具体是偷取下一个刷新命令REFab/Self_REF来产生的，而且被偷取的刷新命令会消失。
在一种可能的实施例中，如图8所示，第二逻辑模块U2可以包括第二非门233、第二与非门234和第三非门235，且第二非门233的输入端与采样模块2021的输出端连接，第二与非门234的第一输入端与第二非门233的输出端连接，第二与非门234的第二输入端与第一延迟模块2022的输出端连接，第二与非门234的输出端与第三非门235的输入端连接，其中：
第二非门233，用于在采样信号处于无效状态时，对采样信号进行非逻辑运算，得到第二中间信号；
第二与非门234，用于对第二中间信号和延迟刷新信号进行与非逻辑运算，得到第三中间信号；
第三非门235，用于对第三中间信号进行非逻辑运算，得到内部刷新信号。
在本公开实施例中，在采样信号处于无效状态时，通过第二逻辑模块U2可以得到内部刷新信号，具体是刷新命令REFab/Self_REF直接输出为内部刷新信号，这时候的刷新命令不会被偷取产生ECS命令信号，进行的刷新操作也不受影响。
进一步地，如图8所示，在一些实施例中，第一延迟模块的延迟时间大于采样模块与第二非门的延迟时间之和。
在本公开实施例中，以图8为例，第一延迟模块2022的延迟时间需要大于采样模块2021与第二非门233的延迟时间之和。换句话说，第一延迟模块2022需要使得延迟刷新信号晚于采样信号反相后的第二中间信号。其中，在ECS_Flag信号处于有效状态(即为逻辑1)时，采样模块2021的输出也为逻辑1，可以通过第二非门233(其输出为逻辑0)来阻断刷新命令REFab/Self_REF的输出；但是采样模块2021与第二非门233均存在有延迟，如果刷新命令REFab/Self_REF到达第二与非门234的时间早于第二非门233的输出(在ECS_Flag信号的电平值为逻辑1时的输出)，此时就不能起到阻断刷新命令REFab/Self_REF的作用；因此，对于刷新命令REFab/Self_REF需经过第一延迟模块2022进行延迟，以使得延迟后的刷新命令REFab/Self_REF到达第二与非门234的时间稍晚于第二非门233的输出。
进一步地，在一些实施例中，对于命令控制模块202而言，参见图8，该命令控制模块202 还可以包括第二延迟模块2024，其中：
第二延迟模块2024，配置为对ECS命令信号进行延迟处理，生成复位信号。
在本公开实施例中，将复位信号发送给时序控制模块201，以使得时序控制模块201重新开始计数并且控制ECS标识信号处于无效状态。具体来说，以图7所示的时序控制模块201为例，在生成复位信号之后，将复位信号发送给锁存模块2013的复位端和计数模块2011的复位端，可以使得计数模块2011重新开始计数并且控制ECS标识信号处于无效状态。这样，ECS命令信号经过延迟之后作为锁存模块2013的复位信号，可以保证ECS_Flag信号的宽度，从而保证在ECS_Flag信号有效的情况下可以偷取刷新命令REFab/Self_REF来产生ECS命令信号；如此，根据该控制电路还可以解决在计数值满足预设条件时，下一个刷新命令距离计数完成时刻距离较远而造成无法借助这个刷新命令来生成ECS命令的技术问题。
本公开实施例提供了一种控制电路，可以应用于DRAM中执行ECS操作的相关电路，具体是能够实现自动ECS操作模式下的ECS命令规划和产生的电路。在该控制电路中，只有在计数值满足预设条件时，使得ECS标识信号处于有效状态，然后获取刷新命令信号，以此产生用于执行ECS操作的ECS命令信号；如此，不仅可以解决相关技术中无法借助自刷新命令来生成ECS命令信号的技术问题，而且根据该控制电路还可以解决在计数值满足预设条件时，下一个刷新命令距离计数完成时刻距离较远而造成无法借助这个刷新命令来生成ECS命令的技术问题，从而可以更好地规划ECS操作的间隔时间，能够确保24小时完成所有的错误检查与清除。本公开的另一实施例中，基于前述实施例所述的控制电路20，以DDR5 DRAM为例，ECS模式允许DRAM内部读取、修改检测到的错误码字，并将修正后的数据写回存储阵列，同时记录错误计数结果。在这里，ECS模式包括自动ECS操作模式和手动ECS操作模式等两种操作模式。对于这两种操作模式，可以通过第一模式寄存器信号MR14 OP[7]来选择。在选择自动ECS操作模式时，可以借助刷新命令REFab/Self_REF来实现ECS命令；而在选择手动ECS操作模式时，需要MPC命令，同时第二模式寄存器信号MR15 OP[3]也可以决定是否在自刷新时执行手动ECS操作。
在一些实施例中，如果第一模式寄存器信号MR14 OP[7]的取值为1，那么确定选择手动ECS操作模式；如果第一模式寄存器信号MR14 OP[7]的取值为0，那么确定选择自动ECS操作模式。
在一些实施例中，在手动ECS操作模式下，如果第二模式寄存器信号MR15 OP[3]的取值为1，那么确定在自刷新时执行ECS操作；如果第二模式寄存器信号MR15 OP[3]的取值为0，那么确定在自刷新时不执行ECS操作。
参见图9，其示出了本公开实施例提供的一种控制电路20的具体电路结构示意图。如图9所示，该控制电路20可以包括环形振荡器901、分频器902、时序控制模块903和命令控制模块904。其中，环形振荡器901输出的第二时钟信号可以用OSC_CLK表示，OSC_CLK信号经过分频器902的分频处理之后，输出的第一时钟信号可以用ECS_CLK表示；随后ECS_CLK信号经过时序控制模块903的计数操作之后，当计数值满足预设条件时，生成的ECS_Flag信号处于有效状态；将该ECS_Flag信号发送到命令控制模块904，在该模块中可以获取下一时刻接收到的刷新命令REFab/Self_REF，并根据刷新命令REFab/Self_REF来产生ECS_CMD信号。另外，对于命令控制模块904而言，还可以接收第一模式寄存器信号MR14 OP[7]，以便确定是选择自动ECS操作模式还是选择手动ECS操作模式。但需要注意的是，这里的时序控制模块903和命令控制模块904是针对自动ECS操作模式来实现的。
具体来说，当第一模式寄存器信号MR14 OP[7]＝0时，选择自动ECS操作模式也是DDR5 DRAM的默认模式，由于DRAM要求至少在24小时内进行一次Full Array完整的错误检查与清除，在自动ECS操作模式下就需要时序控制模块903来规划ECS操作的间隔时间，以确保24小时内完成Full Array完整的错误检查与清除。为了解决在自刷新没有外部时钟和如何规划ECS操作的间隔时间等问题。本公开实施例可以采用环形振荡器901产生固定频率的OSC_CLK信号(周期为550ns)，然后经过分频器902输出ECS_CLK信号作为时序控制模块903中用于计数的时钟信号(周期为4.4us)。
这样，根据该时钟信号，时序控制模块903会在每间隔一个固定时间段之后产生一个有效的ECS_Flag信号，并且停止计数。该ECS_Flag信号会传输到自动ECS操作的命令控制模块904，在该模块中偷取下一个刷新REFab或者自刷新Self_REF的刷新命令来产生ECS_CMD信号，同时对应被偷取的刷新命令会消失，然后再产生一个RESET信号给时序控制模块903，使其ECS_Flag 信号复位为无效值，同时使时序控制模块903重新开始计数。在ECS_Flag信号为无效值期间，刷新命令不会被偷取，直接输出为REF_NEW信号，此时的刷新操作不受影响。
在一种具体的实施例中，参见图10，其示出了本公开实施例提供的另一种控制电路20的具体电路结构示意图。如图10所示，该控制电路20可以包括计数模块101、译码模块102、自动脉冲模块103、锁存模块104、采样模块105、第一延迟模块106、第一与非门107、第一非门108、第二非门109、第二与非门110、第三非门111和第二延迟模块112。其中，计数模块101可以包括若干个D型触发器，其内部结构详见图5或图6；计数模块101输出Code<N:0>信号，然后通过译码模块102对Code<N:0>信号进行译码处理，可以得到ECS_CNT信号；ECS_CNT信号经过自动脉冲模块103之后可以产生SET信号，该SET信号为高电平有效的脉冲信号；锁存模块104的输入端用于接收SET信号，锁存模块104的复位端用于接收RESET信号，锁存模块104的输出端用于输出ECS_Flag信号；通过采样模块105对ECS_Flag信号进行采样处理，得到采样信号；对于该采样信号，如果采样信号处于有效状态，那么可以通过第一延迟模块106、第一与非门107和第一非门108的逻辑运算，输出ECS_CMD信号；如果采样信号处于无效状态，那么可以通过第一延迟模块106、第二非门109、第二与非门110和第三非门111的逻辑运算，输出REF_NEW信号；而对于ECS_CMD信号，经过第二延迟模块112的延迟处理后可以得到RESET信号。在这里，锁存模块104可以为SR型锁存器，采样模块105可以为D型触发器。另外，时序控制模块是由计数模块101、译码模块102、自动脉冲模块103和锁存模块104组成的，命令控制模块是由采样模块105、第一延迟模块106、第一与非门107、第一非门108、第二非门109、第二与非门110、第三非门111和第二延迟模块112组成的。
可以理解地，在本公开实施例中，ECS_CLK信号作为计数模块101的时钟信号，计数模块101输出Code<N:0>信号，经过译码模块102产生ECS_CNT信号(满足计数值条件)，之后产生一个有效的ECS_Flag信号，并且停止时序的计数。该ECS_Flag信号会传输到命令控制模块，然后在命令控制模块中可以更改输出信号，将下一个刷新命令REFab或者自刷新命令Self_REF用来产生ECS_CMD信号并进行输出，而不是输出原来的刷新命令。在ECS_CMD信号产生之后，该模块还会产生一个RESET信号给时序控制模块，使其ECS_Flag信号复位为无效值，同时使时序控制模块重新开始计数。在ECS_Flag信号为无效值期间，刷新命令不会被偷取，直接传输到REF_NEW信号，进行的刷新操作不受影响。例如，如果ECS操作的时间间隔为644us，ECS_CLK信号的周期为4.4us，那么需要计数大约644/4.4＝146次时表示一次计数完成。
参见图11，其示出了本公开实施例提供的一种控制电路20的信号时序示意图。如图11所示，其为自动ECS操作模式产生的信号时序波形图。以计数146次为例，可以看出计数模块输出Code<7:0>为10010010时表示计数146完成，在计数完成的t1时刻，此时产生有效的ECS_CNT信号；但这段时间没有刷新命令，这时候根据SET信号的高电平状态，使得ECS_Flag信号由低电平状态变为高电平状态；在ECS_Flag信号为高电平期间，可以根据有效的ECS_Flag信号来偷取刷新命令REFab/Self_REF，从而产生ECS命令；随后在t2时刻，根据RESET信号的高电平状态，能够使得ECS_Flag信号由高电平状态变为低电平状态。其中，ECS_Flag信号为高电平有效的脉冲信号，而且脉冲宽度能够保证在有效的ECS_Flag信号下可以偷取刷新命令REFab/Self_REF来产生ECS命令。也就是说，经过锁存模块的Latch来产生ECS_Flag信号，在ECS_Flag为有效值时偷取下一个刷新命令REFab/Self_REF用来产生ECS_CMD信号，偷取的刷新命令会消失，同时计数模块在ECS_Flag信号为有效值期间停止工作；在ECS_Flag为无效值期间刷新命令不会被影响，直接输出为REF_NEW信号，且计数器重新计数。
综上可知，在本公开实施例中，该控制电路20可以适用于所有自动ECS操作。具体地，该控制电路不仅可以解决相关技术中无法借助自刷新命令来生成ECS命令信号的技术问题，而且该控制电路在产生ECS命令信号之后，ECS命令信号经过延迟处理后作为锁存模块的复位信号，可以保证ECS_Flag信号的宽度，从而还可以保证在ECS_Flag信号有效的情况下偷取刷新命令REFab/Self_REF来产生ECS命令信号，也就解决了在计数值满足预设条件时，下一个刷新命令距离计数完成时刻距离较远而造成无法借助这个刷新命令来生成ECS命令的技术问题；另外，基于时序控制模块规划ECS操作的间隔时间，还可以准确地产生ECS命令信号，进而能够确保24小时完成所有的错误检查与清除，最终提升存储器的性能。
本公开的又一实施例中，参见图12，其示出了本公开实施例提供的一种控制方法的流程示意 图。如图12所示，该流程可以包括：
S1201：通过时序控制模块接收第一时钟信号，以及根据第一时钟信号进行计数，生成ECS标识信号，并将ECS标识信号发送给命令控制模块；其中，在计数值满足预设条件时，使ECS标识信号处于有效状态。
S1202：通过命令控制模块接收ECS标识信号，以及在ECS标识信号处于有效状态时，获取刷新命令信号，并根据刷新命令信号产生ECS命令信号。
需要说明的是，在本公开实施例中，该控制方法可以应用于前述实施例中任一项所述的控制电路20或者集成有该控制电路的半导体存储器。对于控制电路20而言，其可以包括时序控制模块和命令控制模块，而且时序控制模块的输出端与命令控制模块的输入端连接。
还需要说明的是，在本公开实施例中，对于时序控制模块而言，在ECS标识信号处于有效状态时，还可以通过时序控制模块停止计数。相应地，在一些实施例中，该方法还可以包括：
在根据刷新命令信号产生ECS命令信号之后，通过命令控制模块生成复位信号，将复位信号发送给时序控制模块，响应于复位信号，时序控制模块重新开始计数并且控制ECS标识信号处于无效状态。
进一步地，在一些实施例中，该方法还可以包括：在ECS标识信号处于无效状态时，通过命令控制模块将所接收到的刷新命令信号输出为内部刷新信号。
可以理解地，时序控制模块可以包括计数模块和译码模块。相应地，在一些实施例中，对于S1201来说，该方法还可以包括：
通过计数模块接收第一时钟信号，根据第一时钟信号进行计数，生成计数信号，计数信号用于表征计数值；
通过译码模块接收计数信号，对计数信号进行译码处理，得到目标计数信号；其中，在计数值满足预设条件时，使目标计数信号处于有效状态。
在一种可能的实施例中，计数模块包括异步二进制计数器，其中：异步二进制计数器包括若干个依次级联的触发器，每一级触发器的输入端(D)与其自身的第二输出端(/Q)连接，且每一级触发器的第二输出端(/Q)与下一级触发器的时钟端(CK)连接，第一级触发器的时钟端与第一时钟信号连接。
在另一种可能的实施例中，计数模块包括同步二进制计数器，其中：同步二进制计数器包括若干个依次级联的触发器，且若干个触发器的时钟端均与第一时钟信号连接。
在本公开实施例中，目标计数信号用于生成ECS标识信号。其中，时序控制模块还可以包括锁存模块。相应地，在一些实施例中，该方法还可以包括：
通过锁存模块接收目标计数信号，以及在目标计数信号处于有效状态时，对目标计数信号进行锁存处理，生成处于有效状态的ECS标识信号。
另外，时序控制模块还可以包括自动脉冲模块和锁存模块。相应地，在一些实施例中，该方法还可以包括：
通过自动脉冲模块接收目标计数信号，根据目标计数信号生成置位信号；其中，在目标计数信号处于有效状态时，使置位信号处于有效状态；
通过锁存模块接收置位信号，以及在置位信号处于有效状态时，根据置位信号生成处于有效状态的ECS标识信号。
还可以理解地，自动脉冲模块可以包括延迟反相模块和第一与门。相应地，在一些实施例中，该方法还可以包括：
通过延迟反相模块对目标计数信号进行延迟及反相处理，得到目标计数反相信号；
通过第一与门对目标计数反相信号和目标计数信号进行与逻辑运算，得到置位信号。
还可以理解地，命令控制模块可以包括采样模块、第一延迟模块和逻辑处理模块。相应地，在一些实施例中，对于S1201来说，该方法还可以包括：
通过采样模块接收刷新命令信号和ECS标识信号，根据刷新命令信号对ECS标识信号进行采样处理，得到采样信号；
通过第一延迟模块对刷新命令信号进行延迟处理，得到延迟刷新信号；
通过逻辑处理模块对采样信号和延迟刷新信号进行逻辑运算，在采样信号处于有效状态时，选择输出用于执行ECS操作的ECS命令信号；以及在采样信号处于无效状态时，选择输出用于执 行刷新操作的内部刷新信号。
在本公开实施例中，在ECS标识信号处于有效状态时，使采样信号处于有效状态；在ECS标识信号处于无效状态时，使采样信号处于无效状态。
还可以理解地，逻辑处理模块可以包括第一逻辑模块和第二逻辑模块。相应地，在一些实施例中，该方法还可以包括：
在采样信号处于有效状态时，通过第一逻辑模块对采样信号和延迟刷新信号进行第一逻辑运算，输出ECS命令信号；
在采样信号处于无效状态时，通过第二逻辑模块对采样信号和延迟刷新信号进行第二逻辑运算，输出内部刷新信号。
在这里，第一逻辑模块可以包括第一与非门和第一非门。相应地，在一些实施例中，该方法还可以包括：
在采样信号处于有效状态时，通过第一与非门对采样信号和延迟刷新信号进行与非逻辑运算，得到第一中间信号；
通过第一非门对第一中间信号进行非逻辑运算，得到ECS命令信号。
在这里，第二逻辑模块包括第二非门、第二与非门和第三非门。相应地，在一些实施例中，该方法还可以包括：
在采样信号处于无效状态时，通过第二非门对采样信号进行非逻辑运算，得到第二中间信号；
通过第二与非门对第二中间信号和延迟刷新信号进行与非逻辑运算，得到第三中间信号；
通过第三非门对第三中间信号进行非逻辑运算，得到内部刷新信号。
在本公开实施例中，第一延迟模块的延迟时间大于采样模块与第二非门的延迟时间之和。
还可以理解地，命令控制模块还可以包括第二延迟模块。相应地，在一些实施例中，该方法还可以包括：
通过第二延迟模块对ECS命令信号进行延迟处理，生成复位信号，并将复位信号发送给锁存模块的复位端(RST)，使计数模块重新开始计数并且控制ECS标识信号处于无效状态。
还可以理解地，控制电路还可以包括时钟产生电路。相应地，在一些实施例中，该方法还可以包括：通过时钟产生电路产生第一时钟信号。
还可以理解地，时钟产生电路可以包括振荡模块和分频模块。相应地，在一些实施例中，该方法还可以包括：
通过振荡模块输出预设频率的第二时钟信号；
通过分频模块对第二时钟信号进行n分频处理，得到第一时钟信号。
在本公开实施例中，第一时钟信号的频率为预设频率的n分之一，n为大于零的整数。
在本公开实施例中，刷新命令信号包括下述至少之一：刷新信号和自刷新信号。
本公开实施例提供了一种控制方法，根据该控制方法可以实现规划ECS操作的间隔时间，还可以准确地产生ECS命令信号，进而能够确保24小时完成所有的错误检查与清除，最终提升存储器的性能。
本公开的再一实施例中，参见图13，其示出了本公开实施例提供的一种半导体存储器的组成结构示意图。如图13所示，该半导体存储器130至少包括前述实施例任一项所述的控制电路20。
在一些实施例中，半导体存储器130可以包括DRAM。其中，对于DRAM来说，不仅可以符合DDR、DDR2、DDR3、DDR4、DDR5等内存规格，还可以符合LPDDR、LPDDR2、LPDDR3、LPDDR4、LPDDR5等内存规格，这里不作任何限定。
在本公开实施例中，对于该半导体存储器130而言，其主要涉及集成电路设计中自动错误检查与清除的电路设计，特别涉及DRAM DDR5芯片中，它需要至少每24小时对DRAM进行一次完整的错误检查与清除。DDR5技术规格中说明自动ECS操作模式需要在Refresh和Self-Refresh中规划并产生ECS命令，用来检测错误的信息同时执行内部读写检错和修复。也就是说，本公开实施例可以用于DRAM DDR5芯片中执行错误检查与清除功能的相关电路，但并不局限于此范围，其他命令规划和产生电路及计数时序控制电路均可采用本公开实施例的电路设计。
这样，对于该半导体存储器130而言，在接收第一时钟信号之后，利用第一时钟信号进行计数，只有在计数值满足预设条件时，使得ECS标识信号处于有效状态，然后获取刷新命令信号，以此产生用于执行ECS操作的ECS命令信号；从而不仅可以解决相关技术中无法借助自刷新来生 成ECS命令信号的技术问题，而且根据该控制电路还可以解决在计数值满足预设条件时下一个刷新命令距离计数完成时刻距离较远而造成无法借助这个刷新命令来生成ECS命令的技术问题，同时基于时序控制模块规划ECS操作的间隔时间，还可以准确地产生ECS命令信号，进而能够确保24小时完成所有的错误检查与清除，最终提升存储器的性能。
以上所述，仅为本公开的示例性的实施例而已，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本公开所提供的几个方法或电路实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或电路实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例在接收第一时钟信号之后，利用第一时钟信号进行计数，只有在计数值满足预设条件时，使得ECS标识信号处于有效状态，然后获取刷新命令信号，以此产生用于执行ECS操作的ECS命令信号；从而不仅可以解决相关技术中无法借助自刷新命令来生成ECS命令信号的技术问题，而且基于时序控制模块规划ECS操作的间隔时间，还可以准确地产生ECS命令信号，进而能够确保24小时完成所有的错误检查与清除，最终提升存储器的性能。

Claims (21)

  1. 一种控制电路，包括时序控制模块和命令控制模块，且所述时序控制模块的输出端与所述命令控制模块的输入端连接，其中：
    所述时序控制模块，配置为接收第一时钟信号，根据所述第一时钟信号进行计数，生成错误检查与清除ECS标识信号，并将所述ECS标识信号发送给所述命令控制模块；其中，在计数值满足预设条件时，使所述ECS标识信号处于有效状态；
    所述命令控制模块，配置为接收所述ECS标识信号，以及在所述ECS标识信号处于有效状态时，获取刷新命令信号，并根据所述刷新命令信号产生ECS命令信号。
  2. 根据权利要求1所述的控制电路，其中，
    所述时序控制模块，还配置为在所述ECS标识信号处于有效状态时，停止所述计数；
    所述命令控制模块，还配置为在根据所述刷新命令信号产生ECS命令信号之后生成复位信号，将所述复位信号发送给所述时序控制模块，响应于所述复位信号，所述时序控制模块重新开始计数并且控制所述ECS标识信号处于无效状态。
  3. 根据权利要求2所述的控制电路，其中，
    所述命令控制模块，还配置为在所述ECS标识信号处于无效状态时，将所接收到的刷新命令信号输出为内部刷新信号。
  4. 根据权利要求2所述的控制电路，其中，所述时序控制模块包括计数模块和译码模块，且所述计数模块的输出端与所述译码模块的输入端连接，其中：
    所述计数模块，配置为接收所述第一时钟信号，根据所述第一时钟信号进行计数，生成计数信号，所述计数信号用于表征计数值；
    所述译码模块，配置为接收所述计数信号，对所述计数信号进行译码处理，得到目标计数信号；其中，在所述计数值满足预设条件时，使所述目标计数信号处于有效状态。
  5. 根据权利要求4所述的控制电路，其中，所述计数模块包括异步二进制计数器，其中：
    所述异步二进制计数器包括若干个依次级联的触发器，每一级所述触发器的输入端与其自身的第二输出端连接，且每一级所述触发器的第二输出端与下一级所述触发器的时钟端连接，第一级所述触发器的时钟端与所述第一时钟信号连接。
  6. 根据权利要求4所述的控制电路，其中，所述计数模块包括同步二进制计数器，其中：
    所述同步二进制计数器包括若干个依次级联的触发器，且若干个所述触发器的时钟端均与所述第一时钟信号连接。
  7. 根据权利要求4所述的控制电路，其中，所述时序控制模块还包括锁存模块，且所述锁存模块与所述译码模块的输出端连接，其中：
    所述锁存模块，配置为接收所述目标计数信号，以及在所述目标计数信号处于有效状态时，对所述目标计数信号进行锁存处理，生成处于有效状态的所述ECS标识信号。
  8. 根据权利要求4所述的控制电路，其中，所述时序控制模块还包括自动脉冲模块和锁存模块，且所述自动脉冲模块的输入端与所述译码模块的输出端连接，所述自动脉冲模块的输出端与所述锁存模块的置位端连接，其中：
    所述自动脉冲模块，配置为根据所述目标计数信号生成置位信号；其中，在所述目标计数信号处于有效状态时，使所述置位信号处于有效状态；
    所述锁存模块，配置为接收所述置位信号，以及在所述置位信号处于有效状态时，根据所述置位信号生成处于有效状态的所述ECS标识信号。
  9. 根据权利要求8所述的控制电路，其中，所述自动脉冲模块包括延迟反相模块和第一与门，且所述第一与门的第一输入端和所述延迟反相模块的输入端均与所述译码模块的输出端连接，所述第一与门的第二输入端与所述延迟反相模块的输出端连接，所述第一与门的输出端作为所述自动脉冲模块的输出端与所述锁存模块的置位端连接，其中：
    所述延迟反相模块，配置为对所述目标计数信号进行延迟及反相处理，得到目标计数反相信号；
    所述第一与门，用于对所述目标计数反相信号和所述目标计数信号进行与逻辑运算，得到所 述置位信号。
  10. 根据权利要求2所述的控制电路，其中，所述命令控制模块包括采样模块、第一延迟模块和逻辑处理模块，其中：
    所述采样模块，配置为接收所述刷新命令信号和所述ECS标识信号，根据所述刷新命令信号对所述ECS标识信号进行采样处理，得到采样信号；
    所述第一延迟模块，配置为对所述刷新命令信号进行延迟处理，得到延迟刷新信号；
    所述逻辑处理模块，配置为对所述采样信号和所述延迟刷新信号进行逻辑运算，在所述采样信号处于有效状态时，选择输出用于执行ECS操作的ECS命令信号；以及在所述采样信号处于无效状态时，选择输出用于执行刷新操作的内部刷新信号；
    其中，在所述ECS标识信号处于有效状态时，使所述采样信号处于有效状态；在所述ECS标识信号处于无效状态时，使所述采样信号处于无效状态。
  11. 根据权利要求10所述的控制电路，其中，所述逻辑处理模块包括第一逻辑模块和第二逻辑模块，其中：
    所述第一逻辑模块，配置为在所述采样信号处于有效状态时，对所述采样信号和所述延迟刷新信号进行第一逻辑运算，输出所述ECS命令信号；
    所述第二逻辑模块，配置为在所述采样信号处于无效状态时，对所述采样信号和所述延迟刷新信号进行第二逻辑运算，输出所述内部刷新信号。
  12. 根据权利要求11所述的控制电路，其中，所述第一逻辑模块包括第一与非门和第一非门，且所述第一与非门的第一输入端与所述采样模块的输出端连接，所述第一与非门的第二输入端与所述第一延迟模块的输出端连接，所述第一与非门的输出端与所述第一非门的输入端连接，其中：
    所述第一与非门，用于在所述采样信号处于有效状态时，对所述采样信号和所述延迟刷新信号进行与非逻辑运算，得到第一中间信号；
    所述第一非门，用于对所述第一中间信号进行非逻辑运算，得到所述ECS命令信号。
  13. 根据权利要求11所述的控制电路，其中，所述第二逻辑模块包括第二与非门、第二非门和第三非门，且所述第二与非门的第一输入端与所述第二非门的输出端连接，所述第二与非门的第二输入端与所述第一延迟模块的输出端连接，所述第二与非门的输出端与所述第三非门的输入端连接，其中：
    所述第二非门，用于在所述采样信号处于无效状态时，对所述采样信号进行非逻辑运算，得到第二中间信号；
    所述第二与非门，用于对所述第二中间信号和所述延迟刷新信号进行与非逻辑运算，得到第三中间信号；
    所述第三非门，用于对所述第三中间信号进行非逻辑运算，得到所述内部刷新信号。
  14. 根据权利要求13所述的控制电路，其中，所述第一延迟模块的延迟时间大于所述采样模块与第二非门的延迟时间之和。
  15. 根据权利要求8所述的控制电路，其中，所述命令控制模块还包括第二延迟模块，其中：
    所述第二延迟模块，配置为对所述ECS命令信号进行延迟处理，生成所述复位信号，并将所述复位信号发送给所述锁存模块的复位端，使所述计数模块重新开始计数并且控制所述ECS标识信号处于无效状态。
  16. 根据权利要求1所述的控制电路，其中，所述控制电路还包括时钟产生电路，其中：
    所述时钟产生电路，用于产生所述第一时钟信号。
  17. 根据权利要求16所述的控制电路，其中，所述时钟产生电路包括振荡模块和分频模块，其中：
    所述振荡模块，配置为输出预设频率的第二时钟信号；
    所述分频模块，配置为对所述第二时钟信号进行n分频处理，得到所述第一时钟信号；
    其中，所述第一时钟信号的频率为所述预设频率的n分之一，n为大于零的整数。
  18. 根据权利要求1至17任一项所述的控制电路，其中，所述刷新命令信号包括下述至少之一：刷新信号和自刷新信号。
  19. 一种控制方法，所述方法包括：
    通过时序控制模块接收第一时钟信号，以及根据所述第一时钟信号进行计数，生成ECS标识 信号，并将所述ECS标识信号发送给命令控制模块；其中，在计数值满足预设条件时，使所述ECS标识信号处于有效状态；
    通过所述命令控制模块接收所述ECS标识信号，以及在所述ECS标识信号处于有效状态时，获取刷新命令信号，并根据所述刷新命令信号产生ECS命令信号。
  20. 一种半导体存储器，所述半导体存储器包括如权利要求1至18任一项所述的控制电路。
  21. 根据权利要求20所述的半导体存储器，其中，所述半导体存储器包括动态随机存取存储器DRAM。
PCT/CN2022/126383 2022-10-08 2022-10-20 控制电路、控制方法以及半导体存储器 Ceased WO2024073903A1 (zh)

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