WO2024087401A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2024087401A1
WO2024087401A1 PCT/CN2023/071888 CN2023071888W WO2024087401A1 WO 2024087401 A1 WO2024087401 A1 WO 2024087401A1 CN 2023071888 W CN2023071888 W CN 2023071888W WO 2024087401 A1 WO2024087401 A1 WO 2024087401A1
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WO
WIPO (PCT)
Prior art keywords
common
sub
electrically connected
gate
pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/071888
Other languages
English (en)
French (fr)
Other versions
WO2024087401A9 (zh
Inventor
袁志东
袁粲
张大成
李永谦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei BOE Joint Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei BOE Joint Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/CN2022/128241 external-priority patent/WO2024087166A1/zh
Priority claimed from PCT/CN2022/128244 external-priority patent/WO2024087167A1/zh
Priority claimed from PCT/CN2022/128272 external-priority patent/WO2024087173A1/zh
Application filed by BOE Technology Group Co Ltd, Hefei BOE Joint Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202380008169.9A priority Critical patent/CN118284975A/zh
Priority to EP23881007.1A priority patent/EP4465361A4/en
Priority to US18/555,023 priority patent/US20250095571A1/en
Publication of WO2024087401A1 publication Critical patent/WO2024087401A1/zh
Publication of WO2024087401A9 publication Critical patent/WO2024087401A9/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0204—Compensation of DC component across the pixels in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • At least one embodiment of the present disclosure provides a display substrate, which has a plurality of display partitions arranged in a plurality of rows and columns, at least one of the plurality of display partitions includes a plurality of sub-pixels, the display substrate includes a base substrate and a common scan signal line, the common scan signal line is arranged on the base substrate, including a plurality of first common scan signal lines extending along a first direction and a plurality of second common scan signal lines extending along a second direction, wherein the first direction is different from the second direction; wherein each of the plurality of second common scan signal lines is respectively electrically connected to a first common scan signal line of the plurality of first common scan signal lines, and is configured to provide a common scan signal to one of the plurality of display partitions.
  • the multiple first common scanning signal lines and the multiple second common scanning signal lines are arranged in different layers and have a first overlapping portion in a direction perpendicular to the base substrate
  • the display substrate also includes an auxiliary electrode arranged on a side of the common scanning signal line away from the base substrate, and the auxiliary electrode overlaps with the first overlapping portion in a direction perpendicular to the base substrate.
  • the sub-pixel includes a pixel driving circuit and a light-emitting device electrically connected to the pixel driving circuit
  • the light-emitting device includes a first electrode electrically connected to the pixel driving circuit, a light-emitting material layer arranged on a side of the first electrode away from the base substrate, and a second electrode arranged on a side of the light-emitting material layer away from the base substrate, wherein the auxiliary electrode is arranged on the same layer as the first electrode and is electrically connected to the second electrode.
  • the pixel driving circuit includes a first transistor, the first transistor includes a first gate, a first source and a first drain, the multiple first common scanning signal lines are arranged in the same layer as the first gate, and the first gate is electrically connected to one of the multiple second common scanning signal lines.
  • the display substrate provided by at least one embodiment of the present disclosure also includes: a plurality of data lines and a plurality of first power lines, the plurality of data lines respectively extending along the first direction and configured to provide data signals to the plurality of sub-pixels, and the plurality of first power lines respectively extending along the first direction and configured to provide first power signals to the plurality of sub-pixels, wherein the orthographic projection of at least a portion of at least one of the plurality of first common scanning signal lines on the base substrate is located between the orthographic projections of an adjacent data line and a first power line on the base substrate; and at least one of the plurality of first power lines is electrically connected to the auxiliary electrode.
  • the display substrate provided by at least one embodiment of the present disclosure also includes: a plurality of second power lines, respectively extending along the first direction, and configured to provide a second power signal to the plurality of sub-pixels, wherein the potential of the second power signal is higher than the potential of the first power signal; the plurality of first power lines and the plurality of second power lines are arranged in the same layer, and are alternately arranged along the second direction.
  • the plurality of data lines and the plurality of first power lines are arranged in the same layer and are arranged on a side of the first drain electrode away from the base substrate.
  • the plurality of sub-pixels include a plurality of repeating units arranged in an array, each of the plurality of repeating units includes a plurality of sub-pixels with different luminous colors; and the orthographic projection of at least a portion of at least one of the plurality of first common scanning signal lines on the base substrate is located between the orthographic projections of the pixel driving circuits of adjacent repeating units on the base substrate.
  • the plurality of sub-pixels include Including red sub-pixels, green sub-pixels and blue sub-pixels, at least a portion of at least one of the plurality of first common scan signal lines has an orthographic projection on the substrate that is located between an adjacent data line that provides a data signal to the blue sub-pixel and an orthographic projection of a first power line on the substrate.
  • the pixel driving circuit also includes a second transistor, the second transistor includes a second gate and a second source and a drain arranged on a side of the second gate away from the base substrate, the display substrate also includes a plurality of first scanning signal lines, the second gate is electrically connected to one of the plurality of first scanning signal lines, the second source is electrically connected to one of the plurality of data lines, and the second drain is electrically connected to the first source.
  • the pixel driving circuit also includes a first capacitor, the first capacitor includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode is electrically connected to the first drain, and the second capacitor electrode is electrically connected to the first electrode; the first capacitor electrode includes a first part arranged on the same layer as the first gate and a second part arranged on the same layer as the first drain.
  • the orthographic projection of at least one of the plurality of second common scan signal lines on the base substrate is located between an adjacent first scan signal line and the orthographic projection of the first capacitor electrode on the base substrate.
  • the pixel driving circuit also includes a first common transistor, which is shared by at least two adjacent sub-pixels, and the first common transistor includes a first common gate and a first common source and a first common drain arranged on a side of the first common gate away from the base substrate, and the first common gate is electrically connected to one of the multiple first common scanning signal lines.
  • the first common transistor also includes a first common active layer
  • the multiple sub-pixels include a plurality of repeating units arranged in an array, each of the multiple repeating units includes a plurality of sub-pixels with different luminous colors
  • the orthographic projection of the first common active layer on the base substrate is located between the orthographic projections of the pixel driving circuits of adjacent repeating units on the base substrate.
  • one of the plurality of first common scan signal lines in a direction perpendicular to the base substrate, has a second overlapping portion with the first common active layer, and the second overlapping portion serves as the first common gate.
  • the multiple sub-pixels include red sub-pixels, green sub-pixels and blue sub-pixels, with one red sub-pixel, one green sub-pixel and one blue sub-pixel as a repeating unit, and the first common transistor is shared by at least two adjacent repeating units.
  • a plurality of second common scanning signal lines located in the same row are spaced apart from each other.
  • the plurality of first common scanning signal lines and the plurality of second common scanning signal lines are arranged in the same layer, and are arranged in the same layer as the first gate.
  • each display partition is provided with at least one reset voltage line, one first common scanning signal line and one reference voltage line, and the reset voltage line, the first common scanning signal line and the reference voltage line are respectively located between different sub-pixels.
  • the plurality of sub-pixels include a plurality of repeating units arranged in an array, and at least one of the repeating units includes a red sub-pixel, a green sub-pixel and a blue sub-pixel, wherein the orthographic projection of the first electrode of the light-emitting device of the red sub-pixel on the substrate substrate at least partially overlaps with the orthographic projection of a data line and a reference voltage line on the substrate substrate; the orthographic projection of the first electrode of the light-emitting device of the blue sub-pixel on the substrate substrate at least partially overlaps with the orthographic projection of a data line on the substrate substrate; the orthographic projection of the first electrode of the light-emitting device of the green sub-pixel on the substrate substrate at least partially overlaps with the orthographic projection of a data line and a first power line on the substrate substrate.
  • the plurality of sub-pixels include a plurality of repeating units arranged in an array, each of the plurality of repeating units includes a red sub-pixel, a green sub-pixel and a blue sub-pixel, and the orthographic projection of at least one of the plurality of first common scanning signal lines on the base substrate is located between the orthographic projections of an adjacent data line that provides a data signal to the blue sub-pixel and a data line that provides a data signal to the green sub-pixel on the base substrate.
  • the sub-pixel includes a pixel driving circuit and a light-emitting device electrically connected to the pixel driving circuit
  • the pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a a transistor, a sixth transistor, a first common transistor and a first capacitor
  • the first transistor comprising a first gate, a first source and a first drain, the first gate being electrically connected to the second common scan signal line
  • the second transistor comprising a second gate, a second source and a second drain, the second gate being electrically connected to the first scan signal line, the second source being electrically connected to the data line, the second drain being electrically connected to the first source
  • the third transistor comprising a third gate, a third source and a third drain, the third gate being electrically connected to the third scan signal line
  • the fourth transistor comprising a fourth gate, a fourth source and a fourth drain, the fourth gate being
  • At least one embodiment of the present disclosure further provides a display device, which includes the display substrate provided by the embodiment of the present disclosure.
  • FIG1 is a simplified schematic diagram of a common scan signal line of a display substrate provided by at least one embodiment of the present disclosure
  • FIG2 is a pixel driving circuit diagram of a sub-pixel of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 3 is a partial cross-sectional schematic diagram of a sub-pixel of a display substrate provided by at least one embodiment of the present disclosure
  • 4 to 11B are plan views of various functional layers of a display substrate provided by at least one embodiment of the present disclosure and plan views of various functional layers stacked in sequence;
  • FIG12 is another schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG13 is a schematic plan view of another display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 14 is a schematic plan view of yet another display substrate provided by at least one embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides a display substrate and a display device, wherein the display substrate has a plurality of display partitions arranged in a plurality of rows and columns, at least one of the plurality of display partitions includes a plurality of sub-pixels, the display substrate includes a base substrate and a common scan signal line, the common scan signal line is arranged on the base substrate, including a plurality of first common scan signal lines extending along a first direction and a plurality of second common scan signal lines extending along a second direction, wherein the first direction is different from the second direction; each of the plurality of second common scan signal lines is respectively electrically connected to a first common scan signal line among the plurality of first common scan signal lines, and is configured to provide a common scan signal to one of the plurality of display partitions.
  • the above-mentioned display substrate provided in the embodiment of the present disclosure can use a common scanning signal line to realize regional control of the display substrate, so that each display partition can be refreshed separately in one frame time without affecting other partitions, thereby improving the overall refresh frequency of the display substrate and realizing high-resolution (PPI) display.
  • PPI high-resolution
  • FIG1 shows a simplified schematic diagram of a common scanning signal line of the display substrate.
  • FIG2 shows a pixel driving circuit diagram of a sub-pixel of the display substrate.
  • FIG3 shows a partial cross-sectional schematic diagram of a sub-pixel of the display substrate.
  • the display substrate has a plurality of display partitions DA arranged in a plurality of rows and columns, and at least one (for example, each) of the plurality of display partitions DA includes a plurality of sub-pixels.
  • the display substrate includes a base substrate 101 and common scan signal lines, and the common scan signal lines are arranged on the base substrate 101, including a plurality of first common scan signal lines Gcom1 extending along a first direction (vertical direction in the figure) and a plurality of second common scan signal lines Gcom2 extending along a second direction (horizontal direction in the figure).
  • the first direction is different from the second direction, for example, the first direction is perpendicular to the second direction.
  • the first direction is the column direction of the plurality of display partitions DA
  • the second direction is the row direction of the plurality of display partitions DA
  • the first direction may also be the row direction of the plurality of display partitions DA
  • the second direction may be the column direction of the plurality of display partitions DA.
  • each of the second common scan signal lines Gcom2 is electrically connected to one of the plurality of first common scan signal lines Gcom1 , and is configured to provide a common scan signal to one of the plurality of display partitions DA.
  • a plurality of first common scan signal lines Gcom1 are respectively configured to provide common scan signals to a plurality of columns of display partitions DA, that is, each first common scan signal line Gcom1 is configured to provide a common scan signal to a display partition DA located in the same column.
  • each display partition DA has at least one second common scan signal line Gcom2, for example, a plurality of second common scan signal lines Gcom2, and each second common scan signal line Gcom2 is configured to provide a common scan signal to sub-pixels located in the same row in the display partition DA.
  • the plurality of first common scan signal lines Gcom1 and the plurality of The second common scan signal line Gcom2 is arranged in a different layer, that is, it is not arranged in the same layer in the hierarchical structure of the display substrate, and the multiple first common scan signal lines Gcom1 and the multiple second common scan signal lines Gcom2 have a first overlapping portion OV1 (refer to FIG. 8B later) in a direction perpendicular to the base substrate 101 (that is, in the vertical direction in FIG. 3 ).
  • the display substrate also includes an auxiliary electrode A1 (refer to FIG. 11A later) arranged on the side of the common scan signal line away from the base substrate 101, and the auxiliary electrode A1 overlaps with the first overlapping portion OV1 in a direction perpendicular to the base substrate 101.
  • the auxiliary electrode A1 can be electrically connected to the second electrode E1 of the light-emitting device EM through a via hole, and can be electrically connected to the first power line (described in detail later) through a via hole, thereby connecting the first power line and the second electrode E1 in parallel. Since the square resistance of the second electrode E1 is often large in a large-size display substrate, the voltage at different positions of the display substrate is different, such as local potential rise and other undesirable phenomena, thereby affecting the display.
  • the second electrode E1 By connecting the second electrode E1 to the first power line through the auxiliary electrode A1, most of the current of the second electrode E1 can be provided through the first power line electrically connected to the auxiliary electrode A1, thereby greatly reducing the influence of the large square resistance of the second electrode E1, so that the second electrodes E1 of the light-emitting devices of multiple sub-pixels on the display substrate can obtain substantially the same power signal.
  • each sub-pixel includes a pixel driving circuit D and a light-emitting device EL electrically connected to the pixel driving circuit D
  • the light-emitting device EL includes a first electrode E1 electrically connected to the pixel driving circuit D, a light-emitting material layer E2 arranged on a side of the first electrode E1 away from the base substrate 101, and a second electrode E3 arranged on a side of the light-emitting material layer E2 away from the base substrate 101, for example, the auxiliary electrode A1 is arranged on the same layer as the first electrode E1.
  • the pixel driving circuit includes a first transistor T1, and the first transistor T1 includes a first gate T1g, a first source T1s, and a first drain T1d.
  • the first transistor T1 includes a first gate T1g, a first source T1s, and a first drain T1d.
  • a plurality of first common scanning signal lines Gcom1 are disposed on the same layer as the first gate T1g, and a plurality of second common scanning signal lines Gcom2 are disposed on the same layer as the first drain T1d.
  • “same-layer arrangement” means that two (or more) functional layers or structural layers are in the same layer and are formed of the same material in the hierarchical structure of the display substrate, that is, in the preparation process, the two (or more) functional layers or structural layers can be formed by the same material layer, and the required patterns and structures can be formed by the same composition process.
  • the first gate T1g of the first transistor T1 is electrically connected to a first
  • the second common scanning signal line Gcom2 receives the common scanning signal from the second common scanning signal line Gcom2.
  • the first transistor T1 can serve as a partition control circuit configured to apply at least one of a data voltage provided by the data line data and a reference voltage provided by the reference line voltage line Vref to the sixth gate T6g of the sixth transistor T6 in response to a common scan signal provided by the second common scan signal line Gcom2.
  • the pixel driving circuit also includes a second transistor T2, the second transistor T2 includes a second gate T2g and a second source T2s and a second drain T2d arranged on the side of the second gate T2g away from the base substrate 101, the display substrate also includes a plurality of first scanning signal lines G1, the second gate T2g is electrically connected to one of the plurality of first scanning signal lines G1, the second source T2s is electrically connected to one of the plurality of data lines data, and the second drain T2d is electrically connected to the first source T1s of the first transistor T1.
  • the second transistor T2 may be used as a data writing circuit configured to apply a data voltage provided by the data line data to the sixth gate T6g of the sixth transistor T6 in response to a first control signal provided by the first scan signal line G1.
  • the pixel driving circuit further includes a first capacitor C1, the first capacitor C1 includes a first capacitor electrode C11 and a second capacitor electrode C12, the first capacitor electrode C11 is electrically connected to the first drain electrode T1d of the first transistor T1, and the second capacitor electrode C12 is electrically connected to the first electrode E1 of the light emitting device EL.
  • the first capacitor C1 can be used as a storage capacitor.
  • the second transistor T2 can be turned on in response to the first scanning signal so that the data signal can be written, the first transistor T1 is turned on in response to the common scanning signal, the data signal is written into the sixth transistor T6 through the turned-on first transistor T1, and the data signal is stored in the first capacitor C1, so that in the light emitting stage, for example, a driving current for driving the light emitting device EL to emit light can be generated according to the data signal.
  • the pixel driving circuit also includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a first common transistor T7, and the first common transistor T7 is shared by at least two adjacent sub-pixels SP, that is, at least two adjacent sub-pixels SP located in the same display area DA.
  • the fourth transistor T4 includes a fourth gate T4g and a fourth source T4s and a fourth drain T4d arranged on the side of the fourth gate T4g away from the substrate, the display substrate further includes a plurality of second scanning signal lines G2 and a plurality of reference voltage lines Vref, and the fourth gate T4g is electrically connected to the plurality of second scanning signal lines G2 and the plurality of reference voltage lines Vref.
  • the fourth source T4s is electrically connected to one of the second scan signal lines G2, the fourth drain T4d is electrically connected to the first source T1s of the first transistor T1 and the second drain T2d of the second transistor T2, and the fourth drain T4d is electrically connected to one of the plurality of reference voltage lines Vref.
  • the fourth transistor T4 may be used as a reset circuit, and is configured to apply a reference voltage signal provided by the reference voltage line Vref in response to the second scan signal provided by the second scan signal line G2 to implement a voltage reset function.
  • the third transistor T3 includes a third gate T3g and a third source T3s and a third drain T3d arranged on the side of the third gate T3g away from the base substrate 101.
  • the display substrate also includes multiple third scanning signal lines G3.
  • the third gate T3g is electrically connected to one of the multiple third scanning signal lines G3.
  • the third source T3s is electrically connected to the sixth drain T6d of the sixth transistor T6 (to be introduced later).
  • the third drain T3d is electrically connected to the first common drain T7d of the first common transistor T7 (to be introduced later).
  • the fifth transistor T5 includes a fifth gate T5g and a fifth source T5s and a fifth drain T5d arranged on the side of the fifth gate T5g away from the substrate 101, the fifth gate T5g is electrically connected to the light control signal line EM, the fifth source T5s is electrically connected to the sixth drain T6d of the sixth transistor T6, and the fifth drain T5d is electrically connected to the second power line VDD.
  • the fifth transistor T5 can be used as a light emitting control circuit, configured to apply the second power supply voltage provided by the second power supply line VDD to the sixth transistor T6 in response to the light emitting control signal provided by the light emitting control line EM.
  • the fifth transistor T5 can be turned on in response to the light emitting control signal, so that the second power supply voltage can be applied to the sixth transistor T6.
  • the sixth transistor T6 applies the second power supply voltage to the light emitting device EL to provide a driving voltage, thereby driving the light emitting device EL to emit light.
  • the fifth transistor T5 may also be shared by at least two adjacent sub-pixels, for example, in some embodiments, the fifth transistor T5 may be shared by at least two adjacent repeating units.
  • the sixth transistor T6 includes a sixth gate T6g and a sixth source T6s and a sixth drain T6d arranged on the side of the sixth gate T6g away from the substrate 101, the sixth gate T6g is electrically connected to the first drain T1d of the first transistor T1 and the first capacitor electrode C11 of the first capacitor C1, the sixth source T6s is electrically connected to the first electrode E1 of the light-emitting device EL and the second capacitor electrode C12 of the first capacitor C1, and the sixth drain T6d is electrically connected to the fifth source T5s of the fifth transistor T5 and the third source T3s of the third transistor T3.
  • the sixth transistor T6 can be used as a driving circuit of the light emitting device EL.
  • the sixth transistor T6 can provide a driving current to the light emitting device EL to drive the light emitting device EL to emit light, and can emit light according to the required “gray scale”.
  • the first common transistor T7 includes a first common gate T7g and a first common source T7s and a first common drain T7d arranged on a side of the first common gate T7g away from the base substrate 101, the first common gate T7g is electrically connected to one of the multiple first common scanning signal lines Gcom1, the display substrate also includes multiple reset voltage lines Vini, the first common source T7s is electrically connected to one of the multiple reset voltage lines Vini, and the first common drain T7d is electrically connected to the third drain T3d of the third transistor T3 in the pixel driving circuit of the multiple sub-pixels SP.
  • the third transistor T3 and the first common transistor T7 can be used as another reset circuit.
  • the reset signal can be written into one end of the sixth transistor T6 to reset it.
  • an intrinsic capacitor Coled may be formed between the first electrode E1 and the second electrode E2 of the light emitting device EL.
  • the source and drain of each transistor are symmetrical in structure, and their functions and connection methods can be interchanged.
  • the first transistor T1 can be used as a partition control circuit for displaying the partition DA, and is configured to respond to the common scanning signal provided by the second common scanning signal line Gcom2, and apply at least one of the data voltage provided by the data line data and the reference voltage provided by the reference line voltage line Vref to the sixth gate T6g of the sixth transistor T6.
  • the sixth transistor T6 can be used as a driving circuit for the light-emitting device EL, and the first common transistor T7 is configured to respond to the common scanning signal provided by the first common scanning signal line Gcom1 and the third scanning signal provided by the third scanning signal line G3.
  • the reset voltage provided by the reset voltage line Vini is applied to the sixth transistor T6, so that the pixel driving circuit can realize partition display.
  • the first transistor T1 partition control circuit
  • the first common transistor T7 reset circuit
  • the pixel driving circuit can achieve partition display, for example, updating a certain display partition screen separately, while the display screens of other display areas are not updated, which is conducive to achieving an ultra-high refresh rate of the display partition. Reduce the overall power consumption of the display substrate.
  • the active layer of each transistor (the sixth active layer T6a of the sixth transistor T6 connected to the light-emitting device EL is shown in Figure 3) is arranged on the same layer on the base substrate 101.
  • This functional layer can also be called the semiconductor layer of the display substrate, and a first gate insulating layer GI1 is arranged on the semiconductor layer.
  • the first capacitor electrode C11 of the first capacitor C1 includes two parts respectively overlapping with the second capacitor electrode C12, and the gate of each transistor (the sixth gate T6g of the sixth transistor T6 is shown in the figure) and the first part of the first capacitor electrode C11 of the first capacitor C1 are arranged on the first gate insulating layer GI1 in the same layer, and the functional layer can also be called the first gate metal layer of the display substrate, and the second gate insulating layer GI2 is arranged on the first gate metal layer.
  • the second capacitor electrode C12 is arranged on the first gate insulating layer GI1, and the functional layer can also be called the second gate metal layer of the display substrate, and the interlayer insulating layer IDL is arranged on the second gate metal layer.
  • each transistor the sixth source T6s and the sixth drain T6d of the sixth transistor T6 are shown in the figure
  • another part C13 of the first capacitor electrode C11 that is, the second part
  • This functional layer can also be called the first source and drain metal layer of the display substrate.
  • the first passivation layer PVX1 and the first planarization layer PLN1 are arranged on the first source and drain metal layer.
  • the display substrate further includes a connection electrode CL disposed on the first planarization layer PLN1, the connection electrode CL is used to electrically connect the first electrode E1 of the light emitting device EL to the pixel driving circuit D, and the functional layer where the connection electrode CL is located may also be referred to as a second source-drain metal layer.
  • a second planarization layer PLN2 is disposed on the second source-drain metal layer, and the first electrode E1 of the light emitting device EL is disposed on the second planarization layer PLN2.
  • the display substrate further includes a pixel defining layer PDL disposed on the first electrode E1 of the light emitting device EL, the pixel defining layer PDL includes a plurality of sub-pixel openings for defining the light emitting areas of the plurality of sub-pixels, and the light emitting material layer E2 is at least disposed in the sub-pixel openings.
  • the second electrodes E3 of the plurality of light emitting devices EL are integrated electrodes disposed continuously, and an encapsulation layer EN is disposed above the second electrodes E3 to achieve encapsulation of the display substrate.
  • the encapsulation layer EN may be a composite encapsulation layer including a plurality of inorganic encapsulation layers and an organic encapsulation layer to improve the encapsulation effect of the display substrate.
  • FIG. 4 to FIG. 11B show a display substrate provided by at least one embodiment of the present disclosure. Schematic diagram of the plan of each functional layer and the schematic diagram of the plan of each functional layer superimposed in sequence.
  • FIG. 4 shows a schematic plan view of a semiconductor layer of a display substrate.
  • the semiconductor layer includes active layers T1 a - T7 a of various transistors.
  • the first active layer T1a of the first transistor T1, the second active layer T2a of the second transistor T2, and the fourth active layer T4a of the fourth transistor T4 are connected as one
  • the third active layer T3a of the third transistor T3, the fifth active layer T5a of the fifth transistor T5, and the sixth active layer T6a of the sixth transistor T6 are connected as one
  • the first common active layer T7a of the first common transistor T7 is separately provided, and since the first common transistor T7 is shared by at least two sub-pixels, the arrangement density of the first common active layer T7a is less than the arrangement density of the above-mentioned active layers T1a-T6a.
  • the display substrate includes a plurality of sub-pixels including a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B
  • the orthographic projection of the first common active layer T7a on the base substrate 101 is located between the orthographic projections of the pixel driving circuits of the adjacent green sub-pixel G and the blue sub-pixel B on the base substrate 101.
  • the orthographic projection of the first common active layer T7a on the base substrate 101 is located between the orthographic projections of the active layers T1a-T6a of each transistor of the adjacent green sub-pixel G and the blue sub-pixel B on the base substrate 101.
  • the plurality of sub-pixels include a plurality of repeating units arranged in an array, each repeating unit includes a plurality of sub-pixels with different luminous colors, such as a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, the orthographic projection of the first common active layer T7a on the base substrate 101 is located between the orthographic projections of the pixel driving circuits of two adjacent repeating units on the base substrate 101, and the first common transistor T7 is shared by at least two adjacent repeating units, that is, shared by six sub-pixels.
  • the first common transistor T7 may also be configured to be shared by three or more repeating units.
  • the planar shape of the first common active layer T7 a may be a bent shape having a right-angle turn.
  • FIG. 5A is a schematic plan view of a first gate metal layer of a display substrate
  • FIG. 5B is a schematic plan view of a first gate metal layer of a display substrate after being superimposed on a semiconductor layer.
  • the first gate metal layer includes the gates T1g-T7g of each transistor, a portion of the first capacitor electrode C11, the reset voltage line Vini, the first common scan signal line Gcom1, and the reference voltage line Vref.
  • the signal line Gcom1 and the reference voltage line Vref both extend along a first direction (ie, a vertical direction in the figure).
  • an orthographic projection of at least a portion of at least one of the plurality of first common scanning signal lines Gcom1 on the base substrate 101 is located between orthographic projections of pixel driving circuits of adjacent repeating units on the base substrate 101 .
  • each display partition DA is provided with at least one reset voltage line Vini, one first common scanning signal line Gcom1 and one reference voltage line Vref.
  • the reset voltage line Vini, the first common scanning signal line Gcom1 and the reference voltage line Vref are respectively located between different sub-pixels.
  • the reset voltage line Vini extends between the pixel driving circuits of the adjacent blue sub-pixel B and the red sub-pixel R, that is, the orthographic projection of the reset voltage line Vini on the substrate is located between the orthographic projections of the pixel driving circuits of the adjacent blue sub-pixel B and the red sub-pixel R on the substrate;
  • the first common scanning signal line Gcom1 extends between the pixel driving circuits of the adjacent blue sub-pixel B and the green sub-pixel G, that is, the orthographic projection of the first common scanning signal line Gcom1 on the substrate is located between the orthographic projections of the pixel driving circuits of the adjacent blue sub-pixel B and the green sub-pixel G on the substrate;
  • the reference voltage line Vref extends between the pixel driving circuits of the adjacent blue sub-pixel B and the red sub-pixel R, that is, the orthographic projection of the reference voltage line Vref on the substrate is located between the orthographic projections of the pixel driving circuits of the adjacent blue sub-pixel B and the red sub-pixel R
  • the first common scanning signal line Gcom1 and the first common active layer T7a have a second overlapping portion (i.e., the portion indicated by label T7g in FIG. 5B ), and the second overlapping portion serves as the first common gate T7g, so that the first common gate T7g is also located between the pixel driving circuits of the adjacent blue sub-pixel B and the green sub-pixel G.
  • the first capacitor electrode C11 is connected to the sixth gate electrode T6g of the sixth transistor as a whole.
  • FIG6A shows a schematic plan view of a second gate metal layer of a display substrate
  • FIG6B shows a schematic plan view of the second gate metal layer of the display substrate after being superimposed on the first gate metal layer and the semiconductor layer.
  • the second gate metal layer includes a second capacitor electrode C12 .
  • the second capacitor electrode C12 is connected to the first capacitor electrode C12 .
  • the capacitor electrodes C11 overlap to form a first capacitor C1.
  • FIG. 7A shows a schematic plan view of an interlayer insulating layer of a display substrate
  • FIG. 7B shows a schematic plan view of an interlayer insulating layer of a display substrate superimposed with a second gate metal layer, a first gate metal layer, and a semiconductor layer.
  • the interlayer insulating layer includes a plurality of vias, such as a first via V1 for electrically connecting the first common scanning signal line Gcom1 with the second common scanning signal line Gcom2, a second via V2 for electrically connecting the reference voltage line Vref extending along the first direction with the reference voltage line Vref1 extending along the second direction, a third via V3 for electrically connecting the reset voltage line Vini extending along the first direction with the reset voltage line Vini1 extending along the second direction, and other vias for circuit connection of various transistors, which are not described in detail here.
  • a first via V1 for electrically connecting the first common scanning signal line Gcom1 with the second common scanning signal line Gcom2
  • a second via V2 for electrically connecting the reference voltage line Vref extending along the first direction with the reference voltage line Vref1 extending along the second direction
  • a third via V3 for electrically connecting the reset voltage line Vini extending along the first direction with the reset voltage line Vini1 extending along the second direction
  • FIG8A shows a plan view schematic diagram of a first source/drain metal layer of a display substrate
  • FIG8B shows a plan view schematic diagram of the first source/drain metal layer of the display substrate superimposed with an interlayer insulating layer, a second gate metal layer, a first gate metal layer, and a semiconductor layer.
  • the first source and drain metal layer includes a reference voltage line Vref1 extending along the second direction, a first scan signal line G1, a second scan signal line G2, a third scan signal line G3, a reset voltage line Vini1, a second common scan signal line Gcom2, a light emitting control signal line EM, a second power supply voltage line VDD1 and another part C13 of the first capacitor electrode C11.
  • the orthographic projection of at least one of the plurality of second common scanning signal lines Gcom2 on the base substrate 101 is located between the orthographic projections of an adjacent first scanning signal line G1 and the first capacitor electrode C11 on the base substrate 101 .
  • the reference voltage line Vref1, the second scanning signal line G2, the first scanning signal line G1, the second common scanning signal line Gcom2, the first capacitor electrode C11, the reset voltage line Vini1, the third scanning signal line G3, the light emitting control signal line EM and the second power supply voltage line VDD1 are arranged in sequence along the first direction.
  • the plurality of first common scanning signal lines Gcom1 and the plurality of second common scanning signal lines Gcom2 have a first overlapping portion OV1 in a direction perpendicular to the base substrate 101 .
  • FIG. 9A shows a schematic plan view of a first passivation layer and a first planarization layer of a display substrate
  • FIG. 9B shows a schematic plan view of a first passivation layer and a first planarization layer of a display substrate and a first source layer.
  • the first passivation layer PVX1 and the first planarization layer PLN1 include multiple vias, such as via PN1 that electrically connects the pixel driving circuit to the connecting electrode CL, via PN2 that electrically connects the second power line VDD1 extending along the second direction to the second power line VDD extending along the first direction, and via PN3 that electrically connects the data line data to the pixel driving circuit.
  • via PN1 that electrically connects the pixel driving circuit to the connecting electrode CL
  • via PN2 that electrically connects the second power line VDD1 extending along the second direction to the second power line VDD extending along the first direction
  • PN3 that electrically connects the data line data to the pixel driving circuit.
  • Figure 10A shows a plan schematic diagram of the second source and drain metal layer of the display substrate
  • Figure 10B shows a plan schematic diagram of the second source and drain metal layer of the display substrate after being superimposed with the first passivation layer and the first planarization layer, the first source and drain metal layer, the interlayer insulating layer, the second gate metal layer, the first gate metal layer, and the semiconductor layer.
  • the second source-drain metal layer includes a first power line VSS, a second power line VDD, a data line data, and a connection electrode CL.
  • multiple data lines data are configured to provide data signals to multiple sub-pixels, such as data line dataR providing data signals for red sub-pixels, data line dataB providing data signals for blue sub-pixels, and data line dataG providing data signals for green sub-pixels.
  • a plurality of first power lines VSS and a plurality of data lines data extend along a first direction respectively, and the plurality of first power lines VSS are configured to provide a first power signal, such as a low-level power signal, such as a ground signal, to a plurality of sub-pixels.
  • the plurality of first power lines VSS are electrically connected to the second electrodes E3 of the light-emitting devices EL of the sub-pixels respectively.
  • At least a portion of at least one of the plurality of first common scan signal lines Gcom1 has an orthographic projection on the base substrate 101 located between orthographic projections of an adjacent data line data and a first power line VSS on the base substrate 101 .
  • the orthographic projection of at least a portion of at least one of the multiple first common scan signal lines Gcom1 on the base substrate 101 is located between the orthographic projections of an adjacent data line dataB that provides a data signal to a blue sub-pixel and a first power line VSS on the base substrate 101.
  • a plurality of second power lines VDD extend along the first direction and are configured to provide a second power signal, such as a high-level power signal, to a plurality of sub-pixels, wherein the potential of the second power signal is higher than the potential of the first power signal.
  • the plurality of second power lines VDD are electrically connected to the first electrodes E1 of the light-emitting devices EL of the sub-pixels, respectively.
  • first power lines VSS and multiple second power lines VDD are arranged in the same layer, that is, in the second source and drain metal layer, and are alternately arranged along the second direction (horizontal direction in the figure), that is, a second power line VDD is arranged between two adjacent first power lines VSS, and a first power line VSS is arranged between two adjacent second power lines VDD.
  • the plurality of data lines data and the plurality of first power lines VSS are disposed in the same layer and are disposed on a side of the first source T1s and the first drain T1d away from the base substrate 101 .
  • Figure 11A shows a plan schematic diagram of the first electrode layer of the display substrate
  • Figure 11B shows a plan schematic diagram of the first electrode layer of the display substrate after being superimposed with the second source and drain metal layer, the first passivation layer and the first planarization layer, the first source and drain metal layer, the interlayer insulating layer, the second gate metal layer, the first gate metal layer, and the semiconductor layer.
  • the first electrode layer includes a first electrode E1 of the light emitting device EL and an auxiliary electrode A1, and the auxiliary electrode A1 at least partially overlaps with the first overlapping portion OV1 in a direction perpendicular to the base substrate 101.
  • the auxiliary electrode A1 is a polygon with chamfered or rounded corners as a whole.
  • the orthographic projection of the auxiliary electrode A1 on the base substrate 101 is located between the orthographic projections of the first electrodes E1 of the light emitting devices EL of the adjacent blue sub-pixel and green sub-pixel on the base substrate 101 .
  • the orthographic projection of the first electrode E1 of the light-emitting device of the red sub-pixel R on the substrate substrate 101 at least partially overlaps with the orthographic projection of a data line data and a reference voltage line Vref on the substrate substrate 101;
  • the orthographic projection of the first electrode E1 of the light-emitting device of the blue sub-pixel B on the substrate substrate 101 at least partially overlaps with the orthographic projection of a data line data on the substrate substrate 101;
  • the orthographic projection of the first electrode E1 of the light-emitting device of the green sub-pixel G on the substrate substrate 101 at least partially overlaps with the orthographic projection of a data line data and a first power line VSS on the substrate substrate 101.
  • a light-emitting material layer such as a light-emitting material layer, a second electrode layer, and an encapsulation layer are also disposed on the first electrode layer, which will not be described in detail here.
  • a plurality of second common scan signal lines Gcom2 located in the same row have an interval I between them, that is, a plurality of second common scan signal lines Gcom2 located in the same row and in different display partitions have an interval I between them, thereby providing common scan signals for different display partitions.
  • the plurality of first common scanning signal lines Gcom1 may also be Set at other positions.
  • the orthographic projection of at least one of the plurality of first common scanning signal lines Gcom1 on the substrate substrate 101 is located between the orthographic projections of an adjacent data line dataB that provides a data signal to a blue sub-pixel B and a data line dataR that provides a data signal to a red sub-pixel R on the substrate substrate 101.
  • the orthographic projection of the reference voltage line Vref on the substrate substrate 101 is located between the orthographic projections of an adjacent first power line VSS and a data line dataB that provides a data signal to a blue sub-pixel B on the substrate substrate 101.
  • the first common scanning signal line Gcom1 and the second common scanning signal line Gcom2 are arranged in different layers.
  • the plurality of first common scanning signal lines Gcom1 and the plurality of second common scanning signal lines Gcom2 may also be arranged in the same layer, for example, in the same layer as the first gate electrode T1g, that is, in the first gate metal layer.
  • the first common scanning signal line Gcom1 and the second common scanning signal line Gcom2 do not need to be electrically connected through vias.
  • the substrate substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may include, but is not limited to, one or more of glass and quartz
  • the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked, and the materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate.
  • PI polyimide
  • PET polyethylene terephthalate
  • SiNx silicon nitride
  • SiOx silicon oxide
  • the material of the semiconductor layer can be a semiconductor material such as metal oxide, such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO) or amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene.
  • metal oxide such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO) or amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene.
  • the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer may be made of metal materials, such as any one or more of titanium (Ti), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd). Or molybdenum-niobium alloy (MoNb), can be a single layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo multi-layer structure, etc.
  • the materials of the first gate metal layer, the second gate metal layer, the first source-drain metal layer and the second source-drain metal layer can be the same or different.
  • the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer IDL and the first passivation layer PVX1 may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single-layer structure or a multi-layer structure.
  • the materials of the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer IDL may be the same or different.
  • first planar layer PLN1 and the second planar layer PLN2 may be made of organic materials, such as polyimide, resin, etc.
  • the materials of the first planar layer PLN1 and the second planar layer PLN2 may be the same or different.
  • the first electrode E1 of the light emitting device EL may be made of transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), gallium zinc oxide (GZO), or a laminate of transparent metal oxide and metal (such as silver), and the material of the second electrode E3 may be made of metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • the light emitting material layer E2 may be made of organic light emitting materials or quantum dot light emitting materials that can emit red, green, or blue light.
  • the encapsulation layer EN may be a stack of organic encapsulation materials and inorganic encapsulation materials
  • the organic encapsulation material may be polyimide, resin, etc.
  • the inorganic encapsulation material may be silicon oxide (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiON), etc.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • SiON silicon oxynitride
  • At least one embodiment of the present disclosure further provides a display device, which includes the display substrate provided in the embodiment of the present disclosure.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

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  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

一种显示基板和显示装置，该显示基板具有排布为多行多列的多个显示分区(DA)，至少一个显示分区(DA)包括多个子像素，显示基板包括衬底基板(101)和公共扫描信号线，公共扫描信号线设置在衬底基板(101)上，包括沿第一方向延伸的多条第一公共扫描信号线(Gcom1)以及沿第二方向延伸的多条第二公共扫描信号线(Gcom2)，第一方向不同于第二方向；其中，每条第二公共扫描信号线(Gcom2)分别电连接至一条第一公共扫描信号线(Gcom1)，且配置为向一个显示分区(DA)提供公共扫描信号。该显示基板可以通过公共扫描信号线实现分区域控制，从而实现高刷新率、高分辨率显示。

Description

显示基板和显示装置
本申请要求于2022年10月28日递交的PCT专利申请PCT/CN2022/128241、于2022年10月28日递交的PCT专利申请PCT/CN2022/128244和于2022年10月28日递交的PCT专利申请PCT/CN2022/128272的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板和显示装置。
背景技术
随着显示技术的不断发展，显示产品的应用范围越来越广泛，高分辨率高刷新频率的显示产品越来越受到人们青睐。而中大尺寸的显示产品由于受到负载大的限制，无法很好的实现高刷新频率的产品功能。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板具有排布为多行多列的多个显示分区，所述多个显示分区中的至少一个包括多个子像素，所述显示基板包括衬底基板和公共扫描信号线，公共扫描信号线设置在所述衬底基板上，包括沿第一方向延伸的多条第一公共扫描信号线以及沿第二方向延伸的多条第二公共扫描信号线，其中，所述第一方向不同于所述第二方向；其中，所述多条第二公共扫描信号线的每个分别电连接至所述多条第一公共扫描信号线中的一条第一公共扫描信号线，且配置为向所述多个显示分区中的一个显示分区提供公共扫描信号。
例如，本公开至少一实施例提供的显示基板中，所述多条第一公共扫描信号线和所述多条第二公共扫描信号线异层设置，且在垂直于所述衬底基板的方向上具有第一交叠部分，所述显示基板还包括设置在所述公共扫描信号线远离所述衬底基板一侧的辅助电极，在垂直于所述衬底基板的方向上，所述辅助电极与所述第一交叠部分交叠。
例如，本公开至少一实施例提供的显示基板中，所述子像素包括像素驱动电路以及与所述像素驱动电路电连接的发光器件，所述发光器件包括与所述像素驱动电路电连接的第一电极、设置在所述第一电极的远离所述衬底基板一侧的发光材料层以及设置在所述发光材料层的远离所述衬底基板一侧的第二电极，其中，所述辅助电极与所述第一电极同层设置，且与所述第二电极电连接。
例如，本公开至少一实施例提供的显示基板中，所述像素驱动电路包括第一晶体管，所述第一晶体管包括第一栅极以及第一源极和第一漏极，所述多条第一公共扫描信号线与所述第一栅极同层设置，所述第一栅极电连接所述多条第二公共扫描信号线中的一条。
例如，本公开至少一实施例提供的显示基板还包括：多条数据线以及多条第一电源线，多条数据线分别沿所述第一方向延伸，配置为向所述多个子像素提供数据信号，多条第一电源线分别沿所述第一方向延伸，配置为向所述多个子像素提供第一电源信号，其中，所述多条第一公共扫描信号线中的至少一条的至少部分在所述衬底基板上的正投影位于相邻的一条数据线和一条第一电源线在所述衬底基板上的正投影之间；所述多条第一电源线中的至少一个电连接所述辅助电极。
例如，本公开至少一实施例提供的显示基板还包括：多条第二电源线，分别沿所述第一方向延伸，配置为向所述多个子像素提供第二电源信号，其中，所述第二电源信号的电位高于所述第一电源信号的电位；所述多条第一电源线和所述多条第二电源线同层设置，且沿所述第二方向交替设置。
例如，本公开至少一实施例提供的显示基板中，所述多条数据线和所述多条第一电源线同层设置，且设置在所述第一漏极的远离所述衬底基板的一侧。
例如，本公开至少一实施例提供的显示基板中，所述多个子像素包括阵列排布的多个重复单元，所述多个重复单元中的每个包括多个发光颜色不同的子像素；所述多条第一公共扫描信号线中的至少一条的至少部分在所述衬底基板上的正投影位于相邻的重复单元的像素驱动电路在所述衬底基板上的正投影之间。
例如，本公开至少一实施例提供的显示基板中，所述多个子像素包 括红色子像素、绿色子像素和蓝色子像素，所述多条第一公共扫描信号线中的至少一条的至少部分在所述衬底基板上的正投影位于相邻的一条向所述蓝色子像素提供数据信号的数据线与一条第一电源线在所述衬底基板上的正投影之间。
例如，本公开至少一实施例提供的显示基板中，所述像素驱动电路还包括第二晶体管，所述第二晶体管包括第二栅极以及设置在所述第二栅极的远离所述衬底基板一侧的第二源极和第二漏极，所述显示基板还包括多条第一扫描信号线，所述第二栅极电连接所述多条第一扫描信号线中的一条，所述第二源极电连接所述多条数据线中的一条，所述第二漏极电连接所述第一源极。
例如，本公开至少一实施例提供的显示基板中，所述像素驱动电路还包括第一电容，所述第一电容包括第一电容电极以及第二电容电极，所述第一电容电极电连接所述第一漏极，所述第二电容电极电连接所述第一电极；所述第一电容电极包括与所述第一栅极同层设置的第一部分以及与所述第一漏极同层设置的第二部分。
例如，本公开至少一实施例提供的显示基板中，所述多条第二公共扫描信号线中的至少一条在所述衬底基板上的正投影位于相邻的一条第一扫描信号线和所述第一电容电极在所述衬底基板上的正投影之间。
例如，本公开至少一实施例提供的显示基板中，所述像素驱动电路还包括第一共用晶体管，所述第一共用晶体管至少被相邻的两个子像素共用，所述第一共用晶体管包括第一共用栅极以及设置在所述第一共用栅极的远离所述衬底基板一侧的第一共用源极和第一共用漏极，所述第一共用栅极电连接所述多条第一公共扫描信号线中的一条。
例如，本公开至少一实施例提供的显示基板中，所述第一共用晶体管还包括第一共用有源层，所述多个子像素包括阵列排布的多个重复单元，所述多个重复单元中的每个包括多个发光颜色不同的子像素；所述第一共用有源层在所述衬底基板上的正投影位于相邻的重复单元的像素驱动电路在所述衬底基板上的正投影之间。
例如，本公开至少一实施例提供的显示基板中，在垂直于所述衬底基板的方向上，所述多条第一公共扫描信号线中的一条与所述第一共用有源层具有第二交叠部分，所述第二交叠部分作为所述第一共用栅极。
例如，本公开至少一实施例提供的显示基板中，所述多个子像素包括红色子像素、绿色子像素和蓝色子像素，以一个红色子像素、一个绿色子像素和一个蓝色子像素作为一个重复单元，所述第一共用晶体管至少被相邻的两个重复单元共用。
例如，本公开至少一实施例提供的显示基板中，位于同一行的多条第二公共扫描信号线之间具有间隔。
例如，本公开至少一实施例提供的显示基板中，所述多条第一公共扫描信号线和所述多条第二公共扫描信号线同层设置，且与所述第一栅极同层设置。
例如，本公开至少一实施例提供的显示基板中，每个显示分区对应设置至少一条复位电压线、一条第一公共扫描信号线以及一条参考电压线，所述复位电压线、第一公共扫描信号线及参考电压线分别位于不同的子像素之间。
例如，本公开至少一实施例提供的显示基板中，所述多个子像素包括阵列排布的多个重复单元，至少一个所述重复单元包括红色子像素、绿色子像素和蓝色子像素，其中，所述红色子像素的发光器件的第一电极在所述衬底基板上的正投影与一条数据线以及一条参考电压线在所述衬底基板上的正投影至少部分交叠；所述蓝色子像素的发光器件的第一电极在所述衬底基板上的正投影与一条数据线在所述衬底基板上的正投影至少部分交叠；所述绿色子像素的发光器件的第一电极在所述衬底基板上的正投影与一条数据线以及一条第一电源线在所述衬底基板上的正投影至少部分交叠。
例如，本公开至少一实施例提供的显示基板中，所述多个子像素包括阵列排布的多个重复单元，所述多个重复单元的每个包括红色子像素、绿色子像素和蓝色子像素，所述多条第一公共扫描信号线中的至少一条在所述衬底基板上的正投影位于相邻的一条向所述蓝色子像素提供数据信号的数据线与一条向所述绿色子像素提供数据信号的数据线在所述衬底基板上的正投影之间。
例如，本公开至少一实施例提供的显示基板中，所述子像素包括像素驱动电路以及与所述像素驱动电路电连接的发光器件，所述像素驱动电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶 体管、第六晶体管、第一共用晶体管和第一电容，所述第一晶体管包括第一栅极以及第一源极和第一漏极，所述第一栅极电连接所述第二公共扫描信号线，所述第二晶体管包括第二栅极以及第二源极和第二漏极，所述第二栅极电连接第一扫描信号线，所述第二源极电连接数据线，所述第二漏极电连接所述第一源极，所述第三晶体管包括第三栅极以及第三源极和第三漏极，所述第三栅极电连接第三扫描信号线，所述第四晶体管包括第四栅极以及第四源极和第四漏极，所述第四栅极电连接第二扫描信号线，所述第四源极电连接所述第一源极以及所述第二漏极，所述第四漏极电连接参考电压线，所述第五晶体管包括第五栅极以及第五源极和第五漏极，所述第五栅极电连接发光控制信号线，所述第五漏极电连接第二电源线，所述第一共用晶体管包括第一共用栅极以及第一共用源极和第一共用漏极，所述第一共用栅极电连接第一公共扫描信号线，所述第一共用源极电连接复位电压线，所述第一共用漏极电连接所述第三漏极，所述第六晶体管包括第六栅极以及第六源极和第六漏极，所述第六栅极所述第一漏极，所述第六源极电连接发光器件的第一电极，所述第六漏极电连接所述第五源极以及所述第三源极，所述第一电容包括第一电容电极以及第二电容电极，所述第一电容电极电连接所述第一漏极，所述第二电容电极电连接所述发光器件的第一电极。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一实施例提供的显示基板的公共扫描信号线的简化示意图；
图2为本公开至少一实施例提供的显示基板的一个子像素的像素驱动电路图；
图3为本公开至少一实施例提供的显示基板的一个子像素的部分截面示意图；
图4-图11B为本公开至少一实施例提供的显示基板的各个功能层的平面示意图以及各个功能层依次叠加的平面示意图；
图12为本公开至少一实施例提供的显示基板的另一平面示意图；
图13为本公开至少一实施例提供的另一显示基板的平面示意图；以及
图14为本公开至少一实施例提供的再一显示基板的平面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
由于中大尺寸的显示产品受到负载大的限制，无法很好的实现高刷新频率的产品功能，对此，本公开至少一实施例提供一种显示基板以及显示装置，该显示基板具有排布为多行多列的多个显示分区，多个显示分区中的至少一个包括多个子像素，显示基板包括衬底基板和公共扫描信号线，公共扫描信号线设置在衬底基板上，包括沿第一方向延伸的多条第一公共扫描信号线以及沿第二方向延伸的多条第二公共扫描信号线，其中，第一方向不同于第二方向；多条第二公共扫描信号线的每个分别电连接至多条第一公共扫描信号线中的一条第一公共扫描信号线，且配置为向多个显示分区中的一个显示分区提供公共扫描信号。
本公开实施例提供的上述显示基板可以利用公共扫描信号线实现对显示基板的分区域控制，从而使每个显示分区在一帧时间单独刷新而不影响其他分区，由此可以整体提高显示基板的刷新频率，实现高分辨率(PPI)显示。
下面，通过几个具体的实施例来详细介绍本公开实施例提供的显示基板以及显示装置。
本公开至少一实施例提供一种显示基板，图1示出了该显示基板的公共扫描信号线的简化示意图，图2示出了该显示基板的一个子像素的像素驱动电路图，图3示出了该显示基板的一个子像素的部分截面示意图。
如图1-图3所示，该显示基板具有排布为多行多列的多个显示分区DA，多个显示分区DA中的至少一个(例如每个)包括多个子像素。
显示基板包括衬底基板101和公共扫描信号线，公共扫描信号线设置在衬底基板101上，包括沿第一方向(图中的竖直方向)延伸的多条第一公共扫描信号线Gcom1以及沿第二方向(图中的水平方向)延伸的多条第二公共扫描信号线Gcom2。上述第一方向不同于第二方向，例如，第一方向垂直于第二方向。例如，在图1的示例中，第一方向为多个显示分区DA的列方向，第二方向为多个显示分区DA的行方向；在其他示例中，也可以是第一方向为多个显示分区DA的行方向，第二方向为多个显示分区DA的列方向。
例如，每个第二公共扫描信号线Gcom2分别电连接至多条第一公共扫描信号线Gcom1中的一条第一公共扫描信号线Gcom1，且配置为向多个显示分区DA中的一个显示分区DA提供公共扫描信号。
例如，在一些实施例中，如图1所示，多条第一公共扫描信号线Gcom1分别配置为向多列显示分区DA提供公共扫描信号，也即，每条第一公共扫描信号线Gcom1配置为向位于同一列的显示分区DA提供公共扫描信号。例如，在一些实施例中，每个显示分区DA具有至少一条第二公共扫描信号线Gcom2，例如具有多条第二公共扫描信号线Gcom2，每条第二公共扫描信号线Gcom2配置为向该显示分区DA中位于同一行的子像素提供公共扫描信号。
例如，在一些实施例中，多条第一公共扫描信号线Gcom1和多条 第二公共扫描信号线Gcom2异层设置，也即在显示基板的层级结构中并不设置在同一层，多条第一公共扫描信号线Gcom1和多条第二公共扫描信号线Gcom2在垂直于衬底基板101的方向(也即图3中的竖直方向上)上具有第一交叠部分OV1(参考后面的图8B)，例如，显示基板还包括设置在公共扫描信号线远离衬底基板101一侧的辅助电极A1(参考后面的图11A)，在垂直于衬底基板101的方向上，辅助电极A1与第一交叠部分OV1交叠。
例如，辅助电极A1可以通过过孔与发光器件EM的第二电极E1电连接，并通过过孔与第一电源线(稍后详细介绍)电连接，从而将第一电源线与第二电极E1并联。由于在大尺寸显示基板中，第二电极E1的方阻往往较大，导致显示基板不同位置的电压不同，例如发生局部电位抬升等不良现象，从而影响显示。通过辅助电极A1将第二电极E1连接至第一电源线的设计，可以将第二电极E1的大部分电流通过辅助电极A1电连接的第一电源线提供，从而可以极大降低第二电极E1方阻大的影响，使得显示基板上的多个子像素的发光器件的第二电极E1可以获取基本相同的电源信号。
例如，在一些实施例中，如图3所示，每个子像素包括像素驱动电路D以及与像素驱动电路D电连接的发光器件EL，发光器件EL包括与像素驱动电路D电连接的第一电极E1、设置在第一电极E1的远离衬底基板101一侧的发光材料层E2以及设置在发光材料层E2的远离衬底基板101一侧的第二电极E3，例如，辅助电极A1与第一电极E1同层设置。
例如，在一些实施例中，如图2所示，像素驱动电路包括第一晶体管T1，第一晶体管T1包括第一栅极T1g以及第一源极T1s和第一漏极T1d。例如，多条第一公共扫描信号线Gcom1与第一栅极T1g同层设置，多条第二公共扫描信号线Gcom2与第一漏极T1d同层设置。
需要注意的是，在本公开的实施例中，“同层设置”为两个(或更多个)功能层或结构层在显示基板的层级结构中同层且同材料形成，即在制备工艺中，该两个(或更多个)功能层或结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构。
例如，如图2所示，第一晶体管T1的第一栅极T1g电连接一条第 二公共扫描信号线Gcom2，以从第二公共扫描信号线Gcom2接收公共扫描信号。
例如，第一晶体管T1可以作为分区控制电路，配置为响应于第二公共扫描信号线Gcom2提供的公共扫描信号，将数据线data提供的数据电压和参考线电压线Vref提供的参考电压的至少之一施加至第六晶体管T6的第六栅极T6g。
例如，如图2所示，像素驱动电路还包括第二晶体管T2，第二晶体管T2包括第二栅极T2g以及设置在第二栅极T2g的远离衬底基板101一侧的第二源极T2s和第二漏极T2d，显示基板还包括多条第一扫描信号线G1，第二栅极T2g电连接多条第一扫描信号线G1中的一条，第二源极T2s电连接多条数据线data中的一条，第二漏极T2d电连接第一晶体管T1的第一源极T1s。
例如，第二晶体管T2可以作为数据写入电路，配置为响应于第一扫描信号线G1提供的第一控制信号，将数据线data提供的数据电压施加至第六晶体管T6的第六栅极T6g。
例如，如图2所示，像素驱动电路还包括第一电容C1，第一电容C1包括第一电容电极C11以及第二电容电极C12，第一电容电极C11电连接第一晶体管T1的第一漏极T1d，第二电容电极C12电连接发光器件EL的第一电极E1。例如，第一电容C1可以作为存储电容。
例如，在数据写入阶段，第二晶体管T2可以响应于第一扫描信号而开启，从而可以将数据信号写入，第一晶体管T1响应于公共扫描信号而开启，数据信号经过开启的第一晶体管T1写入第六晶体管T6，并将数据信号存储在第一电容C1中，以在例如发光阶段时可以根据该数据信号生成驱动发光器件EL发光的驱动电流。
例如，如图2所示，像素驱动电路还包括第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6以及第一共用晶体管T7，第一共用晶体管T7至少被相邻的两个子像素SP共用，也即至少被位于同一显示分区DA的至少相邻的两个子像素SP共用。
例如，第四晶体管T4包括第四栅极T4g以及设置在第四栅极T4g远离衬底基板一侧的第四源极T4s和第四漏极T4d，显示基板还包括多条第二扫描信号线G2、多条参考电压线Vref，第四栅极T4g电连接多 条第二扫描信号线G2中的一条，第四源极T4s电连接第一晶体管T1的第一源极T1s以及第二晶体管T2的第二漏极T2d，第四漏极T4d电连接多条参考电压线Vref中的一条。
例如，第四晶体管T4可以作为复位电路，配置为响应于第二扫描信号线G2提供的第二扫描信号而施加参考电压线Vref提供的参考电压信号，以实现电压复位功能。
例如，第三晶体管T3包括第三栅极T3g以及设置在第三栅极T3g远离衬底基板101一侧的第三源极T3s和第三漏极T3d，显示基板还包括多条第三扫描信号线G3，第三栅极T3g电连接多条第三扫描信号线G3中的一条，第三源极T3s电连接第六晶体管T6的第六漏极T6d(稍后介绍)，第三漏极T3d电连接第一共用晶体管T7的第一共用漏极T7d(稍后介绍)。
例如，第五晶体管T5包括第五栅极T5g以及设置在第五栅极T5g远离衬底基板101一侧的第五源极T5s和第五漏极T5d，第五栅极T5g电连接发光控制信号线EM，第五源极T5s电连接第六晶体管T6的第六漏极T6d，第五漏极T5d电连接第二电源线VDD。
例如，第五晶体管T5可以作为发光控制电路，配置为响应于发光控制线EM提供的发光控制信号将第二电源线VDD提供的第二电源电压的施加至第六晶体管T6。例如，在发光阶段，第五晶体管T5可以响应于发光控制信号而开启，从而可以将第二电源电压施加至第六晶体管T6，在第六晶体管T6导通时，第六晶体管T6将此第二电源电压施加至发光器件EL以提供驱动电压，从而驱动发光器件EL发光。
例如，在一些实施例中，第五晶体管T5也可以至少被相邻的两个子像素共用，例如在一些实施例中可以至少被相邻的两个重复单元共用。
例如，第六晶体管T6包括第六栅极T6g以及设置在第六栅极T6g远离衬底基板101一侧的第六源极T6s和第六漏极T6d，第六栅极T6g电连接第一晶体管T1的第一漏极T1d以及第一电容C1的第一电容电极C11，第六源极T6s电连接发光器件EL的第一电极E1以及第一电容C1的第二电容电极C12，第六漏极T6d电连接第五晶体管T5的第五源极T5s以及第三晶体管T3的第三源极T3s。
例如，第六晶体管T6可以作为发光器件EL的驱动电路，在发光阶段，第六晶体管T6可以向发光器件EL提供驱动电流以驱动发光器件EL进行发光，且可以根据需要的“灰度”发光。
例如，第一共用晶体管T7包括第一共用栅极T7g以及设置在第一共用栅极T7g的远离衬底基板101一侧的第一共用源极T7s和第一共用漏极T7d，第一共用栅极T7g电连接多条第一公共扫描信号线Gcom1中的一条，显示基板还包括多条复位电压线Vini，第一共用源极T7s电连接多条复位电压线Vini中的一条，第一共用漏极T7d电连接多个子像素SP的像素驱动电路中第三晶体管T3的第三漏极T3d。
例如，第三晶体管T3和第一共用晶体管T7可作为另一复位电路，在第一共用晶体管T7响应于公共扫描信号开启，且第三晶体管T3响应于第三扫描信号开启时，复位信号可写入第六晶体管T6的一端以对其进行复位。
例如，发光器件EL的第一电极E1和第二电极E2之间可以形成本征电容Coled。
例如，在本公开的实施例中，每个晶体管的源极和漏极在结构上是对称的，二者的功能和连接方式可以互换。
例如，在上述像素驱动电路中，第一晶体管T1可以作为显示分区DA的分区控制电路，配置为响应于第二公共扫描信号线Gcom2提供的公共扫描信号，将数据线data提供的数据电压和参考线电压线Vref提供的参考电压的至少之一施加至第六晶体管T6的第六栅极T6g，第六晶体管T6可以作为发光器件EL的驱动电路，第一共用晶体管T7被配置为响应于第一公共扫描信号线Gcom1提供的公共扫描信号和第三扫描信号线G3提供的第三扫描信号将复位电压线Vini提供的复位电压施加至第六晶体管T6，以使得该像素驱动电路可以实现分区显示。
在本公开实施例提供的上述像素驱动电路中，第一晶体管T1(分区控制电路)和第一共用晶体管T7(复位电路)均响应于公共扫描信号开启，以实现对第六晶体管T6(驱动电路)的第六栅极、第六源极和第六漏极的复位以及实现数据信号写入驱动电路，由此，该像素驱动电路可以实现分区显示，例如，单独更新某一显示分区画面，而其他显示区域的显示画面不更新，由此有利于实现显示分区的超高刷新频率， 降低显示基板的整体功耗。
例如，如图3所示，在显示基板的层级结构中，各晶体管的有源层(图3中示出了与发光器件EL连接的第六晶体管T6的第六有源层T6a)同层设置在衬底基板101上，该功能层也可以称为显示基板的半导体层，半导体层上设置有第一栅绝缘层GI1。
例如，在一些实施例中，如图3所示，第一电容C1的第一电容电极C11，包括分别与第二电容电极C12交叠的两个部分，各晶体管的栅极(图中示出了第六晶体管T6的第六栅极T6g)以及第一电容C1的第一电容电极C11的第一部分同层设置在第一栅绝缘层GI1上，该功能层也可以称为显示基板的第一栅金属层，第一栅金属层上设置有第二栅绝缘层GI2。例如，第二电容电极C12设置在第一栅绝缘层GI1上，该功能层也可称为显示基板的第二栅金属层，第二栅金属层上设置有层间绝缘层IDL。
例如，如图3所示，各晶体管的源极和漏极(图中示出了第六晶体管T6的第六源极T6s和第六漏极T6d)以及第一电容电极C11的另一部分C13，也即第二部分，同层设置在层间绝缘层IDL上，该功能层也可以称为显示基板的第一源漏金属层，第一源漏金属层上设置有第一钝化层PVX1和第一平坦化层PLN1。
例如，如图3所示，显示基板还包括设置在第一平坦化层PLN1上的连接电极CL，连接电极CL用于将发光器件EL的第一电极E1与像素驱动电路D电连接，连接电极CL所在的功能层也可以称为第二源漏金属层。第二源漏金属层上设置有第二平坦化层PLN2，发光器件EL的第一电极E1设置在第二平坦化层PLN2上。
例如，如图3所示，显示基板还包括设置在发光器件EL的第一电极E1上的像素界定层PDL，像素界定层PDL包括多个子像素开口，用于界定多个子像素的发光区域，发光材料层E2至少设置在子像素开口中。例如，多个发光器件EL的第二电极E3为连续设置的一体化电极，第二电极E3上方设置有封装层EN，以实现对显示基板的封装。例如，封装层EN可以为包括多个无机封装层和有机封装层的复合封装层，以提高对显示基板的封装效果。
例如，图4-图11B示出了本公开至少一实施例提供的显示基板的 各个功能层的平面示意图以及各个功能层依次叠加的平面示意图。
例如，图4示出了显示基板的半导体层的平面示意图，如图4所示，半导体层包括各个晶体管的有源层T1a-T7a。
例如，第一晶体管T1的第一有源层T1a、第二晶体管T2的第二有源层T2a以及第四晶体管T4的第四有源层T4a连接为一体，第三晶体管T3的第三有源层T3a、第五晶体管T5的第五有源层T5a以及第六晶体管T6第六有源层T6a连接为一体，第一共用晶体管T7的第一共用有源层T7a单独设置，且由于第一共用晶体管T7被至少两个子像素共用，因此第一共用有源层T7a的排布密度小于上述有源层T1a-T6a的排布密度。
例如，在一些实施例中，显示基板包括的多个子像素包括红色子像素R、绿色子像素G以及蓝色子像素B，第一共用有源层T7a在衬底基板101上的正投影位于相邻的绿色子像素G和蓝色子像素B的像素驱动电路在衬底基板101上的正投影之间。例如，在图4中，第一共用有源层T7a在衬底基板101上的正投影位于相邻的绿色子像素G和蓝色子像素B的各晶体管的有源层T1a-T6a在衬底基板101上的正投影之间。
例如，在一些实施例中，多个子像素包括阵列排布的多个重复单元，每个重复单元包括多个发光颜色不同的子像素，例如红色子像素R、绿色子像素G以及蓝色子像素B，第一共用有源层T7a在衬底基板101上的正投影位于相邻的两个重复单元的像素驱动电路在衬底基板101上的正投影之间，第一共用晶体管T7至少被相邻的两个重复单元共用，也即被六个子像素共用。例如，在其他实施例中，第一共用晶体管T7也可以被配置为被三个或者更多个重复单元共用。
例如，如图4所示，在一些实施例中，第一共用有源层T7a的平面形状可以呈具有直角转弯的弯折形。
例如，图5A示出了显示基板的第一栅金属层的平面示意图，图5B示出了显示基板的第一栅金属层与半导体层叠加后的平面示意图。
例如，如图5A所示，第一栅金属层包括各晶体管的栅极T1g-T7g、第一电容电极C11的一部分、复位电压线Vini、第一公共扫描信号线Gcom1以及参考电压线Vref。例如，复位电压线Vini、第一公共扫描 信号线Gcom1以及参考电压线Vref均沿第一方向(也即图中的竖直方向)延伸。
例如，多条第一公共扫描信号线Gcom1中的至少一条的至少部分在衬底基板101上的正投影位于相邻的重复单元的像素驱动电路在衬底基板101上的正投影之间。
例如，在一些实施例中，每个显示分区DA对应设置至少一条复位电压线Vini、一条第一公共扫描信号线Gcom1以及一条参考电压线Vref。例如，复位电压线Vini、第一公共扫描信号线Gcom1及参考电压线Vref分别位于不同的子像素之间。
例如，在该实施例中，复位电压线Vini延伸在相邻的蓝色子像素B和红色子像素R的像素驱动电路之间，也即复位电压线Vini在衬底基板上的正投影位于相邻的蓝色子像素B和红色子像素R的像素驱动电路在衬底基板上的正投影之间；第一公共扫描信号线Gcom1延伸在相邻的蓝色子像素B和绿色子像素G的像素驱动电路之间，也即第一公共扫描信号线Gcom1在衬底基板上的正投影位于相邻的蓝色子像素B和绿色子像素G的像素驱动电路在衬底基板上的正投影之间；参考电压线Vref延伸在相邻的蓝色子像素B和红色子像素R的像素驱动电路之间，也即参考电压线Vref在衬底基板上的正投影位于相邻的蓝色子像素B和红色子像素R的像素驱动电路在衬底基板上的正投影之间。
例如，在垂直于衬底基板101的方向上，第一公共扫描信号线Gcom1与第一共用有源层T7a具有第二交叠部分(也即图5B中标号T7g所指示的部分)，第二交叠部分作为第一共用栅极T7g，从而第一共用栅极T7g也位于相邻的蓝色子像素B和绿色子像素G的像素驱动电路之间。
例如，在第一栅金属层中，第一电容电极C11与第六晶体管的第六栅极T6g连接为一体。
例如，图6A示出了显示基板的第二栅金属层的平面示意图，图6B示出了显示基板的第二栅金属层与第一栅金属层、半导体层叠加后的平面示意图。
例如，如图6A所示，第二栅金属层包括第二电容电极C12，如图6B所示，在垂直于衬底基板101的方向上，第二电容电极C12与第一 电容电极C11交叠，从而形成第一电容C1。
例如，图7A示出了显示基板的层间绝缘层的平面示意图，图7B示出了显示基板的层间绝缘层与第二栅金属层、第一栅金属层、半导体层叠加后的平面示意图。
例如，如图7A和图7B所示，层间绝缘层包括多个过孔，例如用于将第一公共扫描信号线Gcom1与第二公共扫描信号线Gcom2电连接的第一过孔V1、用于将沿第一方向延伸的参考电压线Vref与沿第二方向延伸的参考电压线Vref1电连接的第二过孔V2、用于将沿第一方向延伸的复位电压线Vini与沿第二方向延伸的复位电压线Vini1电连接的第三过孔V3以及将各个晶体管进行电路连接的其他过孔，这里不再赘述。
例如，图8A示出了显示基板的第一源漏金属层的平面示意图，图8B示出了显示基板的第一源漏金属层与层间绝缘层、第二栅金属层、第一栅金属层、半导体层叠加后的平面示意图。
例如，如图8A所示，第一源漏金属层包括沿第二方向延伸的参考电压线Vref1、第一扫描信号线G1、第二扫描信号线G2、第三扫描信号线G3、复位电压线Vini1、第二公共扫描信号线Gcom2、发光控制信号线EM、第二电源电压线VDD1以及第一电容电极C11的另一部分C13。
例如，如8A和图8B所示，多条第二公共扫描信号线Gcom2中的至少一条在衬底基板101上的正投影位于相邻的一条第一扫描信号线G1和第一电容电极C11在衬底基板101上的正投影之间。
例如，在相同的子像素的像素驱动电路中，参考电压线Vref1、第二扫描信号线G2、第一扫描信号线G1、第二公共扫描信号线Gcom2、第一电容电极C11、复位电压线Vini1、第三扫描信号线G3、发光控制信号线EM和第二电源电压线VDD1沿第一方向依次排布。
例如，如图8B所示，多条第一公共扫描信号线Gcom1和多条第二公共扫描信号线Gcom2在垂直于衬底基板101的方向上具有第一交叠部分OV1。
例如，图9A示出了显示基板的第一钝化层和第一平坦化层的平面示意图，图9B示出了显示基板的第一钝化层和第一平坦化层与第一源 漏金属层、层间绝缘层、第二栅金属层、第一栅金属层、半导体层叠加后的平面示意图。
例如，如图9A所示，第一钝化层PVX1和第一平坦化层PLN1包括多个过孔，例如将像素驱动电路与连接电极CL电连接的过孔PN1、将沿第二方向延伸的第二电源线VDD1与沿第一方向延伸的第二电源线VDD电连接的过孔PN2以及将数据线data与像素驱动电路电连接的过孔PN3。
例如，图10A示出了显示基板的第二源漏金属层的平面示意图，图10B示出了显示基板的第二源漏金属层与第一钝化层和第一平坦化层、第一源漏金属层、层间绝缘层、第二栅金属层、第一栅金属层、半导体层叠加后的平面示意图。
例如，如图10A所示，第二源漏金属层包括第一电源线VSS、第二电源线VDD、数据线data以及连接电极CL。
例如，多条数据线data配置为向多个子像素提供数据信号，例如包括为红色子像素提供数据信号的数据线dataR、为蓝色子像素提供数据信号的数据线dataB以及为绿色子像素提供数据信号的数据线dataG。
例如，多条第一电源线VSS与多条数据线data分别沿第一方向延伸，多条第一电源线VSS配置为向多个子像素提供第一电源信号，例如低电平电源信号，例如接地信号。例如，多条第一电源线VSS分别与子像素的发光器件EL的第二电极E3电连接。
例如，如图10B所示，多条第一公共扫描信号线Gcom1中的至少一条的至少部分在衬底基板101上的正投影位于相邻的一条数据线data和一条第一电源线VSS在衬底基板101上的正投影之间。
例如，在图10B的实施例中，多条第一公共扫描信号线Gcom1中的至少一条的至少部分在衬底基板101上的正投影位于相邻的一条为蓝色子像素提供数据信号的数据线dataB和一条第一电源线VSS在衬底基板101上的正投影之间。
例如，多条第二电源线VDD沿第一方向延伸，配置为向多个子像素提供第二电源信号，例如高电平电源信号，第二电源信号的电位高于第一电源信号的电位。例如，多条第二电源线VDD分别与子像素的发光器件EL的第一电极E1电连接。
例如，多条第一电源线VSS和多条第二电源线VDD同层设置，也即设置在第二源漏金属层，且沿第二方向(图中的水平方向)交替设置，也即相邻的两条第一电源线VSS之间设置一条第二电源线VDD，相邻的两条第二电源线VDD之间设置一条第一电源线VSS。
例如，多条数据线data和多条第一电源线VSS同层设置，且设置在第一源极T1s和第一漏极T1d的远离衬底基板101的一侧。
例如，图11A示出了显示基板的第一电极层的平面示意图，图11B示出了显示基板的第一电极层与第二源漏金属层、第一钝化层和第一平坦化层、第一源漏金属层、层间绝缘层、第二栅金属层、第一栅金属层、半导体层叠加后的平面示意图。
例如，如图11A和图11B所示，第一电极层包括发光器件EL的第一电极E1以及辅助电极A1，在垂直于衬底基板101的方向上，辅助电极A1与第一交叠部分OV1至少部分交叠。例如，辅助电极A1整体呈具有倒角或者圆角的多边形。
例如，辅助电极A1在衬底基板101上的正投影位于相邻的蓝色子像素和绿色子像素的发光器件EL的第一电极E1在衬底基板101上的正投影之间。
例如，红色子像素R的发光器件的第一电极E1在衬底基板101上的正投影与一条数据线data以及一条参考电压线Vref在衬底基板101上的正投影至少部分交叠；蓝色子像素B的发光器件的第一电极E1在衬底基板101上的正投影与一条数据线data在衬底基板101上的正投影至少部分交叠；绿色子像素G的发光器件的第一电极E1在衬底基板101上的正投影与一条数据线data以及一条第一电源线VSS在衬底基板101上的正投影至少部分交叠。
例如，第一电极层上还设置有发光材料层、第二电极层以及封装层等功能层，这里不再赘述。
例如，在一些实施例中，如图12所示，位于同一行的多条第二公共扫描信号线Gcom2之间具有间隔I，也即，位于同一行且位于不同显示分区的多条第二公共扫描信号线Gcom2之间具有间隔I，从而为不同的显示分区提供公共扫描信号。
例如，在其他实施例中，多条第一公共扫描信号线Gcom1也可以 设置在其他位置。例如，在另一些实施例中，如图13所示，多条第一公共扫描信号线Gcom1中的至少一条在衬底基板101上的正投影位于相邻的一条向蓝色子像素B提供数据信号的数据线dataB与一条向红色子像素R提供数据信号的数据线dataR在衬底基板101上的正投影之间。例如，此时的参考电压线Vref在衬底基板101上的正投影位于相邻的一条第一电源线VSS与一条向蓝色子像素B提供数据信号的数据线dataB在衬底基板101上的正投影位于之间。
例如，在上述实施例中，是以第一公共扫描信号线Gcom1和第二公共扫描信号线Gcom2异层设置为例进行介绍的。例如，在另一些实施例中，如图14所示，多条第一公共扫描信号线Gcom1和多条第二公共扫描信号线Gcom2也可以同层设置，例如与第一栅极T1g同层设置，也即设置在第一栅金属层。由此第一公共扫描信号线Gcom1和第二公共扫描信号线Gcom2无需通过过孔实现电连接。
例如，在本公开的实施例中，衬底基板101可以是柔性基底，或者可以是刚性基底。刚性衬底可以包括但不限于玻璃、石英中的一种或多种，柔性衬底可以包括但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。例如，在一些示例中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力。
例如，半导体层的材料可以采用金属氧化物等半导体材料，例如采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)或者非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料。
例如，第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层可以采用金属材料，如钛(Ti)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd) 或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo多层结构等。第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层的材料可以相同也可以不同。
例如，第一栅绝缘层GI1、第二栅绝缘层GI2、层间绝缘层IDL以及第一钝化层PVX1可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层结构或者多层结构。第一栅绝缘层GI1、第二栅绝缘层GI2和层间绝缘层IDL的材料可以相同也可以不同。
例如，第一平坦层PLN1和第二平坦层PLN2可以采用有机材料，如聚酰亚胺、树脂等。第一平坦层PLN1和第二平坦层PLN2的材料可以相同也可以不同。
例如，发光器件EL的第一电极E1可以采用氧化铟锡(ITO)、氧化铟锌(IZO)、氧化镓锌(GZO)等透明金属氧化物，或者采用透明金属氧化物与金属(例如银)的叠层，第二电极E3的材料可以采用锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。发光材料层E2可以采用能够发出红色、绿色或者蓝色光的有机发光材料或者量子点发光材料等。
例如，封装层EN可以采用有机封装材料与无机封装材料的叠层，有机封装材料可以选用聚酰亚胺、树脂等，无机封装材料可以选用硅氧化物(SiOx)、硅氮化物(SiNx)或者氮氧化硅(SiON)等。本公开的实施例对上述各功能层的具体材料不作限定。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的显示基板。例如，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
还有以下几点需要说明：
(1)本公开实施例的附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该 元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (23)

  1. 一种显示基板，具有排布为多行多列的多个显示分区，所述多个显示分区中的至少一个包括多个子像素，所述显示基板包括：
    衬底基板，
    公共扫描信号线，设置在所述衬底基板上，包括沿第一方向延伸的多条第一公共扫描信号线以及沿第二方向延伸的多条第二公共扫描信号线，其中，所述第一方向不同于所述第二方向；
    其中，所述多条第二公共扫描信号线的每个分别电连接至所述多条第一公共扫描信号线中的一条第一公共扫描信号线，且配置为向所述多个显示分区中的一个显示分区提供公共扫描信号。
  2. 根据权利要求1所述的显示基板，其中，所述多条第一公共扫描信号线和所述多条第二公共扫描信号线异层设置，且在垂直于所述衬底基板的方向上具有第一交叠部分，
    所述显示基板还包括设置在所述多条第一公共扫描信号线和所述多条第二公共扫描信号线远离所述衬底基板一侧的辅助电极，
    在垂直于所述衬底基板的方向上，所述辅助电极与所述第一交叠部分交叠。
  3. 根据权利要求2所述的显示基板，其中，所述子像素包括像素驱动电路以及与所述像素驱动电路电连接的发光器件，
    所述发光器件包括与所述像素驱动电路电连接的第一电极、设置在所述第一电极的远离所述衬底基板一侧的发光材料层以及设置在所述发光材料层的远离所述衬底基板一侧的第二电极，
    其中，所述辅助电极与所述第一电极同层设置，且与所述第二电极电连接。
  4. 根据权利要求3所述的显示基板，其中，所述像素驱动电路包括第一晶体管，所述第一晶体管包括第一栅极以及第一源极和第一漏极，
    所述多条第一公共扫描信号线与所述第一栅极同层设置，所述第一栅极电连接所述多条第二公共扫描信号线中的一条。
  5. 根据权利要求4所述的显示基板，还包括：
    多条数据线，分别沿所述第一方向延伸，配置为向所述多个子像素 提供数据信号，
    多条第一电源线，分别沿所述第一方向延伸，配置为向所述多个子像素提供第一电源信号，
    其中，所述多条第一公共扫描信号线中的至少一条的至少部分在所述衬底基板上的正投影位于相邻的一条数据线和一条第一电源线在所述衬底基板上的正投影之间；
    所述多条第一电源线中的至少一个电连接所述辅助电极。
  6. 根据权利要求5所述的显示基板，还包括：
    多条第二电源线，分别沿所述第一方向延伸，配置为向所述多个子像素提供第二电源信号，
    其中，所述第二电源信号的电位高于所述第一电源信号的电位；
    所述多条第一电源线和所述多条第二电源线同层设置，且沿所述第二方向交替设置。
  7. 根据权利要求5所述的显示基板，其中，所述多条数据线和所述多条第一电源线同层设置，且设置在所述第一漏极的远离所述衬底基板的一侧。
  8. 根据权利要求1-7任一所述的显示基板，其中，所述多个子像素包括阵列排布的多个重复单元，所述多个重复单元中的每个包括多个发光颜色不同的子像素；
    所述多条第一公共扫描信号线中的至少一条的至少部分在所述衬底基板上的正投影位于相邻的重复单元的像素驱动电路在所述衬底基板上的正投影之间。
  9. 根据权利要求5所述的显示基板，其中，所述多个子像素包括红色子像素、绿色子像素和蓝色子像素，
    所述多条第一公共扫描信号线中的至少一条的至少部分在所述衬底基板上的正投影位于相邻的一条向所述蓝色子像素提供数据信号的数据线与一条第一电源线在所述衬底基板上的正投影之间。
  10. 根据权利要求5-7任一所述的显示基板，其中，所述像素驱动电路还包括第二晶体管，所述第二晶体管包括第二栅极以及设置在所述第二栅极的远离所述衬底基板一侧的第二源极和第二漏极，
    所述显示基板还包括多条第一扫描信号线，
    所述第二栅极电连接所述多条第一扫描信号线中的一条，
    所述第二源极电连接所述多条数据线中的一条，
    所述第二漏极电连接所述第一源极。
  11. 根据权利要求10所述的显示基板，其中，所述像素驱动电路还包括第一电容，所述第一电容包括第一电容电极以及第二电容电极，
    所述第一电容电极电连接所述第一漏极，所述第二电容电极电连接所述第一电极；
    所述第一电容电极包括与所述第一栅极同层设置的第一部分以及与所述第一漏极同层设置的第二部分。
  12. 根据权利要求11所述的显示基板，其中，所述多条第二公共扫描信号线中的至少一条在所述衬底基板上的正投影位于相邻的一条第一扫描信号线和所述第一电容电极在所述衬底基板上的正投影之间。
  13. 根据权利要求11或12所述的显示基板，其中，所述像素驱动电路还包括第一共用晶体管，所述第一共用晶体管至少被相邻的两个子像素共用，
    所述第一共用晶体管包括第一共用栅极以及设置在所述第一共用栅极的远离所述衬底基板一侧的第一共用源极和第一共用漏极，
    所述第一共用栅极电连接所述多条第一公共扫描信号线中的一条。
  14. 根据权利要求13所述的显示基板，其中，所述第一共用晶体管还包括第一共用有源层，
    所述多个子像素包括阵列排布的多个重复单元，所述多个重复单元中的每个包括多个发光颜色不同的子像素；
    所述第一共用有源层在所述衬底基板上的正投影位于相邻的重复单元的像素驱动电路在所述衬底基板上的正投影之间。
  15. 根据权利要求14所述的显示基板，其中，在垂直于所述衬底基板的方向上，所述多条第一公共扫描信号线中的一条与所述第一共用有源层具有第二交叠部分，所述第二交叠部分作为所述第一共用栅极。
  16. 根据权利要求13-15任一所述的显示基板，其中，所述多个子像素包括红色子像素、绿色子像素和蓝色子像素，
    以一个红色子像素、一个绿色子像素和一个蓝色子像素作为一个重复单元，所述第一共用晶体管至少被相邻的两个重复单元共用。
  17. 根据权利要求1-16任一所述的显示基板，其中，位于同一行的多条第二公共扫描信号线之间具有间隔。
  18. 根据权利要求4所述的显示基板，其中，所述多条第一公共扫描信号线和所述多条第二公共扫描信号线同层设置，且与所述第一栅极同层设置。
  19. 根据权利要求4所述的显示基板，其中，每个显示分区对应设置至少一条复位电压线、一条第一公共扫描信号线以及一条参考电压线，所述复位电压线、第一公共扫描信号线及参考电压线分别位于不同的子像素之间。
  20. 根据权利要求19所述的显示基板，其中，所述多个子像素包括阵列排布的多个重复单元，至少一个所述重复单元包括红色子像素、绿色子像素和蓝色子像素，其中，所述红色子像素的发光器件的第一电极在所述衬底基板上的正投影与一条数据线以及一条参考电压线在所述衬底基板上的正投影至少部分交叠；
    所述蓝色子像素的发光器件的第一电极在所述衬底基板上的正投影与一条数据线在所述衬底基板上的正投影至少部分交叠；
    所述绿色子像素的发光器件的第一电极在所述衬底基板上的正投影与一条数据线以及一条第一电源线在所述衬底基板上的正投影至少部分交叠。
  21. 根据权利要求1所述的显示基板，其中，所述多个子像素包括阵列排布的多个重复单元，所述多个重复单元的每个包括红色子像素、绿色子像素和蓝色子像素，
    所述多条第一公共扫描信号线中的至少一条在所述衬底基板上的正投影位于相邻的一条向所述蓝色子像素提供数据信号的数据线与一条向所述绿色子像素提供数据信号的数据线在所述衬底基板上的正投影之间。
  22. 根据权利要求1所述的显示基板，其中，所述子像素包括像素驱动电路以及与所述像素驱动电路电连接的发光器件，所述像素驱动电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第一共用晶体管和第一电容，
    所述第一晶体管包括第一栅极以及第一源极和第一漏极，所述第一 栅极电连接所述第二公共扫描信号线，
    所述第二晶体管包括第二栅极以及第二源极和第二漏极，所述第二栅极电连接第一扫描信号线，所述第二源极电连接数据线，所述第二漏极电连接所述第一源极，
    所述第三晶体管包括第三栅极以及第三源极和第三漏极，所述第三栅极电连接第三扫描信号线，
    所述第四晶体管包括第四栅极以及第四源极和第四漏极，所述第四栅极电连接第二扫描信号线，所述第四源极电连接所述第一源极以及所述第二漏极，所述第四漏极电连接参考电压线，
    所述第五晶体管包括第五栅极以及第五源极和第五漏极，所述第五栅极电连接发光控制信号线，所述第五漏极电连接第二电源线，
    所述第一共用晶体管包括第一共用栅极以及第一共用源极和第一共用漏极，所述第一共用栅极电连接第一公共扫描信号线，所述第一共用源极电连接复位电压线，所述第一共用漏极电连接所述第三漏极，
    所述第六晶体管包括第六栅极以及第六源极和第六漏极，所述第六栅极所述第一漏极，所述第六源极电连接所述发光器件的第一电极，所述第六漏极电连接所述第五源极以及所述第三源极，
    所述第一电容包括第一电容电极以及第二电容电极，所述第一电容电极电连接所述第一漏极，所述第二电容电极电连接所述发光器件的第一电极。
  23. 一种显示装置，包括权利要求1-22任一所述的显示基板。
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