WO2024093702A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

Info

Publication number
WO2024093702A1
WO2024093702A1 PCT/CN2023/125969 CN2023125969W WO2024093702A1 WO 2024093702 A1 WO2024093702 A1 WO 2024093702A1 CN 2023125969 W CN2023125969 W CN 2023125969W WO 2024093702 A1 WO2024093702 A1 WO 2024093702A1
Authority
WO
WIPO (PCT)
Prior art keywords
pattern
transistor
substrate
conductive
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/125969
Other languages
English (en)
French (fr)
Inventor
青海刚
牟良丰
胡明
邱海军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to EP23884634.9A priority Critical patent/EP4492465A4/en
Priority to US18/843,127 priority patent/US12417741B2/en
Publication of WO2024093702A1 publication Critical patent/WO2024093702A1/zh
Anticipated expiration legal-status Critical
Priority to US19/304,884 priority patent/US20250374763A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0224—Details of interlacing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/046—Dealing with screen burn-in prevention or compensation of the effects thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate and a display device.
  • AMOLED Active-Matrix Organic Light Emitting Diode
  • an array substrate comprising: a substrate and a plurality of pixel driving circuits disposed on the substrate, each of the plurality of pixel driving circuits comprising: a transistor, the transistor comprising: a driving transistor, a data writing transistor and a first light emitting control transistor.
  • the array substrate further comprises: a first polar region and a second polar region of the transistor, the first polar region of the driving transistor, the second polar region of the data writing transistor and the second polar region of the first light emitting control transistor being connected to form a conductive connection pattern, and the conductive connection pattern is a continuous pattern.
  • the multiple pixel driving circuits are configured as: an odd-numbered row circuit group and an even-numbered row circuit group, the odd-numbered row circuit group and the even-numbered row circuit group include a plurality of the pixel driving circuits arranged along a first direction, and along a second direction, the odd-numbered row circuit group and the even-numbered row circuit group are alternately arranged, and the first direction and the second direction intersect.
  • the array substrate further includes: a conductive pattern, wherein the conductive pattern includes a pattern in the pixel driving circuit that is located in a different layer from the conductive connection pattern.
  • An overlapping area between the conductive connection pattern of at least one pixel driving circuit in the odd-numbered circuit group and an orthographic projection of the conductive pattern on the substrate is smaller than an overlapping area between the conductive connection pattern of at least one pixel driving circuit in the even-numbered circuit group and an orthographic projection of the conductive pattern on the substrate.
  • the transistor further includes: a compensation transistor
  • the array substrate further includes: a gate pattern of the compensation transistor and a second scanning signal line, the gate pattern of the compensation transistor is electrically connected to the second scanning signal line; the second electrode region of the compensation transistor is connected to the second electrode region of the driving transistor.
  • the plurality of pixel driving circuits are further configured as: a plurality of pixel group units sequentially arranged along the second direction, each of the plurality of pixel group units including: the odd-numbered row circuit group and the even-numbered row circuit group arranged adjacent to the odd-numbered row circuit group. Each of the pixel group units shares one second scanning signal line.
  • the array substrate further includes: a first semiconductor layer disposed on the base, and the conductive connection pattern is located in the first semiconductor layer.
  • the array substrate further comprises: a shielding layer disposed on the substrate, and a first semiconductor layer disposed on a side of the shielding layer away from the substrate.
  • the conductive pattern is located on the shielding layer.
  • the array substrate further includes: a first gate conductive layer disposed on a side of the first semiconductor layer away from the substrate, and a second gate conductive layer disposed on a side of the first gate conductive layer away from the substrate.
  • the pixel driving circuit further includes: a capacitor and a compensation transistor, the capacitor including: a first electrode plate and a second electrode plate, the first electrode plate being located in the first gate conductive layer, and the second electrode plate being located in the second gate conductive layer.
  • the first electrode plate is electrically connected to a first electrode region of the compensation transistor, and the second electrode plate is electrically connected to a power signal line.
  • the conductive pattern includes: a first portion located in the shielding layer and a second portion electrically connected to the second electrode plate.
  • the array substrate further comprises: a first gate conductive layer disposed on a side of the first semiconductor layer away from the substrate, and a second gate conductive layer disposed on a side of the first gate conductive layer away from the substrate.
  • the conductive pattern is located in the second gate conductive layer.
  • the area of the orthographic projection of the conductive pattern in the odd-numbered circuit group on the substrate is equal to the area of the orthographic projection of the conductive pattern in the even-numbered circuit group on the substrate.
  • the conductive connection pattern is connected to a first extended pattern located in the first semiconductor layer, and the orthographic projection of the conductive pattern on the substrate covers the orthographic projection of the first extended pattern on the substrate.
  • the array substrate further comprises: a second gate conductive layer disposed on a side of the first semiconductor layer away from the substrate.
  • the array substrate further comprises a second scanning signal line, the second scanning signal line being located in the second gate conductive layer.
  • the conductive pattern and the second scanning signal line are an integrated structure.
  • the array substrate further includes: a first source-drain metal layer disposed on a side of the first semiconductor layer away from the substrate, the first source-drain metal layer including a third extension pattern, and the third extension pattern is connected to the conductive connection pattern through a via.
  • the array substrate further includes: a second source-drain metal layer disposed on a side of the first source-drain metal layer away from the substrate, the second source-drain metal layer including a power signal line.
  • the conductive pattern and the power signal line are an integral structure, and an overlapping area of an orthographic projection of the third extension pattern in the odd-numbered circuit group on the substrate and an orthographic projection of the conductive pattern on the substrate is smaller than an overlapping area of an orthographic projection of the third extension pattern in the even-numbered circuit group on the substrate and an orthographic projection of the conductive pattern on the substrate. product.
  • an orthographic projection of the data signal line on the substrate does not overlap with an orthographic projection of the third extended pattern on the substrate.
  • an orthographic projection of the third extended pattern on the substrate overlaps with an orthographic projection of the conductive connection pattern on the substrate.
  • the transistor includes: a first reset transistor, a compensation transistor, a second light-emitting control transistor, and a second reset transistor.
  • the array substrate also includes: a first initial signal line, a second initial signal line, a data signal line, and a power signal line.
  • the first region of the first reset transistor is electrically connected to the first initial signal line
  • the second region of the first reset transistor is electrically connected to the first region of the compensation transistor
  • the second region of the compensation transistor is electrically connected to the second region of the driving transistor.
  • the first region of the second light-emitting control transistor is electrically connected to the second region of the driving transistor, the second region of the second light-emitting control transistor is electrically connected to the second region of the second reset transistor, and the first region of the second reset transistor is electrically connected to the second initial signal line.
  • the first region of the data write transistor is electrically connected to the data signal line, and the first region of the first light-emitting control transistor is electrically connected to the power signal line.
  • the array substrate further includes: a gate pattern of the first reset transistor, a reset signal line, a gate pattern of the second reset transistor, a first scan signal line, a gate pattern of the first light emission control transistor, a gate pattern of the second light emission control transistor, and a light emission control signal line.
  • the gate pattern of the first reset transistor is electrically connected to the reset signal line
  • the gate pattern of the second reset transistor is electrically connected to the first scan signal line
  • the gate pattern of the first light emission control transistor and the gate pattern of the second light emission control transistor are electrically connected to the light emission control signal line.
  • the array substrate also includes: a first semiconductor layer arranged on one side of the substrate, the conductive connection pattern is located in the first semiconductor layer; a first gate conductive layer arranged on a side of the first semiconductor layer away from the substrate, the first scanning signal line and the light-emitting control signal line are located in the first gate conductive layer; a second gate conductive layer arranged on a side of the first gate conductive layer away from the substrate, the first initial signal line and the reset signal line are located in the second gate conductive layer; a first source-drain metal layer arranged on a side of the second gate conductive layer away from the substrate, the second initial signal line is located in the first source-drain metal layer; a second source-drain metal layer arranged on a side of the first source-drain metal layer away from the substrate, the data signal line and the power signal line are located in the second source-drain metal layer.
  • the compensation transistor and the first reset transistor include oxide thin film transistors.
  • the array substrate further includes: a conductive layer disposed between the second gate conductive layer and the first source and drain metal A second semiconductor layer and a third gate conductive layer are provided between the layers, and the third gate conductive layer is provided on a side of the second semiconductor layer away from the substrate.
  • an array substrate comprising: a substrate and a plurality of pixel driving circuits arranged on the substrate.
  • Each of the plurality of pixel driving circuits comprises: a transistor, and the transistor comprises: a driving transistor, a data writing transistor and a first light emitting control transistor.
  • the array substrate further comprises: a first polar region and a second polar region of the transistor; the first polar region of the driving transistor, the second polar region of the data writing transistor and the second polar region of the first light emitting control transistor are connected to form a conductive connection pattern, and the conductive connection pattern is a continuous pattern.
  • the plurality of pixel driving circuits are configured as: an odd-numbered circuit group and an even-numbered circuit group, wherein the odd-numbered circuit group and the even-numbered circuit group include a plurality of the pixel driving circuits arranged along a first direction. Along a second direction, the odd-numbered circuit group and the even-numbered circuit group are alternately arranged; the first direction and the second direction intersect.
  • the array substrate further includes: a conductive pattern, wherein the conductive pattern includes a pattern in the pixel driving circuit that is located at a different layer from the conductive connection pattern.
  • the capacitance of the capacitor formed between the conductive connection pattern and the conductive pattern of at least one pixel driving circuit in the odd-numbered circuit group is smaller than the capacitance of the capacitor formed between the conductive connection pattern and the conductive pattern of at least one pixel driving circuit in the even-numbered circuit group.
  • the insulating layer between the conductive connection pattern and the conductive pattern of at least one pixel driving circuit in the odd-numbered circuit group and the insulating layer between the conductive connection pattern and the conductive pattern of at least one pixel driving circuit in the even-numbered circuit group are made of the same material.
  • the insulating layer between the conductive connection pattern and the conductive pattern of at least one pixel driving circuit in the odd-numbered row circuit group, and the insulating layer between the conductive connection pattern and the conductive pattern of at least one pixel driving circuit in the even-numbered row circuit group include at least one insulating layer of the same material.
  • a display device comprising the array substrate as described in any one of the above embodiments.
  • FIG1 is a structural diagram of a display panel provided according to some embodiments.
  • FIG2 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments.
  • FIG3 is a timing diagram of a pixel driving circuit provided based on FIG2 according to some embodiments.
  • FIG4 is a structural diagram of an array substrate provided according to some embodiments of the present disclosure.
  • FIG5 is an equivalent circuit diagram of a pixel driving circuit provided according to some embodiments of the present disclosure.
  • FIG. 6 is a structural diagram of a shielding layer, a first semiconductor layer, and a first gate conductive layer after being superimposed according to some embodiments of the present disclosure
  • FIG7 is another equivalent circuit diagram of a pixel driving circuit provided according to some embodiments of the present disclosure.
  • FIG8 is a timing diagram of a pixel driving circuit provided based on FIG7 according to some embodiments of the present disclosure.
  • FIG. 9 is a structural diagram of a first semiconductor layer, a first gate conductive layer, a second gate conductive layer, a second semiconductor layer and a third gate conductive layer after being superimposed according to some embodiments of the present disclosure
  • FIG10 is a structural diagram of a display panel provided according to some embodiments of the present disclosure.
  • FIG11 is a structural diagram of a shielding layer, a first semiconductor layer, a first gate conductive layer, and a second gate conductive layer after being superimposed according to some embodiments of the present disclosure
  • FIG12 is a partial structural diagram of a shielding layer, a first semiconductor layer, and a second gate conductive layer after being superimposed according to some embodiments of the present disclosure
  • FIG. 13 is a structural diagram of a first semiconductor layer, a first gate conductive layer, and a second gate conductive layer after being superimposed according to some embodiments of the present disclosure
  • FIG14 is another structural diagram of a shielding layer, a first semiconductor layer, a first gate conductive layer, and a second gate conductive layer stacked according to some embodiments of the present disclosure
  • FIG15 is another structural diagram of a shielding layer, a first semiconductor layer, a first gate conductive layer, and a second gate conductive layer stacked according to some embodiments of the present disclosure
  • 16 is a structural diagram of a shielding layer, a first semiconductor layer, a first gate conductive layer, a second gate conductive layer and a first source-drain metal layer after being superimposed according to some embodiments of the present disclosure
  • 17 is a structural diagram of a shielding layer, a first semiconductor layer, a first gate conductive layer, a second gate conductive layer, a first source-drain metal layer, and a second source-drain metal layer after being stacked according to some embodiments of the present disclosure;
  • 18 is another structural diagram of a shielding layer, a first semiconductor layer, a first gate conductive layer, a second gate conductive layer, a first source-drain metal layer, and a second source-drain metal layer superimposed according to some embodiments of the present disclosure;
  • 19 is a structural diagram of a shielding layer, a first semiconductor layer, a first gate conductive layer, a second gate conductive layer, a second semiconductor layer, a third gate conductive layer, a first source-drain metal layer, and a second source-drain metal layer after being stacked according to some embodiments of the present disclosure;
  • FIG20 is another structural diagram of a first semiconductor layer, a first gate conductive layer, and a second gate conductive layer stacked according to some embodiments of the present disclosure
  • FIG21 is another equivalent circuit diagram of a pixel driving circuit provided according to some embodiments of the present disclosure.
  • FIG22 is another structural diagram of a first semiconductor layer, a first gate conductive layer, and a second gate conductive layer stacked according to some embodiments of the present disclosure
  • FIG23 is another structural diagram of a first semiconductor layer, a first gate conductive layer, and a second gate conductive layer stacked according to some embodiments of the present disclosure
  • FIG. 24 is a structural diagram of a display device provided according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • plural means two or more.
  • Coupled When describing some embodiments, the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” should be understood in a broad sense. For example, “connected” can be a fixed connection or a detachable connection. or integrated; may be directly connected or indirectly connected through an intermediate medium.
  • the term “coupled” indicates, for example, that two or more components are in direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the contents of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • parallel includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°;
  • perpendicular includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two equalities is less than or equal to 5% of either one.
  • Exemplary embodiments are described herein with reference to cross-sectional views and/or plan views that are idealized exemplary drawings.
  • the thickness of the layers and the area of the regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.
  • OLED organic light emitting diode
  • AMOLED active-matrix organic light emitting diode
  • the pixel driving circuit 10' includes: a light-emitting control signal line EM, a first scanning signal line Gate1, and a second scanning signal line Gate2.
  • the GOA (Gate on Array, array substrate row drive) circuit of the first scanning signal line Gate1 drives one row by one row
  • the GOA circuit of the first scanning signal line Gate1 includes: an odd-row GOA circuit (Gate1-odd GOA) and an even-row GOA circuit (Gate1-even GOA).
  • the GOA circuit of the light-emitting control signal line EM and the GOA circuit of the second scanning signal line Gate2 adopt a driving architecture of one GOA circuit driving two rows (i.e., one driving two). That is, the GOA circuit of the light-emitting control signal line EM and the GOA circuit of the second scanning signal line Gate2 drive the two rows of pixel driving circuits 10' located in the display area AA.
  • the compensation transistors T2 in two adjacent rows of pixel driving circuits 10' are driven by the same second scanning signal line Gate2.
  • the first reset transistor T1 and the compensation transistor T2 use LTPO (Low Temperature Polycrystalline Oxide) transistors, which are turned on at a high level, and the remaining transistors use LTPS (Low Temperature Poly-silicon) P-type transistors, which are turned on at a low level.
  • LTPO Low Temperature Polycrystalline Oxide
  • LTPS Low Temperature Poly-silicon
  • FIG3 it is a driving timing diagram corresponding to the pixel driving circuit 10' shown in FIG2, which is mainly divided into 6 stages: 1 The light emitting control signal line EM and the reset signal line Reset are both at high level, and the first node N1 is reset by the first initial signal line Vinit1 signal; 2 The second scanning signal line Gate2 jumps to a high level, and the compensation transistors T2 of the odd-numbered row odd and the even-numbered row even pixel driving circuit 10' are turned on at the same time; 3 The scanning signal Gate1-odd of the first scanning signal line Gate1 of the odd-numbered row odd is at a low level, and the data signal write of the odd-numbered row odd is turned on; 4 The scanning signal Gate1-even of the first scanning signal line Gate1 of the even row even is at a low level, and the data signal writing and the threshold compensation of the driving transistor T3 of the even row even are carried out simultaneously; 5 The odd row odd and the even row even simultaneously use the parasitic capacitance of the second no
  • the cut-off duration of the Gate2 signal is b, and duration a is longer than duration b.
  • the pixel driving circuit 10' After the signal of the first scanning signal line Gate1 is turned off, no matter it is the odd row odd or the even row even, the pixel driving circuit 10' will continue to write the data signal to the first node N1 and compensate the threshold value through the parasitic capacitance Ct of the second node N2 through the driving transistor T3. Since the parasitic capacitance Ct of the second node N2 of the pixel driving circuit 10' of the odd row odd and the pixel driving circuit 10' of the even row even is exactly the same, but the duration a and duration b of the odd row odd and the even row even continuing to write the data signal are different, and the duration a is longer than the duration b.
  • the compensation results of the odd row odd and the even row even will be different under the same data signal voltage, which is finally reflected in the display of the display panel 100' as the odd row odd is dark and the even row even is bright, resulting in poor display problems and affecting the quality of the picture.
  • the present disclosure provides an array substrate 1, as shown in FIG4, the array substrate 1 includes a substrate 101 and a plurality of pixel driving circuits 10 disposed on the substrate 101.
  • each of the plurality of pixel driving circuits 10 includes: a transistor, and the transistor includes: a driving transistor T3, a data writing transistor T4 and a first light emitting control transistor T5.
  • the array substrate 1 also includes: a first electrode region and a second electrode region of the transistor, the first electrode region S3 of the driving transistor T3, the second electrode region D4 of the data writing transistor T4 and the second electrode region D5 of the first light-emitting control transistor T5 are connected as a conductive connection pattern M1, and the conductive connection pattern M1 is a continuous pattern.
  • the electrical connection point of the driving transistor T3, the data writing transistor T4 and the first light emission control transistor T5 is the node N2. Therefore, in the layout design of the array substrate 1, the conductive connection pattern M1 area corresponds to the second node N2 in the pixel driving circuit 10.
  • the transistor includes: a first electrode and a second electrode, the first electrode of the transistor in the pixel driving circuit 10 corresponds to the first electrode region of the transistor in the layout design of the array substrate 1, and the second electrode of the transistor in the pixel driving circuit 10 corresponds to the second electrode region of the transistor in the layout design of the array substrate 1.
  • the first electrode region S3 of the driving transistor T3 in FIG6 corresponds to the first electrode s3 of the driving transistor T3 in FIG5.
  • the second electrode region D4 of the data writing transistor T4 in FIG6 corresponds to the second electrode d4 of the data writing transistor T4 in FIG5.
  • the second electrode region D5 of the first light-emitting control transistor T5 in FIG6 corresponds to the second electrode d5 of the first light-emitting control transistor T5 in FIG5.
  • the conductive connection pattern M1 connecting the first electrode region S3 of the driving transistor T3, the second electrode region D4 of the data writing transistor T4 and the second electrode region D5 of the first light emission control transistor T5 in FIG6 corresponds to the first electrode s3 of the driving transistor T3, the second electrode d4 of the data writing transistor T4 and the second electrode d5 of the first light emission control transistor T5 electrically connected to the junction point, i.e., the node N2.
  • the conductive connection pattern M1 region corresponds to the second node N2 in the pixel driving circuit 10 , which means that the parasitic capacitance existing at the second node N2 is caused by the parasitic capacitance generated in the conductive connection pattern M1 region in the layout design of the array substrate 1 .
  • parasitic capacitance the capacitance is not originally designed here, but because there is always mutual capacitance between the wirings, the mutual capacitance can be considered to be parasitic between the wirings, so it is called parasitic capacitance, also known as stray capacitance.
  • the nodes do not represent actual components, but rather represent the junction points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the junction points of related electrical connections in the circuit diagram being equivalent.
  • the plurality of pixel driving circuits 10 are configured as an odd-numbered row circuit group O1 and an even-numbered row circuit group E1, wherein the odd-numbered row circuit group O1 and the even-numbered row circuit group E1 include a plurality of pixel driving circuits 10 arranged along a first direction X.
  • the odd-numbered row circuit group O1 and the even-numbered row circuit group E1 are alternately arranged along a second direction Y.
  • the first direction X and the second direction Y intersect.
  • the first direction X is the row direction in which the plurality of pixel driving circuits 10 are arranged, and the pixel driving circuits 10 in each row are referred to as a circuit group.
  • the second direction Y is the column direction in which the plurality of pixel driving circuits 10 are arranged, and the plurality of circuit groups are arranged along the second direction Y, namely the first row, the second row, the third row...the nth row, wherein the first row, the third row, the fifth row...are all located in odd rows, and can all be referred to as odd row circuit groups O1.
  • first direction X and the second direction Y are perpendicular to each other.
  • the array substrate 1 further includes: a conductive pattern Q, the conductive pattern Q including a pattern in the pixel driving circuit 10 located in a different layer from the conductive connection pattern M1.
  • the overlapping area of the orthographic projection of the conductive pattern M1 and the conductive pattern Q of at least one pixel driving circuit 10 in the odd-numbered row circuit group O1 on the substrate 101 is smaller than the overlapping area of the orthographic projection of the conductive connection pattern M1 and the conductive pattern Q of at least one pixel driving circuit 10 in the even-numbered row circuit group E1 on the substrate 101.
  • orthographic projection in the present disclosure refers to the projection generated by projection lines that are perpendicular to the projection plane and parallel to each other.
  • the pixel driving circuit 10 is disposed on a substrate 101 .
  • the substrate 101 is not shown in FIGS. 5 to 17 , and the position of the substrate 101 can be referred to as shown in FIG. 4 .
  • the conductive pattern Q of the odd-numbered circuit group O1 is represented as a first conductive pattern Q1
  • the conductive pattern Q of the even-numbered circuit group E1 is represented as a second conductive pattern Q2 .
  • parasitic capacitance is generated between the conductive pattern Q and the conductive connection pattern M1, and the magnitude of the parasitic capacitance is related to the magnitude of the overlapping area of the orthographic projections of the conductive pattern Q and the conductive connection pattern M1 on the substrate 101.
  • the parasitic capacitance Ce generated by the even-numbered circuit group E1 at the second node N2 is greater than the parasitic capacitance Ce generated by the odd-numbered circuit group O1 at the second node N2.
  • the duration a and duration b of the odd row odd and the even row even for continuing to write the data signal are different, and the duration a is longer than the duration b.
  • the present disclosure differentially designs the parasitic capacitance Ce of the second node N2 of the odd row circuit group O1 and the parasitic capacitance Ce of the second node N2 of the even row circuit group E1, and designs the parasitic capacitance Ce of the second node N2 of the odd row circuit group O1 to be smaller, and designs the parasitic capacitance Ce of the second node N2 of the even row circuit group E1 to be larger.
  • the compensation time a of the compensation transistor T2 in the odd-numbered circuit group O1 is greater than the compensation time b of the compensation transistor T2 in the even-numbered circuit group E1
  • the parasitic capacitance Ce of the second node N2 in the even-numbered circuit group E1 is greater than the parasitic capacitance Co of the second node N2 in the odd-numbered circuit group O1.
  • the compensation time b in the even-numbered circuit group E1 is shorter than the compensation time a in the odd-numbered circuit group O1 since the potential of the second node N2 in the even-numbered circuit group E1 drops slowly, the amount of charge written in the same time is greater, and finally the compensation effects of the odd-numbered circuit group O1 and the even-numbered circuit group E1 are consistent.
  • the light-emitting devices L driven by the pixel driving circuit 10 of the odd-row circuit group O1 and the pixel driving circuit 10 of the even-row circuit group E1 have no difference in luminous brightness, thereby solving the problem of brightness difference between odd and even rows caused by inconsistent compensation durations of the compensation transistors T2 of the odd-and-even row pixel driving circuits 10, and improving the image quality of the display panel 100.
  • the conductive pattern Q is located in a pattern in the pixel driving circuit 10 that is located in a different layer from the conductive connection pattern M1.
  • the conductive pattern Q is not connected to the conductive connection pattern M1;
  • the electrical connection patterns M1 are located in different film layers.
  • the transistor further includes: a compensation transistor T2.
  • the array substrate 1 further includes: a gate pattern G2 of the compensation transistor T2 and a second scanning signal line Gate2, and a gate pattern G4 of the compensation transistor T2 is electrically connected to the second scanning signal line Gate2.
  • the second electrode region D2 of the compensation transistor T2 is connected to the second electrode region D3 of the driving transistor T3.
  • the multiple pixel driving circuits 10 are also configured as: a plurality of pixel group units 70 arranged in sequence along the second direction Y, each pixel group unit 70 in the multiple pixel group units 70 includes: an odd-numbered row circuit group O1 and an even-numbered row circuit group E1 arranged adjacent to the odd-numbered row circuit group O1, and each pixel group unit 70 shares a second scanning signal line Gate2.
  • the second direction Y is the column direction in which multiple pixel driving circuits 10 are arranged, and multiple circuit groups are arranged along the second direction Y, namely the first row, the second row, the third row...the nth row, wherein the first row and the second row are a pixel group unit 70, the third row and the fourth row are a pixel group unit 70, the fifth row and the sixth row are a pixel group unit 70..., and each pixel group unit 70 shares a second scanning signal line Gate2.
  • Each pixel group unit 70 shares a second scanning signal line Gate2, which is a driving architecture of the second scanning signal line Gate2 driving two.
  • the design disclosed in the present invention that is, the overlapping area of the orthographic projection of the conductive connection pattern M1 in the odd-numbered circuit group O1 on the substrate 101 and the orthographic projection of the conductive pattern Q on the substrate 101 is smaller than the overlapping area of the orthographic projection of the conductive connection pattern M1 in the even-numbered circuit group E1 on the substrate 101 and the orthographic projection of the conductive pattern Q on the substrate 101, can solve the problem of brightness difference between the light-emitting devices L driven by the odd-numbered circuit group O1 and the even-numbered circuit group E1.
  • an example structure of the pixel driving circuit 10 and an example structure of the layout design of the array substrate 1 are first introduced below. It can be understood that the following content is only an example of the structure of the pixel driving circuit 10 and the layout design structure of the array substrate 1, and is not a limitation on the structure of the pixel driving circuit 10 and the layout design structure of the array substrate 1.
  • the pixel driving circuit 10 in the present disclosure may be a circuit including 7T1C, 8T1C or 9T1C, wherein T represents a transistor, and the number before T represents the number of transistors, and C represents a capacitor, and the number before C represents the number of capacitors.
  • 7T1C means 7 transistors and 1 capacitor.
  • a structure of a pixel driving circuit 10 based on that shown in FIG. 5 is introduced, and the pixel driving circuit 10 includes: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, and a second reset transistor T7.
  • the first reset transistor T1 includes: a gate g1, a first electrode s1, and a second electrode d1.
  • the gate g1 of the first reset transistor T1 is electrically connected to the reset signal line terminal
  • the first electrode s1 of the first reset transistor T1 is electrically connected to the first initial signal terminal
  • the second electrode d1 of the first reset transistor T1 is electrically connected to the first node N1.
  • the reset signal terminal is used to receive a reset signal transmitted by the reset signal line Reset.
  • the first initial signal terminal is used to receive an initial signal transmitted by the first initial signal line Vinit1.
  • the first reset transistor T1 is configured to: in response to the reset signal received at the reset signal line Reset, transmit the initial signal received at the first initial signal line Vinit1 to the first node N1, and reset the gate g3 of the driving transistor T3.
  • the first pole of the transistor disclosed in the present invention is one of the source and drain of the transistor, and the second pole is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first pole and the second pole of the transistor in the embodiment of the present invention can be structurally indistinguishable.
  • the transistor is a P-type transistor
  • the first pole of the transistor is the source
  • the second pole is the drain
  • the first pole of the transistor is the drain
  • the second pole is the source.
  • the compensation transistor T2 includes: a gate g2, a first electrode s2, and a second electrode d2, the gate g2 of the compensation transistor T2 is electrically connected to the second scanning signal terminal, the first electrode s2 of the compensation transistor T2 is electrically connected to the first node N1, and the second electrode d2 of the compensation transistor T2 is electrically connected to the third node N3.
  • the second scanning signal terminal is used to receive a scanning signal transmitted by the second scanning signal line Gate2.
  • the compensation transistor T2 is configured to perform threshold compensation on the driving transistor T3 in response to the scanning signal received at the second scanning signal line Gate2.
  • the driving transistor T3 includes: a gate g3, a first electrode s3, and a second electrode d3, the gate g3 of the driving transistor T3 is electrically connected to the first node N1, the first electrode s3 of the driving transistor T3 is electrically connected to the second node N2, and the second electrode d3 of the driving transistor T3 is electrically connected to the third node N3.
  • the driving transistor T3 is configured to generate a driving current signal.
  • the data writing transistor T4 includes: a gate g4, a first electrode s4 and a second electrode d4, the gate g4 of the data writing transistor T4 is electrically connected to the first scanning signal terminal, the first electrode s4 of the data writing transistor T4 is electrically connected to the data signal terminal, and the second electrode d4 of the data writing transistor T4 is electrically connected to the data signal terminal.
  • the electrode d4 is electrically connected to the second node N2.
  • the data signal terminal is used to receive a data signal transmitted by the data signal line Vdata.
  • the data writing transistor T4 is configured to transmit the data signal received at the data signal line Vdata to the driving transistor T3 in response to the scanning signal received at the first scanning signal line Gate1.
  • the first light emission control transistor T5 includes: a gate g5, a first electrode g5, and a second electrode d5.
  • the gate g5 of the first light emission control transistor T5 is electrically connected to the light emission control signal terminal
  • the first electrode g5 of the first light emission control transistor T5 is electrically connected to the power signal terminal
  • the second electrode d5 of the first light emission control transistor T5 is electrically connected to the second node N2.
  • the light emission control signal terminal is used to receive the light emission control signal transmitted by the light emission control signal line EM.
  • the power signal terminal is used to receive the power signal transmitted by the power signal line ELVDD.
  • the first light emission control transistor T5 is configured to: in response to the light emission control signal received at the light emission control signal line EM, transmit the power signal received at the power signal line ELVDD to the driving transistor T3.
  • the second light emitting control transistor T6 includes: a gate g6, a first electrode s6 and a second electrode d6, the gate g6 of the second light emitting control transistor T6 is electrically connected to the light emitting control signal terminal, the first electrode s6 of the second light emitting control transistor T6 is electrically connected to the third node N3, and the second electrode d6 of the second light emitting control transistor T6 is electrically connected to the fourth node N4.
  • the second light emitting control transistor T6 is configured to: in response to the light emitting control signal received at the light emitting control signal line EM, transmit the driving current signal to the light emitting device L, so as to drive the light emitting device L to emit light.
  • the second reset transistor T7 includes: a gate g7, a first electrode s7 and a second electrode d7, the gate g7 of the second reset transistor T7 is electrically connected to the first scan signal terminal, the first electrode s7 of the second reset transistor T7 is electrically connected to the second initial signal terminal, and the second electrode d7 of the second reset transistor T7 is electrically connected to the fourth node N4.
  • the second reset transistor T7 is configured to: in response to the scan signal received at the first scan signal line Gate1, transmit the initial signal received at the second initial signal line Vinit2 to the light emitting device L to reset the light emitting device L.
  • an anode of the light emitting device L is electrically connected to the fourth node N4, and a cathode of the light emitting device L is electrically connected to the reference voltage line ELVSS.
  • the pixel driving circuit 10 further includes: a capacitor Cst, the capacitor Cst includes: a first plate Cst1 and a second plate Cst2, the first plate Cst1 of the capacitor Cst is electrically connected to the first node N1, and the second plate Cst2 of the capacitor Cst is electrically connected to the power signal terminal.
  • the first reset transistor T1 and the compensation transistor T2 can be oxide thin film transistors, i.e., LTPO (Low Temperature Polycrystalline Oxide) transistors, which are turned on at a high level.
  • the driving transistor T3, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the second reset transistor T7 are all low temperature polycrystalline silicon thin film transistors.
  • the P-type transistor of the body tube (Low Temperature Poly-silicon Thin Film Transistor) is turned on at a low level.
  • the driving timing diagram of the above-mentioned pixel driving circuit 10 can be found in FIG3 , which will not be described in detail here.
  • the above examples of the first reset transistor T1 , the compensation transistor T2 , the driving transistor T3 , the data writing transistor T4 , the first light emission control transistor T5 , the second light emission control transistor T6 and the second reset transistor T7 are not limitations on the transistor types.
  • a structure of a pixel driving circuit 10 based on that shown in FIG. 7 is introduced, and the pixel driving circuit 10 includes: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a second reset transistor T7, a third reset transistor T8 and a capacitor Cst.
  • the compensation transistor T2 can be an N-type transistor
  • the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, the second reset transistor T7 and the third reset transistor T8 can be P-type transistors.
  • the first electrode s2 of the compensation transistor T2 is connected to the gate g3 of the driving transistor T3, the second electrode d2 is connected to the second electrode d3 of the driving transistor T3, and the gate g2 is connected to the second scanning signal terminal;
  • the first electrode s1 of the first reset transistor T1 is connected to the first initial signal terminal, the second electrode d1 is connected to the second electrode d2 of the compensation transistor T2, and the gate g1 is connected to the first reset signal terminal;
  • the first electrode s4 of the data writing transistor T4 is connected to the data signal terminal, the second electrode d4 is connected to the first electrode s3 of the driving transistor T3, and the gate g4 is connected to the first scanning signal terminal;
  • the first electrode s5 of the first light-emitting control transistor T5 is connected to the power supply signal terminal, and the second electrode d5 is connected to the first
  • the first electrode s3 of the second light-emitting control transistor T6 is connected to the second electrode d3 of the first
  • the second scan signal terminal is used to receive the second scan signal transmitted by the second scan signal line Gate2
  • the first initial signal terminal is used to receive the first initial signal transmitted by the first initial signal line Vinit1
  • the first reset signal terminal is used to receive the first reset signal transmitted by the first reset signal line Reset1
  • the data signal terminal is used to receive the data signal transmitted by the data signal line Vdata
  • the first scan signal terminal is used to receive the first scan signal transmitted by the first scan signal line Gate1
  • the power signal terminal is used to receive the power signal transmitted by the power signal line ELVDD
  • the light control signal terminal is used to receive the light control signal transmitted by the light control signal line EM.
  • the second initial signal end is used to receive the second initial signal transmitted by the second initial signal line Vinit2
  • the second reset signal end is used to receive the second reset signal transmitted by the second reset signal line Reset2
  • the third initial signal end is used to receive the third initial signal transmitted by the third initial signal line Vinit3.
  • the timing diagram of the pixel driving circuit 10 shown in Figure 7 is shown in Figure 8, where EM represents the timing diagram of the light-emitting control signal transmitted by the light-emitting control signal line EM; Gate1 represents the timing diagram of the first scanning signal transmitted by the first scanning signal line Gate1; Gate2 represents the timing diagram of the second scanning signal transmitted by the second scanning signal line Gate2; Reset1 represents the timing diagram of the first reset signal transmitted by the first reset signal line Reset1; Reset2 represents the timing diagram of the second reset signal transmitted by the second reset signal line Reset2.
  • the driving method of the pixel driving circuit 10 in the present disclosure may include a scanning frame Ft.
  • the scanning frame Ft may include: a first reset stage t1, a second reset stage t2, a third reset stage t3, a data writing stage t4, and a light emitting stage t5.
  • the first reset stage t1 the second scanning signal terminal outputs a high level signal
  • the second reset signal line Reset2 outputs a low level signal
  • the compensation transistor T2 the second reset transistor T7 and the third reset transistor T8 are turned on, the second initial signal terminal inputs the second initial signal to the first electrode s3 of the light emitting device L
  • the third initial signal terminal inputs the third initial signal to the first electrode s3 of the driving transistor T3.
  • the driving transistor T3 can be turned on, and the third initial signal terminal writes a reset signal to the gate g3 of the driving transistor T3; in the second reset stage t2: the second scanning signal terminal outputs a high level signal, the first reset signal terminal outputs a low level signal, the first reset transistor T1 and the compensation transistor T2 are turned on, and the first initial signal terminal inputs the first initial signal to the gate g3 of the driving transistor T3.
  • the second scanning signal terminal outputs a high level signal, the first reset signal terminal outputs a low level signal, the first reset transistor T1 and the compensation transistor T2 are turned on, and the first initial signal terminal inputs the first initial signal to the gate g3 of the driving transistor T3;
  • the data writing stage t4 the first scanning signal terminal outputs a low level signal, the second scanning signal terminal outputs a high level signal, the compensation transistor T2 and the data writing transistor T4 are turned on, and the data signal terminal outputs a data signal to write a compensation voltage to the gate g3 of the driving transistor T3;
  • the light emitting stage t5 the light emitting control signal terminal outputs a low level signal, the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on, and the driving transistor T3 drives the light emitting device L to emit light under the voltage of its gate g3.
  • the gate g3 of the driving transistor T3 is connected to the first initial signal terminal through the compensation transistor T2 and the first reset transistor T1, so that the leakage current of the driving transistor T3 to the first initial signal terminal during the light-emitting stage can be reduced.
  • the third initial signal terminal inputs a reset signal to the gate g3 of the driving transistor T3 and inputs a third initial signal to the first electrode g3 of the driving transistor T3. This setting can restore the hysteresis of the driving transistor T3 caused by the bias voltage of the previous frame. And solve problems such as dim brightness of the first frame.
  • the pixel driving circuit 10 may also have other driving methods, and the present disclosure does not limit the driving method of the pixel driving circuit 10 .
  • the display panel 100 includes: an array substrate 1 and a light emitting device L, and a pixel driving circuit 10 on the array substrate 1 is used to drive the light emitting device L to emit light.
  • the array substrate 1 includes: a first semiconductor layer 13, a first gate conductive layer 15, a second gate conductive layer 17, a second semiconductor layer 61, a third gate conductive layer 62, a first source-drain metal layer 19, and a second source-drain metal layer 21, which are sequentially stacked on a substrate 101.
  • an insulating layer is also provided between the functional film layers of the array substrate 1.
  • the functional film layers include: a first semiconductor layer 13, a first gate conductive layer 15, a second gate conductive layer 17, a second semiconductor layer 61, a third gate conductive layer 62, a first source-drain metal layer 19, and a second source-drain metal layer 21.
  • the insulating layer between the functional film layers is not shown.
  • the insulating layer includes: a first gate insulating layer 103 , a second gate insulating layer 104 , a first inorganic insulating layer 105 , a third gate insulating layer 106 , a second inorganic insulating layer 107 , a passivation layer 108 , a first planarization layer 109 and a second planarization layer 110 .
  • the pixel driving circuit 10 includes a first semiconductor layer 13, a first gate insulating layer 103, a first gate conductive layer 15, a second gate insulating layer 104, a second gate conductive layer 17, a first inorganic insulating layer 105, a second semiconductor layer 61, a third gate insulating layer 106, a third gate conductive layer 62, a second inorganic insulating layer 107, a first source-drain metal layer 19, a passivation layer 108, a first planarization layer 109, a second source-drain metal layer 21 and a second planarization layer 110 which are stacked in sequence.
  • the material of the first planarization layer 109 and the second planarization layer 110 includes polyimide
  • the material of the first inorganic insulating layer 105 and the second inorganic insulating layer 107 includes any one of silicon nitride and silicon oxide.
  • the following is an introduction to the conductive connection pattern M1 and the conductive pattern Q of the present disclosure.
  • the following embodiments can be understood based on the introduction to the film layer design of the pixel driving circuit 10 and the array substrate 1 in the above example.
  • the array substrate 1 further includes: a first semiconductor layer 13 disposed on the base 101 , and the conductive connection pattern M1 is located in the first semiconductor layer 13 .
  • the material of the first semiconductor layer 13 includes P-Si (polycrystalline silicon).
  • the conductive connection pattern M1 is located in the first semiconductor layer 13, and the parasitic capacitance of the second node N2 includes a parasitic capacitance between the conductive connection pattern M1 located in the first semiconductor layer 13 and the first gate conductive layer 15, a parasitic capacitance between the conductive connection pattern M1 and the second gate conductive layer 17, or a parasitic capacitance between the conductive connection pattern M1 and the first source and drain metal layer 19, etc.
  • the array substrate 1 further includes: a shielding layer 11 disposed on the substrate 101 , and a first semiconductor layer 13 disposed on a side of the shielding layer 11 away from the substrate 101 , and the conductive pattern Q is located on the shielding layer 11 .
  • the overlapping area of the orthographic projection of the conductive connection pattern M1 in the odd-numbered circuit group O1 on the substrate 101 and the orthographic projection of the shielding layer 11 on the substrate 101 is smaller than the overlapping area of the orthographic projection of the conductive connection pattern M1 in the even-numbered circuit group E1 on the substrate 101 and the orthographic projection of the shielding layer 11 on the substrate 101.
  • the conductive connection pattern M1 in the odd-numbered circuit group O1 can be designed in the same shape as the conductive connection pattern M1 in the even-numbered circuit group E1, and the area is equal.
  • the area of the second conductive pattern Q2 is larger than the area of the first conductive pattern Q1, so that the overlapping area of the orthographic projection of the first conductive pattern Q1 on the substrate 101 and the orthographic projection of the conductive connection pattern M1 on the substrate 101 is smaller than the overlapping area of the orthographic projection of the second conductive pattern Q2 on the substrate 101 and the orthographic projection of the conductive connection pattern M1 on the substrate 101.
  • the parasitic capacitance of the pixel driving circuit 10 of the even-numbered circuit group E1 at the second node N2 is greater than the parasitic capacitance of the pixel driving circuit 10 of the odd-numbered circuit group O1 at the second node N2.
  • the overlapping area of the orthographic projection of the first conductive pattern Q1 on the substrate 101 and the orthographic projection of the conductive connection pattern M1 on the substrate 101 can be smaller than the overlapping area of the orthographic projection of the second conductive pattern Q2 on the substrate 101 and the orthographic projection of the conductive connection pattern M1 on the substrate 101.
  • the entire layout design of the array substrate 1 such that the overlapping area of the orthographic projections of all the first conductive patterns Q1 on the substrate 101 and the orthographic projections of the conductive connection pattern M1 on the substrate 101 is smaller than the overlapping area of the orthographic projections of all the second conductive patterns Q2 on the substrate 101 and the orthographic projections of the conductive connection pattern M1 on the substrate 101.
  • the parasitic capacitance Ce of the pixel driving circuit 10 of the even-numbered circuit group E1 at the second node N2 is greater than the parasitic capacitance Co of the pixel driving circuit 10 of the odd-numbered circuit group O1 at the second node N2, which is not limited here.
  • the shielding layer 11 may be connected to a fixed potential to shield the influence of surrounding stray charges on the driving transistor T3.
  • the array substrate 1 further includes a first gate conductive layer 15 disposed on a side of the first semiconductor layer 13 away from the substrate 101 , and a second gate conductive layer 17 disposed on a side of the first gate conductive layer 15 away from the substrate 101 .
  • the pixel driving circuit 10 further includes: a capacitor Cst and a compensation transistor T2, the capacitor Cst includes: a first electrode plate Cst1 and a second electrode plate Cst2, the first electrode plate Cst1 is located in the first gate conductive layer 15, and the second electrode plate Cst2 is located in the second gate conductive layer 17.
  • the first electrode plate Cst1 is electrically connected to the first electrode region S2 of the compensation transistor T2, and the second electrode plate Cst2 is electrically connected to the power signal line ELVDD.
  • first electrode plate Cst1 is connected to the first electrode region S2 of the compensation transistor T2 through a via
  • the second electrode plate Cst2 is connected to the power signal line ELVDD through a via
  • the first electrode region S5 of the first light-emitting control transistor T5 is connected to the power signal line ELVDD through a via.
  • the connection pattern between the first electrode plate Cst1 and the first electrode region S2 of the compensation transistor T2, and the connection pattern between the second electrode plate Cst2 and the power signal line ELVDD are not shown.
  • the conductive pattern Q includes a first portion Qa located at the shielding layer 11 and a second portion Qb electrically connected to the second electrode plate Cst2 .
  • a shielding layer 11, a first semiconductor layer 13, and a second gate conductive layer 17 are sequentially disposed on one side of the substrate 101, and F represents the incident direction of the projection line, which may be perpendicular to the plane of the substrate 101.
  • F represents the incident direction of the projection line, which may be perpendicular to the plane of the substrate 101.
  • the overlapping area of the second electrode plate Cst2 and the conductive connection pattern M1 is equal to the overlapping area of the orthographic projection of the second electrode plate Cst2 on the substrate 101 and the orthographic projection of the conductive connection pattern M1 on the substrate 101.
  • the overlapping area of the orthographic projection of the conductive pattern Q and the conductive connection pattern M1 on the substrate 101 includes two parts: the overlapping area of the second part Qb of the second electrode plate Cst2 and the conductive connection pattern M1 in the projection line direction, and the overlapping area of the first part Qa of the shielding layer 11 and the conductive connection pattern M1 in the projection line direction. Therefore, in this embodiment, the conductive connection pattern M1 is located between the second electrode plate Cst2 and the shielding layer 11, and an interlayer parasitic capacitor is formed on the conductive connection pattern M1.
  • the size of the interlayer parasitic capacitor is proportional to the sum of the overlapping area of the second part Qb of the second electrode plate Cst2 and the conductive connection pattern M1 in the projection line direction, and the overlapping area of the first part Qa of the shielding layer 11 and the conductive connection pattern M1 in the projection line direction.
  • the sum of the overlapping areas of the second portion Qb of the second electrode plate Cst2 in the odd-numbered circuit group O1 and the conductive connection pattern M1 in the projection line direction, and the overlapping areas of the first portion Qa of the shielding layer 11 and the conductive connection pattern M1 in the projection line direction, is smaller than the sum of the overlapping areas of the second portion Qb of the second electrode plate Cst2 in the even-numbered circuit group E1 and the conductive connection pattern M1 in the projection line direction.
  • the overlapping area and the sum of the overlapping areas of the first part Qa of the shielding layer 11 and the conductive connection pattern M1 in the projection line direction can achieve the purpose of designing the parasitic capacitance Ce of the second node N2 of the even-numbered circuit group E1 to be larger, and solve the problem of brightness difference between the light-emitting devices L driven by the odd-numbered circuit group O1 and the even-numbered circuit group E1.
  • the array substrate 1 includes a first gate conductive layer 15 disposed on a side of the first semiconductor layer 13 away from the substrate 101, and a second gate conductive layer 17 disposed on a side of the first gate conductive layer 15 away from the substrate 101.
  • the conductive pattern Q is located in the second gate conductive layer 17.
  • the pixel driving circuit 10 further includes a capacitor Cst, the capacitor Cst includes a first plate Cst1 and a second plate Cst2, the first plate Cst1 is located in the first gate conductive layer 15, and the second plate Cst2 is located in the second gate conductive layer 17.
  • the conductive pattern Q located in the second gate conductive layer 17 is electrically connected to the second plate Cst2, which can also be understood as the conductive pattern Q being located on the second plate Cst2.
  • the second electrode plate Cst2 in the odd-numbered circuit group O1 is provided with a first conductive pattern Q1
  • the second electrode plate Cst2 in the even-numbered circuit group E1 is provided with a second conductive pattern Q2.
  • the overlapping area of the orthographic projection of the first conductive pattern Q1 in the odd-numbered circuit group O1 on the substrate 101 and the orthographic projection of the conductive connection pattern M1 on the substrate 101 is smaller than the overlapping area of the orthographic projection of the second conductive pattern Q2 in the even-numbered circuit group E1 on the substrate 101 and the orthographic projection of the conductive connection pattern M1 on the substrate 101.
  • the purpose of achieving that the parasitic capacitance Ce generated by the even-numbered circuit group E1 at the second node N2 is greater than the parasitic capacitance Ce generated by the odd-numbered circuit group O1 at the second node N2 can solve the problem of brightness difference between the light-emitting devices L driven by the odd-numbered circuit group O1 and the even-numbered circuit group E1.
  • the orthographic projection area of the conductive pattern Q in the odd-numbered circuit group O1 on the substrate 101 is equal to the orthographic projection area of the conductive pattern Q in the even-numbered circuit group E1 on the substrate.
  • the conductive pattern Q is located on the second electrode plate Cst2, and the design area of the second electrode plate Cst2 in the odd-numbered circuit group O1 and the even-numbered circuit group E1 is consistent. It can also be said that in the layout design, the second electrode plates Cst2 in the odd-numbered circuit group O1 and the even-numbered circuit group E1 can have the same shape and equal area.
  • the conductive connection pattern M1 is connected to the first extended pattern U1 located in the first semiconductor layer 13 , and the orthographic projection of the conductive pattern Q on the substrate 101 covers the orthographic projection of the first extended pattern U1 on the substrate 101 .
  • the first extended pattern U1 is connected to the conductive connection pattern M1 and both are located in the first semiconductor layer 13, and the first extended pattern U1 and the conductive connection pattern M1 can be designed as an integral unit.
  • the design area of the conductive connection pattern M1 in the even-numbered circuit group E1 is greater than the design area of the conductive connection pattern M1 in the odd-numbered circuit group O1.
  • the orthographic projection of the second conductive pattern Q2 on the substrate 101 covers the orthographic projection of the first extended pattern U1 on the substrate 101. Therefore, in the even-numbered circuit group E1, the parasitic capacitance Ce of the second node N2 is related to the orthographic projection of the second conductive pattern Q2 on the substrate 101, the overlapping area of the conductive connection pattern M1 and the orthographic projection of the first extended pattern U1 on the substrate 101.
  • the overlapping area is larger than the overlapping area of the orthographic projection of the first conductive pattern Q1 on the substrate 101 and the orthographic projection of the conductive connection pattern M1 on the substrate 101 in the odd-numbered circuit group O1.
  • the design that the parasitic capacitance Ce of the second node N2 in the even-numbered circuit group E1 is larger than the parasitic capacitance Co of the second node N2 in the odd-numbered circuit group O1 can solve the problem of brightness difference between the light-emitting devices L driven by the odd-numbered circuit group O1 and the even-numbered circuit group E1.
  • the orthographic projection of the shielding layer 11 on the substrate 101 overlaps with the orthographic projection of the conductive connection pattern M1 on the substrate 101, and the overlapping area is the same. Therefore, in the even-row circuit group E1 and the odd-row circuit group O1, due to the existence of the shielding layer 11, the second node N2 generates equal parasitic capacitance, and therefore, does not affect the differentiated design of the parasitic capacitance of the even-row circuit group E1 and the odd-row circuit group O1 at the second node N2.
  • the conductive pattern Q is a definition of a pattern for differentially designing the parasitic capacitance of the second node N2 by comparing the even-numbered circuit group E1 with the odd-numbered circuit group O1.
  • the array substrate 1 further includes a second gate conductive layer 17 disposed on a side of the first semiconductor layer 13 away from the substrate 101.
  • the array substrate 1 further includes a second scan signal line Gate2, and the second scan signal line Gate2 is located in the second gate conductive layer 17.
  • the conductive pattern Q and the second scan signal line Gate2 are an integrated structure.
  • the design shape and area of the conductive connection pattern M1 are the same.
  • the orthographic projection of the second scanning signal line Gate2 on the substrate 101 overlaps with the orthographic projection of the conductive connection pattern M1 on the substrate 101.
  • the area of the first conductive pattern Q1 located at the second scanning signal line Gate2 in the odd-row circuit group O1 is smaller than the area of the second conductive pattern Q2 of the second scanning signal line Gate2 in the even-row circuit group E1.
  • the parasitic capacitance Ce of the second node N2 in the even-row circuit group E1 is greater than the parasitic capacitance Co of the second node N2 in the odd-row circuit group O1, which can solve the problem of brightness difference between the light-emitting devices L driven by the odd-row circuit group O1 and the even-row circuit group E1.
  • the orthographic projection of the shielding layer 11 on the substrate 101 overlaps with the orthographic projection of the conductive connection pattern M1 on the substrate 101, and the overlapping area is the same.
  • the orthographic projection of the second electrode plate Cst2 located on the second gate conductive layer 17 on the substrate 101 overlaps with the orthographic projection of the conductive connection pattern M1 on the substrate 101, and the overlapping area is the same.
  • the stacking area is the same.
  • the existence of the shielding layer 11 makes the second node N2 generate equal parasitic capacitance
  • the existence of the second electrode plate Cst2 makes the second node N2 generate equal parasitic capacitance, which does not affect the differentiated design of the parasitic capacitance of the even-row circuit group E1 and the odd-row circuit group O1 at the second node N2. Therefore, in the even-row circuit group E1 and the odd-row circuit group O1, the orthographic projection of the shielding layer 11 and the second electrode plate Cst2 on the substrate 101 overlaps with the orthographic projection of the conductive connection pattern M1 on the substrate 101, and is not called the above-mentioned conductive pattern Q.
  • the array substrate 1 further includes: a second gate conductive layer 17 disposed on a side of the first semiconductor layer 13 away from the substrate 101, and a first source-drain metal layer 19 disposed on a side of the second gate conductive layer 17 away from the substrate 101, and the first source-drain metal layer 19 includes a second extended pattern U2.
  • the conductive pattern Q is located in the second gate conductive layer 17, and in the even-numbered row circuit group E1, the second extended pattern U2 is connected to the conductive connection pattern M1 through the via H1.
  • the second extended pattern U2 located in the first source-drain metal layer 19 is connected to the conductive connection pattern M1 located in the first semiconductor layer 13 through a via H1, which is equivalent to increasing the area of the conductive connection pattern M1.
  • the second extended pattern U2 and the conductive connection pattern M1 have the same function, that is, they can form a parasitic capacitance with the conductive pattern Q.
  • the second conductive pattern Q2 is located at the second electrode plate Cst2, and the second electrode plate Cst2 is located at the second gate conductive layer 17.
  • the second extended pattern U2 is connected to the conductive connection pattern M1
  • the second electrode plate Cst2 is located between the second extended pattern U2 and the conductive connection pattern M1
  • a parasitic capacitor is formed between the conductive connection pattern M1 and the second conductive pattern Q2
  • a parasitic capacitor is also formed between the second extended pattern U2 and the second conductive pattern Q2, thereby achieving the purpose of increasing the parasitic capacitance Ce of the second node N2 in the even-numbered circuit group E1.
  • the overlapping area between the orthographic projection of the second extended pattern U2 in the odd-row circuit group O1 on the substrate 101 and the orthographic projection of the second electrode plate Cst2 on the substrate 101 can be set to be smaller than the overlapping area between the orthographic projection of the second extended pattern U2 in the even-row circuit group E1 on the substrate 101 and the orthographic projection of the second electrode plate Cst2 on the substrate 101, so as to realize the differentiated design of the parasitic capacitance of the second node N2 of the even-row circuit group E1 and the odd-row circuit group O1.
  • the second extension pattern U2 may not be provided in the odd-row circuit group O1.
  • the difference in parasitic capacitance of the second node N2 between the even-row circuit group E1 and the odd-row circuit group O1 is caused by providing the second extension pattern U2 in the even-row circuit group E1.
  • the array substrate 1 further includes: a first source-drain metal layer 19 disposed on a side of the first semiconductor layer 13 away from the substrate 101, the first source-drain metal layer 19 including a third The extended pattern U3, the third extended pattern U3 and the conductive connection pattern M1 are connected through the via H1.
  • the third extended pattern U3 is provided in both the even-numbered circuit group E1 and the odd-numbered circuit group O1, and the third extended pattern U3 in the even-numbered circuit group E1 and the odd-numbered circuit group O1 has the same shape and the same area.
  • the third extended pattern U3 is connected to the conductive connection pattern M1 through the via H1, which increases the area of the conductive connection pattern M1.
  • the third extended pattern U3 and the conductive connection pattern M1 have the same function, that is, they can form a parasitic capacitor with the conductive pattern Q.
  • the array substrate 1 further includes: a second source-drain metal layer 21 disposed on a side of the first source-drain metal layer 19 away from the substrate 101, and the second source-drain metal layer 21 includes a power signal line ELVDD.
  • the conductive pattern Q and the power signal line ELVDD are an integral structure.
  • the overlapping area of the orthographic projection of the third extended pattern U3 in the odd-numbered circuit group O1 on the substrate 101 and the orthographic projection of the conductive pattern Q on the substrate 101 is smaller than the overlapping area of the orthographic projection of the third extended pattern U3 in the even-numbered circuit group E1 on the substrate 101 and the orthographic projection of the conductive pattern Q on the substrate 101.
  • the second conductive pattern Q2 and the power signal line ELVDD are an integrated structure, and the orthographic projection of the second conductive pattern Q2 on the substrate 101 overlaps with the orthographic projection of the third extended pattern U3 on the substrate 101, so a parasitic capacitor is formed between the second conductive pattern Q2 and the third extended pattern U3, thereby achieving the purpose of increasing the parasitic capacitance Ce of the second node N2 in the even-numbered circuit group E1.
  • a second gate conductive layer 17 is provided between the third extended pattern U3 and the first semiconductor layer 13, and the orthographic projection of the pattern connected to the second electrode plate Cst2 located in the second gate conductive layer 17 on the substrate 101 overlaps with the orthographic projection of the third extended pattern U3 and the first semiconductor layer 13 on the substrate 101. Therefore, parasitic capacitance is formed between the first semiconductor layer 13 and the second electrode plate Cst2, between the second electrode plate Cst2 and the third extended pattern U3, and between the third extended pattern U3 and the second conductive pattern Q2, that is, a multi-layer capacitance is formed.
  • the orthographic projection of the power signal line ELVDD on the substrate 101 does not overlap with the orthographic projection of the third extended pattern U3 on the substrate 101 .
  • the power signal line ELVDD in the even-numbered circuit group E1 has an orthographic projection on the substrate 101 that overlaps with the orthographic projection of the third extended pattern U3 on the substrate 101, and the orthographic projection of the power signal line ELVDD in the odd-numbered circuit group O1 on the substrate 101 does not overlap with the orthographic projection of the third extended pattern U3 on the substrate 101.
  • the purpose of increasing the parasitic capacitance Ce of the second node N2 in the even-numbered circuit group E1 is achieved.
  • the orthographic projection of the third extended pattern U3 on the substrate 101 is The orthographic projection of the conductive connection pattern M1 on the substrate 101 overlaps.
  • the third extended pattern U3 is connected to the conductive connection pattern M1 through the via H1, so that the second electrode Cst2 disposed between the third extended pattern U3 and the conductive connection pattern M1 forms a parasitic capacitor with both the third extended pattern U3 and the conductive connection pattern M1, which is beneficial to increase the parasitic capacitance of the second node N2 in the pixel driving circuit 10.
  • the array substrate 1 further includes: a first source-drain metal layer 19 disposed on a side of the first semiconductor layer 13 away from the substrate 101, and a second source-drain metal layer 21 disposed on a side of the first source-drain metal layer 19 away from the substrate 101, wherein the second source-drain metal layer 21 includes a data signal line Vdata and a power signal line ELVDD.
  • the conductive pattern Q and the power signal line ELVDD are an integrated structure.
  • the overlapping area of the orthographic projections of the first conductive pattern and the conductive connection pattern M1 on the substrate 101 in the odd-numbered circuit group O1 is smaller than the overlapping area of the orthographic projections of the second conductive pattern Q2 and the conductive pattern Q on the substrate 101 in the even-numbered circuit group E1.
  • the data signal line Vdata is designed to be avoided so that the orthographic projection of the data signal line Vdata on the substrate 101 does not overlap with the orthographic projection of the conductive connection pattern M1 on the substrate 101.
  • the conductive pattern Q is located in a pattern located in a different layer from the conductive connection pattern M1 in the pixel driving circuit 10.
  • the conductive pattern Q is electrically connected to the reference voltage line ELVSS
  • the conductive pattern Q is electrically connected to the first initial signal line Vinit1
  • the conductive pattern Q is electrically connected to the second initial signal line Vinit2
  • the conductive pattern Q is electrically connected to other constant voltage lines, etc., which is not limited here.
  • the transistor includes: a first reset transistor T1, a compensation transistor T2, a second light emission control transistor T6 and a second reset transistor T7.
  • the array substrate 1 also includes: a first initial signal line Vinit1, a second initial signal line Vinit2, a data signal line Vdata and a power signal line ELVDD.
  • the first electrode region S1 of the first reset transistor T1 is electrically connected to the first initial signal line Vinit1
  • the second electrode region D1 of the first reset transistor T1 is electrically connected to the first electrode region S2 of the compensation transistor T2
  • the second electrode region D2 of the compensation transistor T2 is electrically connected to the second electrode region D3 of the driving transistor T3.
  • the first electrode region S6 of the second light-emitting control transistor T6 is electrically connected to the second electrode region D3 of the driving transistor T3
  • the second electrode region D6 of the second light-emitting control transistor T6 is electrically connected to the second electrode region D7 of the second reset transistor T7
  • the first electrode region S7 of the second reset transistor T7 is electrically connected to the second initial signal line Vinit2
  • the first electrode region S4 of the data writing transistor T4 is electrically connected to the data signal line Vdata
  • the first electrode region S5 of the first light-emitting control transistor T5 is electrically connected to the power signal line ELVDD.
  • the array substrate 1 further includes: a gate pattern G1 of a first reset transistor T1, a reset signal line Reset, a gate pattern G7 of a second reset transistor T7, a first scan The signal line Gate1, the gate pattern G5 of the first light emission control transistor T5, the gate pattern G6 of the second light emission control transistor T6 and the light emission control signal line EM.
  • the gate pattern G1 of the first reset transistor T1 is electrically connected to the reset signal line Reset
  • the gate pattern G7 of the second reset transistor T7 is electrically connected to the first scanning signal line Gate1
  • the gate pattern G5 of the first light emission control transistor T5 and the gate pattern G6 of the second light emission control transistor T6 are electrically connected to the light emission control signal line EM.
  • the array substrate 1 includes: a first semiconductor layer 13 disposed on one side of the substrate 101, and the conductive connection pattern M1 is located in the first semiconductor layer 13.
  • the array substrate 1 includes: a first gate conductive layer 15 disposed on the side of the first semiconductor layer 13 away from the substrate 101, and the first scanning signal line Gate1 and the light-emitting control signal line EM are located in the first gate conductive layer 15.
  • the array substrate 1 includes: a second gate conductive layer 17 disposed on the side of the first gate conductive layer 15 away from the substrate 101, and the first initial signal line Vinit1 and the reset signal line Reset are located in the second gate conductive layer 17.
  • the array substrate 1 includes: a first source-drain metal layer 19 disposed on the side of the second gate conductive layer 17 away from the substrate 101, and the second initial signal line Vinit2 is located in the first source-drain metal layer 19.
  • the array substrate 1 includes: a second source-drain metal layer 21 disposed on the side of the first source-drain metal layer 19 away from the substrate, and the data signal line Vdata and the power signal line ELVDD are located in the second source-drain metal layer 21.
  • the compensation transistor T2 and the first reset transistor T1 include oxide thin film transistors.
  • the compensation transistor T2 and the first reset transistor T1 include N-type oxide thin film transistors.
  • the array substrate 1 further includes: a second semiconductor layer 61 and a third gate conductive layer 62 disposed between the second gate conductive layer 17 and the first source-drain metal layer 19, and the third gate conductive layer 62 is disposed on a side of the second semiconductor layer 61 away from the substrate 101.
  • the material of the second semiconductor layer 61 includes indium gallium zinc oxide, but is not limited thereto.
  • the channel portions of the compensation transistor T2 and the first reset transistor T1 are located in the second semiconductor layer 61 , and the gate patterns of the compensation transistor T2 and the first reset transistor T1 are located in the third gate conductive layer 62 .
  • the array substrate 1 includes a substrate 101 and a plurality of pixel driving circuits 10 disposed on the substrate 101.
  • each of the plurality of pixel driving circuits 10 includes a transistor, and the transistor includes a driving transistor T3, a data writing transistor T4, and a first light emitting control transistor T5.
  • the array substrate 1 also includes: a first electrode region and a second electrode region of the transistor, the first electrode region S3 of the driving transistor T3, the second electrode region D4 of the data writing transistor T4 and the second electrode region D5 of the first light-emitting control transistor T5 are connected to form a conductive connection pattern M1, and the conductive connection pattern M1 is a continuous pattern.
  • the plurality of pixel driving circuits 10 are configured as an odd-numbered circuit group O1 and an even-numbered circuit group E1, wherein the odd-numbered circuit group O1 and the even-numbered circuit group E1 include a plurality of pixel driving circuits 10 arranged along a first direction X.
  • the road groups E1 are arranged alternately.
  • the first direction X and the second direction Y intersect.
  • the array substrate 1 further includes: a conductive pattern Q, the conductive pattern Q including a pattern in the pixel driving circuit 10 located in a different layer from the conductive connection pattern M1.
  • the capacitance Co formed by the conductive connection pattern M1 of at least one pixel driving circuit 10 in the odd-numbered circuit group O1 and the conductive pattern Q is smaller than the capacitance Ce formed by the conductive connection pattern M1 of at least one pixel driving circuit 10 in the even-numbered circuit group E1 and the conductive pattern Q.
  • an insulating layer is provided between each functional film layer of the array substrate 1, and by adjusting the difference of the insulating layer, a differentiated design of the capacitance Co formed by the conductive connection pattern M1 and the conductive pattern Q in the odd-numbered circuit group O1 and the capacitance Ce formed by the conductive connection pattern M1 and the conductive pattern Q in the even-numbered circuit group E1 (i.e., the capacitance value) can be achieved.
  • the insulating layer between the conductive connection pattern M1 and the conductive pattern Q of at least one pixel driving circuit 10 in the odd-numbered circuit group O1 is made of the same material as the insulating layer between the conductive connection pattern M1 and the conductive pattern Q of at least one pixel driving circuit 10 in the even-numbered circuit group E1.
  • the thickness of the insulating layer between the conductive connection pattern M1 and the conductive pattern Q in the odd-numbered circuit group O1 may be set to be greater than the thickness of the insulating layer between the conductive connection pattern M1 and the conductive pattern Q in the even-numbered circuit group E1.
  • the capacitance Co formed by the conductive connection pattern M1 and the conductive pattern Q in the odd-numbered circuit group O1 is smaller than the capacitance Ce formed by the conductive connection pattern M1 and the conductive pattern Q in the even-numbered circuit group E1.
  • the insulating layer between the conductive connection pattern M1 and the conductive pattern Q of at least one pixel driving circuit 10 in the odd-numbered row circuit group O1 and the insulating layer between the conductive connection pattern M1 and the conductive pattern Q of at least one pixel driving circuit 10 in the even-numbered row circuit group E1 include at least one insulating layer of the same material.
  • the design of using at least one insulating layer of the same material can reduce the process steps of forming the film layer of the array substrate 1.
  • the array substrate 1 further includes a first gate conductive layer 15 disposed on a side of the first semiconductor layer 13 away from the substrate 101, and a second gate conductive layer 17 disposed on a side of the first gate conductive layer 15 away from the substrate 101.
  • the pixel driving circuit 10 further includes a capacitor Cst, the capacitor Cst includes a first plate Cst1 and a second plate Cst2, the first plate Cst1
  • the second electrode Cst2 is located in the first gate conductive layer 15 and the second electrode Cst2 is located in the second gate conductive layer 17.
  • the capacitance of the capacitor Cst in the odd-numbered circuit group O1 is greater than the capacitance of the capacitor Cst in the even-numbered circuit group E1.
  • the storage capacitance of the capacitor Cst of the odd-numbered circuit group O1 is greater than the storage capacitance of the even-numbered circuit group E1, which is beneficial for the data signal in the even-numbered circuit group E1 to be quickly input into the first node N1, and makes up for the problem of insufficient time b for writing the data signal and threshold compensation to the first node N1 in the even-numbered circuit group E1.
  • the orthographic projection area of the first electrode plate Cst1 of the capacitor Cst in the odd-numbered circuit group O1 on the substrate 101 is greater than the orthographic projection area of the first electrode plate Cst1 of the capacitor Cst in the even-numbered circuit group E1 on the substrate 101. This achieves the purpose of making the capacitance of the capacitor Cst in the odd-numbered circuit group O1 greater than the capacitance of the capacitor Cst in the even-numbered circuit group E1.
  • the pixel driving circuit 10 provided on the array substrate 1 is used to drive the light emitting devices L emitting different colors of light.
  • the pixel driving circuit 10 includes: a first pixel driving circuit 10a, a second pixel driving circuit 10b, and a third pixel driving circuit 10c.
  • the first pixel driving circuit 10a is used to drive the light emitting device L emitting green light
  • the second pixel driving circuit 10b is used to drive the light emitting device L emitting red light
  • the third pixel driving circuit 10c is used to drive the light emitting device L emitting blue light.
  • the parasitic capacitance Ct of the second node N2 of the odd and even rows of the first pixel driving circuit 10a can be designed differently.
  • the capacitance Co of the second node N2 of the first pixel driving circuit 10a in the odd-numbered row circuit group O1 is smaller than the capacitance Ce of the second node N2 of the first pixel driving circuit 10a in the even-numbered row circuit group E1.
  • the parasitic capacitance Ct of the second node N2 of the second pixel driving circuit 10b and the third pixel driving circuit 10c is not designed differently.
  • the parasitic capacitance Ct of the second node N2 of the second pixel driving circuit 10b and the third pixel driving circuit 10c is equal.
  • the parasitic capacitance Ct of the second node N2 of the second pixel driving circuit 10b and the third pixel driving circuit 10c is set differently according to the chromaticity of the light-emitting device L emitting red light and the light-emitting device L emitting blue light.
  • the light-emitting device L emitting green light has a higher start-up voltage
  • the following two examples are provided to eliminate the problem of uneven display brightness caused by brightness differences.
  • the first pixel driving circuit 10a The capacitance of the capacitor Cst is smaller than the capacitance of the capacitor Cst of the second pixel driving circuit 10b and the third pixel driving circuit 10c.
  • the positive projection area of the first plate Cst1 of the capacitor Cst of the first pixel driving circuit 10a on the substrate 101 is smaller than the positive projection area of the first plate Cst1 of the capacitor Cst of the second pixel driving circuit 10b on the substrate 101, and smaller than the positive projection area of the first plate Cst1 of the capacitor Cst of the third pixel driving circuit 10c on the substrate 101.
  • the capacitance of the parasitic capacitor Ct of the second node N2 of the first pixel driving circuit 10a is greater than the capacitance of the parasitic capacitor Ct of the second node N2 of the second pixel driving circuit 10b, and greater than the capacitance of the parasitic capacitor Ct of the second node N2 of the third pixel driving circuit 10c.
  • the overlapping area of the orthographic projection of the conductive pattern Q of the first pixel driving circuit 10a and the conductive connection pattern M1 on the substrate 101 is greater than the overlapping area of the orthographic projection of the conductive pattern Q of the second pixel driving circuit 10b and the conductive connection pattern M1 on the substrate 101, and greater than the overlapping area of the orthographic projection of the conductive pattern Q of the third pixel driving circuit 10c and the conductive connection pattern M1 on the substrate 101.
  • Some embodiments of the present disclosure further provide a display device 1000 , as shown in FIG. 24 , the display device 1000 includes an array substrate 1 provided in any of the above embodiments.
  • the display device can be any device that displays whether it is moving (e.g., video) or fixed (e.g., still images) and whether it is text or images. More specifically, it is expected that the embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and/or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.
  • PDAs personal data assistants
  • GPS receivers/navigators cameras
  • MP4 video players camcorders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板（1），包括：基底（101）以及设置于基底（101）上的多个像素驱动电路（10），像素驱动电路（10）的驱动晶体管（T3）的第一极区（S3）、数据写入晶体管（T4）的第二极区（D4）和第一发光控制晶体管（T5）的第二极区（D5）连接为导电连接图案（M1），导电连接图案（M1）为连续的图案。多个像素驱动电路（10）被配置为：奇数排电路组（O1）和偶数排电路组（E1）。阵列基板（1）还包括：导电图案（Q），导电图案（Q）包括像素驱动电路（10）中的与导电连接图案（M1）位于不同层的图案。奇数排电路组（O1）中的至少一个像素驱动电路（10）的导电连接图案（M1）与导电图案（Q）在基底（101）上的正投影的交叠面积，小于偶数排电路组（E1）中的至少一个像素驱动电路（10）的导电连接图案（M1）与导电图案（Q）在基底（101）上的正投影的交叠面积。

Description

阵列基板及显示装置
本申请要求于2022年11月4日提交的、申请号为202211378086.2的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及显示装置。
背景技术
随着AMOLED(Active-Matrix Organic Light Emitting Diode，有源矩阵有机发光二极管)技术的成熟，越来越多的终端使用AMOLED作为显示面板。针对游戏类产品，市场对高帧频(90Hz、120Hz)AMOLED屏幕要求也越来越迫切。
发明内容
一方面，提供一种阵列基板，阵列基板包括：基底以及设置于所述基底上的多个像素驱动电路，所述多个像素驱动电路中的每个像素驱动电路包括：晶体管，所述晶体管包括：驱动晶体管、数据写入晶体管和第一发光控制晶体管。所述阵列基板还包括：所述晶体管的第一极区和第二极区，所述驱动晶体管的第一极区、所述数据写入晶体管的第二极区和所述第一发光控制晶体管的第二极区连接为导电连接图案，且所述导电连接图案为连续的图案。
所述多个像素驱动电路被配置为：奇数排电路组和偶数排电路组，所述奇数排电路组和所述偶数排电路组包括沿第一方向排列设置的多个所述像素驱动电路，沿第二方向，所述奇数排电路组和所述偶数排电路组交替设置，所述第一方向和所述第二方向相交叉。
所述阵列基板还包括：导电图案，所述导电图案包括所述像素驱动电路中的与所述导电连接图案位于不同层的图案。所述奇数排电路组中的至少一个像素驱动电路的所述导电连接图案与所述导电图案在所述基底上的正投影的交叠面积，小于所述偶数排电路组中的至少一个像素驱动电路的所述导电连接图案与所述导电图案在所述基底上的正投影的交叠面积。
在一些实施例中，所述晶体管还包括：补偿晶体管，所述阵列基板还包括：所述补偿晶体管的栅极图案和第二扫描信号线，所述补偿晶体管的栅极图案与所述第二扫描信号线电连接；所述补偿晶体管的第二极区与所述驱动晶体管的第二极区连接。所述多个像素驱动电路还被配置为：沿所述第二方向依次设置的多个像素组单元，所述多个像素组单元中的每个像素组单元包括：所述奇数排电路组和与所述奇数排电路组相邻设置的所述偶数排电路组。 每个所述像素组单元共用一条所述第二扫描信号线。
在一些实施例中，阵列基板还包括：设置于所述基底上的第一半导体层，所述导电连接图案位于所述第一半导体层。
在一些实施例中，阵列基板还包括：设置于所述基底上的遮挡层，以及设置于所述遮挡层远离所述基底一侧的第一半导体层。所述导电图案位于所述遮挡层。
在一些实施例中，阵列基板还包括：设置于所述第一半导体层远离所述基底一侧的第一栅导电层，以及设置于所述第一栅导电层远离基底一侧的第二栅导电层。所述像素驱动电路还包括：电容器和补偿晶体管，所述电容器包括：第一极板和第二极板，所述第一极板位于所述第一栅导电层，所述第二极板位于所述第二栅导电层。所述第一极板与所述补偿晶体管的第一极区电连接，所述第二极板与电源信号线电连接。所述导电图案包括：位于所述遮挡层的第一部分和与所述第二极板电连接的第二部分。
在一些实施例中，阵列基板还包括：设置于所述第一半导体层远离所述基底一侧的第一栅导电层，以及设置于所述第一栅导电层远离基底一侧的第二栅导电层。所述导电图案位于所述第二栅导电层。
在一些实施例中，所述奇数排电路组中的所述导电图案在所述基底上的正投影的面积，与所述偶数排电路组中的所述导电图案在所述基底上的正投影的面积相等。在所述偶数排电路组中，所述导电连接图案上连接有位于所述第一半导体层的第一扩展图案，所述导电图案在所述基底上的正投影，覆盖所述第一扩展图案在所述基底上的正投影。
在一些实施例中，所述阵列基板还包括：设置于所述第一半导体层远离所述基底一侧的第二栅导电层。所述阵列基板还包括第二扫描信号线，所述第二扫描信号线位于所述第二栅导电层。所述导电图案与所述第二扫描信号线为一体结构。
在一些实施例中，阵列基板还包括：设置于所述第一半导体层远离所述基底一侧的第一源漏金属层，所述第一源漏金属层包括第三扩展图案，所述第三扩展图案与所述导电连接图案通过过孔连接。阵列基板还包括：设置于所述第一源漏金属层远离所述基底一侧的第二源漏金属层，所述第二源漏金属层包括电源信号线。所述导电图案与所述电源信号线为一体结构，所述奇数排电路组中的所述第三扩展图案在所述基底上的正投影与所述导电图案在所述基底上的正投影的交叠面积，小于所述偶数排电路组中的所述第三扩展图案在所述基底上的正投影与所述导电图案在所述基底上的正投影的交叠面 积。
在一些实施例中，在所述奇数排电路组中，所述数据信号线在所述基底上的正投影，与所述第三扩展图案在所述基底上的正投影无交叠。
在一些实施例中，所述第三扩展图案在所述基底上的正投影，与所述导电连接图案在所述基底上的正投影有交叠。
在一些实施例中，所述晶体管包括：第一复位晶体管、补偿晶体管、第二发光控制晶体管和第二复位晶体管。所述阵列基板还包括：第一初始信号线、第二初始信号线、数据信号线和电源信号线。所述第一复位晶体管的第一极区与所述第一初始信号线电连接，所述第一复位晶体管的第二极区和所述补偿晶体管的第一极区电连接，所述补偿晶体管的第二极区与所述驱动晶体管的第二极区电连接。所述第二发光控制晶体管的第一极区与所述驱动晶体管的第二极区电连接，所述第二发光控制晶体管的第二极区与所述第二复位晶体管的第二极区电连接，所述第二复位晶体管的第一极区与所述第二初始信号线电连接。所述数据写入晶体管的第一极区与所述数据信号线电连接，所述第一发光控制晶体管的第一极区与所述电源信号线电连接。
在一些实施例中，阵列基板还包括：所述第一复位晶体管的栅极图案、复位信号线、所述第二复位晶体管的栅极图案、第一扫描信号线、所述第一发光控制晶体管的栅极图案、所述第二发光控制晶体管的栅极图案和发光控制信号线。所述第一复位晶体管的栅极图案与所述复位信号线电连接，所述第二复位晶体管的栅极图案与所述第一扫描信号线电连接，所述第一发光控制晶体管的栅极图案和所述第二发光控制晶体管的栅极图案与所述发光控制信号线电连接。
在一些实施例中，阵列基板还包括：设置于所述基底一侧的第一半导体层，所述导电连接图案位于所述第一半导体层；设置于所述第一半导体层远离所述基底一侧的第一栅导电层，所述第一扫描信号线和所述发光控制信号线位于所述第一栅导电层；设置于所述第一栅导电层远离所述基底一侧的第二栅导电层，所述第一初始信号线和所述复位信号线位于所述第二栅导电层；设置于所述第二栅导电层远离所述基底一侧的第一源漏金属层，所述第二初始信号线位于所述第一源漏金属层；设置于所述第一源漏金属层远离所述基底一侧的第二源漏金属层，所述数据信号线和所述电源信号线位于所述第二源漏金属层。
在一些实施例中，所述补偿晶体管和所述第一复位晶体管包括氧化物薄膜晶体管。阵列基板还包括：设置于所述第二栅导电层和所述第一源漏金属 层之间的第二半导体层和第三栅导电层，所述第三栅导电层设置于所述第二半导体层远离所述基底的一侧。
另一方面，提供一种阵列基板，该阵列基板包括：基底以及设置于所述基底上的多个像素驱动电路。所述多个像素驱动电路中的每个像素驱动电路包括：晶体管，所述晶体管包括：驱动晶体管、数据写入晶体管和第一发光控制晶体管。所述阵列基板还包括：所述晶体管的第一极区和第二极区；所述驱动晶体管的第一极区、所述数据写入晶体管的第二极区和所述第一发光控制晶体管的第二极区连接为导电连接图案，且所述导电连接图案为连续的图案。
所述多个像素驱动电路被配置为：奇数排电路组和偶数排电路组，所述奇数排电路组和所述偶数排电路组包括沿第一方向排列设置的多个所述像素驱动电路。沿第二方向，所述奇数排电路组和所述偶数排电路组交替设置；所述第一方向和所述第二方向相交叉。所述阵列基板还包括：导电图案，所述导电图案包括所述像素驱动电路中的与所述导电连接图案位于不同层的图案。所述奇数排电路组中的至少一个像素驱动电路的所述导电连接图案与所述导电图案之间形成的电容的容值，小于所述偶数排电路组中的至少一个像素驱动电路的所述导电连接图案与所述导电图案之间形成的电容的容值。
在一些实施例中，所述奇数排电路组中的至少一个像素驱动电路的所述导电连接图案与所述导电图案之间的绝缘层，和所述偶数排电路组中的至少一个像素驱动电路的所述导电连接图案与所述导电图案之间的绝缘层材质相同。
在一些实施例中，所述奇数排电路组中的至少一个像素驱动电路的所述导电连接图案与所述导电图案之间的绝缘层，和所述偶数排电路组中的至少一个像素驱动电路的所述导电连接图案与所述导电图案之间的绝缘层包括至少一层相同材质的绝缘层。
又一方面，提供一种显示装置，包括如上任一实施例所述的阵列基板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例所提供的显示面板的结构图；
图2为根据一些实施例所提供的像素驱动电路的等效电路图；
图3为根据一些实施例基于图2所提供的像素驱动电路的时序图；
图4为根据本公开一些实施例所提供的阵列基板的结构图；
图5为根据本公开一些实施例所提供的像素驱动电路的等效电路图；
图6为根据本公开一些实施例所提供的遮挡层、第一半导体层和第一栅导电层叠加后的结构图；
图7为根据本公开一些实施例所提供的像素驱动电路的另一种等效电路图；
图8为根据本公开一些实施例基于图7所提供的像素驱动电路的时序图；
图9为根据本公开一些实施例所提供的第一半导体层、第一栅导电层、第二栅导电层、第二半导体层和第三栅导电层叠加后的结构图；
图10为根据本公开一些实施例所提供的显示面板的结构图；
图11为根据本公开一些实施例所提供的遮挡层、第一半导体层、第一栅导电层和第二栅导电层叠加后的结构图；
图12为根据本公开一些实施例所提供的遮挡层、第一半导体层和第二栅导电层叠加后的局部结构图；
图13为根据本公开一些实施例所提供的第一半导体层、第一栅导电层和第二栅导电层叠加后的结构图；
图14为根据本公开一些实施例所提供的遮挡层、第一半导体层、第一栅导电层和第二栅导电层叠加后的另一种结构图；
图15为根据本公开一些实施例所提供的遮挡层、第一半导体层、第一栅导电层和第二栅导电层叠加后的又一种结构图；
图16为根据本公开一些实施例所提供的遮挡层、第一半导体层、第一栅导电层、第二栅导电层和第一源漏金属层叠加后的结构图；
图17为根据本公开一些实施例所提供的遮挡层、第一半导体层、第一栅导电层、第二栅导电层、第一源漏金属层和第二源漏金属层叠加后的结构图；
图18为根据本公开一些实施例所提供的遮挡层、第一半导体层、第一栅导电层、第二栅导电层、第一源漏金属层和第二源漏金属层叠加后的另一种结构图；
图19为根据本公开一些实施例所提供的遮挡层、第一半导体层、第一栅导电层、第二栅导电层、第二半导体层、第三栅导电层、第一源漏金属层和第二源漏金属层叠加后的结构图；
图20为根据本公开一些实施例所提供的第一半导体层、第一栅导电层和第二栅导电层叠加后的又一种结构图；
图21为根据本公开一些实施例所提供的像素驱动电路的又一种等效电路图；
图22为根据本公开一些实施例所提供的第一半导体层、第一栅导电层和第二栅导电层叠加后的又一种结构图；
图23为根据本公开一些实施例所提供的第一半导体层、第一栅导电层和第二栅导电层叠加后的又一种结构图；
图24为根据本公开一些实施例所提供的显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接， 或成一体；可以是直接相连，也可以通过中间媒介间接相连。术语“耦接”例如表明两个或两个以上部件有直接物理接触或电接触。术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层的厚度和区域的面积。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
随着有机发光二极管显示(Organic Light Emitting Diode，OLED)技术， 例如有源矩阵有机发光二极管(Active-Matrix Organic Light Emitting Diode，AMOLED)显示技术的发展，人们对显示产品的显示效果要求越来越高，显示产品中的像素驱动电路的设计对AMOLED产品的显示特性至关重要。
现有的像素驱动电路10'中，像素驱动电路10'包括：发光控制信号线EM、第一扫描信号线Gate1和第二扫描信号线Gate2。如图1所示，第一扫描信号线Gate1的GOA(Gate on Array，阵列基板行驱动)电路是一行驱动一行，第一扫描信号线Gate1的GOA电路包括：奇数行GOA电路(Gate1-odd GOA)和偶数行GOA电路(Gate1-even GOA)。然而，为了减少GOA电路对显示面板100'的边框区BB的占用以实现更窄边框的目的，发光控制信号线EM的GOA电路和第二扫描信号线Gate2的GOA电路采用的是一个GOA电路驱动两行(即一驱二)的驱动架构。即一个发光控制信号线EM的GOA电路和第二扫描信号线Gate2的GOA电路驱动位于显示区AA的两行像素驱动电路10'。
示例性的，如图2所示，相邻两行像素驱动电路10'中补偿晶体管T2采用的是同一条第二扫描信号线Gate2进行驱动。例如，第一复位晶体管T1和补偿晶体管T2采用LTPO(Low Temperature Polycrystalline Oxide，低温多晶氧化物)晶体管，高电平开启，其余晶体管采用LTPS(Low Temperature Poly-silicon，低温多晶硅)的P型晶体管，低电平开启。关于像素驱动电路10'的晶体管及其连接关系的具体介绍可以参见后续内容，此处不再赘述。
示例性的，如图3所示，为对应图2所示的像素驱动电路10'的驱动时序图，主要分为6个阶段：①发光控制信号线EM和复位信号线Reset同时为高电平，第一节点N1由第一初始信号线Vinit1信号重置；②第二扫描信号线Gate2跳变为高电平，奇数行odd和偶数行even像素驱动电路10'的补偿晶体管T2同时开启；③奇数行odd第一扫描信号线Gate1的扫描信号Gate1-odd为低电平，奇数行odd的数据信号写入和驱动晶体管T3阈值补偿同时进行；④偶数行even第一扫描信号线Gate1的扫描信号Gate1-even为低电平，偶数行even数据信号写入和驱动晶体管T3阈值补偿同时进行；⑤奇数行odd和偶数行even同时利用第二节点N2的寄生电容继续进行数据信号写入和驱动晶体管T3阈值补偿，至奇数行odd和偶数行even的补偿晶体管T2同时截止；⑥发光控制信号线EM为低电平，奇数行odd和偶数行even同时发光。
发明人发现，在上述的像素驱动电路10'中，通过图3的驱动时序图可以看到，奇数行odd自扫描信号Gate1-odd截止到第二扫描信号线Gate2信号截止的时长为a，偶数行even自扫描信号Gate1-even截止到第二扫描信号线 Gate2信号截止的时长为b，时长a比时长b长。
第一扫描信号线Gate1信号截止后，无论是奇数行odd还是偶数行even，像素驱动电路10'会通过第二节点N2的寄生电容Ct继续经过驱动晶体管T3对第一节点N1进行数据信号写入和阈值补偿。由于奇数行odd像素驱动电路10'和偶数行even的像素驱动电路10'的第二节点N2的寄生电容Ct大小完全一样，但是，奇数行odd和偶数行even继续进行数据信号写入的时长a和时长b不一样，时长a比时长b长，因此，会导致在同样的数据信号电压下奇数行odd和偶数行even补偿结果出现差异，最终体现在显示面板100'的显示上为奇数行odd暗，偶数行even亮，从而出现显示不良的问题，影响画面的品质。
基于此，本公开提供一种阵列基板1，如图4所示，阵列基板1包括基底101以及设置于基底101上的多个像素驱动电路10。如图5所示，多个像素驱动电路10中的每个像素驱动电路10包括：晶体管，晶体管包括：驱动晶体管T3、数据写入晶体管T4和第一发光控制晶体管T5。
如图6所示，阵列基板1还包括：晶体管的第一极区和第二极区，驱动晶体管T3的第一极区S3、数据写入晶体管T4的第二极区D4和第一发光控制晶体管T5的第二极区D5连接为导电连接图案M1，且导电连接图案M1为连续的图案。
在像素驱动电路10中，如图5所示，驱动晶体管T3、数据写入晶体管T4和第一发光控制晶体管T5的电连接汇合点为节点N2。因此，在阵列基板1的布图设计中，导电连接图案M1区域，与像素驱动电路10中的第二节点N2相对应。
可以理解的是，在像素驱动电路10中，晶体管包括：第一极和第二极，像素驱动电路10中晶体管的第一极，对应阵列基板1布图设计中的晶体管的第一极区，像素驱动电路10中晶体管的第二极，对应阵列基板1布图设计中的晶体管的第二极区。例如，图6中驱动晶体管T3的第一极区S3，对应图5中驱动晶体管T3的第一极s3。图6中数据写入晶体管T4的第二极区D4，对应图5中数据写入晶体管T4的第二极d4。图6中第一发光控制晶体管T5的第二极区D5，对应图5中第一发光控制晶体管T5的第二极d5。
因此，图6中驱动晶体管T3的第一极区S3、数据写入晶体管T4的第二极区D4和第一发光控制晶体管T5的第二极区D5连接的导电连接图案M1，对应驱动晶体管T3的第一极s3、数据写入晶体管T4的第二极d4和第一发光控制晶体管T5的第二极d5电连接汇合点即节点N2。那么，可以理解的是， 导电连接图案M1区域，与像素驱动电路10中的第二节点N2相对应是指，在第二节点N2存在的寄生电容，是由于在阵列基板1的布图设计中导电连接图案M1区域产生的寄生电容。
其中，寄生的含义是本来没有在此处设计电容，但由于布线之间总是有互容，互容可以认为是寄生在布线之间，所以叫寄生电容，又称杂散电容。
需要说明的是，在本公开的实施例提供的电路中，节点并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
如图4所示，多个像素驱动电路10被配置为：奇数排电路组O1和偶数排电路组E1，奇数排电路组O1和偶数排电路组E1包括沿第一方向X排列设置的多个像素驱动电路10。沿第二方向Y，奇数排电路组O1和偶数排电路组E1交替设置。第一方向X和第二方向Y相交叉。
示例性的，第一方向X为多个像素驱动电路10排列的行方向，每一行的像素驱动电路10称为一个电路组。第二方向Y为多个像素驱动电路10排列的列方向，多个电路组沿第二方向Y排列设置，分别为第一行、第二行、第三行…第n行，其中，第一行、第三行、第五行…均位于奇数行，均可以称为奇数排电路组O1。第二行、第四行、第六行…均位于偶数行，均可以称为偶数排电路组E1。因此，奇数排电路组O1和偶数排电路组E1交替设置。
示例性的，第一方向X和第二方向Y相垂直。
如图6、图11、图13～图17所示，阵列基板1还包括：导电图案Q，导电图案Q包括像素驱动电路10中的与导电连接图案M1位于不同层的图案。奇数排电路组O1中的至少一个像素驱动电路10的导电连接图案M1与导电图案Q在基底101上的正投影的交叠面积，小于偶数排电路组E1中的至少一个像素驱动电路10的导电连接图案M1与导电图案Q在基底101上的正投影的交叠面积。
需要说明的是，本公开中的“正投影”指的是，由垂直于投影面的、相互平行的投射线所产生的投影。
可以理解的是，如图4所示，像素驱动电路10设置于基底101上，图5～图17中未示出基底101，基底101的位置可以参照图4所示。
为了方便理解奇数排电路组O1的导电图案Q和偶数排电路组E1的导电图案Q，如图6、图11、图13～图17所示，将奇数排电路组O1的导电图案Q表示为第一导电图案Q1，偶数排电路组E1的导电图案Q表示为第二导电图案Q2。
当导电图案Q与导电连接图案M1在基底101上的正投影交叠时，导电图案Q与导电连接图案M1之间会产生寄生电容，寄生电容的大小，与导电图案Q与导电连接图案M1在基底101上的正投影的交叠面积大小有关。导电图案Q与导电连接图案M1在基底101上的正投影交叠面积越大，产生的寄生电容越大。
示例性的，如图5和图6所示，由于奇数排电路组O1中的导电连接图案M1在基底101上的正投影，与第一导电图案Q1在基底101上的正投影的交叠面积，小于偶数排电路组E1中的导电连接图案M1在基底101上的正投影，与第二导电图案Q2在基底101上的正投影的交叠面积。因此，偶数排电路组E1在第二节点N2产生的寄生电容Ce，大于奇数排电路组O1在第二节点N2产生的寄生电容Ce。
如前所述，奇数行odd和偶数行even继续进行数据信号写入的时长a和时长b不一样，时长a比时长b长，具体参照上述内容，此处不再赘述。本公开将奇数排电路组O1的第二节点N2的寄生电容Ce和偶数排电路组E1的第二节点N2的寄生电容Ce进行差异化设计，将奇数排电路组O1在第二节点N2的寄生电容Ce设计小一些，将偶数排电路组E1的第二节点N2的寄生电容Ce设计的大一些。
基于此设计，在现有补偿晶体管T2管一驱二的驱动架构下，虽然第一扫描信号线Gate1信号截止后，奇数排电路组O1中的补偿晶体管T2的补偿时长a，大于偶数排电路组E1中的补偿晶体管T2的补偿时长b。但是偶数排电路组E1中的第二节点N2的寄生电容Ce，大于奇数排电路组O1中的第二节点N2的寄生电容Co。
因此，在第一扫描信号线Gate1信号截止后，偶数排电路组E1中的第二节点N2电位下降慢，奇数排电路组O1中的第二节点N2电位下降快。虽然偶数排电路组E1中的补偿时长b比奇数排电路组O1中的补偿时长a短，但是，由于偶数排电路组E1中的第二节点N2电位下降慢，相同时长写入的电荷量更多，最终使得奇数排电路组O1和偶数排电路组E1的补偿效果一致。
在相同数据电压下，使得奇数排电路组O1的像素驱动电路10和偶数排电路组E1的像素驱动电路10驱动的发光器件L没有发光亮度的差异，从而解决由于奇偶行像素驱动电路10的补偿晶体管T2的补偿时长不一致引起的奇偶行亮度差异的问题，提升显示面板100图像显示的画质。
示例性的，导电图案Q位于像素驱动电路10中的与导电连接图案M1位于不同层的图案。导电图案Q与导电连接图案M1不连接，导电图案Q与导 电连接图案M1位于不同的膜层。
需要说明的是，如图6所示，为了更清楚的显示奇数排电路组O1和偶数排电路组E1中导电连接图案M1区域中，形成寄生电容的结构设计，图中未示出其他不影响寄生电容差异化设计的其他膜层，阵列基板1的其他膜层设计并不设限，以下同理。并且，本公开以示例导电连接图案M1区域的布图设计为主要部分，对于导电连接图案M1区域以外的其他区域的设计并不设限。
在一些实施例中，如图5和图7所示，晶体管还包括：补偿晶体管T2。如图9所示，阵列基板1还包括：补偿晶体管T2的栅极图案G2和第二扫描信号线Gate2，补偿晶体管T2的栅极图案G4和第二扫描信号线Gate2电连接。补偿晶体管T2的第二极区D2与驱动晶体管T3的第二极区D3连接。
如图4和图5所示，多个像素驱动电路10还被配置为：沿第二方向Y依次设置的多个像素组单元70，多个像素组单元70中的每个像素组单元70包括：奇数排电路组O1和与奇数排电路组O1相邻设置的偶数排电路组E1，每个像素组单元70共用一条第二扫描信号线Gate2。
示例性的，第二方向Y为多个像素驱动电路10排列的列方向，多个电路组沿第二方向Y排列设置，分别为第一行、第二行、第三行…第n行，其中，第一行和第二行为一个像素组单元70、第三行和第四行为一个像素组单元70、第五行和第六行为一个像素组单元70…，每个像素组单元70共用一条第二扫描信号线Gate2。
每个像素组单元70共用一条第二扫描信号线Gate2即为第二扫描信号线Gate2一驱二的驱动架构。在第二扫描信号线Gate2一驱二的驱动架构下，本公开的设计，即奇数排电路组O1中的导电连接图案M1在基底101上的正投影，与导电图案Q在基底101上的正投影的交叠面积，小于偶数排电路组E1中的导电连接图案M1在基底101上的正投影，与导电图案Q在基底101上的正投影的交叠面积，可以解决奇数排电路组O1和偶数排电路组E1驱动的发光器件L存在亮度差异的问题。
为了方便理解导电图案Q的设计，以下先介绍像素驱动电路10的示例结构，以及阵列基板1的布图设计的示例结构，可以理解的是，以下内容仅是对像素驱动电路10的结构和阵列基板1的布图设计结构的示例，并不是对素驱动电路10的结构和阵列基板1的布图设计结构的限制。
在一些实施例中，本公开中的像素驱动电路10可以为包括7T1C、8T1C或者9T1C的电路，其中T代表晶体管，位于T前面的数字表示为晶体管的个数，C代表电容器，位于C前面的数字表示为电容器的个数，示例性的， 7T1C表示7个晶体管和1个电容器。
在一些实施例中，介绍基于图5所示的像素驱动电路10的结构，像素驱动电路10包括：第一复位晶体管T1、补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7。
示例性的，如图5所示，第一复位晶体管T1包括：栅极g1、第一极s1和第二极d1，第一复位晶体管T1的栅极g1与复位信号线端电连接，第一复位晶体管T1的第一极s1与第一初始信号端电连接，第一复位晶体管T1的第二极d1与第一节点N1电连接。复位信号端用于接收复位信号线Reset传输的复位信号。第一初始信号端用于接收第一初始信号线Vinit1传输的初始信号。第一复位晶体管T1被配置为：响应于在复位信号线Reset处接收的复位信号，将第一初始信号线Vinit1处接收的初始信号传输至第一节点N1，对驱动晶体管T3的栅极g3进行复位。
需要说明的是，本公开晶体管的第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
示例性的，如图5所示，补偿晶体管T2包括：栅极g2、第一极s2和第二极d2，补偿晶体管T2的栅极g2与第二扫描信号端电连接，补偿晶体管T2的第一极s2与第一节点N1电连接，补偿晶体管T2的第二极d2与第三节点N3电连接。第二扫描信号端用于接收第二扫描信号线Gate2传输的扫描信号。补偿晶体管T2被配置为：响应于第二扫描信号线Gate2处接收的扫描信号，对驱动晶体管T3进行阈值补偿。
示例性的，如图5所示，驱动晶体管T3包括：栅极g3、第一极s3和第二极d3，驱动晶体管T3的栅极g3与第一节点N1电连接，驱动晶体管T3的第一极s3与第二节点N2电连接，驱动晶体管T3的第二极d3与第三节点N3电连接。驱动晶体管T3被配置为产生驱动电流信号。
示例性的，如图5所示，数据写入晶体管T4包括：栅极g4、第一极s4和第二极d4，数据写入晶体管T4的栅极g4与第一扫描信号端电连接，数据写入晶体管T4的第一极s4与数据信号端电连接，数据写入晶体管T4的第二 极d4与第二节点N2电连接。数据信号端用于接收数据信号线Vdata传输的数据信号。数据写入晶体管T4被配置为：响应于在第一扫描信号线Gate1处接收的扫描信号，将在数据信号线Vdata处接收的数据信号传输至驱动晶体管T3。
示例性的，如图5所示，第一发光控制晶体管T5包括：栅极g5、第一极g5和第二极d5，第一发光控制晶体管T5的栅极g5与发光控制信号端电连接，第一发光控制晶体管T5的第一极g5与电源信号端电连接，第一发光控制晶体管T5的第二极d5与第二节点N2电连接。发光控制信号端用于接收发光控制信号线EM传输的发光控制信号。电源信号端用于接收电源信号线ELVDD传输的电源信号。第一发光控制晶体管T5被配置为：响应于在发光控制信号线EM处接收的发光控制信号，将在电源信号线ELVDD处接收的电源信号传输至驱动晶体管T3。
示例性的，如图5所示，第二发光控制晶体管T6包括：栅极g6、第一极s6和第二极d6，第二发光控制晶体管T6的栅极g6与发光控制信号端电连接，第二发光控制晶体管T6的第一极s6与第三节点N3电连接，第二发光控制晶体管T6的第二极d6与第四节点N4电连接。第二发光控制晶体管T6被配置为：响应于在发光控制信号线EM处接收的发光控制信号，将驱动电流信号传输至发光器件L，用于驱动发光器件L发光。
示例性的，如图5所示，第二复位晶体管T7包括：栅极g7、第一极s7和第二极d7，第二复位晶体管T7的栅极g7与第一扫描信号端电连接，第二复位晶体管T7的第一极s7与第二初始信号端电连接，第二复位晶体管T7的第二极d7与第四节点N4电连接。第二复位晶体管T7被配置为：响应于在第一扫描信号线Gate1处接收的扫描信号，将第二初始信号线Vinit2处接收的初始信号传输至发光器件L，以对发光器件L进行复位。
示例性的，发光器件L的阳极与第四节点N4电连接，发光器件L的阴极与参考电压线ELVSS电连接。
示例性的，如图5所示，像素驱动电路10还包括：电容器Cst，电容器Cst包括：第一极板Cst1和第二极板Cst2，电容器Cst的第一极板Cst1与第一节点N1电连接，电容器Cst的第二极板Cst2与电源信号端电连接。
示例性的，第一复位晶体管T1和补偿晶体管T2可以采用氧化物薄膜晶体管，即LTPO(Low Temperature Polycrystalline Oxide，低温多晶氧化物)晶体管，高电平导通。驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7均为低温多晶硅薄膜晶 体管(Low Temperature Poly-silicon Thin Film Transistor)的P型晶体管，低电平导通。
上述像素驱动电路10的驱动时序图，可以参见图3，此处不再赘述。
需要说明的是，上述第一复位晶体管T1、补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7的示例并不是对晶体管类型的限制。
在一些实施例中，介绍基于图7所示的像素驱动电路10的结构，像素驱动电路10包括：第一复位晶体管T1、补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、第二复位晶体管T7、第三复位晶体管T8和电容器Cst。
其中，补偿晶体管T2可以为N型晶体管，第一复位晶体管T1、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、第二复位晶体管T7和第三复位晶体管T8可以为P型晶体管。
示例性的，如图7所示，补偿晶体管T2的第一极s2连接驱动晶体管T3的栅极g3，第二极d2连接驱动晶体管T3的第二极d3，栅极g2连接第二扫描信号端；第一复位晶体管T1的第一极s1连接第一初始信号端，第二极d1连接补偿晶体管T2的第二极d2，栅极g1连接第一复位信号端；数据写入晶体管T4的第一极s4连接数据信号端，第二极d4连接驱动晶体管T3的第一极s3，栅极g4连接第一扫描信号端；第一发光控制晶体管T5的第一极s5连接电源信号端，第二极d5连接驱动晶体管T3的第一极s3，栅极g5连接发光控制信号端；第二发光控制晶体管T6的第一极s6连接驱动晶体管T3的第二极d3，栅极g6连接发光控制信号端；第二复位晶体管T7的第一极s7连接第二初始信号端，第二极d7连接第二发光控制晶体管T6的第二极d6，栅极g7连接第二复位信号端；第三复位晶体管T8的第一极s8连接第三初始信号端，第二极d8连接驱动晶体管T3的第一极s3，栅极g8连接第二复位信号端；电容器Cst的第一极板Cst1连接驱动晶体管T3的栅极g3，第二极板Cst2连接电源信号端。该像素驱动电路10可以用于驱动发光器件L发光。
第二扫描信号端用于接收第二扫描信号线Gate2传输的第二扫描信号，第一初始信号端用于接收第一初始信号线Vinit1传输的第一初始信号，第一复位信号端用于接收第一复位信号线Reset1传输的第一复位信号，数据信号端用于接收数据信号线Vdata传输的数据信号，第一扫描信号端用于接收第一扫描信号线Gate1传输的第一扫描信号，电源信号端用于接收电源信号线ELVDD传输的电源信号，发光控制信号端用于接收发光控制信号线EM传输 的发光控制信号，第二初始信号端用于接收第二初始信号线Vinit2传输的第二初始信号，第二复位信号端用于接收第二复位信号线Reset2传输的第二复位信号，第三初始信号端用于接收第三初始信号线Vinit3传输的第三初始信号。
示例性的，如图7所示的像素驱动电路10的时序图如图8所示，EM表示发光控制信号线EM传输的发光控制信号的时序图；Gate1表示第一扫描信号线Gate1传输的第一扫描信号时序图；Gate2表示第二扫描信号线Gate2传输的第二扫描信号的时序图；Reset1表示第一复位信号线Reset1传输的第一复位信号的时序图；Reset2表示第二复位信号线Reset2传输的第二复位信号的时序图。
本公开中像素驱动电路10的驱动方法可以包括扫描帧Ft。扫描帧Ft可以包括：第一复位阶段t1、第二复位阶段t2、第三复位阶段t3、数据写入阶段t4、发光阶段t5。在第一复位阶段t1：第二扫描信号端输出高电平信号，第二复位信号线Reset2输出低电平信号，补偿晶体管T2、第二复位晶体管T7和第三复位晶体管T8导通，第二初始信号端向发光器件L的第一电极输入第二初始信号，第三初始信号端向驱动晶体管T3的第一极s3输入第三初始信号，同时，驱动晶体管T3可以导通，第三初始信号端向驱动晶体管T3栅极g3写入复位信号；在第二复位阶段t2：第二扫描信号端输出高电平信号，第一复位信号端输出低电平信号，第一复位晶体管T1、补偿晶体管T2导通，第一初始信号端向驱动晶体管T3的栅极g3输入第一初始信号；在第三复位阶段t3：第二扫描信号端输出高电平信号，第一复位信号端输出低电平信号，第一复位晶体管T1、补偿晶体管T2导通，第一初始信号端向驱动晶体管T3的栅极g3输入第一初始信号；在数据写入阶段t4，第一扫描信号端输出低电平信号，第二扫描信号端输出高电平信号，补偿晶体管T2、数据写入晶体管T4导通，数据信号端输出数据信号以向驱动晶体管T3的栅极g3写入补偿电压；在发光阶段t5：发光控制信号端输出低电平信号，第一发光控制晶体管T5、第二发光控制晶体管T6导通，驱动晶体管T3在其栅极g3的电压作用下驱动发光器件L发光。
本示例性实施例中，驱动晶体管T3的栅极g3通过补偿晶体管T2和第一复位晶体管T1连接第一初始信号端，从而可以降低驱动晶体管T3在发光阶段向第一初始信号端的漏电流。此外，在第一复位阶段t1，第三初始信号端向驱动晶体管T3的栅极g3输入复位信号，向驱动晶体管T3的第一极g3输入第三初始信号，该设置可以恢复驱动晶体管T3由于前一帧偏压造成的磁滞， 以及解决首帧亮度偏暗等问题。
需要说明的是，在其他示例性实施例中，该像素驱动电路10还可以有其他驱动方法，本公开不对像素驱动电路10的驱动方法进行限定。
以下示例性的介绍一种阵列基板1的膜层设计结构。需要说明的是，下述示例并不是对阵列基板1膜层结构设计的限制。
如图10所示，显示面板100包括：阵列基板1和发光器件L，阵列基板1上的像素驱动电路10用于驱动发光器件L发光。阵列基板1包括：在基底101上依次层叠设置的第一半导体层13、第一栅导电层15、第二栅导电层17、第二半导体层61、第三栅导电层62、第一源漏金属层19和第二源漏金属层21。
需要说明的是，阵列基板1的各功能膜层之间还设置有绝缘层。功能膜层包括：第一半导体层13、第一栅导电层15、第二栅导电层17、第二半导体层61、第三栅导电层62、第一源漏金属层19和第二源漏金属层21。在布图设计的示例图中，为了更清晰的表示功能膜层之间的层叠关系，未示出功能膜层之间的绝缘层。
示例性的，如图10所示，绝缘层包括：第一栅绝缘层103、第二栅绝缘层104、第一无机绝缘层105、第三栅绝缘层106、第二无机绝缘层107、钝化层108、第一平坦化层109和第二平坦化层110。
例如，像素驱动电路10包括依次层叠设置的第一半导体层13、第一栅绝缘层103、第一栅导电层15、第二栅绝缘层104、第二栅导电层17、第一无机绝缘层105、第二半导体层61、第三栅绝缘层106、第三栅导电层62、第二无机绝缘层107、第一源漏金属层19、钝化层108、第一平坦化层109、第二源漏金属层21和第二平坦化层110。
示例性的，第一平坦化层109和第二平坦化层110的材料包括聚酰亚胺，第一无机绝缘层105和第二无机绝缘层107的材料包括氮化硅和氧化硅中的任一种。
以下为本公开关于导电连接图案M1和导电图案Q的介绍，可以基于以上的示例的像素驱动电路10和阵列基板1的膜层设计的介绍理解以下实施例。
在一些实施例中，如图6、图11、图13～图17所示，阵列基板1还包括：设置于基底101上的第一半导体层13，导电连接图案M1位于第一半导体层13。
示例性的，第一半导体层13的材料包括P-Si(多晶硅)。
示例性的，导电连接图案M1位于第一半导体层13，第二节点N2的寄生电容包括位于第一半导体层13的导电连接图案M1与第一栅导电层15之间的寄生电容、导电连接图案M1与第二栅导电层17之间的寄生电容或导电连接图案M1与第一源漏金属层19之间的寄生电容等。
在一些实施例中，如图6所示，阵列基板1还包括：设置于基底101上的遮挡层11，以及设置于遮挡层11远离基底101一侧的第一半导体层13，导电图案Q位于遮挡层11。
示例性的，如图6所示，奇数排电路组O1中的导电连接图案M1在基底101上的正投影，与遮挡层11在基底101上的正投影的交叠面积，小于偶数排电路组E1中的导电连接图案M1在基底101上的正投影，与遮挡层11在基底101上的正投影的交叠面积。
也就是说，如图6所示，在第一半导体层13的布图设计中，奇数排电路组O1中的导电连接图案M1可以与偶数排电路组E1的导电连接图案M1的设计形状一致，且面积相等。在遮挡层11的布图设计中，第二导电图案Q2的面积，大于第一导电图案Q1的面积，使得第一导电图案Q1在基底101上的正投影与导电连接图案M1在基底101上的正投影的交叠面积，小于第二导电图案Q2在基底101上的正投影与导电连接图案M1在基底101上的正投影的交叠面积。从而实现在一个像素组单元70中，偶数排电路组E1的像素驱动电路10在第二节点N2的寄生电容，大于奇数排电路组O1的像素驱动电路10在第二节点N2的寄生电容的目的。
可以理解的是，可以在一个像素组单元70中，使得第一导电图案Q1在基底101上的正投影与导电连接图案M1在基底101上的正投影的交叠面积，小于第二导电图案Q2在基底101上的正投影与导电连接图案M1在基底101上的正投影的交叠面积。
也可以在阵列基板1的整个布图设计中，使得所有的第一导电图案Q1在基底101上的正投影与导电连接图案M1在基底101上的正投影的交叠面积，小于所有的第二导电图案Q2在基底101上的正投影与导电连接图案M1在基底101上的正投影的交叠面积。
即在一个像素组单元70中，达到偶数排电路组E1的像素驱动电路10在第二节点N2的寄生电容Ce，大于奇数排电路组O1的像素驱动电路10在第二节点N2的寄生电容Co的目的即可，此处并不设限。
示例性的，遮挡层11可以接入固定电位，屏蔽周边杂散电荷对驱动晶体管T3的影响。
在一些实施例中，如图11所示，阵列基板1还包括设置于第一半导体层13远离基底101一侧的第一栅导电层15，以及设置于第一栅导电层15远离基底101一侧的第二栅导电层17。
如图5和图9所示，像素驱动电路10还包括：电容器Cst和补偿晶体管T2，电容器Cst包括：第一极板Cst1和第二极板Cst2，第一极板Cst1位于第一栅导电层15，第二极板Cst2位于第二栅导电层17。第一极板Cst1与补偿晶体管T2的第一极区S2电连接，第二极板Cst2与电源信号线ELVDD电连接。
需要说明的是，第一极板Cst1与补偿晶体管T2的第一极区S2通过过孔连接，第二极板Cst2与电源信号线ELVDD通过过孔连接，第一发光控制晶体管T5的第一极区S5与电源信号线ELVDD通过过孔连接，为了更清楚的表示各个晶体管的位置，并未示出第一极板Cst1与补偿晶体管T2的第一极区S2之间的连接图案，及第二极板Cst2与电源信号线ELVDD之间的连接图案。
如图11和图12所示，导电图案Q包括：位于遮挡层11的第一部分Qa和与第二极板Cst2电连接的第二部分Qb。
示例性的，如图12所示，位于基底101的一侧依次设置有遮挡层11、第一半导体层13和第二栅导电层17，F代表投射线的入射方向，投射线的入射方向可以垂直基底101所在平面。从投射线的入射方向观察，第二极板Cst2与导电连接图案M1交叠的面积，等于第二极板Cst2在基底101上的正投影，与导电连接图案M1在基底101上的正投影的交叠面积。
从图12可以看出，导电图案Q与导电连接图案M1在基底101上的正投影的交叠面积包括两部分：第二极板Cst2的第二部分Qb与导电连接图案M1在投射线方向的交叠面积，以及遮挡层11的第一部分Qa与导电连接图案M1在投射线方向的交叠面积。因此，在该实施例中，导电连接图案M1位于第二极板Cst2和遮挡层11之间，在导电连接图案M1上形成了夹层寄生电容，该夹层寄生电容的大小与第二极板Cst2的第二部分Qb和导电连接图案M1在投射线方向的交叠面积，以及遮挡层11的第一部分Qa和导电连接图案M1在投射线方向的交叠面积之和成正比。
示例性的，如图12所示，奇数排电路组O1中的第二极板Cst2的第二部分Qb与导电连接图案M1在投射线方向的交叠面积，以及遮挡层11的第一部分Qa与导电连接图案M1在投射线方向的交叠面积之和，小于偶数排电路组E1中的第二极板Cst2的第二部分Qb与导电连接图案M1在投射线方向的 交叠面积，以及遮挡层11的第一部分Qa与导电连接图案M1在投射线方向的交叠面积之和。即可实现将偶数排电路组E1的第二节点N2的寄生电容Ce设计的大一些的目的，可以解决奇数排电路组O1和偶数排电路组E1驱动的发光器件L存在亮度差异的问题。
在一些实施例中，如图13所示，阵列基板1包括设置于第一半导体层13远离基底101一侧的第一栅导电层15，以及设置于第一栅导电层15远离基底101一侧的第二栅导电层17。导电图案Q位于第二栅导电层17。
示例性的，如图13所示，像素驱动电路10还包括：电容器Cst，电容器Cst包括：第一极板Cst1和第二极板Cst2，第一极板Cst1位于第一栅导电层15，第二极板Cst2位于第二栅导电层17。位于第二栅导电层17的导电图案Q与第二极板Cst2电连接，也可以理解为导电图案Q位于第二极板Cst2上。
示例性的，如图13所示，奇数排电路组O1中的第二极板Cst2设置有第一导电图案Q1，偶数排电路组E1中的第二极板Cst2设置有第二导电图案Q2。奇数排电路组O1中第一导电图案Q1在基底101上的正投影，与导电连接图案M1在基底101上的正投影的交叠面积，小于偶数排电路组E1中的第二导电图案Q2在基底101上的正投影，与导电连接图案M1在基底101上的正投影的交叠面积。实现偶数排电路组E1在第二节点N2产生的寄生电容Ce，大于奇数排电路组O1在第二节点N2产生的寄生电容Ce的目的，可以解决奇数排电路组O1和偶数排电路组E1驱动的发光器件L存在亮度差异的问题。
在一些实施例中，如图14所示，奇数排电路组O1中的导电图案Q在基底上101的正投影的面积，与偶数排电路组E1中的导电图案Q在基底上的正投影的面积相等。
示例性的，导电图案Q位于第二极板Cst2，在奇数排电路组O1和偶数排电路组E1中，第二极板Cst2的设计面积一致。也可以说，在布图设计中，奇数排电路组O1和偶数排电路组E1中的第二极板Cst2可以具有相同的形状和相等的面积。
如图14所示，在偶数排电路组E1中，导电连接图案M1上连接有位于第一半导体层13的第一扩展图案U1，导电图案Q在基底101上的正投影，覆盖第一扩展图案U1在基底101上的正投影。
示例性的，如图14所示，在偶数排电路组E1中，第一扩展图案U1与导电连接图案M1连接且均位于第一半导体层13，第一扩展图案U1与导电连接图案M1可以一体成型设计。也就是说，在偶数排电路组E1中导电连接图案M1的设计面积，大于奇数排电路组O1中导电连接图案M1的设计面积。
在偶数排电路组E1中，由于第二导电图案Q2在基底101上的正投影，覆盖第一扩展图案U1在基底101上的正投影。因此，在偶数排电路组E1中，第二节点N2的寄生电容Ce由第二导电图案Q2在基底101上的正投影，与导电连接图案M1和第一扩展图案U1在基底101上的正投影的交叠面积有关。该交叠面积大于奇数排电路组O1中，第一导电图案Q1在基底101上的正投影，与导电连接图案M1在基底101上的正投影的交叠面积。从而实现偶数排电路组E1中的第二节点N2的寄生电容Ce，大于奇数排电路组O1中的第二节点N2的寄生电容Co的设计，可以解决奇数排电路组O1和偶数排电路组E1驱动的发光器件L存在亮度差异的问题。
需要说明的是，如图14所示，在偶数排电路组E1和奇数排电路组O1中，遮挡层11在基底101上的正投影，与导电连接图案M1在基底101上的正投影有交叠，且交叠面积相同。因此，在偶数排电路组E1和奇数排电路组O1中，由于遮挡层11的存在使得第二节点N2产生相等的寄生电容，因此，不影响偶数排电路组E1和奇数排电路组O1在第二节点N2的寄生电容的差异化设计。
所以，可以理解的是，导电图案Q是将偶数排电路组E1和奇数排电路组O1进行比对，引起第二节点N2的寄生电容的差异化设计的图案的定义。
在一些实施例中，如图15所示，阵列基板1还包括设置于第一半导体层13远离基底101一侧的第二栅导电层17。阵列基板1还包括第二扫描信号线Gate2，第二扫描信号线Gate2位于第二栅导电层17。导电图案Q与第二扫描信号线Gate2为一体结构。
示例性的，如图15所示，在偶数排电路组E1和奇数排电路组O1中，导电连接图案M1的设计形状和面积相同。第二扫描信号线Gate2在基底101上的正投影与导电连接图案M1在基底101上的正投影有交叠。在奇数排电路组O1中位于第二扫描信号线Gate2的第一导电图案Q1的面积，小于在偶数排电路组E1中第二扫描信号线Gate2的第二导电图案Q2的面积。从而实现偶数排电路组E1中的第二节点N2的寄生电容Ce，大于奇数排电路组O1中的第二节点N2的寄生电容Co的设计，可以解决奇数排电路组O1和偶数排电路组E1驱动的发光器件L存在亮度差异的问题。
需要说明的是，如图15所示，在偶数排电路组E1和奇数排电路组O1中，遮挡层11在基底101上的正投影，与导电连接图案M1在基底101上的正投影有交叠，且交叠面积相同。位于第二栅导电层17的第二极板Cst2在基底101上的正投影，与导电连接图案M1在基底101上的正投影有交叠，且交 叠面积相同。
因此，在偶数排电路组E1和奇数排电路组O1中，由于遮挡层11的存在使得第二节点N2产生相等的寄生电容，由于第二极板Cst2的存在使得第二节点N2产生相等的寄生电容，均不影响偶数排电路组E1和奇数排电路组O1在第二节点N2的寄生电容的差异化设计。因此，在偶数排电路组E1和奇数排电路组O1中，遮挡层11和第二极板Cst2在基底101上的正投影，与导电连接图案M1在基底101上的正投影有交叠的部分，不称为上述的导电图案Q。
在一些实施例中，如图16所示，阵列基板1还包括：设置于第一半导体层13远离基底101一侧的第二栅导电层17，以及设置于所述第二栅导电层17远离基底101一侧的第一源漏金属层19，第一源漏金属层19包括第二扩展图案U2。导电图案Q位于第二栅导电层17，在偶数排电路组E1中，第二扩展图案U2与导电连接图案M1通过过孔H1连接。
示例性的，如图16所示，在偶数排电路组E1中，位于第一源漏金属层19的第二扩展图案U2与位于第一半导体层13的导电连接图案M1通过过孔H1连接，相当于增大了导电连接图案M1的面积，第二扩展图案U2和导电连接图案M1具有相同的功能，即可以与导电图案Q之间形成寄生电容。
因此，如图16所示，在偶数排电路组E1中，第二导电图案Q2位于第二极板Cst2，第二极板Cst2位于第二栅导电层17。第二扩展图案U2与导电连接图案M1处于连接的状态，第二极板Cst2位于第二扩展图案U2和导电连接图案M1之间，导电连接图案M1与第二导电图案Q2之间形成寄生电容，同时第二扩展图案U2与第二导电图案Q2之间也形成寄生电容，实现增加在偶数排电路组E1中第二节点N2的寄生电容Ce的目的。
示例性的，可以设置奇数排电路组O1中的第二扩展图案U2在基底101上的正投影，与第二极板Cst2在基底101上的正投影的交叠面积，小于偶数排电路组E1中的第二扩展图案U2在基底101上的正投影，与第二极板Cst2在基底101上的正投影的交叠面积，实现偶数排电路组E1和奇数排电路组O1的第二节点N2的寄生电容的差异化设计。
示例性的，如图16所示，在奇数排电路组O1中，可以不设置第二扩展图案U2，此时，可以认为偶数排电路组E1和奇数排电路组O1的第二节点N2的寄生电容的差异是由于在偶数排电路组E1中设置第二扩展图案U2引起的。
在一些实施例中，如图17所示，阵列基板1还包括：设置于第一半导体层13远离基底101一侧的第一源漏金属层19，第一源漏金属层19包括第三 扩展图案U3，第三扩展图案U3与导电连接图案M1通过过孔H1连接。
示例性的，在偶数排电路组E1和奇数排电路组O1中均设置有第三扩展图案U3，且在偶数排电路组E1和奇数排电路组O1中的第三扩展图案U3的形状一致、面积相等。第三扩展图案U3通过过孔H1与导电连接图案M1连接，增大了导电连接图案M1的面积，第三扩展图案U3和导电连接图案M1具有相同的功能，即可以与导电图案Q之间形成寄生电容。
如图17所示，阵列基板1还包括：设置于第一源漏金属层19远离基底101一侧的第二源漏金属层21，第二源漏金属层21包括电源信号线ELVDD。导电图案Q与电源信号线ELVDD为一体结构。奇数排电路组O1中的第三扩展图案U3在基底101上的正投影与导电图案Q在基底101上的正投影的交叠面积，小于偶数排电路组E1中的第三扩展图案U3在基底101上的正投影与导电图案Q在基底101上的正投影的交叠面积。
示例性的，如图17所示，在偶数排电路组E1中，第二导电图案Q2与电源信号线ELVDD为一体结构，第二导电图案Q2在基底101上的正投影，与第三扩展图案U3在基底101上的正投影有交叠，因此，第二导电图案Q2与第三扩展图案U3之间形成寄生电容。从而实现增加在偶数排电路组E1中第二节点N2的寄生电容Ce的目的。
并且，如图17所示，在偶数排电路组E1中，在第三扩展图案U3和第一半导体层13之间设置有第二栅导电层17，位于第二栅导电层17的与第二极板Cst2连接的图案在基底101上的正投影，与第三扩展图案U3和第一半导体层13在基底101上的正投影均有交叠。因此，第一半导体层13和第二极板Cst2之间、第二极板Cst2和第三扩展图案U3之间，第三扩展图案U3和第二导电图案Q2之间均形成了寄生电容，即形成了多层电容。
在一些实施例中，如图17所示，在奇数排电路组O1中，电源信号线ELVDD在基底101上的正投影，与第三扩展图案U3在基底101上的正投影无交叠。
示例性的，如图17所示，偶数排电路组E1的电源信号线ELVDD与奇数排电路组O1中的电源信号线ELVDD相比，偶数排电路组E1中的电源信号线ELVDD在基底101上的正投影，与第三扩展图案U3在基底101上的正投影有交叠，奇数排电路组O1中的电源信号线ELVDD在基底101上的正投影，与第三扩展图案U3在基底101上的正投影无交叠。实现增加在偶数排电路组E1中第二节点N2的寄生电容Ce的目的。
示例性的，如图17所示，第三扩展图案U3在基底101上的正投影，与 导电连接图案M1在基底101上的正投影有交叠。第三扩展图案U3与导电连接图案M1通过过孔H1连接，使得设置于第三扩展图案U3和导电连接图案M1之间的第二极板Cst2，与第三扩展图案U3和导电连接图案M1均形成寄生电容，有利于增加像素驱动电路10中第二节点N2的寄生电容。
在一些实施例中，如图18所示，阵列基板1还包括：设置于第一半导体层13远离基底101一侧的第一源漏金属层19，设置于第一源漏金属层19远离基底101一侧的第二源漏金属层21，第二源漏金属层21包括数据信号线Vdata和电源信号线ELVDD。导电图案Q与电源信号线ELVDD为一体结构。
在奇数排电路组O1中第一导电图案与导电连接图案M1在基底101上的正投影的交叠面积，小于偶数排电路组E1中第二导电图案Q2与导电图案Q在基底101上的正投影的交叠面积。为了避免数据信号线Vdata的影响，将数据信号线Vdata进行避让设计，使得数据信号线Vdata在基底101上的正投影，与导电连接图案M1在基底101上的正投影的无交叠。
在一些示例中，导电图案Q位于像素驱动电路10中的与导电连接图案M1位于不同层的图案。例如，导电图案Q与参考电压线ELVSS电连接、导电图案Q与第一初始信号线Vinit1电连接、导电图案Q与第二初始信号线Vinit2电连接或者导电图案Q与其他恒压线电连接等，此处并不设限。
结合以上关于导电连接图案M1和导电图案Q的介绍，以下示例又一种阵列基板1的膜层设计。
在一些实施例中，如图19所示，晶体管包括：第一复位晶体管T1、补偿晶体管T2、第二发光控制晶体管T6和第二复位晶体管T7。阵列基板1还包括：第一初始信号线Vinit1、第二初始信号线Vinit2、数据信号线Vdata和电源信号线ELVDD。
第一复位晶体管T1的第一极区S1与第一初始信号线Vinit1电连接，第一复位晶体管T1的第二极区D1和补偿晶体管T2的第一极区S2电连接，补偿晶体管T2的第二极区D2与驱动晶体管T3的第二极区D3电连接。第二发光控制晶体管T6的第一极区S6与驱动晶体管T3的第二极区D3电连接，第二发光控制晶体管T6的第二极区D6与第二复位晶体管T7的第二极区D7电连接，第二复位晶体管T7的第一极区S7与第二初始信号线Vinit2电连接，数据写入晶体管T4的第一极区S4与数据信号线Vdata电连接，第一发光控制晶体管T5的第一极区S5与电源信号线ELVDD电连接。
示例性的，如图9所示，阵列基板1还包括：第一复位晶体管T1的栅极图案G1、复位信号线Reset、第二复位晶体管T7的栅极图案G7、第一扫描 信号线Gate1、第一发光控制晶体管T5的栅极图案G5、第二发光控制晶体管T6的栅极图案G6和发光控制信号线EM。第一复位晶体管T1的栅极图案G1与复位信号线Reset电连接，第二复位晶体管T7的栅极图案G7与第一扫描信号线Gate1电连接，第一发光控制晶体管T5的栅极图案G5和第二发光控制晶体管T6的栅极图案G6与发光控制信号线EM电连接。
示例性的，如图19所示，阵列基板1包括：设置于基底101一侧的第一半导体层13，导电连接图案M1位于第一半导体层13。阵列基板1包括：设置于第一半导体层13远离基底101一侧的第一栅导电层15，第一扫描信号线Gate1和发光控制信号线EM位于第一栅导电层15。阵列基板1包括：设置于第一栅导电层15远离基底101一侧的第二栅导电层17，第一初始信号线Vinit1和复位信号线Reset位于第二栅导电层17。阵列基板1包括：设置于第二栅导电层17远离基底101一侧的第一源漏金属层19，第二初始信号线Vinit2位于第一源漏金属层19。阵列基板1包括：设置于第一源漏金属层19远离基底一侧的第二源漏金属层21，数据信号线Vdata和电源信号线ELVDD位于第二源漏金属层21。
在一些实施例中，如图9和图19所示，补偿晶体管T2和第一复位晶体管T1包括氧化物薄膜晶体管。例如，补偿晶体管T2和第一复位晶体管T1包括N型的氧化物薄膜晶体管。阵列基板1还包括：设置于第二栅导电层17和第一源漏金属层19之间的第二半导体层61和第三栅导电层62，第三栅导电层62设置于第二半导体层61远离基底101的一侧。
示例性的，第二半导体层61的材料包括铟镓锌氧化物，但不限于此。补偿晶体管T2和第一复位晶体管T1的沟道部分位于第二半导体层61，补偿晶体管T2和第一复位晶体管T1的栅极图案位于第三栅导电层62。
本公开的一些实施例还提供一种阵列基板1，如图4和图5所示，阵列基板1包括基底101以及设置于基底101上的多个像素驱动电路10。如图5所示，多个像素驱动电路10中的每个像素驱动电路10包括：晶体管，晶体管包括：驱动晶体管T3、数据写入晶体管T4和第一发光控制晶体管T5。
阵列基板1还包括：晶体管的第一极区和第二极区，驱动晶体管T3的第一极区S3、数据写入晶体管T4的第二极区D4和第一发光控制晶体管T5的第二极区D5连接为导电连接图案M1，且导电连接图案M1为连续的图案。
如图4所示，多个像素驱动电路10被配置为：奇数排电路组O1和偶数排电路组E1，奇数排电路组O1和偶数排电路组E1包括沿第一方向X排列设置的多个像素驱动电路10。沿第二方向Y，奇数排电路组O1和偶数排电 路组E1交替设置。第一方向X和第二方向Y相交叉。
如图6、图11、图13～图17所示，阵列基板1还包括：导电图案Q，导电图案Q包括像素驱动电路10中的与导电连接图案M1位于不同层的图案。奇数排电路组O1中的至少一个像素驱动电路10的导电连接图案M1与导电图案Q形成的电容Co的容值，小于偶数排电路组E1中的至少一个像素驱动电路10的导电连接图案M1与导电图案Q形成的电容Ce的容值。
示例性的，阵列基板1的各功能膜层之间设置有绝缘层，可以通过调整绝缘层的不同，实现奇数排电路组O1中的导电连接图案M1与导电图案Q形成的电容Co的容值，和偶数排电路组E1中的导电连接图案M1与导电图案Q形成的电容Ce之间的容值(即电容值)的差异化设计。
在一些实施例中，奇数排电路组O1中的至少一个像素驱动电路10的导电连接图案M1与导电图案Q之间的绝缘层，和偶数排电路组E1中的至少一个像素驱动电路10的导电连接图案M1与导电图案Q之间的绝缘层材质相同。
示例性的，可以通过设置奇数排电路组O1中的导电连接图案M1与导电图案Q之间的绝缘层厚度，大于偶数排电路组E1中的导电连接图案M1与导电图案Q之间的绝缘层厚度。从而使得奇数排电路组O1中导电连接图案M1与导电图案Q形成的电容Co的容值，小于偶数排电路组E1中的导电连接图案M1与导电图案Q形成的电容Ce的容值。
在一些实施例中，奇数排电路组中O1的至少一个像素驱动电路10的导电连接图案M1与导电图案Q之间的绝缘层，和偶数排电路组E1中的至少一个像素驱动电路10的导电连接图案M1与导电图案Q之间的绝缘层包括至少一层相同材质的绝缘层。
示例性的，通过调整奇数排电路组中O1的导电连接图案M1与导电图案Q之间的绝缘层，与偶数排电路组E1中的导电连接图案M1与导电图案Q之间的绝缘层的材质的差异，可以实现奇数排电路组O1中导电连接图案M1与导电图案Q形成的电容Co的容值，与偶数排电路组E1中的导电连接图案M1与导电图案Q形成的电容Ce的容值的差异化设计。并且，在奇数排电路组O1和偶数排电路组E1中，采用至少一层相同材质的绝缘层的设计，可以减少阵列基板1的膜层形成的工艺步骤。
在一些实施例中，如图11所示，阵列基板1还包括设置于第一半导体层13远离基底101一侧的第一栅导电层15，以及设置于第一栅导电层15远离基底101一侧的第二栅导电层17。如图9所示，像素驱动电路10还包括：电容器Cst，电容器Cst包括：第一极板Cst1和第二极板Cst2，第一极板Cst1 位于第一栅导电层15，第二极板Cst2位于第二栅导电层17。如图20所示，奇数排电路组O1中电容器Cst的容值，大于偶数排电路组E1中电容器Cst的容值。
也就是说，奇数排电路组O1的电容器Cst的存储电容，大于偶数排电路组E1中的存储电容，这样有利于偶数排电路组E1中的数据信号快速输入第一节点N1，弥补偶数排电路组E1中对对第一节点N1进行数据信号写入和阈值补偿的时长b不足的问题。
示例性的，如图20所示，奇数排电路组O1中电容器Cst的第一极板Cst1在基底101上的正投影面积，大于偶数排电路组E1中电容器Cst的第一极板Cst1在基底101上的正投影面积。实现奇数排电路组O1中电容器Cst的容值，大于偶数排电路组E1中电容器Cst的容值的目的。
在一些实施例中，如图21所示，阵列基板1上设置的像素驱动电路10用于驱动出射不同颜色光的发光器件L。像素驱动电路10包括：第一像素驱动电路10a、第二像素驱动电路10b和第三像素驱动电路10c。示例性的，第一像素驱动电路10a用于驱动出射绿色光的发光器件L，第二像素驱动电路10b用于驱动出射红色光的发光器件L，第三像素驱动电路10c用于驱动出射蓝色光的发光器件L。
如图21所示，由于出射绿色光的发光器件L出射的绿色光较亮，可以将第一像素驱动电路10a的奇偶行的第二节点N2的寄生电容Ct进行差异化设计。例如，奇数排电路组O1中第一像素驱动电路10a的第二节点N2的寄生电容Co的容值，小于偶数排电路组E1中第一像素驱动电路10a的第二节点N2的寄生电容Ce的容值。
第二像素驱动电路10b和第三像素驱动电路10c的第二节点N2的寄生电容Ct不进行差异化设计，例如，在奇数排电路组O1和偶数排电路组E1，第二像素驱动电路10b和第三像素驱动电路10c的第二节点N2的寄生电容Ct相等。或者，根据出射红色光的发光器件L和出射蓝色光的发光器件L的色度，对第二像素驱动电路10b和第三像素驱动电路10c的第二节点N2的寄生电容Ct进行差异化设置。
关于第二节点N2的寄生电容Ct的差异化设计的方案，可以参照上述内容，此处不再赘述。
在一些实施例中，由于出射绿色光的发光器件L的启亮电压较高，为了消除亮度差异造成的显示亮度不均的问题提供以下两种示例。
示例性的，如图22所示，在同一行电路组中，第一像素驱动电路10a的 电容器Cst的容值，小于第二像素驱动电路10b和第三像素驱动电路10c的电容器Cst的容值。例如，第一像素驱动电路10a的电容器Cst第一极板Cst1在基底101上的正投影面积，小于第二像素驱动电路10b的电容器Cst第一极板Cst1在基底101上的正投影面积，且小于第三像素驱动电路10c的电容器Cst第一极板Cst1在基底101上的正投影面积。
示例性的，如图23所示，在同一行电路组中，第一像素驱动电路10a的第二节点N2的寄生电容Ct的容值，大于第二像素驱动电路10b的第二节点N2的寄生电容Ct的容值，且大于第三像素驱动电路10c的第二节点N2的寄生电容Ct的容值。例如，第一像素驱动电路10a的导电图案Q与导电连接图案M1在基底101上的正投影的交叠面积，大于第二像素驱动电路10b的导电图案Q与导电连接图案M1在基底101上的正投影的交叠面积，且大于于第三像素驱动电路10c的导电图案Q与导电连接图案M1在基底101上的正投影的交叠面积。
本公开的一些实施例还提供一种显示装置1000，如图24所示，显示装置1000包括如上任一实施例所提供的阵列基板1。
本公开实施例所提供的显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种阵列基板，包括：基底以及设置于所述基底上的多个像素驱动电路；
    所述多个像素驱动电路中的每个像素驱动电路包括：晶体管，所述晶体管包括：驱动晶体管、数据写入晶体管和第一发光控制晶体管；
    所述阵列基板还包括：所述晶体管的第一极区和第二极区；所述驱动晶体管的第一极区、所述数据写入晶体管的第二极区和所述第一发光控制晶体管的第二极区连接为导电连接图案，且所述导电连接图案为连续的图案；
    所述多个像素驱动电路被配置为：奇数排电路组和偶数排电路组，所述奇数排电路组和所述偶数排电路组包括沿第一方向排列设置的多个所述像素驱动电路；沿第二方向，所述奇数排电路组和所述偶数排电路组交替设置；所述第一方向和所述第二方向相交叉；
    所述阵列基板还包括：导电图案，所述导电图案包括所述像素驱动电路中的与所述导电连接图案位于不同层的图案；
    所述奇数排电路组中的至少一个像素驱动电路的所述导电连接图案与所述导电图案在所述基底上的正投影的交叠面积，小于所述偶数排电路组中的至少一个像素驱动电路的所述导电连接图案与所述导电图案在所述基底上的正投影的交叠面积。
  2. 根据权利要求1所述的阵列基板，其中，所述晶体管还包括：补偿晶体管；
    所述阵列基板还包括：所述补偿晶体管的栅极图案和第二扫描信号线；所述补偿晶体管的栅极图案和所述第二扫描信号线电连接；所述补偿晶体管的第二极区与所述驱动晶体管的第二极区连接；
    所述多个像素驱动电路还被配置为：沿所述第二方向依次设置的多个像素组单元，所述多个像素组单元中的每个像素组单元包括：所述奇数排电路组和与所述奇数排电路组相邻设置的所述偶数排电路组；每个所述像素组单元共用一条所述第二扫描信号线。
  3. 根据权利要求1或2所述的阵列基板，其中，还包括：设置于所述基底上的第一半导体层，所述导电连接图案位于所述第一半导体层。
  4. 根据权利要求1～3任一项所述的阵列基板，其中，还包括：设置于所述基底上的遮挡层，以及设置于所述遮挡层远离所述基底一侧的第一半导体层；
    所述导电图案位于所述遮挡层。
  5. 根据权利要求3所述的阵列基板，其中，还包括：设置于所述第一半 导体层远离所述基底一侧的第一栅导电层，以及设置于所述第一栅导电层远离基底一侧的第二栅导电层；
    所述像素驱动电路还包括：电容器和补偿晶体管，所述电容器包括：第一极板和第二极板，所述第一极板位于所述第一栅导电层，所述第二极板位于所述第二栅导电层；所述第一极板与所述补偿晶体管的第一极区电连接，所述第二极板与电源信号线电连接；
    所述导电图案包括：位于所述遮挡层的第一部分和与所述第二极板电连接的第二部分。
  6. 根据权利要求3所述的阵列基板，其中，还包括：设置于所述第一半导体层远离所述基底一侧的第一栅导电层，以及设置于所述第一栅导电层远离基底一侧的第二栅导电层；所述导电图案位于所述第二栅导电层。
  7. 根据权利要求6所述的阵列基板，其中，所述奇数排电路组中的所述导电图案在所述基底上的正投影的面积，与所述偶数排电路组中的所述导电图案在所述基底上的正投影的面积相等；
    在所述偶数排电路组中，所述导电连接图案上连接有位于所述第一半导体层的第一扩展图案，所述导电图案在所述基底上的正投影，覆盖所述第一扩展图案在所述基底上的正投影。
  8. 根据权利要求3所述的阵列基板，其中，所述阵列基板还包括：设置于所述第一半导体层远离所述基底一侧的第二栅导电层；
    所述阵列基板还包括第二扫描信号线，所述第二扫描信号线位于所述第二栅导电层；
    所述导电图案与所述第二扫描信号线为一体结构。
  9. 根据权利要求3所述的阵列基板，其中，
    还包括：设置于所述第一半导体层远离所述基底一侧的第一源漏金属层，所述第一源漏金属层包括第三扩展图案，所述第三扩展图案与所述导电连接图案通过过孔连接；
    还包括：设置于所述第一源漏金属层远离所述基底一侧的第二源漏金属层，所述第二源漏金属层包括电源信号线；
    所述导电图案与所述电源信号线为一体结构；所述奇数排电路组中的所述第三扩展图案在所述基底上的正投影与所述导电图案在所述基底上的正投影的交叠面积，小于所述偶数排电路组中的所述第三扩展图案在所述基底上的正投影与所述导电图案在所述基底上的正投影的交叠面积。
  10. 根据权利要求9所述的阵列基板，其中，在所述奇数排电路组中， 所述电源信号线在所述基底上的正投影，与所述第三扩展图案在所述基底上的正投影无交叠。
  11. 根据权利要求9或10所述的阵列基板，其中，所述第三扩展图案在所述基底上的正投影，与所述导电连接图案在所述基底上的正投影有交叠。
  12. 根据权利要求1～11任一项所述的阵列基板，其中，
    所述晶体管包括：第一复位晶体管、补偿晶体管、第二发光控制晶体管和第二复位晶体管；
    所述阵列基板还包括：第一初始信号线、第二初始信号线、数据信号线和电源信号线；
    所述第一复位晶体管的第一极区与所述第一初始信号线电连接，所述第一复位晶体管的第二极区和所述补偿晶体管的第一极区电连接，所述补偿晶体管的第二极区与所述驱动晶体管的第二极区电连接；所述第二发光控制晶体管的第一极区与所述驱动晶体管的第二极区电连接，所述第二发光控制晶体管的第二极区与所述第二复位晶体管的第二极区电连接，所述第二复位晶体管的第一极区与所述第二初始信号线电连接；所述数据写入晶体管的第一极区与所述数据信号线电连接，所述第一发光控制晶体管的第一极区与所述电源信号线电连接。
  13. 根据权利要求12所述的阵列基板，其中，还包括：所述第一复位晶体管的栅极图案、复位信号线、所述第二复位晶体管的栅极图案、第一扫描信号线、所述第一发光控制晶体管的栅极图案、所述第二发光控制晶体管的栅极图案和发光控制信号线；
    所述第一复位晶体管的栅极图案与所述复位信号线电连接，所述第二复位晶体管的栅极图案与所述第一扫描信号线电连接，所述第一发光控制晶体管的栅极图案和所述第二发光控制晶体管的栅极图案与所述发光控制信号线电连接。
  14. 根据权利要求13所述的阵列基板，其中，还包括：
    设置于所述基底一侧的第一半导体层；所述导电连接图案位于所述第一半导体层；
    设置于所述第一半导体层远离所述基底一侧的第一栅导电层；所述第一扫描信号线和所述发光控制信号线位于所述第一栅导电层；
    设置于所述第一栅导电层远离所述基底一侧的第二栅导电层；所述第一初始信号线和所述复位信号线位于所述第二栅导电层；
    设置于所述第二栅导电层远离所述基底一侧的第一源漏金属层；所述第 二初始信号位于所述第一源漏金属层；
    设置于所述第一源漏金属层远离所述基底一侧的第二源漏金属层；所述数据信号线和所述电源信号线位于所述第二源漏金属层。
  15. 根据权利要求14所述的阵列基板，其中，所述补偿晶体管和所述第一复位晶体管包括氧化物薄膜晶体管；
    所述阵列基板还包括：设置于所述第二栅导电层和所述第一源漏金属层之间的第二半导体层和第三栅导电层，所述第三栅导电层设置于所述第二半导体层远离所述基底的一侧。
  16. 一种阵列基板，包括：基底以及设置于所述基底上的多个像素驱动电路；
    所述多个像素驱动电路中的每个像素驱动电路包括：晶体管，所述晶体管包括：驱动晶体管、数据写入晶体管和第一发光控制晶体管；
    所述阵列基板还包括：所述晶体管的第一极区和第二极区；所述驱动晶体管的第一极区、所述数据写入晶体管的第二极区和所述第一发光控制晶体管的第二极区连接为导电连接图案，且所述导电连接图案为连续的图案；
    所述多个像素驱动电路被配置为：奇数排电路组和偶数排电路组，所述奇数排电路组和所述偶数排电路组包括沿第一方向排列设置的多个所述像素驱动电路；
    沿第二方向，所述奇数排电路组和所述偶数排电路组交替设置；所述第一方向和所述第二方向相交叉；
    所述阵列基板还包括：导电图案，所述导电图案包括所述像素驱动电路中的与所述导电连接图案位于不同层的图案；
    所述奇数排电路组中的至少一个像素驱动电路的所述导电连接图案与所述导电图案之间形成的电容的容值，小于所述偶数排电路组中的至少一个像素驱动电路的所述导电连接图案与所述导电图案之间形成的电容的容值。
  17. 根据权利要求16所述的阵列基板，其中，所述奇数排电路组中的至少一个像素驱动电路的所述导电连接图案与所述导电图案之间的绝缘层，和所述偶数排电路组中的至少一个像素驱动电路的所述导电连接图案与所述导电图案之间的绝缘层材质相同。
  18. 根据权利要求16所述的阵列基板，其中，所述奇数排电路组中的至少一个像素驱动电路的所述导电连接图案与所述导电图案之间的绝缘层，和所述偶数排电路组中的至少一个像素驱动电路的所述导电连接图案与所述导电图案之间的绝缘层包括至少一层相同材质的绝缘层。
  19. 一种显示装置，包括如权利要求1～15中任一项所述的阵列基板，或如权利要求16～18中任一项所述的阵列基板。
PCT/CN2023/125969 2022-11-04 2023-10-23 阵列基板及显示装置 Ceased WO2024093702A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP23884634.9A EP4492465A4 (en) 2022-11-04 2023-10-23 NETWORK SUBSTRATE AND DISPLAY DEVICE
US18/843,127 US12417741B2 (en) 2022-11-04 2023-10-23 Array substrate and display device
US19/304,884 US20250374763A1 (en) 2022-11-04 2025-08-20 Array Substrate and Display Device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211378086.2A CN115911056B (zh) 2022-11-04 2022-11-04 阵列基板及显示装置
CN202211378086.2 2022-11-04

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US18/843,127 A-371-Of-International US12417741B2 (en) 2022-11-04 2023-10-23 Array substrate and display device
US19/304,884 Continuation US20250374763A1 (en) 2022-11-04 2025-08-20 Array Substrate and Display Device

Publications (1)

Publication Number Publication Date
WO2024093702A1 true WO2024093702A1 (zh) 2024-05-10

Family

ID=86482761

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/125969 Ceased WO2024093702A1 (zh) 2022-11-04 2023-10-23 阵列基板及显示装置

Country Status (4)

Country Link
US (2) US12417741B2 (zh)
EP (1) EP4492465A4 (zh)
CN (1) CN115911056B (zh)
WO (1) WO2024093702A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115911056B (zh) 2022-11-04 2026-04-07 京东方科技集团股份有限公司 阵列基板及显示装置
CN119234311A (zh) * 2023-04-28 2024-12-31 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置
WO2024229689A1 (en) * 2023-05-09 2024-11-14 Boe Technology Group Co., Ltd. Array substrate and display apparatus
EP4612730A4 (en) * 2023-06-01 2025-12-31 Boe Technology Group Co Ltd MATRIX SUBSTRATE AND DISPLAY DEVICE
WO2025043382A1 (zh) * 2023-08-25 2025-03-06 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111403465A (zh) * 2020-03-30 2020-07-10 昆山国显光电有限公司 阵列基板、显示面板和显示装置
CN113920934A (zh) * 2021-09-30 2022-01-11 成都京东方光电科技有限公司 显示基板和显示装置
US20220037370A1 (en) * 2020-08-03 2022-02-03 Au Optronics Corporation Pixel array substrate
CN114530464A (zh) * 2022-02-22 2022-05-24 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置
CN115911056A (zh) * 2022-11-04 2023-04-04 京东方科技集团股份有限公司 阵列基板及显示装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100335951C (zh) 2003-06-20 2007-09-05 友达光电股份有限公司 具有电容补偿的平面显示器
KR102833463B1 (ko) * 2016-10-11 2025-07-11 삼성디스플레이 주식회사 표시 장치
WO2021018304A1 (zh) * 2019-07-31 2021-02-04 京东方科技集团股份有限公司 显示基板以及显示装置
CN111968576B (zh) * 2020-08-21 2022-01-07 上海视涯技术有限公司 一种有机发光显示面板以及驱动方法
US20220320225A1 (en) * 2020-08-31 2022-10-06 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate and method for manufacturing the same, and display device
US12029073B2 (en) * 2020-08-31 2024-07-02 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate and display apparatus
CN114616669B (zh) * 2020-08-31 2026-01-30 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置
WO2022041238A1 (zh) * 2020-08-31 2022-03-03 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置
GB2610957A (en) * 2021-01-29 2023-03-22 Boe Technology Group Co Ltd Display substrate and display device
CN114361186B (zh) * 2022-01-05 2025-03-04 京东方科技集团股份有限公司 显示基板和显示装置
CN114783349B (zh) * 2022-05-27 2025-03-18 武汉天马微电子有限公司 显示面板及其驱动方法、显示装置
JP2025527385A (ja) * 2022-08-08 2025-08-22 京東方科技集團股▲ふん▼有限公司 表示基板及びその製造方法、表示装置
US20250098468A1 (en) * 2022-08-09 2025-03-20 Chengdu Boe Optoelectronics Technology Co., Ltd. Display Substrate, Preparation Method Therefor, and Display Apparatus

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111403465A (zh) * 2020-03-30 2020-07-10 昆山国显光电有限公司 阵列基板、显示面板和显示装置
US20220037370A1 (en) * 2020-08-03 2022-02-03 Au Optronics Corporation Pixel array substrate
CN113920934A (zh) * 2021-09-30 2022-01-11 成都京东方光电科技有限公司 显示基板和显示装置
CN114530464A (zh) * 2022-02-22 2022-05-24 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置
CN115911056A (zh) * 2022-11-04 2023-04-04 京东方科技集团股份有限公司 阵列基板及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4492465A4

Also Published As

Publication number Publication date
US20250201190A1 (en) 2025-06-19
US20250374763A1 (en) 2025-12-04
CN115911056A (zh) 2023-04-04
US12417741B2 (en) 2025-09-16
CN115911056B (zh) 2026-04-07
EP4492465A4 (en) 2025-08-20
EP4492465A1 (en) 2025-01-15

Similar Documents

Publication Publication Date Title
CN111696484B (zh) 像素驱动电路及其驱动方法、阵列基板及显示装置
WO2024093702A1 (zh) 阵列基板及显示装置
CN113192463B (zh) 发光控制移位寄存器、栅极驱动电路、显示装置及方法
CN114220384B (zh) 显示面板及其驱动方法、显示装置
US20250391355A1 (en) Array substrate and display panel
WO2025241781A1 (zh) 测试基板、显示面板及制备方法、显示装置
WO2023231742A9 (zh) 像素驱动电路及其驱动方法、显示面板、显示装置
WO2025149004A1 (zh) 像素电路的控制方法、显示面板及显示装置
CN111724743A (zh) 像素驱动电路及其驱动方法、显示装置
US20240221675A1 (en) Shift register, scan driving circuit and display substrate
WO2024244784A1 (zh) 显示面板及显示装置
WO2024109428A1 (zh) 显示面板及显示装置
CN116114398B (zh) 显示面板和显示装置
WO2024119503A1 (zh) 像素电路及其驱动方法、阵列基板、显示装置
WO2026001355A1 (zh) 显示面板及显示装置
WO2024036629A1 (zh) 显示基板及其驱动方法、显示装置
WO2023206167A1 (zh) 显示基板及显示装置
US20260024502A1 (en) Array Substrate, and Display Panel
US12455643B2 (en) Display panel and display device
US20250087153A1 (en) Pixel Circuit and Driving Method Thereof, Display Panel and Display Apparatus
WO2025200802A1 (zh) 像素电路及驱动方法、显示面板和显示装置
WO2025146091A1 (zh) 显示面板及显示装置
WO2025031073A1 (zh) 阵列基板、显示面板及显示装置
CN117746794A (zh) 显示面板和显示装置
WO2025050327A1 (zh) 显示基板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23884634

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 18843127

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2023884634

Country of ref document: EP

Ref document number: 23884634.9

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2023884634

Country of ref document: EP

Effective date: 20241011

NENP Non-entry into the national phase

Ref country code: DE

WWP Wipo information: published in national office

Ref document number: 18843127

Country of ref document: US

WWG Wipo information: grant in national office

Ref document number: 18843127

Country of ref document: US