WO2024108989A1 - 太阳电池及其制备方法 - Google Patents

太阳电池及其制备方法 Download PDF

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Publication number
WO2024108989A1
WO2024108989A1 PCT/CN2023/100575 CN2023100575W WO2024108989A1 WO 2024108989 A1 WO2024108989 A1 WO 2024108989A1 CN 2023100575 W CN2023100575 W CN 2023100575W WO 2024108989 A1 WO2024108989 A1 WO 2024108989A1
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Prior art keywords
layer
silicon substrate
type silicon
doped polysilicon
boron
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PCT/CN2023/100575
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English (en)
French (fr)
Inventor
张鹏
孟夏杰
邢国强
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Tongwei Solar Chengdu Co Ltd
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Tongwei Solar Chengdu Co Ltd
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Priority to US18/869,882 priority Critical patent/US20250351615A1/en
Priority to AU2023386275A priority patent/AU2023386275B2/en
Priority to EP23893089.5A priority patent/EP4503147A4/en
Publication of WO2024108989A1 publication Critical patent/WO2024108989A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/131—Recrystallisation; Crystallization of amorphous or microcrystalline semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/17—Photovoltaic cells having only PIN junction potential barriers
    • H10F10/174—Photovoltaic cells having only PIN junction potential barriers comprising monocrystalline or polycrystalline materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H10F71/1221—The active layers comprising only Group IV materials comprising polycrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H10F77/219—Arrangements for electrodes of back-contact photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • H10F77/707—Surface textures, e.g. pyramid structures of the substrates or of layers on substrates, e.g. textured ITO layer on a glass substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/546—Polycrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the technical field of solar cell production, and in particular to a solar cell and a method for preparing the same.
  • N-type single crystal IBC (Interdigitated back contact) solar cells usually use a diffusion process to form a heavily doped emitter and back field region on the back of the silicon wafer, which can effectively solve the problem of light blocking by metal grid lines and can significantly increase the short-circuit current density.
  • N-type single crystal IBC solar cells Compared with traditional crystalline silicon solar cells, N-type single crystal IBC solar cells have the following advantages in actual outdoor photovoltaic power stations and system applications: 1. High photoelectric conversion efficiency; 2. No light-induced degradation (LID) and high stability; 3. Good weak light response and low temperature coefficient; 4. Beautiful components, no grid line blocking the front, more beautiful appearance than traditional components, can be widely used in photovoltaic building integration; 5. Long service life.
  • a method for preparing a solar cell comprising the following steps:
  • a first silicon oxide layer On the back of the n-type silicon substrate, a first silicon oxide layer, an intrinsic amorphous silicon layer, a phosphorus silicon glass layer, and a a glass layer and a second silicon oxide layer;
  • a first electrode connected to the boron-doped polysilicon layer and a second electrode connected to the phosphorus-doped polysilicon layer are prepared.
  • the boron diffusion is performed on the back side of the n-type silicon substrate, comprising the following steps:
  • the back side of the n-type silicon substrate is subjected to diffusion treatment using a boron source at a temperature of 900° C. to 1050° C. for 1 h to 3 h.
  • the boron source is one or more of BCl 3 or BBr 3 .
  • the volume proportion of the boron source in the boron diffusion atmosphere is 5% to 30%.
  • removing the phosphosilicate glass layer and the second silicon oxide layer from a portion of the back side of the n-type silicon substrate comprises the following steps:
  • the patterned blocking layer is removed.
  • the patterned barrier layer is a waxy resin material.
  • the patterned barrier layer is removed using an alkaline solution containing hydrogen peroxide.
  • forming an isolation trench at the interface between the boron-doped polysilicon layer and the phosphorus-doped polysilicon layer comprises the following steps:
  • Laser grooving is performed on the interface between the boron-doped polysilicon layer and the phosphorus-doped polysilicon layer.
  • the laser grooves are etched with an alkaline solution.
  • the preparation method further includes a step of removing a wrap-around layer on the front side of the n-type silicon substrate.
  • the preparation method further includes the step of forming a third silicon oxide layer in the isolation trench.
  • the preparation method further includes the steps of texturing the front side of the n-type silicon substrate and cleaning the n-type silicon substrate with a mixed solution of hydrofluoric acid and hydrochloric acid.
  • the preparation method further includes the step of forming an aluminum oxide layer on the front and back sides of the n-type silicon substrate.
  • the preparation method further includes the step of forming a passivation anti-reflection layer on the aluminum oxide layer on the front and back sides of the n-type silicon substrate, respectively.
  • the preparation method further includes the step of opening a hole in the passivation anti-reflection layer on the back side of the n-type silicon substrate to form a first electrode contact hole connected to the boron-doped polysilicon layer and a second electrode contact hole connected to the phosphorus-doped polysilicon layer.
  • the first electrode is prepared in the first electrode contact hole by screen printing; and the second electrode is prepared in the second electrode contact hole by screen printing.
  • a solar cell is provided.
  • the solar cell is prepared by the above-mentioned method for preparing a solar cell of the present application.
  • a solar cell comprising:
  • a first silicon oxide layer is provided on the back side of the n-type silicon substrate
  • boron-doped polysilicon layer disposed on the first silicon oxide layer
  • a phosphorus-doped polysilicon layer disposed on the first silicon oxide layer and separated from the boron-doped polysilicon layer by an isolation trench;
  • an aluminum oxide layer disposed on the front surface of the n-type silicon substrate, on the boron-doped polysilicon layer, on the phosphorus-doped polysilicon layer and in the isolation trench;
  • a passivation anti-reflection layer is disposed on the aluminum oxide layer
  • a first electrode passing through the passivation anti-reflection layer and the aluminum oxide layer on the back side of the n-type silicon substrate and connected to the boron-doped polysilicon layer;
  • the second electrode passes through the passivation anti-reflection layer and the aluminum oxide layer on the back side of the n-type silicon substrate and is connected to the phosphorus-doped polysilicon layer.
  • the preparation method of the present application forms a boron-doped polysilicon layer and a phosphorus-doped polysilicon layer in one step on the back of the n-type silicon substrate by removing the phosphorus-silicon glass layer and the second silicon oxide layer in a partial area of the back of the n-type silicon substrate and then performing boron diffusion.
  • the preparation method can simultaneously prepare the boron-doped polysilicon layer and the phosphorus-doped polysilicon layer through only one high-temperature process (boron diffusion), which greatly simplifies the preparation process of solar cells and reduces production costs.
  • FIG1 is a schematic diagram of an n-type silicon substrate
  • FIG2 is a schematic diagram showing a first silicon oxide layer, an intrinsic amorphous silicon layer, a phosphosilicate glass layer, and a second silicon oxide layer formed on the back side of an n-type silicon substrate;
  • FIG3 is a schematic diagram showing a portion of the second silicon oxide layer after a patterned barrier layer is formed
  • FIG4 is a schematic diagram showing the removal of the phosphosilicate glass layer and the second silicon oxide layer in the region where no barrier layer is provided;
  • FIG5 is a schematic diagram after removing the patterned barrier layer
  • FIG6 is a schematic diagram after boron diffusion
  • FIG7 is a schematic diagram of an isolation groove formed by laser grooving
  • FIG8 is a schematic diagram after chain acid polishing treatment
  • FIG9 is a schematic diagram of the process after the texturing and cleaning
  • FIG10 is a schematic diagram showing the formation of aluminum oxide layers on the front and back sides of an n-type silicon substrate
  • FIG11 is a schematic diagram showing a passivation anti-reflection layer formed on the front and back sides of an n-type silicon substrate;
  • FIG12 is a schematic diagram showing a hole formed in the passivation anti-reflection layer on the back side of an n-type silicon substrate;
  • FIG. 13 is a schematic diagram of a solar cell according to an embodiment of the present application.
  • n-type silicon substrate 2. first silicon oxide layer; 3. intrinsic amorphous silicon layer; 4. phosphosilicate glass layer; 5. Second silicon oxide layer; 6. Patterned barrier layer; 7. Boron-doped polysilicon layer; 8. Borosilicate glass; 9. Phosphorus-doped polysilicon layer; 10. Isolation groove; 11. Wrap-around coating; 12. Aluminum oxide layer; 13. Passivation anti-reflection layer; 14. First electrode; 15. Second electrode; 100. Solar cell.
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number or order of the indicated technical features. Therefore, a feature defined as “first” or “second” may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality” is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
  • an embodiment of the present application provides a method for preparing a solar cell 100 , and the method comprises the following steps S1 to S14:
  • Step S1 providing an n-type silicon substrate 1, and performing a damage removal treatment on the n-type silicon substrate 1 using an alkaline solution, and then performing a cleaning treatment.
  • the structure of the n-type silicon substrate 1 is shown in FIG1 .
  • the n-type silicon substrate 1 is dedamaged by using a sodium hydroxide solution to remove the damaged layer on the surface of the n-type silicon substrate 1 after mechanical processing; and then the surface of the n-type silicon substrate 1 is cleaned by washing with water.
  • Step S2 On the back side of the n-type silicon substrate 1 (the lower surface of the n-type silicon substrate 1 in FIG. 1 ), a first silicon oxide layer 2, an intrinsic amorphous silicon layer 3, a phosphosilicate glass layer 4, and a second silicon oxide layer 5 are sequentially formed.
  • the structure after forming the first silicon oxide layer 2, the intrinsic amorphous silicon layer 3, the phosphosilicate glass layer 4, and the second silicon oxide layer 5 is shown in FIG. 2 .
  • LPCVD Low Pressure Chemical Vapor Deposition
  • PECVD Pullasma Enhanced Chemical Vapor Deposition
  • first silicon oxide layer 2 has a thickness of 1 nm to 2 nm
  • the intrinsic amorphous silicon layer 3 has a thickness of 50 nm to 500 nm.
  • APCVD Advanced Pressure Chemical Vapor Deposition
  • PSG phosphosilicate glass layer 4
  • second silicon oxide layer 5 on the intrinsic amorphous silicon layer 3.
  • the thickness of the phosphosilicate glass layer 4 is 30nm to 100nm, and the mass ratio of phosphorus (P) in the phosphosilicate glass layer 4 is less than or equal to 50%; the thickness of the second silicon oxide layer 5 is 30nm to 100nm.
  • Step S3 forming a patterned barrier layer 6 in a partial area on the surface of the second silicon oxide layer 5.
  • the structure after forming the patterned barrier layer 6 is shown in FIG3 .
  • the barrier layer slurry is graphically printed on a partial area of the surface of the second silicon oxide layer 5 according to a preset pattern and then dried to form the above-mentioned graphical barrier layer 6.
  • the barrier layer slurry has the following characteristics: the formed barrier layer can be dissolved in alkali but insoluble in acid.
  • the patterned barrier layer 6 is a wax-like resin material.
  • the printed line spacing of the patterned barrier layer 6 formed after printing is 500 ⁇ m to 2000 ⁇ m.
  • Step S4 using a solution containing HF (hydrofluoric acid) to remove the phosphosilicate glass layer 4 and the second silicon oxide layer 5 in the area where the patterned barrier layer 6 is not formed on the back of the n-type silicon substrate 1.
  • HF hydrofluoric acid
  • a hydrofluoric acid solution is used to remove the phosphosilicate glass layer 4 and the second silicon oxide layer 5 in the region where the patterned barrier layer 6 is not formed, and the first silicon oxide layer 2 is retained.
  • the phosphosilicate glass layer 4 and the second silicon oxide layer 5 on the inner side thereof will not be removed due to the presence of the patterned barrier layer 6.
  • Step S5 removing the patterned barrier layer 6.
  • the structure after removing the patterned barrier layer 6 is shown in FIG5 .
  • a mixed solution of sodium hydroxide and hydrogen peroxide (H 2 O 2 ) is used to remove the patterned barrier layer 6 , and after removing the patterned barrier layer 6 , the n-type silicon substrate 1 is cleaned with a mixed solution of hydrochloric acid (HCl) and H 2 O 2 .
  • the phosphosilicate glass layer 4 and the second silicon oxide layer 5 are retained at corresponding positions of the patterned barrier layer 6 .
  • steps S3, S4 and S5 are to form a stacked structure having a phosphorus silicon glass layer 4 and a second silicon oxide layer 5 in a partial area on the back of the n-type silicon substrate 1, while in other areas on the back of the n-type silicon substrate 1, there are only the first silicon oxide layer 2 and the intrinsic amorphous silicon layer 3.
  • Steps S3 to S5 are achieved by setting a patterned barrier layer 6 as a mask layer. It is understandable that other methods can be used to achieve the above purpose in some other embodiments of the present application, as long as a stacked structure having a phosphorus silicon glass layer 4 and a second silicon oxide layer 5 can be formed in a partial area on the back of the n-type silicon substrate 1.
  • Step S6 Boron diffusion is performed on the back side of the n-type silicon substrate 1. The structure after the boron diffusion is shown in FIG6 .
  • the intrinsic amorphous silicon layer 3 in the area where the phosphorus silicon glass layer 4 and the second silicon oxide layer 5 are removed from the back of the n-type silicon substrate 1 can be converted into boron-doped polycrystalline silicon.
  • the outer layer of the layer 7 will diffuse to form borosilicate glass 8 (BSG); while the intrinsic amorphous silicon layer 3 in the area where the phosphosilicate glass layer 4 and the second silicon oxide layer 5 are not removed on the back of the n-type silicon substrate 1 (i.e., the corresponding area where the patterned barrier layer 6 is set), the phosphorus in the phosphosilicate glass layer 4 is diffused into the intrinsic amorphous silicon layer 3 due to the high temperature, and crystallized and annealed to form a phosphorus-doped polysilicon layer 9. Since the area is blocked by the second silicon oxide layer 5 on the outside, boron will not be doped into the intrinsic amorphous silicon layer 3 in the area.
  • BSG borosilicate glass 8
  • the preparation of the boron-doped polysilicon layer 7 and the phosphorus-doped polysilicon layer 9 can be achieved simultaneously through a one-step high-temperature process (boron diffusion), which greatly simplifies the preparation process of the solar cell 100 and reduces the production cost of the solar cell 100.
  • the region corresponding to the boron-doped polysilicon layer 7 is the p-region, and the region corresponding to the phosphorus-doped polysilicon layer 9 is the n-region.
  • the n-type silicon substrate 1 is placed in a boron diffusion furnace, and a boron source (boron trichloride (BCl 3 ) and/or boron tribromide (BBr 3 )) is used to perform a boron diffusion treatment at a temperature of 900° C. to 1050° C. for 1 h to 3 h, and the volume ratio of the boron source in the boron diffusion atmosphere in the boron diffusion furnace is 5% to 30%.
  • a boron source boron trichloride (BCl 3 ) and/or boron tribromide (BBr 3 )
  • BCl 3 boron trichloride
  • BBr 3 boron tribromide
  • the temperature of the boron diffusion can be but not limited to 900° C., 920° C., 950° C., 980° C., 1000° C., 1020° C., 1050° C., etc.; the time of the boron diffusion can be but not limited to 1 h, 1.5 h, 2 h, 2.5 h, 3 h, etc.; the volume ratio of the boron source in the boron diffusion atmosphere can be but not limited to 5%, 8%, 10%, 12%, 15%, 18%, 20%, 22%, 25%, 28%, 30%, etc.
  • Step S7 Use laser to perform laser grooving on the region at the interface between the boron-doped polysilicon layer 7 and the phosphorus-doped polysilicon layer 9, and then perform etching with an alkaline solution to form an isolation groove 10.
  • the structure after laser grooving to form the isolation groove 10 is shown in FIG7 .
  • a laser is used to perform laser grooving on the boundary area between the boron-doped polysilicon layer 7 and the phosphorus-doped polysilicon layer 9 to remove the polysilicon layer at the grooving location, and then an alkaline solution (such as a sodium hydroxide solution) is used to etch the grooving location to separate the boron-doped polysilicon layer 7 and the phosphorus-doped polysilicon layer 9 so that they are not directly connected to each other.
  • an alkaline solution such as a sodium hydroxide solution
  • Step S8 removing the coating layer 11 on the front side of the n-type silicon substrate 1.
  • a chain acid polishing (HF+HNO 3 ) device is used to remove the silicon oxide layer, phosphosilicate glass, polysilicon layer, borosilicate glass and other coating layers 11 coated on the front side of the n-type silicon substrate 1.
  • the chain acid polishing (HF+HNO 3 ) device can remove the silicon oxide layer, phosphosilicate glass, polysilicon layer and borosilicate glass coated on the front side at one time, thereby avoiding the problem of the coating layer 11 not being completely removed. This causes leakage and appearance problems of the solar cell 100.
  • the phosphosilicate glass layer 4 the second silicon oxide layer 5 and the borosilicate glass 8 on the back of the n-type silicon substrate 1 are also removed.
  • the schematic diagram after the chain acid polishing treatment is shown in FIG8 .
  • APCVD is used to deposit a silicon oxide film in the isolation groove 10, and then the n-type silicon substrate 1 is placed in a chain acid polishing device to remove the winding coating 11.
  • the silicon oxide film can protect the isolation groove 10 area on the back side of the n-type silicon substrate 1 from being textured in the subsequent texture process, maintain the surface morphology, reduce the carrier recombination in this area, and thus improve the overall passivation performance of the back side of the n-type silicon substrate 1.
  • Step S9 texturing and cleaning the front surface of the n-type silicon substrate 1.
  • the structure after texturing and cleaning is shown in FIG9 .
  • the n-type silicon substrate 1 is sent to a tank cleaning machine, and sodium hydroxide is used to texturize the front side of the n-type silicon substrate 1.
  • the back side of the n-type silicon substrate 1 will not be etched by the alkaline solution (texturizing solution) due to the protection of phosphosilicate glass and borosilicate glass.
  • a mixed solution of HF and HCl hydroochloric acid is used for cleaning.
  • Step S10 forming an aluminum oxide layer 12 on the front and back surfaces of the n-type silicon substrate 1.
  • the structure after forming the aluminum oxide layer 12 is shown in FIG.
  • an aluminum oxide layer 12 is formed on the front and back sides of the n-type silicon substrate 1 by ALD (Atomic Layer Deposition).
  • the thickness of the aluminum oxide layer 12 on the front and back sides of the n-type silicon substrate 1 is 3 nm to 10 nm respectively.
  • Step S11 forming a passivation anti-reflection layer 13 on the aluminum oxide layer 12 on the front and back sides of the n-type silicon substrate 1.
  • the structure after forming the passivation anti-reflection layer 13 is shown in FIG.
  • a passivation anti-reflection layer 13 is first deposited on the aluminum oxide layer 12 on the front side of the n-type silicon substrate 1 by PECVD, and the thickness of the passivation anti-reflection layer 13 on the front side is 60nm-100nm; then, a passivation anti-reflection layer 13 is deposited on the aluminum oxide layer 12 on the back side of the n-type silicon substrate 1 by PECVD, and the thickness of the passivation anti-reflection layer 13 on the back side is 80nm-150nm.
  • Step S12 opening a hole in the passivation anti-reflection layer 13 on the back side of the n-type silicon substrate 1.
  • the structure after the hole is opened is shown in FIG.
  • a hole is opened on the passivation anti-reflection layer 13 on the back side of the n-type silicon substrate 1 by using a laser to form a first electrode contact hole connected to the boron-doped polysilicon layer 7 and a second electrode contact hole connected to the phosphorus-doped polysilicon layer 9.
  • electrodes connected to the boron-doped polysilicon layer 7 and the phosphorus-doped polysilicon layer 9 can be prepared in the first electrode contact hole and the second electrode contact hole, respectively.
  • Step S13 preparing the first electrode 14 and the second electrode 15 in the first electrode contact hole and the second electrode contact hole respectively.
  • the structure of the obtained solar cell 100 is shown in FIG13 .
  • a first electrode 14 is prepared in a first electrode contact hole by screen printing, and the first electrode 14 is connected to the boron-doped polysilicon layer 7;
  • a second electrode 15 is prepared in a second electrode contact hole by screen printing, and the second electrode 15 is connected to the phosphorus-doped polysilicon layer 9.
  • Step S14 light injection.
  • Light injection equipment is used to inject light into the prepared solar cell 100 .
  • the preparation method of the solar cell 100 of the present application forms a boron-doped polysilicon layer 7 and a phosphorus-doped polysilicon layer 9 in one step on the back side of the n-type silicon substrate 1 by removing the phosphosilicate glass layer 4 and the second silicon oxide layer 5 in a partial area of the back side of the n-type silicon substrate 1 and then performing boron diffusion.
  • the preparation method can simultaneously prepare the boron-doped polysilicon layer 7 and the phosphorus-doped polysilicon layer 9 through only one high-temperature process (boron diffusion), which greatly simplifies the preparation process of the solar cell 100 and reduces the production cost.
  • the back side of the n-type silicon substrate 1 is patterned, so that the phosphosilicate glass layer 4 and the second silicon oxide layer 5 in a partial area of the back side of the n-type silicon substrate 1 can be easily removed, and the phosphosilicate glass layer 4 and the second silicon oxide layer 5 in a partial area are retained.
  • the preparation method of the solar cell 100 of the present application forms a first silicon oxide layer 2 and a boron-doped polysilicon layer 7 in the p-region on the back side of the n-type silicon substrate 1, and forms a first silicon oxide layer 1 and a phosphorus-doped polysilicon layer 9 in the n-region, which greatly improves the passivation performance of the solar cell 100, thereby facilitating the improvement of the open circuit voltage (Voc) of the solar cell 100.
  • Voc open circuit voltage
  • One embodiment of the present application provides a back-contact solar cell 100, which includes an n-type silicon substrate 1, a first silicon oxide layer 2, a boron-doped polysilicon layer 7, a phosphorus-doped polysilicon layer 9, an aluminum oxide layer 12, a passivation anti-reflection layer 13, a first electrode 14 and a second electrode 15.
  • the first silicon oxide layer 2 is arranged on the back side of the n-type silicon substrate 1; the boron-doped polysilicon layer 7 is arranged on the first silicon oxide layer 2; the phosphorus-doped polysilicon layer 9 is arranged on the first silicon oxide layer 2, and is separated from the boron-doped polysilicon layer 7 by the isolation groove 10; an aluminum oxide layer 12 is arranged on the front side of the n-type silicon substrate 1, on the boron-doped polysilicon layer 7, on the phosphorus-doped polysilicon layer 9 and in the isolation groove 10; a passivation anti-reflection layer 13 is arranged on each aluminum oxide layer 12; a first electrode 14 passes through the passivation anti-reflection layer 13 and the aluminum oxide layer 12 on the back side of the n-type silicon substrate 1, and is connected to the boron-doped polysilicon layer 7; a second electrode 15 passes through the passivation anti-reflection layer 13 and the aluminum oxide layer 12 on
  • the passivation anti-reflection layer 13 is a silicon nitride layer
  • the first electrode 14 and the second electrode 15 are metal gate electrodes.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • a preparation process of an n-type full back electrode solar cell 100 comprises the following steps:
  • a first silicon oxide layer 2 with a thickness of 1 nm and an intrinsic amorphous silicon layer 3 with a thickness of 200 nm are sequentially deposited on the back side of an n-type silicon substrate 1 by using LPCVD;
  • a phosphosilicate glass layer 4 (PSG) and a second silicon oxide layer 5 are sequentially deposited on the intrinsic amorphous silicon layer 3 by APCVD; wherein the thickness of the phosphosilicate glass layer 4 is 50 nm, the mass proportion of phosphorus (P) in the phosphosilicate glass layer 4 is 30%, and the thickness of the second silicon oxide layer 5 is 50 nm;
  • a corrosion-resistant slurry is printed on a partial area of the second silicon oxide layer 5 on the back of the n-type silicon substrate 1, and dried to form a patterned barrier layer 6;
  • the corrosion-resistant slurry is a waxy resin material, and the characteristics of the corrosion-resistant slurry are that it is acid-resistant but not alkali-resistant;
  • the printed line spacing of the patterned barrier layer 6 is 1200 ⁇ m;
  • the phosphosilicate glass layer 4 and the second silicon oxide layer 5 in the region where the patterned barrier layer 6 is not formed are removed by using an HF solution, and then the patterned barrier layer 6 is removed by using a mixed solution of NaOH and H 2 O 2 , and then cleaned by using a mixed solution of HCl and H 2 O 2 ;
  • the n-type silicon substrate 1 is placed in a boron diffusion furnace, and BCl 3 is used as a boron source (in the atmosphere).
  • the boron source accounts for 20% by volume), and the back side of the n-type silicon substrate 1 is diffused with boron at a temperature of 980°C for 2h to form p-type B-doped polysilicon (i.e., boron-doped polysilicon layer 7), and BSG (borosilicate glass) is diffused in the outer layer of the boron-doped polysilicon layer 7; and the area where the phosphosilicate glass layer 4 and the second silicon oxide layer 5 are retained, due to the high temperature, the phosphorus in the phosphosilicate glass layer 4 is pushed into the intrinsic amorphous silicon layer 3 to form n-type P-doped polysilicon (i.e., phosphorus-doped polysilicon layer 9), and in this area, due to the blocking of the outer second silicon oxide layer 5,
  • a laser is used to ablate the interface between the p-region (i.e., the region having the boron-doped polysilicon layer 7) and the n-region (i.e., the region having the phosphorus-doped polysilicon layer 9), and then the interface is etched in a NaOH solution to form an isolation groove 10 separating the boron-doped polysilicon layer 7 from the phosphorus-doped polysilicon layer 9;
  • a chain acid polishing (HF+HNO 3 ) device is used to remove silicon oxide, phosphosilicate glass, polysilicon and borosilicate glass coated on the front side of the n-type silicon substrate 1, and then the n-type silicon substrate 1 is texturized on the front side using NaOH in a tank cleaning machine, while the back side will not be etched by alkali due to the protection of the phosphosilicate glass layer 4 and the borosilicate glass layer, and finally cleaned with a mixed solution of HF and HCl;
  • An aluminum oxide layer 12 (AlOx) is prepared on the front and back sides of the n-type silicon substrate 1 by ALD, and the thickness of the aluminum oxide layer 12 is 5 nm;
  • a silicon nitride (SiNx) passivation anti-reflection layer 13 is prepared on the front and back sides of the n-type silicon substrate 1 by using a tubular PECVD method; wherein the thickness of the passivation anti-reflection layer 13 on the front side of the n-type silicon substrate 1 is 75 nm, and the thickness of the passivation anti-reflection layer 13 on the back side of the n-type silicon substrate 1 is 100 nm;
  • a hole is opened on the passivation anti-reflection layer 13 on the back side of the n-type silicon substrate 1 by using a laser to form a first electrode contact hole connected to the boron-doped polysilicon layer 7 and a second electrode contact hole connected to the phosphorus-doped polysilicon layer 9 respectively;
  • a first electrode 14 is formed at the first electrode contact hole, and a second electrode 15 is formed at the second electrode contact hole by screen printing; the first electrode 14 is connected to the boron-doped polysilicon layer 7, and the second electrode 15 is connected to the phosphorus-doped polysilicon layer 9;
  • Light is injected into the prepared solar cell 100 to obtain an n-type full back electrode solar cell 100 .
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the preparation method of the solar cell 100 of this embodiment is basically the same as that of the embodiment 1, except that In this embodiment, a first silicon oxide layer 2 and an intrinsic amorphous silicon layer 3 are sequentially formed on the back side of an n-type silicon substrate 1 by PECVD.
  • the coating layer 11 on the front side of the n-type silicon substrate 1 is less and easier to remove, which is beneficial to improving the appearance and yield of the solar cell 100.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • the preparation method of the solar cell 100 of this embodiment is basically the same as that of Example 1, with the only difference being that in this embodiment, the mass proportion of phosphorus (P) in the phosphosilicate glass layer 4 deposited on the intrinsic amorphous silicon layer 3 by APCVD is reduced from 30% in Example 1 to 20% in this embodiment.
  • the doping concentration of the n-region of the solar cell 100 prepared in this embodiment is reduced, the concentration of phosphorus in the phosphorus-doped polysilicon layer 9 is reduced, and the carrier recombination in the n-region is reduced, thereby improving the passivation performance of the n-region.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • the preparation method of the solar cell 100 of this embodiment is basically the same as that of Example 1, with the only difference being that in this embodiment, after forming the isolation trench 10, an APCVD method is used to deposit a third silicon oxide layer in the isolation trench 10, and the thickness of the third silicon oxide layer is 50nm to 200nm; and then the chain acid polishing, winding plating and texturing are performed in step 8.
  • the preparation method of this embodiment by depositing a third silicon oxide layer in the isolation groove 10, can protect the laser grooved area on the back side of the n-type silicon substrate 1 from being textured, maintain the morphology of the polished surface on the back side of the n-type silicon substrate, reduce the carrier recombination in this area, and thus improve the overall passivation performance of the back side of the n-type silicon substrate 1.

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Abstract

本申请提供了一种太阳电池的制备方法，包括如下步骤：在n型硅衬底的背面依次形成第一氧化硅层、本征非晶硅层、磷硅玻璃层和第二氧化硅层；去除n型硅衬底背面部分区域的磷硅玻璃层和第二氧化硅层；对n型硅衬底背面进行硼扩散，以使去除磷硅玻璃层和第二氧化硅层区域内的本征非晶硅层转化为硼掺杂多晶硅层，并使未去除磷硅玻璃层和第二氧化硅层区域内的本征非晶硅层转化为磷掺杂多晶硅层；在硼掺杂多晶硅层和磷掺杂多晶硅层的交界处形成隔离槽；制备与硼掺杂多晶硅层连接的第一电极和与磷掺杂多晶硅层连接的第二电极。该制备方法工艺简单、生产成本较低。并涉及相应的太阳电池。

Description

太阳电池及其制备方法
本申请要求于2022年11月24日提交中国专利局、申请号为2022114796707、发明名称为“太阳电池及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及太阳电池生产技术领域，特别是涉及一种太阳电池及其制备方法。
背景技术
N型单晶IBC(Interdigitated back contact，指交叉背接触)太阳电池通常是采用扩散工艺在硅片背面形成重掺杂的发射极和背场区域，其能够有效地解决金属栅线对光的遮挡，能够大幅度地提高短路电流密度。
N型单晶IBC太阳电池相对于传统晶硅太阳电池，在实际户外光伏电站和系统应用中，具有以下优势：1、光电转化效率高；2、无光致衰减(LID)，具有较高的稳定性；3、良好的弱光响应和较低的温度系数；4、组件美观，正面无栅线遮挡，较传统组件外观漂亮，可以广泛应用于光伏建筑一体化；5、使用寿命较长。
然而，N型单晶IBC太阳电池的制造工艺较为复杂、技术门槛高、制造成本高，是制约N型单晶IBC太阳电池实现量产化的重要因素。因此，如何简化N型单晶IBC太阳电池的制备工艺、降低制造成本是本来领域研究的一个重要方向。
发明内容
基于此，有必要提供一种制备工艺较为简单、生产成本较低的太阳电池及其制备方法。
根据本申请的一个方面，提供了一种太阳电池的制备方法，包括如下步骤：
在n型硅衬底的背面依次形成第一氧化硅层、本征非晶硅层、磷硅玻 璃层和第二氧化硅层；
去除所述n型硅衬底背面部分区域的所述磷硅玻璃层和所述第二氧化硅层；
对所述n型硅衬底背面进行硼扩散，以使去除所述磷硅玻璃层和第二氧化硅层区域内的所述本征非晶硅层转化为硼掺杂多晶硅层，使未去除所述磷硅玻璃层和第二氧化硅层区域内的所述本征非晶硅层转化为磷掺杂多晶硅层；
在所述硼掺杂多晶硅层和所述磷掺杂多晶硅层的交界处形成隔离槽；
制备与所述硼掺杂多晶硅层连接的第一电极和与所述磷掺杂多晶硅层连接的第二电极。
在任意的实施方式中，对所述n型硅衬底背面进行硼扩散，包括如下步骤：
在900℃～1050℃温度下，利用硼源对所述n型硅衬底的背面进行扩散处理1h～3h。
在任意的实施方式中，所述硼源为BCl3或BBr3中的一种或多种。
在任意的实施方式中，所述硼扩散的气氛中所述硼源的体积占比为5％～30％。
在任意的实施方式中，去除所述n型硅衬底背面部分区域的所述磷硅玻璃层和所述第二氧化硅层，包括如下步骤：
在所述第二氧化硅层表面的部分区域内形成图形化阻挡层；
用含有HF的溶液去除所述n型硅衬底背面未形成所述图形化阻挡层区域内的所述磷硅玻璃层和所述第二氧化硅层；
去除所述图形化阻挡层。
在任意的实施方式中，所述图形化阻挡层为蜡状树脂材料。
在任意的实施方式中，利用含有双氧水的碱溶液去除所述图形化阻挡层。
在任意的实施方式中，在所述硼掺杂多晶硅层和所述磷掺杂多晶硅层的交界处形成隔离槽，包括如下步骤：
对所述硼掺杂多晶硅层和所述磷掺杂多晶硅层的交界处进行激光开槽， 并用碱溶液对所述激光开槽处进行刻蚀。
在任意的实施方式中，在形成所述隔离槽之后，且在制备所述第一电极和所述第二电极之前，所述制备方法还包括去除所述n型硅衬底正面的绕镀层的步骤。
在任意的实施方式中，在形成所述隔离槽之后，且在去除所述n型硅衬底正面的绕镀层之前，所述制备方法还包括在所述隔离槽内形成第三氧化硅层的步骤。
在任意的实施方式中，在去除所述n型硅衬底正面的绕镀层之后，且在制备所述第一电极和所述第二电极之前，所述制备方法还包括对所述n型硅衬底的正面进行制绒处理以及用氢氟酸和盐酸混合溶液对所述n型硅衬底进行清洗的步骤。
在任意的实施方式中，在对所述n型硅衬底进行清洗之后，且在制备所述第一电极和所述第二电极之前，所述制备方法还包括在所述n型硅衬底正面和背面形成氧化铝层的步骤。
在任意的实施方式中，在形成所述氧化铝层之后，且在制备所述第一电极和所述第二电极之前，所述制备方法还包括在所述n型硅衬底正面和背面的所述氧化铝层上分别形成钝化减反射层的步骤。
在任意的实施方式中，在形成所述钝化减反射层之后，且在制备所述第一电极和所述第二电极之前，所述制备方法还包括在所述n型硅衬底背面的所述钝化减反射层上开孔，形成与所述硼掺杂多晶硅层连通的第一电极接触孔和与所述磷掺杂多晶硅层连通的第二电极接触孔的步骤。
在任意的实施方式中，通过丝网印刷在所述第一电极接触孔内制备所述第一电极；通过丝网印刷在所述第二电极接触孔内制备所述第二电极。
根据本申请的另一方面，提供了一种太阳电池，所述太阳电池通过本申请上述的太阳电池的制备方法制备得到。
根据本申请的另一方面，提供了一种太阳电池，所述太阳电池包括：
n型硅衬底；
第一氧化硅层，设于所述n型硅衬底的背面；
硼掺杂多晶硅层，设于所述第一氧化硅层上；
磷掺杂多晶硅层，设于所述第一氧化硅层上，且与所述硼掺杂多晶硅层通过隔离槽隔开；
氧化铝层，设于所述n型硅衬底的正面、所述硼掺杂多晶硅层上、所述磷掺杂多晶硅层上及所述隔离槽内；
钝化减反射层，设于所述氧化铝层上；
第一电极，穿过所述n型硅衬底背面的所述钝化减反射层和所述氧化铝层与所述硼掺杂多晶硅层相连接；
第二电极，穿过所述n型硅衬底背面的所述钝化减反射层和所述氧化铝层与所述磷掺杂多晶硅层相连接。
本申请的制备方法通过去除n型硅衬底背面部分区域的磷硅玻璃层和第二氧化硅层，然后进行硼扩散在n型硅衬底的背面一步形成硼掺杂多晶硅层和磷掺杂多晶硅层。该制备方法只需通过一步高温工序(硼扩散)即可同时实现硼掺杂多晶硅层和磷掺杂多晶硅层的制备，大大简化了太阳电池的制备工艺流程，降低了生产成本。
附图说明
为了更好地描述和说明本申请的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的申请、目前描述的实施例和/或示例以及目前理解的这些申请的最佳模式中的任何一者的范围的限制。
图1为n型硅衬底的示意图；
图2为在n型硅衬底背面形成第一氧化硅层、本征非晶硅层、磷硅玻璃层和第二氧化硅层后的示意图；
图3为在第二氧化硅层的部分区域形成图形化阻挡层后的示意图；
图4为去除未设置阻挡层区域的磷硅玻璃层和第二氧化硅层后的示意图；
图5为去除图形化阻挡层后的示意图；
图6为进行硼扩散后的示意图；
图7为激光开槽形成隔离槽后的示意图；
图8为链式酸抛光处理后的示意图；
图9为制绒并清洗后的示意图；
图10为在n型硅衬底正面和背面形成氧化铝层后的示意图；
图11为在n型硅衬底正面和背面形成钝化减反射层后的示意图；
图12为在n型硅衬底背面的钝化减反射层上开孔后的示意图；
图13为本申请一实施例的太阳电池的示意图。
附图标记说明：
1、n型硅衬底；2、第一氧化硅层；3、本征非晶硅层；4、磷硅玻璃层；
5、第二氧化硅层；6、图形化阻挡层；7、硼掺杂多晶硅层；8、硼硅玻璃；9、磷掺杂多晶硅层；10、隔离槽；11、绕镀层；12、氧化铝层；13、钝化减反射层；14、第一电极；15、第二电极；100、太阳电池。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。应该理解，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量或顺序。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
在描述位置关系时，除非另有规定，否则当一元件例如层、膜或基板被指为在另一膜层“上”时，其能直接在其他膜层上或亦可存在中间膜层。进一步说，当层被指为在另一层“下”时，其可直接在下方，亦可存在一或多个中间层。亦可以理解的是，当层被指为在两层“之间”时，其可为两层之间的唯一层，或亦可存在一或多个中间层。
除非相反地提及，否则单数形式的术语可以包括复数形式，并不能理解为其数量为一个。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
请参阅图1至图13，本申请一实施方式提供了一种太阳电池100的制备方法，该制备方法包括如下步骤S1至步骤S14：
步骤S1：提供n型硅衬底1，并采用碱性溶液对n型硅衬底1进行去损伤处理，然后进行清洗处理。n型硅衬底1的结构如图1所示。
在其中一些实施例中，采用氢氧化钠溶液对n型硅衬底1进行去损伤处理，以去除n型硅衬底1经机械加工后表面的损伤层；然后水洗使n型硅衬底1表面洁净。
步骤S2：在n型硅衬底1的背面(图1中n型硅衬底1的下表面)依次形成第一氧化硅层2、本征非晶硅层3、磷硅玻璃层4和第二氧化硅层5。形成第一氧化硅层2、本征非晶硅层3、磷硅玻璃层4和第二氧化硅层5后的结构如图2所示。
在其中一些实施例中，采用LPCVD(Low Pressure Chemical Vapor Deposition，低压化学气相沉积)或者PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积)的方式，先在n型硅衬底1的背面沉积形成第一氧化硅层2，然后在第一氧化硅层2上沉积形成本征非晶硅层3。其中，第一氧化硅层2的厚度为1nm～2nm，本征非晶硅层3的厚度为50nm～500nm。
在其中一些实施例中，采用APCVD(Atmospheric Pressure Chemical Vapor Deposition常压化学气相沉积)方式依次在本征非晶硅层3上沉积形成磷硅玻璃层4(PSG)和第二氧化硅层5。其中，磷硅玻璃层4的厚度为30nm～100nm，磷硅玻璃层4中磷(P)的质量比小于或等于50％；第二氧化硅层5的厚度为30nm～100nm。
步骤S3：在第二氧化硅层5表面的部分区域内形成图形化阻挡层6。形成图形化阻挡层6后的结构如图3所示。
在其中一些实施例中，将阻挡层浆料按照预设图案图形化印刷在第二氧化硅层5表面的部分区域内，烘干，形成上述的图形化阻挡层6。其中， 该阻挡层浆料具有如下特点：所形成的阻挡层能够溶于碱，但不溶于酸。
在其中一些实施例中，图形化阻挡层6为一种蜡状树脂材料。
在其中一些实施例中，印刷后形成的图形化阻挡层6的印刷线条间距为500μm～2000μm。
步骤S4：用含有HF(氢氟酸)的溶液去除n型硅衬底1背面未形成图形化阻挡层6区域内的磷硅玻璃层4和第二氧化硅层5。去除未设置阻挡层区域的磷硅玻璃层4和第二氧化硅层5后的结构如图4所示。
在其中一些实施例中，采用氢氟酸溶液去除未形成图形化阻挡层6区域内的磷硅玻璃层4和第二氧化硅层5，保留第一氧化硅层2。n型硅衬底1背面设置有图形化阻挡层6的区域，由于图形化阻挡层6的存在其内侧的磷硅玻璃层4和第二氧化硅层5不会被去除。
步骤S5：去除图形化阻挡层6。去除图形化阻挡层6后的结构如图5所示。
在其中一些实施例中，采用氢氧化钠和双氧水(H2O2)的混合溶液去除上述的图形化阻挡层6，并在去除图形化阻挡层6之后用盐酸(HCl)和H2O2的混合溶液对n型硅衬底1进行清洗。
可以理解，在去除该图形化阻挡层6之后，在该图形化阻挡层6的对应位置保留磷硅玻璃层4和第二氧化硅层5。
需要说明的是，上述步骤S3、步骤S4和步骤S5的目的是在n型硅衬底1背面的部分区域内形成具有磷硅玻璃层4和第二氧化硅层5的叠层结构，而在n型硅衬底1背面的其他区域内则只有第一氧化硅层2和本征非晶硅层3。步骤S3至步骤S5是通过设置图形化阻挡层6作为掩膜层，来实现上述目的的。可以理解，本申请的其他一些实施例中还可以采用其他的方式来实现上述目的，只要能够在n型硅衬底1背面的部分区域内形成具有磷硅玻璃层4和第二氧化硅层5的叠层结构即可。
步骤S6：对n型硅衬底1背面进行硼扩散。硼扩散后的结构如图6所示。
在硼扩散的高温处理过程中，可以使n型硅衬底1背面去除了磷硅玻璃层4和第二氧化硅层5的区域内的本征非晶硅层3转化为硼掺杂多晶硅 层7，其外层会扩散生成硼硅玻璃8(BSG)；而n型硅衬底1背面未去除磷硅玻璃层4和第二氧化硅层5的区域内(即设置图形化阻挡层6的对应区域)的本征非晶硅层3，则由于高温作用将磷硅玻璃层4中的磷扩散进入本征非晶硅层3，并晶化退火形成磷掺杂多晶硅层9，该区域由于外侧有第二氧化硅层5的阻挡，硼不会被掺入该区域内的到本征非晶硅层3中。如此，可以通过一步高温工序(硼扩散)同时实现硼掺杂多晶硅层7和磷掺杂多晶硅层9的制备，大大简化了太阳电池100的制备工艺流程，降低了太阳电池100的生产成本。
其中，硼掺杂多晶硅层7对应的区域为p区，磷掺杂多晶硅层9对应的区域为n区。
在其中一些实施例中，将n型硅衬底1置于硼扩散炉中，利用硼源(三氯化硼(BCl3)和/或三溴化硼(BBr3))在900℃～1050℃温度下进行硼扩散处理1h～3h，硼扩散炉内硼扩散气氛中硼源的体积占比为5％～30％。可以理解，硼扩散的温度可以为但不限于900℃、920℃、950℃、980℃、1000℃、1020℃、1050℃等；硼扩散的时间可以为但不限于1h、1.5h、2h、2.5h、3h等；硼扩散气氛中硼源的体积比可以为但不限于5％、8％、10％、12％、15％、18％、20％、22％、25％、28％、30％等。
步骤S7：使用激光对硼掺杂多晶硅层7和磷掺杂多晶硅层9的交界处的区域进行激光开槽，然后用碱溶液进行刻蚀处理，形成隔离槽10。激光开槽形成隔离槽10后的结构如图7所示。
在其中一些实施例中，利用激光对硼掺杂多晶硅层7和磷掺杂多晶硅层9的交界处的区域进行激光开槽，去除开槽位置处的多晶硅层，然后利用碱溶液(如氢氧化钠溶液)对开槽位置进行刻蚀处理，使硼掺杂多晶硅层7和磷掺杂多晶硅层9间隔开来，彼此不直接相连。
步骤S8：去除n型硅衬底1正面的绕镀层11。
在其中一些实施例中，采用链式酸抛(HF+HNO3)设备去除n型硅衬底1正面绕镀的氧化硅层、磷硅玻璃、多晶硅层以及硼硅玻璃等绕镀层11。使用链式酸抛(HF+HNO3)设备，可以将正面绕镀的氧化硅层、磷硅玻璃、多晶硅层以及硼硅玻璃一次性全部去除，避免了因绕镀层11未去除完全而 导致太阳电池100漏电和外观问题。在去除正面绕镀层11的同时，也会将n型硅衬底1背面的磷硅玻璃层4、第二氧化硅层5和硼硅玻璃8去除。链式酸抛光处理后的示意图如图8所示。
在其中一些实施例中，在去除n型硅衬底1正面的绕镀层11之前，还使用APCVD在隔离槽10内沉积形成一层氧化硅薄膜，再将n型硅衬底1进入链式酸抛设备进行去绕镀层11处理。如此，通过该氧化硅薄膜可以保护n型硅衬底1背面隔离槽10区域不会在后续的制绒工序中被制绒，保持表面形貌，减少该区域的载流子复合，进而提升n型硅衬底1背面的整体钝化性能。
步骤S9：对n型硅衬底1的正面进行制绒处理并清洗。制绒并清洗后的结构如图9所示。
在其中一些实施例中，将n型硅衬底1送入槽式清洗机中，使用氢氧化钠对n型硅衬底1进行正面制绒，n型硅衬底1的背面则由于有磷硅玻璃、硼硅玻璃的保护而不会被碱溶液(制绒药液)刻蚀。制绒完成后使用HF和HCl(盐酸)混合溶液进行清洗。
步骤S10：在n型硅衬底1正面和背面形成氧化铝层12。形成氧化铝层12后的结构如图10所示。
在其中一些实施例中，采用ALD(Atomic Layer Deposition，原子层沉积)的方式在n型硅衬底1正面和背面分别制备形成氧化铝层12。其中，n型硅衬底1正面和背面的氧化铝层12的厚度分别独立的为3nm～10nm。
步骤S11：在n型硅衬底1正面和背面的氧化铝层12上形成钝化减反射层13。形成钝化减反射层13后的结构如图11所示。
在其中一些实施例中，采用PECVD的方式先在n型硅衬底1正面的氧化铝层12上沉积形成钝化减反射层13，正面的钝化减反射层13的厚度为60nm～100nm；然后采用PECVD的方式在n型硅衬底1背面的氧化铝层12上沉积形成钝化减反射层13，背面的钝化减反射层13的厚度为80nm～150nm。
步骤S12：在n型硅衬底1背面的钝化减反射层13上开孔。开孔后的结构如图12所示。
在其中一些实施例中，利用激光在n型硅衬底1背面的钝化减反射层13上开孔，分别形成与硼掺杂多晶硅层7连通的第一电极接触孔和与磷掺杂多晶硅层9连通的第二电极接触孔。如此，可在该第一电极接触孔和第二电极接触孔内分别制备与硼掺杂多晶硅层7和磷掺杂多晶硅层9连接的电极。
步骤S13：在第一电极接触孔和第二电极接触孔内分别制备第一电极14和第二电极15。所得太阳电池100的结构如图13所示。
在其中一些实施例中，通过丝网印刷在第一电极接触孔内制备第一电极14，该第一电极14与硼掺杂多晶硅层7相连接；通过丝网印刷在第二电极接触孔内制备第二电极15，该第二电极15与磷掺杂多晶硅层9相连接。
步骤S14：光注入。
利用光注入设备对上述制备好的太阳电池100进行光注入。
总体而言，本申请的太阳电池100的制备方法通过去除n型硅衬底1背面部分区域的磷硅玻璃层4和第二氧化硅层5，然后进行硼扩散在n型硅衬底1的背面一步形成硼掺杂多晶硅层7和磷掺杂多晶硅层9。该制备方法只需通过一步高温工序(硼扩散)即可同时实现硼掺杂多晶硅层7和磷掺杂多晶硅层9的制备，大大简化了太阳电池100的制备工艺流程，降低了生产成本。
此外，通过在第二氧化硅层5表面的部分区域内形成图形化阻挡层6的方式进行n型硅衬底1背面图形化设计，能够方便地去除n型硅衬底1背面部分区域的磷硅玻璃层4和第二氧化硅层5，并保留部分区域的磷硅玻璃层4和第二氧化硅层5。本申请的太阳电池100的制备方法在n型硅衬底1背面的p区形成第一氧化硅层2和硼掺杂多晶硅层7，n区均形成第一氧化硅层1和磷掺杂多晶硅层9，大大提升了太阳电池100的钝化性能，从而有利于提高太阳电池100的开路电压(Voc)。
请参阅图13，本申请一实施方式提供一种背接触太阳电池100，该太阳电池100包括n型硅衬底1、第一氧化硅层2、硼掺杂多晶硅层7、磷掺杂多晶硅层9、氧化铝层12、钝化减反射层13、第一电极14和第二电极15。
其中，第一氧化硅层2设置在n型硅衬底1的背面；硼掺杂多晶硅层7设置在第一氧化硅层2上；磷掺杂多晶硅层9设置在第一氧化硅层2上，且与硼掺杂多晶硅层7通过隔离槽10隔开；在n型硅衬底1的正面、硼掺杂多晶硅层7上、磷掺杂多晶硅层9上以及隔离槽10内均设置有氧化铝层12；钝化减反射层13设于各氧化铝层12之上；第一电极14穿过n型硅衬底1背面的钝化减反射层13和氧化铝层12，且与硼掺杂多晶硅层7相连接；第二电极15穿过n型硅衬底1背面的钝化减反射层13和氧化铝层12，且与磷掺杂多晶硅层9相连接。
在其中一些实施例中，钝化减反射层13为氮化硅层，第一电极14和第二电极15为金属栅线电极。
下面将结合具体实施例和对比例对本申请作进一步说明，但不应将其理解为对本申请保护范围的限制。
实施例1：
一种n型全背电极太阳电池100的制备工艺，包括如下步骤：
提供n型硅衬底1，采用氢氧化钠(NaOH)碱性溶液对n型硅衬底1进行去损伤处理和清洗；
采用LPCVD的方式在n型硅衬底1的背面依次沉积形成厚度为1nm的第一氧化硅层2和厚度为200nm的本征非晶硅层3；
使用APCVD的方式在本征非晶硅层3上依次沉积形成一层磷硅玻璃层4(PSG)和第二氧化硅层5；其中，磷硅玻璃层4的厚度为50nm，磷硅玻璃层4中磷(P)的质量占比为30％，第二氧化硅层5的厚度为50nm；
在n型硅衬底1背面第二氧化硅层5的部分区域内印刷耐腐蚀性浆料，并烘干，形成图形化阻挡层6；该耐腐蚀性浆料为一种蜡状树脂材料，该耐腐蚀性浆料的特点是耐酸不耐碱；图形化阻挡层6的印刷线条间距为1200μm；
用HF溶液去除未形成图形化阻挡层6区域内的磷硅玻璃层4和第二氧化硅层5，随后用NaOH和H2O2的混合溶液去除图形化阻挡层6，并用HCl和H2O2的混合溶液进行清洗；
将上述的n型硅衬底1置于硼扩散炉中，利用BCl3作为硼源(气氛中 硼源体积占比20％)，在980℃温度下对n型硅衬底1的背面进行硼扩散2h，形成p型掺B多晶硅(即硼掺杂多晶硅层7)，在硼掺杂多晶硅层7的外层则扩散生成BSG(硼硅玻璃)；而保留有磷硅玻璃层4和第二氧化硅层5的区域则由于高温作用将磷硅玻璃层4中的磷推进本征非晶硅层3中形成n型掺P多晶硅(即磷掺杂多晶硅层9)，该区域中由于外层第二氧化硅层5的阻挡，硼不会被掺入本征非晶硅层3中；
使用激光对p区(即具有硼掺杂多晶硅层7的区域)和n区(即具有磷掺杂多晶硅层9的区域)交界处进行激光烧灼，然后转入用NaOH溶液中进行刻蚀，形成将硼掺杂多晶硅层7和磷掺杂多晶硅层9分隔开来的隔离槽10；
采用链式酸抛(HF+HNO3)设备去除n型硅衬底1正面绕镀的氧化硅、磷硅玻璃、多晶硅和硼硅玻璃，随后进入槽式清洗机使用NaOH对n型硅衬底1进行正面制绒，背面则由于磷硅玻璃层4和硼硅玻璃层的保护作用而不会被碱刻蚀，最后再利用HF和HCl混合溶液清洗；
使用ALD的方式在n型硅衬底1的正面和背面分别制备氧化铝层12(AlOx)，氧化铝层12的厚度为5nm；
使用管式PECVD的方式在n型硅衬底1的正面和背面分别制备氮化硅(SiNx)钝化减反射层13；其中，n型硅衬底1的正面的钝化减反射层13的厚度为75nm，n型硅衬底1的背面的钝化减反射层13的厚度为100nm；
利用激光在n型硅衬底1背面的钝化减反射层13上开孔，分别形成与硼掺杂多晶硅层7连通的第一电极接触孔和与磷掺杂多晶硅层9连通的第二电极接触孔；
通过丝网印刷在第一电极接触孔处形成第一电极14，在第二电极接触孔处形成第二电极15；第一电极14与硼掺杂多晶硅层7相连接，第二电极15与磷掺杂多晶硅层9相连接；
对制备的太阳电池100进行光注入，即得到n型全背电极太阳电池100。
实施例2：
本实施例的太阳电池100的制备方法与实施例1基本相同，区别仅在 于：本实施例采用PECVD方式在n型硅衬底1的背面依次形成第一氧化硅层2和本征非晶硅层3。采用上述的制备方法，n型硅衬底1正面的绕镀层11更少，也更容易去除，有利于提高太阳电池100的外观和良率。
实施例3：
本实施例的太阳电池100的制备方法与实施例1基本相同，区别仅在于：本实施例中使用APCVD方式在本征非晶硅层3上沉积形成的磷硅玻璃层4中磷(P)的质量占比由实施例1的30％，降低为本实施例的20％。
即，本实施例制备的太阳电池100的n区的掺杂浓度降低，磷掺杂多晶硅层9中磷的浓度降低，降低了n区的载流子复合，从而可以提高n区的钝化性能。
实施例4：
本实施例的太阳电池100的制备方法与实施例1基本相同，区别仅在于：本实施例中，在形成隔离槽10之后，使用APCVD方法在隔离槽10中沉积形成一层第三氧化硅层，该第三氧化硅层的厚度为50nm～200nm；然后再进行第8步的链式酸抛去绕镀和制绒。
本实施例的制备方法，通过在隔离槽10中沉积形成一层第三氧化硅层，可以保护n型硅衬底1背面的激光开槽区域不被制绒，保持n型硅衬底背面抛光面的形貌，减少该区域的载流子复合，从而提升n型硅衬底1背面的整体钝化性能。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请发明构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请的保护范围应以所附权利要求为准。

Claims (17)

  1. 一种太阳电池的制备方法，其特征在于，包括如下步骤：
    在n型硅衬底的背面依次形成第一氧化硅层、本征非晶硅层、磷硅玻璃层和第二氧化硅层；
    去除所述n型硅衬底背面部分区域的所述磷硅玻璃层和所述第二氧化硅层；
    对所述n型硅衬底背面进行硼扩散，以使去除所述磷硅玻璃层和第二氧化硅层区域内的所述本征非晶硅层转化为硼掺杂多晶硅层，并使未去除所述磷硅玻璃层和第二氧化硅层区域内的所述本征非晶硅层转化为磷掺杂多晶硅层；
    在所述硼掺杂多晶硅层和所述磷掺杂多晶硅层的交界处形成隔离槽；
    制备与所述硼掺杂多晶硅层连接的第一电极和与所述磷掺杂多晶硅层连接的第二电极。
  2. 根据权利要求1所述的太阳电池的制备方法，其特征在于，对所述n型硅衬底背面进行硼扩散，包括如下步骤：
    在900℃～1050℃温度下，利用硼源对所述n型硅衬底的背面进行扩散处理1h～3h。
  3. 根据权利要求2所述的太阳电池的制备方法，其特征在于，所述硼源为BCl3或BBr3中的一种或多种。
  4. 根据权利要求2或3所述的太阳电池的制备方法，其特征在于，所述硼扩散的气氛中所述硼源的体积占比为5％～30％。
  5. 根据权利要求1至4中任一项所述的太阳电池的制备方法，其特征在于，去除所述n型硅衬底背面部分区域的所述磷硅玻璃层和所述第二氧化硅层，包括如下步骤：
    在所述第二氧化硅层表面的部分区域内形成图形化阻挡层；
    用含有HF的溶液去除所述n型硅衬底背面未形成所述图形化阻挡层区域内的所述磷硅玻璃层和所述第二氧化硅层；
    去除所述图形化阻挡层。
  6. 根据权利要求5所述的太阳电池的制备方法，其特征在于，所述图形化阻挡层为蜡状树脂材料。
  7. 根据权利要求5或6所述的太阳电池的制备方法，其特征在于，利用含有双氧水的碱溶液去除所述图形化阻挡层。
  8. 根据权利要求5至7中任一项所述的太阳电池的制备方法，其特征在于，在所述硼掺杂多晶硅层和所述磷掺杂多晶硅层的交界处形成隔离槽，包括如下步骤：
    对所述硼掺杂多晶硅层和所述磷掺杂多晶硅层的交界处进行激光开槽，并用碱溶液对所述激光开槽处进行刻蚀。
  9. 根据权利要求1至8中任一项所述的太阳电池的制备方法，其特征在于，在形成所述隔离槽之后，且在制备所述第一电极和所述第二电极之前，所述制备方法还包括去除所述n型硅衬底正面的绕镀层的步骤。
  10. 根据权利要求9所述的太阳电池的制备方法，其特征在于，在形成所述隔离槽之后，且在去除所述n型硅衬底正面的绕镀层之前，所述制备方法还包括在所述隔离槽内形成第三氧化硅层的步骤。
  11. 根据权利要求9或10所述的太阳电池的制备方法，其特征在于，在去除所述n型硅衬底正面的绕镀层之后，且在制备所述第一电极和所述第二电极之前，所述制备方法还包括对所述n型硅衬底的正面进行制绒处理以及用氢氟酸和盐酸混合溶液对所述n型硅衬底进行清洗的步骤。
  12. 根据权利要求11所述的太阳电池的制备方法，其特征在于，在对所述n型硅衬底进行清洗之后，且在制备所述第一电极和所述第二电极之前，所述制备方法还包括在所述n型硅衬底正面和背面形成氧化铝层的步骤。
  13. 根据权利要求12所述的太阳电池的制备方法，其特征在于，在形成所述氧化铝层之后，且在制备所述第一电极和所述第二电极之前，所述制备方法还包括在所述n型硅衬底正面和背面的所述氧化铝层上分别形成钝化减反射层的步骤。
  14. 根据权利要求13所述的太阳电池的制备方法，其特征在于，在形成所述钝化减反射层之后，且在制备所述第一电极和所述第二电极之前，所述制备方法还包括在所述n型硅衬底背面的所述钝化减反射层上开孔，形成 与所述硼掺杂多晶硅层连通的第一电极接触孔和与所述磷掺杂多晶硅层连通的第二电极接触孔的步骤。
  15. 根据权利要求14所述的太阳电池的制备方法，其特征在于，通过丝网印刷在所述第一电极接触孔内制备所述第一电极；通过丝网印刷在所述第二电极接触孔内制备所述第二电极。
  16. 一种太阳电池，其特征在于，所述太阳电池通过权利要求1至15中任一项所述的太阳电池的制备方法制备得到。
  17. 一种太阳电池，其特征在于，包括：
    n型硅衬底；
    第一氧化硅层，设于所述n型硅衬底的背面；
    硼掺杂多晶硅层，设于所述第一氧化硅层上；
    磷掺杂多晶硅层，设于所述第一氧化硅层上，且与所述硼掺杂多晶硅层通过隔离槽隔开；
    氧化铝层，设于所述n型硅衬底的正面、所述硼掺杂多晶硅层上、所述磷掺杂多晶硅层上及所述隔离槽内；
    钝化减反射层，设于所述氧化铝层上；
    第一电极，穿过所述n型硅衬底背面的所述钝化减反射层和所述氧化铝层与所述硼掺杂多晶硅层相连接；
    第二电极，穿过所述n型硅衬底背面的所述钝化减反射层和所述氧化铝层与所述磷掺杂多晶硅层相连接。
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