WO2024113531A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2024113531A1
WO2024113531A1 PCT/CN2023/080321 CN2023080321W WO2024113531A1 WO 2024113531 A1 WO2024113531 A1 WO 2024113531A1 CN 2023080321 W CN2023080321 W CN 2023080321W WO 2024113531 A1 WO2024113531 A1 WO 2024113531A1
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WO
WIPO (PCT)
Prior art keywords
pin group
binding
pin
group
driving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/080321
Other languages
English (en)
French (fr)
Inventor
刘佳
黄耀
王蓉
何翼
颜俊
官慧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US18/727,336 priority Critical patent/US20250089496A1/en
Priority to CN202380008194.7A priority patent/CN118435725A/zh
Priority to EP23895706.2A priority patent/EP4496455A4/en
Publication of WO2024113531A1 publication Critical patent/WO2024113531A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/90—Assemblies of multiple devices comprising at least one organic light-emitting element
    • H10K59/95—Assemblies of multiple devices comprising at least one organic light-emitting element wherein all light-emitting elements are organic, e.g. assembled OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests

Definitions

  • the present disclosure relates to but is not limited to the field of display technology, and in particular to a display panel and a display device.
  • OLED display devices have the advantages of ultra-thin, wide viewing angle, active light emission, high brightness, continuously adjustable light color, low cost, fast response speed, low power consumption, wide operating temperature range and flexible display, and have gradually become the next generation display technology with great development prospects. According to different driving modes, OLED can be divided into passive matrix drive (PM) type and active matrix drive (AM) type. AM OLED is a current driven device, which uses independent thin film transistors (TFT) to control each sub-pixel, and each sub-pixel can be driven to emit light continuously and independently.
  • TFT thin film transistors
  • an embodiment of the present disclosure provides a display panel, comprising a display substrate, comprising a display area and a binding area located on one side of the display area;
  • a plurality of sub-pixels are located in the display area
  • a plurality of data lines located in the display area and electrically connected to the plurality of sub-pixels
  • a plurality of binding pin groups are located in the binding area, the binding pin groups include at least one driving pin group and at least one touch pin group, in the plurality of binding pin groups, the plurality of driving pin groups are arranged along a first direction, and the at least one touch pin group is interspersed and arranged in the plurality of driving pin groups. At least one touch pin group is arranged between the pin groups, and between two adjacent drive pin groups. At least some of the drive pins in the drive pin groups are configured to be electrically connected to the multiple data lines, and the at least one touch pin group is configured to be electrically connected to the touch line.
  • the display substrate further includes: a frame area surrounding the display area, the frame area including the binding area, and a gate driving circuit is disposed in the frame area;
  • At least two of the plurality of binding pin groups respectively include a gate driving circuit pin group, and the gate driving circuit pin group is configured to be electrically connected to the gate driving circuit.
  • the number of the at least two binding pin groups is two, the two binding pin groups each include a gate driving circuit pin group, and the two gate driving circuit pin groups are respectively located in two binding pin groups on both sides.
  • the plurality of binding pin groups include n binding pin groups, and the first binding pin group to the nth binding pin group are arranged in sequence along the first direction, and n is a positive integer greater than or equal to 2;
  • the two gate drive circuit pin groups include a first gate drive circuit pin group and a second gate drive circuit pin group, the first gate drive circuit pin group is located in the first binding pin group, and the second gate drive circuit pin group is located in the nth binding pin group;
  • the first gate drive circuit pin group is located on a side of the drive pin group away from the nth binding pin group, and the first gate drive circuit pin group and the touch pin group are respectively located on both sides of the drive pin group; in the nth binding pin group, the second gate drive circuit pin group is located on a side of the drive pin group away from the first binding pin group, and the second gate drive circuit pin group and the touch pin group are respectively located on both sides of the drive pin group.
  • the binding pin group further includes two power pin groups, and the power pin groups are configured to be electrically connected to power lines;
  • the two power pin groups are respectively arranged on both sides of the driving pin group, the power pin group and the touch pin group located on the same side of the driving pin group are arranged along the first direction, and the power pin group and the gate driving circuit pin group located on the same side of the driving pin group are arranged along the first direction.
  • the power pin group located on the same side of the driving pin group includes a first power pin group and a second power pin group, and the second power pin group is located on a side of the first power pin group away from the driving pin group, the first power pin group is configured to be electrically connected to a first power line, and the second power pin group is configured to be electrically connected to a second power line.
  • two first power pin groups located on both sides of the driving pin group are symmetrical relative to the driving pin group
  • two second power pin groups located on both sides of the driving pin group are symmetrical relative to the driving pin group.
  • the first gate driving circuit pin group in the first binding pin group, in the first direction, on a side of the driving pin group away from the nth binding pin group, is located on a side of the second power pin group away from the first power pin group, or the first gate driving circuit pin group is located between the first power pin group and the second power pin group, or the first gate driving circuit pin group is located between the first power pin group and the driving pin group;
  • the second gate drive circuit pin group is located on the side of the second power pin group away from the first power pin group, or the second gate drive circuit pin group is located between the first power pin group and the second power pin group, or the second gate drive circuit pin group is located between the first power pin group and the driving pin group.
  • the power pin group and the touch pin group located on the same side of the driving pin group are arranged along the first direction, and the touch pin group is located on a side of the second power pin group away from the first power pin group, or the touch pin group is located between the first power pin group and the second power pin group, or the touch pin group is located between the driving pin group and the first power pin group.
  • a touch pin group is arranged between two adjacent driving pin groups, and the touch pin group is located between two second power pin groups, or the touch pin group is located between the first power pin group and the second power pin group in the same binding pin group, or the touch pin group is located between the first power pin group and the driving pin group in the same binding pin group.
  • At least one touch pin group is provided on a side of the first binding pin group away from the nth binding pin group, and on a side of the first binding pin group away from the nth binding pin group, the at least one touch pin group is located between the first gate drive circuit pin group and the second power pin group, or the at least one touch pin group is located between the first power pin group and the second power pin group, or the at least one touch pin group is located between the first power pin group and the driving pin group;
  • At least one touch pin group is arranged on a side of the nth binding pin group away from the first binding pin group; and on a side of the nth binding pin group away from the first binding pin group, the at least one touch pin group is located between the second gate drive circuit pin group and the second power pin group, or the at least one touch pin group is located between the first power pin group and the second power pin group, or the at least one touch pin group is located between the first power pin group and the driving pin group.
  • the binding area includes a binding pin area and a driving chip area, and in the second direction, the driving chip area is located between the display area and the binding pin area, and the plurality of binding pin groups are arranged in the binding pin area;
  • the driving chip area is provided with a plurality of integrated circuit pin groups arranged along the first direction, the plurality of integrated circuit pin groups are configured to be bound to the integrated circuit and electrically connected to the plurality of data lines, the plurality of driving pin groups are respectively connected to the corresponding plurality of integrated circuit pin groups through pin connection lines; the plurality of binding pin groups are configured to be electrically connected to the plurality of data lines through the plurality of integrated circuit pin groups, respectively.
  • the multiple integrated circuit pin groups include n integrated circuit pin groups, and the first integrated circuit pin group to the nth integrated circuit pin group are arranged in sequence along the first direction and are respectively connected to the first binding pin group to the nth binding pin group; the gate drive circuit is configured to be electrically connected to the first integrated circuit pin group and the nth integrated circuit pin group through a gate drive circuit signal line.
  • the frame area includes a first frame area and a second frame area located on both sides of the display area in the first direction;
  • the gate drive circuit signal line includes a first gate drive circuit signal line and a second gate drive circuit signal line, the first gate drive circuit signal line extends from the first frame area to the binding area, and the second gate drive circuit signal line Extending from the second border area to the binding area;
  • the gate drive circuit includes a first gate drive circuit arranged in the first border area and a second gate drive circuit arranged in the second border area, the first gate drive circuit is configured to be electrically connected to the first integrated circuit pin group through the first gate drive circuit signal line, and the second gate drive circuit is configured to be electrically connected to the nth integrated circuit pin group through the second gate drive circuit signal line.
  • the binding area is further provided with a first adapter wire and a second adapter wire, the first adapter wire is configured to be connected to the first gate drive circuit signal line and the first gate drive circuit pin group, and the second adapter wire is configured to be connected to the second gate drive circuit signal line and the second gate drive circuit pin group.
  • the binding area also includes a plurality of test circuit groups, which are located in the binding area and arranged along a first direction, and in a second direction, the plurality of test circuit groups are located between the plurality of binding pin groups and the display area; the plurality of test circuit groups are electrically connected to the plurality of data lines, and each test circuit group is configured to be connected to at least one binding pin group during a testing phase; the first direction intersects with the second direction.
  • an embodiment of the present disclosure further provides a display panel, including:
  • a display substrate comprising a display area and a binding area located on one side of the display area;
  • a plurality of sub-pixels are located in the display area
  • a plurality of data lines located in the display area and electrically connected to the plurality of sub-pixels
  • a plurality of binding pin groups are located in the binding area, the binding pin groups include at least one driving pin group, among the plurality of binding pin groups, the plurality of driving pin groups are arranged along a first direction, two binding pin groups located on both sides of the plurality of binding pin groups respectively include a gate driving circuit pin group, at least part of the driving pins in the driving pin groups are configured to be electrically connected to the plurality of data lines, and the gate driving circuit pin group is configured to be electrically connected to the gate driving circuit signal line.
  • the plurality of binding pin groups include n binding pin groups, the first binding pin group to the nth binding pin group are arranged in sequence along the first direction, and n is a positive integer greater than or equal to 2; the binding pin group further includes at least one touch pin group, and the at least one touch pin group is arranged interspersed between the n driving pin groups, and the distance between two adjacent driving pin groups is At least one touch pin group is arranged between the touch control pins, and the at least one touch pin group is configured to be electrically connected to the touch control line;
  • the two gate drive circuit pin groups include a first gate drive circuit pin group and a second gate drive circuit pin group, the first gate drive circuit pin group is located in the first binding pin group, and the second gate drive circuit pin group is located in the nth binding pin group;
  • the first gate drive circuit pin group is located on a side of the drive pin group away from the nth binding pin group; in the nth binding pin group, the second gate drive circuit pin group is located on a side of the drive pin group away from the first binding pin group.
  • no touch pin group is set on the side of the first gate drive circuit pin group away from the nth binding pin group; no touch pin group is set on the side of the second gate drive circuit pin group away from the first binding pin group.
  • the binding area includes a binding pin area and a driving chip area, and in the second direction, the driving chip area is located between the display area and the binding pin area, and the plurality of binding pin groups are arranged in the binding pin area;
  • the driving chip area is provided with n integrated circuit pin groups arranged along the first direction, the first integrated circuit pin group to the nth integrated circuit pin group are arranged in sequence along the first direction, and are respectively connected to the first binding pin group to the nth binding pin group, the n integrated circuit pin groups are configured to be respectively bound to n integrated circuits and electrically connected to the multiple data lines, the n driving pin groups are respectively connected to the corresponding n integrated circuit pin groups through pin connecting lines; the n binding pin groups are configured to be respectively electrically connected to the multiple data lines through the n integrated circuit pin groups.
  • the display substrate further includes: a frame area surrounding the display area, the frame area including the binding area and a first frame area and a second frame area located on both sides of the display area in the first direction, the frame area is provided with a gate drive circuit and a gate drive circuit signal line;
  • the gate drive circuit signal line includes a first gate drive circuit signal line and a second gate drive circuit signal line, the first gate drive circuit signal line extends from the first frame area to the binding area, and the second gate drive circuit signal line extends from the second frame area to the binding area;
  • the gate drive circuit includes a first gate drive circuit arranged in the first border area and a second gate drive circuit arranged in the second border area, the first gate drive circuit is configured to be electrically connected to the first integrated circuit pin group through the first gate drive circuit signal line, and the second gate drive circuit is configured to be electrically connected to the nth integrated circuit pin group through the second gate drive circuit signal line.
  • the binding area is further provided with a first adapter wire and a second adapter wire, the first adapter wire is configured to be connected to the first gate drive circuit signal line and the first gate drive circuit pin group, and the second adapter wire is configured to be connected to the second gate drive circuit signal line and the second gate drive circuit pin group.
  • the binding pin group further includes two power pin groups, and the power pin groups are configured to be electrically connected to power lines;
  • the two power pin groups are respectively arranged on both sides of the driving pin group, and the power pin group and the gate driving circuit pin group on the same side of the driving pin group are arranged along the first direction.
  • the power pin group located on the same side of the driving pin group includes a first power pin group and a second power pin group, and the second power pin group is located on a side of the first power pin group away from the driving pin group, the first power pin group is configured to be electrically connected to a first power line, and the second power pin group is configured to be electrically connected to a second power line.
  • the first gate driving circuit pin group in the first binding pin group, in the first direction, on a side of the driving pin group away from the nth binding pin group, is located on a side of the second power pin group away from the first power pin group, or the first gate driving circuit pin group is located between the first power pin group and the second power pin group, or the first gate driving circuit pin group is located between the first power pin group and the driving pin group;
  • the second gate driving circuit pin group In the nth binding pin group, in the first direction, on the side of the driving pin group away from the first binding pin group, the second gate driving circuit pin group is located on the side of the second power pin group away from the first power pin group, or the second gate driving circuit pin group is located between the first power pin group and the second power pin group, or the second The gate driving circuit pin group is located between the first power supply pin group and the driving pin group.
  • an embodiment of the present disclosure further provides a display device, comprising the display panel described in any of the above embodiments.
  • FIG1 is a schematic diagram showing the structure of a display device
  • FIG2 is a schematic diagram showing a planar structure of a display substrate
  • FIG3 is a schematic diagram showing a cross-sectional structure of a display substrate
  • FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG5 is a working timing diagram of a pixel driving circuit
  • FIG6 is a schematic diagram showing the structure of a display panel
  • FIG7 is a schematic diagram showing a structure of a binding area in a display panel
  • FIG8 is a schematic diagram showing the structure of a display panel
  • FIG9 is a schematic diagram showing the structure of a display panel
  • FIG10 is a schematic diagram showing the structure of a display panel
  • FIG11 is a schematic diagram of a display panel structure provided by an embodiment of the present disclosure.
  • FIG12 is a schematic diagram of a display panel structure provided by an exemplary embodiment of the present disclosure.
  • FIG13a is a schematic diagram of a display panel structure provided by an exemplary embodiment of the present disclosure.
  • FIG13b is a schematic diagram of a display panel structure provided by an exemplary embodiment of the present disclosure.
  • FIG14 is a schematic diagram of a display panel structure provided by an exemplary embodiment of the present disclosure.
  • FIG15 is a schematic diagram of a display panel structure provided by an exemplary embodiment of the present disclosure.
  • FIG16 is a schematic diagram of a display panel structure provided by an exemplary embodiment of the present disclosure.
  • FIG17 is a schematic diagram of a display panel structure provided by an exemplary embodiment of the present disclosure.
  • FIG18 is a schematic diagram of a display panel structure provided by an exemplary embodiment of the present disclosure.
  • FIG19 is a schematic diagram of a display panel structure provided by an exemplary embodiment of the present disclosure.
  • FIG20 is an enlarged structural diagram of a first binding pin group provided by an exemplary embodiment of the present disclosure.
  • FIG21 is a schematic diagram of a display panel structure provided by an embodiment of the present disclosure.
  • FIG22 is a schematic diagram of a display panel structure provided by an embodiment of the present disclosure.
  • FIG23 is a schematic diagram of a display panel structure provided by an exemplary embodiment of the present disclosure.
  • FIG24 is a schematic diagram of a display panel structure provided by an exemplary embodiment of the present disclosure.
  • FIG. 25 is a schematic diagram showing the wiring arrangement of a flexible circuit board in a display panel provided by an exemplary embodiment of the present disclosure
  • FIG26 is a schematic diagram showing the wiring arrangement of a flexible circuit board in a display panel provided by an exemplary embodiment of the present disclosure
  • FIG. 27 is a schematic diagram showing the wiring arrangement of a flexible circuit board in a display panel provided by an exemplary embodiment of the present disclosure.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate component, or it can be the internal communication of two components.
  • installed should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate component, or it can be the internal communication of two components.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (or drain electrode terminal, drain connection region, or drain electrode) and a source electrode (or source electrode terminal, source connection region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • a channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may sometimes be interchanged. Therefore, in the present disclosure, the "source electrode” and the “drain electrode” may be interchanged.
  • the gate electrode may also be referred to as a control electrode.
  • “electrically connected” includes the case where components are connected together through an element having some kind of electrical function.
  • “Element having some kind of electrical function” means any element that can electrically connect components. There is no particular limitation on the transmission and reception of signals.
  • “Elements having some kind of electrical function” may be, for example, electrodes or wirings, or switching elements such as transistors, or other functional elements such as resistors, inductors or capacitors.
  • FIG1 is a schematic diagram of the structure of a display device, wherein a display substrate may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array, wherein the timing controller is connected to the data signal driver, the scan signal driver, and the light emitting signal driver, respectively, wherein the data signal driver is connected to a plurality of data signal lines (D1 to Dn), respectively, wherein the scan signal driver is connected to a plurality of scan signal lines (S1 to Sm), respectively, and the light emitting signal driver is connected to a plurality of light emitting signal lines (E1 to Eo).
  • the timing controller is connected to the data signal driver, the scan signal driver, and the light emitting signal driver, respectively
  • the data signal driver is connected to a plurality of data signal lines (D1 to Dn), respectively
  • the scan signal driver is connected to a plurality of scan signal lines (S1 to Sm), respectively
  • the light emitting signal driver is connected to a pluralit
  • the pixel array may include a plurality of sub-pixels Pxij, wherein i and j may be natural numbers, wherein at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, wherein the circuit unit may include at least one scan signal line, at least one data signal line, at least one light emitting signal line, and a pixel driving circuit.
  • the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data signal driver to the data signal driver, may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan signal driver to the scan signal driver, and may provide a clock signal, an emission stop signal, etc.
  • the data signal driver can generate data voltages to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller.
  • the data signal driver can sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, and n can be a natural number.
  • the scan signal driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller.
  • the scan signal driver can sequentially provide scan signals with conduction level pulses to the scan signal lines S1 to Sm.
  • the scan signal driver can be constructed in the form of a shift register, and can sequentially transmit the scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of the clock signal to generate a scan signal, and m can be a natural number.
  • the light-emitting signal driver can generate emission signals to be provided to the light-emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller.
  • the light emitting signal driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo.
  • the light emitting driver may be constructed in the form of a shift register, and may sequentially transmit emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal.
  • the transmission signal is generated by the formula, and o can be a natural number.
  • FIG2 is a schematic diagram of a planar structure of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, and the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light-emitting device.
  • the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device.
  • the light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which they are located.
  • a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel may be included in the pixel unit P.
  • the shape of the sub-pixels in the pixel unit may be rectangular, rhombus, pentagonal, or hexagonal, and the three sub-pixels may be arranged in parallel horizontally, vertically, or in a herringbone pattern, which is not limited in the present disclosure.
  • FIG3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101.
  • the display substrate may include other film layers, such as spacers, etc., which are not limited in the present disclosure.
  • the substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit.
  • the light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304.
  • the anode 301 is connected to the drain electrode of the driving transistor 210 through a via
  • the organic light-emitting layer 303 is connected to the anode 301
  • the cathode 304 is connected to the organic light-emitting layer 303.
  • the organic light-emitting layer 303 emits light of corresponding colors under the drive of the anode 301 and the cathode 304.
  • the encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together.
  • the first encapsulation layer 401 The third encapsulation layer 403 may be made of inorganic materials
  • the second encapsulation layer 402 may be made of organic materials
  • the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting structure layer 103 .
  • the organic light-emitting layer 303 may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).
  • HIL stacked hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • EML emitting layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the hole injection layers of all sub-pixels may be a common layer connected together
  • the electron injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers of all sub-pixels may be a common layer connected together
  • the electron transport layers of all sub-pixels may be a common layer connected together
  • the hole blocking layers of all sub-pixels may be a common layer connected together
  • the light-emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated
  • the electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may include 7 transistors (a first transistor T1 to a seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit may be connected to 7 signal lines (a data signal line D, a first scanning signal line S1, a second scanning signal line S2, a light emitting signal line E, an initial signal line INIT, a first power line VDD, and a second power line VSS).
  • the pixel driving circuit may include a first node N1, a second node N2, and a third node N3.
  • the first node N1 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5,
  • the second node N2 is respectively connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C
  • the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.
  • a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .
  • the control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3, so that the charge amount of the control electrode of the third transistor T3 is initialized.
  • the control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the third transistor T3 can be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When the on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the fifth transistor T5 and the sixth transistor T6 can be called light emitting transistors. When the on-level light emitting signal is applied to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to make the light emitting device emit light.
  • the control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the seventh transistor T7 The initialization voltage is transmitted to the first electrode of the light emitting device to initialize or release the charge accumulated in the first electrode of the light emitting device.
  • the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously provided high level signal.
  • the first scanning signal line S1 is a scanning signal line in the pixel driving circuit of the current display row
  • the second scanning signal line S2 is a scanning signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the first scanning signal line S1 is S(n), and the second scanning signal line S2 is S(n-1), and the second scanning signal line S2 of the current display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row, which can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.
  • the first scan signal line S1, the second scan signal line S2, the emission signal line E, and the initial signal line INIT extend in a horizontal direction
  • the second power line VSS, the first power line VDD, and the data signal line D extend in a vertical direction.
  • the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.
  • OLED organic light emitting diode
  • FIG5 is a working timing diagram of a pixel driving circuit. An exemplary embodiment is described below through the working process of the pixel driving circuit illustrated in FIG4.
  • the pixel driving circuit in FIG4 includes 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C and 7 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS), and all 7 transistors are P-type transistors.
  • the operation process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage.
  • the signal of the second scanning signal line S2 is a low level signal, and the signals of the first scanning signal line S1 and the light emitting signal line E are high level signals.
  • the signal of S2 is a low-level signal, which turns on the first transistor T1, and the signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, which turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7, and the OLED does not emit light at this stage.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low level signal
  • the signals of the second scanning signal line S2 and the light emitting signal line E are high level signals
  • the data signal line D outputs the data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C.
  • the voltage of the second end (the second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the OLED is ensured not to emit light.
  • the signal of the second scanning signal line S2 is a high-level signal, which turns off the first transistor T1.
  • the signal of the light-emitting signal line E is a high-level signal, which turns off the fifth transistor T5 and the sixth transistor T6.
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • )-Vth]2 K*[(Vdd-Vd)]2
  • I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the threshold voltage of the third transistor T3
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • FIG6 is a schematic diagram of the structure of a display panel.
  • the display panel may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100.
  • the display area 100 may include a plurality of sub-pixels Pxij arranged regularly, the sub-pixels may include a pixel driving circuit and a light-emitting device, the binding area 200 may include a binding circuit for connecting a signal line to an external driving device, and the frame area 300 may include a gate driving circuit and a second power line VSS for transmitting a voltage signal to the plurality of sub-pixels.
  • FIG7 is a schematic diagram of the structure of the binding area in the display panel.
  • the binding area 200 in a plane parallel to the display panel, the binding area 200 is located on one side of the display area 100, and the binding area 200 includes a first fan-out area 201, a bending area 202, and a composite circuit area 2001 arranged in sequence along a direction away from the display area 100; wherein the composite circuit area 2001 may include a second fan-out area 203, an anti-static area 204, a driver chip area 205, and a binding electrode area 206 arranged in sequence along a direction away from the bending area 202.
  • the first fan-out area 201 includes a data fan-out line, a first power line, and a second power line.
  • the data fan-out line is located in the middle of the first fan-out area 201 and includes a plurality of data connection lines, and the plurality of data connection lines are configured to connect the data line (Data Line) of the display area 100 in a fan-out routing manner.
  • the first power line is configured to connect the high voltage power line (VDD) of the display area 100
  • the second power line is a low voltage power line (VSS) located in the frame area 300.
  • the bending area 202 includes a composite insulating layer provided with grooves, and is configured to bend the binding area 200 to the back of the display area 100.
  • the second fan-out area 203 includes a plurality of data connection lines led out in a fan-out routing manner.
  • the anti-static area 204 includes an anti-static circuit, and is configured to prevent electrostatic damage to the display panel by eliminating static electricity.
  • the driving chip area 205 includes an integrated circuit (IC) 400, which is configured to be connected to a plurality of data connection lines.
  • the binding electrode area 206 includes a plurality of binding pads (Bonding Pad), which is configured to be bound and connected to a flexible printed circuit (FPC) 500.
  • the integrated circuit (IC) 400 can be bound and connected to the driving chip area 205, and the flexible printed circuit (FPC) 500 can be bound and connected to the binding electrode area 206.
  • the integrated circuit 400 can be generated for The driving signal required to drive the sub-pixel can be provided to the sub-pixel in the display area 100.
  • the driving signal can be a data signal that controls the light luminance of the sub-pixel.
  • the binding electrode area 206 can be provided with a pad including a plurality of pins (PINs), and the flexible circuit board 500 can be bound and connected to the pad.
  • the bending region 202 may be bent at a curvature, and the surface of the composite circuit region 2001 may be reversed, that is, the surface of the composite circuit region 2001 facing upward may be converted to face downward by the bending of the bending region 202.
  • the composite circuit region 2001 may overlap with the display region 100 in the thickness direction of the display panel.
  • a flexible printed circuit (FPC) 500 includes a binding connection area 501 and a mainboard connection area 502.
  • the FPC is bound and connected to the binding area 200 through the binding connection area 501, and the FPC is connected to the mainboard 600 through the mainboard connection area 502.
  • the FPC and the mainboard can be connected through a board-to-board (BTB) connector.
  • a printed circuit board (PCB) can be provided on the mainboard, and the flexible printed circuit 500 can be electrically connected to the PCB on the mainboard 600 through the mainboard connection area 502.
  • multiple ICs and multiple FPCs need to be set, and the multiple FPCs are respectively bound and connected to the multiple ICs.
  • four ICs can be set to be bound and connected to four FPCs respectively, and the embodiment of the present disclosure is not limited to four ICs and four FPCs.
  • the number of ICs and FPCs can be set according to the size and function requirements of the display panel, and the present disclosure is not limited here.
  • the display panel is provided with a plurality of gate drive circuits (GOA) and gate drive circuit signal lines (GOA signal lines), the GOA signal lines may include clock signal lines (for example, CK signal lines, CB signal lines, STV signal lines, etc.), and the plurality of GOA signal lines are arranged on the left and right side frames of the display panel as shown in FIG. 10 and FIG. 6, and the left and right side frames are connected to the FPC via the lower frame through the binding pin group.
  • GOA gate drive circuits
  • GOA signal lines may include clock signal lines (for example, CK signal lines, CB signal lines, STV signal lines, etc.)
  • the plurality of GOA signal lines are arranged on the left and right side frames of the display panel as shown in FIG. 10 and FIG. 6, and the left and right side frames are connected to the FPC via the lower frame through the binding pin group.
  • GOA is an abbreviation for array substrate row drive, and its full English name is Gate Driver on Array.
  • the FPC is provided with a plurality of gate drive circuit traces (GOA traces), the display panel is provided with a plurality of GOA signal lines and binding pins connected to the plurality of GOA signal lines, the plurality of GOA traces in the FPC are respectively bound and connected to the plurality of binding pins, so that the GOA traces in the FPC are respectively electrically connected to the plurality of GOA signal lines in the display panel.
  • GOA gate drive circuit traces
  • the gate drive circuit routing on the FPC also increases accordingly, which increases the size of the FPC along the GOA (gate drive circuit) routing on the display panel and the binding pins connected to the gate drive circuit in the display panel along the arrangement direction, resulting in an increase in the space occupied by the FPC on the display panel, and there is a problem of insufficient space for the display panel to access the FPC.
  • a display panel which may include:
  • a display substrate comprising a display area and a binding area located on one side of the display area;
  • a plurality of sub-pixels are located in the display area
  • a plurality of data lines located in the display area and electrically connected to the plurality of sub-pixels;
  • a plurality of binding pin groups are located in the binding area, the binding pin groups include at least one driving pin group and at least one touch pin group, among the plurality of binding pin groups, the plurality of driving pin groups are arranged along a first direction, the at least one touch pin group is interspersed and arranged between the plurality of driving pin groups, at least one touch pin group is arranged between two adjacent driving pin groups, at least part of the driving pins in the driving pin groups are configured to be electrically connected to the plurality of data lines, and the at least one touch pin group is configured to be electrically connected to the touch line.
  • At least one touch pin group is interspersed between multiple driving pin groups, at least one touch pin group is arranged between two adjacent driving pin groups, and the touch pin group is arranged in the middle position of multiple binding pin groups.
  • the gaps between the multiple binding pin groups can be fully utilized, which greatly saves the space occupied by the flexible circuit board in the display panel and overcomes the problem of insufficient space for the display panel to connect to the FPC in the prior art.
  • an embodiment of the present disclosure provides a display panel, which may include:
  • the display substrate includes a display area AA and a binding area B1 located on one side of the display area AA;
  • a plurality of data lines located in the display area AA and electrically connected to the plurality of sub-pixels Pxij;
  • the binding pin groups 41 include at least one driving pin group 411 and at least one touch pin group 412.
  • the multiple driving pin groups 411 are arranged along the first direction X
  • at least one touch pin group 412 is interspersed and arranged between the multiple driving pin groups 411
  • at least one touch pin group 412 is arranged between two adjacent driving pin groups 411.
  • At least part of the driving pins in the driving pin group 411 are configured to be electrically connected to multiple data lines
  • at least one touch pin group 412 is configured to be electrically connected to the touch line TP.
  • a plurality of driving pins may be included in the driving pin group 411 .
  • the plurality of data lines include at least a plurality of data signal lines D, and the plurality of data signal lines D may be provided to provide data signals to the plurality of sub-pixels Pxij.
  • the display substrate may further include: a frame region surrounding the display region AA, the frame region including a binding region B1 , and a gate driving circuit GOA is disposed in the frame region;
  • At least two of the plurality of binding pin groups 41 include a gate driving circuit pin group 413 , respectively.
  • the gate driving circuit pin group 413 is configured to be electrically connected to the gate driving circuit.
  • the number of at least two binding pin groups is two, and the two binding pin groups each include a gate drive circuit pin group 413.
  • the two gate drive circuit pin groups 413 are respectively located in the two binding pin groups 41 on both sides.
  • the plurality of binding pin groups 41 include n binding pin groups 41, and the first binding pin group 41 to the nth binding pin group 41 are sequentially arranged along the first direction X, and n is a positive integer greater than or equal to 2; as shown in FIG. 13a and FIG. 13b, n may be 4;
  • the two gate drive circuit pin groups 413 include a first gate drive circuit pin group 4131 and a second gate drive circuit pin group 4132.
  • the first gate drive circuit pin group 4131 is located in the first binding pin group 41
  • the second gate drive circuit pin group 4132 is located in the nth binding pin group 41.
  • the first gate drive circuit pin group 4131 is located on the side of the driving pin group 411 away from the nth binding pin group 41, and the first gate drive circuit pin group 4131 and the touch pin group 412 are respectively located on both sides of the driving pin group 411; in the nth binding pin group 41
  • the second gate driving circuit pin group 4132 is located at a side of the driving pin group 411 away from the first binding pin group 41, and the second gate driving circuit pin group 4132 and the touch pin group 412 are located at two sides of the driving pin group 411 respectively.
  • the plurality of binding pin groups 41 may include a first binding pin group 41a, a second binding pin group 41b, a third binding pin group 41c, and a fourth binding pin group 41d arranged along a first direction X, the first binding pin group 41a, the second binding pin group 41b, the third binding pin group 41c, and the fourth binding pin group 41d respectively include a driving pin group 411a, a driving pin group 411b, a driving pin group 411c, and a driving pin group 411d, the first gate drive circuit pin group 4131 is located in the first binding pin group 41a, and the second gate drive circuit pin group 4132 is located in the In the fourth binding pin group 41d; in the first binding pin group 41a, the first gate drive circuit pin group 4131 is located on the side of the driving pin group 411a away from the fourth binding pin group 41d, and the first gate drive circuit pin group 4131 and the touch pin group 412a are respectively located on both sides of the driving pin group 411a
  • the binding pin group 41 further includes two power pin groups 414 , and the power pin groups 414 are configured to be electrically connected to the power line;
  • the two power pin groups 414 are respectively arranged on both sides of the driving pin group 411, the power pin group 414 and the touch pin group 412 located on the same side of the driving pin group 411 are arranged along the first direction X, and the power pin group 414 and the gate driving circuit pin group 413 located on the same side of the driving pin group 411 are arranged along the first direction X.
  • the power pin group 414 located on the same side of the driving pin group 411 includes a first power pin group 4141 and a second power pin group 4142, and the second power pin group 4142 is located on the side of the first power pin group 4141 away from the driving pin group 411, the first power pin group 4141 is configured to be electrically connected to the first power line PL1, and the second power pin group 4142 is configured to be electrically connected to the second power line PL2.
  • the first gate driving circuit pin group 4131 in the first binding pin group 41, in the first direction X, on the side of the driving pin group 411 away from the nth binding pin group 41, the first gate driving circuit pin group 4131 is located on the side of the second power pin group 4142 away from the first power pin group 4141, or as shown in FIG. 14 , the first gate driving circuit pin group 413 is located between the first power pin group 4141 and the second power pin group 4142, or as shown in FIG. 15 , the first gate driving circuit pin group 4131 is located between the first power pin group 4141a and the driving pin group 411a;
  • the second gate drive circuit pin group 4132 is located on the side of the second power pin group 4142 away from the first power pin group 4141, or as shown in Figure 14, the second gate drive circuit pin group 4132 is located between the first power pin group 4141 and the second power pin group 4142, or as shown in Figure 15, the second gate drive circuit pin group 4132 is located between the first power pin group 4141 and the driving pin group 411.
  • the power pin group 414 and the touch pin group 412 located on the same side of the driving pin group 411 are arranged along the first direction X, and, as shown in Figures 12 to 13b, the touch pin group 412 is located on a side of the second power pin group 4142 away from the first power pin group 4141, or as shown in Figure 14, the touch pin group 412 is located between the first power pin group 4141 and the second power pin group 4142, or as shown in Figure 19, the touch pin group 412 is located between the driving pin group 411 and the first power pin group 4141.
  • a touch pin group 412 is arranged between two adjacent driving pin groups, and the touch pin group 412 may be located between two second power pin groups 4142 as shown in Figure 16, or the touch pin group 412 may be located between the first power pin group 4141 and the second power pin group 4142 in the same binding pin group 41 as shown in Figure 17, or the touch pin group 412 is located between the first power pin group 4141 and the driving pin group 411 in the same binding pin group 41 as shown in Figure 18.
  • At least one touch pin group 412 is disposed on a side of the first binding pin group 41 away from the nth binding pin group 41, and at least one touch pin group 412 is disposed on the side of the first binding pin group 41 away from the nth binding pin group 41.
  • the pin group is away from the side of the nth binding pin group, as shown in FIG17, at least one touch pin group 412 is located between the first gate driving circuit pin group 4131 and the second power pin group 4142, or as shown in FIG18, at least one touch pin group 412 is located between the first power pin group 4141 and the second power pin group 4142, or as shown in FIG19, at least one touch pin group 412 is located between the first power pin group 4141 and the driving pin group 411;
  • At least one touch pin group is arranged on a side of the nth binding pin group 41 away from the first binding pin group 41; and on a side of the nth binding pin group away from the first binding pin group, as shown in FIG17 , at least one touch pin group 412 is located between the second gate drive circuit pin group 4132 and the second power pin group 4142, or as shown in FIG18 , at least one touch pin group 412 is located between the first power pin group 4141 and the second power pin group 4142, or as shown in FIG19 , at least one touch pin group 412 is located between the first power pin group 4141 and the driving pin group 411.
  • the binding area B1 may include a binding pin area B10 and a driving chip area B116 .
  • the driving chip area B116 is located between the display area AA and the binding pin area B10 .
  • a plurality of binding pin groups 41 are disposed in the binding pin area B116 .
  • the driving chip area B116 is provided with a plurality of integrated circuit pin groups 61 arranged along the first direction X, the plurality of integrated circuit pin groups 61 are configured to be bound to the integrated circuit and electrically connected to a plurality of data lines, the plurality of driving pin groups 411 are respectively connected to the corresponding plurality of integrated circuit pin groups 61 through pin connection lines; the plurality of binding pin groups 41 are configured to be respectively electrically connected to the plurality of data lines through the plurality of integrated circuit pin groups 61.
  • the plurality of integrated circuit pin groups include n integrated circuit pin groups, and the first integrated circuit pin group 61 to the nth integrated circuit pin group 61 are arranged in sequence along the first direction X, and are respectively connected to the first binding pin group 41 to the nth binding pin group 41; the gate drive circuit GOA is configured to be electrically connected to the first integrated circuit pin group 61 and the nth integrated circuit pin group 61 through the gate drive circuit signal line.
  • the frame area includes a first frame area B21 and a second frame area B22 located on both sides of the display area AA in the first direction X;
  • the gate drive circuit signal line includes a first gate drive circuit signal line 71 a and a second gate drive circuit signal line 71 b, the first gate drive circuit signal line 71 a extends from the first frame area B21 to the binding area B1, and the second gate drive circuit signal line 71 b extends from the second frame area B22 to the binding area B1;
  • the gate drive circuit GOA includes a first gate drive circuit arranged in the first border area B21 and a second gate drive circuit arranged in the second border area B22.
  • the first gate drive circuit is configured to be electrically connected to the first integrated circuit pin group 61a through the first gate drive circuit signal line 71a
  • the second gate drive circuit is configured to be electrically connected to the nth integrated circuit pin group 61 through the second gate drive circuit signal line 71b.
  • n may be 4, and the integrated circuit pin group may include an integrated circuit pin group 61 a , an integrated circuit pin group 61 b , an integrated circuit pin group 61 c , and an integrated circuit pin group 61 d .
  • the binding area B1 may also be provided with a first adapter wire 37a and a second adapter wire 37b, the first adapter wire 37a is configured to be connected to the first gate drive circuit signal line 71a and the first gate drive circuit pin group 4131, and the second adapter wire 37b is configured to be connected to the second gate drive circuit signal line 71b and the second gate drive circuit pin group 4132.
  • the display panel may further include a plurality of test circuit groups 42, which are located in the binding area B1 and arranged along the first direction X.
  • the plurality of test circuit groups 42 are located between the plurality of binding pin groups 41 and the display area AA; the plurality of test circuit groups 42 are electrically connected to the plurality of data lines, and each test circuit group 42 is configured to be connected to at least one binding pin group 41 during the test phase.
  • the plurality of test circuit groups 42 may include a first test circuit group 42a, a second test circuit group 42b, a third test circuit group 42c, and a fourth test circuit group.
  • the first direction X intersects with the second direction Y. In an exemplary embodiment, within the plane where the display substrate is located, the first direction X is perpendicular to the second direction Y.
  • FIG. 20 it is an enlarged structural diagram of the first binding pin group 41a in FIG. 13a and FIG. 13b .
  • the power pin group 414 (including the first power pin group 4141 and the second power pin group 4142) is located on both sides of the driving pin group 411a
  • the first gate drive circuit 391 pin group 4131 is located on the side of the driving pin group 411a away from the fourth driving pin group 41d
  • the power pin group 414 (including the first power pin group 4141 and the second power pin group 4142) is located between the first gate drive circuit 391 pin group 4131 and the driving pin group 411a
  • the touch pin group 412a is located between the driving pin group 411a and the second binding pin group 41b.
  • the first power pin group 4141a and the second power pin group 4142a are located on the same side of the driving pin group 411a, and the first power pin group 4141a is located between the driving pin group 411a and the second power pin group 4142a.
  • the driving pin group 411a may include a plurality of driving pins 4110 arranged along the first direction
  • the touch pin group 412a may include a plurality of touch pins 4120 arranged along the first direction X
  • the first gate driving circuit 391 pin group 4131 may include a plurality of gate driving circuit pins 4130 arranged along the first direction X
  • the first power pin group 4141a may include at least one first power pin 41410
  • the second power pin group 4142a may include at least one second power pin 41420
  • the first power pin 41410 is configured to be connected to the first power line PL1
  • the second power pin 41420 is configured to be connected to the second power line PL2.
  • the value of n can be 4, the binding area B1 can include a first binding pin group 41a, a second binding pin group 41b, a third binding pin group 41c and a fourth binding pin group 41d, and the driving pin group 411 can include a first driving pin group 411a, a second driving pin group 411b, a third driving pin group 411c and a fourth driving pin group 411d; the first power pin group 4141 can include a first first power pin group 4141a, a second first power pin group 4141b, a third first power pin group 4141c and a fourth first power pin group 4141d.
  • the present disclosure also provides a display panel, as shown in FIG. 21 and FIG. 22 , including:
  • the display substrate includes a display area AA and a binding area B1 located on one side of the display area AA;
  • a plurality of data lines located in the display area AA and electrically connected to the plurality of sub-pixels Pxij;
  • a plurality of binding pin groups 41 are located in the binding area B1, and the binding pin groups 41 include at least one driving pin group 411.
  • the plurality of driving pin groups 411 are arranged along the first direction X, and two binding pin groups 41 located on both sides of the plurality of binding pin groups 41 respectively include a gate driving circuit pin group 413, and at least part of the driving pins in the driving pin group 411 are configured to be electrically connected to the plurality of data lines, and the gate driving circuit pin group 413 is configured to be electrically connected to the gate driving circuit signal Electrical connection.
  • the plurality of binding pin groups 41 may include n binding pin groups 41 , the first binding pin group 41 to the nth binding pin group 41 are sequentially arranged along the first direction X, and n is a positive integer greater than or equal to 2; the binding pin group may further include at least one touch pin group 412, the at least one touch pin group 412 is interspersed and arranged between the n driving pin groups 411, at least one touch pin group 412 is arranged between two adjacent driving pin groups 411, and the at least one touch pin group 412 is configured to be electrically connected to the touch line TP; the value of n may be 4;
  • the two gate drive circuit pin groups 413 may include a first gate drive circuit pin group 4131 and a second gate drive circuit pin group 4132, the first gate drive circuit pin group 4131 is located in the first binding pin group 41, and the second gate drive circuit pin group 4132 is located in the nth binding pin group 41;
  • the first gate drive circuit pin group 4131 is located on the side of the drive pin group 411 away from the nth binding pin group 41; in the nth binding pin group 41, the second gate drive circuit pin group 4132 is located on the side of the drive pin group 411 away from the first binding pin group 41.
  • no touch pin group is set on the side of the first gate drive circuit pin group 4131 away from the nth binding pin group 41 ; and no touch pin group is set on the side of the second gate drive circuit pin group 4132 away from the first binding pin group 41 .
  • the binding area B1 includes a binding pin area B10 and a driving chip area B116 .
  • the driving chip area B116 is located between the display area AA and the binding pin area B10 .
  • a plurality of binding pin groups 41 are disposed in the binding pin area B10 .
  • the driving chip area B116 is provided with n integrated circuit pin groups 61 arranged along the first direction X.
  • the first integrated circuit pin group 61 to the nth integrated circuit pin group 61 are arranged in sequence along the first direction X and are respectively connected to the first binding pin group 41 to the nth binding pin group 41.
  • the n integrated circuit pin groups 61 are configured to be respectively bound to n integrated circuits and electrically connected to multiple data lines.
  • the n driving pin groups 411 are respectively connected to the corresponding n integrated circuit pin groups 61 through the pin connection lines L0; the n binding pin groups 41 are configured to be respectively electrically connected to multiple data lines through the n integrated circuit pin groups 61.
  • the display substrate may further include: a frame region surrounding the display area AA, the frame region including a binding area B1 and a first frame B21 region and a second frame B22 region located on both sides of the display area AA in the first direction X; a gate drive circuit and a gate drive circuit signal line are provided in the frame region; the gate drive circuit signal line may include a first gate drive circuit signal line 71 a and a second gate drive circuit 392 signal line 71 b, the first gate drive circuit signal line 71 a extends from the first frame B21 region to the binding area B1, and the second gate drive circuit 392 signal line 71 b extends from the second frame B22 region to the binding area B1;
  • the gate drive circuit GOA may include a first gate drive circuit 391 arranged in the first border B21 area and a second gate drive circuit 392 arranged in the second border B22 area, the first gate drive circuit 391 is configured to be electrically connected to the first integrated circuit pin group 61 through the first gate drive circuit signal line 71a, and the second gate drive circuit 392 is configured to be electrically connected to the nth integrated circuit pin group 61 through the second gate drive circuit signal line 71b.
  • the binding area B1 is also provided with a first adapter wire 37a and a second adapter wire 37b, the first adapter wire 37a is configured to be connected to the first gate drive circuit signal line 71a and the first gate drive circuit pin group 4131, and the second adapter wire 37b is configured to be connected to the second gate drive circuit signal line 71b and the second gate drive circuit pin group 4132.
  • the binding pin group 41 further includes two power pin groups 414, and the power pin groups 414 are configured to be electrically connected to the power line;
  • the power pin groups 414 are respectively arranged on both sides of the driving pin group 411, and the power pin group 414 and the gate driving circuit pin group 413 located on the same side of the driving pin group 411 are arranged along the first direction X.
  • the power pin group 414 located on the same side of the driving pin group 411 includes a first power pin group 4141 and a second power pin group 4142, and the second power pin group 4142 is located on the side of the first power pin group 4141 away from the driving pin group 411, the first power pin group 4141 is configured to be electrically connected to the first power line PL1, and the second power pin group 4142 is configured to be electrically connected to the second power line PL2.
  • the first gate driving circuit pin group 4131 is located at the second gate driving circuit pin group 4132.
  • the source pin group 4142 is located away from the side of the first power pin group 4141, or as shown in FIG. 14, the first gate drive circuit pin group 413 is located between the first power pin group 4141 and the second power pin group 4142, or as shown in FIG. 15, the first gate drive circuit pin group 4131 is located between the first power pin group 4141a and the drive pin group 411a;
  • the second gate drive circuit pin group 4132 is located on the side of the second power pin group 4142 away from the first power pin group 4141, or as shown in Figure 14, the second gate drive circuit pin group 4132 is located between the first power pin group 4141 and the second power pin group 4142, or as shown in Figure 15, the second gate drive circuit pin group 4132 is located between the first power pin group 4141 and the driving pin group 411.
  • the binding pin group 41 may further include a touch pin group 412.
  • the setting method of the touch pin group 412 may refer to the above embodiment and FIGS. 12 to 19 , and will not be described in detail here.
  • the present disclosure also provides a display panel, which may include:
  • the display substrate includes a display area AA and a binding area B1 located on one side of the display area AA;
  • a plurality of data lines located in the display area AA and electrically connected to the plurality of sub-pixels Pxij;
  • the circuit area 700 is located on a side of the binding area B1 away from the display area AA.
  • the circuit area 700 is provided with a plurality of flexible circuit boards arranged along a first direction X.
  • the plurality of flexible circuit boards are configured to be bound and connected to the binding area B1.
  • At least one drive wiring group C1 and at least one touch wiring group C2 are provided on the flexible circuit boards.
  • the plurality of drive wiring groups C1 are arranged along the first direction X, at least one touch wiring group C2 is interspersed and arranged between the plurality of drive wiring groups C1, at least one touch wiring group C2 is provided between two adjacent drive wiring groups C1, at least part of the drive wiring groups C1 are configured to be electrically connected to a plurality of data lines, and at least one touch wiring group C2 is configured to be electrically connected to the touch line TP.
  • the plurality of flexible circuit boards may include n flexible circuit boards, and the first flexible circuit board FPC1 to the nth flexible circuit board are sequentially arranged along the first direction X, where n is a positive integer greater than or equal to 2;
  • the two gate drive circuit wiring groups C3 include a first gate drive circuit wiring group C31 and a second gate drive circuit wiring group C32, the first gate drive circuit wiring group C31 is located in the first flexible circuit board FPC1, and the second gate drive circuit wiring group C32 is located in the nth flexible circuit board;
  • the first gate drive circuit wiring group C31 is located on the side of the driving wiring group C1 away from the nth flexible circuit board, and the first gate drive circuit wiring group C31 and the touch wiring group C2 are respectively located on both sides of the driving wiring group C1; in the nth flexible circuit board, the second gate drive circuit wiring group C32 is located on the side of the driving wiring group C1 away from the first flexible circuit board FPC1, and the second gate drive circuit wiring group C32 and the touch wiring group C2 are respectively located on both sides of the driving wiring group C1.
  • the value of n may be 4, and the four flexible circuit boards may include a first flexible circuit board FPC1 , a second flexible circuit board FPC2 , a third flexible circuit board FPC3 , and a fourth flexible circuit board FPC4 arranged along the first direction X.
  • any one of the flexible circuit boards further includes two power trace groups C4;
  • the first direction X in the same flexible circuit board, two power wiring groups C4 are respectively arranged on both sides of the driving wiring group C1, the power wiring group C4 and the touch wiring group C2 located on the same side of the driving wiring group C1 are arranged along the first direction X, and the power wiring group C4 and the gate driving circuit wiring group C3 located on the same side of the driving wiring group C1 are arranged along the first direction X.
  • the power wiring group C4 located on the same side of the driving wiring group C1 includes a first power wiring group C41 and a second power wiring group C42, and the second power wiring group C42 is located on a side of the first power wiring group C41 away from the driving wiring group C1.
  • the two first power wiring groups C41 located on both sides of the driving wiring group C1 are symmetrical relative to the driving wiring group C1
  • the two second power wiring groups C42 located on both sides of the driving wiring group C1 are symmetrical relative to the driving wiring group C1.
  • the first gate driving circuit wiring group C31 is located on the side of the second power wiring group C42 away from the first power wiring group C41, or as shown in FIG. 26, the first gate driving circuit wiring group C31 is located on the side of the first power wiring group C42 away from the first power wiring group C41. between the source wiring group C41 and the second power wiring group C42, or as shown in FIG. 27, the first gate drive circuit wiring group C31 is located between the first power wiring group C41 and the drive wiring group C1;
  • the second gate drive circuit wiring group C32 is located on the side of the second power wiring group C42 away from the first power wiring group C41, or as shown in Figure 26, the second gate drive circuit wiring group C32 is located between the first power wiring group C41 and the second power wiring group C42, or as shown in Figure 27, the second gate drive circuit wiring group C32 is located between the first power wiring group C41 and the driving wiring group C1.
  • the power wiring group C41 and the touch wiring group C2 located on the same side of the driving wiring group C1 are arranged along the first direction X, and, as shown in Figures 24 and 25, the touch wiring group C2 is located on a side of the second power wiring group C42 away from the first power wiring group C41, or as shown in Figure 26, the touch wiring group C2 is located between the first power wiring group C41 and the second power wiring group C42, or as shown in Figure 27, the touch wiring group C2 is located between the driving wiring group C1 and the first power wiring group C41.
  • the multiple flexible circuit boards shown in Figure 25 can be bound and connected to the display panel in Figure 13b; the multiple flexible circuit boards shown in Figure 26 can be bound and connected to the display panel in Figure 14; and the multiple flexible circuit boards shown in Figure 27 can be bound and connected to the display panel in Figure 15.
  • a frame 300 is disposed around the display area 100 .
  • the frame 300 may include a first frame B21 and a second frame B22 .
  • the routing arrangement of the flexible circuit board, the binding pin group of the binding area B1 in the display panel, the routing of the flexible circuit board and the signal line arrangement of the display area frame 300 are adjusted, and the gaps between the binding pin groups and between the multiple flexible circuit boards are reasonably utilized.
  • the arrangement of the outer lead bonding (OLB) routing in the flexible circuit board is not adjusted (that is, the arrangement of multiple driving routings in the driving routing group), and there is no need to adjust the driver chip and the arrangement of the binding pads in the binding area B1, which can avoid re-customizing the driver chip due to adjusting the driver chip, reduce the cost of replacing the driver chip, and save the display panel space occupied by the flexible circuit board at the lowest possible cost.
  • the gate driving circuit GOA can be electrically connected to the scanning signal line S of the display area AA, and the plurality of sub-pixels Pxij in the display panel can be electrically connected to the scanning signal line S of the display area AA.
  • the gate driving circuit GOA can be electrically connected to the scanning signal line S of the display area AA, and the plurality of sub-pixels Pxij in the display panel can be electrically connected to the scanning signal line S of the display area AA.
  • a plurality of test pin groups 51 arranged along the first direction X are further provided on a side of the binding area B1 away from the display area AA, and each test pin group may include a plurality of test pins arranged along the first direction X.
  • the test pins are configured as pins for signal transmission in the lighting test phase.
  • the display panel may further include a plurality of aging pins 31 arranged along the first direction X, and the plurality of aging pin groups 31 may be arranged between the plurality of binding pin groups 41.
  • the aging pin group 31 may be configured to be used in the aging phase or the test phase, and after the aging phase and the test phase are ended and the binding pin group is bound and connected to the flexible circuit board FPC, the aging pin group may be retained in the binding area B1 as an invalid pin, as shown in FIG. 13 b , which is a schematic diagram of the structure after the test pin group 51 in FIG. 13 a is cut off.
  • a plurality of aging pin groups 31 may be electrically connected via a second connection line 38.
  • the second connection line 38 may include at least a line segment extending along the first direction X and a line segment extending along the second direction Y, wherein the line segment extending along the first direction X may be located on a side of the test pin group 51 away from the display area AA.
  • the second connection line 38 may be electrically connected to the first adapter line 37 a and the second adapter line 37 b to ensure signal transmission consistency.
  • B112 is a bending area in the binding area B1 , and the bending area B112 may be configured such that the binding area B1 is bent to the back side of the display area AA.
  • the present disclosure also provides a display device, which may include the display panel described in any of the above embodiments.
  • the display device may be an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a car display, a digital photo frame, or a navigator, or any other product or component with a display function.
  • this embodiment is not limited to this.
  • At least one touch pin group in the display panel is interspersed and arranged between multiple driving pin groups, at least one touch pin group is arranged between two adjacent driving pin groups, and the touch pin group is arranged in the middle position of multiple binding pin groups, so that the gaps between the multiple binding pin groups can be fully utilized, which greatly saves the space occupied by the flexible circuit board in the display panel and overcomes the problem of insufficient space for the display panel to connect to the FPC in the prior art.

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Abstract

一种显示面板、显示装置，显示面板包括显示基板，显示基板包括显示区域(AA)和位于显示区域(AA)一侧的绑定区域(B1)；多个子像素(Pxij)，位于显示区域(AA)；多条数据线，位于显示区域(AA)，且与多个子像素(Pxij)电连接；多个绑定引脚组(41)，位于绑定区域(B1)，绑定引脚组(41)包括至少一个驱动引脚组(411)和至少一个触控引脚组(412)，在多个绑定引脚组(41)中，多个驱动引脚组(411)沿第一方向排布，至少一个触控引脚组(412)穿插排布在多个驱动引脚组(411)之间，相邻两个驱动引脚组(411)之间设置有至少一个触控引脚组(412)。

Description

显示面板和显示装置
本申请要求于2022年12月01日提交中国专利局、申请号为202211533619.X、发明名称为“显示基板及显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开涉及但不限于显示技术领域，尤其涉及一种显示面板、显示装置。
背景技术
有机发光二极管显示装置(Organic Light Emitting Diode，OLED)具有超薄、大视角、主动发光、高亮度、发光颜色连续可调、成本低、响应速度快、低功耗、工作温度范围宽及可柔性显示等优点，已逐渐成为极具发展前景的下一代显示技术。依据驱动方式的不同，OLED可以分为无源矩阵驱动(Passive Matrix，PM)型和有源矩阵驱动(Active Matrix，AM)型两种，AM OLED是电流驱动器件，采用独立的薄膜晶体管(Thin Film Transistor，TFT)控制每个子像素，每个子像素皆可以连续且独立的驱动发光。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开实施例提供了一种显示面板，包括显示基板，包括显示区域和位于所述显示区域一侧的绑定区域；
多个子像素，位于所述显示区域；
多条数据线，位于所述显示区域，且与所述多个子像素电连接；
多个绑定引脚组，位于所述绑定区域，所述绑定引脚组包括至少一个驱动引脚组和至少一个触控引脚组，在所述多个绑定引脚组中，所述多个驱动引脚组沿第一方向排布，所述至少一个触控引脚组穿插排布在所述多个驱动 引脚组之间，相邻两个驱动引脚组之间设置有至少一个触控引脚组，所述驱动引脚组中的至少部分驱动引脚被配置为与所述多条数据线电连接，所述至少一个触控引脚组被配置为与触控线电连接。
在示例性实施方式中，所述显示基板还包括：围绕所述显示区域的边框区域，所述边框区域包括所述绑定区域，所述边框区域设置有栅极驱动电路；
所述多个绑定引脚组中的至少两个绑定引脚组分别包括栅极驱动电路引脚组，所述栅极驱动电路引脚组被配置为与所述栅极驱动电路电连接。
在示例性实施方式中，在所述第一方向上，所述至少两个绑定引脚组的数量为两个，所述两个绑定引脚组分别包括一个栅极驱动电路引脚组，所述两个栅极驱动电路引脚组分别位于两侧的两个绑定引脚组中。
在示例性实施方式中，所述多个绑定引脚组包括n个绑定引脚组，第一个绑定引脚组至第n个绑定引脚组沿所述第一方向依次排布，n为大于或者等于2的正整数；
所述两个栅极驱动电路引脚组包括第一栅极驱动电路引脚组和第二栅极驱动电路引脚组，所述第一栅极驱动电路引脚组位于所述第一个绑定引脚组中，所述第二栅极驱动电路引脚组位于所述第n个绑定引脚组中；
在所述第一个绑定引脚组中，所述第一栅极驱动电路引脚组位于所述驱动引脚组远离所述第n个绑定引脚组的一侧，所述第一栅极驱动电路引脚组和所述触控引脚组分别位于所述驱动引脚组的两侧；在第n个绑定引脚组中，所述第二栅极驱动电路引脚组位于所述驱动引脚组远离所述第一个绑定引脚组的一侧，所述第二栅极驱动电路引脚组和触所述控引脚组分别位于所述驱动引脚组的两侧。
在示例性实施方式中，所述绑定引脚组中还包括两个电源引脚组，所述电源引脚组被配置为与电源线电连接；
在所述第一方向上，在同一个绑定引脚组中，所述两个电源引脚组分别设置于所述驱动引脚组的两侧，位于所述驱动引脚组同一侧的电源引脚组和触控引脚组沿所述第一方向排布，位于所述驱动引脚组同一侧的电源引脚组和栅极驱动电路引脚组沿所述第一方向排布。
在示例性实施方式中，在同一个绑定引脚组中，在所述第一方向上，位于所述驱动引脚组同一侧的所述电源引脚组包括第一电源引脚组和第二电源引脚组，并且所述第二电源引脚组位于所述第一电源引脚组远离所述驱动引脚组的一侧，所述第一电源引脚组被配置为与第一电源线电连接，所述第二电源引脚组被配置为与第二电源线电连接。
在示例性实施方式中，在同一个绑定引脚组中，在所述第一方向上，位于所述驱动引脚组两侧的两个第一电源引脚组相对于所述驱动引脚组对称，位于所述驱动引脚组两侧的两个第二电源引脚组相对于所述驱动引脚组对称。
在示例性实施方式中，在所述第一个绑定引脚组中，在所述第一方向上，在所述驱动引脚组远离所述第n个绑定引脚组的一侧，所述第一栅极驱动电路引脚组位于所述第二电源引脚组远离所述第一电源引脚组的一侧，或者所述第一栅极驱动电路引脚组位于所述第一电源引脚组和所述第二电源引脚组之间，或者所述第一栅极驱动电路引脚组位于所述第一电源引脚组和所述驱动引脚组之间；
在所述第n个绑定引脚组中，在所述第一方向上，在所述驱动引脚组远离所述第一个绑定引脚组的一侧，所述第二栅极驱动电路引脚组位于所述第二电源引脚组远离所述第一电源引脚组的一侧，或者所述第二栅极驱动电路引脚组位于所述第一电源引脚组和所述第二电源引脚组之间，或者所述第二栅极驱动电路引脚组位于所述第一电源引脚组和所述驱动引脚组之间。
在示例性实施方式中，在所述第一方向上，在同一个绑定引脚组中，位于所述驱动引脚组同一侧的电源引脚组与触控引脚组沿所述第一方向排布，并且，所述触控引脚组位于所述第二电源引脚组远离所述第一电源引脚组的一侧，或者所述触控引脚组位于所述第一电源引脚组和所述第二电源引脚组之间，或者所述触控引脚组位于所述驱动引脚组和所述第一电源引脚组之间。
在示例性实施方式中，相邻两个驱动引脚组之间设置一个触控引脚组，并且，所述触控引脚组位于两个第二电源引脚组之间，或者所述触控引脚组位于同一个绑定引脚组中的所述第一电源引脚组和所述第二电源引脚组之间，或者所述触控引脚组位于同一个绑定引脚组中的所述第一电源引脚组与所述驱动引脚组之间。
在示例性实施方式中，在所述第一方向上，所述第一个绑定引脚组远离所述第n个绑定引脚组的一侧设置有至少一个触控引脚组，并且在所述第一个绑定引脚组远离所述第n个绑定引脚组的一侧，所述至少一个触控引脚组位于所述第一栅极驱动电路引脚组与所述第二电源引脚组之间，或者所述至少一个触控引脚组位于所述第一电源引脚组与所述第二电源引脚组之间，或者所述至少一个触控引脚组位于所述第一电源引脚组与所述驱动引脚组之间；
所述第n个绑定引脚组远离所述第一个绑定引脚组的一侧设置有至少一个触控引脚组；并且在所述第n个绑定引脚组远离所述第一个绑定引脚组的一侧，所述至少一个触控引脚组位于所述第二栅极驱动电路引脚组与所述第二电源引脚组之间，或者所述至少一个触控引脚组位于所述第一电源引脚组与所述第二电源引脚组之间，或者所述至少一个触控引脚组位于所述第一电源引脚组与所述驱动引脚组之间。
在示例性实施方式中，所述绑定区域包括绑定引脚区和驱动芯片区，在第二方向上，所述驱动芯片区位于所述显示区域和所述绑定引脚区之间，所述多个绑定引脚组设置于所述绑定引脚区；
所述驱动芯片区设置有沿所述第一方向排布的多个集成电路引脚组，所述多个集成电路引脚组被配置为与集成电路绑定并与所述多条数据线电连接，所述多个驱动引脚组通过引脚连接线分别与对应的所述多个集成电路引脚组连接；所述多个绑定引脚组被配置为分别通过所述多个集成电路引脚组与所述多条数据线电连接。
在示例性实施方式中，所述多个集成电路引脚组包括n个集成电路引脚组，第一个集成电路引脚组至第n个集成电路引脚组沿所述第一方向依次排布，并分别与所述第一个绑定引脚组至第n个所述绑定引脚组连接；所述栅极驱动电路被配置为通过栅极驱动电路信号线与所述第一个集成电路引脚组和第n个集成电路引脚组电连接。
在示例性实施方式中，所述边框区域包括在所述第一方向上位于所述显示区域两侧的第一边框区和第二边框区；所述栅极驱动电路信号线包括第一栅极驱动电路信号线和第二栅极驱动电路信号线，所述第一栅极驱动电路信号线由所述第一边框区延伸至所述绑定区域，所述第二栅极驱动电路信号线 由所述第二边框区延伸至所述绑定区域；
所述栅极驱动电路包括设置于所述第一边框区的第一栅极驱动电路和设置于所述第二边框区的第二栅极驱动电路，所述第一栅极驱动电路被配置为通过所述第一栅极驱动电路信号线与所述第一个集成电路引脚组电连接，所述第二栅极驱动电路被配置为通过所述第二栅极驱动电路信号线与所述第n个集成电路引脚组电连接。
在示例性实施方式中，所述绑定区域还设有第一转接线和第二转接线，所述第一转接线被配置为与所述第一栅极驱动电路信号线和所述第一栅极驱动电路引脚组连接，所述第二转接线被配置为与所述第二栅极驱动电路信号线和所述第二栅极驱动电路引脚组连接。
在示例性实施方式中，绑定区域还包括多个测试电路组，位于所述绑定区域并沿第一方向排布，在第二方向上，所述多个测试电路组位于所述多个绑定引脚组与所述显示区域之间；所述多个测试电路组与所述多条数据线电连接，每个测试电路组被配置为在测试阶段与至少一个绑定引脚组连接；所述第一方向和所述第二方向交叉。
第二方面，本公开实施例还提供了一种显示面板，包括：
显示基板，包括显示区域和位于所述显示区域一侧的绑定区域；
多个子像素，位于所述显示区域；
多条数据线，位于所述显示区域，且与所述多个子像素电连接；
多个绑定引脚组，位于所述绑定区域，所述绑定引脚组包括至少一个驱动引脚组，在所述多个绑定引脚组中，所述多个驱动引脚组沿第一方向排布，所述多个绑定引脚组中位于两侧的两个绑定引脚组分别包括一个栅极驱动电路引脚组，所述驱动引脚组中的至少部分驱动引脚被配置为与所述多条数据线电连接，所述栅极驱动电路引脚组被配置为与栅极驱动电路信号线电连接。
在示例性实施方式中，所述多个绑定引脚组包括n个绑定引脚组，第一个绑定引脚组至第n个绑定引脚组沿所述第一方向依次排布，n为大于或者等于2的正整数；所述绑定引脚组还包括至少一个触控引脚组，所述至少一个触控引脚组穿插排布在所述n个驱动引脚组之间，相邻两个驱动引脚组之 间设置有至少一个触控引脚组，所述至少一个触控引脚组被配置为与触控线电连接；
所述两个栅极驱动电路引脚组包括第一栅极驱动电路引脚组和第二栅极驱动电路引脚组，所述第一栅极驱动电路引脚组位于所述第一个绑定引脚组中，所述第二栅极驱动电路引脚组位于所述第n个绑定引脚组中；
在所述第一个绑定引脚组中，所述第一栅极驱动电路引脚组位于所述驱动引脚组远离所述第n个绑定引脚组的一侧；在第n个绑定引脚组中，所述第二栅极驱动电路引脚组位于所述驱动引脚组远离所述第一个绑定引脚组的一侧。
在示例性实施方式中，在所述第一方向上，所述第一栅极驱动电路引脚组远离所述第n个绑定引脚组的一侧不设置触控引脚组；所述第二栅极驱动电路引脚组远离所述第一个绑定引脚组的一侧不设置触控引脚组。
在示例性实施方式中，所述绑定区域包括绑定引脚区和驱动芯片区，在第二方向上，所述驱动芯片区位于所述显示区域和所述绑定引脚区之间，所述多个绑定引脚组设置于所述绑定引脚区；
所述驱动芯片区设置有沿所述第一方向排布的n个集成电路引脚组，第一个集成电路引脚组至第n个集成电路引脚组沿所述第一方向依次排布，并分别与所述第一个绑定引脚组至第n个所述绑定引脚组连接，所述n个集成电路引脚组被配置为分别与n个集成电路绑定并与所述多条数据线电连接，所述n个驱动引脚组通过引脚连接线分别与对应的所述n个集成电路引脚组连接；所述n个绑定引脚组被配置为分别通过所述n个集成电路引脚组与所述多条数据线电连接。
在示例性实施方式中，所述显示基板还包括：围绕所述显示区域的边框区域，所述边框区域包括所述绑定区域以及在所述第一方向上位于所述显示区域两侧的第一边框区和第二边框区，所述边框区域设置有栅极驱动电路和栅极驱动电路信号线；所述栅极驱动电路信号线包括第一栅极驱动电路信号线和第二栅极驱动电路信号线，所述第一栅极驱动电路信号线由所述第一边框区延伸至所述绑定区域，所述第二栅极驱动电路信号线由所述第二边框区延伸至所述绑定区域；
所述栅极驱动电路包括设置于所述第一边框区的第一栅极驱动电路和设置于所述第二边框区的第二栅极驱动电路，所述第一栅极驱动电路被配置为通过所述第一栅极驱动电路信号线与所述第一个集成电路引脚组电连接，所述第二栅极驱动电路被配置为通过所述第二栅极驱动电路信号线与所述第n个集成电路引脚组电连。
在示例性实施方式中，所述绑定区域还设有第一转接线和第二转接线，所述第一转接线被配置为与所述第一栅极驱动电路信号线和所述第一栅极驱动电路引脚组连接，所述第二转接线被配置为与所述第二栅极驱动电路信号线和所述第二栅极驱动电路引脚组连接。
在示例性实施方式中，所述绑定引脚组中还包括两个电源引脚组，所述电源引脚组被配置为与电源线电连接；
在所述第一方向上，在同一个绑定引脚组中，所述两个电源引脚组分别设置于所述驱动引脚组的两侧，位于驱动引脚组同一侧的电源引脚组和栅极驱动电路引脚组沿所述第一方向排布。
在示例性实施方式中，在同一个绑定引脚组中，在所述第一方向上，位于所述驱动引脚组同一侧的所述电源引脚组包括第一电源引脚组和第二电源引脚组，并且所述第二电源引脚组位于所述第一电源引脚组远离所述驱动引脚组的一侧，所述第一电源引脚组被配置为与第一电源线电连接，所述第二电源引脚组被配置为与第二电源线电连接。
在示例性实施方式中，在所述第一个绑定引脚组中，在所述第一方向上，在所述驱动引脚组远离所述第n个绑定引脚组的一侧，所述第一栅极驱动电路引脚组位于所述第二电源引脚组远离所述第一电源引脚组的一侧，或者所述第一栅极驱动电路引脚组位于所述第一电源引脚组和所述第二电源引脚组之间，或者所述第一栅极驱动电路引脚组位于所述第一电源引脚组和所述驱动引脚组之间；
在所述第n个绑定引脚组中，在所述第一方向上，在所述驱动引脚组远离所述第一个绑定引脚组的一侧，所述第二栅极驱动电路引脚组位于所述第二电源引脚组远离所述第一电源引脚组的一侧，或者所述第二栅极驱动电路引脚组位于所述第一电源引脚组和所述第二电源引脚组之间，或者所述第二 栅极驱动电路引脚组位于所述第一电源引脚组和所述驱动引脚组之间。
第三方面，本公开实施例还提供了一种显示装置，包括上述任一实施例所述的显示面板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中每个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1所示为一种显示装置的结构示意图；
图2所示为一种显示基板的平面结构示意图；
图3所示为一种显示基板的剖面结构示意图；
图4所示为一种像素驱动电路的等效电路示意图；
图5所示为一种像素驱动电路的工作时序图；
图6所示为一种显示面板的结构示意图；
图7所示为一种显示面板中绑定区域的结构示意图；
图8所示为一种显示面板的结构示意图；
图9所示为一种显示面板的结构示意图；
图10所示为一种显示面板的结构示意图；
图11为本公开实施例提供的一种显示面板结构示意图；
图12为本公开一种示例性实施例提供的显示面板结构示意图；
图13a为本公开一种示例性实施例提供的显示面板结构示意图；
图13b为本公开一种示例性实施例提供的显示面板结构示意图；
图14为本公开一种示例性实施例提供的显示面板结构示意图；
图15为本公开一种示例性实施例提供的显示面板结构示意图；
图16为本公开一种示例性实施例提供的显示面板结构示意图；
图17为本公开一种示例性实施例提供的显示面板结构示意图；
图18为本公开一种示例性实施例提供的显示面板结构示意图；
图19为本公开一种示例性实施例提供的显示面板结构示意图；
图20为本公开一种示例性实施例提供的第一个绑定引脚组的放大结构示意图；
图21为本公开实施例提供的一种显示面板结构示意图；
图22为本公开实施例提供的一种显示面板结构示意图；
图23为本公开一种示例性实施例提供的显示面板结构示意图；
图24为本公开一种示例性实施例提供的显示面板结构示意图；
图25所示为本公开一种示例性实施例提供的显示面板中柔性电路板的走线排布示意图；
图26所示为本公开一种示例性实施例提供的显示面板中柔性电路板的走线排布示意图；
图27所示为本公开一种示例性实施例提供的显示面板中柔性电路板的走线排布示意图。
具体实施方式
下文中将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
除非另外定义，本公开实施例公开使用的技术术语或者科学术语应当为 本发明所属领域内具有一般技能的人士所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语一直出该词前面的元件或误检涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者误检。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间件间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以结合具体情况理解上述术语在本发明中的具体含义。
在本公开中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(或称漏电极端子、漏连接区域或漏电极)与源电极(或称源电极端子、源连接区域或源电极)之间具有沟道区，并且电流能够流过漏电极、沟道区以及源电极。在本公开中，沟道区是指电流主要流过的区域。
在本公开中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况下，“源电极”及“漏电极”的功能有时可以互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。栅电极也可以称为控制极。
在本公开中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电 信号的授受，就对其没有特别的限制。“具有某种电作用的元件”例如可以是电极或布线，或者是晶体管等开关元件，或者是电阻器、电感器或电容器等其它功能元件等。
图1所示为一种显示装置的结构示意图，显示基板可以包括时序控制器、数据信号驱动器、扫描信号驱动器、发光信号驱动器和像素阵列，时序控制器分别与数据信号驱动器、扫描信号驱动器和发光信号驱动器连接，数据信号驱动器分别与多个数据信号线(D1到Dn)连接，扫描信号驱动器分别与多个扫描信号线(S1到Sm)连接，发光信号驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括至少一个扫描信号线、至少一个数据信号线、至少一个发光信号线和像素驱动电路。在示例性实施方式中，时序控制器可以将适合于数据信号驱动器的规格的灰度值和控制信号提供到数据信号驱动器，可以将适合于扫描信号驱动器的规格的时钟信号、扫描起始信号等提供到扫描信号驱动器，可以将适合于发光信号驱动器的规格的时钟信号、发射停止信号等提供到发光信号驱动器。数据信号驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据信号驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描信号驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描信号驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光信号驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光信号驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方 式产生发射信号，o可以是自然数。
图2为一种显示基板的平面结构示意图。如图2所示，显示基板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P至少一个包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路和发光器件。第一子像素P1、第二子像素P2和第三子像素P3中的像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向所述发光器件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，像素单元P中可以包括红色(R)子像素、绿色(G)子像素和蓝色(B)子像素。在示例性实施方式中，像素单元中子像素的形状可以是矩形状、菱形、五边形或六边形，三个子像素可以采用水平并列、竖直并列或品字方式排列，本公开在此不做限定。
图3为一种显示基板的剖面结构示意图，示意了OLED显示基板三个子像素的结构。如图3所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存储电容。发光结构层103可以包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301通过过孔与驱动晶体管210的漏电极连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401 和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层303可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。图4为一种像素驱动电路的等效电路示意图。如图4所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，像素驱动电路可以与7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管T1的第二极、第二晶体管T2的第一极、第三晶体管T3的控制极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将初始化电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7 将初始化电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、发光信号线E和初始信号线INIT沿水平方向延伸，第二电源线VSS、第一电源线VDD和数据信号线D沿竖直方向延伸。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图5为一种像素驱动电路的工作时序图。下面通过图4示例的像素驱动电路的工作过程说明一种示例性实施例，图4中的像素驱动电路包括7个晶体管(第一晶体管T1到第七晶体管T7)、1个存储电容C和7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)，7个晶体管均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线 S2的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vd+|Vth|)-Vth]2＝K*[(Vdd-Vd)]2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
图6为一种显示面板的结构示意图。如图6所示，显示面板可以包括显示区域100、位于显示区域100一侧的绑定区域200和位于显示区域100其它侧的边框区域300。显示区域100可以包括规则排列的多个子像素Pxij，子像素可以包括像素驱动电路和发光器件，绑定区域200可以包括将信号线连接至外部驱动装置的绑定电路，边框区域300可以包括栅极驱动电路和向多个子像素传输电压信号的第二电源线VSS。
图7为显示面板中绑定区域的结构示意图。如图6和图7所示，在平行于显示面板的平面内，绑定区域200位于显示区域100的一侧，绑定区域200包括沿着远离显示区域100的方向依次设置的第一扇出区201、弯折区202、复合电路区2001；其中，复合电路区2001可以包括沿着远离弯折区202的方向依次设置的第二扇出区203、防静电区204、驱动芯片区205和绑定电极区206。第一扇出区201包括数据扇出线、第一电源线和第二电源线，数据扇出线位于第一扇出区201的中部，包括多条数据连接线，多条数据连接线被配置为以扇出(Fanout)走线方式连接显示区域100的数据线(Data Line)，第一电源线被配置为连接显示区域100的高电压电源线(VDD)，第二电源线为位于边框区域300的低电压电源线(VSS)。弯折区202包括设置有凹槽的复合绝缘层，被配置为使绑定区域200弯折到显示区域100的背面。第二扇出区203包括扇出走线方式引出的多条数据连接线。防静电区204包括防静电电路，被配置为通过消除静电防止显示面板的静电损伤。驱动芯片区205包括集成电路(Integrated Circuit，简称IC)400，被配置为与多条数据连接线连接。绑定电极区206包括多个绑定焊盘(Bonding Pad)，被配置为与柔性电路板(Flexible Printed Circuit，简称FPC)500绑定连接。在示例性实施方式中，集成电路(Integrate Circuit，简称IC)400可以绑定连接在驱动芯片区205，柔性电路板(Flexible Printed Circuit，简称FPC)500可以绑定连接在绑定电极区206。在示例性实施方式中，集成电路400可以产生用 于驱动子像素所需的驱动信号，并且可以将驱动信号提供给在显示区域100中的子像素。例如，驱动信号可以是控制子像素发光亮度的数据信号。在示例性实施方式中，绑定电极区206可以设置包括多个引脚(PIN)的焊盘，柔性电路板500可以绑定连接到焊盘上。
在示例性实施方式中，如图8所示，弯折区202可以以一曲率弯曲，可以将复合电路区2001的表面反转，即复合电路区2001朝向上方的表面可以通过弯折区202的弯曲转换成朝向下方。在示例性实施方式中，当弯折区202被弯曲时，复合电路区2001可以在显示面板厚度方向上与显示区域100重叠。
在示例性实施方式中，如图9所示，柔性电路板(FPC)500上包括绑定连接区501、主板连接区502，FPC通过绑定连接区501与绑定区域200绑定连接，FPC通过主板连接区502与主板600连接。在示例性实施方式中，FPC与主板之间可以通过板对板(Board-To-Board，简称BTB)连接器连接。在示例性实施方式中，主板上可以设置印刷电路板(Printed Circuit Board，简称PCB)，柔性电路板500可以通过主板连接区502与主板600上的PCB电连接。
在示例性实施方式中，对于大尺寸的显示面板，需要设置多个IC以及多个FPC，多个FPC与分别与多个IC绑定连接，如图10所示，可以设置四个IC分别与四个FPC绑定连接，本公开实施例不限于四个IC和四个FPC。在本公开实施例中，IC和FPC的数量可以根据显示面板尺寸以及功能的需要设置，本公开在此不做限定。
通常情况下，显示面板设有多个栅极驱动电路(GOA)和栅极驱动电路信号线(GOA信号线)，GOA信号线可以包括时钟信号线(例如可以包括CK信号线、CB信号线、STV信号线等)，多个GOA信号线设置于如图10和图6所示显示面板的左右两侧边框，并由左右两侧的边框经由下边框通过绑定引脚组与FPC连接，在显示面板的尺寸比较小的情况下，由于栅极驱动电路的数量相对少，GOA信号线数量也相对较少，多个GOA信号经由PCB板、FPC传输到显示面板左右两侧的GOA信号线中，显示面板的下边框的尺寸可以容纳多个GOA信号线。本公开实施例中，GOA为阵列基板行驱动的简写，英文全称为Gate Driver on Array。
FPC设有多个栅极驱动电路走线(GOA走线)，显示面板设有多个GOA信号线以及与多个GOA信号线连接的绑定引脚，FPC中的多个GOA走线分别与多个绑定引脚绑定连接，实现FPC中GOA走线分别与显示面板中的多个GOA信号线电连接，目前，由很多因素会导致显示面板GOA信号线数量增多，其中一种因素是，随着显示面板的尺寸增大，FPC上的GOA(栅极驱动电路)走线以及显示面板的GOA信号线也随之增多。
在显示面板GOA信号线数量增多的情况下，FPC上栅极驱动电路走线也对应增加，使得FPC在显示面板上沿GOA(栅极驱动电路)走线以及显示面板中与栅极驱动电路连接的绑定引脚沿排布方向的尺寸增大，导致FPC占用显示面板的空间增大，存在显示面板接入FPC的空间不足的问题。
本公开实施例提供一种显示面板，可以包括：
显示基板，包括显示区域和位于所述显示区域一侧的绑定区域；
多个子像素，位于所述显示区域；
多条数据线，位于所述显示区，且与所述多个子像素电连接；
多个绑定引脚组，位于所述绑定区域，所述绑定引脚组包括至少一个驱动引脚组和至少一个触控引脚组，在所述多个绑定引脚组中，所述多个驱动引脚组沿第一方向排布，所述至少一个触控引脚组穿插排布在所述多个驱动引脚组之间，相邻两个驱动引脚组之间设置有至少一个触控引脚组，所述驱动引脚组中的至少部分驱动引脚被配置为与所述多条数据线电连接，所述至少一个触控引脚组被配置为与触控线电连接。
本公开实施例提供的显示面板，至少一个触控引脚组穿插排布在多个驱动引脚组之间，相邻两个驱动引脚组之间设置至少一个触控引脚组，将触控引脚组设置于多个绑定引脚组中间位置，可以充分利用多个绑定引脚组之间的空隙，在很大程度上节省了柔性电路板占用显示面板的空间，克服了现有技术中显示面板接入FPC的空间不足的问题。
如图11所示，本公开实施例提供了一种显示面板，可以包括：
显示基板，包括显示区域AA和位于显示区域AA一侧的绑定区域B1；
多个子像素Pxij，位于显示区域AA；
多条数据线，位于显示区域AA，且与多个子像素Pxij电连接；
多个绑定引脚组41，位于绑定区域B1绑定区域B1，绑定引脚组41包括至少一个驱动引脚组411和至少一个触控引脚组412，在多个绑定引脚组41中，多个驱动引脚组411沿第一方向X排布，至少一个触控引脚组412穿插排布在多个驱动引脚组411之间，相邻两个驱动引脚组411之间设置有至少一个触控引脚组412，驱动引脚组411中的至少部分驱动引脚被配置为与多条数据线电连接，至少一个触控引脚组412被配置为与触控线TP电连接。
在示例性实施方式中，驱动引脚组411中可以包括多个驱动引脚。
在示例性实施方式中，多条数据线至少包括多条数据信号线D，多条数据信号线D可以设置为向多个子像素Pxij提供数据信号。
在示例性实施方式中，如图12、图13a和图13b所示，显示基板还可以包括：围绕显示区域AA的边框区域，边框区域包括绑定区域B1，边框区域设置有栅极驱动电路GOA；
多个绑定引脚组41中的至少两个绑定引脚组41分别包括一个栅极驱动电路引脚组413，栅极驱动电路引脚组413被配置为与栅极驱动电路电连接。
在示例性实施方式中，如图13a和图13b所示，至少两个绑定引脚组的数量为两个，两个绑定引脚组分别包括一个栅极驱动电路引脚组413，在第一方向X上，两个栅极驱动电路引脚组413分别位于两侧的两个绑定引脚组41中。
在示例性实施方式中，多个绑定引脚组41包括n个绑定引脚组41，第一个绑定引脚组41至第n个绑定引脚组41沿第一方向X依次排布，n为大于或者等于2的正整数；如图13a和图13b所示，n可以为4；
两个栅极驱动电路引脚组413包括第一栅极驱动电路引脚组4131和第二栅极驱动电路引脚组4132，第一栅极驱动电路引脚组4131位于第一个绑定引脚组41中，第二栅极驱动电路引脚组4132位于第n个绑定引脚组41中；
在第一个绑定引脚组41中，第一栅极驱动电路引脚组4131位于驱动引脚组411远离第n个绑定引脚组41的一侧，第一栅极驱动电路引脚组4131和触控引脚组412分别位于驱动引脚组411的两侧；在第n个绑定引脚组41 中，第二栅极驱动电路引脚组4132位于驱动引脚组411远离第一个绑定引脚组41的一侧，第二栅极驱动电路引脚组4132和触控引脚组412分别位于驱动引脚组411的两侧。
如图13a和图13b所示，多个绑定引脚组41可以包括沿第一方向X排布的第一绑定引脚组41a、第二绑定引脚组41b、第三绑定引脚组41c和第四绑定引脚组41d，第一绑定引脚组41a、第二绑定引脚组41b、第三绑定引脚组41c和第四绑定引脚组41d分别包括驱动引脚组411a、驱动引脚组411b、驱动引脚组411c、驱动引脚组411d，第一栅极驱动电路引脚组4131位于第一个绑定引脚组41a中，第二栅极驱动电路引脚组4132位于第四个绑定引脚组41d中；在第一个绑定引脚组41a中，第一栅极驱动电路引脚组4131位于驱动引脚组411a远离第四个绑定引脚组41d的一侧，第一栅极驱动电路引脚组4131和触控引脚组412a分别位于驱动引脚组411a的两侧；在第四个绑定引脚组41d中，第二栅极驱动电路引脚组4132位于驱动引脚组411d远离第一个绑定引脚组41a的一侧，第二栅极驱动电路引脚组4132和触控引脚组412d分别位于驱动引脚组411d的两侧。
在示例性实施方式中，如图12至13b图所示，绑定引脚组41中还包括两个电源引脚组414，电源引脚组414被配置为与电源线电连接；
在第一方向X上，在同一个绑定引脚组41中，两个电源引脚组414分别设置于驱动引脚组411的两侧，位于驱动引脚组411同一侧的电源引脚组414和触控引脚组412沿第一方向X排布，位于驱动引脚组411同一侧的电源引脚组414和栅极驱动电路引脚组413沿第一方向X排布。
在示例性实施方式中，如图13a和图13b所示，在同一个绑定引脚组41中，在第一方向X上，位于驱动引脚组411同一侧的电源引脚组414包括第一电源引脚组4141和第二电源引脚组4142，并且第二电源引脚组4142位于第一电源引脚组4141远离驱动引脚组411的一侧，第一电源引脚组4141被配置为与第一电源线PL1电连接，第二电源引脚组4142被配置为与第二电源线PL2电连接。
在示例性实施方式中，如图13a至图15所示，在同一个绑定引脚组41中，在第一方向X上，位于驱动引脚组411两侧的两个第一电源引脚组4141 相对于驱动引脚组411对称，位于驱动引脚组411两侧的两个第二电源引脚组4142相对于驱动引脚组411对称。
在示例性实施方式中，如图13a和图13b所示，在第一个绑定引脚组41中，在第一方向X上，在驱动引脚组411远离第n个绑定引脚组41的一侧，第一栅极驱动电路引脚组4131位于第二电源引脚组4142远离第一电源引脚组4141的一侧，或者如图14所示，第一栅极驱动电路引脚组413位于第一电源引脚组4141和第二电源引脚组4142之间，或者如图15所示，第一栅极驱动电路引脚组4131位于第一电源引脚组4141a和驱动引脚组411a之间；
如图13a和图13b所示，在第n个绑定引脚组41中，在第一方向X上，在驱动引脚组411远离第一个绑定引脚组41的一侧，第二栅极驱动电路引脚组4132位于第二电源引脚组4142远离第一电源引脚组4141的一侧，或者如图14所示，第二栅极驱动电路引脚组4132位于第一电源引脚组4141和第二电源引脚组4142之间，或者如图15所示，第二栅极驱动电路引脚组4132位于第一电源引脚组4141和驱动引脚组411之间。
在示例性实施方式中，如图12至图15所示，在第一方向X上，在同一个绑定引脚组41中，位于驱动引脚组411同一侧的电源引脚组414与触控引脚组412沿第一方向X排布，并且，如图12至图13b所示，触控引脚组412位于第二电源引脚组4142远离第一电源引脚组4141的一侧，或者如图14所示，触控引脚组412位于第一电源引脚组4141和第二电源引脚组4142之间，或者如图19所示，触控引脚组412位于驱动引脚组411和第一电源引脚组4141之间。
在示例性实施方式中，如图16至图18所示，相邻两个驱动引脚组之间设置一个触控引脚组412，并且，如图16所示触控引脚组412可以位于两个第二电源引脚组4142之间，或者如图17所示触控引脚组412可以位于同一个绑定引脚组41中的第一电源引脚组4141和第二电源引脚组4142之间，或者如图18所示触控引脚组412位于同一个绑定引脚组41中的第一电源引脚组4141与驱动引脚组411之间。
在示例性实施方式中，在第一方向X上，第一个绑定引脚组41远离第n个绑定引脚组41的一侧设置有至少一个触控引脚组412，并且在第一个绑定 引脚组远离第n个绑定引脚组的一侧，如图17所示，至少一个触控引脚组412位于第一栅极驱动电路引脚组4131与第二电源引脚组4142之间，或者如图18所示，至少一个触控引脚组412位于第一电源引脚组4141与第二电源引脚组4142之间，或者如图19所示至少一个触控引脚组412位于第一电源引脚组4141与驱动引脚组411之间；
第n个绑定引脚组41远离第一个绑定引脚组41的一侧设置有至少一个触控引脚组；并且在第n个绑定引脚组远离第一个绑定引脚组的一侧，如图17所示，至少一个触控引脚组412位于第二栅极驱动电路引脚组4132与第二电源引脚组4142之间，或者如图18所示，至少一个触控引脚组412位于第一电源引脚组4141与第二电源引脚组4142之间，或者如图19所示，至少一个触控引脚组412位于第一电源引脚组4141与驱动引脚组411之间。
在示例性实施方式中，如图12所示，绑定区域B1可以包括绑定引脚区B10和驱动芯片区B116，在第二方向Y上，驱动芯片区B116位于显示区域AA和绑定引脚区B10之间，多个绑定引脚组41设置于绑定引脚区B116；
驱动芯片区B116设置有沿第一方向X排布的多个集成电路引脚组61，多个集成电路引脚组61被配置为与集成电路绑定并与多条数据线电连接，多个驱动引脚组411通过引脚连接线分别与对应的多个集成电路引脚组61连接；多个绑定引脚组41被配置为分别通过多个集成电路引脚组61与多条数据线电连接。
在示例性实施方式中，如图12至图15多个集成电路引脚组包括n个集成电路引脚组，第一个集成电路引脚组61至第n个集成电路引脚组61沿第一方向X依次排布，并分别与第一个绑定引脚组41至第n个绑定引脚组41连接；栅极驱动电路GOA被配置为通过栅极驱动电路信号线与第一个集成电路引脚组61和第n个集成电路引脚组61电连接。
在示例性实施方式中，如图12至图15所示，边框区域包括在第一方向X上位于显示区域AA两侧的第一边框区B21和第二边框区B22；栅极驱动电路信号线包括第一栅极驱动电路信号线71a和第二栅极驱动电路信号线71b，第一栅极驱动电路信号线71a由第一边框区B21延伸至绑定区域B1，第二栅极驱动电路信号线71b由第二边框区B22延伸至绑定区域B1；
栅极驱动电路GOA包括设置于第一边框区B21的第一栅极驱动电路和设置于第二边框区B22的第二栅极驱动电路，第一栅极驱动电路被配置为通过第一栅极驱动电路信号线71a与第一个集成电路引脚组61a电连接，第二栅极驱动电路被配置为通过第二栅极驱动电路信号线71b与第n个集成电路引脚组61电连接。
在图12至图15中，n可以为4，集成电路引脚组可以包括集成电路引脚组61a、集成电路引脚组61b、集成电路引脚组61c、集成电路引脚组61d。
在示例性实施方式中，如图12至图15所示，绑定区域B1还可以设有第一转接线37a和第二转接线37b，第一转接线37a被配置为与第一栅极驱动电路信号线71a和第一栅极驱动电路引脚组4131连接，第二转接线37b被配置为与第二栅极驱动电路信号线71b和第二栅极驱动电路引脚组4132连接。
在示例性实施方式中，如图12至图15所示，显示面板还可以包括多个测试电路组42，位于绑定区域B1并沿第一方向X排布，在第二方向Y上，多个测试电路组42位于多个绑定引脚组41与显示区域AA之间；多个测试电路组42与多条数据线电连接，每个测试电路组42被配置为在测试阶段与至少一个绑定引脚组41连接。其中，多个测试电路组42可以包括第一个测试电路组42a、第二个测试电路组42b、第三个测试电路组42c和第四个测试电路组。
在示例性实施方式中，在所述显示基板所在平面内，第一方向X与第二方向Y交叉。在示例性实施方式中，在所述显示基板所在平面内，第一方向X与第二方向Y垂直。
如图20所示，为图13a和图13b中第一个绑定引脚组41a的放大结构示意图，在第一个绑定引脚组41中，电源引脚组414(包括第一电源引脚组4141和第二电源引脚组4142)位于驱动引脚组411a的两侧，第一栅极驱动电路391引脚组4131位于驱动引脚组411a远离第四个驱动引脚组41d的一侧，并且电源引脚组414(包括第一电源引脚组4141和第二电源引脚组4142)位于第一栅极驱动电路391引脚组4131与驱动引脚组411a之间，触控引脚组412a位于驱动引脚组411a与第二个绑定引脚组41b之间。在第一方向X上， 位于驱动引脚组411a同一侧包括第一电源引脚组4141a和第二电源引脚组4142a,并且第一电源引脚组4141a位于驱动引脚组411a和第二电源引脚组4142a之间。如图20所示，驱动引脚组411a可以包括沿第一方向排布的多个驱动引脚4110，触控引脚组412a可以包括沿第一方向X排布的多个触控引脚4120，第一栅极驱动电路391引脚组4131可以包括沿第一方向X排布的多个栅极驱动电路引脚4130，第一电源引脚组4141a可以包括至少一个第一电源引脚41410，第二电源引脚组4142a可以包括至少一个第二电源引脚41420，第一电源引脚41410被配置为与第一电源线PL1连接，第二电源引脚41420被配置为与第二电源线PL2连接。
在本公开实施例中，如图12至图15所示，上述n的取值可以为4，绑定区域B1可以包括第一个绑定引脚组41a、第二个绑定引脚组41b、第三个绑定引脚组41c和第四个绑定引脚组41d，相应地驱动引脚组411可以包括第一个驱动引脚组411a、第二个驱动引脚组411b、第三个驱动引脚组411c和第四个驱动引脚组411d；第一电源引脚组4141可以包括第一个第一电源引脚组4141a、第二个第一电源引脚组4141b、第三个第一电源引脚组4141c和第四个第一电源引脚组4141d，第二电源引脚组4142可以包括第一个第二电源引脚组4142a、第二个第二电源引脚组4142b、第三个第二电源引脚组4142c和第四个第二电源引脚组4142d；触控引脚组412可以包括第一个触控引脚组412a、第二个触控引脚组412b、第三个触控引脚组412c和第四个触控引脚组412d。
本公开实施例还提供一种显示面板，如图21和图22所示，包括：
显示基板，包括显示区域AA和位于显示区域AA一侧的绑定区域B1；
多个子像素Pxij，位于显示区域AA；
多条数据线，位于显示区域AA，且与多个子像素Pxij电连接；
多个绑定引脚组41，位于绑定区域B1，绑定引脚组41包括至少一个驱动引脚组411，在多个绑定引脚组41中，多个驱动引脚组411沿第一方向X排布，多个绑定引脚组41中位于两侧的两个绑定引脚组41分别包括一个栅极驱动电路引脚组413，驱动引脚组411中的至少部分驱动引脚被配置为与多条数据线电连接，栅极驱动电路引脚组413被配置为与栅极驱动电路信号 线电连接。
在示例性实施方式中，如图23所示，多个绑定引脚组41可以包括n个绑定引脚组41，第一个绑定引脚组41至第n个绑定引脚组41沿第一方向X依次排布，n为大于或者等于2的正整数；绑定引脚组还可以包括至少一个触控引脚组412，至少一个触控引脚组412穿插排布在n个驱动引脚组411之间，相邻两个驱动引脚组411之间设置有至少一个触控引脚组412，至少一个触控引脚组412被配置为与触控线TP电连接；n的取值可以为4；
两个栅极驱动电路引脚组413可以包括第一栅极驱动电路引脚组4131和第二栅极驱动电路引脚组4132，第一栅极驱动电路引脚组4131位于第一个绑定引脚组41中，第二栅极驱动电路引脚组4132位于第n个绑定引脚组41中；
在第一个绑定引脚组41中，第一栅极驱动电路引脚组4131位于驱动引脚组411远离第n个绑定引脚组41的一侧；在第n个绑定引脚组41中，第二栅极驱动电路引脚组4132位于驱动引脚组411远离第一个绑定引脚组41的一侧。
在示例性实施方式中，如图23所示，在所述第一方向X上，第一栅极驱动电路引脚组4131远离第n个绑定引脚组41的一侧不设置触控引脚组；第二栅极驱动电路引脚组4132远离第一个绑定引脚组41的一侧不设置触控引脚组。
在示例性实施方式中，如图23所示，绑定区域B1包括绑定引脚区B10和驱动芯片区B116，在第二方向Y上，驱动芯片区B116位于显示区域AA和绑定引脚区B10之间，多个绑定引脚组41设置于绑定引脚区B10；
驱动芯片区B116设置有沿第一方向X排布的n个集成电路引脚组61，第一个集成电路引脚组61至第n个集成电路引脚组61沿第一方向X依次排布，并分别与第一个绑定引脚组41至第n个绑定引脚组41连接，n个集成电路引脚组61被配置为分别与n个集成电路绑定并与多条数据线电连接，n个驱动引脚组411通过引脚连接线L0分别与对应的n个集成电路引脚组61连接；n个绑定引脚组41被配置为分别通过n个集成电路引脚组61与多条数据线电连接。
在示例性实施方式中，如图23所示，显示基板还可以包括：围绕显示区域AA的边框区域，边框区域包括绑定区域B1以及在第一方向X上位于显示区域AA两侧的第一边框B21区和第二边框B22区；边框区域设置有栅极驱动电路和栅极驱动电路信号线；栅极驱动电路信号线可以包括第一栅极驱动电路信号线71a和第二栅极驱动电路392信号线71b，第一栅极驱动电路信号线71a由第一边框B21区延伸至绑定区域B1，第二栅极驱动电路392信号线71b由第二边框B22区延伸至绑定区域B1；
栅极驱动电路GOA可以包括设置于第一边框B21区的第一栅极驱动电路391和设置于第二边框B22区的第二栅极驱动电路392，第一栅极驱动电路391被配置为通过第一栅极驱动电路信号线71a与第一个集成电路引脚组61电连接，第二栅极驱动电路392被配置为通过第二栅极驱动电路信号线71b与第n个集成电路引脚组61电连。
在示例性实施方式中，如图23所示，绑定区域B1还设有第一转接线37a和第二转接线37b，第一转接线37a被配置为与第一栅极驱动电路信号线71a和第一栅极驱动电路引脚组4131连接，第二转接线37b被配置为与第二栅极驱动电路信号线71b和第二栅极驱动电路引脚组4132连接。
在示例性实施方式中，绑定引脚组41中还包括两个电源引脚组414，电源引脚组414被配置为与电源线电连接；
在第一方向X上，在同一个绑定引脚组41中，两个电源引脚组414分别设置于驱动引脚组411的两侧，位于驱动引脚组411同一侧的电源引脚组414和栅极驱动电路引脚组413沿第一方向X排布。
在示例性实施方式中，在同一个绑定引脚组41中，在第一方向X上，位于驱动引脚组411同一侧的电源引脚组414包括第一电源引脚组4141和第二电源引脚组4142，并且第二电源引脚组4142位于第一电源引脚组4141远离驱动引脚组411的一侧，第一电源引脚组4141被配置为与第一电源线PL1电连接，第二电源引脚组4142被配置为与第二电源线PL2电连接。
在示例性实施方式中，在示例性实施方式中，如图13a、图13b和图23所示，在第一个绑定引脚组41中，在第一方向X上，在驱动引脚组411远离第n个绑定引脚组41的一侧，第一栅极驱动电路引脚组4131位于第二电 源引脚组4142远离第一电源引脚组4141的一侧，或者如图14所示，第一栅极驱动电路引脚组413位于第一电源引脚组4141和第二电源引脚组4142之间，或者如图15所示，第一栅极驱动电路引脚组4131位于第一电源引脚组4141a和驱动引脚组411a之间；
如图13a和图13b所示，在第n个绑定引脚组41中，在第一方向X上，在驱动引脚组411远离第一个绑定引脚组41的一侧，第二栅极驱动电路引脚组4132位于第二电源引脚组4142远离第一电源引脚组4141的一侧，或者如图14所示，第二栅极驱动电路引脚组4132位于第一电源引脚组4141和第二电源引脚组4142之间，或者如图15所示，第二栅极驱动电路引脚组4132位于第一电源引脚组4141和驱动引脚组411之间。
在本公开实施例中，绑定引脚组41中还可以包括触控引脚组412，触控引脚组412的设置方式可以参考上述实施例以及图12至图19所示，在此不再详细说明。
本公开实施例还提供一种显示面板，如图24所示可以包括：
显示基板，包括显示区域AA和位于显示区域AA一侧的绑定区域B1；
多个子像素Pxij，位于显示区域AA；
多条数据线，位于显示区域AA，且与多个子像素Pxij电连接；
电路区域700，位于绑定区域B1远离显示区域AA的一侧，电路区域700设有沿第一方向X排布的多个柔性电路板，多个柔性电路板设置为与绑定区域B1绑定连接，柔性电路板上设有至少一个驱动走线组C1和至少一个触控走线组C2，在多个柔性电路板中，多个驱动走线组C1沿第一方向X排布，至少一个触控走线组C2穿插排布在多个驱动走线组C1之间，相邻两个驱动走线组C1之间设置至少一个触控走线组C2，驱动走线组C1中的至少部分驱动走线被配置为与多条数据线电连接，至少一个触控走线组C2被配置为与触控线TP电连接。
在示例性实施方式中，如图24所示，多个柔性电路板可以包括n个柔性电路板，第一个柔性电路板FPC1至第n个柔性电路板沿第一方向X依次排布，n为大于或者等于2的正整数；
两个栅极驱动电路走线组C3包括第一栅极驱动电路走线组C31和第二栅极驱动电路走线组C32，第一栅极驱动电路引走线组C31位于第一个柔性电路板FPC1中，第二栅极驱动电路走线组C32位于第n个柔性电路板中；
如图24和图25所示，在第一个柔性电路板FPC1中，第一栅极驱动电路走线组C31位于驱动走线组C1远离第n个柔性电路板的一侧，第一栅极驱动电路走线组C31和触控走线组C2分别位于驱动走线组C1的两侧；在第n个柔性电路板中，第二栅极驱动电路走线组C32位于驱动走线组C1远离第一个柔性电路板FPC1的一侧，第二栅极驱动电路走线组C32和触控走线组C2分别位于驱动走线组C1的两侧。
如图24所示，n的取值可以为4，四个柔性电路板可以包括沿第一方向X排布的第一个柔性电路板FPC1、第二个柔性电路板FPC2、第三个柔性电路板FPC3、第四个柔性电路板FPC4。
在示例性实施方式中，任意一个柔性电路板中还包括两个电源走线组C4；
在第一方向X上，如图24所示，在同一个柔性电路板中，两个电源走线组C4分别设置于驱动走线组C1的两侧，位于驱动走线组C1同一侧的电源走线组C4和触控走线组C2沿第一方向X排布，位于驱动走线组C1同一侧的电源走线组C4和栅极驱动电路走线组C3沿第一方向X排布。
在示例性实施方式中，如图25所示，在同一个柔性电路板中，在第一方向X上，位于驱动走线组C1同一侧的电源走线组C4包括第一电源走线组C41和第二电源走线组C42，并且第二电源走线组C42位于第一电源走线组C41远离驱动走线组C1的一侧。
在示例性实施方式中，如图25所示，在同一个柔性电路板中，在第一方向X上，位于驱动走线组C1两侧的两个第一电源走线组C41相对于驱动走线组C1对称，位于驱动走线组C1两侧的两个第二电源走线组C42相对于驱动走线组C1对称。
在示例性实施方式中，在第一个柔性电路板FPC1中，在第一方向X上，在驱动走线组C1远离第n个柔性电路板的一侧，如图24和图25所示，第一栅极驱动电路走线组C31位于第二电源走线组C42远离第一电源走线组C41的一侧，或者如图26所示，第一栅极驱动电路走线组C31位于第一电 源走线组C41和第二电源走线组C42之间，或者如图27所示，第一栅极驱动电路走线组C31位于第一电源走线组C41和驱动走线组C1之间；
在第n个柔性电路板中，在第一方向X上，在驱动走线组C1远离第一个柔性电路板FPC1的一侧，如图24和图25所示，第二栅极驱动电路走线组C32位于第二电源走线组C42远离第一电源走线组C41的一侧，或者如图26所示，第二栅极驱动电路走线组C32位于第一电源走线组C41和第二电源走线组C42之间，或者如图27所示，第二栅极驱动电路走线组C32位于第一电源走线组C41和驱动走线组C1之间。
在示例性实施方式中，在第一方向X上，在同一个柔性电路板中，位于驱动走线组C1同一侧的电源走线组C41与触控走线组C2沿第一方向X排布，并且，如图24和图25所示，触控走线组C2位于第二电源走线组C42远离第一电源走线组C41的一侧，或者如图26所示，触控走线组C2位于第一电源走线组C41和第二电源走线组C42之间，或者如图27所示，触控走线组C2位于驱动走线组C1和第一电源走线组C41之间。
在本公开实施例中，图25所示的多个柔性电路板可以与图13b中的显示面板绑定连接；图26所示的多个柔性电路板可以与图14中的显示面板绑定连接；图27所示的多个柔性电路板可以与图15中的显示面板绑定连接。
在示例性实施方式中，显示区域100周边设有边框300，在第一方向X上，边框300可以包括第一边框B21和第二边框B22。
在本公开实施例中，与现有技术相比，在柔性电路板的走线排布上进行改进，对显示面板中绑定区域B1的绑定引脚组、柔性电路板的走线以及显示区域边框300的信号线排布方式进行调整，合理利用绑定引脚组之间以及多个柔性电路板之间的空隙，另外，未对柔性电路板中外引脚接合(OLB，Outer Lead Bonding)走线的排布方式调整(即驱动走线组中多个驱动走线的排布方式)，也不需要对驱动芯片以及绑定区域B1绑定焊盘的排布方式进行调整，可以避免因调整驱动芯片而重新定制驱动芯片，可以降低更换驱动芯片的成本，在尽可能小的成本下实现节省柔性电路板占用显示面板空间。
在本公开实施例中，如图12至图13b所示，栅极驱动电路GOA可以与显示区域AA的扫描信号线S电连接，显示面板中的多个子像素Pxij可以通 过如图12所示的单侧驱动，或者通过如图13a和图13b所示的双侧驱动。
在一些示例中，如图12至图15所示，显示基板中，在绑定区域B1远离显示区域AA的一侧还设有多个沿第一方向X排布的多个测试引脚组51，每个测试引脚组可以包括沿第一方向X排布的多个测试引脚。测试引脚配置为在点灯测试阶段中进行信号传输的引脚。
在一些示例中，如图12至图15所示，显示面板还可以包括多个沿第一方向X排布的老化引脚31，多个老化引脚组31可以排布在多个绑定引脚组41之间。其中，老化引脚组31可以被配置为在老化阶段或测试阶段中使用，在结束老化阶段和测试阶段，且绑定引脚组与柔性电路板FPC绑定连接之后，老化引脚组可以作为无效引脚保留在绑定区域B1内，如图13b所示，为图13a中将位于测试引脚组51切除之后的结构示意图。
在一些示例中，如图12至图15所示，在第一方向X上，多个老化引脚组31可以通过第二连接线38电连接。第二连接线38可以至少包括沿第一方向X延伸的线段和沿第二方向Y延伸的线段，其中，沿第一方向X延伸的线段可以位于测试引脚组51远离显示区域AA的一侧。在一些示例中，第二连接线38可以与第一转接线37a和第二转接线37b电连接，以保证信号传输一致性。
在图12至图15所示结构中，B112为绑定区域B1中的弯折区，弯折区B112可以配置为使得绑定区域B1弯折到显示区域AA的背面。
本公开实施例还提供一种显示装置，可以包括上述任一实施例所述的显示面板。显示装置可以为：OLED显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、车载显示器、数码相框或导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
本公开实施例提供的显示面板、显示装置，显示面板中至少一个触控引脚组穿插排布在多个驱动引脚组之间，相邻两个驱动引脚组之间设置至少一个触控引脚组，将触控引脚组设置于多个绑定引脚组中间位置，可以充分利用多个绑定引脚组之间的空隙，在很大程度上节省了柔性电路板占用显示面板的空间，克服了现有技术中显示面板接入FPC的空间不足的问题。
本公开实施例附图只涉及本公开实施例涉及到的结构，其他结构可参考 通常设计。
在不冲突的情况下，本发明的实施例即实施例中的特征可以相互组合以得到新的实施例。
虽然本公开实施例所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (22)

  1. 一种显示面板，包括：
    显示基板，包括显示区域和位于所述显示区域一侧的绑定区域；
    多个子像素，位于所述显示区域；
    多条数据线，位于所述显示区域，且与所述多个子像素电连接；
    多个绑定引脚组，位于所述绑定区域，所述绑定引脚组包括至少一个驱动引脚组和至少一个触控引脚组，在所述多个绑定引脚组中，所述多个驱动引脚组沿第一方向排布，所述至少一个触控引脚组穿插排布在所述多个驱动引脚组之间，相邻两个驱动引脚组之间设置有至少一个触控引脚组，所述驱动引脚组中的至少部分驱动引脚被配置为与所述多条数据线电连接，所述至少一个触控引脚组被配置为与触控线电连接。
  2. 根据权利要求1所述的显示面板，其中，所述显示基板还包括：围绕所述显示区域的边框区域，所述边框区域包括所述绑定区域，所述边框区域设置有栅极驱动电路；
    所述多个绑定引脚组中的至少两个绑定引脚组包括栅极驱动电路引脚组，所述栅极驱动电路引脚组被配置为与所述栅极驱动电路电连接。
  3. 根据权利要求2所述的显示面板，其中，所述至少两个绑定引脚组的数量为两个，所述两个绑定引脚组分别包括一个栅极驱动电路引脚组，在所述第一方向上，所述两个栅极驱动电路引脚组分别位于两侧的两个绑定引脚组中。
  4. 根据权利要求3所述的显示面板，其中，所述多个绑定引脚组包括n个绑定引脚组，第一个绑定引脚组至第n个绑定引脚组沿所述第一方向依次排布，n为大于或者等于2的正整数；
    所述两个栅极驱动电路引脚组包括第一栅极驱动电路引脚组和第二栅极驱动电路引脚组，所述第一栅极驱动电路引脚组位于所述第一个绑定引脚组中，所述第二栅极驱动电路引脚组位于所述第n个绑定引脚组中；
    在所述第一个绑定引脚组中，所述第一栅极驱动电路引脚组位于所述驱动引脚组远离所述第n个绑定引脚组的一侧，所述第一栅极驱动电路引脚组 和所述触控引脚组分别位于所述驱动引脚组的两侧；在第n个绑定引脚组中，所述第二栅极驱动电路引脚组位于所述驱动引脚组远离所述第一个绑定引脚组的一侧，所述第二栅极驱动电路引脚组和所述触控引脚组分别位于所述驱动引脚组的两侧。
  5. 根据权利要求4所述的显示面板，其中，所述绑定引脚组中还包括两个电源引脚组，所述电源引脚组被配置为与电源线电连接；
    在所述第一方向上，在同一个绑定引脚组中，所述两个电源引脚组分别设置于所述驱动引脚组的两侧，位于所述驱动引脚组同一侧的电源引脚组和触控引脚组沿所述第一方向排布，位于所述驱动引脚组同一侧的电源引脚组和栅极驱动电路引脚组沿所述第一方向排布。
  6. 根据权利要求5所述的显示面板，其中，在同一个绑定引脚组中，在所述第一方向上，位于所述驱动引脚组同一侧的所述电源引脚组包括第一电源引脚组和第二电源引脚组，并且所述第二电源引脚组位于所述第一电源引脚组远离所述驱动引脚组的一侧，所述第一电源引脚组被配置为与第一电源线电连接，所述第二电源引脚组被配置为与第二电源线电连接。
  7. 根据权利要求6所述的显示面板，其中，在同一个绑定引脚组中，在所述第一方向上，位于所述驱动引脚组两侧的两个第一电源引脚组相对于所述驱动引脚组对称，位于所述驱动引脚组两侧的两个第二电源引脚组相对于所述驱动引脚组对称。
  8. 根据权利要求6所述的显示面板，其中，在所述第一个绑定引脚组中，在所述第一方向上，在所述驱动引脚组远离所述第n个绑定引脚组的一侧，所述第一栅极驱动电路引脚组位于所述第二电源引脚组远离所述第一电源引脚组的一侧，或者所述第一栅极驱动电路引脚组位于所述第一电源引脚组和所述第二电源引脚组之间，或者所述第一栅极驱动电路引脚组位于所述第一电源引脚组和所述驱动引脚组之间；
    在所述第n个绑定引脚组中，在所述第一方向上，在所述驱动引脚组远离所述第一个绑定引脚组的一侧，所述第二栅极驱动电路引脚组位于所述第二电源引脚组远离所述第一电源引脚组的一侧，或者所述第二栅极驱动电路引脚组位于所述第一电源引脚组和所述第二电源引脚组之间，或者所述第二 栅极驱动电路引脚组位于所述第一电源引脚组和所述驱动引脚组之间。
  9. 根据权利要求6所述的显示面板，其中，在所述第一方向上，在同一个绑定引脚组中，位于所述驱动引脚组同一侧的电源引脚组与触控引脚组沿所述第一方向排布，并且，所述触控引脚组位于所述第二电源引脚组远离所述第一电源引脚组的一侧，或者所述触控引脚组位于所述第一电源引脚组和所述第二电源引脚组之间，或者所述触控引脚组位于所述驱动引脚组和所述第一电源引脚组之间。
  10. 根据权利要求6所述的显示面板，其中，相邻两个驱动引脚组之间设置一个触控引脚组，并且，所述触控引脚组位于两个第二电源引脚组之间，或者所述触控引脚组位于同一个绑定引脚组中的所述第一电源引脚组和所述第二电源引脚组之间，或者所述触控引脚组位于同一个绑定引脚组中的所述第一电源引脚组与所述驱动引脚组之间。
  11. 根据权利要求6所述的显示面板，其中，在所述第一方向上，所述第一个绑定引脚组远离所述第n个绑定引脚组的一侧设置有至少一个触控引脚组，并且在所述第一个绑定引脚组远离所述第n个绑定引脚组的一侧，所述至少一个触控引脚组位于所述第一栅极驱动电路引脚组与所述第二电源引脚组之间，或者所述至少一个触控引脚组位于所述第一电源引脚组与所述第二电源引脚组之间，或者所述至少一个触控引脚组位于所述第一电源引脚组与所述驱动引脚组之间；
    所述第n个绑定引脚组远离所述第一个绑定引脚组的一侧设置有至少一个触控引脚组；并且在所述第n个绑定引脚组远离所述第一个绑定引脚组的一侧，所述至少一个触控引脚组位于所述第二栅极驱动电路引脚组与所述第二电源引脚组之间，或者所述至少一个触控引脚组位于所述第一电源引脚组与所述第二电源引脚组之间，或者所述至少一个触控引脚组位于所述第一电源引脚组与所述驱动引脚组之间。
  12. 根据权利要求4所述的显示面板，其中，所述绑定区域包括绑定引脚区和驱动芯片区，在第二方向上，所述驱动芯片区位于所述显示区域和所述绑定引脚区之间，所述多个绑定引脚组设置于所述绑定引脚区；
    所述驱动芯片区设置有沿所述第一方向排布的多个集成电路引脚组，所 述多个集成电路引脚组被配置为与集成电路绑定并与所述多条数据线电连接，所述多个驱动引脚组通过引脚连接线分别与对应的所述多个集成电路引脚组连接；所述多个绑定引脚组被配置为分别通过所述多个集成电路引脚组与所述多条数据线电连接。
  13. 根据权利要求12所述的显示面板，其中，所述多个集成电路引脚组包括n个集成电路引脚组，第一个集成电路引脚组至第n个集成电路引脚组沿所述第一方向依次排布，并分别与所述第一个绑定引脚组至第n个所述绑定引脚组连接；所述栅极驱动电路被配置为通过栅极驱动电路信号线与所述第一个集成电路引脚组和第n个集成电路引脚组电连接。
  14. 根据权利要求13所述的显示面板，其中，所述边框区域包括在所述第一方向上位于所述显示区域两侧的第一边框区和第二边框区；所述栅极驱动电路信号线包括第一栅极驱动电路信号线和第二栅极驱动电路信号线，所述第一栅极驱动电路信号线由所述第一边框区延伸至所述绑定区域，所述第二栅极驱动电路信号线由所述第二边框区延伸至所述绑定区域；
    所述栅极驱动电路包括设置于所述第一边框区的第一栅极驱动电路和设置于所述第二边框区的第二栅极驱动电路，所述第一栅极驱动电路被配置为通过所述第一栅极驱动电路信号线与所述第一个集成电路引脚组电连接，所述第二栅极驱动电路被配置为通过所述第二栅极驱动电路信号线与所述第n个集成电路引脚组电连接。
  15. 根据权利要求14所述的显示面板，其中，所述绑定区域还设有第一转接线和第二转接线，所述第一转接线被配置为与所述第一栅极驱动电路信号线和所述第一栅极驱动电路引脚组连接，所述第二转接线被配置为与所述第二栅极驱动电路信号线和所述第二栅极驱动电路引脚组连接。
  16. 根据权利要求1至15任一项所述的显示面板，其中，所述绑定区域还包括多个测试电路组，位于所述绑定区域并沿第一方向排布，在第二方向上，所述多个测试电路组位于所述多个绑定引脚组与所述显示区域之间；所述多个测试电路组与所述多条数据线电连接，每个测试电路组被配置为在测试阶段与至少一个绑定引脚组连接；所述第一方向和所述第二方向交叉。
  17. 一种显示面板，包括：
    显示基板，包括显示区域和位于所述显示区域一侧的绑定区域；
    多个子像素，位于所述显示区域；
    多条数据线，位于所述显示区域，且与所述多个子像素电连接；
    多个绑定引脚组，位于所述绑定区域，所述绑定引脚组包括至少一个驱动引脚组，在所述多个绑定引脚组中，所述多个驱动引脚组沿第一方向排布，所述多个绑定引脚组中位于两侧的两个绑定引脚组分别包括一个栅极驱动电路引脚组，所述驱动引脚组中的至少部分驱动引脚被配置为与所述多条数据线电连接，所述栅极驱动电路引脚组被配置为与栅极驱动电路信号线电连接。
  18. 根据权利要求17所述的显示面板，其中，所述多个绑定引脚组包括n个绑定引脚组，第一个绑定引脚组至第n个绑定引脚组沿所述第一方向依次排布，n为大于或者等于2的正整数；所述绑定引脚组还包括至少一个触控引脚组，所述至少一个触控引脚组穿插排布在所述n个驱动引脚组之间，相邻两个驱动引脚组之间设置有至少一个触控引脚组，所述至少一个触控引脚组被配置为与触控线电连接；
    所述两个栅极驱动电路引脚组包括第一栅极驱动电路引脚组和第二栅极驱动电路引脚组，所述第一栅极驱动电路引脚组位于所述第一个绑定引脚组中，所述第二栅极驱动电路引脚组位于所述第n个绑定引脚组中；
    在所述第一个绑定引脚组中，所述第一栅极驱动电路引脚组位于所述驱动引脚组远离所述第n个绑定引脚组的一侧；在第n个绑定引脚组中，所述第二栅极驱动电路引脚组位于所述驱动引脚组远离所述第一个绑定引脚组的一侧。
  19. 根据权利要求18所述的显示面板，其中，在所述第一方向上，所述第一栅极驱动电路引脚组远离所述第n个绑定引脚组的一侧不设置触控引脚组；所述第二栅极驱动电路引脚组远离所述第一个绑定引脚组的一侧不设置触控引脚组。
  20. 根据权利要求18所述的显示面板，其中，所述绑定区域包括绑定引脚区和驱动芯片区，在第二方向上，所述驱动芯片区位于所述显示区域和所述绑定引脚区之间，所述多个绑定引脚组设置于所述绑定引脚区；
    所述驱动芯片区设置有沿所述第一方向排布的n个集成电路引脚组，第一个集成电路引脚组至第n个集成电路引脚组沿所述第一方向依次排布，并分别与所述第一个绑定引脚组至第n个所述绑定引脚组连接，所述n个集成电路引脚组被配置为分别与n个集成电路绑定并与所述多条数据线电连接，所述n个驱动引脚组通过引脚连接线分别与对应的所述n个集成电路引脚组连接；所述n个绑定引脚组被配置为分别通过所述n个集成电路引脚组与所述多条数据线电连接。
  21. 根据权利要求20所述的显示面板，其中，所述显示基板还包括：围绕所述显示区域的边框区域，所述边框区域包括所述绑定区域以及在所述第一方向上位于所述显示区域两侧的第一边框区和第二边框区，所述边框区域设置有栅极驱动电路和栅极驱动电路信号线；所述栅极驱动电路信号线包括第一栅极驱动电路信号线和第二栅极驱动电路信号线，所述第一栅极驱动电路信号线由所述第一边框区延伸至所述绑定区域，所述第二栅极驱动电路信号线由所述第二边框区延伸至所述绑定区域；
    所述栅极驱动电路包括设置于所述第一边框区的第一栅极驱动电路和设置于所述第二边框区的第二栅极驱动电路，所述第一栅极驱动电路被配置为通过所述第一栅极驱动电路信号线与所述第一个集成电路引脚组电连接，所述第二栅极驱动电路被配置为通过所述第二栅极驱动电路信号线与所述第n个集成电路引脚组电连。
  22. 一种显示装置，包括如权利要求1至16任一项所述的显示显示面板，或者包括如权利要求17至21任一项所述的显示面板。
PCT/CN2023/080321 2022-12-01 2023-03-08 显示面板和显示装置 Ceased WO2024113531A1 (zh)

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116249400B (zh) * 2022-12-01 2026-02-13 京东方科技集团股份有限公司 显示基板及显示装置
CN119937830B (zh) * 2025-01-22 2026-04-03 京东方科技集团股份有限公司 一种显示面板、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109102781A (zh) * 2018-08-28 2018-12-28 武汉天马微电子有限公司 一种显示面板及显示装置
CN109917959A (zh) * 2019-02-28 2019-06-21 上海天马微电子有限公司 显示装置及其制作方法
CN110908544A (zh) * 2019-05-13 2020-03-24 友达光电股份有限公司 触控显示装置
CN113380864A (zh) * 2021-05-31 2021-09-10 京东方科技集团股份有限公司 显示装置及母板
CN115004370A (zh) * 2020-10-27 2022-09-02 京东方科技集团股份有限公司 显示面板及其制备方法、显示装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100479184C (zh) * 2007-06-08 2009-04-15 信利半导体有限公司 有机电致发光显示器检查线的布线方法
KR100924142B1 (ko) * 2008-04-01 2009-10-28 삼성모바일디스플레이주식회사 평판표시장치, 이의 에이징 방법 및 점등 테스트 방법
KR101527971B1 (ko) * 2008-07-21 2015-06-10 삼성디스플레이 주식회사 유기전계발광 표시 장치
KR101930846B1 (ko) * 2011-12-30 2018-12-20 삼성디스플레이 주식회사 디스플레이 장치의 에이징 시스템과, 이를 이용한 에이징 방법
KR102750445B1 (ko) * 2016-12-30 2025-01-03 엘지디스플레이 주식회사 터치 내장형 표시장치
CN107703664A (zh) * 2017-09-27 2018-02-16 武汉华星光电技术有限公司 内嵌式触控面板
CN107908052A (zh) * 2017-11-06 2018-04-13 深圳市华星光电技术有限公司 液晶面板结构
CN108761853A (zh) * 2018-04-08 2018-11-06 深圳市华星光电半导体显示技术有限公司 一种液晶显示面板的点灯检测装置及方法
JP7269055B2 (ja) * 2019-03-25 2023-05-08 株式会社ジャパンディスプレイ 表示装置
KR102906050B1 (ko) * 2019-12-31 2025-12-29 엘지디스플레이 주식회사 인-셀(In-cell)터치 유기발광다이오드 표시 장치 및 그 검사 방법
CN114667504B (zh) * 2020-10-22 2025-09-05 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
KR20220078777A (ko) * 2020-12-03 2022-06-13 삼성디스플레이 주식회사 표시 장치
CN112684945B (zh) * 2021-01-08 2022-05-17 武汉华星光电半导体显示技术有限公司 显示面板、触控测试方法及电子设备
CN113270055B (zh) * 2021-05-27 2022-11-01 深圳市华星光电半导体显示技术有限公司 显示面板及测试装置
CN113964109A (zh) * 2021-10-19 2022-01-21 成都京东方光电科技有限公司 显示基板及其制备方法、显示装置
CN115166317A (zh) * 2022-09-01 2022-10-11 北京京瀚禹电子工程技术有限公司 一种直插固态继电器老化座装置
CN115312577B (zh) * 2022-09-16 2026-01-23 京东方科技集团股份有限公司 显示母板及其检测方法、显示基板和显示装置
CN116249400B (zh) * 2022-12-01 2026-02-13 京东方科技集团股份有限公司 显示基板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109102781A (zh) * 2018-08-28 2018-12-28 武汉天马微电子有限公司 一种显示面板及显示装置
CN109917959A (zh) * 2019-02-28 2019-06-21 上海天马微电子有限公司 显示装置及其制作方法
CN110908544A (zh) * 2019-05-13 2020-03-24 友达光电股份有限公司 触控显示装置
CN115004370A (zh) * 2020-10-27 2022-09-02 京东方科技集团股份有限公司 显示面板及其制备方法、显示装置
CN113380864A (zh) * 2021-05-31 2021-09-10 京东方科技集团股份有限公司 显示装置及母板

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4496455A4

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