WO2024113802A1 - 存储器、电子设备及存储器的制备方法 - Google Patents

存储器、电子设备及存储器的制备方法 Download PDF

Info

Publication number
WO2024113802A1
WO2024113802A1 PCT/CN2023/102773 CN2023102773W WO2024113802A1 WO 2024113802 A1 WO2024113802 A1 WO 2024113802A1 CN 2023102773 W CN2023102773 W CN 2023102773W WO 2024113802 A1 WO2024113802 A1 WO 2024113802A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
capacitor
memory
layer
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/102773
Other languages
English (en)
French (fr)
Inventor
李靖宇
景蔚亮
殷士辉
李文魁
王正波
廖恒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to KR1020257017546A priority Critical patent/KR20250093562A/ko
Priority to EP23895966.2A priority patent/EP4618710A4/en
Publication of WO2024113802A1 publication Critical patent/WO2024113802A1/zh
Priority to US19/217,400 priority patent/US20250285658A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/10—Arrangements for interconnecting storage elements electrically, e.g. by wiring for interconnecting capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2275—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/312—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with a bit line higher than the capacitor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/50—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

Definitions

  • the present application relates to the field of semiconductor storage technology, and in particular to a memory, an electronic device, a method for preparing a memory, and a method for preparing a storage array chip.
  • FIG. 1A, FIG. 1B, FIG. 1C and FIG. 2 increases the storage density by 3D stacking the storage array vertically upward on the substrate.
  • the 3D memory includes not only a storage array for storing data, but also a control circuit for controlling the reading and writing of the storage array.
  • the control circuit may be referred to as a CMOS peripheral circuit.
  • CMOS next Array CnA
  • This structure is based on the manufacturing process of a two-dimensional (2-dimensional, 2D) planar structure chip, and integrates the control circuit and the memory array on the same surface of the same chip and arranges them in parallel, wherein the memory array is stacked upward perpendicular to the substrate to form a 3D structure.
  • the 3D memory structure of CMOS under Array (CuA) is shown. This structure integrates the control circuit under the memory array. During the preparation process, the control circuit is prepared first, and then the memory array is prepared above the control circuit, and 3D stacking is performed upward to achieve high-density storage.
  • CuA CMOS under Array
  • the manufacturing of the memory array includes a high-temperature process (such as the crystallization of Si needs to be performed at a high temperature), and this high temperature will affect the performance of the control circuit formed below, for example, reducing the transmission speed of the control circuit.
  • a high-temperature process such as the crystallization of Si needs to be performed at a high temperature
  • the preparation process shown in FIG. 2 can be understood as the incompatibility between the memory array manufacturing process and the CMOS peripheral circuit manufacturing process. Therefore, although the structure shown in FIG. 2 can reduce the two-dimensional size of the memory device, it will limit the performance of the memory device.
  • the present application provides a memory, an electronic device, a method for preparing a memory, and a method for preparing a memory array.
  • the main purpose is to provide a structure for bonding a memory array chip and a control circuit chip together, which can not only reduce the two-dimensional area of the chip, but also solve the problem of process incompatibility.
  • the present application provides a memory, which may include a memory array chip and a control circuit chip, the memory array chip includes a first substrate, a plurality of memory cells formed on one side of the first substrate, each memory cell includes a transistor and at least one capacitor electrically connected to the transistor; the control circuit chip includes a second substrate, a circuit structure formed on one side of the second substrate, the circuit structure is used to control the reading and writing of the plurality of memory cells; the plurality of memory cells and the circuit structure face each other and are electrically connected through a bonding structure formed between the plurality of memory cells and the circuit structure; and the transistor and the at least one capacitor are stacked along a direction perpendicular to the first substrate, and the transistor is arranged close to the bonding structure relative to the at least one capacitor.
  • the memory array chip includes a first substrate, a plurality of memory cells formed on one side of the first substrate, each memory cell includes a transistor and at least one capacitor electrically connected to the transistor;
  • the control circuit chip includes a second substrate, a circuit
  • the memory involved in the present application integrates multiple storage units in a storage array chip, and integrates a circuit structure for controlling the reading and writing of the storage units in another control circuit chip.
  • the two chips are then bonded together via a bonding structure, that is, the interconnection between the storage units and the circuit structure is achieved through the bonding structure.
  • the process used to prepare the multiple memory cells may be incompatible with the process used to prepare the circuit structure.
  • the phenomenon that process incompatibility leads to performance impact between devices, that is, the 3D memory architecture provided in this application can achieve process decoupling of the storage array chip and the control circuit chip in the preparation process.
  • transistors and capacitors are stacked in a direction perpendicular to the first substrate, so that more memory units can be integrated on a unit area of the first substrate, thereby improving the storage density; and, the memory array chip and the control circuit chip are arranged in a 3D stack.
  • the increase in the number of stacking layers of the memory array chip will not lead to a larger two-dimensional area of the entire chip stacking structure. Therefore, the 3D memory structure provided in the present application will not increase the two-dimensional area of the chip while improving the storage density.
  • a first solder joint is formed on a side of the plurality of storage units facing away from the first substrate, a second solder joint is formed on a side of the circuit structure facing away from the second substrate, and the first solder joint and the second solder joint are bonded to form a bonding structure.
  • the first solder joint on the memory array chip and the second solder joint on the control circuit chip can be bonded together to form a memory with a multi-chip stacking structure.
  • the bonding structure is manufactured using a hybrid bonding process.
  • a first conductive channel perpendicular to the first substrate is disposed at the periphery of at least one capacitor, and each capacitor is electrically connected to the bonding structure through the first conductive channel.
  • a conductive channel can be used to connect the capacitor to the bonding structure.
  • a conductive channel as an electrical connection structure is not only simple in structure but also easy to implement in process.
  • each storage unit includes a plurality of capacitors, each capacitor including a first capacitor electrode, a capacitor layer, and a second capacitor electrode; multiple dielectric layers and multiple conductive layers are alternately stacked on the first substrate in a direction perpendicular to the first substrate; the second capacitor electrode penetrates the alternately stacked multiple dielectric layers and multiple conductive layers to form a common second capacitor electrode for multiple capacitors; the capacitor layer penetrates the alternately stacked multiple dielectric layers and multiple conductive layers to form a common capacitor layer for multiple capacitors, and the common capacitor layer surrounds the common second capacitor electrode; at least a portion of the conductive layer surrounding the periphery of the capacitor layer forms a first capacitor electrode; and two adjacent first capacitor electrodes in a direction perpendicular to the first substrate are isolated by a dielectric layer.
  • the second capacitor electrodes and the capacitor layers of the multiple capacitors can be shared, which not only simplifies the preparation process, but also simplifies the structure and improves the storage density.
  • first capacitor electrodes of a plurality of capacitors arranged parallel to the first substrate are connected in one piece.
  • a conductive layer parallel to the first substrate can be formed, and then multiple holes can be punched in the conductive layer, and each hole is filled with a capacitor material and another capacitor electrode material.
  • the capacitor electrodes of multiple capacitors parallel to the first substrate are connected as a whole, that is, a conductive layer parallel to the first substrate.
  • multiple conductive layers are arranged in a stepped manner along a direction away from the first substrate, and in two adjacent conductive layers, the orthographic projection of the conductive layer away from the first substrate on the first substrate is located within the boundary of the orthographic projection of the conductive layer close to the first substrate on the first substrate; the first conductive channel is located at the edge of the conductive layer.
  • the multi-layer conductive layers are arranged in a stepped manner, so that space can be reserved for the conductive channel connected to the lower conductive layer (the conductive layer close to the first substrate).
  • the first conductive channel as the electrical connection structure is arranged at the edge of the conductive layer to make full use of the edge space of the conductive layer, so that the interconnection structure between the capacitor and the bonding structure will not be complicated, thereby improving the storage density.
  • a side of the transistor close to the bonding structure has a second conductive channel perpendicular to the first substrate, and the transistor is electrically connected to the bonding structure through the second conductive channel.
  • the memory array chip further includes: a first electrode line and a second electrode line, the first electrode line is electrically connected to the gate of the transistor, the second electrode line is electrically connected to the first electrode of the transistor, and the second electrode of the transistor is electrically connected to the capacitor.
  • the first electrode line may be a word line WL
  • the second electrode line may be a bit line BL.
  • the transistor is turned on and off through the word line WL, and the memory cell is read and written through the bit line BL.
  • the first electrode and the second electrode of the transistor are arranged in a direction perpendicular to the first substrate, the channel layer of the transistor is located between the first electrode and the second electrode, and the first electrode is arranged away from the capacitor relative to the second electrode, the second electrode line shares the same electrode layer with the first electrode, and the second electrode line is electrically connected to the bonding structure through a second conductive channel perpendicular to the first substrate.
  • the transistor Since the transistor is arranged on a side away from the first substrate, the transistor can be electrically connected to the bonding structure through a conductive channel with a simple structure.
  • the transistor is a gate-all-around transistor.
  • the first electrode and the second electrode of the transistor are arranged in a direction perpendicular to the first substrate, the channel layer of the transistor is located between the first electrode and the second electrode, the gate surrounds the channel layer, and the gate and the channel layer are isolated by a gate dielectric layer, thus forming a ring-gate transistor.
  • the memory array chip is a DRAM memory array chip, or the memory array chip is a ferroelectric memory array chip.
  • the present application also provides a method for preparing a memory, the method comprising:
  • a memory array chip and a control circuit chip are provided.
  • the memory array chip comprises a first substrate, a plurality of memory cells formed on one side of the first substrate, each memory cell comprises a transistor and at least one capacitor electrically connected to the transistor, and a first solder joint is provided on a side of the plurality of memory cells away from the first substrate.
  • the control circuit chip comprises a second substrate, a circuit structure formed on one side of the second substrate, and a second solder joint is provided on a side of the circuit structure away from the second substrate.
  • the multiple storage cells and the circuit structure are oriented toward each other, and the first solder joint is bonded to the second solder joint to form a bonding structure connecting the storage array chip and the control circuit chip, so that the circuit structure controls the reading and writing of the multiple storage cells through the bonding structure.
  • the storage unit and the circuit structure are not integrated in the same chip, but are integrated in different chips respectively to form an independent storage array chip and control circuit chip. Then, the storage array chip and the control circuit chip are bonded to realize the control circuit's control over the reading and writing of the storage unit.
  • incompatible and mutually non-restrictive process methods can be used. In this way, not only will the process methods not interfere with each other, but the processes will also not affect each other's working performance.
  • a hybrid bonding process is used to bond the first solder joint and the second solder joint.
  • the bonding temperature is less than or equal to 450° C.
  • the bonding temperature is less than or equal to 400° C.
  • the bonding temperature is not higher than 450° C., the performance of the storage array chip and the performance of the control circuit chip will basically not be affected.
  • the present application also provides a method for preparing a memory array chip, the method comprising:
  • a transistor is formed on a side of at least one capacitor away from the substrate, and each memory cell in the memory array chip includes at least one capacitor and a transistor;
  • a first conductive channel perpendicular to the substrate is formed at the periphery of at least one capacitor, and a second conductive channel perpendicular to the substrate is formed at a side of the transistor facing away from the substrate;
  • a solder joint is formed on a side of the memory cell facing away from the substrate, such that at least one capacitor is electrically connected to the solder joint through a first conductive path, and the transistor is electrically connected to the solder joint through a second conductive path.
  • capacitors and transistors are stacked in a direction perpendicular to the substrate, so that more storage units can be formed per unit area of the substrate, thereby improving the storage density; the capacitors are arranged closer to the substrate than the transistors, the capacitors are electrically connected to the solder joints through a conductive channel with a simple structure, and the transistors are also electrically connected to the solder joints through a conductive channel with a simple structure.
  • forming at least one capacitor on a substrate includes: alternately stacking multiple dielectric layers and multiple conductive layers on the substrate; opening through holes that penetrate the multiple dielectric layers and the multiple conductive layers; sequentially filling the through holes with capacitor materials and electrode materials to form capacitor layers and capacitor electrodes in the through holes, wherein the capacitor layers are formed between the capacitor electrodes and the side walls of the through holes to obtain multiple capacitors, wherein the capacitor layers form a common capacitor layer for the multiple capacitors, the capacitor electrodes form a common second capacitor electrode for the multiple capacitors, and at least a portion of the conductive layer surrounding the capacitor layer forms a first capacitor electrode for the capacitor.
  • the capacitors in the memory cell are arranged close to the substrate, and the capacitor layers of multiple capacitors and one of the capacitor electrodes are respectively shared, which can simplify the process structure, reduce the area of each memory cell, and improve the storage density.
  • the preparation method further includes: etching the edges of the multiple dielectric layers and the multiple conductive layers, and arranging the multiple conductive layers in a stepped manner along a direction away from the substrate, and in two adjacent conductive layers, the orthographic projection of the conductive layer away from the substrate on the substrate is located within the boundary of the orthographic projection of the conductive layer close to the substrate on the substrate.
  • This design is to facilitate the electrical connection of the capacitor to the bonding structure through the conductive channel.
  • the preparation method further includes: setting a first conductive channel at the edge of each conductive layer so that the conductive layer can be electrically connected to the solder joint through the first conductive channel.
  • the present application also provides an electronic device, which includes a processor and a memory in any of the above implementations, the processor is electrically connected to the memory, and the memory is used to store data generated by the processor.
  • the electronic device provided in the embodiment of the present application includes the memory in any of the above-mentioned implementation methods. Therefore, the electronic device provided in the embodiment of the present application and the memory of the above-mentioned technical solution can solve the same technical problems and achieve the same expected effects.
  • FIGS. 1A to 1C are schematic diagrams of the structure of a CMOS next Array (CnA) 3D memory in the related art
  • FIG2 is a schematic diagram of the structure of a CMOS under Array (CuA) 3D memory in the related art
  • FIG3 is a circuit diagram of an electronic device provided in an embodiment of the present application.
  • FIG4 is a simplified circuit diagram of a memory provided in an embodiment of the present application.
  • FIG5 is a circuit diagram of a memory provided in an embodiment of the present application.
  • FIG6 is a schematic diagram of how to manufacture a memory according to an embodiment of the present application.
  • FIG7 is a process structure diagram of a memory provided in an embodiment of the present application.
  • FIG8A is a process structure diagram of a control circuit chip provided in an embodiment of the present application.
  • FIG8B is a process structure diagram of a memory array chip provided in an embodiment of the present application.
  • FIG8C is a process structure diagram of a memory provided in an embodiment of the present application.
  • FIG9 is a circuit diagram of a storage unit in a memory provided by an embodiment of the present application.
  • FIG10 is a circuit diagram of a memory array chip provided in an embodiment of the present application.
  • FIG11A is a process structure diagram of a memory array chip provided in an embodiment of the present application.
  • FIG11B is an enlarged view of point A in FIG11A ;
  • FIG11C is a process structure diagram of a memory cell provided in an embodiment of the present application.
  • FIG11D is a process structure diagram of a memory array chip provided in an embodiment of the present application.
  • FIG12A is a three-dimensional view of a transistor provided in an embodiment of the present application.
  • Fig. 12B is a cross-sectional view taken along line M-M of Fig. 12A;
  • FIG13 is a flowchart of a method for manufacturing a memory array chip according to an embodiment of the present application.
  • FIGS. 14A to 14F are schematic diagrams of corresponding structures after each step is completed in a preparation process of a memory array chip provided in an embodiment of the present application;
  • 15A to 15F are schematic diagrams of corresponding structures after each step is completed in a preparation process of a gate-all-around transistor provided in an embodiment of the present application.
  • 210-SOC 211-application processor
  • 212-GPU 213-second memory
  • 205-bus 220-first memory
  • 230-communication chip 240-power management chip
  • FIG3 is a circuit block diagram of an electronic device 100 provided in the embodiment of the present application.
  • the electronic device 100 may be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc.
  • the electronic device 100 includes a bus 205, and a system on chip (SOC) 210 and a first memory 220 connected to the bus 205.
  • the SOC 210 can be used to process data, such as processing application data, processing image data, and caching temporary data.
  • the first memory 220 can be used to store non-volatile data, such as audio files, video files, etc.
  • the first memory 220 can be a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a flash memory, etc.
  • the electronic device 100 may further include a communication chip 230 and a power management chip 240.
  • the communication chip 230 may be used for processing the protocol stack, or for amplifying and filtering analog radio frequency signals, or for simultaneously implementing the above functions.
  • the power management chip 240 may be used for powering other chips.
  • the SOC 210 may include an application processor for processing application programs.
  • processor AP
  • GPU graphics processing unit
  • the AP 211, GPU 212 and second memory 213 may be integrated into one die, or may be integrated into multiple dies, and packaged into a packaging structure, such as using 2.5D (dimension), 3D packaging, or other advanced packaging technologies.
  • the AP 211 and GPU 212 are integrated into one die, the second memory 213 is integrated into another die, and the two dies are packaged into a packaging structure, so as to obtain a faster inter-die data transmission rate and a higher data transmission bandwidth.
  • FIG4 is a circuit block diagram of a memory 300 that can be used in an electronic device according to an embodiment of the present application.
  • the memory 300 can be a ferroelectric random access memory (FeRAM or FRAM), or a dynamic random access memory (DRAM).
  • FeRAM ferroelectric random access memory
  • DRAM dynamic random access memory
  • the memory 300 includes a memory array and a control circuit for accessing the memory array, wherein the control circuit is used to control the read and write operations of the memory array.
  • the memory array in the memory may include a plurality of memory cells 400 arranged in an array as shown in FIG. 5 , wherein each memory cell 400 may be used to store 1 bit (bit) or multiple bits of data.
  • the memory array may also include electrode lines such as word lines (WL) and bit lines (BL).
  • Each memory cell 400 is electrically connected to the corresponding word lines WL and bit lines BL, respectively.
  • One or more of the above-mentioned word lines WL and bit lines BL are used to select the memory cell 400 to be read or written in the memory array by receiving the control level output by the control circuit, thereby realizing the reading and writing operations of the data.
  • the control circuit in the memory may include one or more circuit structures of the decoder 320 , the driver 330 , the timing controller 340 , the buffer 350 , or the input/output driver 360 shown in FIG. 5 .
  • the decoder 320 is used to decode according to the received address to determine the storage unit 400 to be accessed.
  • the driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, so as to The access to the designated storage unit 400 is realized.
  • the buffer 350 is used to cache the read data, for example, a first-in first-out (FIFO) can be used for caching.
  • the timing controller 340 is used to control the timing of the buffer 350, and control the driver 330 to drive the signal line in the storage array.
  • the input and output driver 360 is used to drive the transmission signal, for example, to drive the received data signal and the data signal to be sent, so that the data signal can be transmitted over a long distance.
  • the above storage array may be integrated into one chip.
  • the decoder 320, the driver 330, the timing controller 340, the buffer 350 and the input/output driver 360 may be integrated into another chip.
  • the memory array is integrated into one chip to form a memory array chip 31
  • the control circuit is integrated into another chip to form a control circuit chip 32, and then the memory array chip 31 and the control circuit chip 32 are bonded to form a multi-chip stacked memory 300 including the memory array chip 31 and the control circuit chip 32.
  • the storage array chip 31 or the control circuit chip 32 may be a wafer or a bare die cut from the wafer.
  • the memory 300 includes a memory array chip 31 and a control circuit chip 32, wherein the memory array chip 31 includes a first substrate 311 and a storage layer 312 formed on one side of the first substrate 311, and the storage layer 312 includes a plurality of storage units 400 as shown in FIG5; the control circuit chip 32 includes a second substrate 321 and a circuit structure 322 formed on one side of the second substrate 321.
  • the storage layer 312 is close to the circuit structure 322 relative to the first substrate 311, and the circuit structure 322 is close to the storage layer 312 relative to the second substrate 321, that is, the storage layer 312 and the circuit structure 322 are facing each other, and there is a bonding structure 33 between the storage layer 312 and the circuit structure 322.
  • the storage layer 312 and the circuit structure 322 are physically and electrically connected through the bonding structure 33, so that the circuit structure 322 can read and write the storage cells in the storage layer 312 through the bonding structure 33.
  • FIG8A exemplarily shows a process structure diagram of a control circuit chip 32.
  • a plurality of transistors are integrated on the second substrate 321 of the control circuit chip 32.
  • three transistors are exemplarily shown in FIG8A . These transistors are all made through the front-end process.
  • each transistor includes a source doping region 11 and a drain doping region 12 formed by doping injection in the second substrate 321.
  • a channel region is formed between the source doping region 11 and the drain doping region 12 of the second substrate 321.
  • a gate 13 is formed on the channel region, and the gate 13 and the channel region are isolated by a gate dielectric layer 14.
  • passive devices such as resistors, capacitors, inductors, etc.
  • These active device transistors and passive device resistors, capacitors, inductors, etc. can be connected using the interconnection lines shown in Figure 8A to form a circuit structure 322, which can be used to control the reading and writing of storage cells in the storage array chip 31.
  • the interlayer dielectric is not shown.
  • the metal traces in FIG8A and the conductive channels for electrically connecting different metal traces are formed in the interlayer dielectric.
  • the interlayer dielectric can be a single layer or multiple layers stacked.
  • solder joints 331 are formed on the side of the circuit structure 322 away from the second substrate 321 , and the solder joints 331 are electrically connected to the circuit structure 322 . Then, the signal of the circuit structure 322 can be communicated with the peripheral circuit through the solder joints 331 .
  • solder joint 331 there are multiple materials that can be selected for the solder joint 331, for example, at least one of Cu, NiSi, NiPtSi, etc. can be selected.
  • FIG8B exemplarily shows a process structure diagram of a memory array chip 31.
  • two memory cells are exemplarily shown, and the two memory cells are arranged in a direction parallel to the first substrate 311.
  • FIG8B also shows word lines (word line, WL) and bit lines (bit line, BL), and the word lines WL and the bit lines BL are electrically connected to the memory cells, respectively.
  • word line, WL word line
  • bit line, BL bit lines
  • a plurality of solder joints 332 are formed on a side of the storage layer 312 facing away from the first substrate 311 .
  • the solder joints 332 are electrically connected to the storage layer 312 .
  • solder joint 332 may be made of a variety of materials, for example, at least one of Cu, NiSi, NiPtSi, etc. may be selected.
  • the circuit structure 322 in the control circuit chip 32 is oriented toward the storage layer 312 in the storage array chip 31, and the solder joints 331 and 332 are bonded together to form the bonding structure 33 in FIG8C .
  • the solder joints 331 on the storage array chip 31 may be referred to as first solder joints
  • the solder joints 332 on the control circuit chip 32 may be referred to as second solder joints.
  • the storage layer 312 can be electrically connected to the circuit structure 322 through the bonding structure 33 , so that the circuit structure 322 can control the reading and writing of the storage unit.
  • the memory 300 provided in the embodiment of the present application is a first chip formed by a storage array chip 31 and a second chip formed by a control circuit chip 32, which are stacked through a bonding structure 33 to form a multi-chip 3D stacking structure.
  • the memory 300 provided in the embodiment of the present application as shown in Figure 8C, since the memory array chip 31 and the control circuit chip 32 are stacked, and the active surface of the memory array chip 31 (the side including the memory unit) is opposite to the active surface of the control circuit chip 32 (the side including the circuit structure), this structure can be called wafer on wafer-face to face (WoW-F2F) 3D storage architecture.
  • WoW-F2F wafer on wafer-face to face
  • the WoW-F2F 3D storage architecture involved in the embodiment of the present application compared with the 3D memory structure of the CMOS next Array (CnA) in the related technology, will not increase the two-dimensional area occupied by the control circuit chip due to the increase in the number of stacked layers of storage units in the storage array chip. Therefore, the memory of the example in Figure 8C improves the storage density while bringing a smaller chip two-dimensional area.
  • the "two-dimensional area of the chip” involved in the embodiments of the present application can be understood as: the area parallel to the substrate, such as the area occupied in the X-Y plane.
  • the storage array chip 31 and the control circuit chip 32 may be manufactured separately using independent manufacturing processes, and then the two chips may be bonded together using a bonding process.
  • the preparation process of the storage array chip 31 and the preparation process of the control circuit chip 32 may be incompatible and will not interfere with each other.
  • the process decoupling of CMOS and Array is achieved.
  • the high-temperature process for preparing the storage unit in the storage array chip 31 will not affect the performance of the control circuit chip 32, thereby ensuring the performance of each chip.
  • a hybrid bonding process can be adopted, and the bonding temperature is not higher than 450°C.
  • the bonding temperature is less than or equal to 400°C, and this temperature basically does not affect the performance of the storage unit and circuit structure that have been formed.
  • CMOS-wafer and Array-wafer can be designed and manufactured independently, eliminating process incompatibility and constraints and improving yield. Therefore, CMOS and Array can use the most advanced processes respectively, without the impact of Array's high-temperature process on CMOS causing the performance of Array and CMCOS to restrict each other. Array can use advanced high-temperature processes to obtain better device performance, and CMOS can use advanced logic processes to obtain high transmission speeds without considering the impact of Array's high-temperature process.
  • the structure for conducting the memory array chip 31 and the control circuit chip 32 is a bonding structure 33, which can be made by a hybrid bonding process, which is not only simple in process, but also does not require the selection of some special materials as the material of the bonding structure because of the need to consider the compatibility of the preparation process of the memory array chip 31 and the preparation process of the control circuit chip 32. Therefore, the material range selected for the bonding structure 33 of the present application is relatively wide, for example, Cu, NiSi, NiPtSi, etc. with low resistance can be selected. When a material with low resistance is selected as the bonding structure material, the signal transmission rate between the control circuit chip 32 and the memory array chip 31 is basically not affected.
  • the memory 300 involved in the embodiment of the present application may be a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • it may be a DRAM including 1TnC storage cells.
  • the memory 300 involved in the embodiment of the present application may also be a ferroelectric random access memory (FeRAM), for example, it may also be a FeRAM including a 1TnC storage unit.
  • FeRAM ferroelectric random access memory
  • FIG9 is a circuit diagram of a memory cell 400 in a memory 300 according to an embodiment of the present application.
  • the memory cell 400 belongs to a gain-cell memory cell structure of 1TnC, that is, a memory cell 400 includes a transistor Tr and a plurality of capacitors C.
  • FIG9 exemplarily shows a memory cell 400 including a transistor Tr and three capacitors.
  • a memory cell may include two or more capacitors.
  • one electrode of transistor Tr (one of the source and drain) is electrically connected to a bit line (BL)
  • the other electrode of transistor Tr (the other of the source and drain) is electrically connected to one capacitor electrode of a plurality of capacitors C, respectively
  • the gate of transistor Tr is electrically connected to a word line (WL)
  • the other capacitor electrodes of the plurality of capacitors C are electrically connected to a plate line (PL), respectively, for example, to ground.
  • the memory cell shown in Fig. 9 may be a FeRAM memory cell, that is, the capacitor layer formed between the first capacitor electrode and the second capacitor electrode is a ferroelectric material layer.
  • the memory cell shown in Fig. 9 may also be a DRAM memory cell.
  • the word line WL is used to receive the word line control signal to turn on the transistor Tr
  • the bit line BL is used to receive the bit line control signal
  • the plate line PL electrically connected to the ferroelectric capacitor is used to receive the plate line control signal.
  • the voltage difference of the line control signal, the bit line control signal and the plate line control signal causes the ferroelectric layer of the selected ferroelectric capacitor to be positively polarized or negatively polarized, so as to write different logic information in the selected ferroelectric capacitor. For example, when the ferroelectric layer is positively polarized, the logic signal "0" is written, and for another example, when the ferroelectric layer is negatively polarized, the logic signal "1" is written.
  • the transistor Tr shown in FIG. 9 may be an NMOS (N-channel metal oxide semiconductor) tube, or a PMOS (P-channel metal oxide semiconductor) tube.
  • one of the drain or source of the transistor Tr is called the first electrode, the other corresponding electrode is called the second electrode, and the control terminal of the transistor is the gate.
  • the drain and source of the transistor can be determined according to the direction of current flow.
  • the circuit structure of the storage array chip 31 in FIG8C may be as shown in FIG10.
  • the gates of the transistors Tr of the plurality of storage cells arranged in the same direction may be electrically connected to the same word line WL; and the second electrodes of the transistors Tr of the plurality of storage cells arranged in the same direction may be electrically connected to the same bit line BL.
  • a plurality of word lines WL and a plurality of bit lines BL are formed.
  • the circuit structure in FIG8A includes at least a row decoder and a column decoder, the row decoder is coupled to the word line WL and is configured to turn on or off the gate of the transistor Tr, and the column decoder is coupled to the bit line BL and is configured to read or write the storage cell.
  • FIG11A and FIG11B exemplarily show the process structure diagram of the memory cell that can be used in the memory array chip 31, and FIG11B is an enlarged view of A in FIG11A.
  • a memory cell includes a transistor Tr and a plurality of capacitors C, and the plurality of capacitors C and the transistor Tr are stacked in a direction perpendicular to the first substrate 311.
  • the plurality of capacitors C are arranged close to the first substrate 311 relative to the transistor Tr, and the transistor Tr is arranged away from the first substrate 311 relative to the plurality of capacitors C.
  • each capacitor C includes a first capacitor electrode 502, a capacitor layer 503, and a second capacitor electrode 504.
  • FIG11B exemplarily shows three stacked capacitors C, which are stacked in a direction perpendicular to the first substrate 311, and the capacitors C share the same second capacitor electrode 504.
  • dielectric layers 501 and first capacitor electrodes 502 arranged alternately may be stacked on the first substrate 311, through holes may be opened in the stacked dielectric layers 501 and first capacitor electrodes 502, and stacked capacitor layers 503 and electrode layers may be formed in the through holes, so that the capacitors C share the same second capacitor electrode 504.
  • more capacitors C may be stacked according to the structure shown in FIG11B; or, as shown in FIG11C, a capacitor C and a transistor Tr are provided in a memory cell.
  • a memory cell includes a transistor Tr and a capacitor C
  • the formed memory cell is called a 1T1C memory cell.
  • the transistor Tr includes a first electrode 506, a second electrode 504, a channel layer 505, a gate dielectric layer 507, and a gate 508.
  • the first electrode 506 and the second electrode 504 are arranged in a direction perpendicular to the first substrate 311.
  • the second electrode 504 of the transistor Tr can share the same electrode with the second capacitor electrode 504 of the capacitor C.
  • the channel layer 505 is located between the first electrode 506 and the second electrode 504. The channel formed in this way can be called a vertical channel perpendicular to the first substrate 311.
  • FIG. 12A and 12B show the structure of the transistor Tr, and FIG. 12B is a cross-sectional view taken along the line M-M of FIG. 12A.
  • the gate 508 surrounds the channel layer 505, and the gate 508 and the channel layer 505 are isolated by a gate dielectric layer 507.
  • the transistor Tr structure formed in this way can be referred to as a gate-all-around (GAA) transistor.
  • GAA gate-all-around
  • the memory array chip 31 further includes word lines WL and bit lines BL, wherein the word lines WL are disposed around the gate 508 , and the bit lines BL can share the same film layer with the first electrode 506 of the transistor Tr.
  • a plurality of memory cells arranged along a first direction may share the same word line WL.
  • the gate of the transistor in the first memory cell 401 arranged along the X direction and the gate of the transistor in the second memory cell 402 are electrically connected to the same word line WL, but the bit line BL electrically connected to the first memory cell 401 and the bit line BL electrically connected to the second memory cell 402 are electrically isolated.
  • a plurality of memory cells arranged along a second direction may share the same bit line BL.
  • the second electrode of the transistor in the first memory cell 401 arranged along the Y direction and the second electrode of the transistor in the third memory cell 403 may share the same bit line BL.
  • the second electrode of is electrically connected to the same bit line BL, but the word line WL of the first memory cell 401 and the word line WL of the second memory cell 402 are electrically isolated.
  • a conductive channel (e.g., a through silicon via TSV) is provided on the side of the bit line BL facing away from the first substrate 311, and one end of the conductive channel is connected to the bit line BL, and the other end is connected to the solder joint 332, that is, the memory cell and the solder joint 332 are interconnected through the conductive channel.
  • the first capacitor electrode 502 of the capacitor C is electrically connected to the solder joint 332 through a conductive channel (eg, a through silicon via TSV).
  • a conductive channel eg, a through silicon via TSV
  • the interlayer dielectric is not shown.
  • the memory cell in FIG. 11D is formed in the interlayer dielectric.
  • the interlayer dielectric may be a single layer or may be formed by stacking multiple layers.
  • the transistor Tr is arranged close to the solder joint, and the capacitor C is arranged close to the substrate. Then, the transistor Tr can be electrically connected to the solder joint 332 through a simple electrical connection structure (such as a conductive channel), and a capacitor electrode of the capacitor is also electrically connected to the solder joint 332 through a simple electrical connection structure (such as a conductive channel).
  • a simple electrical connection structure such as a conductive channel
  • a capacitor electrode of the capacitor is also electrically connected to the solder joint 332 through a simple electrical connection structure (such as a conductive channel).
  • the electrical connection structure between the transistor Tr and the capacitor C and the solder joint 332 is relatively simple, which will simplify the wiring structure of the entire memory array chip 31. By simplifying the wiring structure, more accommodation space can be avoided for the memory cell to increase the number of memory cells, thereby increasing the storage density and capacity.
  • various functional layers of the transistor Tr, various functional layers of the capacitor C, and the word line WL and the bit line BL may be made of a variety of materials, and some of the selectable materials are given below.
  • the materials of the first electrode, the second electrode, the gate, the word line WL and the bit line BL of the transistor Tr are all conductive materials, such as metal materials.
  • it can be one or more of TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver) and other conductive materials.
  • the channel layer 505 of the transistor Tr can be selected from one or more semiconductor materials such as Si (silicon), poly-Si (p-Si, polycrystalline silicon), amorphous-Si (a-Si, amorphous silicon), In-Ga-Zn-O (IGZO, indium gallium zinc oxide) multi-compound, ZnO (zinc oxide), ITO (indium tin oxide), TiO2 (titanium dioxide), MoS2 (molybdenum disulfide), WS2 (tungsten disulfide), graphene, black phosphorus, etc.
  • semiconductor materials such as Si (silicon), poly-Si (p-Si, polycrystalline silicon), amorphous-Si (a-Si, amorphous silicon), In-Ga-Zn-O (IGZO, indium gallium zinc oxide) multi-compound, ZnO (zinc oxide), ITO (indium tin oxide), TiO2 (titanium dioxide), MoS2 (molybden
  • the material of the gate dielectric layer 507 of the transistor Tr may be one or more insulating materials such as SiO2 (silicon dioxide), Al2O3 ( aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconium oxide), TiO2 (titanium dioxide) , Y2O3 (yttrium oxide) and Si3N4 (silicon nitride).
  • SiO2 silicon dioxide
  • Al2O3 aluminum oxide
  • HfO2 hafnium dioxide
  • ZrO2 zirconium oxide
  • TiO2 titanium dioxide
  • Y2O3 yttrium oxide
  • Si3N4 silicon nitride
  • the first capacitor electrode and the second capacitor electrode in the capacitor C are both made of conductive materials.
  • one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver) can be used.
  • the capacitance layer in the capacitor C can be selected from insulating materials such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4, HAO, etc., or ferroelectric materials such as ZrO2, HfO2, Al-doped HfO2, Si-doped HfO2, Zr-doped HfO2, La-doped HfO2, Y-doped HfO2, or materials doped with other elements based on these materials and any combination thereof.
  • insulating materials such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4, HAO, etc.
  • ferroelectric materials such as ZrO2, HfO2, Al-doped HfO2, Si-doped HfO2, Zr-doped HfO2, La-doped HfO2, Y-doped HfO2, or materials doped with other elements based on these materials and any combination thereof.
  • FIG. 13 exemplarily shows a flowchart of preparing a memory.
  • Step S1 Provide a storage array chip and a control circuit chip
  • the storage array chip includes a first substrate, a plurality of storage cells formed on one side of the first substrate, each storage cell includes a transistor and at least one capacitor electrically connected to the transistor, a side of the plurality of storage cells facing away from the first substrate has a first solder joint
  • the control circuit chip includes a second substrate, a circuit structure formed on one side of the second substrate, and a side of the circuit structure facing away from the second substrate has a second solder joint.
  • the memory array chip and the control circuit chip can be manufactured by using independent processes, thus avoiding the influence of process incompatibility and mutual restriction.
  • the memory array chip and the control circuit chip can be manufactured by using advanced processes.
  • the preparation of the memory array chip and the preparation of the control circuit chip can be performed simultaneously to shorten the manufacturing cycle of the memory.
  • Step S2 Align the multiple storage cells and the circuit structure toward each other, bond the first solder joint to the second solder joint, and form a bonding structure connecting the storage array chip and the control circuit chip, so that the circuit structure controls the reading and writing of the multiple storage cells through the bonding structure.
  • the circuit structure can be interconnected with the storage unit through the bonding structure, so that the control circuit chip can control the read and write operations of the storage unit.
  • step S1 and step S2 are introduced below in conjunction with the accompanying drawings.
  • FIG. 14A to 14F show the process structure after each step is completed in the process of manufacturing a memory array chip according to an embodiment of the present application.
  • multiple dielectric layers 601 and multiple conductive layers 602 are stacked on the first substrate 311 , and the multiple dielectric layers 601 and the multiple conductive layers 602 are stacked alternately.
  • the dielectric layers 601 may be made of one or more insulating materials such as SiO2 (silicon dioxide), Al2O3 ( aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconium oxide), TiO2 (titanium dioxide), Y2O3 (yttrium oxide), and Si3N4 (silicon nitride ).
  • SiO2 silicon dioxide
  • Al2O3 aluminum oxide
  • HfO2 hafnium dioxide
  • ZrO2 zirconium oxide
  • TiO2 titanium dioxide
  • Y2O3 yttrium oxide
  • Si3N4 silicon nitride
  • the conductive layer 602 can be selected from one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).
  • conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).
  • the number of dielectric layers 601 is equal to the number of conductive layers 602. For example, when a 1T3C memory cell is to be manufactured, three dielectric layers 601 and three conductive layers 602 can be stacked alternately; for another example, when a 1T1C memory cell is to be manufactured, one dielectric layer 601 and one conductive layer 602 can be stacked.
  • the multi-layer dielectric layer 601 and the multi-layer conductive layer 602 are etched to form a stepped structure.
  • the multi-layer dielectric layer 601 and the multi-layer conductive layer 602 can be divided into multiple groups of functional layers, and an adjacent layer of dielectric layer 601 and conductive layer 602 is a group of functional layers.
  • N groups of functional layers can be included, and, along the direction away from the first substrate 311, the size of the N groups of functional layers along the first direction gradually decreases to form a step shape, and the dielectric layers 601 and conductive layers 602 in each group of functional layers are equal in size in the first direction, and the first direction is a direction parallel to the first substrate 311.
  • the multiple conductive layers 602 are arranged in a stepped manner, and among two adjacent conductive layers 602, the orthographic projection of the conductive layer 602 away from the first substrate 311 on the first substrate 311 is located within the orthographic projection boundary of the conductive layer 602 close to the first substrate 311 on the first substrate 311.
  • the outer edge of the conductive layer 602 close to the first substrate 311 is more protruding than the outer edge of the conductive layer far from the first substrate 311 .
  • through holes 603 are opened to penetrate the multi-layer dielectric layers 601 and the multi-layer conductive layers 602 , and each through hole 603 penetrates to the first substrate 311 .
  • capacitor material and conductive material are sequentially filled into each through hole 603 to form a capacitor layer 503 and an electrode.
  • the electrode formed by the conductive layer 602 can be referred to as the first capacitor electrode 502 of the capacitor, and the electrode located in the through hole can be referred to as the second capacitor electrode 504 of the capacitor.
  • the capacitor material that can be filled can be selected from ferroelectric materials such as ZrO2, HfO2, Al-doped HfO2, Si-doped HfO2, Zr-doped HfO2, La-doped HfO2, and Y-doped HfO2.
  • a channel layer 505 , a gate dielectric layer 507 and a gate 508 of the transistor Tr are formed, and the gate 508 is disposed around the channel layer 505 , and a word line WL and a bit line BL are formed.
  • a conductive channel is formed through the interlayer dielectric (not shown in the figure), and a solder joint 332 is formed, so that the first capacitor electrode of the capacitor C is electrically connected to the solder joint 332 through the conductive channel, and the bit line BL is electrically connected to the solder joint 332 through the conductive channel.
  • the conductive channel can be arranged at the edge of the conductive layer to avoid occupying the space where the storage unit is located.
  • control circuit chip can be manufactured using advanced technology, and then the control circuit chip can be bonded to the memory array chip manufactured in FIG. 14A to FIG. 14F to obtain a three-dimensional stacked memory structure.
  • FIGS. 15A to 15F When manufacturing the gate-all-around transistor shown in FIG. 14F , the process flow shown in the following FIGS. 15A to 15F may be adopted.
  • a dielectric layer 601 , a conductive layer 602 , and a dielectric layer 601 are sequentially stacked.
  • a through hole is opened that penetrates the dielectric layer 601 , the conductive layer 602 , and the dielectric layer 601 .
  • gate dielectric material and channel material are sequentially deposited in the through hole. In some implementation processes, as shown in Figures 15C and 15D , gate dielectric material and channel material are also deposited on the surface of dielectric layer 601 located above conductive layer 602 .
  • the gate dielectric material and the channel material on the surface of the dielectric layer 601 above the conductive layer 602 are removed.
  • the dielectric layers on both sides of the conductive layer 602 are removed, and the conductive layer 602 surrounds the channel layer 505 to form a ring gate structure.
  • the conductive layer 602 can be used as the gate 508 of the transistor and also as the word line WL in the memory array chip.
  • 15A to 15F exemplarily show a method for preparing a ring-gate transistor.
  • the ring-gate transistor involved in the embodiment of the present application can also adopt other preparation processes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Databases & Information Systems (AREA)
  • Semiconductor Memories (AREA)

Abstract

本申请提供一种存储器、电子设备及存储器的制备方法。涉及半导体存储技术领域。该存储器可以包括存储阵列芯片和控制电路芯片，存储阵列芯片包括第一衬底、形成在第一衬底上的多个存储单元，每一个存储单元包括晶体管、与晶体管电连接的至少一个电容器；控制电路芯片包括第二衬底、形成在第二衬底上的电路结构，电路结构用于控制多个存储单元的读写；多个存储单元和电路结构朝向彼此，并通过形成在多个存储单元和电路结构之间的键合结构电连接。通过将存储阵列芯片集成在一个芯片中，控制电路芯片集成在另外一个芯片中，并将两个芯片键合，形成存储器，这样，可以利用不兼容的工艺制得存储阵列芯片和控制电路芯片。

Description

存储器、电子设备及存储器的制备方法
本申请要求于2022年11月28日提交国家知识产权局、申请号为202211501780.9、发明名称为“存储器、电子设备及存储器的制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体存储技术领域，尤其涉及一种存储器、电子设备、存储器的制备方法，以及存储阵列芯片的制备方法。
背景技术
随着信息爆炸发展，存储技术的发展方向是更高的存储密度，以获得更高的存储容量，进而，三维(3dimensional，3D)存储器应运而生。诸如图1A、图1B、图1C和图2所示存储器，是通过垂直于衬底向上3D堆叠存储阵列来提高存储密度。
如图1A至图1C，以及图2，3D存储器不仅包括用于存储数据的存储阵列(Array)，还包括用于控制存储阵列读写的控制电路，一些示例中，控制电路可以被称为CMOS外围电路。
继续参阅如图1A至图1C，示出的是CMOS next Array(CnA)的3D存储器结构，这种结构是基于二维(2 dimensional，2D)平面结构芯片的制造工艺，把控制电路和存储阵列集成在同一芯片的同一面上，且并行排列，其中，存储阵列通过垂直于衬底向上堆叠形成3D结构。
对于该CnA架构的3D存储器结构，如图1A至图1C，随着存储阵列堆叠高度(如沿Z方向)的增加，控制电路在衬底上占用面积的比例也会增加，这样不利于制备小尺寸高密度的存储器件。
再如图2，示出的是CMOS under Array(CuA)的3D存储器结构，这种结构是把控制电路集成在存储阵列下面，在制备过程中，先制备控制电路，然后在控制电路上方制备存储阵列，并向上进行3D堆叠来实现高密度存储。
但是，在图2所示CuA架构的3D存储器中，存储阵列的制造包括高温制程(如Si的结晶化需要在高温下进行)，此高温会对下方已经形成的控制电路的性能造成影响，比如，降低控制电路的传输速度。
图2所示制备工艺，可以理解为，存储阵列制造工艺和CMOS外围电路制造工艺不兼容，所以，图2所示结构，尽管可以缩减存储器件二维尺寸，但是，又会限制存储器件的性能。
发明内容
本申请提供一种存储器、电子设备、存储器的制备方法，以及，存储阵列的制备方法。主要目的是提供一种将存储阵列芯片和控制电路芯片键合于一起的结构，不仅可以减小芯片二维面积，还可以解决工艺不兼容的问题。
为达到上述目的，本申请的实施例采用如下技术方案：
一方面，本申请提供了一种存储器，该存储器可以包括存储阵列芯片和控制电路芯片，存储阵列芯片包括第一衬底、形成在第一衬底一侧的多个存储单元，每一个存储单元包括晶体管、与晶体管电连接的至少一个电容器；控制电路芯片包括第二衬底、形成在第二衬底一侧的电路结构，电路结构用于控制多个存储单元的读写；多个存储单元和电路结构朝向彼此，并通过形成在多个存储单元和电路结构之间的键合结构电连接；并且，晶体管和至少一个电容器沿着与第一衬底相垂直的方向堆叠，晶体管相对至少一个电容器靠近键合结构设置。
本申请涉及的存储器，将多个存储单元集成在存储阵列芯片中，以及，将用于控制存储单元读写的电路结构集成在另一个控制电路芯片中，这两个芯片再通过键合结构键合于一起，即通过键合结构实现存储单元和电路结构的互连。
由于多个存储单元被集成在一个芯片中，电路结构被集成在另一个芯片中，那么，在制备工艺中，制备多个存储单元所采用的工艺，可以与制备电路结构的工艺不兼容，这样，不会因为工 艺不兼容导致器件之间性能影响的现象，即本申请给出的3D存储器架构，在制备工艺上，可以实现存储阵列芯片和控制电路芯片的工艺解耦。
并且，本申请的存储阵列芯片中，晶体管和电容器沿着与第一衬底相垂直的方向堆叠，这样可以在第一衬底的单位面积上，集成更多的存储单元，提升存储密度；以及，存储阵列芯片和控制电路芯片又呈3D堆叠设置，相比CMOS next Array(CnA)的3D存储器结构，不会因为存储阵列芯片堆叠层数的增加，导致整个芯片堆叠结构的二维尺寸面积较大，所以，本申请给出的3D存储器结构，在提高存储密度的基础上，还不会增加芯片二维面积。
在一种可以实现的方式中，多个存储单元的背离第一衬底的一侧形成有第一焊点，电路结构的背离第二衬底的一侧形成有第二焊点，第一焊点和第二焊点键合形成键合结构。
即在制备过程中，可以将存储阵列芯片上的第一焊点，与控制电路芯片上的第二焊点，键合在一起，形成多芯片堆叠结构的存储器。
在一种可以实现的方式中，键合结构采用混合键合Hybrid Bonding工艺制得。
在一种可以实现的方式中，至少一个电容器的外围设置有垂直于第一衬底的第一导电通道，每一个电容器通过第一导电通道与键合结构电连接。
由于电容器相对晶体管靠近第一衬底设置，为了将电容器与外围的控制电路芯片电连接，可以采用导电通道将电容器与键合结构连接，采用导电通道作为电连接结构，不仅结构简单，在工艺上还容易实现。
在一种可以实现的方式中，每一个存储单元包括多个电容器，每一个电容器包括第一电容电极、电容层和第二电容电极；沿与第一衬底相垂直的方向，第一衬底上交替堆叠有多层介质层和多层导电层；第二电容电极贯通交替堆叠的多层介质层和多层导电层，形成多个电容器的共用第二电容电极；电容层贯通交替堆叠的多层介质层和多层导电层，形成多个电容器的共用电容层，且共用电容层环绕共用第二电容电极；环绕在电容层外围的至少部分导电层，形成第一电容电极；沿与第一衬底相垂直的相邻两个第一电容电极之间，被介质层隔离开。
当具有多个电容器时，在工艺结构中，多个电容器的第二电容电极和电容层均可以共用，这样，不仅可以简化制备工艺，还可以简化结构，提升存储密度。
在一种可以实现的方式中，沿与第一衬底相平行排布的多个电容器的第一电容电极连接呈一体。
在一些制备工艺中，可以形成与第一衬底相平行的导电层，再在导电层内打多个孔，并在每一个孔内填充电容材料和另一电容电极材料，这样的话，与第一衬底相平行的多个电容器的电容电极连接呈一体，即为与第一衬底相平行的导电层。
在一种可以实现的方式中，沿着远离第一衬底的方向，多层导电层呈阶梯状排布，相邻两个导电层中，远离第一衬底的导电层在第一衬底上的正投影，位于靠近第一衬底的导电层在第一衬底上的正投影边界内；第一导电通道位于导电层的边缘。
将多层导电层设置为阶梯状排布，可以给与下层的导电层(靠近第一衬底的导电层)连接的导电通道预留容置空间。并将作为电连接结构的第一导电通道设置在导电层的边缘，以充分利用导电层边缘空间，这样，不会使得电容器与键合结构的互连结构复杂，进而，可以提升存储密度。
在一种可以实现的方式中，晶体管的靠近键合结构的一侧具有垂直于第一衬底的第二导电通道，晶体管通过第二导电通道与键合结构电连接。
在一种可以实现的方式中，存储阵列芯片还包括：第一电极线和第二电极线，第一电极线与晶体管的栅极电连接，第二电极线与晶体管的第一极电连接，晶体管的第二极与电容器电连接。
比如，该第一电极线可以是字线WL，第二电极线为位线BL。通过字线WL实现晶体管的导通和关断，通过位线BL进行存储单元的读写。
在一种可以实现的方式中，晶体管的第一极和第二极沿与第一衬底相垂直的方向排布，晶体管的沟道层位于第一极和第二极之间，且第一极相对第二极远离电容器设置，第二电极线与第一极共用同一电极层，第二电极线通过垂直于第一衬底的第二导电通道与键合结构电连接。
由于晶体管被设置在远离第一衬底的一侧，那么，就可以通过结构简单的导电通道，将晶体管与键合结构电连接于一起。
在一种可以实现的方式中，晶体管为环栅晶体管。
例如，晶体管的第一极和第二极沿与第一衬底相垂直的方向排布，晶体管的沟道层位于第一极和第二极之间，栅极环绕沟道层，且栅极和沟道层之间被栅介质层隔离开，这样，就形成环栅晶体管。
在一种可以实现的方式中，存储阵列芯片为DRAM存储阵列芯片，或者，存储阵列芯片为铁电存储阵列芯片。
另一方面，本申请还提供一种存储器的制备方法，该制备方法包括：
提供存储阵列芯片和控制电路芯片，存储阵列芯片包括第一衬底、形成在第一衬底一侧的多个存储单元，每一个存储单元包括晶体管、与晶体管电连接的至少一个电容器，多个存储单元的背离第一衬底的一侧具有第一焊点，控制电路芯片包括第二衬底、形成在第二衬底一侧的电路结构，电路结构的背离第二衬底的一侧具有第二焊点；
将多个存储单元和电路结构朝向彼此，第一焊点与第二焊点键合，形成连接存储阵列芯片和控制电路芯片的键合结构，使得电路结构通过键合结构控制多个存储单元的读写。
此种制备方法中，存储单元和电路结构不是被集成在同一芯片中，而是被分别集成在不同的芯片，以形成独立的存储阵列芯片和控制电路芯片，然后，再将存储阵列芯片和控制电路芯片进行键合，实现控制电路对存储单元读写的控制。
从而，在制备存储单元和制备用于控制存储单元读写的电路结构时，可以采用不兼容、相互不制约的工艺手段，这样，不仅工艺方法不干涉，也不会因为工艺彼此相互影响工作性能。
在一种可以实现的方式中，采用混合键合Hybrid Bonding工艺键合第一焊点和第二焊点。
在一种可以实现的方式中，第一焊点与第二焊点键合时，键合温度小于或等于450℃。比如，键合温度小于或等于400℃。
键合温度不高于450℃时，基本不会对存储阵列芯片的性能，和控制电路芯片的性能造成影响。
再一方面，本申请还提供一种存储阵列芯片的制备方法，该制备方法包括：
在衬底上形成至少一个电容器；
在至少一个电容器的背离衬底一侧形成晶体管，存储阵列芯片中的每一个存储单元包括至少一个电容器和晶体管；
在至少一个电容器的外围形成垂直于衬底的第一导电通道，在晶体管的背离衬底一侧形成垂直于衬底的第二导电通道；
在存储单元的背离衬底一侧形成焊点，使得至少一个电容器通过第一导电通道与焊点电连接，以及，晶体管通过第二导电通道与焊点电连接。
本申请给出的制备存储阵列的方法中，电容器和晶体管沿着与衬底相垂直的方向堆叠，这样，可以在衬底的单位面积上形成更多的存储单元，提升存储密度；电容器相对晶体管更加靠近衬底设置，电容器通过结构简单的导电通道与焊点电连接，以及，晶体管也通过结构简单的导电通道与焊点电连接。
在一种可以实现的方式中，在衬底上形成至少一个电容器包括：在衬底上交替堆叠多层介质层和多层导电层；开设贯通多层介质层和多层导电层的通孔；在通孔内依次填充电容材料和电极材料，以在通孔内形成电容层和电容电极，电容层形成在电容电极和通孔侧壁之间，以制得多个电容器，电容层形成多个电容器的共用电容层，电容电极形成多个电容器的共用第二电容电极，环绕在电容层外围的至少部分导电层，形成电容器的第一电容电极。
即就是，将存储单元中的电容器靠近衬底设置，并且，多个电容器的电容层和其中一个电容电极分别共用，这样可以简化工艺结构，缩小每一存储单元的面积，以提升存储密度。
在一种可以实现的方式中，在衬底上交替堆叠多层介质层和多层导电层之后，制备方法还包括：对多层介质层和多层导电层的边缘进行刻蚀，沿着远离衬底的方向，多层导电层呈阶梯状排布，相邻两个导电层中，远离衬底的导电层在衬底上的正投影，位于靠近衬底的导电层在衬底上的正投影边界内。
如此设计，是为了便于将电容器通过导电通道与键合结构电连接。
在一种可以实现的方式中，对多层介质层和多层导电层的边缘进行刻蚀，使得多层导电层呈阶梯状排布后，制备方法还包括：在每一层导电层的边缘设置第一导电通道，使得导电层通过第一导电通道能够与焊点电连接。
又一方面，本申请还提供一种电子设备，该电子设备包括处理器和上述任一实现方式中的存储器，处理器与存储器电连接，存储器用于存储处理器产生的数据。
本申请实施例提供的电子设备包括上述任一实现方式中的存储器，因此本申请实施例提供的电子设备与上述技术方案的存储器能够解决相同的技术问题，并达到相同的预期效果。
附图说明
图1A至图1C为相关技术中一种CMOS next Array(CnA)的3D存储器的结构示意图；
图2为相关技术中一种CMOS under Array(CuA)的3D存储器的结构示意图；
图3为本申请实施例提供的一种电子设备中的电路图；
图4为本申请实施例提供的一种存储器的简易电路图；
图5为本申请实施例提供的一种存储器的电路图；
图6为本申请实施例提供的一种如何制得存储器的示意图；
图7为本申请实施例提供的一种存储器的工艺结构图；
图8A为本申请实施例提供的一种控制电路芯片的工艺结构图；
图8B为本申请实施例提供的一种存储阵列芯片的工艺结构图；
图8C为本申请实施例提供的一种存储器的工艺结构图；
图9为本申请实施例提供的一种存储器中一个存储单元的电路图；
图10为本申请实施例提供的一种存储阵列芯片的电路图；
图11A为本申请实施例提供的一种存储阵列芯片的工艺结构图；
图11B为图11A的A处放大图；
图11C为本申请实施例提供的一种存储单元的工艺结构图；
图11D为本申请实施例提供的一种存储阵列芯片的工艺结构图；
图12A为本申请实施例提供的一种晶体管的三维视图；
图12B为图12A的M-M剖面图；
图13为本申请实施例提供的一种存储阵列芯片制作方法的流程框图；
图14A至图14F为本申请实施例提供的一种存储阵列芯片的制备过程中，每一步骤完成后相对应的结构示意图；
图15A至图15F为本申请实施例提供的一种环栅晶体管的制备过程中，每一步骤完成后相对应的结构示意图。
附图标记：
100-电子设备；
210-SOC；211-应用处理器；212-GPU；213-第二存储器；205-总线；220-第一存储器；230-通信芯片；240-电源管理芯片；
300-存储器；
31-存储阵列芯片；
32-控制电路芯片；
33-键合结构；
311-第一衬底；
312-存储层；
321-第二衬底；
322-电路结构；
331-第一焊点；
332-第二焊点；
400-存储单元；
501、601-介质层；
502-第一电容电极；
503-电容层；
504-第二电容电极、第二极；
505-沟道层；
506-第一极；
507-栅介质层；
508-栅极；
602-导电层。
具体实施方式
下面结合附图对本申请实施例涉及的内容进行详细说明。
本申请实施例提供一种包含存储器的电子设备。图3为本申请实施例提供的一种电子设备100中的电路框图，该电子设备100可以是终端设备，例如手机，平板电脑，智能手环，也可以是个人电脑(personal computer，PC)、服务器、工作站等。
见图3所示，电子设备100包括总线205，以及与总线205连接的片上系统(system on chip，SOC)210和第一存储器220。SOC210可以用于处理数据，例如处理应用程序的数据，处理图像数据，以及缓存临时数据。第一存储器220可以用于保存非易失性数据，例如音频文件、视频文件等。第一存储器220可以为可编程序只读存储器(programmable read-only memory，PROM)、可擦除可编程只读存储器erasable(programmable read-only memory，EPROM)、闪存(flash memory)等。
此外，电子设备100还可以包括通信芯片230和电源管理芯片240。通信芯片230可以用于协议栈的处理，或对模拟射频信号进行放大、滤波等处理，或同时实现上述功能。电源管理芯片240可以用于对其他芯片进行供电。
在一种实施方式中，SOC210可以包括用于处理应用程序的应用处理器(application
processor，AP)211，用于处理图像数据的图像处理单元(graphics processing unit，GPU)212，以及第二存储器213。
上述AP211、GPU212和第二存储器213可以被集成于一个裸片(die)中，或者分别集成于多个裸片(die)中，并被封装在一个封装结构中，例如采用2.5D(dimension)，3D封装，或其他的先进封装技术。在一种实施方式中，上述AP211和GPU212被集成于一个die中，第二存储器213被集成于另一个die中，这两个die被封装在一个封装结构中，以此获得更快的die间数据传输速率和更高的数据传输带宽。
图4为本申请实施例提供的一种可以被应用在电子设备中的存储器300的电路框图。在一种实施方式中，存储器300可以是铁电随机存取存储器(Ferroelectric Random Access Memory，FeRAM或FRAM)，或者，也可以是动态随机存取存储器(dynamic random access memory，DRAM)。本申请对存储器300的应用场景不做限定。
如图4所示，存储器300包括存储阵列和用于访问存储阵列的控制电路，其中，控制电路用于控制存储阵列的读写操作。
在一种实施方式中，存储器中的存储阵列可以包括图5所示的多个阵列排布的存储单元400，其中每个存储单元400都可以用于存储1比特(bit)或者多bit的数据。存储阵列还可以包括字线(word line，WL)和位线(bit line，BL)等电极线。每一个存储单元400都与对应的字线WL和位线BL分别电连接。上述字线WL和位线BL中的一个或多个用于通过接收控制电路输出的控制电平，选择存储阵列中待读写的存储单元400，从而实现数据的读写操作。
存储器中的控制电路可以包括图5所示的译码器320、驱动器330、时序控制器340、缓存器350或输入输出驱动360中的一个或多个电路结构。
在图5所示存储器300结构中，译码器320用于根据接收到的地址进行译码，以确定需要访问的存储单元400。驱动器330用于根据译码器320产生的译码结果来控制信号线的电平，从而 实现对指定存储单元400的访问。缓存器350用于将读取的数据进行缓存，例如可以采用先入先出(first-in first-out，FIFO)来进行缓存。时序控制器340用于控制缓存器350的时序，以及控制驱动器330驱动存储阵列中的信号线。输入输出驱动360用于驱动传输信号，例如驱动接收的数据信号和驱动需要发送的数据信号，使得数据信号可以被远距离传输。
上述存储阵列可以集成在一个芯片中。译码器320、驱动器330、时序控制器340、缓存器350和输入输出驱动360可以集成于另一个芯片中。
比如，如图6所示，存储阵列被集成在一个芯片中，形成存储阵列芯片31，控制电路被集成在另一个芯片中，形成控制电路芯片32，再将存储阵列芯片31和控制电路芯片32键合，以形成包含存储阵列芯片31和控制电路芯片32的多芯片堆叠的存储器300。
在本申请涉及的实施例中，比如，存储阵列芯片31或者控制电路芯片32分别可以是晶圆wafer，也可以是从晶圆wafer切割下来的裸片die。
图7是本申请实施例给出的一种存储器300的工艺结构图。存储器300包括存储阵列芯片31和控制电路芯片32，其中，存储阵列芯片31包括第一衬底311，和形成在第一衬底311一侧的存储层312，存储层312包括多个如图5所示的存储单元400；控制电路芯片32包括第二衬底321，和形成在第二衬底321一侧的电路结构322。
并且，如图7所示，存储层312相对第一衬底311靠近电路结构322，以及，电路结构322相对第二衬底321靠近存储层312，也就是，存储层312和电路结构322朝向彼此，存储层312和电路结构322之间具有键合结构33，存储层312和电路结构322通过键合结构33进行物理连接和电连接，使得电路结构322通过键合结构33，对存储层312中的存储单元进行读写控制。
图8A示例性的给出了一种控制电路芯片32的工艺结构图，该控制电路芯片32的第二衬底321上，会集成多个晶体管，比如，在图8A中，示例性的展示了三个晶体管，这些晶体管均通过前道工艺制得，例如，每一个晶体管均包括在第二衬底321中掺杂注入形成的源极掺杂区11、漏极掺杂区12，第二衬底321的位于源极掺杂区11和漏极掺杂区12之间形成沟道区，沟道区上形成有栅极13，且栅极13和沟道区之间被栅介质层14隔离开。
在一些示例中，还可以在第二衬底321形成无源器件，比如，电阻、电容、电感等，利用图8A示出的互连线，将这些有源器件晶体管，无源器件电阻、电容、电感等进行连接，以形成电路结构322，该电路结构322可以用于控制存储阵列芯片31中存储单元的读写。
在图8A中，为了清楚显示集成在第二衬底321上的晶体管和互连线，并未将层间介质示出，在实际产品中，图8A中的金属走线、用于电连接不同金属走线的导电通道，均形成在层间介质中。该层间介质可以是一层，也可以是多层堆叠而成。
继续参阅图8A，在电路结构322的背离第二衬底321的一侧，形成有多个焊点331，这些焊点331与电路结构322电连接。那么，电路结构322的信号可以通过焊点331与外围的电路互通。
示例的，焊点331可以选择的材料具有多种，比如，可以选择Cu、NiSi、NiPtSi等中的至少一种。
图8B示例性的给出了一种存储阵列芯片31的工艺结构图。在图8B中，示例性的展示了两个存储单元，两个存储单元沿着与第一衬底311相平行的方向排布。另外，在图8B中，还示出了字线(word line，WL)和位线(bit line，BL)，字线WL和位线BL分别与存储单元电连接。下面会结合附图对本申请涉及的存储单元电路结构、工艺结构详细描述。
继续参阅图8B，存储层312的背离第一衬底311的一侧，形成有多个焊点332，这些焊点332与存储层312电连接。
在一些示例中，焊点332可以选择的材料具有多种，比如，可以选择Cu、NiSi、NiPtSi等中的至少一种。
见图8A和图8B所示，将控制电路芯片32中的电路结构322朝向存储阵列芯片31中的存储层312，并将焊点331和焊点332键合在一起，形成图8C中的键合结构33。为了清楚描述，可以将存储阵列芯片31上的焊点331称为第一焊点，控制电路芯片32上的焊点332称为第二焊点。
将存储阵列芯片31和控制电路芯片32依照图8A、图8B和图8C所示键合后，存储层312就可以通过键合结构33与电路结构322电连接，实现电路结构322对存储单元读写的控制。
基于图8A至图8C可以得知，本申请实施例提供的存储器300，是由存储阵列芯片31形成的第一芯片，和由控制电路芯片32形成的第二芯片，通过键合结构33堆叠而成，以形成多芯片3D堆叠结构。
本申请实施例提供的如图8C所示的存储器300，由于存储阵列芯片31与控制电路芯片32堆叠，且存储阵列芯片31的有源面(包含存储单元的一面)，与控制电路芯片32的有源面(包含电路结构的一面)相对，所以，可以将此种结构称为wafer on wafer-face to face(WoW-F2F)3D存储架构。
本申请实施例涉及的WoW-F2F的3D存储架构，与相关技术的CMOS next Array(CnA)的3D存储器结构相比，不会因为存储阵列芯片中存储单元堆叠层数的增加，而增加控制电路芯片所占据的二维面积，所以，图8C示例的存储器，在提升存储密度的同时，带来了更小的芯片二维面积。
本申请实施例涉及的“芯片二维面积”可以理解为：与衬底相平行的面积，比如在X-Y平面内所占据的面积。
在制得图8C所示的WoW-F2F的3D存储架构时，可以先利用彼此独立的制造工艺，分别制得存储阵列芯片31芯片和控制电路芯片32芯片，然后，利用键合工艺，将两个芯片键合于一起。
那么，首先，在分别制得存储阵列芯片31和控制电路芯片32时，存储阵列芯片31的制备工艺和控制电路芯片32的制备工艺可以不兼容，相互不会干涉影响，与相关技术的CMOS under Array(CuA)的3D存储器结构工艺相比，实现了CMOS和Array的工艺解耦，这样的话，比如，制备存储阵列芯片31中的存储单元的高温工艺，不会对控制电路芯片32造成性能影响，从而，可以保障各自的性能；其次，两个芯片在键合时，可以采用混合键合工艺，键合温度不高于450℃，比如，键合温度为小于或等于400℃，此温度基本不会对已经形成的存储单元和电路结构性能造成影响。
CMOS-wafer和Array-wafer可以进行独立的设计和制造，消除了工艺上的不兼容和制约并提升良率。所以，CMOS和Array可以分别采用最先进的工艺，不用因为Array的高温制程对CMOS的影响从而造成Array和CMCOS的性能相互制约。Array可以使用先进的高温工艺来获得更好的器件性能，CMOS可以选用先进的逻辑工艺来获得高的传输速度，不用考虑会受到Array高温工艺的影响。
除此之外，导通存储阵列芯片31和控制电路芯片32的结构为键合结构33，键合结构33可以采用混合键合工艺制得，不仅工艺简单，并且，也不会因为需要考虑存储阵列芯片31制备工艺和控制电路芯片32制备工艺的兼容，而选择一些特殊材料作为键合结构的材料，所以，本申请键合结构33所选择的材料范围较广，比如，可以选择电阻较低的Cu，NiSi，NiPtSi等。当选择电阻较低的材料作为键合结构材料时，基本不会影响控制电路芯片32和存储阵列芯片31之间的信号传输速率。
本申请实施例涉及的存储器300可以是动态随机存取存储器(dynamic random access memory，DRAM)。比如，可以是包括1TnC存储单元的DRAM。
另外，本申请实施例涉及的存储器300也可以是铁电随机存取存储器(ferroelectric random access memory，FeRAM)，比如，也可以是包含1TnC存储单元的FeRAM。
图9是本申请实施例给出的存储器300中的一个存储单元400的电路图。如图9，该存储单元400属于1TnC的gain-cell存储单元结构，也就是在一个存储单元400中包括一个晶体管Tr和多个电容器C。比如，图9示例性的给出了一个存储单元400中包括一个晶体管Tr和三个电容器。当然，在一些实施例中，一个存储单元可以包括两个电容器或者更多个电容器。
见图9所示，晶体管Tr的一个电极(源漏极中的一个)与位线(bit line，BL)电连接，晶体管Tr的另一个电极(源漏极中的另一个)与多个电容器C的一个电容电极分别电连接，晶体管Tr的栅极与字线(word line，WL)电连接；以及，多个电容器C的另一个电容电极分别与板线(plate line，PL)电连接，比如，接地。
示例的，图9所示存储单元可以为FeRAM存储单元，即形成在第一电容电极和第二电容电极之间的电容层为铁电材料层。当然，图9所示存储单元也可以是DRAM存储单元。
比如，当图9所示存储单元为FeRAM存储单元时，在写入阶段，字线WL用于接收字线控制信号，使得晶体管Tr导通，位线BL用于接收位线控制信号，铁电电容电连接的板线PL用于接收板 线控制信号，位线控制信号和板线控制信号的电压差使被选中的铁电电容的铁电层发生正极化或者发生负极化，以在被选中的铁电电容中写入不同的逻辑信息。比如，当铁电层发生正极化时，写入逻辑信号“0”，再比如，当铁电层发生负极化时，写入逻辑信号“1”。
在本申请所涉及的实施例中，例如上述图9所示的晶体管Tr可以选择NMOS(N-channel metal oxide semiconductor，N沟道金属氧化物半导体)管，或者可以选择PMOS(P-channel metal oxide semiconductor，P沟道金属氧化物半导体)管。
另外，在本申请所涉及的实施例中，晶体管Tr的漏极(drain)或源极(source)中的一极称为第一极，相应的另一极称为第二极，晶体管的控制端为栅极。晶体管的漏极和源极可以根据电流的流向而确定。
当图8C中的存储单元包括图9所示的晶体管Tr，和晶体管Tr电连接的多个电容器C时，图8C中的存储阵列芯片31的电路结构可以如图10所示。见图10，沿同一方向排布的多个存储单元的晶体管Tr的栅极可以与同一条字线WL电连接；以及，沿同一方向排布的多个存储单元的晶体管Tr的第二极可以与同一条位线BL电连接。这样，就会形成多条字线WL和多条位线BL，在一些示例中，图8A中的电路结构至少包括行解码器和列解码器，行解码器耦合至字线WL，并且被配置为导通或者截止晶体管Tr的栅极，列解码器耦合至位线BL，并且被配置为对存储单元进行读或写。
图11A和图11B示例性的给出了可以被应用在存储阵列芯片31中的存储单元的工艺结构图，图11B是图11A的A处放大图。见图11B，在该实施例中，一个存储单元包括一个晶体管Tr和多个电容器C，并且，多个电容器C和晶体管Tr，沿着与第一衬底311相垂直的方向堆叠。多个电容器C相对晶体管Tr靠近第一衬底311设置，晶体管Tr相对多个电容器C远离第一衬底311设置。
继续见图11B所示，每一个电容器C包括第一电容电极502、电容层503和第二电容电极504。在图11B中，示例性的展示了三个堆叠的电容器C，这些电容器C沿与第一衬底311相垂直的方向堆叠，并且，这些电容器C共用同一第二电容电极504。
在可以实现的工艺中，可以先在第一衬底311上堆叠交替排布的介质层501和第一电容电极502，在这些堆叠的介质层501和第一电容电极502内开设通孔，并在通孔内形成堆叠的电容层503和电极层，以使得电容器C共用同一第二电容电极504。
在另外一些实施例中，可以依照图11B所示结构，堆叠更多的电容器C；或者，如图11C所示，一个存储单元中设置一个电容器C和一个晶体管Tr。当一个存储单元包括一个晶体管Tr和一个电容器C时，形成的存储单元被称为1T1C存储单元。
再结合图11B和图11C，晶体管Tr包括第一极506、第二极504、沟道层505、栅介质层507和栅极508。其中，第一极506和第二极504沿与第一衬底311相垂直的方向排布，在一些工艺结构中，为了简化工艺结构，晶体管Tr的第二极504可以和电容器C的第二电容电极504共用同一电极。另外，沟道层505位于第一极506和第二极504之间，这样形成的沟道可以被称为与第一衬底311相垂直的垂直沟道。
还有，再如图12A和图12B，图12A和图12B示出了晶体管Tr的结构图，且图12B是图12A的M-M剖面图。一并结合图12A和图12B，栅极508环绕沟道层505，并且，栅极508和沟道层505之间被栅介质层507隔离开。这样形成的晶体管Tr结构可以被称为环栅全环绕栅型(Gate-All-Around，GAA)晶体管。
再参阅图11B和图11C，存储阵列芯片31中还包括字线WL和位线BL，其中，字线WL环绕栅极508设置，位线BL可以和晶体管Tr的第一极506共用同一膜层。
如图11A，沿第一方向(如图11A的X方向)排布的多个存储单元中，可以共用同一字线WL，比如，沿X排布的第一存储单元401中晶体管的栅极，和第二存储单元402中晶体管的栅极，与同一字线WL电连接，但是，与第一存储单元401电连接的位线BL，和第二存储单元402电连接的位线BL被电隔离开。
以及，如图11D，沿第二方向(如图11D的Y方向)排布的多个存储单元中，可以共用同一位线BL，比如，沿Y排布的第一存储单元401中晶体管的第二极，和第三存储单元403中晶体管 的第二极，与同一位线BL电连接，但是，第一存储单元401的字线WL，和第二存储单元402的字线WL被电隔离开。
继续参阅图11D，为了使得存储单元与焊点332电连接，在位线BL的背离第一衬底311的一侧设置导电通道(比如，硅通孔TSV)，导电通道的一端与位线BL连接，另一端与焊点332连接，即通过导电通道，实现存储单元与焊点332之间的互连。
还有，如图11D，电容器C的第一电容电极502通过导电通道(比如，硅穿孔TSV)与焊点332电连接。
在图11A至图11D中，为了清楚显示集成在第一衬底311上的存储单元，并未将层间介质示出，在实际产品中，图11D中的存储单元形成在层间介质中。该层间介质可以是一层，也可以是多层堆叠而成。
基于上述涉及的存储单元结构，可以看出，本申请实施例涉及的每一个存储单元中，晶体管Tr靠近焊点设置，而电容器C靠近衬底设置，那么，可以通过简单的电连接结构(如导电通道)将晶体管Tr与焊点332电连接，以及，电容器的一个电容电极也通过结构简单的电连接结构(如导电通道)与焊点332电连接。总之，当依照图11A至图11D布设晶体管Tr和电容器C时，晶体管Tr和电容器C均与焊点332的电连接结构比较简单，这样会简化整个存储阵列芯片31的布线结构，通过简化布线结构，可以为存储单元避让出更多的容置空间，以提升存储单元数量，进而提升存储密度和容量。
上述各个实施例提供的1TnC或者1T1C存储单元中，晶体管Tr的各个功能层、电容器C的各个功能层，以及字线WL和位线BL可以选择的材料具有多种，下述给出了可以选择的部分材料。
在可选择的材料中，晶体管Tr的第一极、第二极、栅极、字线WL和位线BL的材料均为导电材料，例如金属材料。在可选择的实施方式中，可以为TiN(氮化钛)、Ti(钛)、Au(金)、W(钨)、Mo(钼)、In-Ti-O(ITO，氧化铟锡)、Al(铝)、Cu(铜)、Ru(钌)、Ag(银)等导电材料中的一种或多种。
在可选择的材料中，晶体管Tr的沟道层505可以选择Si(硅)、poly-Si(p-Si，多晶硅)、amorphous-Si(a-Si，非晶硅)、In-Ga-Zn-O(IGZO，铟镓锌氧化物)多元化合物、ZnO(氧化锌)、ITO(氧化铟锡)、TiO2(二氧化钛)、MoS2(二硫化钼)、WS2(二硫化钨)、石墨烯、黑磷等半导体材料中的一种或多种。
上述的晶体管Tr栅介质层507的材料可以SiO2(二氧化硅)、Al2O3(氧化铝)、HfO2(二氧化铪)、ZrO2(氧化锆)、TiO2(二氧化钛)、Y2O3(三氧化二钇)和Si3N4(氮化硅)等绝缘材料中的一种或多种。
电容器C中的第一电容电极和第二电容电极均为导电材料。在可以选择的材料中，可以为TiN(氮化钛)、Ti(钛)、Au(金)、W(钨)、Mo(钼)、In-Ti-O(ITO，氧化铟锡)、Al(铝)、Cu(铜)、Ru(钌)、Ag(银)等导电材料中的一种或多种。
电容器C中的电容层可以选择可以为SiO2、Al2O3、HfO2、ZrO2、TiO2、Y2O3、Si3N4、HAO等绝缘材料，也可以为ZrO2,HfO2,Al掺杂HfO2，Si掺杂HfO2，Zr参杂HfO2，La掺杂HfO2，Y掺杂HfO2等铁电材料，或者基于该材料的进行其他元素掺杂的材料以及它们的任意组合。
上述结合附图介绍了本申请实施给出的包含存储阵列芯片31和控制电路芯片32的存储器，下面结合附图详细介绍本申请实施例给出的制备方法，以制得包含存储阵列芯片31和控制电路芯片32的存储器，具体见下述。
图13示例性的给出了制备存储器的流程框图。
步骤S1：提供存储阵列芯片和控制电路芯片，存储阵列芯片包括第一衬底、形成在第一衬底一侧的多个存储单元，每一个存储单元包括晶体管、与晶体管电连接的至少一个电容器，多个存储单元的背离第一衬底的一侧具有第一焊点，控制电路芯片包括第二衬底、形成在第二衬底一侧的电路结构，电路结构的背离第二衬底的一侧具有第二焊点。
即就是，在该实施例中，可以采用彼此独立的工艺分别制得存储阵列芯片和控制电路芯片，这样，就可以避免工艺不兼容，相互制约的影响。从而，就可以采用先进的工艺制得存储真理，以及，采用先进的工艺制得控制电路芯片。
另外，在可以实现的工艺在，制备存储阵列芯片和制备控制电路芯片可以同步进行，以缩短存储器的制造周期。
步骤S2：将多个存储单元和电路结构朝向彼此，第一焊点与第二焊点键合，形成连接存储阵列芯片和控制电路芯片的键合结构，使得电路结构通过键合结构控制多个存储单元的读写。
这样的话，电路结构就可以通过键合结构与存储单元互连，实现控制电路芯片对存储单元读写操作的控制。
下面结合附图对上述步骤S1和步骤S2所涉及的具体工艺流程进行介绍。
图14A至图14F给出了制得本申请实施例一种存储阵列芯片的工艺过程中每一步骤完成后的工艺结构。
如图14A，在第一衬底311上堆叠多层介质层601和多层导电层602，且多层介质层601和多层导电层602呈交替堆叠。
这些介质层601可以选择SiO2(二氧化硅)、Al2O3(氧化铝)、HfO2(二氧化铪)、ZrO2(氧化锆)、TiO2(二氧化钛)、Y2O3(三氧化二钇)和Si3N4(氮化硅)等绝缘材料中的一种或多种。
导电层602可以选择TiN(氮化钛)、Ti(钛)、Au(金)、W(钨)、Mo(钼)、In-Ti-O(ITO，氧化铟锡)、Al(铝)、Cu(铜)、Ru(钌)、Ag(银)等导电材料中的一种或多种。
其中，介质层601的层数和导电层602的层数相等。比如，需要制得1T3C存储单元时，就可以交替堆叠三层介质层601和三层导电层602；再比如，需要制得1T1C存储单元时，就可以堆叠一层介质层601和一层导电层602。
如图14B，对多层介质层601和多层导电层602进行刻蚀，形成阶梯结构。
具体的，见图14B，多层介质层601和多层导电层602可以被划分为多组功能层，相邻的一层介质层601和导电层602为一组功能层，比如，包括N层介质层601和N层导电层602时，可以包括N组功能层，并且，沿着远离第一衬底311的方向，N组功能层沿第一方向的尺寸逐渐变小，以形成阶梯状，且每一组功能层中的介质层601和导电层602在第一方向上的尺寸相等，该第一方向是平行于第一衬底311的方向。
也可以理解为：沿着远离第一衬底311的方向，多层导电层602呈阶梯状排布，相邻两个导电层602中，远离第一衬底311的导电层602在第一衬底311上的正投影，位于靠近第一衬底311的导电层602在第一衬底311上的正投影边界内。
这样，靠近第一衬底311的导电层602的外缘，相比远离第一衬底311的导电层的外缘凸出。
如图14C，开设贯通这些多层介质层601和多层导电层602的通孔603，且每一个通孔603贯通至第一衬底311。
如图14D，在每一个通孔603内依次填充电容材料和导电材料，以形成电容层503和电极，可以把导电层602形成的电极称为电容器的第一电容电极502，位于通孔内的电极称为电容器的第二电容电极504。
比如，当需要制得铁电电容时，图14D中，可以填充的电容材料可以选择ZrO2,HfO2,Al掺杂HfO2，Si掺杂HfO2，Zr参杂HfO2，La掺杂HfO2，Y掺杂HfO2等铁电材料。
如图14E，形成晶体管Tr的沟道层505、栅介质层507和栅极508，且栅极508环绕沟道层505设置，以及，形成字线WL和位线BL。
如图14F，形成贯通层间介质(图中未示出)的导电通道，以及，形成焊点332，使得电容器C的第一电容电极通过导电通道与焊点332电连接，位线BL通过导电通道与焊点332电连接。
如图14F，由于在图14B中，使得多层导电层呈阶梯状结构，那么，可以将导电通道设置在导电层的边缘，避免占用存储单元所处的空间。
图14A至图14F示例性的给出了制得一种包含1TnC存储单元的存储阵列芯片结构，在制得此存储阵列芯片时，不需要考虑工艺是不是与制备控制电路芯片的工艺要兼容，也不需要考虑会不会影响控制电路芯片的性能，所以，可以利用先进的工艺手段制得此种存储阵列芯片。
类似的，可以利用先进的工艺制得控制电路芯片，再将控制电路芯片与图14A至图14F制得的存储阵列芯片，进行键合，以制得三维堆叠的存储器结构。
在制备图14F中所示的环栅晶体管时，可以采用下述图15A至图15F所示的工艺流程。
如图15A，形成依次堆叠的介质层601、导电层602和介质层601。
如图15B，开设贯通介质层601、导电层602和介质层601的通孔。
如图15C和图15D，在通孔内依次沉积栅介质材料和沟道材料。在一些实现工艺中，如图15C和图15D，会在位于导电层602之上的介质层601的表面也沉积有栅介质材料和沟道材料。
如图15E，将位于导电层602之上的介质层601的表面上的栅介质材料和沟道材料去除掉。
如图15F，去除位于导电层602两侧的介质层，则该导电层602环绕沟道层505，形成环栅结构，该导电层602可以作为晶体管的栅极508，也作为存储阵列芯片中的字线WL。
图15A至图15F示例性的给出了一种制备环栅晶体管的方法，本申请实施例涉及的环栅晶体管，也可以采用其他制备工艺。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种存储器，其特征在于，包括：
    存储阵列芯片，包括第一衬底、形成在所述第一衬底一侧的多个存储单元；
    控制电路芯片，包括第二衬底、形成在所述第二衬底一侧的电路结构，所述电路结构用于控制所述多个存储单元的读写；
    键合结构，所述多个存储单元和所述电路结构朝向彼此，并通过形成在所述多个存储单元和所述电路结构之间的所述键合结构电连接；
    每一个所述存储单元包括晶体管、与所述晶体管电连接的至少一个电容器；
    所述晶体管和所述至少一个电容器沿着与所述第一衬底相垂直的方向堆叠，所述晶体管相对所述至少一个电容器靠近所述键合结构设置。
  2. 根据权利要求1所述的存储器，其特征在于，所述至少一个电容器的外围设置有垂直于所述第一衬底的第一导电通道，每一个所述电容器通过所述第一导电通道与所述键合结构电连接。
  3. 根据权利要求2所述的存储器，其特征在于，每一个所述存储单元包括多个所述电容器，每一个所述电容器包括第一电容电极、电容层和第二电容电极；
    沿与所述第一衬底相垂直的方向，所述第一衬底上交替堆叠有多层介质层和多层导电层；
    所述第二电容电极贯通交替堆叠的所述多层介质层和所述多层导电层，形成多个所述电容器的共用第二电容电极；
    所述电容层贯通交替堆叠的所述多层介质层和所述多层导电层，形成多个所述电容器的共用电容层，且所述共用电容层环绕所述共用第二电容电极；
    环绕在所述电容层外围的至少部分所述导电层，形成所述第一电容电极，每一个所述第一电容电极通过所述第一导电通道，与所述键合结构电连接。
  4. 根据权利要求3所述的存储器，其特征在于，沿与所述第一衬底相平行排布的多个所述电容器的所述第一电容电极连接呈一体。
  5. 根据权利要求3或4所述的存储器，其特征在于，沿着远离所述第一衬底的方向，所述多层导电层呈阶梯状排布，相邻两个所述导电层中，远离所述第一衬底的所述导电层在所述第一衬底上的正投影，位于靠近所述第一衬底的所述导电层在所述第一衬底上的正投影边界内；
    所述第一导电通道设置在所述导电层的边缘。
  6. 根据权利要求1-5中任一项所述的存储器，其特征在于，所述晶体管的靠近所述键合结构的一侧具有垂直于所述第一衬底的第二导电通道，所述晶体管通过所述第二导电通道与所述键合结构电连接。
  7. 根据权利要求6所述的存储器，其特征在于，所述存储阵列芯片还包括：第一电极线和第二电极线，所述第一电极线与所述晶体管的栅极电连接，所述第二电极线与所述晶体管的第一极电连接，所述晶体管的第二极与所述电容器电连接。
  8. 根据权利要求7所述的存储器，其特征在于，所述晶体管的所述第一极和所述第二极沿与所述第一衬底相垂直的方向排布，所述晶体管的沟道层位于所述第一极和所述第二极之间，且所述第一极相对所述第二极远离所述电容器设置，所述第二电极线与所述第一极共用同一电极层，所述第二电极线通过所述第二导电通道与所述键合结构电连接。
  9. 根据权利要求1-8中任一项所述的存储器，其特征在于，所述多个存储单元的背离所述第一衬底的一侧形成有第一焊点，所述电路结构的背离所述第二衬底的一侧形成有第二焊点，所述第一焊点和所述第二焊点键合形成所述键合结构。
  10. 根据权利要求1-9中任一项所述的存储器，其特征在于，所述存储阵列芯片为DRAM存储阵列芯片，或者，所述存储阵列芯片为铁电存储阵列芯片。
  11. 一种存储器的制备方法，其特征在于，所述制备方法包括：
    提供存储阵列芯片和控制电路芯片，所述存储阵列芯片包括第一衬底、形成在所述第一衬底一侧的多个存储单元，每一个所述存储单元包括晶体管、与所述晶体管电连接的至少一个电容器，所述多个存储单元的背离所述第一衬底的一侧具有第一焊点，所述控制电路芯片包括第二衬底、形成在所述第二衬底一侧的电路结构，所述电路结构的背离所述第二衬底的一侧具有第二焊点；
    将所述多个存储单元和所述电路结构朝向彼此，所述第一焊点与所述第二焊点键合，形成连接所述存储阵列芯片和所述控制电路芯片的键合结构，使得所述电路结构通过所述键合结构控制所述多个存储单元的读写。
  12. 根据权利要求11所述的存储器的制备方法，其特征在于，采用混合键合Hybrid Bonding工艺键合所述第一焊点和所述第二焊点。
  13. 根据权利要求11或12所述的存储器的制备方法，其特征在于，所述第一焊点与所述第二焊点键合时，键合温度小于或等于450℃。
  14. 一种存储阵列芯片的制备方法，其特征在于，所述制备方法包括：
    在衬底上形成至少一个电容器；
    在所述至少一个电容器的背离所述衬底一侧形成晶体管，所述存储阵列芯片中的每一个存储单元包括所述至少一个电容器和所述晶体管；
    在所述至少一个电容器的外围形成垂直于所述衬底的第一导电通道，在所述晶体管的背离所述衬底一侧形成垂直于所述衬底的第二导电通道；
    在所述存储单元的背离所述衬底一侧形成焊点，使得所述至少一个电容器通过所述第一导电通道与所述焊点电连接，以及，所述晶体管通过所述第二导电通道与所述焊点电连接。
  15. 根据权利要求14所述的存储阵列芯片的制备方法，其特征在于，在所述衬底上形成所述至少一个电容器包括：
    在所述衬底上交替堆叠多层介质层和多层导电层；
    开设贯通所述多层介质层和所述多层导电层的通孔；
    在所述通孔内依次填充电容材料和电极材料，以在所述通孔内形成电容层和电容电极，所述电容层形成在所述电容电极和所述通孔侧壁之间，以制得多个所述电容器，所述电容层形成多个所述电容器的共用电容层，所述电容电极形成多个所述电容器的共用第二电容电极，环绕在所述电容层外围的至少部分所述导电层，形成所述电容器的第一电容电极。
  16. 根据权利要求15所述的存储阵列芯片的制备方法，其特征在于，在所述衬底上交替堆叠所述多层介质层和所述多层导电层之后，所述制备方法还包括：
    对所述多层介质层和所述多层导电层的边缘进行刻蚀，沿着远离所述衬底的方向，所述多层导电层呈阶梯状排布，相邻两个所述导电层中，远离所述衬底的所述导电层在所述衬底上的正投影，位于靠近所述衬底的所述导电层在所述衬底上的正投影边界内。
  17. 根据权利要求16所述的存储阵列芯片的制备方法，其特征在于，对所述多层介质层和所述多层导电层的边缘进行刻蚀，使得所述多层导电层呈阶梯状排布后，所述制备方法还包括：
    在每一层所述导电层的边缘设置所述第一导电通道，使得所述导电层通过所述第一导电通道能够与所述焊点电连接。
  18. 一种电子设备，其特征在于，包括：
    处理器；
    如权利要求1～10中任一项所述的存储器，或者，或者如权利要求11～13中任一项所述的存储器的制备方法制得的存储器；
    所述存储器用于存储所述处理器产生的数据。
PCT/CN2023/102773 2022-11-28 2023-06-27 存储器、电子设备及存储器的制备方法 Ceased WO2024113802A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020257017546A KR20250093562A (ko) 2022-11-28 2023-06-27 메모리, 전자 장치 및 메모리 제조 방법
EP23895966.2A EP4618710A4 (en) 2022-11-28 2023-06-27 MEMORY, ELECTRONIC DEVICE AND MEMORY PREPARATION METHOD
US19/217,400 US20250285658A1 (en) 2022-11-28 2025-05-23 Memory, electronic device, and memory manufacturing method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211501780.9A CN118102712A (zh) 2022-11-28 2022-11-28 存储器、电子设备及存储器的制备方法
CN202211501780.9 2022-11-28

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US19/217,400 Continuation US20250285658A1 (en) 2022-11-28 2025-05-23 Memory, electronic device, and memory manufacturing method

Publications (1)

Publication Number Publication Date
WO2024113802A1 true WO2024113802A1 (zh) 2024-06-06

Family

ID=91142890

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/102773 Ceased WO2024113802A1 (zh) 2022-11-28 2023-06-27 存储器、电子设备及存储器的制备方法

Country Status (5)

Country Link
US (1) US20250285658A1 (zh)
EP (1) EP4618710A4 (zh)
KR (1) KR20250093562A (zh)
CN (1) CN118102712A (zh)
WO (1) WO2024113802A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240213220A1 (en) * 2022-12-23 2024-06-27 Samsung Electronics Co., Ltd. Method, apparatus, and system with integrated circuit manufacturing

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN121510592A (zh) * 2024-08-05 2026-02-10 华为技术有限公司 存储芯片及其制备方法、存储器、电子设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109192734A (zh) * 2018-09-28 2019-01-11 长江存储科技有限责任公司 3d存储器件
US20190043868A1 (en) * 2018-06-18 2019-02-07 Intel Corporation Three-dimensional (3d) memory with control circuitry and array in separately processed and bonded wafers
CN109326557A (zh) * 2018-09-28 2019-02-12 长江存储科技有限责任公司 三维存储器结构及制造方法
US20220208778A1 (en) * 2020-12-26 2022-06-30 Intel Corporation 3d-ferroelectric random (3d-fram) with buried trench capacitors

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10600468B2 (en) * 2018-08-13 2020-03-24 Wuxi Petabyte Technologies Co, Ltd. Methods for operating ferroelectric memory cells each having multiple capacitors
US10886286B2 (en) * 2018-09-28 2021-01-05 Intel Corporation Vertical memory control circuitry located in interconnect layers
JP7331119B2 (ja) * 2019-04-15 2023-08-22 長江存儲科技有限責任公司 複数の機能性チップを伴う三次元ｎａｎｄメモリデバイスの集積
US20210111179A1 (en) * 2019-10-11 2021-04-15 Intel Corporation 3d-ferroelectric random access memory (3d-fram)

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190043868A1 (en) * 2018-06-18 2019-02-07 Intel Corporation Three-dimensional (3d) memory with control circuitry and array in separately processed and bonded wafers
CN109192734A (zh) * 2018-09-28 2019-01-11 长江存储科技有限责任公司 3d存储器件
CN109326557A (zh) * 2018-09-28 2019-02-12 长江存储科技有限责任公司 三维存储器结构及制造方法
US20220208778A1 (en) * 2020-12-26 2022-06-30 Intel Corporation 3d-ferroelectric random (3d-fram) with buried trench capacitors

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4618710A1

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240213220A1 (en) * 2022-12-23 2024-06-27 Samsung Electronics Co., Ltd. Method, apparatus, and system with integrated circuit manufacturing

Also Published As

Publication number Publication date
US20250285658A1 (en) 2025-09-11
CN118102712A (zh) 2024-05-28
EP4618710A4 (en) 2026-04-29
EP4618710A1 (en) 2025-09-17
KR20250093562A (ko) 2025-06-24

Similar Documents

Publication Publication Date Title
US12170258B2 (en) Memory devices having vertical transistors and methods for forming the same
US20250285658A1 (en) Memory, electronic device, and memory manufacturing method
CN117546624A (zh) 存储器、存储器的控制方法和形成方法、电子设备
US20240121942A1 (en) Memory and forming method thereof, and electronic device
EP4461105A1 (en) Memory devices having vertical transistors and methods for forming the same
US20260011350A1 (en) Three-dimensional memory array, memory, and electronic device
CN117597735A (zh) 存储器件和用于形成存储器件的方法
WO2023004598A1 (zh) 铁电存储器及其形成方法、电子设备
CN119769185B (zh) 一种三维存储阵列、存储器及电子设备
US20260032884A1 (en) Three-Dimensional Memory Array and Preparation Method Thereof, Memory, and Electronic Device
US20240206148A1 (en) Memory devices and methods for forming the same
EP4449835A1 (en) Memory devices having vertical transistors and methods for forming thereof
US20250185254A1 (en) Three-Dimensional Memory Array, Memory, and Electronic Device
CN117750777B (zh) 一种三维存储阵列、存储器及电子设备
CN121057192A (zh) 一种存储阵列、存储器及电子设备
CN119922900A (zh) 静态随机存取存储阵列、存储器、存储阵列的制备方法
WO2023221925A1 (en) Memory devices having vertical transistors and methods for forming the same
CN119922901A (zh) 静态随机存取存储阵列、存储器、存储阵列的控制方法
WO2024113824A1 (zh) 一种存储阵列、存储器及电子设备
TW202610428A (zh) 記憶體裝置及其形成方法
WO2025107556A1 (zh) 存储阵列及其制备方法、存储器、电子设备
CN121368111A (zh) 存储阵列及其制备方法、存储器和电子设备
CN121888594A (zh) 一种存储阵列及其制作方法、存储器、电子设备
WO2025123345A1 (zh) 一种存储阵列及其制作方法、存储器以及电子设备
WO2025175754A1 (zh) 存储阵列及其制备方法、存储装置、电子设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23895966

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 20257017546

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 1020257017546

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2023895966

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1020257017546

Country of ref document: KR

ENP Entry into the national phase

Ref document number: 2023895966

Country of ref document: EP

Effective date: 20250612

NENP Non-entry into the national phase

Ref country code: DE

WWP Wipo information: published in national office

Ref document number: 2023895966

Country of ref document: EP