WO2024125174A1 - 芯片集成结构及其制备方法、电子设备 - Google Patents

芯片集成结构及其制备方法、电子设备 Download PDF

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Publication number
WO2024125174A1
WO2024125174A1 PCT/CN2023/130829 CN2023130829W WO2024125174A1 WO 2024125174 A1 WO2024125174 A1 WO 2024125174A1 CN 2023130829 W CN2023130829 W CN 2023130829W WO 2024125174 A1 WO2024125174 A1 WO 2024125174A1
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Prior art keywords
chip
layer
structure layer
layers
chip structure
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English (en)
French (fr)
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WO2024125174A9 (zh
Inventor
刘曙光
张师伟
景蔚亮
张春雨
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to EP23902374.0A priority Critical patent/EP4625493A4/en
Publication of WO2024125174A1 publication Critical patent/WO2024125174A1/zh
Publication of WO2024125174A9 publication Critical patent/WO2024125174A9/zh
Priority to US19/237,436 priority patent/US20250309195A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D80/00—Assemblies of multiple devices comprising at least one device covered by this subclass
    • H10D80/30—Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups H10D84/00 - H10D86/00, e.g. assemblies comprising integrated circuit processor chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P58/00—Singulating wafers or substrates into multiple chips, i.e. dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
    • H10W46/503—Located in scribe lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/10—Configurations of laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

Definitions

  • the present application relates to the field of chip technology, and in particular to a chip integrated structure and a preparation method thereof, and an electronic device.
  • 3D IC three-dimensional integrated circuit
  • 3D IC refers to the vertical integration and stacking of multiple chips in three-dimensional space, which can reduce the package size, improve chip performance, and improve chip integration.
  • 3D IC technology has been successfully applied by many semiconductor manufacturers to produce CMOS (complementary metal oxide semiconductor) image sensors, NAND flash, high bandwidth memory (HBM) and other products, and has greatly improved product performance.
  • CMOS complementary metal oxide semiconductor
  • NAND flash high bandwidth memory
  • HBM high bandwidth memory
  • the embodiments of the present application provide a chip integration structure and a preparation method thereof, and an electronic device, which are used to improve the problem that the spacing between adjacent functional chips in the same stacking layer of the current chip is large, so that the number of functional chips set per unit area is reduced, which in turn leads to poor performance of the stacking layer.
  • a chip integration structure comprising: a packaging substrate and a first chip structure layer.
  • the first chip structure layer is located on one side of the packaging substrate and is electrically connected to the packaging substrate;
  • the first chip structure layer comprises a dicing road structure and a plurality of first bare chips;
  • the dicing road structure connects the plurality of first bare chips and electrically separates the plurality of first bare chips;
  • the first bare chips have electrical functions.
  • the first chip structure layer includes a cutting road structure and a plurality of first bare chips, the cutting road structure connects the plurality of first bare chips, and electrically separates the plurality of first bare chips, and the first bare chips have electrical functions.
  • electrical function means that the first bare chip has a device and can be powered on.
  • the first bare chip may include a digital chip, an analog chip, an optical chip, and the like.
  • Each first bare chip is a bare chip, that is, the plurality of first bare chips are a plurality of bare chips located in the same wafer, and the adjacent bare chips are connected by a cutting road structure, that is, the cutting road area between the plurality of first bare chips is not cut, so the cutting road structure is retained.
  • the number of first bare die per unit area in the first chip structure layer increases, which is beneficial to improving the storage capacity of the first chip structure layer, and further helps to improve the storage capacity of the chip integrated structure;
  • the first bare die includes a logic chip, the number of first bare die per unit area in the first chip structure layer increases, which is beneficial to improving the computing processing rate of the first chip structure layer, and further helps to improve the computing processing rate of the chip integrated structure.
  • multiple first bare chips are multiple bare chips located in the same wafer, multiple first bare chips can be obtained by one cutting, which is beneficial to improving the processing efficiency of the chip integration structure and further increasing the output of the chip integration structure per unit time.
  • the first die includes a first substrate; the dicing structure includes a first connection substrate; the first connection substrate is connected to the first substrate and is arranged in the same layer.
  • adjacent first substrates can be connected through the first connection substrate.
  • "arranged in the same layer” means that the first substrate and the first connection substrate use the same film forming process to form a film layer for forming a specific pattern, and then use the same mask to form a layer structure through a single patterning process.
  • the single patterning process may include multiple exposure, development or etching processes, and the material of the specific pattern in the formed layer structure is the same.
  • the first die further includes a sealing ring, which is located at an edge region of the first die and is adjacent to the dicing path structure.
  • the sealing ring includes a plurality of stacked sealing layers and a plurality of sealing plugs, one sealing plug is located between two adjacent sealing layers, and the sealing plug is in contact with the two adjacent sealing layers.
  • the first bare chip further includes a plurality of first insulating layers, the plurality of first insulating layers are located on the first substrate, and the plurality of first insulating layers are stacked.
  • the cutting road structure further includes a plurality of first insulating connection layers, the plurality of first insulating connection layers are located on the first connection substrate, and the plurality of first insulating connection layers are stacked. Among them, the plurality of first insulating connection layers are connected one-to-one with the plurality of first insulating layers, and the correspondingly connected first insulating connection layers are arranged in the same layer as the first insulating layer.
  • the corresponding two first insulating layers in adjacent first bare chips are connected by corresponding first insulating connection layers.
  • “arranged in the same layer” means that the first insulating layer and the first insulating connection layer are formed by the same film forming process to form a film layer for forming a specific pattern, and then the layer structure is formed by a single patterning process using the same mask template, and the single patterning process may include multiple exposure, development or etching processes, and the material of the specific pattern in the formed layer structure is the same.
  • the first bare chip also includes a plurality of first conductive layers, the plurality of first conductive layers are located on the first substrate, and the plurality of first conductive layers are stacked.
  • the cutting path structure also includes a plurality of first insulating connection layers, the plurality of first insulating connection layers are located on the first connection substrate, and the plurality of first insulating connection layers are stacked.
  • the number of the plurality of first insulating connection layers is the same as the number of the plurality of conductive layers.
  • the first conductive layer includes a multilayer metal circuit, which is used to electrically connect a plurality of electronic components together to form a circuit structure of the first bare chip.
  • the electronic components may include, for example, transistors, capacitors, resistors, and the like.
  • the stacked first conductive layer and the first insulating layer together constitute a functional layer of the first bare chip so as to realize the storage, logic or other functions of the first bare chip.
  • the cutting path structure includes multiple metal layers, the multiple metal layers are located on the first connection substrate, and the multiple metal layers are stacked.
  • the multiple metal layers correspond one-to-one to some of the multiple first conductive layers, and the corresponding metal layers and the first conductive layers are arranged in the same layer and are electrically isolated.
  • multiple metal layers can be arranged on the first connection substrate, and the multiple metal layers can be stacked and are located on the same side of the first connection substrate as the first insulating connection layer.
  • the multiple metal layers correspond one-to-one to some of the multiple first conductive layers and do not contact, so that the corresponding metal layers and the first conductive layers are electrically isolated.
  • arranged in the same layer means that the metal layer and the first conductive layer are formed by the same film forming process to form a film layer for forming a specific pattern, and then the layer structure is formed by a single patterning process using the same mask template.
  • the single patterning process may include multiple exposure, development or etching processes, and the material of the specific pattern in the formed layer structure is the same.
  • At least a portion of the plurality of metal layers constitutes a test structure.
  • the test structure (Testkey) is tested by a specific test machine to reflect process fluctuations during the manufacturing process of the first die and detect whether an abnormality occurs in the production line.
  • the cutting path structure includes a positioning mark.
  • at least one positioning mark is provided on the first connection substrate; and/or, at least one positioning mark is provided on at least one first insulating connection layer.
  • the number of positioning marks may be only one. Among them, the positioning mark may be provided on the first connection substrate and located between the first connection substrate and the first insulating connection layer; or, the positioning mark may be stacked with the first insulating connection layer and located on the same side of the first connection substrate as the first insulating connection layer. In some other embodiments, the number of positioning marks may be multiple.
  • multiple positioning marks may all be located on the first connection substrate or any first insulating connection layer; or, among the multiple positioning marks, a part of the positioning marks are located on the first connection substrate, and another part of the positioning marks are stacked with the first insulating connection layer (for example, one positioning mark may be located on one first insulating connection layer, which is not specifically limited in this embodiment).
  • the cutting road structure includes a first sub-cutting road structure, the first sub-cutting road structure extends along a first direction, and the length of the first sub-cutting road structure along a second direction ranges from 80 microns to 120 microns; wherein the first direction is perpendicular to the second direction and both are parallel to the package substrate; and/or, the cutting road structure includes a second sub-cutting road structure; wherein the first sub-cutting road structure extends along the first direction, the second sub-cutting road structure extends along the second direction, and the length of the second sub-cutting road structure along the first direction ranges from 80 microns to 120 microns; wherein the first direction is perpendicular to the second direction and both are parallel to the package substrate.
  • the number of first chip structure layers is multiple, and the multiple first chip structure layers are stacked along a third direction, and the third direction is perpendicular to the package substrate. Among them, two adjacent first chip structure layers are electrically connected. So that each first chip structure layer is electrically connected to the package substrate.
  • By setting multiple first chip structure layers it is beneficial to further improve the performance of the chip integration structure. For example, when the first bare chip includes storage capacity, it is beneficial to improve the storage capacity of the chip integration structure; when the first bare chip includes a logic chip, it is beneficial to improve the computing processing rate of the chip integration structure.
  • the chip integration structure further includes a first redistribution layer.
  • the first redistribution layer is located between two adjacent first chips. Between structural layers.
  • the first redistribution layer includes a first part and a second part which are stacked, the first part is electrically connected to one first chip structure layer, and the second part is electrically connected to another first chip structure layer.
  • the first part can be located above the first redistribution layer, and is used to rearrange the wiring of the first chip structure layer located above in the two adjacent first chip structure layers; correspondingly, the second part can be located below the first redistribution layer, and is used to rearrange the wiring of the first chip structure layer located below in the two adjacent first chip structure layers.
  • the two adjacent first chip structure layers can be electrically connected through the first redistribution layer.
  • the material of the first part and the second part can include materials, for example, one or more conductive materials selected from copper, aluminum, nickel, gold, silver, titanium, cobalt, tungsten, etc., or other conductive alloy materials.
  • the first redistribution layer also includes a first bonding portion and a second bonding portion, wherein the first bonding portion is located on a side of the first part close to the second part, and the second bonding portion is located on a side of the second part close to the first part, and the second part is bonded to the first part through the first bonding portion and the second bonding portion.
  • bonding is a technology that directly combines two homogeneous or heterogeneous semiconductor materials with clean surfaces and atomically flat surfaces under certain conditions after surface cleaning and activation treatment, and bonds the wafers into one through van der Waals forces, molecular forces, or even atomic forces.
  • the bonding method may be hybrid bonding.
  • the first bonding portion is located on a side of the first part close to the second part
  • the second bonding portion is located on a side of the second part close to the first part.
  • the number of first bonding portions is multiple
  • the number of second bonding portions is multiple
  • the multiple first bonding portions and the multiple second bonding portions are arranged in a one-to-one correspondence.
  • the cross-sectional area of one end of the first bonding portion close to the second portion is larger than the cross-sectional area of one end close to the first portion; and/or, the cross-sectional area of one end of the second bonding portion close to the first portion is larger than the cross-sectional area of one end close to the second portion.
  • cross-sectional area refers to the cross-sectional area of the first bonding portion and/or the second bonding portion along the first direction.
  • the first bonding portion includes a first connection pad and a second connection pad arranged in a stacked manner, the first connection pad is close to the first part relative to the second connection pad, and the cross-sectional area of the second connection pad is larger than the cross-sectional area of the first connection pad in a direction parallel to the package substrate.
  • the second bonding portion includes a third connection pad and a fourth connection pad arranged in a stacked manner, the third connection pad is close to the second part relative to the fourth connection pad, and the cross-sectional area of the fourth connection pad is larger than the cross-sectional area of the third connection pad in a direction parallel to the package substrate.
  • the cross-sectional area of the second connection pad is larger than the cross-sectional area of the first connection pad, it is convenient for the first bonding portion to contact the second bonding portion through the second connection pad; similarly, since the cross-sectional area of the fourth connection pad is larger than the cross-sectional area of the third connection pad, it is convenient for the second bonding portion to contact the first bonding portion through the fourth connection pad.
  • the second connection pad it is convenient for the second connection pad to contact the fourth connection pad, it is convenient to achieve bonding between the first bonding portion and the second bonding portion, and ensure the conductive performance of the first redistribution layer.
  • the first chip structure layer farthest from the package substrate is the top structure layer
  • the first chip structure layer located between the top structure layer and the package substrate is the middle structure layer.
  • the middle structure layer includes a first conductive via that penetrates the first bare chip along a third direction
  • the top structure layer is also electrically connected to the first conductive via of the middle structure layer through the redistribution layer.
  • the first part is electrically connected to the first conductive layer in the top structure layer
  • the second part is electrically connected to the first conductive via in the middle structure layer. It can be seen that by setting the first conductive via, the electrical connection between the top structure layer and the middle structure layer can be achieved.
  • the chip integrated structure also includes a second chip structure layer, the second chip structure layer is stacked with the first chip structure layer, and the second chip structure layer includes a structural chip, a second bare chip, and an isolation structure between the structural chip and the second bare chip.
  • the second bare chip includes a second substrate and a functional layer located on the second substrate, and the first chip structure layer is electrically connected to the functional layer of the second bare chip.
  • the second chip structure layer can be located between the first chip structure layer and the packaging substrate.
  • the second chip structure layer can also be located on the side of the first chip structure layer away from the packaging substrate, and the embodiments of the present application are not limited to this.
  • the material of the isolation structure includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.
  • the second chip structure layer can include multiple isolation structures, and the multiple isolation structures can be prepared and formed simultaneously. For example, after the structure chip and the second die are spaced apart, There is a gap between the structural chip and the second bare chip, and an isolation material may be filled in the gap to form an isolation structure.
  • the chip integrated structure further includes a second redistribution layer.
  • the second chip structure layer is located between the first chip structure layer and the packaging substrate, the second redistribution layer is located between the first chip structure layer and the second chip structure layer, the first chip structure layer and the second chip structure layer are electrically connected through the second redistribution layer, and the second chip structure layer is electrically connected to the packaging substrate.
  • the second chip structure layer may be located between the first chip structure layer and the packaging substrate, where the first chip structure layer is the first chip structure layer closest to the packaging substrate among multiple first chip structure layers.
  • the second redistribution layer is located between the first chip structure layer and the second chip structure layer, and the first chip structure layer and the second chip structure layer are electrically connected through the second redistribution layer.
  • the structure of the second redistribution layer may be the same as the structure of the first redistribution layer, which is conducive to improving the regularity of the chip integrated structure and improving the preparation efficiency of the chip integrated structure.
  • the second bare chip further includes a second conductive via that penetrates the second substrate, the functional layer is close to the packaging substrate relative to the second substrate, and the functional layer is electrically connected to the packaging substrate.
  • One end of the second conductive via is electrically connected to the functional layer, and the other end of the second conductive via is electrically connected to the second redistribution layer.
  • the intermediate redistribution layer in the second connector can be used to rearrange the wiring in the functional layer so that the functional layer is electrically connected to the packaging substrate through the second connector.
  • the second bare chip further includes a second conductive via that penetrates the second substrate, the functional layer is away from the packaging substrate relative to the second substrate, and the functional layer is electrically connected to the second redistribution layer.
  • the functional layer is electrically connected to the second redistribution layer.
  • one end of the second conductive via is electrically connected to the functional layer, and the other end of the second conductive via is electrically connected to the packaging substrate.
  • the second bare chip can be electrically connected to the packaging substrate through the second connector, and one end of the second conductive via is electrically connected to the packaging substrate, one end of the second conductive via can be electrically connected to the second connector. Since one end of the second conductive via is electrically connected to the functional layer, one end of the second conductive via can be electrically connected to the first conductive layer of the functional layer.
  • electrical connection between the first chip structure layer, the second chip structure layer and the packaging substrate can be achieved.
  • a third die is also included, the third die is stacked with the first chip structure layer, and the third die is electrically connected to the package substrate.
  • the third die can be located between the first chip structure layer and the second chip structure layer, where the first chip structure layer is a first chip structure layer closest to the package substrate among the multiple first chip structure layers.
  • the third die is also electrically connected to the first chip structure layer and the second chip structure layer, respectively, so that the third die is electrically connected to the package substrate.
  • the third die includes a third substrate and a third conductive layer located on one side of the third substrate.
  • the stacking method between the third die and the first chip structure layer can be that the third substrate faces the functional layer (Back-to-Face, B2F).
  • a method for preparing a chip integrated structure comprising: providing a packaging substrate.
  • the first chip structure layer is arranged on one side of the packaging substrate, and the first chip structure layer is electrically connected to the packaging substrate.
  • the first bare chip when the first bare chip includes storage capacity, the number of first bare chips per unit area in the first chip structure layer increases, which is beneficial to increasing the storage capacity of the first chip structure layer, thereby increasing the storage capacity of the chip integrated structure; when the first bare chip includes a logic chip, the number of first bare chips per unit area in the first chip structure layer increases, which is beneficial to increasing the computing processing rate of the first chip structure layer, thereby increasing the computing processing rate of the chip integrated structure.
  • the number of first chip structure layers is multiple.
  • the first chip structure layer is arranged on one side of the packaging substrate, and the first chip structure layer is electrically connected to the packaging substrate, including: stacking multiple first chip structure layers in sequence on the packaging substrate, wherein, among the multiple first chip structure layers, the first chip structure layer closest to the packaging substrate is electrically connected to the packaging substrate, and any two adjacent first chip structure layers are electrically connected.
  • adjacent first chip structure layers can be electrically connected through a first redistribution layer.
  • a first redistribution layer can be set on the side of the first chip structure layer away from the packaging substrate. layer, and then a second first chip structure layer is arranged on a side of the first redistribution layer away from the packaging substrate... and so on.
  • the first chip structure layer before the first chip structure layer is disposed on one side of the packaging substrate and the first chip structure layer is electrically connected to the packaging substrate, it also includes: forming a second chip structure layer on a carrier; disposing the first chip structure layer on a side of the second chip structure layer away from the carrier, and electrically connecting the first chip structure layer to the second chip structure layer.
  • Disposing the first chip structure layer on one side of the packaging substrate and electrically connecting the first chip structure layer to the packaging substrate includes: removing the carrier; electrically connecting the side of the second chip structure layer away from the first chip structure layer to the packaging substrate.
  • forming a second chip structure layer on a carrier includes: selecting a structure chip from a first wafer and placing the selected structure chip on the carrier; selecting a second bare chip from a second wafer and placing the selected second bare chip on the carrier; forming an isolation structure between the structure chip and the second bare chip, the structure chip, the second bare chip and the isolation structure together forming the second chip structure layer.
  • the second chip structure layer can be formed on the carrier, thereby improving the performance of the chip integration structure.
  • the first chip structure layer before the first chip structure layer is disposed on one side of the packaging substrate and the first chip structure layer is electrically connected to the packaging substrate, it also includes: forming a second chip structure layer on the first chip structure layer, and electrically connecting the first chip structure layer to the second chip structure layer.
  • the first chip structure layer is disposed on one side of the packaging substrate, and the first chip structure layer is electrically connected to the packaging substrate, and it also includes: electrically connecting the side of the second chip structure layer away from the first chip structure layer to the packaging substrate.
  • forming a second chip structure layer on the first chip structure layer and electrically connecting the first chip structure layer to the second chip structure layer includes: selecting a structure chip from the first wafer, and setting the selected structure chip on the first chip structure layer, so that the structure chip is connected to the first chip structure layer; selecting a second bare chip from the second wafer, and setting the selected second bare chip on the first chip structure layer, so that the second bare chip is electrically connected to the first chip structure layer; forming an isolation structure between the structure chip and the second bare chip, and the structure chip, the second bare chip and the isolation structure together constitute the second chip structure layer.
  • the second chip structure layer can be formed on the first chip structure layer, thereby improving the performance of the chip integration structure.
  • an electronic device comprising a printed circuit board and a chip integration structure as in the above embodiment, wherein the chip integration structure is electrically connected to the printed circuit board.
  • the electronic device provided by the embodiment of the present application includes the chip integration structure as described above, and therefore has all the above-mentioned beneficial effects, which will not be described in detail here.
  • FIG1 is a structural diagram of an electronic device provided in an embodiment of the present application.
  • FIG2 is a structural diagram of a chip stacking structure provided by some current embodiments.
  • FIG3 is a structural diagram of a chip wafer provided by some current embodiments.
  • FIG4 is a structural diagram of a chip integration structure provided in an embodiment of the present application.
  • FIG5 is a top view of a first chip structure layer provided in an embodiment of the present application.
  • FIG6 is a structural diagram of a wafer provided in an embodiment of the present application.
  • FIG7 is a cross-sectional view of a first chip structure layer provided in an embodiment of the present application.
  • FIG8 is a cross-sectional view of the first chip structure layer along the S1-S2 section line in FIG7;
  • FIG9 is a cross-sectional view of a first chip structure layer provided in an embodiment of the present application.
  • FIG10 is a top view of another first chip structure layer provided in an embodiment of the present application.
  • FIG11 is a structural diagram of another chip integration structure provided in an embodiment of the present application.
  • FIG12 is a structural diagram of another chip integration structure provided in an embodiment of the present application.
  • FIG13 is a structural diagram of another chip integration structure provided in an embodiment of the present application.
  • FIG14 is a structural diagram of another chip integration structure provided in an embodiment of the present application.
  • FIG15 is a flowchart of a method for preparing a chip integrated structure provided in an embodiment of the present application.
  • FIG16 is a flowchart of the steps of another method for preparing a chip integrated structure provided in an embodiment of the present application.
  • FIG17 is a structural diagram of a preparation process in a method for preparing the chip integrated structure in FIG16 ;
  • FIG18 is a flowchart of the steps of another method for preparing a chip integrated structure provided in an embodiment of the present application.
  • FIG. 19 is a structural diagram of a chip integrated structure during the preparation process of the chip integrated structure in FIG. 18 .
  • electrical connection may refer to a direct electrical connection or an indirect electrical connection via an intermediate medium.
  • words such as “exemplary” or “for example” are used to indicate examples, illustrations or descriptions. Any embodiment or design described as “exemplary” or “for example” in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as “exemplary” or “for example” is intended to present related concepts in a specific way.
  • a and/or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural.
  • the character “/” generally indicates that the associated objects are in an "or” relationship.
  • directional indications such as up, down, left, right, front, and back, etc., used to explain the structure and movement of different components in the present application are relative. These indications are appropriate when the components are in the positions shown in the figures. However, if the description of the component position changes, then these directional indications will also change accordingly.
  • FIG1 is a structural diagram of an electronic device provided in an embodiment of the present application.
  • the electronic device 1000 may include an image sensor, a NAND flash memory, a high bandwidth memory, a mobile phone, a tablet computer (pad), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, and other electronic products.
  • a smart wearable product e.g., a smart watch, a smart bracelet
  • VR virtual reality
  • AR augmented reality
  • the embodiment of the present application does not impose any special restrictions on the specific form of the above-mentioned electronic device 1000.
  • the electronic device 1000 may include a printed circuit board 3 (PCB), a chip integrated structure 1, and a first connector 2 disposed between the printed circuit board 3 and the chip integrated structure 1, and the chip integrated structure 1 is electrically connected to the printed circuit board 3 via the first connector 2.
  • the first connector 2 may be, for example, a ball grid array (BGA).
  • FIG2 is a structural diagram of a chip stacking structure 91 provided by some current embodiments.
  • the chip stacking structure 91 includes a package substrate 911 (substrate) and a plurality of stacking layers 912, wherein the plurality of stacking layers 912 are stacked on one side of the package substrate 911, and any stacking layer 912 is electrically connected to the package substrate 911.
  • Each stacking layer 912 may include a plurality of chips 921, and a conductive column 913 is disposed on a side of each chip 921 close to the package substrate 911, and the chip 921 is electrically connected to the package substrate 911 through the corresponding conductive column 913.
  • FIG3 is a structural diagram of a chip wafer 92 provided in some current embodiments. As shown in FIG3, in the process of manufacturing the above-mentioned chip stacking structure 91, it is necessary to select on the chip wafer 92, and the selected functional chips 921 are arranged at intervals to form a stacking layer. It can be understood that after the epitaxial layer is grown on the wafer, the chip wafer 92 is formed.
  • the chip wafer 92 includes a cutting path structure 922 and a chip 921, and the cutting path structure 922 separates a plurality of chips 921.
  • the laser When cutting the chip wafer 92, the laser will irradiate the cutting path structure 922, heat the cutting path structure 922, and draw a cutting groove on the cutting path structure 922, so as to facilitate the separation between the functional chips.
  • the desired chip 921 can be obtained, and the chip 921 is a bare chip (die).
  • the stacking layer 912 is formed by selection, and the intervals between adjacent chips 921 in the same stacking layer 912 are large, resulting in a decrease in the number of chips 921 set per unit area of the same stacking layer 912, which in turn leads to poor performance of the stacking layer 912.
  • the stacking layer 912 is formed by selection, and multiple cuts are required to obtain multiple chips 921. The preparation process is relatively complicated and the processing efficiency is low, which leads to a decrease in product output efficiency.
  • the embodiment of the present application provides a chip integration structure 1.
  • the chip integration structure 1 provided in the embodiment of the present application can be applied to a central processing unit (CPU), a graphics processing unit (GPU), an AI chip, etc. under large capacity and high bandwidth requirements.
  • CPU central processing unit
  • GPU graphics processing unit
  • AI chip etc. under large capacity and high bandwidth requirements.
  • FIG4 is a structural diagram of a chip integration structure 1 provided in an embodiment of the present application.
  • the chip integration structure 1 includes The package substrate 30 includes a package substrate 30 and a first chip structure layer 10.
  • the first chip structure layer 10 is located on one side of the package substrate 30 and is electrically connected to the package substrate 30.
  • the chip integration structure 1 can be electrically connected to the printed circuit board 3 through the first connector 2, that is, the package substrate 30 in the chip integration structure 1 is electrically connected to the printed circuit board 3 through the first connector 2. Since the first chip structure layer 10 is electrically connected to the package substrate 30 through the second connector 20, and the package substrate 30 is electrically connected to the printed circuit board 3 through the first connector 2, the communication between the chip integration structure 1 and the electronic device 1000 can be achieved.
  • a second connector 20 may be provided between the first chip structure layer 10 and the package substrate 30, and the first chip structure may be electrically connected to the package substrate 30 through the second connector 20.
  • the second connector 20 may include, for example, an intermediate redistribution layer 21 (RDL), which is located between the first chip structure layer 10 and the package substrate 30.
  • RDL intermediate redistribution layer 21
  • the intermediate redistribution layer 21 is used to re-layout the wiring of the first chip structure layer 10, so as to facilitate the preparation of other required structures on the intermediate redistribution layer 21.
  • the second connector 20 may also include, for example, a bump 22 (Micro Bump, uBump), which is located between the intermediate redistribution layer 21 and the package substrate 30, and the intermediate redistribution layer 21 is electrically connected to the package substrate 30 through the bump 22.
  • the material of the bump 22 may include, for example, metals such as tin.
  • the first chip structure layer 10 includes a dicing road structure 12 and a plurality of first bare chips 11.
  • the dicing road structure 12 connects the plurality of first bare chips 11 and separates the plurality of first bare chips 11.
  • the number of first bare chips 11 in the first chip structure layer 10 is not limited and can be set according to application requirements.
  • the sizes of the plurality of first bare chips 11 can be the same or different, and the embodiment of the present application does not specifically limit this.
  • the first bare chip 11 has electrical functions.
  • electrical functions means that the first bare chip 11 has devices and can be powered on.
  • the first bare chip 11 may include digital chips, analog chips, optical chips, etc.
  • it can be a memory chip, a logic chip, or a chip with any other function, etc.
  • the memory chip can be, for example, a dynamic random access memory (DRAM) chip.
  • the multiple first bare chips 11 in the first chip structure layer 10 can be chips of the same type, for example, all memory chips; or they can be different types of chips, for example, different types of chips can be processed on the same wafer using corresponding processes. Based on this, the first bare chip 11 provided in the embodiment of the present application can realize the integration between chips of the same type or different types.
  • FIG5 is a top view of a first chip structure layer 10 provided in an embodiment of the present application.
  • the first chip structure layer 10 may include three first bare chips 11, the three first bare chips 11 are arranged in parallel, and adjacent first bare chips 11 are connected by a cutting road structure 12.
  • FIG6 is a structural diagram of a wafer provided in an embodiment of the present application. As shown in FIG5 and FIG6, the wafer 100 includes a cutting road structure 12 and a plurality of bare chips (dies), and the cutting road structure 12 separates the plurality of bare chips.
  • the first bare die 11 in FIG. 5 can be obtained from the wafer 100 in FIG. 6 .
  • the dicing road structure 12 at A in the figure is used as an example for explanation. Since the dicing road structure 12 at A is arranged around the periphery of three adjacent bare chips, after cutting along the dicing road structure 12 at A, the three adjacent bare chips are separated from the wafer 100, and the dicing road structure 12 between the three bare chips (such as the dicing road structure 12 at B in the figure) is retained, that is, the first chip structure layer 10 with three first bare chips 11 in FIG. 5 is obtained. Among them, the three bare chips are the three first bare chips 11 in the first chip structure layer 10, and the dicing road structure 12 retained between the three bare chips is the dicing road structure 12 in the first chip structure layer 10.
  • each first bare chip 11 is a bare chip, that is, the multiple first bare chips 11 are multiple bare chips located in the same wafer 100, and the adjacent bare chips are connected by the cutting road structure 12, that is, the cutting road area between the multiple first bare chips is not cut, so the cutting road structure is retained.
  • the number of the first bare die 11 per unit area in the first chip structure layer 10 increases, which is beneficial to improving the storage capacity of the first chip structure layer 10, and further helps to improve the storage capacity of the chip integrated structure 1;
  • the first bare die 11 includes a logic chip the number of the first bare die 11 per unit area in the first chip structure layer 10 increases, which is beneficial to improving the computing processing rate of the first chip structure layer 10, and further helps to improve the computing processing rate of the chip integrated structure 1.
  • multiple first bare chips 11 are multiple bare chips located in the same wafer 100, multiple first bare chips 11 can be obtained by one cutting, which is beneficial to improving the processing efficiency of the chip integration structure 1 and further improving the output of the chip integration structure 1 per unit time.
  • the chip integration structure 1 provided in the embodiment of the present application connects a plurality of first bare chips 11 through a cutting road structure 12 and separates the plurality of first bare chips 11.
  • the performance can be improved exponentially.
  • FIG7 is a cross-sectional view of a first chip structure layer 10 provided in an embodiment of the present application.
  • the first bare chip 11 may include a first substrate 111
  • the cutting path structure 12 may include a first connecting substrate 121; the first connecting substrate 121 is connected to the first substrate 111 and is arranged in the same layer.
  • adjacent first substrates 111 may be connected by the first connecting substrate 121.
  • "arranged in the same layer” means that the first substrate 111 and the first connecting substrate 121 adopt the same film forming process to form a film layer for forming a specific pattern, and then use the same mask to form a layer structure through a single patterning process.
  • the single patterning process may include multiple exposure, development or etching processes, and the material of the specific pattern in the formed layer structure is the same.
  • the materials of the first substrate 111 and the first connection substrate 121 may be the same, for example, the first substrate 111 and the first connection substrate 121 may be made of semiconductor materials, such as silicon substrate, gallium arsenide (GaAs) substrate, gallium arsenic phosphate (GaAsP) substrate, silicon carbide (SiC) substrate, etc.
  • the materials of the first substrate 111 and the first connection substrate 121 may also include other materials, which are not specifically limited in the embodiments of the present application.
  • the first die 11 may include a seal ring 113, which is located at the edge region of the first die 11 and is adjacent to the dicing road structure 12.
  • the edge region of the first die 11 may be a region arranged along the circumferential direction of the first die 11, that is, the seal ring 113 is arranged along the circumferential direction of the first die 11.
  • FIG. 8 is a cross-sectional view of the first chip structure layer 10 along the S1-S2 section line in FIG. 7 . As shown in FIG.
  • the seal ring 113 includes a plurality of stacked seal layers 113A and a plurality of seal plugs 113B, one seal plug 113B is located between two adjacent seal layers 113A, and the seal plug 113B is in contact with the two adjacent seal layers 113A. It is understandable that when the dicing road structure adjacent to the first die 11 is cut, stress is easily transferred to the first die 11, resulting in damage to the first die 11, thereby reducing the performance of the first die 11.
  • the sealing ring 113 is provided to reduce the stress transmitted to the first die 11 , thereby reducing the damage to the first die 11 and improving the performance of the first die 11 .
  • the first bare chip 11 may include a plurality of first insulating layers 1121, the plurality of first insulating layers 1121 are located on the first substrate 111, and the plurality of first insulating layers 1121 are stacked;
  • the dicing road structure 12 includes a plurality of first insulating connection layers 122, the plurality of first insulating connection layers 122 are located on the first connection substrate 121, and the plurality of first insulating connection layers 122 are stacked.
  • the plurality of first insulating connection layers 122 are connected to the plurality of first insulating layers 1121 one by one, and the correspondingly connected first insulating connection layers 122 are arranged in the same layer as the first insulating layers 1121.
  • the corresponding two first insulating layers 1121 in the adjacent first bare chips 11 are connected by the corresponding first insulating connection layers 122.
  • first insulating layer 1121 and the first insulating connection layer 122 are formed by the same film forming process to form a film layer for forming a specific pattern, and then the layer structure is formed by a single patterning process using the same mask, and the single patterning process may include multiple exposure, development or etching processes, and the material of the specific pattern in the formed layer structure is the same.
  • the material of the first insulating layer 1121 and the first insulating connection layer 122 may include one or more of silicon oxide, silicon nitride and silicon oxynitride.
  • the material of the first insulating layer 1121 and the first insulating connection layer 122 may also include other materials, which are not specifically limited in the present embodiment.
  • FIG9 is a cross-sectional view of a first chip structure layer 10 provided in an embodiment of the present application.
  • the first bare chip 11 may further include a plurality of first conductive layers 1122, the plurality of first conductive layers 1122 being located on the first substrate 111, and the plurality of first conductive layers 1122 being stacked.
  • the first conductive layer 1122 and the first insulating layer 1121 are located on the same side of the first substrate 111.
  • the dicing road structure 12 includes a plurality of first insulating connection layers 122, the plurality of first insulating connection layers 122 being located on the first connection substrate 121, and the plurality of first insulating connection layers 122 being stacked.
  • the plurality of first insulating connection layers 122 may be the same in number as the plurality of first conductive layers 1122.
  • the plurality of first insulating connection layers 122 and the plurality of first conductive layers 1122 may correspond one to one, so that the plurality of first insulating connection layers 122 and the plurality of first conductive layers 1122 are the same in number.
  • the first conductive layer 1122 includes a multilayer metal circuit, which is used to electrically connect multiple electronic components together to form a circuit structure of the first bare chip 11.
  • the electronic components may include, for example, transistors, capacitors, resistors, and the like.
  • the stacked first conductive layer 1122 and the first insulating layer 1121 together constitute the functional layer 112 of the first bare chip 11, so as to realize the storage, logic or other functions of the first bare chip 11.
  • the number of the plurality of first insulating connection layers 122 may be greater than the number of the plurality of first conductive layers 1122, and the plurality of first conductive layers 1122 may correspond one-to-one to part of the first insulating connection layers 122, which is not limited in the embodiments of the present application.
  • the first insulating layer 1121 may be close to the package substrate 30 relative to the first substrate 111, and correspondingly, the first insulating connection layer 122 may be close to the package substrate 30 relative to the first connection substrate 121.
  • the first insulating layer 1121 may be far away from the package substrate 30 relative to the first substrate 111, and the first insulating connection layer 122 may be far away from the package substrate 30 relative to the first connection substrate 121.
  • the cutting road structure 12 may include a positioning mark 123.
  • at least one positioning mark 123 may be provided on the first connection substrate 121.
  • the number of the positioning mark 123 may be only one.
  • the positioning mark 123 may be provided on the first connection substrate 121 and located between the first connection substrate 121 and the first insulating connection layer 122.
  • the number of the positioning mark 123 may be multiple.
  • multiple positioning marks 123 may all be located on the first connection substrate 121.
  • At least one positioning mark 123 may be provided on at least one first insulating connection layer 122.
  • the number of positioning marks 123 may be only one.
  • the positioning mark 123 is located on the first insulating connection layer 122 and is located on the same side of the first connection substrate 121 as the first insulating connection layer 122.
  • the number of positioning marks 123 may be multiple. Among them, multiple positioning marks 123 may all be located on the first connection substrate 121 or any first insulating connection layer 122; here, the positioning mark 123 can play a positioning role in the process of preparing the first insulating layer 1121 and the first insulating connection layer 122.
  • a portion of the positioning marks 123 are located on the first connecting substrate 121, and another portion of the positioning marks 123 are located on the first insulating connecting layer 122 (for example, one positioning mark 123 can be located on a first insulating connecting layer 122, and this embodiment of the present application does not specifically limit this).
  • the cutting path structure 12 includes a plurality of metal layers 124, the plurality of metal layers 124 are located on the first connection substrate 121, and the plurality of metal layers 124 are stacked.
  • the plurality of metal layers 124 correspond one-to-one to a portion of the plurality of first conductive layers 1122, and the corresponding metal layers 124 and the first conductive layers 1122 are arranged in the same layer and are electrically isolated.
  • a plurality of metal layers 124 may be arranged on the first insulating connection layer 122, the plurality of metal layers 124 may be stacked, and are located on the same side of the first connection substrate 121 as the first insulating connection layer 122.
  • the plurality of metal layers 124 correspond one-to-one to a portion of the plurality of first conductive layers 1122 and are not in contact, so that the corresponding metal layers 124 and the first conductive layers 1122 are electrically isolated.
  • “same-layer setting" means that the metal layer 124 and the first conductive layer 1122 are formed by the same film-forming process to form a film layer for forming a specific pattern, and then the layer structure is formed by a single composition process using the same mask template.
  • a single composition process may include multiple exposure, development or etching processes, and the material of the specific pattern in the formed layer structure is the same.
  • At least a portion of the plurality of metal layers 124 constitutes a test structure.
  • the test structure (Testkey) is tested by a specific test machine to reflect the process fluctuations in the manufacturing process of the first die 11 and detect whether the production line is abnormal.
  • FIG10 is a top view of another first chip structure layer 10 provided in an embodiment of the present application.
  • the cutting road structure 12 may include a first sub-cutting road structure 12A.
  • the first sub-cutting road structures 12A extend along the first direction X and are parallel to the package substrate 30.
  • the length H1 of the first sub-cutting road structure 12A along the second direction Y may range from 80 microns to 120 microns.
  • the length H1 of the first sub-cutting road structure 12A along the second direction Y may be 80 microns, 90 microns, or 120 microns.
  • the scribe line structure 12 may include a second sub-scribe line structure 12B.
  • the second sub-scribe line structure 12B extends along the second direction Y, and the first direction X is perpendicular to the second direction Y and both are parallel to the package substrate 30.
  • the length H2 of the second sub-scribe line structure 12B along the first direction X may range from 80 microns to 120 microns.
  • the length H2 of the second sub-scribe line structure 12B along the first direction X may be 80 microns, 90 microns, or 120 microns.
  • the length H1 of the first sub-cutting street structure 12A along the second direction Y may be greater than 120 microns
  • the length H2 of the second sub-cutting street structure 12B along the first direction X may be greater than 120 microns, which is not specifically limited in the embodiments of the present application.
  • the first chip structure layer 10 may include six first bare chips 11, and the six first bare chips 11 are arranged in an array.
  • the dicing road structure 12 may include a first sub-dicing road structure 12A extending along the first direction X and two second sub-dicing road structures 12B extending along the second direction Y.
  • FIG11 is a structural diagram of another chip integrated structure 1 provided in an embodiment of the present application.
  • the chip integrated structure 1 may further include a second chip structure layer 40, the second chip structure layer 40 is stacked with the first chip structure layer 10, and the second chip structure layer 40 is electrically connected to the packaging substrate 30.
  • the second chip structure layer 40 may be located between the first chip structure layer 10 and the packaging substrate 30.
  • the second chip structure layer 40 may also be located on the side of the first chip structure layer 10 away from the packaging substrate 30, which is not limited in the embodiment of the present application.
  • By setting the second chip structure it is beneficial to further improve the performance of the chip integrated structure 1.
  • the following is only an embodiment in which the second chip structure layer 40 is located between the first chip structure layer 10 and the packaging substrate 30 for explanation.
  • the second connector 20 can be located between the second chip structure layer 40 and the packaging substrate 30, and the first chip structure layer 10 is electrically connected to the second connector 20 through the second chip structure layer 40. Since the second connector 20 is also electrically connected to the packaging substrate 30, the first chip structure layer 10 can be electrically connected to the packaging substrate 30 through the second chip structure layer 40 and the second connector 20.
  • the second chip structure layer 40 may include a structure chip 41, a second die 42, and an isolation structure 43 between the structure chip 41 and the second die 42.
  • the second chip structure may include one second die 42 and two structure chips 41, the two structure chips 41 are respectively located on the left and right sides of the illustrated position of the second die 42, and the second die 42 is connected to the structure chip 41 through the isolation structure 43.
  • the structure chip 41 may include a structure substrate 411, and the material of the structure substrate 411 may be the same as the material of the first substrate 111, which will not be repeated here.
  • the material of the structure substrate 411 may be different from the material of the first substrate 111, and this is not limited in the embodiment of the present application.
  • the structure chip 41 By setting the structure chip 41, it can play a supporting role, which is beneficial to improve the stability of the chip integrated structure 1.
  • the number of structure chips 41 can be set according to actual needs, or the structure chip 41 can be omitted.
  • the structure chip 41 may further include an intermediate conductive via 412 penetrating the structure substrate 411, one end of the intermediate conductive via 412 being electrically connected to the first conductive layer 1122 of the first bare die 11, and the other end of the intermediate conductive via 412 being electrically connected to the second connector 20, so that the first conductive layer 1122 of the first bare die 11 can be electrically connected to the second connector 20 through the structure chip 41, and further electrically connected to the package substrate 30.
  • the intermediate conductive via 412 may be a through silicon via (TSV) or a through hole of other materials, and a conductive material may be filled in the through hole to ensure the conductive function.
  • TSV through silicon via
  • the second chip structure layer 40 may include multiple isolation structures 43, and the multiple isolation structures 43 can be prepared and formed simultaneously. For example, after the structural chip 41 and the second bare chip 42 are spaced apart, there is a gap between the structural chip 41 and the second bare chip 42, and the isolation material can be filled in the gap to form the isolation structure 43.
  • the material of the isolation structure 43 may include, for example, one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. Of course, the material of the isolation structure 43 may also include other materials to achieve the effect of electrical isolation, and the embodiments of the present application do not specifically limit this.
  • the length H3 of the isolation structure 43 along the first direction X may be greater than 50 microns, for example, the length H3 of the isolation structure 43 along the first direction may be 50 microns, 100 microns or 150 microns.
  • the above configuration is helpful to reduce the distance between the second die 42 and the structure chip 41, thereby reducing the size of the second chip structure layer 40, and further improving the performance of the chip integration structure 1.
  • the type of the second die 42 is not limited, and the type of the second die 42 may be the same as that of the first die 11, or the type of the second die 42 may be different from that of the first die 11.
  • the second die 42 has an electrical function.
  • electrical function means that the second die 42 has a device and can be powered on.
  • the second die 42 may include a digital chip, an analog chip, an optical chip, etc., for example, a memory chip, a logic chip, or a chip with any other function, etc., which is not specifically limited in the embodiment of the present application.
  • the second bare chip 42 may include a second substrate 421 and a functional layer 422 located on the second substrate 421, and the first chip structure layer 10 is electrically connected to the functional layer 422 of the second bare chip 42.
  • the material of the second substrate 421 may include one or more combinations of silicon oxide, silicon nitride and silicon oxynitride.
  • the functional layer 422 may include a second conductive layer 4221, and the second conductive layer 4221 includes a multi-layer metal line, and the metal line is used to electrically connect multiple electronic components together to form a circuit structure of the second bare chip 42.
  • the first conductive layer 1122 of the first bare chip 11 in the first chip structure layer 10 can be electrically connected to the second conductive layer 4221 of the second bare chip 42, and the second bare chip 42 is also electrically connected to the packaging substrate 30 to achieve communication between the packaging substrate 30 and the first bare chip 11 and the second bare chip 42 respectively.
  • the second chip structure layer 40 can be electrically connected to the packaging substrate 30 through The second connector 20 is electrically connected to the package substrate 30
  • the second die 42 in the second chip structure layer 40 can be electrically connected to the package substrate 30 through the second connector 20 .
  • the second bare die 42 may further include a second conductive via 423 penetrating the second substrate 421.
  • the functional layer 422 is close to the package substrate 30 relative to the second substrate 421, and the functional layer 422 is electrically connected to the package substrate 30.
  • the second conductive via 423 may penetrate the second substrate 421 along a third direction Z, and the third direction Z is perpendicular to the package substrate 30.
  • One end of the second conductive via 423 is electrically connected to the functional layer 422, and the other end of the second conductive via 423 is electrically connected to the first chip structure layer 10.
  • the first die 11 in the first chip structure layer 10 can be electrically connected to the functional layer 422 of the second die 42 through the second conductive via 423, and further, the first conductive layer 1122 in the first die 11 can be electrically connected to the second conductive layer 4221 in the functional layer 422 through the second conductive via 423.
  • the intermediate redistribution layer 21 in the second connector 20 can be used to rearrange the wiring in the functional layer 422 so that the functional layer 422 is electrically connected to the package substrate 30 through the second connector 20.
  • electrical connection between any two of the first chip structure layer 10, the second chip structure layer 40 and the package substrate 30 can be achieved.
  • FIG12 is a structural diagram of another chip integration structure 1 provided in an embodiment of the present application.
  • the functional layer 422 is away from the packaging substrate 30 relative to the second substrate 421, and the functional layer 422 is electrically connected to the first chip structure layer 10.
  • one end of the second conductive via 423 is electrically connected to the functional layer 422, and the other end of the second conductive via 423 is electrically connected to the packaging substrate 30.
  • the first bare chip 11 in the first chip structure layer 10 can be electrically connected to the functional layer 422, and further, the first conductive layer 1122 of the first bare chip 11 can be electrically connected to the second conductive layer 4221 of the functional layer 422.
  • the second bare chip 42 can be electrically connected to the packaging substrate 30 through the second connector 20, and one end of the second conductive via 423 is electrically connected to the packaging substrate 30, one end of the second conductive via 423 can be electrically connected to the second connector 20. Since one end of the second conductive via 423 is electrically connected to the functional layer 422, one end of the second conductive via 423 can be electrically connected to the first conductive layer 1122 of the functional layer 422. In summary, through the above configuration, electrical connections between the first chip structure layer 10, the second chip structure layer 40 and the package substrate 30 can be achieved.
  • the second conductive via 423 can be a through silicon via (TSV) or a through hole made of other materials, and a conductive material can be filled in the through hole to ensure the conductive function.
  • TSV through silicon via
  • FIG13 is a structural diagram of another chip integrated structure 1 provided in an embodiment of the present application.
  • the number of first chip structure layers 10 may be multiple, and multiple first chip structure layers 10 may be stacked along a third direction Z, and the third direction Z is perpendicular to the package substrate 30.
  • two adjacent first chip structure layers 10 are electrically connected so that each first chip structure layer 10 is electrically connected to the package substrate 30.
  • the first bare chip 11 includes storage capacity, it is beneficial to improve the storage capacity of the chip integrated structure 1; when the first bare chip 11 includes a logic chip, it is beneficial to improve the computing processing rate of the chip integrated structure 1.
  • the stacking manner between two adjacent first chip structure layers 10 can be that the functional layer 112 faces the functional layer 112 (Face-to-Face, F2F), and the stacking manner between the remaining two adjacent first chip structure layers 10 can be that the first substrate 111 faces the first substrate 111 (Back-to-Back, B2B).
  • the stacking manner between two adjacent first chip structure layers 10 is that the first substrate 111 faces the functional layer 112 (Back-to-Face, B2F).
  • the functional layer 112 in any first chip structure layer 10 can be close to the package substrate 30 relative to the first substrate 111.
  • the functional layer 112 in any first chip structure layer 10 can be far away from the package substrate 30 relative to the first substrate 111, and the embodiment of the present application does not specifically limit this.
  • the number of first bare chips 11 in the multiple first chip structure layers 10 can be the same or different, and the embodiment of the present application does not specifically limit this.
  • the cutting street structures 12 in the multiple first chip structure layers 10 can be staggered along the third direction Z, or the cutting street structures 12 in the multiple first chip structure layers 10 can also overlap in sequence along the third direction Z, and the embodiment of the present application does not specifically limit this.
  • the chip integrated structure 1 may further include a first redistribution layer 50, which is located between two adjacent first chip structure layers 10.
  • the first redistribution layer 50 includes a first portion 51 and a second portion 52 which are stacked, the first portion 51 being electrically connected to one first chip structure layer 10, and the second portion 52 being electrically connected to another first chip structure layer 10.
  • the first part 51 may be located above the first redistribution layer 50 in the illustrated position, and is used to re-layout the wiring of the first chip structure layer 10 located in the upper middle position of the illustrated position among the two adjacent first chip structure layers 10; correspondingly, the second part 52 may be located below the first redistribution layer 50 in the illustrated position, and is used to re-layout the wiring of the first chip structure layer 10 located in the lower middle position of the illustrated position among the two adjacent first chip structure layers 10.
  • the two adjacent first chip structure layers 10 can be electrically connected through the first redistribution layer 50.
  • the first redistribution layer 50 can be provided to realize the transfer between multiple first chip structure layers 10, so that multiple first chip structure layers 10 are all electrically connected to the package substrate 30, which is conducive to reducing the connection distance between the first chip structure layer 10 and the package substrate 30, and improving the performance of the chip integration structure.
  • the material of the first part 51 and the second part 52 may include materials such as one or more conductive materials such as copper, aluminum, nickel, gold, silver, titanium, cobalt, tungsten, etc., or other conductive alloy materials.
  • the first rewiring layer 50 further includes a first bonding portion 53 and a second bonding portion 54, and the second portion 52 and the first portion 51 can be bonded through the first bonding portion 53 and the second bonding portion 54.
  • bonding is a technology of directly bonding two homogeneous or heterogeneous semiconductor materials with clean surfaces and atomic-level flatness through surface cleaning and activation treatment under certain conditions, and bonding the wafers into one through van der Waals force, molecular force or even atomic force.
  • the bonding method can be hybrid bonding.
  • the first bonding portion 53 is located on the side of the first portion 51 close to the second portion 52
  • the second bonding portion 54 is located on the side of the second portion 52 close to the first portion 51.
  • the number of the first bonding portions 53 is multiple
  • the number of the second bonding portions 54 is multiple
  • the multiple first bonding portions 53 and the multiple second bonding portions 54 are arranged in a one-to-one correspondence.
  • the cross-sectional area of the end of the first bonding portion 53 close to the second portion 52 may be greater than the cross-sectional area of the end close to the first portion 51.
  • the “cross-sectional area” refers to the cross-sectional area of the first bonding portion 53 along the first direction X.
  • the cross-sectional area of the end of the second bonding portion 54 close to the first portion 51 may be greater than the cross-sectional area of the end close to the second portion 52.
  • the “cross-sectional area” refers to the cross-sectional area of the second bonding portion 54 along the first direction X.
  • the first bonding portion 53 may include a first connection pad 531 and a second connection pad 532 which are stacked, the first connection pad 531 being closer to the first portion 51 than the second connection pad 532, and the cross-sectional area of the second connection pad 532 being larger than the cross-sectional area of the first connection pad 531 in the direction parallel to the package substrate 30.
  • the direction parallel to the package substrate 30 is the first direction X shown in the figure, and since the cross-sectional area of the second connection pad 532 is larger than the cross-sectional area of the first connection pad 531, it is convenient for the first bonding portion 53 to contact the second bonding portion 54 through the second connection pad 532.
  • the second bonding portion 54 may include a third connection pad 541 and a fourth connection pad 542 which are stacked, the third connection pad 541 being closer to the second portion 52 relative to the fourth connection pad 542, and the cross-sectional area of the fourth connection pad 542 being larger than the cross-sectional area of the third connection pad 541 in the direction parallel to the package substrate 30.
  • the direction parallel to the package substrate 30 is the first direction X shown in the figure, and since the cross-sectional area of the fourth connection pad 542 is larger than the cross-sectional area of the third connection pad 541, it is convenient for the second bonding portion 54 to contact the first bonding portion 53 through the fourth connection pad 542.
  • the above arrangement facilitates the contact between the second connection pad 532 and the fourth connection pad 542, facilitates the bonding between the first bonding portion 53 and the second bonding portion 54, and ensures the conductive performance of the first redistribution layer 50.
  • the first redistribution layer 50 may further include a bump 22 , and the bump 22 is located between the first portion 51 and the second portion 52 , so that the first portion 51 and the second portion 52 are electrically connected together through the bump 22 .
  • the plurality of first chip structure layers 10 may be located on a side of the second chip structure layer 40 away from the package substrate 30.
  • the first chip structure layer 10 farthest from the package substrate 30 may be the top structure layer 10A
  • the first chip structure layer 10 located between the top structure layer 10A and the package substrate 30 may be the middle structure layer 10B.
  • the middle structure layer 10B may include a first conductive via 13 penetrating the first die 11 along the third direction Z
  • the top structure layer 10A may also be electrically connected through the first conductive via 13 of the middle structure layer 10B.
  • the first portion 51 is electrically connected to the first conductive layer 1122 in the top structure layer 10A
  • the second portion 52 is electrically connected to the first conductive layer 1122 in the middle structure layer 10B.
  • the holes 13 are electrically connected. It can be seen that by providing the first conductive through holes 13, electrical connection between the top structure layer 10A and the middle structure layer 10B can be achieved.
  • the first portion 51 is electrically connected to the first conductive via 13 of the intermediate structure layer 10B at the upper middle position shown in the figure, the first portion 51 is also electrically connected to the first conductive layer 1122 of the intermediate structure layer 10B at the upper middle position shown in the figure, and the second portion 52 is electrically connected to the first conductive via 13 of the intermediate structure layer 10B at the lower middle position shown in the figure. It can be seen that by providing the first conductive via 13, the electrical connection between adjacent intermediate structure layers 10B can also be achieved, and the top structure layer 10A can also be electrically connected to any intermediate structure layer 10B through multiple first conductive vias 13.
  • the chip integrated structure 1 may further include a second redistribution layer 60.
  • the second chip structure layer 40 may be located between the first chip structure layer 10 and the package substrate 30, where the first chip structure layer 10 is a first chip structure layer 10 closest to the package substrate 30 among the plurality of first chip structure layers 10.
  • the second redistribution layer 60 is located between the first chip structure layer 10 and the second chip structure layer 40, and the first chip structure layer 10 and the second chip structure layer 40 are electrically connected via the second redistribution layer 60.
  • the structure of the second redistribution layer 60 may be the same as that of the first redistribution layer 50 , thereby facilitating improving the regularity of the chip integrated structure 1 and improving the manufacturing efficiency of the chip integrated structure 1 .
  • the side of the second redistribution layer 60 close to the first chip structure layer 10 is electrically connected to the first conductive via 13.
  • the side of the second redistribution layer 60 in the structure layer close to the second chip structure layer 40 is electrically connected to the middle conductive via 412 and the second bare chip 42.
  • the functional layer 422 in the second bare chip 42 is close to the package substrate 30 relative to the second substrate 421, the functional layer 422 is electrically connected to the package substrate 30, one end of the second conductive via 423 is electrically connected to the functional layer 422, and the other end of the second conductive via 423 is electrically connected to the second redistribution layer 60; in the embodiment where the functional layer 422 in the second bare chip 42 is far away from the package substrate 30 relative to the second substrate 421, the functional layer 422 is electrically connected to the second redistribution layer 60, one end of the second conductive via 423 is electrically connected to the functional layer 422, and the other end of the second conductive via 423 is electrically connected to the package substrate 30.
  • the first chip structure layer 10 can be electrically connected to the second chip structure layer 40 through the second redistribution layer 60.
  • FIG. 14 is a structural diagram of another chip integration structure 1 provided in an embodiment of the present application.
  • the chip integration structure 1 may further include a third die 70, which may be stacked with the first chip structure layer 10, and the third die 70 is electrically connected to the package substrate 30.
  • the third die 70 may be located between the first chip structure layer 10 and the second chip structure layer 40, where the first chip structure layer 10 is the first chip structure layer 10 closest to the package substrate 30 among the multiple first chip structure layers 10.
  • the third die 70 is also electrically connected to the first chip structure layer 10 and the second chip structure layer 40, respectively, so that the third die 70 is electrically connected to the package substrate 30.
  • the third die 70 includes a third substrate 71 and a third conductive layer 72 located on one side of the third substrate 71.
  • the stacking method between the third die 70 and the first chip structure layer 10 may be that the third substrate 71 faces the functional layer 112 (Back-to-Face, B2F).
  • B2F Back-to-Face
  • the type of the third die 70 is not limited, and the type of the third die 70 may be the same as that of the first die 11, or the type of the third die 70 may be different from that of the first die 11.
  • the third die 70 has an electrical function.
  • electrical function means that the third die 70 has a device and can be powered on.
  • the third die 70 may include a digital chip, an analog chip, an optical chip, etc., for example, a memory chip, a logic chip, or a chip with any other function, etc., which is not specifically limited in the embodiment of the present application.
  • the first rewiring layer 50 may also be located between the third die 70 and the first chip structure layer 10, and the third die 70 and the first chip structure layer 10 may be electrically connected through the first rewiring layer 50; the second rewiring layer 60 may also be located between the third die 70 and the second chip structure layer 40, and the third die 70 and the second chip structure layer 40 may be electrically connected through the second rewiring layer 60.
  • the third die 70 may also include a third conductive via 73 running through it along the third direction Z, one end of the third conductive via 73 is electrically connected to the first rewiring layer 50, and the other end of the second conductive via 423 is electrically connected to the second rewiring layer 60.
  • the third conductive via 73 may be a through silicon via (TSV) or a through hole of other materials, and a conductive material may be filled in the through hole to ensure the conductive function.
  • TSV through silicon via
  • the third bare die 70 may also be located between two adjacent first chip structure layers 10, or located on a side of the first chip structure layer 10 away from the package substrate 30 (here, the first chip structure layer 10 is the first chip structure layer 10 farthest from the package substrate 30 among the multiple first chip structure layers 10).
  • the embodiment of the present application does not specifically limit the position of the third bare die 70.
  • the present application embodiment also provides a method for preparing a chip integrated structure 1.
  • the chip integrated structure in the above embodiment The chip integrated structure 1 can be prepared by the preparation method of the chip integrated structure 1.
  • Figure 15 is a flowchart of the steps of the preparation method of the chip integrated structure 1 provided in an embodiment of the present application. As shown in Figure 15, and in combination with Figure 14, the preparation method of the chip integrated structure 1 can include the following steps S101 to S103.
  • the packaging substrate 30 may be a circuit board with a wiring circuit, or may be a substrate formed of silicon (e.g., single crystal silicon), ceramic, glass, or any other appropriate material.
  • the packaging substrate 30 may be provided with a plurality of structures for forming electrical connections, such as a pad structure located on the upper surface of the packaging substrate 30, a contact structure located on the lower surface of the packaging substrate 30, and a circuit structure located inside the packaging substrate 30.
  • the process further includes step S102 .
  • the first chip structure layer comprising a dicing line structure and a plurality of first bare chips, the dicing line structure connecting the plurality of first bare chips and electrically separating the plurality of first bare chips, the first bare chips having electrical functions.
  • each first bare die 11 is a bare chip, that is, the multiple first bare dies 11 are multiple bare chips located in the same wafer 100, and the adjacent bare chips are connected by the dicing road structure 12.
  • the preparation process of the first chip structure layer 10 can be as described in the above embodiment, and will not be repeated here.
  • the number of the first chip structure layers 10 may be multiple, and adjacent first chip structure layers 10 may be electrically connected via the first redistribution layer 50 .
  • a first redistribution layer 50 may be arranged on one side of the first chip structure layer 10, and then a second first chip structure layer 10 may be arranged on the other side of the first redistribution layer 50... and so on, and any two adjacent first chip structure layers 10 may be electrically connected through the above arrangement.
  • the preparation process of the first redistribution layer 50 may include the redistribution process and the bonding interface process in the related process, which will not be described in detail in the embodiment of the present application.
  • the first chip structure layer 10 after providing the first chip structure layer 10, includes a dicing line structure 12 and a plurality of first bare chips 11, and the dicing line structure 12 connects the plurality of first bare chips 11 and separates the plurality of first bare chips 11, step S103 is further included.
  • the above configuration is conducive to reducing the spacing between adjacent first bare dies 11 in the first chip structure layer 10, thereby increasing the number of first bare dies 11 per unit area in the first chip structure layer 10, thereby improving the performance of the chip integrated structure 1.
  • the first bare die 11 includes storage capacity
  • the number of first bare dies 11 per unit area in the first chip structure layer 10 increases, which is conducive to improving the storage capacity of the first chip structure layer 10, thereby improving the storage capacity of the chip integrated structure 1
  • the first bare die 11 includes a logic chip
  • the number of first bare dies 11 per unit area in the first chip structure layer 10 increases, which is conducive to improving the computing processing rate of the first chip structure layer 10, thereby improving the computing processing rate of the chip integrated structure 1.
  • Fig. 16 is a flow chart of steps of another method for preparing a chip integrated structure 1 provided in an embodiment of the present application
  • Fig. 17 is a structural diagram of the preparation process in the method for preparing the chip integrated structure 1 in Fig. 16.
  • the method for preparing the chip integrated structure 1 may include the following steps S211 to S214.
  • the step of providing a first chip structure layer 10 may include: providing a plurality of first chip structure layers 10 , wherein the plurality of first chip structure layers 10 may be located in different wafers, respectively.
  • multiple first chip structure layers 10 are stacked in sequence, and any two adjacent first chip structure layers 10 are electrically connected.
  • the wafers where the multiple first chip structure layers 10 are located can be stacked in sequence, and any two adjacent wafers are electrically connected.
  • wafer C and wafer D can both include multiple first chip structure layers 10, and wafer C and wafer D are stacked, and wafer C and wafer D are electrically connected, so that the first chip structure layer 10 in wafer C is stacked with the corresponding first chip structure layer 10 in wafer D, and the corresponding two first chip structure layers 10 are electrically connected.
  • the step of stacking the wafers where the multiple first chip structure layers 10 are located can be as described in the above embodiments, and will not be repeated here.
  • step S211 is also included.
  • 40C (carrier) serves as a temporary bonding structure to facilitate the fabrication of chip structures on the carrier 40C.
  • the carrier 40C can be called a wafer carrier layer.
  • the wafer carrier layer can be bonded to the corresponding chip by fusion bonding, and finally the wafer 100 carrier layer can be removed by grinding; or, the wafer carrier layer can be bonded to the corresponding chip by temporary bonding (using bonding glue, with a bonding film layer), and finally the wafer carrier layer can be removed by hot melting.
  • the step of forming the second chip structure layer 40 on the carrier 40C may include: selecting a structure chip 41 from the first wafer 40A, and placing the selected structure chip 41 on the carrier 40C.
  • the structure chip 41 may be made of semiconductor materials, such as a silicon substrate, a gallium arsenide (GaAs) substrate, a gallium arsenic phosphate (GaAsP) substrate, a silicon carbide (SiC) substrate, etc.
  • a supporting function may be provided, which is beneficial to improving the stability of the chip integrated structure 1.
  • the number of structure chips 41 may be provided according to actual needs, or the structure chip 41 may be omitted.
  • the step of forming the second chip structure layer 40 on the carrier 40C may further include: selecting a second bare die 42 from the second wafer 40B, and placing the selected second bare die 42 on the carrier 40C.
  • the second bare die 42 and the structure chip 41 can be arranged at intervals.
  • the arrangement between the second bare die 42 and the structure chip 41 can be arranged according to actual needs.
  • one second bare die 42 and two structure chips 41 can be arranged in the second chip structure layer 40, and the two structure chips 41 are respectively arranged on both sides of the second bare die 42.
  • the first wafer 40A and the second wafer 40B may have different wafer structures, and the required structure chips 41 may be cut from the first wafer 40A by selection, and then the cut structure chips 41 may be placed on the carrier 40C; similarly, the required second bare chips 42 may be cut from the second wafer 40B by selection, and then the cut second bare chips 42 may be placed on the carrier 40C.
  • the selected structure chips 41 and second bare chips 42 are both chips that meet the quality standards.
  • the step of forming a second chip structure layer 40 on the carrier 40C may also include: after setting the second bare chip 42 and the structure chip 41 on the carrier 40C, forming an isolation structure 43 between the structure chip 41 and the second bare chip 42, and the structure chip 41, the second bare chip 42 and the isolation structure 43 together constitute the second chip structure layer 40.
  • the second bare chip 42 and the structural chip 41 are arranged at intervals, there is a certain gap between the second bare chip 42 and the structural chip 41, and the isolation material can be filled in the gap to form an isolation structure 43.
  • the side of the second chip structure layer 40 away from the carrier 40C can be flattened by a chemical mechanical polishing (CMP) process to facilitate subsequent processing and preparation.
  • CMP chemical mechanical polishing
  • step S212 is also included.
  • the chip integrated structure 1 may further include a second redistribution layer 60, which may be disposed on a side of the second chip structure layer 40 away from the carrier 40C, and then the first chip structure layer 10 may be disposed on a side of the second redistribution layer 60 away from the carrier 40C.
  • the structure of the second redistribution layer 60 may be as described in the above embodiment, and will not be described in detail herein.
  • the stacked wafers where the multiple first chip structure layers 10 are located are electrically connected to the second redistribution layer 60, so that the wafers are stacked, so that any first chip structure layer 10 is electrically connected to the second chip structure layer 40.
  • the step of disposing the first chip structure layer 10 on one side of the packaging substrate 30 and electrically connecting the first chip structure layer 10 to the packaging substrate 30 further includes step S213 .
  • the step of removing the carrier sheet 40C may be as described in the above embodiment and will not be repeated here.
  • the step of disposing the first chip structure layer 10 on one side of the packaging substrate 30 and electrically connecting the first chip structure layer 10 to the packaging substrate 30 further includes step S214.
  • the chip integrated structure 1 may further include a second connector 20.
  • the second chip structure layer 40 is spaced away from the first chip.
  • the step of electrically connecting one side of the chip structure layer 10 to the packaging substrate 30 also includes: arranging the second connector 20 on the side of the second chip structure layer 40 away from the first chip structure layer 10, and arranging the packaging substrate 30 on the side of the second connector 20 away from the second chip structure layer 40, so that the second chip structure layer 40 is electrically connected to the packaging substrate 30 through the second connector 20.
  • the structure of the second connector 20 can be as described in the above embodiment, and the embodiment of the present application does not specifically limit this.
  • a wafer M can be formed after the side of the second chip structure layer 40 away from the first chip structure layer 10 is electrically connected to the packaging substrate 30, a wafer M can be formed. Among them, through the above steps, the stacking arrangement and electrical connection between the packaging substrate 30, the second chip structure layer 40 and the first chip structure layer 10 can be realized, thereby forming a chip integrated structure 1.
  • the wafer M includes a plurality of chip integrated structures 1, and the wafer M can be cut to obtain a plurality of independent chip integrated structures 1.
  • Fig. 18 is a flow chart of steps of another method for preparing a chip integrated structure 1 provided in an embodiment of the present application
  • Fig. 19 is a structural diagram of the chip integrated structure 1 during the preparation process of the method for preparing the chip integrated structure 1 in Fig. 18.
  • the method for preparing the chip integrated structure 1 may include the following steps S221 to S222.
  • the step of providing a first chip structure layer 10 may include: providing a plurality of first chip structure layers 10 , wherein the plurality of first chip structure layers 10 may be located in different wafers, respectively.
  • first chip structure layers 10 are stacked in sequence, and any two adjacent first chip structure layers 10 are electrically connected.
  • the wafers where the multiple first chip structure layers 10 are located can be stacked in sequence, and any two adjacent wafers are electrically connected.
  • wafer C and wafer D can both include multiple first chip structure layers 10, and wafer C and wafer D are stacked, and wafer C and wafer D are electrically connected, so that the first chip structure layer 10 in wafer C is stacked with the corresponding first chip structure layer 10 in wafer D, and the corresponding two first chip structure layers 10 are electrically connected.
  • step S221 is also included.
  • the step of forming the second chip structure layer 40 on the first chip structure layer 10 and electrically connecting the first chip structure layer 10 with the second chip structure layer 40 may include: selecting a structure chip 41 from the first wafer 40A, and setting the selected structure chip 41 on the first chip structure layer 10, so that the structure chip 41 is connected to the first chip structure layer 10.
  • a second redistribution layer 60 can be formed on the first chip structure layer 10, and then the structure chip 41 is set on the side of the second redistribution layer 60 away from the first chip structure layer 10, so that the structure chip 41 is connected to the first chip structure layer 10 through the second redistribution layer 60.
  • the step of forming the second chip structure layer 40 on the first chip structure layer 10 and electrically connecting the first chip structure layer 10 to the second chip structure layer 40 may also include: selecting a second bare die 42 from the second wafer 40B, and disposing the selected second bare die 42 on the first chip structure layer 10, so that the second bare die 42 and the first chip structure layer 10 are electrically connected.
  • the second die 42 may be disposed on a side of the second redistribution layer 60 away from the first chip structure layer 10 , so that the second die 42 is electrically connected to the first chip structure layer 10 through the second redistribution layer 60 .
  • a second redistribution layer 60 is formed on the stacked wafers where the multiple first chip structure layers 10 are located (for example, wafer C and wafer D are stacked in FIG. 19 , and wafer C and wafer D are electrically connected), and then a structure chip 41 and a second bare chip 42 are arranged on the side of the second redistribution layer 60 away from the first chip structure layer 10, thereby achieving stacking between wafers and chips.
  • the structure chip 41 and the second bare chip 42 are arranged on the side of the second redistribution layer 60 away from the first chip structure layer 10, it also includes: forming an isolation structure 43 between the structure chip 41 and the second bare chip 42, and the structure chip 41, the second bare chip 42 and the isolation structure 43 together constitute the second chip structure layer 40.
  • the step of arranging the first chip structure layer 10 on one side of the packaging substrate 30 and electrically connecting the first chip structure layer 10 to the packaging substrate 30 also includes step S222.
  • the chip integrated structure 1 may further include a second connector 20.
  • the second connector 20 may be disposed on a side of the second chip structure layer 40 away from the first chip structure layer 10, and the package substrate 30 may be disposed on the second chip structure layer 40.
  • the connector 20 is away from one side of the second chip structure layer 40, so that the second chip structure layer 40 is electrically connected to the package substrate 30 through the second connector 20.
  • the structure of the second connector 20 can be as described in the above embodiment, and the embodiment of the present application does not specifically limit this.
  • a wafer M can be formed after the side of the second chip structure layer 40 away from the first chip structure layer 10 is electrically connected to the packaging substrate 30, a wafer M can be formed. Among them, through the above steps, the stacking arrangement and electrical connection between the packaging substrate 30, the second chip structure layer 40 and the first chip structure layer 10 can be realized, thereby forming a chip integrated structure 1.
  • the wafer M includes a plurality of chip integrated structures 1, and the wafer M can be cut to obtain a plurality of independent chip integrated structures 1.
  • the stacking step between the packaging substrate 30 , the second chip structure layer 40 and the first chip structure layer 10 may also not be limited to the above two implementations, and the embodiment of the present application does not make any specific limitation on this.

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Abstract

本申请的实施例提供了一种芯片集成结构及其制备方法、电子设备，用于改善目前芯片同一堆叠层中相邻功能芯片之间间距较大，使得单位面积内，设置的功能芯片的数量降低，进而导致堆叠层的性能较差的问题。芯片集成结构包括：封装基板和第一芯片结构层。第一芯片结构层位于封装基板的一侧，且与封装基板电连接；第一芯片结构层包括切割道结构和多个第一裸片；切割道结构连接多个第一裸片，且将多个第一裸片电性分隔，第一裸片具有电性功能。通过上述设置，有利于缩小第一芯片结构层中相邻第一裸片之间的间距，进而提高第一芯片结构层中单位面积内第一裸片的数量，从而提升芯片集成结构的集成性，芯片集成结构的性能。

Description

芯片集成结构及其制备方法、电子设备
本申请要求于2022年12月15日提交国家知识产权局、申请号为202211626334.0、申请名称为“芯片集成结构及其制备方法、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片技术领域，尤其涉及一种芯片集成结构及其制备方法、电子设备。
背景技术
随着半导体技术的快速发展，3D IC(three-dimensional integrated circuit，三维集成电路)已经得到广泛应用。3D IC是指将多个芯片进行三维空间的垂直整合堆叠，从而可以缩小封装尺寸、提升芯片性能、提升芯片的集成度等。3D IC技术已被许多半导体制造商成功应用于生产CMOS(complementary metal oxide semiconductor，互补金属氧化物半导体)图像传感器、NAND flash(闪存)、高带宽存储器(high bandwidth memory，HBM)等产品，并大幅提升了产品性能。然而，芯片同一堆叠层的性能较差。
发明内容
本申请实施例提供一种芯片集成结构及其制备方法、电子设备，用于改善目前芯片同一堆叠层中相邻功能芯片之间间距较大，使得单位面积内，设置的功能芯片的数量降低，进而导致堆叠层的性能较差的问题。
为达到上述目的，本申请采用如下技术方案：
一方面，提供一种芯片集成结构，包括：封装基板和第一芯片结构层。第一芯片结构层位于封装基板的一侧，且与封装基板电连接；第一芯片结构层包括切割道结构和多个第一裸片；切割道结构连接多个第一裸片，且将多个第一裸片电性分隔；所述第一裸片具有电性功能。
上述实施例中的芯片集成结构，第一芯片结构层包括切割道结构和多个第一裸片，切割道结构连接多个第一裸片，且将多个第一裸片电性分隔，第一裸片具有电性功能。此处，“电性功能”是指第一裸片具有器件且能够上电工作。第一裸片可以包括数字芯片、模拟芯片以及光芯片等等。每个第一裸片均为一个裸芯片，也即，多个第一裸片为位于同一晶圆中的多个裸芯片，且相邻的裸芯片之间通过切割道结构连接，也即该多个第一裸片之间的切割道区域未被切割，故保留有切割道结构。通过上述设置，有利于缩小第一芯片结构层中相邻第一裸片之间的间距，进而提高第一芯片结构层中单位面积内第一裸片的数量，从而提升芯片集成结构的集成度，进而提升芯片集成结构的性能。例如，当第一裸片包括存储芯片时，第一芯片结构层中单位面积内第一裸片的数量增加，有利于提高第一芯片结构层的存储容量，进而有利于提高芯片集成结构的存储容量；当第一裸片包括逻辑芯片时，第一芯片结构层中单位面积内第一裸片的数量增加，有利于提高第一芯片结构层的计算处理速率，进而有利于提高芯片集成结构的计算处理速率。
同时，由于多个第一裸片为位于同一晶圆中的多个裸芯片，可以通过一次切割得到多个第一裸片，有利于提高芯片集成结构的加工效率，进而提高单位时间内芯片集成结构的产量。
在一些实施例中，第一裸片包括第一衬底；切割道结构包括第一连接衬底；第一连接衬底与第一衬底相连，且同层设置。示例性的，相邻的第一衬底之间可以通过第一连接衬底连接。此处，“同层设置”是指第一衬底和第一连接衬底采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构，一次构图工艺可以包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形的材质相同。
在一些实施例中，第一裸片还包括密封圈，密封圈位于第一裸片的边缘区域，且密封圈与切割道结构相邻接。密封圈包括多个层叠设置的密封层以及多个密封插塞，一个密封插塞位于相邻的两个密封层之间，且密封插塞与相邻的两个密封层之间接触。可以理解的是，在对与第一裸片相邻接的切割道结构进行切割时，应力容易传递至第一裸片内，导致第一裸片内损伤，进而导致 第一裸片的性能降低。通过设置密封圈，有利于减小传递至第一裸片内的应力，进而降低第一裸片的出现损伤的现象，有利于提高第一裸片的性能。
在一些实施例中，第一裸片还包括多个第一绝缘层，多个第一绝缘层位于第一衬底上，且多个第一绝缘层层叠设置。切割道结构还包括多个第一绝缘连接层，多个第一绝缘连接层位于第一连接衬底上，且多个第一绝缘连接层层叠设置。其中，多个第一绝缘连接层与多个第一绝缘层一一对应连接，且对应连接的第一绝缘连接层与第一绝缘层同层设置。示例性的，相邻的第一裸片中的对应的两个第一绝缘层之间通过对应的第一绝缘连接层连接。此处，“同层设置”是指第一绝缘层和第一绝缘连接层采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构，一次构图工艺可以包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形的材质相同。
在一些实施例中，第一裸片还包括多个第一导电层，多个第一导电层位于第一衬底上，且多个第一导电层层叠设置。切割道结构还包括多个第一绝缘连接层，多个第一绝缘连接层位于第一连接衬底上，且多个第一绝缘连接层层叠设置。其中，多个第一绝缘连接层与多个导电层数量相同。第一导电层包括多层金属线路，金属线路用于将多个电子元器件电连接在一起，以构成第一裸片的电路结构。电子元器件例如可以包括晶体管、电容电阻等等。层叠设置的第一导电层和第一绝缘层共同构成第一裸片的功能层，以便实现第一裸片的存储、逻辑或者其他功能。
在一些实施例中，切割道结构包括多个金属层，多个金属层位于第一连接衬底上，且多个金属层层叠设置。其中，多个金属层与部分多个第一导电层一一对应，对应的金属层和第一导电层同层设置且电性隔离。例如，第一连接衬底上可以设置有多个金属层，多个金属层可以层叠设置，且与第一绝缘连接层位于第一连接衬底的同一侧。其中，多个金属层与部分多个第一导电层一一对应且不接触，以使对应的金属层和第一导电层之间电性隔离。此处，“同层设置”是指金属层和第一导电层采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构，一次构图工艺可以包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形的材质相同。
在一些实施例中，多个金属层的至少部分构成测试结构。此处，通过特定测试机台对测试结构(Testkey)进行测试，从而反应第一裸片的制作过程中的工艺波动以及侦测产线是否出现异常。
在一些实施例中，切割道结构包括定位标记。示例性的，第一连接衬底上设置有至少一个定位标记；和/或，至少一个第一绝缘连接层上设置有至少一个定位标记。在一些实施例中，定位标记的数量可以仅为一个。其中，定位标记可以设置在第一连接衬底上，且位于第一连接衬底和第一绝缘连接层之间；或者，定位标记可以与第一绝缘连接层层叠设置，且与第一绝缘连接层位于第一连接衬底的同一侧。在一些其他的实施例中，定位标记的数量可以为多个。其中，多个定位标记可以均位于第一连接衬底或者任一第一绝缘连接层上；或者，多个定位标记中，一部分定位标记位于第一连接衬底上，另一部分定位标记与第一绝缘连接层层叠设置(例如，一个定位标记可以位于一个第一绝缘连接层上，本实施例对此不进行具体限定)。
在一些实施例中，切割道结构包括第一子切割道结构，第一子切割道结构沿第一方向延伸，第一子切割道结构沿第二方向的长度的取值范围为80微米-120微米；其中，第一方向与第二方向垂直，且均平行于封装基板；和/或，切割道结构包括第二子切割道结构；其中，第一子切割道结构沿第一方向延伸，第二子切割道结构沿第二方向延伸，第二子切割道结构沿第一方向的长度的取值范围为80微米-120微米；其中，第一方向与第二方向垂直，且均平行于封装基板。通过上述设置，有利于进一步缩小第一芯片结构层中相邻第一裸片之间的间距，进一步提高第一芯片结构层的存储容量。
在一些实施例中，第一芯片结构层的数量为多个，多个第一芯片结构层沿第三方向层叠设置，第三方向垂直于封装基板。其中，相邻的两个第一芯片结构层之间电连接。以使每个第一芯片结构层均与封装基板电连接。通过设置多个第一芯片结构层，有利于进一步提高芯片集成结构的性能。例如，当第一裸片包括存储容量时，有利于提高芯片集成结构的存储容量；当第一裸片包括逻辑芯片时，有利于提高芯片集成结构的计算处理速率。
在一些实施例中，芯片集成结构还包括第一重布线层。第一重布线层位于相邻两个第一芯片 结构层之间。其中，第一重布线层包括层叠设置的第一部分和第二部分，第一部分与一个第一芯片结构层电连接，第二部分与另一个第一芯片结构层电连接。第一部分可以位于第一重布线层的上方，用于将相邻两第一芯片结构层中位于上方的第一芯片结构层的布线重新布局；相应的，第二部分可以位于第一重布线层的下方，用于将相邻两第一芯片结构层中位于下方的第一芯片结构层的布线重新布局。通过将第一重布线层的第一部分和第二部分电连接在一起，可以使相邻的两个第一芯片结构层之间通过第一重布线层电连接。其中，第一部分和第二部分的材质可以包括材料例如可以包括铜、铝、镍、金、银、钛、钴、钨等中的一种或多种导电材料，或者其他导电合金材料。
第一重布线层还包括第一键合部和第二键合部，第一键合部位于第一部分靠近第二部分的一侧，第二键合部位于第二部分靠近第一部分的一侧，第二部分与第一部分通过第一键合部和第二键合部键合。此处，键合(Bonding)，是将两片表面清洁、原子级平整的同质或异质半导体材料经表面清洗和活化处理，在一定条件下直接结合，通过范德华力、分子力甚至原子力使晶片键合成为一体的技术。比如，键合方式例如可以为混合键合(Hybrid Bonding)。其中，第一键合部位于第一部分靠近第二部分的一侧，第二键合部位于第二部分靠近第一部分的一侧。示例性的，第一键合部的数量为多个，第二键合部的数量为多个，多个第一键合部和多个第二键合部一一对应设置。通过上述设置，由于第一键合部和第二键合部沿第三方向的长度较小，有利于减小相邻第一芯片结构层之间的间距，便于布置更多线路，实现相邻第一芯片结构层之间进行更多线路的信息传输以实现更多功能，同时，还有利于降低芯片集成结构的厚度。
在一些实施例中，第一键合部靠近第二部分的一端的截面面积大于靠近第一部分的一端的截面面积；和/或，第二键合部靠近第一部分的一端的截面面积大于靠近第二部分的一端的截面面积。此处，“截面面积”是指第一键合部和/或第二键合部沿第一方向上的截面面积。通过上述设置，便于第一键合部靠近第二部分的一端与第二键合部靠近第一部分的一端接触，有利于实现第一键合部和第二键合部之间的键合，保证第一重布线层的导电性能。
在一些实施例中，第一键合部包括层叠设置的第一连接垫和第二连接垫，第一连接垫相对于第二连接垫靠近第一部分，在平行于封装基板的方向上，第二连接垫的截面面积大于第一连接垫的截面面积。和/或，第二键合部包括层叠设置的第三连接垫和第四连接垫，第三连接垫相对于第四连接垫靠近第二部分，在平行于封装基板的方向上，第四连接垫的截面面积大于第三连接垫的截面面积。由于第二连接垫的截面面积大于第一连接垫的截面面积，便于第一键合部通过第二连接垫与第二键合部接触；相同的，由于第四连接垫的截面面积大于第三连接垫的截面面积，便于第二键合部通过第四连接垫与第一键合部接触。通过上述设置，有利于便于第二连接垫与第四连接垫接触，有利于实现第一键合部和第二键合部之间的键合，保证第一重布线层的导电性能。
在一些实施例中，多个层叠设置的第一芯片结构层中，与封装基板之间的距离最远的第一芯片结构层为顶层结构层，位于顶层结构层和封装基板之间的第一芯片结构层为中间结构层。其中，中间结构层包括沿第三方向贯穿第一裸片的第一导电通孔，顶层结构层还通过重布线层与中间结构层的第一导电通孔电连接。示例性的，位于顶层结构层和中间结构层之间的第一重布线层中，第一部分与顶层结构层中的第一导电层电连接，第二部分与中间结构层中的第一导电通孔电连接。可见，通过设置第一导电通孔，可以实现顶层结构层与中间结构层之间的电连接。
在一些实施例中，芯片集成结构还包括第二芯片结构层，第二芯片结构层与第一芯片结构层层叠设置，第二芯片结构层包括结构芯片、第二裸片以及位于结构芯片和第二裸片之间的隔离结构。其中，第二裸片包括第二衬底以及位于第二衬底上的功能层，第一芯片结构层与第二裸片的功能层之间电连接。在一些实施例中，第二芯片结构层可以位于第一芯片结构层和封装基板之间，当然，在一些其他实施例中，第二芯片结构层还可以位于第一芯片结构层远离封装基板的一侧，本申请实施例对此不进行限定。通过设置第二裸片，有利于进一步提高芯片集成结构的性能。通过设置结构芯片，可以起到支撑的作用，有利于提高芯片集成结构的稳定性。
在一些实施例中，隔离结构的材质包括氧化硅、氮化硅以及氮氧化硅中一种或者多种的组合。通过设置隔离结构，可以实现结构芯片和第二裸片之间的结构连接。第二芯片结构层中可以包括多个隔离结构，多个隔离结构可以同步制备形成。例如，将结构芯片和第二裸片间隔设置以后， 结构芯片和第二裸片之间具有间隙，可以在间隙内填充隔离材料，以形成隔离结构。
在一些实施例中，芯片集成结构还包括第二重布线层。第二芯片结构层位于第一芯片结构层和封装基板之间，第二重布线层位于第一芯片结构层和第二芯片结构层之间，第一芯片结构层和第二芯片结构层之间通过第二重布线层电连接，第二芯片结构层与封装基板电连接。第二芯片结构层可以位于第一芯片结构层和封装基板之间，此处，第一芯片结构层为多个第一芯片结构层中最靠近封装基板的一个第一芯片结构层。第二重布线层位于第一芯片结构层和第二芯片结构层之间，第一芯片结构层和第二芯片结构层之间通过第二重布线层电连接。其中，第二重布线层的结构可以与第一重布线层的结构相同，从而有利于提高芯片集成结构的规整性，提高芯片集成结构的制备效率。
在一些实施例中，第二裸片还包括贯穿第二衬底的第二导电通孔，功能层相对于第二衬底靠近封装基板，功能层与封装基板电连接。其中，第二导电通孔的一端与功能层电连接，第二导电通孔的另一端与第二重布线层电连接。通过上述设置，第一芯片结构层中的第一裸片可以通过第二导电通孔与第二裸片的功能层电连接，进一步地，第一裸片中的第一导电层可以通过第二导电通孔与功能层中的第二导电层电连接。如上述实施例中所述，由于第二裸片可以通过第二连接件与封装基板电连接，且功能层相对于第二衬底靠近封装基板，第二连接件中的中间重布线层可以用于将功能层中的布线重新布置，以使功能层通过第二连接件与封装基板电连接。综上所述，通过上述设置，可以实现第一芯片结构层、第二芯片结构层与封装基板三者中两两之间的电连接。
在一些实施例中，第二裸片还包括贯穿第二衬底的第二导电通孔，功能层相对于第二衬底远离封装基板，功能层与第二重布线层电连接。其中，第二导电通孔的一端与功能层电连接，第二导电通孔的另一端与封装基板电连接。通过上述设置，第一芯片结构层中的第一裸片可以与功能层电连接，进一步地，第一裸片的第一导电层可以与功能层的第二导电层电连接。如上述实施例中所述，由于第二裸片可以通过第二连接件与封装基板电连接，且第二导电通孔的一端与封装基板电连接，第二导电通孔的一端可以与第二连接件电连接。由于第二导电通孔的一端与功能层电连接，第二导电通孔的一端可以与功能层的第一导电层电连接。综上所述，通过上述设置，可以实现第一芯片结构层、第二芯片结构层与封装基板三者中两两之间的电连接。
在一些实施例中，还包括第三裸片，第三裸片与第一芯片结构层层叠设置，第三裸片与封装基板电连接。示例性的，第三裸片可以位于第一芯片结构层和第二芯片结构层之间，此处，该第一芯片结构层为多个第一芯片结构层中最靠近封装基板的一个第一芯片结构层。第三裸片还分别与第一芯片结构层和第二芯片结构层电连接，以使第三裸片与封装基板电连接。第三裸片包括第三衬底和位于第三衬底一侧的第三导电层。例如，第三裸片与第一芯片结构层之间的堆叠方式可以为第三衬底面对功能层(Back-to-Face，B2F)。通过设置第三裸片，有利于进一步提高芯片集成结构的性能。
另一方面，还提供一种芯片集成结构的制备方法，包括：提供封装基板。提供第一芯片结构层，第一芯片结构层包括切割道结构和多个第一裸片，切割道结构连接多个第一裸片，且将多个第一裸片分隔开。将第一芯片结构层设置在封装基板的一侧，并使第一芯片结构层与封装基板电连接。综上所述，通过上述设置，有利于缩小第一芯片结构层中相邻第一裸片之间的间距，进而提高第一芯片结构层中单位面积内第一裸片的数量，从而提升芯片集成结构的性能。例如，当第一裸片包括存储容量时，第一芯片结构层中单位面积内第一裸片的数量增加，有利于提高第一芯片结构层的存储容量，进而有利于提高芯片集成结构的存储容量；当第一裸片包括逻辑芯片时，第一芯片结构层中单位面积内第一裸片的数量增加，有利于提高第一芯片结构层的计算处理速率，进而有利于提高芯片集成结构的计算处理速率。
在一些实施例中，第一芯片结构层的数量为多个。将第一芯片结构层设置在封装基板的一侧，并使第一芯片结构层与封装基板电连接，包括：将多个第一芯片结构层依次层叠设置在封装基板上，其中，多个第一芯片结构层中，最靠近封装基板的第一芯片结构层与封装基板电连接，且任意相邻的两个第一芯片结构层之间电连接。如上述实施例中所述，相邻的第一芯片结构层可以通过第一重布线层进行电连接。在将多个第一芯片结构层依次层叠设置在封装基板的过程中，可以在设置一个第一芯片结构层以后，再改第一芯片结构层远离封装基板的一侧设置一个第一重布线 层，然后在该第一重布线层远离封装基板的一侧设置第二个第一芯片结构层……依次类推，通过上述设置可以实现任意相邻的两个第一芯片结构层之间电连接。
在一些实施例中，将第一芯片结构层设置在封装基板的一侧，并使第一芯片结构层与封装基板电连接之前，还包括：在载片上形成第二芯片结构层；将第一芯片结构层设置在第二芯片结构层远离载片的一侧，并使第一芯片结构层与第二芯片结构层电连接。将第一芯片结构层设置在封装基板的一侧，并使第一芯片结构层与封装基板电连接，包括：去除载片；将第二芯片结构层远离第一芯片结构层的一侧与封装基板电连接。通过上述步骤，可以实现封装基板、第二芯片结构层以及第一芯片结构层之间的层叠设置及电连接，从而形成芯片集成结构。
在一些实施例中，在载片上形成第二芯片结构层，包括：从第一晶圆中挑选结构芯片，并将挑选的结构芯片设置在载片上；从第二晶圆中挑选第二裸片，并将挑选的第二裸片设置在载片上；在结构芯片和第二裸片之间形成隔离结构，结构芯片、第二裸片和隔离结构共同构成第二芯片结构层。通过上述设置，可以在载片上形成第二芯片结构层，从而提高芯片集成结构的性能。
在一些实施例中，将第一芯片结构层设置在封装基板的一侧，并使第一芯片结构层与封装基板电连接之前，还包括：在第一芯片结构层上形成第二芯片结构层，并使第一芯片结构层与第二芯片结构层电连接。将第一芯片结构层设置在封装基板的一侧，并使第一芯片结构层与封装基板电连接，还包括：将第二芯片结构层远离第一芯片结构层的一侧与封装基板电连接。通过上述步骤，可以实现封装基板、第二芯片结构层以及第一芯片结构层之间的层叠设置及电连接，从而形成芯片集成结构。
在一些实施例中，在第一芯片结构层上形成第二芯片结构层，并使第一芯片结构层与第二芯片结构层电连接，包括：从第一晶圆中挑选结构芯片，并将挑选的结构芯片设置在第一芯片结构层上，使结构芯片与第一芯片结构层连接；从第二晶圆中挑选第二裸片，并将挑选的第二裸片设置在第一芯片结构层上，使第二裸片与第一芯片结构层电连接；在结构芯片和第二裸片之间形成隔离结构，结构芯片、第二裸片和隔离结构共同构成第二芯片结构层。通过上述设置，可以在第一芯片结构层上形成第二芯片结构层，从而提高芯片集成结构的性能。
又一方面，还提供一种电子设备，包括印刷电路板和如上述实施例中的芯片集成结构，所述芯片集成结构与所述印刷电路板电性连接。
本申请的实施例提供的电子设备包括如上述的芯片集成结构，因此具有上述的全部有益效果，在此不再赘述。
附图说明
图1为本申请实施例提供的一种电子设备的结构图；
图2为目前一些实施例提供的一种芯片堆叠结构的结构图；
图3为目前一些实施例提供的一种芯片晶圆的结构图；
图4为本申请实施例提供的一种芯片集成结构的结构图；
图5为本申请实施例提供的一种第一芯片结构层的俯视图；
图6为本申请实施例提供的一种晶圆的结构图；
图7为本申请实施例提供的一种第一芯片结构层的剖面图；
图8为图7中第一芯片结构层沿S1-S2剖面线的剖面图；
图9为本申请实施例提供的一种第一芯片结构层的剖面图；
图10为本申请实施例提供的另一种第一芯片结构层的俯视图；
图11为本申请实施例提供的另一种芯片集成结构的结构图；
图12为本申请实施例提供的另一种芯片集成结构的结构图；
图13为本申请实施例提供的又一种芯片集成结构的结构图；
图14为本申请实施例提供的再一种芯片集成结构的结构图；
图15为本申请实施例提供的一种芯片集成结构的制备方法的步骤流程图；
图16为本申请实施例提供的又一种芯片集成结构的制备方法的步骤流程图；
图17为图16中的芯片集成结构的制备方法中的制备过程的结构图；
图18为本申请实施例提供的又一种芯片集成结构的制备方法的步骤流程图；
图19为图18中的芯片集成结构的制备方法中的制备过程芯片集成结构的结构图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在本申请实施例中，除非另有明确的规定和限定，术语“电连接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或“例如”等词旨在以具体方式呈现相关概念。
在本申请实施例中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
在本申请实施例中，例如上、下、左、右、前和后等用于解释本申请中不同部件的结构和运动的方向指示是相对的。当部件处于图中所示的位置时，这些指示是恰当的。但是，如果元件位置的说明发生变化，那么这些方向指示也将会相应地发生变化。
图1为本申请实施例提供的一种电子设备的结构图。该电子设备1000可以包括图像传感器、NAND闪存、高带宽存储器、手机(mobile phone)、平板电脑(pad)、电视、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备等电子产品。本申请实施例对上述电子设备1000的具体形式不做特殊限制。
上述电子设备1000可以包括印刷电路板3(printed circuit board，PCB)、芯片集成结构1以及设置在印刷电路板3和芯片集成结构1之间的第一连接件2，芯片集成结构1通过第一连接件2与印刷电路板3电连接。第一连接件2例如可以为球栅阵列(ball grid array，BGA)。
图2为目前一些实施例提供的一种芯片堆叠结构91的结构图。如图2所示，芯片堆叠结构91包括封装基板911(substrate)和多个堆叠层912，多个堆叠层912在封装基板911的一侧堆叠设置，且任一堆叠层912均与封装基板911电连接。其中，每一堆叠层912中可以包括多个芯片921，每一芯片921靠近封装基板911的一侧均设置有一个导电柱913，芯片921通过相应的导电柱913与封装基板911电连接。
图3为目前一些实施例提供的一种芯片晶圆92的结构图。如图3所示，在上述芯片堆叠结构91的制作过程中，需要在芯片晶圆92上进行挑选，并将挑选后的功能芯片921间隔设置，以形成堆叠层。可以理解的是，在晶圆(wafer)上生长外延层后，形成了所述的芯片晶圆92。芯片晶圆92包括切割道结构922和芯片921，切割道结构922将多个芯片921分隔开。在切割芯片晶圆92时，激光会照射切割道结构922，对切割道结构922加热，以在切割道结构922上画出切割槽，便于实现功能芯片之间的分离。通过上述工艺步骤，可以得到所需的芯片921，该芯片921即为裸芯片(die)。
然而，通过挑选的方式形成堆叠层912，同一堆叠层912中相邻芯片921之间的间隔较大，导致同一堆叠层912的单位面积内，设置的芯片921的数量降低，进而导致堆叠层912的性能较差。例如，当芯片921为存储容量时，同一堆叠层912的单位面积内存储容量较小；当芯片921为逻辑芯片(logic)时，同一堆叠层的单位面积内计算处理能力降低。同时，通过挑选的方式形成堆叠层912，需要进行多次切割以得到多个芯片921，制备工艺较为复杂，加工效率较低，进而导致产品产出效率也降低。
基于此，本申请实施例提供一种芯片集成结构1。本申请实施例所提供的芯片集成结构1可以应用于大容量、高宽带需求下的中央处理器(Central Processing Unit，CPU)、图形处理器(graphics processing unit，GPU)、AI芯片等。
图4为本申请实施例提供的一种芯片集成结构1的结构图。如图4所示，芯片集成结构1包 括封装基板30和第一芯片结构层10。其中，第一芯片结构层10位于封装基板30的一侧，且与封装基板30电连接。
如上述实施例中所示，芯片集成结构1可以通过第一连接件2与印刷电路板3电连接，即指芯片集成结构1中的封装基板30通过第一连接件2与印刷电路板3电连接。由于第一芯片结构层10通过第二连接件20与封装基板30电连接，封装基板30通过第一连接件2与印刷电路板3电连接，从而可以实现芯片集成结构1与电子设备1000的通信。
如图4所示，第一芯片结构层10和封装基板30之间可以设置有第二连接件20，第一芯片结构可以通过第二连接件20与封装基板30电连接。第二连接件20例如可以包括中间重布线层21(Redistribution Layer，RDL)，中间重布线层21位于第一芯片结构层10和封装基板30之间，中间重布线层21用于将第一芯片结构层10的布线重新布局，方便在中间重布线层21上制备其他需要的结构。第二连接件20例如还可以包括凸块22(Micro Bump，uBump)，凸块22位于中间重布线层21和封装基板30之间，中间重布线层21通过凸块22与封装基板30电连接。凸块22的材质例如可以包括锡等金属。
继续参照图4，第一芯片结构层10包括切割道结构12和多个第一裸片11。其中，切割道结构12连接多个第一裸片11，且将多个第一裸片11分隔开。本申请实施例中，第一芯片结构层10中第一裸片11的数量不进行限定，可以根据应用需要进行设置。进一步地，第一芯片结构中，多个第一裸片11的尺寸可以相同也可以不相同，本申请实施例对此不进行具体限定。
其中，第一裸片11具有电性功能。此处，“电性功能”是指第一裸片11具有器件且能够上电工作。第一裸片11可以包括数字芯片、模拟芯片以及光芯片等等。例如，可以为存储芯片、逻辑芯片或其它任何功能的芯片等，存储芯片例如可以动态随机存取存储(dynamic random access memory，DRAM)芯片。此外，第一芯片结构层10中的多个第一裸片11可以是同一类型芯片，例如均为存储芯片；也可以是不同类型芯，例如可以使用相应工艺在同一片晶圆上加工出不同类型的芯片。基于此，本申请实施例提供的第一裸片11可以实现同类或不同类芯片之间的集成。
图5为本申请实施例提供的一种第一芯片结构层10的俯视图。如图5所示，第一芯片结构层10可以包括三个第一裸片11，三个第一裸片11并列排布，且相邻第一裸片11之间通过切割道结构12连接。图6为本申请实施例提供的一种晶圆的结构图。如图5和图6所示，晶圆100包括切割道结构12和多个裸芯片(die)，切割道结构12将多个裸芯片分隔开。
结合图5和图6所示，图5中的第一裸片11可以是从图6中的晶圆100中得到的。示意性的，以图中A处的切割道结构12为例进行说明，由于A处的切割道结构12中围设在相邻的三个裸芯片外围，沿A处的切割道结构12进行切割以后，相邻的三个裸芯片从晶圆100中分离出来，且三个裸芯片之间的切割道结构12(如图中B处的切割道结构12)得到保留，也即得到了图5中具有三个第一裸片11的第一芯片结构层10。其中，三个裸芯片即为第一芯片结构层10中的三个第一裸片11，三个裸芯片之间保留的切割道结构12即为第一芯片结构层10中的切割道结构12。
综上所述，由于切割道结构12连接多个第一裸片11，且将多个第一裸片11分隔开。每个第一裸片11均为一个裸芯片，也即，多个第一裸片11为位于同一晶圆100中的多个裸芯片，且相邻的裸芯片之间通过切割道结构12连接，也即该多个第一裸片之间的切割道区域未被切割，故保留有切割道结构。通过上述设置，有利于缩小第一芯片结构层10中相邻第一裸片11之间的间距，进而提高第一芯片结构层10中单位面积内第一裸片11的数量，从而提升芯片集成结构1的集成度，进而提升芯片集成结构1的性能。例如，当第一裸片11包括存储芯片时，第一芯片结构层10中单位面积内第一裸片11的数量增加，有利于提高第一芯片结构层10的存储容量，进而有利于提高芯片集成结构1的存储容量；当第一裸片11包括逻辑芯片时，第一芯片结构层10中单位面积内第一裸片11的数量增加，有利于提高第一芯片结构层10的计算处理速率，进而有利于提高芯片集成结构1的计算处理速率。
同时，由于多个第一裸片11为位于同一晶圆100中的多个裸芯片，可以通过一次切割得到多个第一裸片11，有利于提高芯片集成结构1的加工效率，进而提高单位时间内芯片集成结构1的产量。
可以理解的是，目前的较为常见的另一种芯片堆叠结构中，通常将多个功能芯片堆叠设置， 也即每一堆叠层包括一个功能芯片。本申请实施例提供的芯片集成结构1，通过切割道结构12连接多个第一裸片11，且将多个第一裸片11分隔开，在堆叠层数相同的情况下，相比于目前的芯片堆叠结构，可以实现性能的成倍的提升。
图7为本申请实施例提供的一种第一芯片结构层10的剖面图。参照图7，第一裸片11可以包括第一衬底111，切割道结构12可以包括第一连接衬底121；第一连接衬底121与第一衬底111相连，且同层设置。示例性的，相邻的第一衬底111之间可以通过第一连接衬底121连接。此处，“同层设置”是指第一衬底111和第一连接衬底121采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构，一次构图工艺可以包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形的材质相同。
其中，第一衬底111和第一连接衬底121的材料可以相同，例如第一衬底111和第一连接衬底121可以是半导体材料构成，可以是硅衬底、砷化镓(GaAs)衬底、磷酸镓砷(GaAsP)衬底、碳化硅(SiC)衬底等。当然，第一衬底111和第一连接衬底121的材质也可以包括其他材质，本申请实施例对此不进行具体限定。
继续参照图7，第一裸片11可以包括密封圈(seal ring)113，密封圈113位于第一裸片11的边缘区域，且密封圈113与切割道结构12相邻接。示例性的，第一裸片11的边缘区域可以为沿第一裸片11的周向方向设置一周的区域，也即，密封圈113沿第一裸片11的周向方向设置一周。图8为图7中第一芯片结构层10沿S1-S2剖面线的剖面图。如图8所示，密封圈113包括多个层叠设置的密封层113A以及多个密封插塞113B，一个密封插塞113B位于相邻的两个密封层113A之间，且密封插塞113B与相邻的两个密封层113A之间接触。可以理解的是，在对与第一裸片11相邻接的切割道结构进行切割时，应力容易传递至第一裸片11内，导致第一裸片11内损伤，进而导致第一裸片11的性能降低。通过设置密封圈113，有利于减小传递至第一裸片11内的应力，进而降低第一裸片11的出现损伤的现象，有利于提高第一裸片11的性能。
继续参照图7，第一裸片11可以包括多个第一绝缘层1121，多个第一绝缘层1121位于第一衬底111上，且多个第一绝缘层1121层叠设置；切割道结构12包括多个第一绝缘连接层122，多个第一绝缘连接层122位于第一连接衬底121上，且多个第一绝缘连接层122层叠设置。其中，多个第一绝缘连接层122与多个第一绝缘层1121一一对应连接，且对应连接的第一绝缘连接层122与第一绝缘层1121同层设置。示例性的，相邻的第一裸片11中的对应的两个第一绝缘层1121之间通过对应的第一绝缘连接层122连接。此处，“同层设置”是指第一绝缘层1121和第一绝缘连接层122采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构，一次构图工艺可以包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形的材质相同。
其中，第一绝缘层1121和第一绝缘连接层122的材质可以包括氧化硅、氮化硅以及氮氧化硅中一种或者多种的组合。当然，第一绝缘层1121和第一绝缘连接层122的材质也可以包括其他材质，本申请实施例对此不进行具体限定。
图9为本申请实施例提供的一种第一芯片结构层10的剖面图。参照图9，第一裸片11还可以包括多个第一导电层1122，多个第一导电层1122位于第一衬底111上，且多个第一导电层1122层叠设置。示例性的，第一导电层1122与第一绝缘层1121位于第一衬底111的同一侧。如上述实施例中所述，切割道结构12包括多个第一绝缘连接层122，多个第一绝缘连接层122位于第一连接衬底121上，且多个第一绝缘连接层122层叠设置。其中，多个第一绝缘连接层122与多个第一导电层1122可以数量相同。示例性的，多个第一绝缘连接层122和多个第一导电层1122可以一一对应，以使多个第一绝缘连接层122与多个第一导电层1122数量相同。第一导电层1122包括多层金属线路，金属线路用于将多个电子元器件电连接在一起，以构成第一裸片11的电路结构。电子元器件例如可以包括晶体管、电容电阻等等。层叠设置的第一导电层1122和第一绝缘层1121共同构成第一裸片11的功能层112，以便实现第一裸片11的存储、逻辑或者其他功能。当然，在一些其他的实施例中，多个第一绝缘连接层122的数量可以大于多个第一导电层1122的数量，且多个第一导电层1122可以与部分第一绝缘连接层122一一对应，本申请实施例对此不进行限定。
在一些实施例中，结合图4所示，第一绝缘层1121可以相对于第一衬底111靠近封装基板30，相应的，第一绝缘连接层122相对于第一连接衬底121靠近封装基板30。当然，在一些其他的实施例中，相应的，第一绝缘层1121可以相对于第一衬底111远离封装基板30，第一绝缘连接层122相对于第一连接衬底121远离封装基板30。
参照图7，切割道结构12可以包括定位标记123。示例性的，第一连接衬底121上可以设置有至少一个定位标记123。在一些实施例中，定位标记123的数量可以仅为一个。其中，定位标记123可以设置在第一连接衬底121上，且位于第一连接衬底121和第一绝缘连接层122之间。在一些其他的实施例中，定位标记123的数量可以为多个。其中，多个定位标记123可以均位于第一连接衬底121上。通过在第一连接衬底121上设置有至少一个定位标记123，定位标记123可以在制备第一绝缘层1121和第一绝缘连接层122的过程中起到定位的作用。
参照图7，示例性的，至少一个第一绝缘连接层122上可以设置有至少一个定位标记123。在一些实施例中，定位标记123的数量可以仅为一个。定位标记123位于第一绝缘连接层122上，且与第一绝缘连接层122位于第一连接衬底121的同一侧。在一些其他的实施例中，定位标记123的数量可以为多个。其中，多个定位标记123可以均位于第一连接衬底121或者任一第一绝缘连接层122上；此处，定位标记123可以在制备第一绝缘层1121和第一绝缘连接层122的过程中起到定位的作用。
在一些其他实施例中，多个定位标记123中，一部分定位标记123位于第一连接衬底121上，另一部分定位标记123位于第一绝缘连接层122上(例如，一个定位标记123可以位于一个第一绝缘连接层122上，本申请实施例对此不进行具体限定)。
继续参照图9，切割道结构12包括多个金属层124，多个金属层124位于第一连接衬底121上，且多个金属层124层叠设置。其中，多个金属层124与部分多个第一导电层1122一一对应，对应的金属层124和第一导电层1122同层设置且电性隔离。例如第一绝缘连接层122上可以设置有多个金属层124，多个金属层124可以层叠设置，且与第一绝缘连接层122位于第一连接衬底121的同一侧。其中，多个金属层124与部分多个第一导电层1122一一对应且不接触，以使对应的金属层124和第一导电层1122之间电性隔离。此处，“同层设置”是指金属层124和第一导电层1122采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构，一次构图工艺可以包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形的材质相同。
在一些实施例中，多个金属层124的至少部分构成测试结构。此处，通过特定测试机台对测试结构(Testkey)进行测试，从而反应第一裸片11的制作过程中的工艺波动以及侦测产线是否出现异常。
图10为本申请实施例提供的另一种第一芯片结构层10的俯视图。如图10所示，切割道结构12可以包括第一子切割道结构12A。其中，第一子切割道结构12A沿第一方向X延伸，且均平行于封装基板30。在一些实施例中，第一子切割道结构12A沿第二方向Y的长度H1的取值范围可以为80微米-120微米。例如，第一子切割道结构12A沿第二方向Y的长度H1可以为80微米、90微米或者120微米。
如图10所示，切割道结构12可以包括第二子切割道结构12B。第二子切割道结构12B沿第二方向Y延伸，第一方向X与第二方向Y垂直，且均平行于封装基板30。第二子切割道结构12B沿第一方向X的长度H2的取值范围可以为80微米-120微米。例如，第二子切割道结构12B沿第一方向X的长度H2可以为80微米、90微米或者120微米。
当然，在一些其他的实施例中，第一子切割道结构12A沿第二方向Y的长度H1还可以大于120微米，第二子切割道结构12B沿第一方向X的长度H2还可以大于120微米，本申请实施例不进行具体限定。
示例性的，第一芯片结构层10可以包括六个第一裸片11，且六个第一裸片11阵列排布。相应的，切割道结构12可以包括沿第一方向X延伸的一条第一子切割道结构12A和沿第二方向Y延伸的两条第二子切割道结构12B。通过上述设置，有利于进一步缩小第一芯片结构层10中相邻第一裸片11之间的间距，进一步提高第一芯片结构层10的存储容量。
图11为本申请实施例提供的另一种芯片集成结构1的结构图。如图11所示，芯片集成结构1还可以包括第二芯片结构层40，第二芯片结构层40与第一芯片结构层10层叠设置，第二芯片结构层40与封装基板30电连接。在一些实施例中，第二芯片结构层40可以位于第一芯片结构层10和封装基板30之间，当然，在一些其他实施例中，第二芯片结构层40还可以位于第一芯片结构层10远离封装基板30的一侧，本申请实施例对此不进行限定。通过设置第二芯片结构，有利于进一步提高芯片集成结构1的性能。下面仅以第二芯片结构层40位于第一芯片结构层10和封装基板30之间的实施例进行说明。
继续参照图11，第二连接件20可以位于第二芯片结构层40和封装基板30之间，且第一芯片结构层10通过第二芯片结构层40与第二连接件20电连接，由于第二连接件20还与封装基板30电连接，第一芯片结构层10可以通过第二芯片结构层40和第二连接件20与封装基板30电连接。
继续参照图11，第二芯片结构层40可以包括结构芯片41、第二裸片42以及位于结构芯片41和第二裸片42之间的隔离结构43。示例性的，第二芯片结构可以包括一个第二裸片42和两个结构芯片41，两个结构芯片41分别位于第二裸片42图示位置的左侧和右侧，第二裸片42与结构芯片41之间通过隔离结构43连接。
其中，结构芯片41可以包括结构衬底411，结构衬底411的材质可以与第一衬底111的材质相同，在此不再赘述。当然，结构衬底411的材质可以与第一衬底111的材质不相同，本申请实施例对此不进行限定。通过设置结构芯片41，可以起到支撑的作用，有利于提高芯片集成结构1的稳定性。当然，在一些其他的实施例中，还可以根据实际需要设置结构芯片41的数量，或者省略结构芯片41。
在一些实施例中，结构芯片41还可以包括贯穿结构衬底411的中间导电通孔412，中间导电通孔412的一端与第一裸片11的第一导电层1122电连接，中间导电通孔412的另一端与第二连接件20电连接，以使第一裸片11的第一导电层1122可以通过结构芯片41与第二连接件20电连接，并进一步与封装基板30电连接。其中，中间导电通孔412可以是硅通孔(TSV，Through Silicon Via)，也可以是其他材质的通孔，可以在通孔内填充导电材料以保证导电功能。
其中，通过设置隔离结构43，可以实现结构芯片41和第二裸片42之间的结构连接。第二芯片结构层40中可以包括多个隔离结构43，多个隔离结构43可以同步制备形成。例如，将结构芯片41和第二裸片42间隔设置以后，结构芯片41和第二裸片42之间具有间隙，可以在间隙内填充隔离材料，以形成隔离结构43。隔离结构43的材质例如可以包括氧化硅、氮化硅以及氮氧化硅中一种或者多种的组合。当然，隔离结构43的材质还可以包括其他材料，以实现电性隔离的效果，本申请实施例对此不进行特殊限定。
在一些实施例中，隔离结构43沿第一方向X的长度H3可以大于50微米，例如，隔离结构43沿第一方向的长度H3可以为50微米、100微米或者150微米。通过上述设置，有利于缩小第二裸片42与结构芯片41之间的间距，进而缩小第二芯片结构层40的尺寸，进一步提高芯片集成结构1的性能。
此处，对于第二裸片42的类型不进行限定，第二裸片42的类型可以与第一裸片11的类型相同，或者第二裸片42的类型也可以与第一裸片11不同。如上述实施例中所述，第二裸片42具有电性功能。此处，“电性功能”是指第二裸片42具有器件且能够上电工作。第二裸片42可以包括数字芯片、模拟芯片以及光芯片等等，例如可以为存储芯片、逻辑芯片或其它任何功能的芯片等，本申请实施例对此不进行具体限定。
其中，第二裸片42可以包括第二衬底421以及位于第二衬底421上的功能层422，第一芯片结构层10与第二裸片42的功能层422之间电连接。第二衬底421的材质可以包括氧化硅、氮化硅以及氮氧化硅中一种或者多种的组合。功能层422可以包括第二导电层4221，第二导电层4221包括多层金属线路，金属线路用于将多个电子元器件电连接在一起，以构成第二裸片42的电路结构。示例性的，第一芯片结构层10中的第一裸片11的第一导电层1122可以与第二裸片42的第二导电层4221之间电连接，且第二裸片42还与封装基板30电连接，以实现封装基板30分别与第一裸片11和第二裸片42之间的通信。如上述实施例中所述，由于第二芯片结构层40可以通过 第二连接件20与封装基板30电连接，第二芯片结构层40中第二裸片42可以通过第二连接件20与封装基板30电连接。
继续参照图11，第二裸片42还可以包括贯穿第二衬底421的第二导电通孔423。在一些实施方式中，功能层422相对于第二衬底421靠近封装基板30，功能层422与封装基板30电连接。示例性的，第二导电通孔423可以沿第三方向Z贯穿第二衬底421，第三方向Z垂直于封装基板30。其中，第二导电通孔423的一端与功能层422电连接，第二导电通孔423的另一端与第一芯片结构层10电连接。
通过上述设置，第一芯片结构层10中的第一裸片11可以通过第二导电通孔423与第二裸片42的功能层422电连接，进一步地，第一裸片11中的第一导电层1122可以通过第二导电通孔423与功能层422中的第二导电层4221电连接。如上述实施例中所述，由于第二裸片42可以通过第二连接件20与封装基板30电连接，且功能层422相对于第二衬底421靠近封装基板30，第二连接件20中的中间重布线层21可以用于将功能层422中的布线重新布置，以使功能层422通过第二连接件20与封装基板30电连接。综上所述，通过上述设置，可以实现第一芯片结构层10、第二芯片结构层40与封装基板30三者中两两之间的电连接。
图12为本申请实施例提供的另一种芯片集成结构1的结构图。如图12所示，在一些其他的实施方式中，功能层422相对于第二衬底421远离封装基板30，功能层422与第一芯片结构层10电连接。其中，第二导电通孔423的一端与功能层422电连接，第二导电通孔423的另一端与封装基板30电连接。通过上述设置，第一芯片结构层10中的第一裸片11可以与功能层422电连接，进一步地，第一裸片11的第一导电层1122可以与功能层422的第二导电层4221电连接。如上述实施例中所述，由于第二裸片42可以通过第二连接件20与封装基板30电连接，且第二导电通孔423的一端与封装基板30电连接，第二导电通孔423的一端可以与第二连接件20电连接。由于第二导电通孔423的一端与功能层422电连接，第二导电通孔423的一端可以与功能层422的第一导电层1122电连接。综上所述，通过上述设置，可以实现第一芯片结构层10、第二芯片结构层40与封装基板30三者中两两之间的电连接。
此处，第二导电通孔423可以是硅通孔(TSV，Through Silicon Via)，也可以是其他材质的通孔，可以在通孔内填充导电材料以保证导电功能。
图13为本申请实施例提供的又一种芯片集成结构1的结构图。如图13所示，第一芯片结构层10的数量可以为多个，多个第一芯片结构层10可以沿第三方向Z层叠设置，第三方向Z垂直于封装基板30。其中，相邻的两个第一芯片结构层10电连接，以使每个第一芯片结构层10均与封装基板30电连接。通过设置多个第一芯片结构层10，有利于进一步提高芯片集成结构1的性能。例如，当第一裸片11包括存储容量时，有利于提高芯片集成结构1的存储容量；当第一裸片11包括逻辑芯片时，有利于提高芯片集成结构1的计算处理速率。
在一些实施例中，多个层叠设置的第一芯片结构层10中，相邻的两个第一芯片结构层10之间的堆叠方式可以是功能层112面对功能层112(Face-to-Face，F2F)，其余相邻的两个第一芯片结构层10之间的堆叠方式可以是第一衬底111面对第一衬底111(Back-to-Back，B2B)。
在另外一些实施例中，多个层叠设置的第一芯片结构层10中，相邻的两个第一芯片结构层10之间的堆叠方式均是第一衬底111面对功能层112(Back-to-Face，B2F)。示例性的，如图13所示，任一第一芯片结构层10中功能层112可以均相对于第一衬底111靠近封装基板30。当然，在其他的示例中，任一第一芯片结构层10中功能层112可以均相对于第一衬底111远离封装基板30，本申请实施例对此不进行具体限定。
多个层叠设置的第一芯片结构层10中，多个第一芯片结构层10中的第一裸片11的数量可以相同也可以不同，本申请实施例对此不进行特殊限定。进一步地，多个第一芯片结构层10中的切割道结构12可以沿第三方向Z错开设置，或者，多个第一芯片结构层10中的切割道结构12也可以沿第三方向Z依次交叠，本申请实施例对此不进行特殊限定。
继续参照图13，芯片集成结构1还可以包括第一重布线层50，第一重布线层50位于相邻两个第一芯片结构层10之间。其中，第一重布线层50包括层叠设置的第一部分51和第二部分52，第一部分51与一个第一芯片结构层10电连接，第二部分52与另一个第一芯片结构层10电连接。 示例性的，第一部分51可以位于图示位置中第一重布线层50的上方，用于将相邻两个第一芯片结构层10中位于图示位置中上方的第一芯片结构层10的布线重新布局；相应的，第二部分52可以位于图示位置中第一重布线层50的下方，用于将相邻两个第一芯片结构层10中位于图示位置中下方的第一芯片结构层10的布线重新布局。通过将第一重布线层50的第一部分51和第二部分52电连接在一起，可以使相邻的两个第一芯片结构层10之间通过第一重布线层50电连接。相比于目前使用对叠层912通过导电柱913直接连接在封装基板911上，通过设置第一重布线层50可以实现多个第一芯片结构层10之间的转接，从而实现多个第一芯片结构层10均与封装基板30电连接，有利于缩小第一芯片结构层10与封装基板30之间的连线距离，提升芯片集成结构的性能。
其中，第一部分51和第二部分52的材质可以包括材料例如可以包括铜、铝、镍、金、银、钛、钴、钨等中的一种或多种导电材料，或者其他导电合金材料。
继续参照图13，第一重布线层50还包括第一键合部53和第二键合部54，第二部分52与第一部分51可以通过第一键合部53和第二键合部54键合。此处，键合(Bonding)，是将两片表面清洁、原子级平整的同质或异质半导体材料经表面清洗和活化处理，在一定条件下直接结合，通过范德华力、分子力甚至原子力使晶片键合成为一体的技术。比如，键合方式例如可以为混合键合(Hybrid Bonding)。其中，第一键合部53位于第一部分51靠近第二部分52的一侧，第二键合部54位于第二部分52靠近第一部分51的一侧。示例性的，第一键合部53的数量为多个，第二键合部54的数量为多个，多个第一键合部53和多个第二键合部54一一对应设置。通过上述设置，由于第一键合部53和第二键合部54沿第三方向Z的长度较小，有利于减小相邻第一芯片结构层10之间的间距，便于布置更多线路，实现相邻第一芯片结构层10之间进行更多线路的信息传输以实现更多功能，同时，还有利于降低芯片集成结构1的厚度。
继续参照图13，第一键合部53靠近第二部分52的一端的截面面积可以大于靠近第一部分51的一端的截面面积。此处，“截面面积”是指第一键合部53沿第一方向X上的截面面积。第二键合部54靠近第一部分51的一端的截面面积可以大于靠近第二部分52的一端的截面面积。此处，“截面面积”是指第二键合部54沿第一方向X上的截面面积。通过上述设置，便于第一键合部53靠近第二部分52的一端与第二键合部54靠近第一部分51的一端接触，有利于实现第一键合部53和第二键合部54之间的键合，保证第一重布线层50的导电性能。
继续参照图13，第一键合部53可以包括层叠设置的第一连接垫531和第二连接垫532，第一连接垫531相对于第二连接垫532靠近第一部分51，在平行于封装基板30的方向上，第二连接垫532的截面面积大于第一连接垫531的截面面积。示例性的，平行于封装基板30的方向即为图示的第一方向X，由于第二连接垫532的截面面积大于第一连接垫531的截面面积，便于第一键合部53通过第二连接垫532与第二键合部54接触。
继续参照图13，第二键合部54可以包括层叠设置的第三连接垫541和第四连接垫542，第三连接垫541相对于第四连接垫542靠近第二部分52，在平行于封装基板30的方向上，第四连接垫542的截面面积大于第三连接垫541的截面面积。示例性的，平行于封装基板30的方向即为图示的第一方向X，由于第四连接垫542的截面面积大于第三连接垫541的截面面积，便于第二键合部54通过第四连接垫542与第一键合部53接触。通过上述设置，有利于便于第二连接垫532与第四连接垫542接触，有利于实现第一键合部53和第二键合部54之间的键合，保证第一重布线层50的导电性能。
当然，在一些其他的示例中，第一重布线层50还可以包括凸块22，凸块22位于第一部分51和第二部分52之间，以使第一部分51和第二部分52通过凸块22电连接在一起。
继续参照图13，多个第一芯片结构层10可以位于第二芯片结构层40远离封装基板30的一侧。多个层叠设置的第一芯片结构层10中，与封装基板30之间的距离最远的第一芯片结构层10可以为顶层结构层10A，位于顶层结构层10A和封装基板30之间的第一芯片结构层10可以为中间结构层10B。其中，中间结构层10B可以包括沿第三方向Z贯穿第一裸片11的第一导电通孔13，顶层结构层10A还可以通过中间结构层10B的第一导电通孔13电连接。
示例性的，位于顶层结构层10A和中间结构层10B之间的第一重布线层50中，第一部分51与顶层结构层10A中的第一导电层1122电连接，第二部分52与中间结构层10B中的第一导电通 孔13电连接。可见，通过设置第一导电通孔13，可以实现顶层结构层10A与中间结构层10B之间的电连接。
示例性的，位于相邻的中间结构层10B之间的第一重布线层50中，第一部分51与图示位置中上方的中间结构层10B的第一导电通孔13电连接，第一部分51还与图示位置中上方的中间结构层10B的第一导电层1122电连接，第二部分52与图示位置中下方的中间结构层10B的第一导电通孔13电连接。可见，通过设置第一导电通孔13，还能够实现相邻的中间结构层10B之间的电连接，并且顶层结构层10A还能够通过多个第一导电通孔13与任一中间结构层10B电连接。
继续参照图13，芯片集成结构1还可以包括第二重布线层60。如上述实施例中所述，第二芯片结构层40可以位于第一芯片结构层10和封装基板30之间，此处，第一芯片结构层10为多个第一芯片结构层10中最靠近封装基板30的一个第一芯片结构层10。第二重布线层60位于第一芯片结构层10和第二芯片结构层40之间，第一芯片结构层10和第二芯片结构层40之间通过第二重布线层60电连接。
在一些实施例中，第二重布线层60的结构可以与第一重布线层50的结构相同，从而有利于提高芯片集成结构1的规整性，提高芯片集成结构1的制备效率。
示例性的，第二重布线层60靠近第一芯片结构层10的一侧与第一导电通孔13电连接。结构层中的第二重布线层60靠近第二芯片结构层40的一侧与中间导电通孔412和第二裸片42电连接。在第二裸片42中的功能层422相对与第二衬底421靠近封装基板30的实施例中，功能层422与封装基板30电连接，第二导电通孔423的一端与功能层422电连接，第二导电通孔423的另一端与第二重布线层60电连接；在第二裸片42中的功能层422相对于第二衬底421远离封装基板30的实施例中，功能层422与第二重布线层60电连接，第二导电通孔423的一端与功能层422电连接，第二导电通孔423的另一端与封装基板30电连接。通过上述设置，第一芯片结构层10可以通过第二重布线层60与第二芯片结构层40实现电连接。
图14为本申请实施例提供的再一种芯片集成结构1的结构图。如图14所示，芯片集成结构1还可以包括第三裸片70，第三裸片70可以与第一芯片结构层10层叠设置，第三裸片70与封装基板30电连接。示例性的，第三裸片70可以位于第一芯片结构层10和第二芯片结构层40之间，此处，该第一芯片结构层10为多个第一芯片结构层10中最靠近封装基板30的一个第一芯片结构层10。第三裸片70还分别与第一芯片结构层10和第二芯片结构层40电连接，以使第三裸片70与封装基板30电连接。第三裸片70包括第三衬底71和位于第三衬底71一侧的第三导电层72。例如，第三裸片70与第一芯片结构层10之间的堆叠方式可以为第三衬底71面对功能层112(Back-to-Face，B2F)。通过设置第三裸片70，有利于进一步提高芯片集成结构1的性能。
此处，对于第三裸片70的类型不进行限定，第三裸片70的类型可以与第一裸片11的类型相同，或者第三裸片70的类型也可以与第一裸片11不同。如上述实施例中所述，第三裸片70具有电性功能。此处，“电性功能”是指第三裸片70具有器件且能够上电工作。第三裸片70可以包括数字芯片、模拟芯片以及光芯片等等，例如可以为存储芯片、逻辑芯片或其它任何功能的芯片等，本申请实施例对此不进行具体限定。
其中，第一重布线层50还可以位于第三裸片70与第一芯片结构层10之间，第三裸片70与第一芯片结构层10可以通过第一重布线层50电连接；第二重布线层60还可以位于第三裸片70与第二芯片结构层40之间，第三裸片70与第二芯片结构层40可以通过第二重布线层60电连接。示例性的，第三裸片70还可以包括沿第三方向Z贯穿其的第三导电通孔73，第三导电通孔73的一端与第一重布线层50电连接，第二导电通孔423的另一端与第二重布线层60电连接。其中，第三导电通孔73可以是硅通孔(TSV，Through Silicon Via)，也可以是其他材质的通孔，可以在通孔内填充导电材料以保证导电功能。
当然，在一些其他的实施例中，第三裸片70还可以位于相邻两个第一芯片结构层10之间，或者位于第一芯片结构层10远离封装基板30的一侧(此处，该第一芯片结构层10为多个第一芯片结构层10中距离封装基板30最远的一个第一芯片结构层10)。本申请实施例对第三裸片70的位置不进行具体限定。
基于此，本申请实施例还提供一种芯片集成结构1的制备方法，上述实施例中的芯片集成结 构1可以采用芯片集成结构1的制备方法进行制备。图15为本申请实施例提供的一种芯片集成结构1的制备方法的步骤流程图。如图15所示，并结合图14，芯片集成结构1的制备方法可以包括以下步骤S101至S103。
S101、提供封装基板。
封装基板30可以是具有布线电路的电路板，也可以是包括硅(例如单晶硅)、陶瓷、玻璃或任何其他适当的材料所形成的衬底。在一些实施例中，封装基板30上可设置有多个用于形成电连接的结构，比如位于封装基板30上表面的焊垫结构、位于封装基板30下表面的触点结构以及位于封装基板30内部的线路结构等。
本实施例中，在提供封装基板30以后，还包括步骤S102。
S102、提供第一芯片结构层，第一芯片结构层包括切割道结构和多个第一裸片，切割道结构连接多个第一裸片，且将多个第一裸片电性分隔，第一裸片具有电性功能。
由于切割道结构12连接多个第一裸片11，且将多个第一裸片11分隔开。每个第一裸片11均为一个裸芯片，也即，多个第一裸片11为位于同一晶圆100中的多个裸芯片，且相邻的裸芯片之间通过切割道结构12连接。此处，第一芯片结构层10的制备过程可以如上述实施例中所述，在此不再赘述。
如上述实施例中所述，第一芯片结构层10的数量可以为多个相邻的第一芯片结构层10可以通过第一重布线层50进行电连接。
在将多个第一芯片结构层10依次层叠设置的过程中，可以在第一芯片结构层10的一侧设置一个第一重布线层50，然后在该第一重布线层50的另一侧设置第二个第一芯片结构层10……依次类推，通过上述设置可以实现任意相邻的两个第一芯片结构层10电连接。其中，第一重布线层50的制备过程可以包括相关工艺中的重布线工艺制程和键合界面工艺制程，本申请实施例在此不再赘述。
本实施例中，在提供第一芯片结构层10，第一芯片结构层10包括切割道结构12和多个第一裸片11，切割道结构12连接多个第一裸片11，且将多个第一裸片11分隔开以后，还包括步骤S103。
S103、将第一芯片结构层设置在封装基板的一侧，并使第一芯片结构层与封装基板电连接。
综上所述，通过上述设置，有利于缩小第一芯片结构层10中相邻第一裸片11之间的间距，进而提高第一芯片结构层10中单位面积内第一裸片11的数量，从而提升芯片集成结构1的性能。例如，当第一裸片11包括存储容量时，第一芯片结构层10中单位面积内第一裸片11的数量增加，有利于提高第一芯片结构层10的存储容量，进而有利于提高芯片集成结构1的存储容量；当第一裸片11包括逻辑芯片时，第一芯片结构层10中单位面积内第一裸片11的数量增加，有利于提高第一芯片结构层10的计算处理速率，进而有利于提高芯片集成结构1的计算处理速率。
图16为本申请实施例提供的又一种芯片集成结构1的制备方法的步骤流程图，图17为图16中的芯片集成结构1的制备方法中的制备过程的结构图。如图16和图17所示，在一些实施例中，芯片集成结构1的制备方法可以包括以下步骤S211至S214。
如图17所示，提供第一芯片结构层10的步骤可以包括：提供多个第一芯片结构层10其中，多个第一芯片结构层10可以分别位于不同的晶圆内。
如上述实施例中所述，多个第一芯片结构层10依次层叠设置，且任意相邻的两个第一芯片结构层10电连接。在一些实施例中，可以将多个第一芯片结构层10所在的晶圆依次层叠设置，且任意相邻的两个晶圆电连接。例如，晶圆C和晶圆D均可以包括多个第一芯片结构层10，将晶圆C和晶圆D层叠设置，且晶圆C和晶圆D之间电连接，以使晶圆C中的第一芯片结构层10与晶圆D中对应的第一芯片结构层10层叠设置，且对应的两个第一芯片结构层10电连接。其中，多个第一芯片结构层10所在的晶圆依次层叠设置的步骤可以如上述实施例中所述，此处不再赘述。
本申请实施例中，在提供第一芯片结构层10之后，以及，将第一芯片结构层10设置在封装基板30的一侧，并使第一芯片结构层10与封装基板30电连接之前，还包括步骤S211。
S211、在载片上形成第二芯片结构层。
可以理解的是，由于芯片的厚度较薄，在第二芯片结构层40的制作过程中，需要使用载片 40C(carrier)作为临时键合结构，方便芯片在载片40C上进行结构的制作，该载片40C可以称为晶圆载体层，晶圆载体层可以通过硅溶键合(Fusion Bonding)的方式与对应芯片键合连接，最后该晶圆100载体层可以通过研磨去除；或者，晶圆载体层可以通过临时键合(采用键合胶，具有键合薄膜层)的方式与对应芯片键合连接，最后该晶圆载体层可以通过热熔的方式去除。
本实施例中，在载片40C上形成第二芯片结构层40的步骤，可以包括：从第一晶圆40A中挑选结构芯片41，并将挑选的结构芯片41设置在载片40C上。
如上述实施例中所述，结构芯片41可以是半导体材料构成，可以是硅衬底、砷化镓(GaAs)衬底、磷酸镓砷(GaAsP)衬底、碳化硅(SiC)衬底等。通过设置结构芯片41，可以起到支撑的作用，有利于提高芯片集成结构1的稳定性。当然，在一些其他的实施例中，还可以根据实际需要设置结构芯片41的数量，或者省略结构芯片41。
本实施例中，在载片40C上形成第二芯片结构层40的步骤还可以包括：从第二晶圆40B中挑选第二裸片42，并将挑选的第二裸片42设置在载片40C上。
其中，在第二裸片42和结构芯片41的放置过程中，可以使第二裸片42和结构芯片41间隔设置。此处，第二裸片42和结构芯片41之间的排布可以根据实际的需要进行设置，例如，可以在第二芯片结构层40中设置一个第二裸片42和两个结构芯片41，且使两个结构芯片41分别设置在第二裸片42的两侧。
在一些示例中，第一晶圆40A和第二晶圆40B可以为不同的晶圆结构，可以通过挑选的方式，在第一晶圆40A中将所需的结构芯片41切割下来，然后将切割下来的结构芯片41设置在载片40C上；相同的，可以通过挑选的方式，在第二晶圆40B中将所需的第二裸片42切割下来，然后将切割下来的第二裸片42设置在载片40C上。此处，挑选的结构芯片41与第二裸片42均为品质达标的芯片。
本实施例中，在载片40C上形成第二芯片结构层40的步骤还可以包括：在载片40C上设置第二裸片42和结构芯片41以后，在结构芯片41和第二裸片42之间形成隔离结构43，结构芯片41、第二裸片42和隔离结构43共同构成第二芯片结构层40。
其中，由于第二裸片42和结构芯片41间隔设置，第二裸片42和结构芯片41之间具有一定间隙，可以在间隔内填充隔离材料，以形成隔离结构43。在一些实施例中，在形成多个隔离结构43以后，还可以通过化学机械研磨(chemical mechanical polishing，CMP)工艺将第二芯片结构层40远离载片40C的一侧平坦化，便于后续进行加工制备。
本实施例中，将第一芯片结构层10设置在封装基板30的一侧，并使第一芯片结构层10与封装基板30电连接之前，且在载片40C上形成第二芯片结构层40之后，还包括步骤S212。
S212、将第一芯片结构层设置在第二芯片结构层远离载片的一侧，并使第一芯片结构层与第二芯片结构层电连接。
其中，如图13所示，芯片集成结构1还可以包括第二重布线层60，可以在第二芯片结构层40远离载片40C的一侧设置第二重布线层60，然后在第二重布线层60远离所述载片40C的一侧设置第一芯片结构层10。第二重布线层60的结构可以如上述实施例中所述，在此不再赘述。
在第一芯片结构层10的数量为多个的实施例中，将多个第一芯片结构层10所在的层叠设置的晶圆(例如图17中层叠设置的晶圆C与晶圆D，且晶圆C与晶圆D之间电连接)与第二重布线层60电连接，使得晶圆与晶圆之间堆叠，以使任一第一芯片结构层10均与第二芯片结构层40电连接。
本实施例中，将第一芯片结构层10设置在封装基板30的一侧，并使第一芯片结构层10与封装基板30电连接的步骤，还包括步骤S213。
S213、去除载片。
其中，去除载片40C的步骤可以如上述实施例中所述，在此不再赘述。
本实施例中，在去除载片40C以后，将第一芯片结构层10设置在封装基板30的一侧，并使第一芯片结构层10与封装基板30电连接的步骤，还包括步骤S214。
S214、将第二芯片结构层远离第一芯片结构层的一侧与封装基板电连接。
如图13所示，芯片集成结构1还可以包括第二连接件20。将第二芯片结构层40远离第一芯 片结构层10的一侧与封装基板30电连接的步骤还包括：将第二连接件20设置在第二芯片结构层40远离第一芯片结构层10的一侧，将封装基板30设置在第二连接件20远离第二芯片结构层40的一侧，以使第二芯片结构层40通过第二连接件20与封装基板30电连接。第二连接件20的结构可以如上述实施例中所述，本申请实施例对此不进行具体限定。
本实施例中，在将第二芯片结构层40远离第一芯片结构层10的一侧与封装基板30电连接之后，能够形成晶圆M。其中，通过上述步骤，可以实现封装基板30、第二芯片结构层40以及第一芯片结构层10之间的层叠设置及电连接，从而形成芯片集成结构1。晶圆M包括多个芯片集成结构1，可以对晶圆M进行切割，从而得到多个独立的芯片集成结构1。
图18为本申请实施例提供的又一种芯片集成结构1的制备方法的步骤流程图，图19为图18中的芯片集成结构1的制备方法中的制备过程芯片集成结构1的结构图。如图18和图19所示，在另一些实施例中，芯片集成结构1的制备方法可以包括以下步骤S221至S222。
如图19所示，提供第一芯片结构层10的步骤可以包括：提供多个第一芯片结构层10其中，多个第一芯片结构层10可以分别位于不同的晶圆内。
如上述实施例中所述，多个第一芯片结构层10依次层叠设置，且任意相邻的两个第一芯片结构层10电连接。在一些实施例中，可以将多个第一芯片结构层10所在的晶圆依次层叠设置，且任意相邻的两个晶圆电连接。例如，晶圆C和晶圆D均可以包括多个第一芯片结构层10，将晶圆C和晶圆D层叠设置，且晶圆C和晶圆D之间电连接，以使晶圆C中的第一芯片结构层10与晶圆D中对应的第一芯片结构层10层叠设置，且对应的两个第一芯片结构层10电连接。其中，多个第一芯片结构层10所在的晶圆依次层叠设置的步骤可以如上述实施例中所述，此处不再赘述。本实施例中，提供第一芯片结构层10之后，以及，将第一芯片结构层10设置在封装基板30的一侧，并使第一芯片结构层10与封装基板30电连接之前，还包括步骤S221。
S221、在第一芯片结构层上形成第二芯片结构层，并使第一芯片结构层与第二芯片结构层电连接。
本实施例中，在第一芯片结构层10上形成第二芯片结构层40，并使第一芯片结构层10与第二芯片结构层40电连接的步骤，可以包括：从第一晶圆40A中挑选结构芯片41，并将挑选的结构芯片41设置在第一芯片结构层10上，使结构芯片41与第一芯片结构层10连接。
其中，如图13所示，在将结构芯片41设置在第一芯片结构层10之前，可以在第一芯片结构层10上形成第二重布线层60，然后在第二重布线层60远离第一芯片结构层10的一侧设置结构芯片41，从而实现结构芯片41通过第二重布线层60与第一芯片结构层10连接。
本实施例中，在第一芯片结构层10上形成第二芯片结构层40，并使第一芯片结构层10与第二芯片结构层40电连接的步骤，还可以包括：从第二晶圆40B中挑选第二裸片42，并将挑选的第二裸片42设置在第一芯片结构层10上，使第二裸片42与第一芯片结构层10电连接。
其中，第二裸片42可以设置在第二重布线层60远离第一芯片结构层10的一侧，从而实现第二裸片42通过第二重布线层60与第一芯片结构层10电连接。
在第一芯片结构层10的数量为多个的实施例中，在多个第一芯片结构层10所在的层叠设置的晶圆(例如图19中层叠设置的晶圆C与晶圆D，且晶圆C与晶圆D之间电连接)上形成第二重布线层60，然后在第二重布线层60远离第一芯片结构层10的一侧设置结构芯片41和第二裸片42，从而实现晶圆与芯片之间堆叠。
本实施例中，在第二重布线层60远离第一芯片结构层10的一侧设置结构芯片41和第二裸片42以后，还包括：在结构芯片41和第二裸片42之间形成隔离结构43，结构芯片41、第二裸片42和隔离结构43共同构成第二芯片结构层40。
其中，由于第二裸片42和结构芯片41间隔设置，第二裸片42和结构芯片41之间具有一定间隙，可以在间隔内填充隔离材料，以形成隔离结构43。本实施例中，将第一芯片结构层10设置在封装基板30的一侧，并使第一芯片结构层10与封装基板30电连接的步骤，还包括步骤S222。
S222、将第二芯片结构层远离第一芯片结构层的一侧与封装基板电连接。
如上述实施例中所述，如图13所示，芯片集成结构1还可以包括第二连接件20。可以在第二芯片结构层40远离第一芯片结构层10的一侧设置第二连接件20，将封装基板30设置在第二 连接件20远离第二芯片结构层40的一侧，以使第二芯片结构层40通过第二连接件20与封装基板30电连接。第二连接件20的结构可以如上述实施例中所述，本申请实施例对此不进行具体限定。
本实施例中，在将第二芯片结构层40远离第一芯片结构层10的一侧与封装基板30电连接之后，能够形成晶圆M。其中，通过上述步骤，可以实现封装基板30、第二芯片结构层40以及第一芯片结构层10之间的层叠设置及电连接，从而形成芯片集成结构1。晶圆M包括多个芯片集成结构1，可以对晶圆M进行切割，从而得到多个独立的芯片集成结构1。
本申请实施例中封装基板30、第二芯片结构层40以及第一芯片结构层10之间的堆叠步骤也可以不限于上述两种实施方式，本申请实施例对此不进行具体的限定。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (27)

  1. 一种芯片集成结构，其特征在于，包括：封装基板和第一芯片结构层；所述第一芯片结构层位于所述封装基板的一侧，且与所述封装基板电连接；
    所述第一芯片结构层包括切割道结构和多个第一裸片；所述切割道结构连接所述多个第一裸片，且将所述多个第一裸片电性分隔；所述第一裸片具有电性功能。
  2. 根据权利要求1所述的芯片集成结构，其特征在于，
    所述第一裸片包括第一衬底；所述切割道结构包括第一连接衬底；所述第一连接衬底与所述第一衬底相连，且同层设置。
  3. 根据权利要求1或2所述的芯片集成结构，其特征在于，所述第一裸片还包括密封圈，所述密封圈位于所述第一裸片的边缘区域，且所述密封圈与所述切割道结构相邻接。
  4. 根据权利要求2或3所述的芯片集成结构，其特征在于，
    所述第一裸片还包括多个第一绝缘层，所述多个第一绝缘层位于所述第一衬底上，且所述多个第一绝缘层层叠设置；
    所述切割道结构还包括多个第一绝缘连接层，所述多个第一绝缘连接层位于所述第一连接衬底上，且所述多个第一绝缘连接层层叠设置；
    其中，所述多个第一绝缘连接层与所述多个第一绝缘层一一对应连接，且对应连接的第一绝缘连接层与第一绝缘层同层设置。
  5. 根据权利要求2-4中任一项所述的芯片集成结构，其特征在于，
    所述第一裸片还包括多个第一导电层，所述多个第一导电层位于所述第一衬底上，且所述多个第一导电层层叠设置；
    所述切割道结构还包括多个第一绝缘连接层，所述多个第一绝缘连接层位于所述第一连接衬底上，且所述多个第一绝缘连接层层叠设置；
    其中，所述多个第一绝缘连接层与所述多个第一导电层的数量相同。
  6. 根据权利要求5所述的芯片集成结构，其特征在于，所述切割道结构包括多个金属层，所述多个金属层位于所述第一连接衬底上，且所述多个金属层层叠设置；
    其中，所述多个金属层与部分所述多个第一导电层一一对应，对应的金属层和第一导电层同层设置且电性隔离。
  7. 根据权利要求6所述的芯片集成结构，其特征在于，所述多个金属层的至少部分构成测试结构。
  8. 根据权利要求1-7中任一项所述的芯片集成结构，其特征在于，所述切割道结构包括定位标记。
  9. 根据权利要求1-8中任一项所述的芯片集成结构，其特征在于，
    所述切割道结构包括第一子切割道结构，所述第一子切割道结构沿第一方向延伸，所述第一子切割道结构沿第二方向的长度的取值范围为80微米-120微米；其中，所述第一方向与所述第二方向垂直，且均平行于所述封装基板；
    和/或，
    所述切割道结构包括第二子切割道结构，所述第二子切割道结构沿第二方向延伸，所述第二子切割道结构沿第一方向的长度的取值范围为80微米-120微米；其中，所述第一方向与所述第二方向垂直，且均平行于所述封装基板。
  10. 根据权利要求1-9中任一项所述的芯片集成结构，其特征在于，
    所述第一芯片结构层的数量为多个，多个所述第一芯片结构层沿第三方向层叠设置，所述第三方向垂直于所述封装基板；
    其中，相邻的两个所述第一芯片结构层电连接。
  11. 根据权利要求10所述的芯片集成结构，其特征在于，还包括第一重布线层，所述第一重布线层位于相邻两个所述第一芯片结构层之间；
    其中，所述第一重布线层包括层叠设置的第一部分和第二部分，所述第一部分与一个所述第一芯片结构层电连接，所述第二部分与另一个所述第一芯片结构层电连接；
    所述第一重布线层还包括第一键合部和第二键合部，所述第一键合部位于所述第一部分靠近所述第二部分的一侧，所述第二键合部位于所述第二部分靠近所述第一部分的一侧，所述第二部分与所述第一部分通过所述第一键合部和所述第二键合部键合。
  12. 根据权利要求11所述的芯片集成结构，其特征在于，所述第一键合部靠近所述第二部分的一端的截面面积大于靠近所述第一部分的一端的截面面积；和/或，
    所述第二键合部靠近所述第一部分的一端的截面面积大于靠近所述第二部分的一端的截面面积。
  13. 根据权利要求11所述的芯片集成结构，其特征在于，第一键合部包括层叠设置的第一连接垫和第二连接垫，所述第一连接垫相对于所述第二连接垫靠近所述第一部分，在平行于所述封装基板的方向上，所述第二连接垫的截面面积大于所述第一连接垫的截面面积；和/或，
    第二键合部包括层叠设置的第三连接垫和第四连接垫，所述第三连接垫相对于所述第四连接垫靠近所述第二部分，在平行于所述封装基板的方向上，所述第四连接垫的截面面积大于所述第三连接垫的截面面积。
  14. 根据权利要求11-13中任一项所述的芯片集成结构，其特征在于，多个层叠设置的所述第一芯片结构层中，与所述封装基板之间的距离最远的所述第一芯片结构层为顶层结构层，位于所述顶层结构层和所述封装基板之间的所述第一芯片结构层为中间结构层；
    其中，所述中间结构层包括沿所述第三方向贯穿所述第一裸片的第一导电通孔，所述顶层结构层还通过所述重布线层与所述中间结构层的所述第一导电通孔电连接。
  15. 根据权利要求1-14中任一项所述的芯片集成结构，其特征在于，还包括第二芯片结构层，所述第二芯片结构层与所述第一芯片结构层层叠设置，所述第二芯片结构层包括结构芯片、第二裸片以及位于所述结构芯片和所述第二裸片之间的隔离结构；
    其中，所述第二裸片包括第二衬底以及位于所述第二衬底上的功能层；第一芯片结构层与所述第二裸片的所述功能层之间电连接。
  16. 根据权利要求15所述的芯片集成结构，其特征在于，所述隔离结构的材质包括氧化硅、氮化硅以及氮氧化硅中一种或者多种的组合。
  17. 根据权利要求15所述的芯片集成结构，其特征在于，还包括第二重布线层，所述第二芯片结构层位于所述第一芯片结构层和所述封装基板之间，所述第二重布线层位于所述第一芯片结构层和所述第二芯片结构层之间，所述第一芯片结构层和所述第二芯片结构层之间通过所述第二重布线层电连接，所述第二芯片结构层与所述封装基板电连接。
  18. 根据权利要求17所述的芯片集成结构，其特征在于，所述第二裸片还包括贯穿所述第二衬底的第二导电通孔，所述功能层相对于所述第二衬底靠近所述封装基板，所述功能层与所述封装基板电连接；
    其中，所述第二导电通孔的一端与所述功能层电连接，所述第二导电通孔的另一端与所述第二重布线层电连接。
  19. 根据权利要求17所述的芯片集成结构，其特征在于，所述第二裸片还包括贯穿所述第二衬底的第二导电通孔，所述功能层相对于所述第二衬底远离所述封装基板，所述功能层与所述第二重布线层电连接；
    其中，所述第二导电通孔的一端与所述功能层电连接，所述第二导电通孔的另一端与所述封装基板电连接。
  20. 根据权利要求1-19中任一项所述的芯片集成结构，其特征在于，还包括第三裸片，所述第三裸片与所述第一芯片结构层层叠设置，所述第三裸片与所述封装基板电连接。
  21. 一种芯片集成结构的制备方法，其特征在于，包括：
    提供封装基板；
    提供第一芯片结构层，所述第一芯片结构层包括切割道结构和多个第一裸片；所述切割道结构连接所述多个第一裸片，且将所述多个第一裸片分隔开；
    将所述第一芯片结构层设置在所述封装基板的一侧，并使所述第一芯片结构层与所述封装基板电连接。
  22. 根据权利要求21所述的芯片集成结构的制备方法，其特征在于，所述第一芯片结构层的数量为多个；
    所述将所述第一芯片结构层设置在所述封装基板的一侧，并使所述第一芯片结构层与所述封装基板电连接，包括：
    将多个所述第一芯片结构层依次层叠设置在所述封装基板上，其中，多个所述第一芯片结构层中，最靠近所述封装基板的所述第一芯片结构层与所述封装基板电连接，且任意相邻的两个所述第一芯片结构层电连接。
  23. 根据权利要求21或22所述的芯片集成结构的制备方法，其特征在于，所述将所述第一芯片结构层设置在所述封装基板的一侧，并使所述第一芯片结构层与所述封装基板电连接之前，还包括：
    在载片上形成第二芯片结构层；
    将所述第一芯片结构层设置在所述第二芯片结构层远离所述载片的一侧，并使所述第一芯片结构层与所述第二芯片结构层电连接；
    所述将所述第一芯片结构层设置在所述封装基板的一侧，并使所述第一芯片结构层与所述封装基板电连接，包括：
    去除所述载片；
    将所述第二芯片结构层远离所述第一芯片结构层的一侧与所述封装基板电连接。
  24. 根据权利要求22所述的芯片集成结构的制备方法，其特征在于，所述在载片上形成第二芯片结构层，包括：
    从第一晶圆中挑选结构芯片，并将挑选的所述结构芯片设置在所述载片上；
    从第二晶圆中挑选第二裸片，并将挑选的所述第二裸片设置在所述载片上；
    在所述结构芯片和所述第二裸片之间形成隔离结构，所述结构芯片、所述第二裸片和所述隔离结构共同构成所述第二芯片结构层。
  25. 根据权利要求21或22所述的芯片集成结构的制备方法，其特征在于，所述将所述第一芯片结构层设置在所述封装基板的一侧，并使所述第一芯片结构层与所述封装基板电连接之前，还包括：
    在所述第一芯片结构层上形成第二芯片结构层，并使所述第一芯片结构层与所述第二芯片结构层电连接；
    所述将所述第一芯片结构层设置在所述封装基板的一侧，并使所述第一芯片结构层与所述封装基板电连接，还包括：
    将所述第二芯片结构层远离所述第一芯片结构层的一侧与所述封装基板电连接。
  26. 根据权利要求25所述的芯片集成结构的制备方法，其特征在于，所述在所述第一芯片结构层上形成第二芯片结构层，并使所述第一芯片结构层与所述第二芯片结构层电连接，包括：
    从第一晶圆中挑选结构芯片，并将挑选的所述结构芯片设置在所述第一芯片结构层上，使所述结构芯片与所述第一芯片结构层连接；
    从第二晶圆中挑选第二裸片，并将挑选的所述第二裸片设置在所述第一芯片结构层上，使所述第二裸片与所述第一芯片结构层电连接；
    在所述结构芯片和所述第二裸片之间形成隔离结构，所述结构芯片、所述第二裸片和所述隔离结构共同构成所述第二芯片结构层。
  27. 一种电子设备，其特征在于，包括印刷电路板和如权利要求1-20中任一项所述的芯片集成结构，所述芯片集成结构与所述印刷电路板电性连接。
PCT/CN2023/130829 2022-12-15 2023-11-09 芯片集成结构及其制备方法、电子设备 Ceased WO2024125174A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112490186A (zh) * 2020-11-25 2021-03-12 通富微电子股份有限公司 多芯片封装方法
US20220028834A1 (en) * 2020-07-23 2022-01-27 Samsung Electronics Co., Ltd. Semiconductor package
CN114899155A (zh) * 2022-06-08 2022-08-12 华天科技（昆山）电子有限公司 多种类多数量芯片三维堆叠集成封装结构及其制造方法
CN115440663A (zh) * 2021-07-23 2022-12-06 台湾积体电路制造股份有限公司 半导体器件结构及形成方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990053079A (ko) * 1997-12-23 1999-07-15 윤종용 인식 마크가 형성된 반도체 웨이퍼 및 그 인식 마크를 이용한 웨이퍼 절삭 방법
US8748295B2 (en) * 2009-06-15 2014-06-10 Infineon Technologies Ag Pads with different width in a scribe line region and method for manufacturing these pads
US10692837B1 (en) * 2018-07-20 2020-06-23 Xilinx, Inc. Chip package assembly with modular core dice
US10727205B2 (en) * 2018-08-15 2020-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bonding technology for stacking integrated circuits
US11728275B2 (en) * 2021-03-18 2023-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220028834A1 (en) * 2020-07-23 2022-01-27 Samsung Electronics Co., Ltd. Semiconductor package
CN112490186A (zh) * 2020-11-25 2021-03-12 通富微电子股份有限公司 多芯片封装方法
CN115440663A (zh) * 2021-07-23 2022-12-06 台湾积体电路制造股份有限公司 半导体器件结构及形成方法
CN114899155A (zh) * 2022-06-08 2022-08-12 华天科技（昆山）电子有限公司 多种类多数量芯片三维堆叠集成封装结构及其制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4625493A1

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