WO2024130634A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2024130634A1
WO2024130634A1 PCT/CN2022/141002 CN2022141002W WO2024130634A1 WO 2024130634 A1 WO2024130634 A1 WO 2024130634A1 CN 2022141002 W CN2022141002 W CN 2022141002W WO 2024130634 A1 WO2024130634 A1 WO 2024130634A1
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WIPO (PCT)
Prior art keywords
signal line
line
circuit
electrode
exemplary embodiment
Prior art date
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Ceased
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PCT/CN2022/141002
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English (en)
French (fr)
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WO2024130634A9 (zh
Inventor
肖丽
曲燕
郑皓亮
赵蛟
郭玉珍
崔晓荣
张晨阳
玄明花
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to EP22968932.8A priority Critical patent/EP4462981A4/en
Priority to JP2024569595A priority patent/JP2025539970A/ja
Priority to PCT/CN2022/141002 priority patent/WO2024130634A1/zh
Priority to CN202280005235.2A priority patent/CN118542092A/zh
Priority to US18/555,548 priority patent/US20250081610A1/en
Priority to TW112128992A priority patent/TWI887722B/zh
Priority to TW114118863A priority patent/TW202536839A/zh
Publication of WO2024130634A1 publication Critical patent/WO2024130634A1/zh
Publication of WO2024130634A9 publication Critical patent/WO2024130634A9/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device.
  • LED Semiconductor light emitting diode
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • Micro LED display/Mini LED display can achieve large-size displays through splicing, which can break through size limitations. Because LED has the advantages of self-luminescence, wide viewing angle, fast response, simple structure, small size, light weight, energy saving, high efficiency, long life, clear light, etc., it is easier to achieve high resolution (Pixels Per Inch, PPI), and it is considered to be the most competitive next-generation display technology.
  • an embodiment of the present disclosure provides a display substrate, comprising a plurality of first circuit areas and a plurality of second circuit areas alternately arranged along a second direction, the first circuit area comprising a plurality of repeating units and a plurality of blank units alternately arranged along the first direction, the first direction and the second direction intersecting; the repeating unit comprising a plurality of circuit units, the circuit units comprising a pixel driving circuit and a data signal line and a driving signal line connected to the pixel driving circuit; the second circuit area comprising at least one gate unit, the gate unit comprising at least one gate driving circuit, the gate driving circuit being connected to the driving signal line in an adjacent circuit unit, the orthographic projection of the gate driving circuit on the plane of the display substrate not overlapping with the orthographic projection of the data signal line on the plane of the display substrate.
  • At least one second circuit area has a baseline, which is a straight line that bisects the second circuit area in the second direction and extends along the first direction; the orthographic projection of at least one gate drive circuit on the baseline at least partially overlaps with the orthographic projection of at least one blank cell on the baseline.
  • At least one gate driving circuit is also connected to a clock signal line, a high voltage line and a low voltage line.
  • the clock signal line is arranged between the high voltage line and the low voltage line, and the orthographic projection of the clock signal line on the display substrate plane does not overlap with the orthographic projection of the data signal line on the display substrate plane.
  • the data signal line in the first direction, is disposed on a side of the high voltage line away from the clock signal line, or the data signal line is disposed on a side of the low voltage line away from the clock signal line.
  • in the first direction in the first direction, there is a first distance between an edge of the high voltage line close to the data signal line and an edge of the data signal line close to the high voltage line, and there is a second distance between an edge of the low voltage line close to the data signal line and an edge of the data signal line close to the low voltage line, and the second distance is greater than the first distance.
  • the first distance is greater than or equal to 25 ⁇ m
  • the second distance is greater than or equal to 25 ⁇ m
  • the clock signal line includes a first clock signal line and a second clock signal line
  • the second clock signal line is arranged on a side of the first clock signal line away from the low voltage line; there is a third distance between an edge of the first clock signal line close to the low voltage line and an edge of the low voltage line close to the first clock signal line, there is a fourth distance between an edge of the second clock signal line close to the high voltage line and an edge of the high voltage line close to the second clock signal line, and the third distance is greater than the fourth distance.
  • At least one drive signal line is connected to a gate drive circuit, and the gate drive circuit is arranged in a first center line area of the second circuit area, and the gate drive circuit is connected to the first midpoint area of the drive signal line through an output line;
  • the first center line area is an area including the first center line
  • the first midpoint area is an area including the first midpoint
  • the width of the first center line area and the first midpoint area in the first direction is 1% to 10% of the width of the display substrate
  • the first center line is a straight line that bisects the second circuit area in the first direction and extends along the second direction
  • the first midpoint is a point that bisects the drive signal line in the first direction
  • the display substrate width is the dimension of the display substrate in the first direction.
  • At least one driving signal line is respectively connected to the first gate driving circuit and the second gate driving circuit
  • the first gate driving circuit is arranged in the second midline area of the second circuit area, and is connected to the second midpoint area of the driving signal line through an output line
  • the second gate driving circuit is arranged in the third midline area of the second circuit area, and is connected to the third midpoint area of the driving signal line through an output line
  • the second midline area is an area including the second midline
  • the third midline area is an area including the third midline
  • the second midpoint area is an area including the second midpoint
  • the third midpoint area is an area including the third midpoint
  • the width of the second midline area, the third midline area, the second midpoint area and the third midpoint area in the first direction X is 1/4 of the width of the display substrate.
  • the second circuit area includes a first center line that bisects the second circuit area in the first direction and extends along the second direction, the first center line divides the second circuit area into a first area and a second area, the second center line is a straight line that bisects the first area in the first direction and extends along the second direction, and the third center line is a straight line that bisects the second area in the first direction and extends along the second direction;
  • the drive signal line includes a first midpoint that bisects the drive signal line in the first direction, the first midpoint divides the drive signal line into a first line segment and a second line segment, the second midpoint is a point that bisects the first line segment in the first direction, and the third midpoint is a point that bisects the second line segment in the first direction.
  • At least one second circuit area has a baseline, which is a straight line that bisects the second circuit area in the second direction and extends along the first direction, and the pixel driving circuits in the first circuit areas on both sides of the second circuit area in the second direction are mirror-symmetric relative to the baseline.
  • the at least one second circuit region further includes at least one first mark, and an orthographic projection of the at least one first mark on the reference line at least partially overlaps with an orthographic projection of the at least one blank cell on the reference line.
  • the at least one second circuit region further includes at least one second mark, and an orthographic projection of the at least one second mark on the reference line at least partially overlaps with an orthographic projection of the at least one blank cell on the reference line.
  • an orthographic projection of the second mark on the display substrate plane does not overlap with an orthographic projection of the data signal line, the drive signal line, and the clock signal line on the display substrate plane.
  • the display substrate on a plane perpendicular to the display substrate, includes a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer sequentially arranged on a base, the drive signal line is arranged in the second gate metal layer, and the data signal line and the clock signal line are arranged in the first source-drain metal layer.
  • the at least one second circuit region further includes at least one first mark and at least one second mark, the first mark being disposed in the first source-drain metal layer, and the second mark being disposed in the second source-drain metal layer.
  • the display substrate further includes a first flat layer and a first passivation layer, the first flat layer is arranged on a side of the first source-drain metal layer away from the substrate, the first passivation layer is arranged on a side of the first flat layer away from the substrate, and the second source-drain metal layer is arranged on a side of the first passivation layer away from the substrate; a first marking hole exposing the first mark is arranged on the first flat layer, the orthographic projection of the first marking hole on the substrate plane includes the orthographic projection of the first mark on the substrate plane, and the first passivation layer covers the first mark in the first marking hole.
  • the display substrate further includes a second passivation layer and a second flat layer, the second passivation layer is arranged on a side of the second source/drain metal layer away from the substrate, and the second flat layer is arranged on a side of the second passivation layer away from the substrate; a second marking hole and a third marking hole are arranged on the second flat layer, the second marking hole exposes the second passivation layer covering the second mark, the orthographic projection of the second marking hole on the substrate plane includes the orthographic projection of the second mark on the substrate plane, the third marking hole exposes the second passivation layer covering the first mark, and the orthographic projection of the third marking hole on the substrate plane includes the orthographic projection of the first mark on the substrate plane.
  • the present disclosure further provides a display device, comprising the display substrate as described above.
  • the present disclosure further provides a method for preparing a display substrate, comprising: the display substrate comprises a plurality of first circuit areas and a plurality of second circuit areas alternately arranged along a second direction, the first circuit area comprises a plurality of repeating units and a plurality of blank units alternately arranged along the first direction, the repeating unit comprises a plurality of circuit units, the second circuit area comprises at least one gate unit, and the first direction and the second direction intersect; the preparation method comprises:
  • a pixel driving circuit and a data signal line and a driving signal line connected to the pixel driving circuit are formed in the circuit unit, and at least one gate driving circuit and a clock signal line connected to the gate driving circuit are formed in the gate unit.
  • the gate driving circuit is connected to the driving signal line in an adjacent circuit unit, and the orthographic projection of the data signal line on the display substrate plane does not overlap with the orthographic projection of the clock signal line on the display substrate plane.
  • FIG1 is a schematic structural diagram of a display device
  • FIG2 is a schematic diagram of a planar structure of a light-emitting structure layer in a display substrate
  • FIG3 is a schematic diagram of a planar structure of a driving structure layer in a display substrate
  • FIG4 is an equivalent circuit diagram of a pixel driving circuit
  • FIG5 is a schematic structural diagram of a gate driving device
  • FIG6 is an equivalent circuit diagram of a gate drive circuit
  • FIG7 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure.
  • FIG8 is a schematic diagram of a gate drive circuit routing according to an exemplary embodiment of the present disclosure.
  • FIG9 is a schematic diagram of an arrangement of a gate unit according to an exemplary embodiment of the present disclosure.
  • FIG10 is a schematic diagram of another arrangement of gate units according to an exemplary embodiment of the present disclosure.
  • 11 and 12 are schematic diagrams of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure
  • FIG. 13 to 15 are schematic diagrams showing a substrate after forming a first conductive layer pattern according to the present disclosure
  • 16 to 18 are schematic diagrams showing a substrate after a semiconductor layer pattern is formed according to the present disclosure.
  • 19 to 21 are schematic diagrams showing a substrate after forming a second conductive layer pattern according to the present disclosure.
  • 22 to 24 are schematic diagrams showing a substrate after a third insulating layer pattern is formed in the present disclosure.
  • 25 to 28 are schematic diagrams showing a substrate after a third conductive layer pattern is formed in the present disclosure.
  • 29 to 31 are schematic diagrams showing a substrate after forming a first flat layer pattern according to the present disclosure.
  • 32 and 33 are schematic diagrams showing a substrate after a fourth conductive layer pattern is formed in the present disclosure.
  • 34 and 35 are schematic diagrams showing a substrate after forming a second flat layer pattern according to the present disclosure.
  • FIG. 36 is a schematic diagram of another gate drive circuit routing according to an exemplary embodiment of the present disclosure.
  • AT1 first active layer
  • AT2 second active layer
  • AT3 third active layer
  • AT4 fourth active layer
  • AT5 farifth active layer
  • AT6 silverth active layer
  • AT7 the seventh active layer
  • AT8 the eighth active layer
  • AT9 the ninth active layer
  • AT10 the tenth active layer
  • AT11 the eleventh active layer
  • AT21 the twenty-first active layer
  • AT22 the twenty-second active layer
  • AT23 the twenty-third active layer
  • AT24 the twenty-fourth active layer
  • AT25 the twenty-fifth active layer
  • AT26 the twenty-sixth active layer
  • AT27 the twenty-seventh active layer
  • AT28 the twenty-eighth active layer
  • CF1 the first electrode plate
  • CF2 the second electrode plate
  • CF3 third plate
  • CF4 fourth plate
  • CF5 sixth plate
  • CF6 ixth plate
  • CF7 sineth plate
  • CF8 eighth plate
  • CF9 nointh plate
  • CF11 embryoventh plate
  • CF12 twelfth plate
  • CF13 thirteenth plate
  • CF14 fourth plate
  • Cs storage capacitor
  • C1 first capacitor
  • C2 second capacitor
  • CT1 first control line
  • CT2 second control line
  • CLK first clock signal line
  • CLKB second clock signal line
  • DataI data signal line
  • DataT duration signal line
  • EM luminous signal line
  • Gate1 first gate electrode
  • Gate2 second gate electrode
  • Gate3-B third bottom gate electrode
  • Gate3-T the third top gate electrode
  • Gate4 the fourth gate electrode
  • Gate5 the fifth gate electrode
  • Gate6 the sixth gate electrode
  • Gate7 the seventh gate electrode
  • Gate8 the eighth gate electrode
  • Gate9 the ninth gate electrode
  • Gate10 the tenth gate electrode
  • Gate11 the eleventh gate electrode
  • Gate21 the twenty-first gate electrode
  • Gate22 the twenty-second gate electrode
  • Gate23 the twenty-third gate electrode
  • Gate24 the twenty-fourth gate electrode
  • Gate25 the twenty-fifth gate electrode
  • Gate26 the twenty-sixth gate electrode
  • Gate27 the 27th gate electrode
  • Gate28 the 28th gate electrode
  • Hf high-frequency signal line
  • Hf-C high frequency connecting line
  • MARK1 first mark
  • MARK2 second mark
  • S1 first scanning signal line
  • S2 second scanning signal line
  • VDD high voltage power line
  • VDD-C high voltage connection line
  • VSS low voltage power line
  • VSS-C low voltage connection line
  • Vint initial signal line
  • VGH high voltage line
  • VGL low voltage line
  • 200 display substrate
  • 210 first circuit area
  • 220 second circuit area
  • the proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values shown in the drawings.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed should be understood in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the “source electrode” and the “drain electrode” may be interchanged, and the “source terminal” and the “drain terminal” may be interchanged.
  • connection includes the case where components are connected together through an element having some kind of electrical function.
  • element having some kind of electrical function There is no particular limitation on the "element having some kind of electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • Examples of “element having some kind of electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • thickness and “height” refer to the vertical distance between the surface of the film layer away from the substrate and the surface of the film layer close to the substrate.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • FIG1 is a schematic diagram of the structure of a display device.
  • the main structure of a large-size display device may include a plurality of display substrates 200 arranged on a motherboard 100, and the plurality of display substrates 200 are closely spliced together for image display.
  • at least one display substrate 200 may include at least a driving structure layer 20 arranged on a substrate 10 and a light-emitting structure layer 30 arranged on a side of the driving structure layer 20 away from the substrate.
  • the driving structure layer 20 may include a plurality of circuit units, at least one circuit unit may include a pixel driving circuit and a plurality of signal lines connected to the pixel driving circuit, and the pixel driving circuit is configured to receive a data voltage under the control of the signal line and output a corresponding current.
  • the light-emitting structure layer 30 may include a plurality of light-emitting units, at least one light-emitting unit may include a light-emitting diode 40, the light-emitting diodes 40 in the plurality of light-emitting units are correspondingly connected to the pixel driving circuits in the plurality of circuit units, and the light-emitting diodes 40 are configured to emit light of corresponding brightness under the drive of the output current of the corresponding pixel driving circuit.
  • the circuit unit mentioned in the present disclosure refers to an area divided according to a pixel driving circuit
  • the light-emitting unit mentioned in the present disclosure refers to an area divided according to a light-emitting diode.
  • the positions of the light-emitting unit and the circuit unit may correspond, or the positions of the light-emitting unit and the circuit unit may not correspond, and the present disclosure does not limit this.
  • FIG2 is a schematic diagram of a planar structure of a light emitting structure layer in a display substrate.
  • the light emitting structure layer may include a first light emitting unit P1 emitting a first color light, a second light emitting unit P2 emitting a second color light, and a third light emitting unit P3 emitting a third color light.
  • the first light emitting unit P1 may be a red light emitting unit emitting red light to form a red (R) sub-pixel
  • the second light emitting unit P2 may be a green light emitting unit emitting green light to form a green (G) sub-pixel
  • the third light emitting unit P3 may be a blue light emitting unit emitting blue light to form a blue (B) sub-pixel.
  • a red sub-pixel, a blue sub-pixel, and a green sub-pixel may form a pixel unit P.
  • the shape of the sub-pixel may be rectangular, rhombus, pentagonal, or hexagonal, and the three sub-pixels in a pixel unit P may be arranged in a horizontal parallel, vertical parallel, or in a triangular pattern, which is not limited in the present disclosure.
  • a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, a square arrangement, a diamond arrangement, or the like.
  • the light emitting diode 40 may be a sub-millimeter light emitting diode Mini LED or a micro light emitting diode Micro LED.
  • FIG3 is a schematic diagram of a planar structure of a driving structure layer in a display substrate, illustrating a structure in which a gate driving circuit is arranged in a display area (Gate Driver In AA, GIA for short).
  • the driving structure layer may include at least a first circuit area 210 and a second circuit area 220, the second circuit area 220 may be in the shape of a strip extending along a second direction Y, the second circuit area 220 may be arranged on one side of the first direction X of the first circuit area 210 or on the side opposite to the first direction X, and the first direction X and the second direction Y intersect.
  • the first circuit area 210 may include a plurality of circuit units Q forming a plurality of unit rows and a plurality of unit columns, the unit row may include a plurality of circuit units Q sequentially arranged along the first direction X, and the unit column may include a plurality of circuit units Q sequentially arranged along the second direction Y.
  • At least one circuit unit Q may include at least a pixel driving circuit, a plurality of pixel driving circuits in a unit row are connected to a driving signal line in the unit row, and the pixel driving circuit is configured to receive a data voltage under the control of the driving signal line and output a corresponding current to a connected light emitting diode.
  • the second circuit area 220 may include at least a gate driving device, which may include at least a plurality of gate units G arranged in sequence and cascaded along the second direction Y, at least one gate unit G may include at least one gate driving circuit, the gate driving circuit is connected to the driving signal line in the corresponding unit row, and the gate driving circuit is configured to output a row driving signal to the driving signal line in the corresponding unit row.
  • a gate driving device which may include at least a plurality of gate units G arranged in sequence and cascaded along the second direction Y
  • at least one gate unit G may include at least one gate driving circuit
  • the gate driving circuit is connected to the driving signal line in the corresponding unit row
  • the gate driving circuit is configured to output a row driving signal to the driving signal line in the corresponding unit row.
  • the driving signal line may include at least a scanning signal line and a light-emitting signal line
  • the gate unit G may include at least a first gate driving circuit (GOA circuit) and a second gate driving circuit (EOA circuit)
  • the first gate driving circuit may be connected to the scanning signal line
  • the second gate driving circuit may be connected to the light-emitting signal line.
  • FIG4 is an equivalent circuit diagram of a pixel driving circuit, illustrating a 11T3C pixel driving circuit structure.
  • multiple light-emitting diodes in a display substrate may be driven by current mode. Since current-mode light-emitting diodes may have problems of color coordinate drift and low external quantum efficiency when driven at a lower current density, resulting in poor brightness uniformity, it is difficult to accurately represent low grayscale by only controlling the amplitude of the current.
  • the pixel driving circuit includes at least two types of data terminals: a current data terminal and a duration data terminal.
  • the current data terminal is configured to provide current signals of different amplitudes to the light-emitting diodes
  • the duration data terminal is configured to provide the light-emitting diodes with the time length of the above current signal.
  • the pixel driving circuit may include at least a current control subcircuit DK and a duration control subcircuit SK.
  • the current control subcircuit DK may include at least a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cs
  • the duration control subcircuit SK may include at least an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a first capacitor C1 and a second capacitor C2.
  • the pixel driving circuit may include at least a first node N1, a second node N2, a third node N3, a fourth node N4, a fifth node N5, a sixth node N6, and a seventh node N7.
  • the first node N1 is connected to the gate electrode of the sixth transistor T6, the second electrode of the ninth transistor T9 and the second electrode of the eleventh transistor T11, respectively;
  • the second node N2 is connected to the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7 and the anode of the light emitting diode EL, respectively;
  • the third node N3 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3 and the first end of the storage capacitor Cs, respectively;
  • the fourth node N4 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6, respectively;
  • the fifth node N5 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4 and the second electrode of the fifth transistor T5, respectively;
  • the sixth node N6 is connected to the second electrode of the eighth transistor T8, the gate electrode of the ninth transistor T9 and the first end
  • a gate electrode of the first transistor T1 is connected to the second scan signal line S2 , a first electrode of the first transistor T1 is connected to the initial signal line Vint, and a second electrode of the first transistor T1 is connected to the third node N3 .
  • a gate electrode of the second transistor T2 is connected to the first scan signal line S1 , a first electrode of the second transistor T2 is connected to the third node N3 , and a second electrode of the second transistor T2 is connected to the fourth node N4 .
  • a gate electrode of the third transistor T3 is connected to the third node N3
  • a first electrode of the third transistor T3 is connected to the fifth node N5
  • a second electrode of the third transistor T3 is connected to the fourth node N4 .
  • a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1
  • a first electrode of the fourth transistor T4 is connected to the data signal line Data1
  • a second electrode of the fourth transistor T4 is connected to the fifth node N5.
  • a gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the fifth node N5.
  • a gate electrode of the sixth transistor T6 is connected to the first node N1 , a first electrode of the sixth transistor T6 is connected to the fourth node N4 , and a second electrode of the sixth transistor T6 is connected to the second node N2 .
  • a gate electrode of the seventh transistor T7 is connected to the second scan signal line S2 , a first electrode of the seventh transistor T7 is connected to the initial signal line Vint, and a second electrode of the seventh transistor T7 is connected to the second node N2 .
  • a gate electrode of the eighth transistor T8 is connected to the first control line CT1 , a first electrode of the eighth transistor T8 is connected to the duration signal line DataT, and a second electrode of the eighth transistor T8 is connected to the sixth node N6 .
  • a gate electrode of the ninth transistor T9 is connected to the sixth node N6, a first electrode of the ninth transistor T9 is connected to the light emitting signal line EM, and a second electrode of the ninth transistor T9 is connected to the first node N1.
  • a gate electrode of the tenth transistor T10 is connected to the second control line CT2 , a first electrode of the tenth transistor T10 is connected to the duration signal line DataT, and a second electrode of the tenth transistor T10 is connected to the seventh node N7 .
  • a gate electrode of the eleventh transistor T11 is connected to the seventh node N7 , a first electrode of the eleventh transistor T11 is connected to the high-frequency signal line Hf, and a second electrode of the eleventh transistor T11 is connected to the first node N1 .
  • a first end of the storage capacitor Cs is connected to the third node N3 , and a second end of the storage capacitor Cs is connected to the first power line VDD.
  • a first end of the first capacitor C1 is connected to the sixth node N6 , and a second end of the first capacitor C1 is connected to the initial signal line Vint.
  • a first end of the second capacitor C2 is connected to the seventh node N7, and a second end of the second capacitor C2 is connected to the initial signal line Vint.
  • the first transistor T1 , the second transistor T2 , and the fourth to eleventh transistors T4 to T11 may be switching transistors, and the third transistor T3 may be a driving transistor.
  • the light emitting diode EL may be a Mini LED or a Micro LED.
  • a first electrode of the light emitting diode EL is connected to a second node N2, and a second electrode of the light emitting diode EL is connected to a second power line VSS, and a signal of the second power line VSS is a continuously provided low-level signal, such as a DC low voltage.
  • a signal of the first power line VDD is a continuously provided high-level signal, such as a DC high voltage.
  • the first transistor T1 to the eleventh transistor T11 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the eleventh transistor T11 may include a P-type transistor and an N-type transistor.
  • the first transistor T1 to the eleventh transistor T11 may be a low-temperature polysilicon transistor, or an oxide transistor, or a low-temperature polysilicon transistor and a metal oxide transistor.
  • the active layer of the low-temperature polysilicon transistor is low-temperature polysilicon (LTPS), and the active layer of the metal oxide transistor is metal oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • Oxide metal oxide semiconductor
  • Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, and oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and metal oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.
  • the operation process of the pixel driving circuit may include:
  • the operation process of the pixel driving circuit may include an initialization phase, a writing phase and a light-emitting phase, and the initialization phase may include a first sub-phase and a second sub-phase.
  • the signals of the first scanning signal line S1 and the light-emitting signal line EM are high-level signals
  • the signal of the second scanning signal line S2 is a low-level signal
  • the first transistor T1 and the seventh transistor T7 are turned on.
  • the first transistor T1 is turned on so that the signal of the initial signal line Vint is written into the third node N3, the storage capacitor Cs is initialized (reset), and the original charge in the storage capacitor Cs is cleared. Since the first end of the storage capacitor C is at a low level, the third transistor T3 is turned on.
  • the seventh transistor T7 is turned on so that the signal of the initial signal line Vint is written into the second node N2, the first pole of the light-emitting diode EL is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed to ensure that the light-emitting diode EL does not emit light.
  • the signal of the time length signal line DataT is a high level signal
  • the signal of the second control line CT2 is a low level signal
  • the tenth transistor T10 is turned on, so that the signal of the time length signal line DataT is written into the seventh node N7, and the second capacitor C2 is charged. Since the signal of the time length signal line DataT is a high level signal at this time, the eleventh transistor T11 is turned off, and the signal of the high-frequency signal line Hf cannot be written into the first node N1.
  • the signal of the duration signal line DataT is a low level signal
  • the signal of the first control line CT1 is a low level signal
  • the eighth transistor T8 is turned on, so that the signal of the duration signal line DataT is written into the sixth node N6, and the first capacitor C1 is charged. Since the signal of the duration signal line DataT is a low level signal at this time, the ninth transistor T9 is turned on, and the signal of the light emitting signal line EM is written into the first node N1.
  • the data signal line DataI outputs a data voltage
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals
  • the signal of the first scanning signal line S1 is a low-level signal
  • the second transistor T2 and the fourth transistor T4 are turned on.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line DataI is provided to the third node N3 through the fifth node N5, the turned-on third transistor T3, the fourth node N4, and the turned-on second transistor T2, and the difference between the data voltage Vd output by the data signal line DataI and the threshold voltage Vth of the third transistor T3 is charged into the storage capacitor Cs, and the voltage of the first end (third node N3) of the storage capacitor Cs is Vd-
  • the first capacitor C1 keeps the potential of the signal of the sixth node N6 unchanged, the ninth transistor T9 remains turned on, and the signal of the light-emitting signal line EM is written into the first node N1.
  • the signal of the light-emitting signal line EM is a low-level signal
  • the fifth transistor T5 is turned on
  • the first capacitor C1 maintains the potential of the signal of the sixth node N6
  • the ninth transistor T9 remains turned on
  • the signal of the light-emitting signal line EM is written into the first node N1, and the sixth transistor T6 is turned on.
  • the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting diode EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light-emitting diode EL to emit light.
  • the operation process of the pixel driving circuit includes: an initialization phase, a writing phase and a light-emitting phase, and the initialization phase may include a first sub-phase and a second sub-phase.
  • the signals of the first scanning signal line S1 and the light-emitting signal line EM are high-level signals
  • the signal of the second scanning signal line S2 is a low-level signal
  • the first transistor T1 and the seventh transistor T7 are turned on.
  • the first transistor T1 is turned on so that the signal of the initial signal line Vint is written into the third node N3, the storage capacitor Cs is initialized (reset), and the original charge in the storage capacitor Cs is cleared. Since the first end of the storage capacitor C is at a low level, the third transistor T3 is turned on.
  • the seventh transistor T7 is turned on so that the signal of the initial signal line Vint is written into the second node N2, the first pole of the light-emitting diode EL is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed to ensure that the light-emitting diode EL does not emit light.
  • the signal of the time length signal line DataT is a low level signal
  • the signal of the second control line CT2 is a low level signal
  • the tenth transistor T10 is turned on, so that the signal of the time length signal line DataT is written into the seventh node N7, and the second capacitor C2 is charged. Since the signal of the time length signal line DataT is a low level signal at this time, the eleventh transistor T11 is turned on, and the signal of the high frequency signal line Hf is written into the first node N1.
  • the signal of the duration signal line DataT is a high level signal
  • the signal of the first control line CT1 is a low level signal
  • the eighth transistor T8 is turned on, so that the signal of the duration signal line DataT is written into the sixth node N6, and the first capacitor C1 is charged. Since the signal of the duration signal line DataT is a high level signal at this time, the ninth transistor T9 is turned off, and the signal of the light emitting signal line EM cannot be written into the first node N1.
  • the data signal line DataI outputs a data voltage
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals
  • the signal of the first scanning signal line S1 is a low-level signal
  • the second transistor T2 and the fourth transistor T4 are turned on.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line DataI is provided to the third node N3 through the fifth node N5, the turned-on third transistor T3, the fourth node N4, and the turned-on second transistor T2, and the difference between the data voltage Vd output by the data signal line DataI and the threshold voltage Vth of the third transistor T3 is charged into the storage capacitor Cs, and the voltage of the first end (third node N3) of the storage capacitor Cs is Vd-
  • the second capacitor C2 keeps the signal potential of the seventh node N7 unchanged, the eleventh transistor T11 is always turned on, and the signal of the high-frequency signal line Hf is written into the first node N1.
  • the signal of the light-emitting signal line EM is a low-level signal
  • the fifth transistor T5 is turned on
  • the second capacitor C2 keeps the signal potential of the seventh node N7 unchanged
  • the eleventh transistor T11 is always turned on
  • the signal of the high-frequency signal line Hf is written into the first node N1
  • the sixth transistor T6 is turned on.
  • the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting diode EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light-emitting diode EL to emit light.
  • the driving current output by the third transistor T3 in the pixel driving circuit is not affected by the threshold voltage of the third transistor T3, but is only related to the voltage of the data signal line and the voltage of the first power line, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect.
  • a control signal is provided to the first node N1 through the light-emitting signal line, so that the grayscale of the light-emitting diode is controlled by the driving current.
  • a control signal is provided to the first node N1 through the high-frequency signal line, so that the grayscale of the light-emitting diode is controlled by the driving current and the light-emitting duration.
  • the signal of the high-frequency signal line Hf is a pulse signal, and within an image frame, the signal of the high-frequency signal line Hf has multiple pulses.
  • the frequency of the signal of the high-frequency signal line Hf may be greater than the frequency of the signal of the light-emitting signal line EM.
  • the frequency of the signal of the high-frequency signal line Hf may be between 3000Hz and 60000Hz, and the frequency of the light-emitting signal line EM may be between 60Hz and 120Hz.
  • the present disclosure controls the light-emitting duration through the high-frequency pulse signal of the high-frequency signal line, disperses the short light-emitting duration into one frame time, reduces the flicker that occurs when the grayscale displayed by the light-emitting diode connected to the pixel driving circuit is less than the threshold grayscale, and improves the display effect of the display product.
  • FIG5 is a schematic diagram of the structure of a gate driving device.
  • the gate driving device may include at least a plurality of cascaded GOA circuits (first gate driving circuits).
  • the plurality of GOA circuits may include a first-stage GOA circuit, a second-stage GOA circuit, a third-stage GOA circuit, ... an i-th-stage GOA circuit, ...
  • the first-stage GOA circuit may generate a scanning signal G(1) for the pixel driving circuit in the first unit row according to an initial signal provided by an initial signal line STV, a clock signal provided by a first clock signal line CLK and a second clock signal line CLKB, etc.
  • the i-th-stage GOA circuit may generate a scanning signal G(i) provided to the pixel driving circuit in the i-th unit row according to a scanning signal G(i-1) generated by an i-1-th-stage GOA circuit, a scanning signal G(i+1) generated by an i+1-th-stage GOA circuit, a clock signal provided by a first clock signal line CLK and a second clock signal line CLKB, etc., wherein i is a positive integer greater than 1.
  • FIG6 is an equivalent circuit diagram of a gate drive circuit, illustrating an 8T2C GOA circuit structure.
  • the gate drive circuit may include 8 transistors (the 21st transistor T21 to the 28th transistor T28) and 2 capacitors (the third capacitor C3 and the fourth capacitor C4), and the gate drive circuit is respectively connected to 6 signal lines (the first clock signal line CLK, the second clock signal line CLKB, the high voltage line VGH, the low voltage line VGL, the previous level signal output line G(n-1) and the current level signal output line G(n)).
  • the gate driving circuit may include at least an eleventh node N11, a twelfth node N12, a thirteenth node N13, and a fourteenth node N14.
  • the eleventh node N11 is connected to the second electrode of the twenty-first transistor T21, the gate electrode of the twenty-second transistor T22, the second electrode of the twenty-seventh transistor T27, and the first electrode of the twenty-eighth transistor T28, respectively.
  • the twelfth node N12 is connected to the second electrode of the twenty-third transistor T23, the second electrode of the twenty-second transistor T22, the gate electrode of the twenty-fourth transistor T24, the gate electrode of the twenty-sixth transistor T26, and the first end of the fourth capacitor C4, respectively.
  • the thirteenth node N13 is connected to the second electrode of the twenty-sixth transistor T26 and the first electrode of the twenty-seventh transistor T27, respectively.
  • the fourteenth node N14 is connected to the gate electrode of the twenty-fifth transistor T25, the second electrode of the twenty-eighth transistor T28, and the first end of the third capacitor C3, respectively.
  • a gate electrode of the 21st transistor T21 is connected to the first clock signal line CLK, a first electrode of the 21st transistor T21 is connected to the previous stage signal output line G(n-1), and a second electrode of the 21st transistor T21 is connected to the 11th node N11.
  • a gate electrode of the 22nd transistor T22 is connected to the eleventh node N11 , a first electrode of the 22nd transistor T22 is connected to the first clock signal line CLK, and a second electrode of the 22nd transistor T22 is connected to the twelfth node N12 .
  • a gate electrode of the twenty-third transistor T23 is connected to the first clock signal line CLK, a first electrode of the twenty-third transistor T23 is connected to the low voltage line VGL, and a second electrode of the twenty-third transistor T23 is connected to the twelfth node N12.
  • a gate electrode of the 24th transistor T24 is connected to the twelfth node N12, a first electrode of the 24th transistor T24 is connected to the high voltage line VGH, and a second electrode of the 24th transistor T24 is connected to the current stage signal output line G(n).
  • a gate electrode of the twenty-fifth transistor T25 is connected to the fourteenth node N14, a first electrode of the twenty-fifth transistor T25 is connected to the second clock signal line CLKB, and a second electrode of the twenty-fifth transistor T25 is connected to the current stage signal output line G(n).
  • a gate electrode of the twenty-sixth transistor T26 is connected to the twelfth node N12 , a first electrode of the twenty-sixth transistor T26 is connected to the high voltage line VGH, and a second electrode of the twenty-sixth transistor T26 is connected to the thirteenth node N13 .
  • a gate electrode of the twenty-seventh transistor T27 is connected to the second clock signal line CLKB, a first electrode of the twenty-seventh transistor T27 is connected to the thirteenth node N13, and a second electrode of the twenty-seventh transistor T27 is connected to the eleventh node N11.
  • a gate electrode of the 28th transistor T28 is connected to the low voltage line VGL, a first electrode of the 28th transistor T28 is connected to the 11th node N11, and a second electrode of the 28th transistor T28 is connected to the 14th node N14.
  • a first end of the third capacitor C3 is connected to the fourteenth node N14, and a second end of the third capacitor C3 is connected to the current-stage signal output line G(n).
  • a first end of the fourth capacitor C4 is connected to the twelfth node N12, and a second end of the fourth capacitor C4 is connected to the high voltage line VGH.
  • the level of the first clock signal line CLK when the level of the first clock signal line CLK is a valid level, the level of the second clock signal line CLKB is an invalid level, and when the level of the second clock signal line CLKB is a valid level, the level of the first clock signal line CLK is an invalid level, the high voltage line VGH continuously provides a high level signal, and the low voltage line VGL continuously provides a low level signal.
  • a pulse duration of the first clock signal line CLK active level signal and a pulse duration of the second clock signal line CLKB active level signal may be substantially equal.
  • the twenty-first transistor T21 to the twenty-eighth transistor T28 may all be N-type thin film transistors, or may all be P-type thin film transistors, which can unify the process flow, reduce the process steps, and help improve the yield of the product.
  • the twenty-first transistor T21 to the twenty-eighth transistor T28 may be low-temperature polycrystalline silicon thin film transistors, and the thin film transistors may adopt a bottom gate structure or a top gate structure.
  • the display substrate includes a plurality of first circuit areas and a plurality of second circuit areas alternately arranged along a second direction
  • the first circuit area includes a plurality of repeating units and a plurality of blank units alternately arranged along a first direction, and the first direction and the second direction intersect
  • the repeating unit includes a plurality of circuit units, the circuit unit includes a pixel driving circuit and a data signal line and a driving signal line connected to the pixel driving circuit
  • the second circuit area includes at least one gate unit, the gate unit includes at least one gate driving circuit, the gate driving circuit is connected to the driving signal line in the adjacent circuit unit, and the orthographic projection of the gate driving circuit on the display substrate plane does not overlap with the orthographic projection of the data signal line on the display substrate plane.
  • At least one second circuit area has a baseline, which is a straight line that bisects the second circuit area in the second direction and extends along the first direction; the orthographic projection of at least one gate drive circuit on the baseline at least partially overlaps with the orthographic projection of at least one blank cell on the baseline.
  • At least one gate driving circuit is also connected to a clock signal line, a high voltage line and a low voltage line.
  • the clock signal line is arranged between the high voltage line and the low voltage line, and the orthographic projection of the clock signal line on the display substrate plane does not overlap with the orthographic projection of the data signal line on the display substrate plane.
  • the data signal line in the first direction, is disposed on a side of the high voltage line away from the low voltage line, or the data signal line is disposed on a side of the low voltage line away from the high voltage line.
  • the at least one second circuit region further includes at least one first mark, and a location of the at least one first mark in the second circuit region corresponds to a location of the at least one blank cell in the first circuit region.
  • the at least one second circuit region further includes at least one second mark, and a setting position of the at least one second mark in the second circuit region corresponds to a setting position of the at least one blank cell in the first circuit region.
  • the display substrate on a plane perpendicular to the display substrate, includes a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer sequentially arranged on a base, the drive signal line is arranged in the second gate metal layer, and the data signal line and the clock signal line are arranged in the first source-drain metal layer.
  • the at least one second circuit region further includes at least one first mark and at least one second mark, the first mark being disposed in the first source-drain metal layer, and the second mark being disposed in the second source-drain metal layer.
  • FIG7 is a schematic diagram of a planar structure of a display substrate of an exemplary embodiment of the present disclosure, illustrating the planar structure of a driving structure layer in the display substrate.
  • the display substrate 200 may include at least a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate.
  • the driving structure layer may include at least a plurality of first circuit areas 210 and a plurality of second circuit areas 220.
  • each of the first circuit area 210 and the second circuit area 220 may be in the shape of a strip extending along a first direction X, and a plurality of first circuit areas 210 and a plurality of second circuit areas 220 may be alternately arranged along a second direction Y.
  • the first circuit area may be referred to as a pixel circuit area
  • the second circuit area may be referred to as a gate circuit area.
  • the first circuit area 210 may include a plurality of repeating units RU and a plurality of blank units KB, and the plurality of repeating units RU and the plurality of blank units KB may be alternately arranged along the first direction X.
  • At least one repeating unit RU may include m1*m2 circuit units Q, m1 may be the number of unit rows included in the repeating unit RU, m2 may be the number of unit columns included in the repeating unit RU, and m1 and m2 may be positive integers greater than or equal to 2.
  • the repeating unit RU may include 2 unit rows and 3 unit columns, and the repeating unit RU forms a 2*3 circuit unit array.
  • the repeating unit RU may include 2 unit rows and 6 unit columns, and the repeating unit RU forms a 2*6 circuit unit array.
  • the repeating unit RU may be an area where a pixel driving circuit is provided
  • the blank unit KB may be an area where no pixel driving circuit is provided.
  • part of the blank unit KB may be used as a routing area of a gate driving device to reduce interference between signal lines.
  • Part of the blank unit KB may be used as a light-transmitting area of a display substrate so that external light can pass through the display substrate to form a transparent display.
  • the width of the blank unit KB may be greater than the width between adjacent circuit units Q in the first direction X within the repeating unit RU, and the width may be the dimension in the first direction X.
  • At least one circuit unit Q may include at least a pixel driving circuit, a driving signal line extending along a first direction X, and a data signal line extending along a second direction Y, the pixel driving circuit is connected to the driving signal line and the data signal line, respectively, and the pixel driving circuit is configured to receive a data voltage of the data signal line under the control of the driving signal line, and output a corresponding current to the connected light-emitting diode.
  • the light-emitting structure layer may include a plurality of light-emitting units, the light-emitting unit may include at least a light-emitting diode, and the light-emitting diodes in the plurality of light-emitting units are correspondingly connected to the pixel driving circuits in the plurality of circuit units, so that the light-emitting diodes emit light of corresponding brightness under the drive of the output current of the corresponding pixel driving circuit.
  • the second circuit area 220 may include at least one gate unit G, and the at least one gate unit G may include a gate driving circuit, which is connected to the driving signal line in the adjacent first circuit area 210, and the gate driving circuit is configured to output a row driving signal to the connected driving signal line.
  • At least one second circuit area 220 may have a reference line O1, which may be a straight line bisecting the second circuit area 220 in the second direction Y and extending along the first direction X.
  • the arrangement position of at least one gate driving circuit in the second circuit area 220 may substantially correspond to the arrangement position of at least one blank cell KB in the first circuit area 210, and the orthographic projection of the at least one gate driving circuit on the reference line O1 at least partially overlaps with the orthographic projection of the at least one blank cell KB on the reference line O1.
  • At least one second circuit area 220 may further include at least one first mark MARK1, and the first mark MARK1 may be located at one side edge or both side edges of the second circuit area 220 in the first direction X.
  • the first mark MARK1 is configured as a splicing mark, and positioning is performed by the first mark MARK1 when splicing display substrates.
  • the shape of the first mark MARK1 can be a cross
  • the setting position of at least one first mark MARK1 in the second circuit area 220 can basically correspond to the setting position of at least one blank cell KB in the first circuit area 210
  • the positive projection of at least one first mark MARK1 on the reference line O1 at least partially overlaps with the positive projection of at least one blank cell KB on the reference line O1.
  • At least one second circuit area 220 may further include at least one second mark MARK2, and the second mark MARK2 may be located at one side edge or both side edges of the second circuit area 220 in the first direction X, and located at a side of the first mark MARK1 close to the gate unit G.
  • the second mark MARK2 is configured as a binding mark, and positioning is performed by the second mark MARK2 when performing light emitting diode binding connection.
  • the shape of the second mark MARK2 can be circular
  • the setting position of at least one second mark MARK2 in the second circuit area 220 can basically correspond to the setting position of at least one blank cell KB in the first circuit area 210
  • the positive projection of at least one second mark MARK2 on the reference line O1 at least partially overlaps with the positive projection of at least one blank cell KB on the reference line O1.
  • FIG8 is a schematic diagram of a gate drive circuit routing of an exemplary embodiment of the present disclosure.
  • the pixel drive circuit in the circuit unit Q is connected to a drive signal line HL and a data signal line DataI.
  • the shape of the drive signal line HL can be a line shape extending along the first direction X, and the drive signal line HL is configured to be connected to a plurality of pixel drive circuits in a unit row.
  • the shape of the data signal line DataI can be a line shape extending along the second direction Y, and the data signal line DataI is configured to be connected to a plurality of pixel drive circuits in a unit column.
  • the gate drive circuit in the gate unit G is connected to a first clock signal line CLK, a second clock signal line CLKB, a high voltage line VGH, and a low voltage line VGL, and the gate drive circuit is connected to the drive signal line HL in an adjacent unit row through an output line OUT.
  • the first clock signal line CLK, the second clock signal line CLKB, the high voltage line VGH and the low voltage line VGL may be in the shape of lines extending along the second direction Y, and are sequentially arranged along the first direction X.
  • the first clock signal line CLK, the second clock signal line CLKB, the high voltage line VGH and the low voltage line VGL are configured to provide the first clock signal, the second clock signal, the high voltage signal and the low voltage signal to the connected gate driving circuit, respectively.
  • the first clock signal line CLK and the second clock signal line CLKB constitute the clock signal lines of the present disclosure.
  • the orthographic projection of the gate driving circuit in the gate unit G on the display substrate plane does not overlap with the orthographic projection of the data signal line DataI on the display substrate plane
  • the gate driving circuit may include twenty-first to twenty-eighth transistors, a third capacitor and a fourth capacitor.
  • the orthographic projection of the first clock signal line CLK on the display substrate plane does not overlap with the orthographic projection of the data signal line DataI on the display substrate plane
  • the orthographic projection of the second clock signal line CLKB on the display substrate plane does not overlap with the orthographic projection of the data signal line DataI on the display substrate plane.
  • the first clock signal line CLK may be substantially parallel to the data signal line DataI
  • the second clock signal line CLKB may be substantially parallel to the data signal line DataI
  • the orthographic projection of the first clock signal line CLK on the display substrate plane may be substantially parallel to the orthographic projection of the data signal line DataI on the display substrate plane
  • the orthographic projection of the second clock signal line CLKB on the display substrate plane may be substantially parallel to the orthographic projection of the data signal line DataI on the display substrate plane.
  • the repeating units RU of the plurality of first circuit areas 210 may form a repeating unit column extending along the second direction Y
  • the blank cells KB of the plurality of first circuit areas 210 may form a blank column extending along the second direction Y
  • the data signal line DataI may be disposed in the region where the repeating unit column is located
  • the first clock signal line CLK and the second clock signal line CLKB may be disposed in the region where the blank column is located, so that there is no overlap between the data signal line DataI and the first clock signal line CLK and the second clock signal line CLKB.
  • the first clock signal line CLK and the second clock signal line CLKB can be arranged between the high voltage line VGH and the low voltage line VGL, so that the data signal line DataI is located on the side of the high voltage line VGH away from the first clock signal line CLK, and the data signal line DataI is located on the side of the low voltage line VGL away from the second clock signal line CLKB, and the high voltage line VGH and the low voltage line VGL that transmit the constant voltage signal can play a shielding role, effectively reducing the coupling capacitance between the clock signal line and the data signal line.
  • an edge of the high voltage line VGH close to the data signal line DataI has a first distance L1 from an edge of the data signal line DataI close to the high voltage line VGH, and an edge of the low voltage line VGL close to the data signal line DataI has a second distance L2 from an edge of the data signal line DataI close to the low voltage line VGL.
  • the second distance L2 may be greater than the first distance L1, and the first distance L1 and the second distance L2 may be dimensions in the first direction X.
  • the first distance L1 may be greater than or equal to 25 ⁇ m
  • the second distance L2 may be greater than or equal to 25 ⁇ m.
  • the second clock signal line CLKB may be disposed on a side of the first clock signal line CLK away from the low voltage line VGL, that is, the low voltage line VGL, the first clock signal line CLK, the second clock signal line CLKB, and the high voltage line VGH may be sequentially disposed along the first direction X.
  • a third distance L3 is provided between an edge of the first clock signal line CLK close to the low voltage line VGL and an edge of the low voltage line VGL close to the first clock signal line CLK, a fourth distance L4 is provided between an edge of the second clock signal line CLKB close to the high voltage line VGH and an edge of the high voltage line VGH close to the second clock signal line CLKB, the third distance L3 may be greater than the fourth distance L4, and the third distance L3 and the fourth distance L4 may be dimensions in the first direction X.
  • adjacent data signal lines DataI may have a first width D1
  • at least one blank unit KB may have a second width D2
  • the second width D2 may be greater than the first width D1
  • the first width D1 and the second width D2 may be dimensions in the first direction X.
  • a third width D3 may be provided between the first clock signal line CLK and the second clock signal line CLKB, the first width D1 may be greater than the third width D3, and the third width D3 may be a dimension in the first direction X.
  • FIG9 is a schematic diagram of the arrangement of a gate unit in an exemplary embodiment of the present disclosure.
  • each gate circuit area may include a gate unit G, that is, a gate driving circuit in a gate unit G is connected to a driving signal line HL in a unit row through an output line OUT, and the gate unit G may be arranged in a middle position area of the display substrate.
  • the gate driving circuit in one gate unit G is connected to the driving signal line HL in one unit row through the output line OUT, which means that for the driving signal line in one unit row including a scanning signal line and a light-emitting signal line, one gate unit G includes a GOA circuit and an EOA circuit, the scanning signal line in one unit row is connected to a GOA circuit through a scanning output line, and the light-emitting signal line in one unit row is connected to an EOA circuit through a light-emitting output line.
  • At least one gate driving circuit may be disposed in a first centerline region of the second circuit region 220, and the gate driving circuit is connected to a first midpoint region of the driving signal line HL through an output line OUT.
  • the second circuit region 220 may have a first centerline
  • the driving signal line HL may have a first midpoint
  • the first centerline may be a straight line bisecting the second circuit region 220 in the first direction X and extending along the second direction Y
  • the first midpoint may be a point bisecting the driving signal line HL in the first direction X.
  • the first centerline region may be a region including the first centerline, and the width of the first centerline region in the first direction X may be approximately 1% to 10% of the width of the display substrate, the first midpoint region may be a region including the first midpoint, and the width of the first centerline region in the first direction X may be approximately 1% to 10% of the width of the display substrate, and the display substrate width may be the size of the display substrate in the first direction X.
  • the gate unit G when the gate unit G is set on one side of the display substrate (such as the left side), the row drive signal is transmitted from the left side of the display substrate (the beginning of the drive signal line) to the right side of the display substrate (the end of the drive signal line), and the transmission distance of the row drive signal is L, then the RC delay at the end of the drive signal line is the RC delay of the total length of the drive signal line.
  • the present disclosure sets the gate unit G in the middle area of the display substrate, and the row drive signal is transmitted from the middle position of the display substrate (the beginning of the drive signal line) to both sides of the display substrate (the end of the drive signal line), and the transmission distance of the row drive signal is L/2.
  • the RC delay at the end of the drive signal line of the present disclosure can be reduced by half, thereby effectively reducing the RC delay and increasing the charging time.
  • the routing pads and anti-static circuits on both sides of the display substrate can be avoided, effectively avoiding mutual interference between the anti-static circuits of the gate drive circuit.
  • each gate circuit area may include two gate units G, that is, the gate driving circuits in the two gate units G are respectively connected to the driving signal line HL in one unit row through the output line OUT, and the two gate units G may be respectively arranged in the 1/4 position area and the 3/4 position area of the display substrate.
  • the gate driving circuits in two gate units G are connected to the driving signal lines in one unit row, which means that one gate unit G includes a first gate driving circuit, the other gate unit G includes a second gate driving circuit, and the driving signal lines in one unit row are respectively connected to the first gate driving circuit and the second gate driving circuit through output lines.
  • the first gate driving circuit may be disposed in the second midline area of the second circuit area 220, the first gate driving circuit is connected to the second midpoint area of the driving signal line HL through an output line, the second gate driving circuit may be disposed in the third midline area of the second circuit area 220, the second gate driving circuit is connected to the third midpoint area of the driving signal line HL through an output line.
  • the second circuit area 220 may have a first midline that bisects the second circuit area 220 in the first direction X and extends along the second direction Y, the first midline divides the second circuit area 220 into a first region and a second region, the second midline may be a straight line that bisects the first region in the first direction X and extends along the second direction Y, the third midline may be a straight line that bisects the second region in the first direction X and extends along the second direction Y.
  • the second midline area may be an area including the second midline, the width of the second midline area in the first direction X may be approximately 1% to 10% of the width of the display substrate, the third midline area may be an area including the third midline, the width of the third midline area in the first direction X may be approximately 1% to 10% of the width of the display substrate.
  • the driving signal line HL may have a point bisecting the driving signal line HL in the first direction X, the first midpoint divides the driving signal line HL into a first line segment and a second line segment, the second midpoint may be a point bisecting the first line segment in the first direction X, and the third midpoint may be a point bisecting the second line segment in the first direction X.
  • the second midpoint region may be a region including the second midpoint, and the width of the second midpoint region in the first direction X may be approximately 1% to 10% of the width of the display substrate, and the third midpoint region may be a region including the third midpoint, and the width of the third midpoint region in the first direction X may be approximately 1% to 10% of the width of the display substrate.
  • the transmission distance of the row drive signal is L/4. Then, relative to the RC delay of the total length of the drive signal line, the RC delay at the end of the drive signal line can be reduced to 1/4, which can further reduce the RC delay and further increase the charging time.
  • FIG11 and FIG12 are schematic diagrams of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure
  • FIG11 illustrates the planar structure of region A in FIG7
  • FIG12 illustrates the planar structure of region B in FIG7
  • the circuit unit includes the pixel driving circuit shown in FIG4
  • the gate unit includes the gate driving circuit shown in FIG6 .
  • the first circuit area 210 may include a plurality of repeating units RU and a plurality of blank units KB, and the plurality of repeating units RU and the plurality of blank units KB may be alternately arranged along the first direction X.
  • the second circuit area 220 may include at least one gate driving circuit.
  • At least one repeating unit RU includes 12 circuit units forming 2 unit rows and 6 unit columns, each unit row may include a first circuit unit Q1, a second circuit unit Q2 and a third circuit unit Q3 periodically arranged along a first direction X, the first circuit unit Q1 may include at least a first pixel driving circuit, the second circuit unit Q2 may include at least a second pixel driving circuit, the third circuit unit Q3 may include at least a third pixel driving circuit, the first pixel driving circuit is configured to be connected to a red light emitting diode, the second pixel driving circuit is configured to be connected to a green light emitting diode, and the third pixel driving circuit is configured to be connected to a blue light emitting diode.
  • the pixel driving circuit of at least one circuit unit may include at least a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a storage capacitor Cs, a first capacitor C1 and a second capacitor C2, and the pixel driving circuit may be respectively connected to the first scanning signal line S1, the second scanning signal line S2, the light emitting signal line EM, the initial signal line Vint, the data signal line DataI and the high-frequency signal line Hf.
  • the shapes of the first scan signal line S1, the second scan signal line S2, the light emitting signal line EM and the initial signal line Vint can be line shapes extending along the first direction X
  • the shapes of the data signal line DataI and the high-frequency signal line Hf can be line shapes extending along the second direction Y.
  • the pixel driving circuit is configured to receive the data voltage of the data signal line and the initial voltage of the initial signal line Vint under the control of the first scan signal line S1, the second scan signal line S2, the light emitting signal line EM and the high-frequency signal line Hf, and output a corresponding current of a corresponding duration to the connected light emitting diode.
  • At least one second circuit area 220 may have a reference line O1, which is a straight line bisecting the second circuit area 220 in the second direction Y and extending along the first direction X.
  • the pixel driving circuits in the first circuit area 210 on both sides of the second circuit area 220 in the second direction Y may be mirror-symmetric with respect to the reference line O1.
  • the gate driving circuit may include a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, a twenty-fourth transistor T24, a twenty-fifth transistor T25, a twenty-sixth transistor T26, a twenty-seventh transistor T27, a twenty-eighth transistor T28, a third capacitor C3, and a fourth capacitor C4, and the gate driving circuit may be connected to the first clock signal line CLK, the second clock signal line CLKB, the high voltage line VGH, and the low voltage line VGL, respectively.
  • one gate unit may include a first GOA circuit, a second GOA circuit, and an EOA circuit
  • the first GOA circuit may be connected to the first scan signal line S1 through an output line
  • the second GOA circuit may be connected to the second scan signal line S2 through an output line
  • the EOA circuit may be connected to the light emitting signal line EM through an output line
  • FIG. 12 only illustrates the structure of the second GOA circuit.
  • the setting position of the gate driving circuit may substantially correspond to the setting position of at least one blank cell KB in the first circuit area 210, and the orthographic projection of the gate driving circuit on the reference line O1 at least partially overlaps with the orthographic projection of at least one blank cell KB on the reference line O1.
  • an orthographic projection of the gate driving circuit on the plane of the display substrate does not overlap with an orthographic projection of the data signal line DataI on the plane of the display substrate.
  • the first clock signal line CLK, the second clock signal line CLKB, the high voltage line VGH, and the low voltage line VGL may have a line shape extending along the second direction Y and be sequentially disposed along the first direction X.
  • the orthographic projections of the first clock signal line CLK and the second clock signal line CLKB on the display substrate plane do not overlap with the orthographic projection of the data signal line DataI on the display substrate plane.
  • the first clock signal line CLK may be substantially parallel to the data signal line DataI
  • the second clock signal line CLKB may be substantially parallel to the data signal line DataI
  • the orthographic projection of the first clock signal line CLK on the display substrate plane may be substantially parallel to the orthographic projection of the data signal line DataI on the display substrate plane
  • the orthographic projection of the second clock signal line CLKB on the display substrate plane may be substantially parallel to the orthographic projection of the data signal line DataI on the display substrate plane.
  • the orthographic projections of the first clock signal line CLK and the second clock signal line CLKB on the display substrate plane do not overlap with the orthographic projection of the gate driving circuit on the display substrate plane.
  • the first clock signal line CLK and the second clock signal line CLKB can be arranged between the high voltage line VGH and the low voltage line VGL, so that the high voltage line VGH and the low voltage line VGL that transmit the constant voltage signal can play a shielding role, effectively reducing the coupling capacitance between the clock signal line and the data signal line.
  • a first distance L1 is provided between an edge of the high voltage line VGH close to the data signal line DataI and an edge of the data signal line DataI close to the high voltage line VGH
  • a second distance L2 is provided between an edge of the low voltage line VGL close to the data signal line DataI and an edge of the data signal line DataI close to the low voltage line VGL.
  • the second distance L2 may be greater than the first distance L1, and the first distance L1 and the second distance L2 may be dimensions in the first direction X.
  • the first distance L1 may be greater than or equal to 25 ⁇ m
  • the second distance L2 may be greater than or equal to 25 ⁇ m.
  • a third distance L3 is provided between an edge of the first clock signal line CLK close to the low voltage line VGL and an edge of the low voltage line VGL close to the first clock signal line CLK
  • a fourth distance L4 is provided between an edge of the second clock signal line CLKB close to the high voltage line VGH and an edge of the high voltage line VGH close to the second clock signal line CLKB.
  • the third distance L3 may be greater than the fourth distance L4, and the third distance L3 and the fourth distance L4 may be dimensions in the first direction X.
  • the second circuit region 220 may further include at least one first mark MARK1 and at least one second mark MARK2.
  • the first mark MARK1 may be in a cross shape
  • the second mark MARK2 may be in a circle shape.
  • the setting position of the first mark MARK1 in the second circuit area 220 may substantially correspond to the setting position of the at least one blank cell KB in the first circuit area 210, and the orthographic projection of the at least one first mark MARK1 on the reference line O1 at least partially overlaps with the orthographic projection of the at least one blank cell KB on the reference line O1.
  • the setting position of the second mark MARK2 in the second circuit area 220 may substantially correspond to the setting position of the at least one blank cell KB in the first circuit area 210, and the positive projection of the at least one second mark MARK2 on the reference line O1 at least partially overlaps with the positive projection of the at least one blank cell KB on the reference line O1.
  • the orthographic projections of the first mark MARK1 and the second mark MARK2 on the plane of the display substrate do not overlap with the orthographic projections of the first scan signal line S1, the second scan signal line S2, the light emitting signal line EM, the high-frequency signal line Hf, the initial signal line Vint, the data signal line DataI, the first clock signal line CLK, the second clock signal line CLKB, the high voltage line VGH and the low voltage line VGL on the plane of the display substrate.
  • the display substrate may include a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer sequentially arranged on a base, one electrode plate of a plurality of capacitors may be arranged in the first gate metal layer, a first scan signal line S1, a second scan signal line S2, a light emitting signal line EM, and another electrode plate of a plurality of capacitors may be arranged in the second gate metal layer, a data signal line DataI, a high-frequency signal line Hf, a first clock signal line CLK, a second clock signal line CLKB, a high voltage line VGH, and a low voltage line VGL may be arranged in the first source-drain metal layer, and a high voltage power line and a low voltage power line may be arranged in the second source-drain metal layer.
  • the first mark MARK1 may be disposed in the first source-drain metal layer
  • the second mark MARK2 may be disposed in the second source-drain metal layer.
  • structure A extends along direction B means that structure A may include a main part and a secondary part connected to the main part, the main part is roughly in the shape of a strip extending along a certain direction, the secondary part has no limitation on shape, and the main part is at least 60% of structure A; the main part extends along direction B, and the size of the main part extending along direction B is greater than the size of the secondary part extending along other directions.
  • structure A extends along direction B means “the main part of structure A extends along direction B".
  • the following is an exemplary explanation through the preparation process of the display substrate.
  • the "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A” or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • a process of preparing a display substrate may include the following operations.
  • forming the first conductive layer pattern may include: depositing a first conductive film on a substrate, patterning the first conductive film through a patterning process, and forming a first conductive layer pattern disposed on the substrate, as shown in FIGS. 13, 14, and 15, wherein FIG. 13 is a structure of region A in FIG. 7, FIG. 14 is an enlarged view of a circuit unit in FIG. 13, and FIG. 15 is an enlarged view of a gate drive circuit in FIG. 13.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern of each circuit unit may include at least a first electrode plate CF1 , a second electrode plate CF2 , a third electrode plate CF3 , and a third bottom gate electrode Gate3 -B.
  • the shapes of the first electrode plate CF1, the second electrode plate CF2 and the third electrode plate CF3 may be rectangular, and the corners of the rectangular shape may be chamfered.
  • the first electrode plate CF1 may be arranged on one side of the second electrode plate CF2 in the first direction X
  • the first electrode plate CF1 and the second electrode plate CF2 may be arranged on one side of the circuit unit in the second direction Y
  • the third electrode plate CF3 may be arranged on the other side of the circuit unit in the second direction Y.
  • the first plate CF1 can be used as a plate of a first capacitor in a pixel driving circuit
  • the second plate CF2 can be used as a plate of a second capacitor in a pixel driving circuit
  • the third plate CF3 can be used as a plate of a storage capacitor in a pixel driving circuit
  • the positions, shapes and sizes of the first plate CF1, the second plate CF2 and the third plate CF3 in the first circuit unit Q1, the second circuit unit Q2 and the third circuit unit Q3 can be substantially the same.
  • a plate connection line may be connected to one side of the third electrode plate CF3 in the first direction X or in the opposite direction of the first direction X.
  • the shape of the plate connection line may be a strip extending along the first direction X.
  • the first end of the plate connection line is connected to the third electrode plate CF3 of the circuit unit.
  • the second end of the plate connection line extends along the first direction X or in the opposite direction of the first direction X, and is connected to the third electrode plate CF3 of the adjacent circuit unit, thereby connecting the third electrode plates CF3 in a unit row.
  • the plurality of third plates CF3 and the plurality of plate connection lines in a unit row may be interconnected integral structures.
  • the third plate CF3 in each circuit unit is connected to a subsequently formed high-voltage power supply line, by forming the third plates CF3 of adjacent circuit units into an integral structure interconnected, the third plates CF3 of the integral structure may be reused as a high-voltage power supply signal line, and the plurality of third plates CF3 in a unit row may be ensured to have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the third bottom gate electrode Gate3-B may be used as a bottom gate electrode of a third transistor (driving transistor).
  • the third bottom gate electrode Gate3-B may be in an "L" shape, and in the second direction Y, the third bottom gate electrode Gate3-B may be located on a side of the third electrode plate CF3 away from the first electrode plate CF1 and the second electrode plate CF2.
  • the position, shape, and size of the third bottom gate electrode Gate3 -B in the first circuit unit Q1 , the second circuit unit Q2 , and the third circuit unit Q3 may be substantially the same.
  • the first conductive layer patterns on both sides of the second circuit region 220 in the second direction Y may be mirror-symmetrical with respect to a reference line, which may be a straight line bisecting the second circuit region 220 in the second direction Y and extending along the first direction X.
  • the first conductive layer pattern of each gate driving circuit may include at least an eleventh plate CF11 and a twelfth plate CF12 .
  • the eleventh plate CF11 and the twelfth plate CF12 may be rectangular in shape, and the corners of the rectangles may be chamfered.
  • the twelfth plate CF12 may be disposed on one side of the eleventh plate CF11 in the first direction X.
  • the eleventh plate CF11 may serve as a plate of the third capacitor in the gate drive circuit
  • the twelfth plate CF12 may serve as a plate of the fourth capacitor in the gate drive circuit.
  • forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the first conductive layer, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIGS. 16, 17, and 18, wherein FIG. 16 is a structure of region A in FIG. 7, FIG. 17 is an enlarged view of a circuit unit in FIG. 16, and FIG. 18 is an enlarged view of a gate drive circuit in FIG. 16.
  • the semiconductor layer pattern of each circuit unit may include at least first to eleventh active layers AT1 to AT11 .
  • the first active layer AT1 may serve as an active layer of the first transistor T1
  • the second active layer AT2 may serve as an active layer of the second transistor T2
  • the third active layer AT3 may serve as an active layer of the third transistor T3
  • the fourth active layer AT4 may serve as an active layer of the fourth transistor T4
  • the fifth active layer AT5 may serve as an active layer of the fifth transistor T5
  • the sixth active layer AT6 may serve as an active layer of the sixth transistor T6
  • the seventh active layer AT7 may serve as an active layer of the seventh transistor T7
  • the eighth active layer AT8 may serve as an active layer of the eighth transistor T8
  • the ninth active layer AT9 may serve as an active layer of the ninth transistor T9
  • the tenth active layer AT10 may serve as an active layer of the tenth transistor T10
  • the eleventh active layer AT11 may serve as an active layer of the eleventh transistor T11.
  • the first active layer AT1, the second active layer AT2, the fourth active layer AT4, the seventh active layer AT7, the eighth active layer AT8, the ninth active layer AT9 and the tenth active layer AT10 may be shaped like strips extending along the first direction X
  • the third active layer AT3, the fifth active layer AT5, the sixth active layer AT6 and the eleventh active layer AT11 may be shaped like rectangles.
  • the second to sixth active layers AT2 to AT6 may be located on a side of the third plate CF3 away from the first plate CF1, and the first and seventh to eleventh active layers AT1 to AT11 may be located between the first and third plates CF1 and CF3.
  • the third active layer AT3 may be located on a side of the third electrode plate CF3 away from the first electrode plate CF1, and the orthographic projection of the third active layer AT3 on the substrate at least partially overlaps with the orthographic projection of the third bottom gate electrode Gate3-B on the substrate.
  • the second active layer AT2 may be located on one side of the third active layer AT3 in the first direction X
  • the fourth active layer AT4 may be located on one side of the third active layer AT3 in the opposite direction of the first direction X.
  • the fifth active layer AT5 and the sixth active layer AT6 may be located between the third electrode plate CF3 and the third active layer AT3, and the sixth active layer AT6 may be located on one side of the fifth active layer AT5 in the first direction X.
  • the tenth active layer AT10 may be located on a side of the first electrode plate CF1 close to the third electrode plate CF3
  • the eighth active layer AT8 may be located on a side of the tenth active layer AT10 close to the third electrode plate CF3
  • the eleventh active layer AT11 may be located on a side of the tenth active layer AT10 close to the third electrode plate CF3
  • the first active layer AT1 and the seventh active layer AT7 may be located on one side of the eighth active layer AT8 in the first direction X
  • the first active layer AT1 and the seventh active layer AT7 may be an integral structure connected to each other
  • the ninth active layer AT9 may be located on one side of the eleventh active layer AT11 in the first direction X.
  • the width of the third active layer AT3 in the first circuit unit Q1 may be greater than the width of the third active layer AT3 in the second circuit unit Q2 and the third circuit unit Q3, and the width may be a dimension in the first direction X so that the width-to-length ratio of the driving transistor (third transistor T3) in the first circuit unit Q1 is greater than the width-to-length ratio of the driving transistor in the second circuit unit Q2 and the third circuit unit Q3.
  • the first active layer AT1 to the eleventh active layer AT11 may each include a first region, a second region, and a channel region located between the first region and the second region, the first regions and the second regions of the plurality of active layers may each be separately arranged, and the first region of the first active layer AT1 and the first region of the seventh active layer AT7 are connected to each other.
  • the semiconductor layer patterns located at both sides of the second circuit region 220 in the second direction Y may be mirror-symmetrical with respect to the reference line.
  • the semiconductor layer pattern of each gate driving circuit may include at least twenty-first to twenty-eighth active layers AT21 to AT28 .
  • the twenty-first active layer AT21 may serve as an active layer of the twenty-first transistor T21
  • the twenty-second active layer AT22 may serve as an active layer of the twenty-second transistor T22
  • the twenty-third active layer AT23 may serve as an active layer of the twenty-third transistor T23
  • the twenty-fourth active layer AT24 may serve as an active layer of the twenty-fourth transistor T24
  • the twenty-fifth active layer AT25 may serve as an active layer of the twenty-fifth transistor T25
  • the twenty-sixth active layer AT26 may serve as an active layer of the twenty-sixth transistor T26
  • the twenty-seventh active layer AT27 may serve as an active layer of the twenty-seventh transistor T27
  • the twenty-eighth active layer AT28 may serve as an active layer of the twenty-eighth transistor T28.
  • the shape of the twenty-first active layer AT21, the twenty-second active layer AT22, the twenty-third active layer AT23, the twenty-sixth active layer AT26, the twenty-seventh active layer AT27 and the twenty-eighth active layer AT28 can be a strip shape extending along the second direction Y
  • the shape of the twenty-fourth active layer AT24 and the twenty-fifth active layer AT25 can be a parallel structure of multiple strip shapes extending along the second direction Y.
  • the twenty-fourth active layer AT24 may be located on the side of the eleventh plate CF11 in the opposite direction of the second direction Y, and the twenty-fifth active layer AT25 may be located on the side of the eleventh plate CF11 in the second direction Y.
  • the twenty-sixth active layer AT26 and the twenty-seventh active layer AT27 may be an integral structure connected to each other, and may be located on the side of the twelfth plate CF12 in the second direction Y, and the twenty-first active layer AT21 may be located on the side of the twenty-seventh active layer AT27 in the second direction Y.
  • the twenty-eighth active layer AT28 may be located on the side of the eleventh plate CF11 in the first direction X
  • the twenty-third active layer AT23 may be located on the side of the first direction X of the twenty-eighth active layer AT28
  • the twenty-second active layer AT22 may be located on the side of the first direction X of the twenty-third active layer AT23.
  • the twenty-first active layer AT21 to the twenty-eighth active layer AT28 may each include a first region, a second region, and a channel region located between the first region and the second region, the first regions and the second regions of the multiple active layers may each be separately arranged, and the second region of the twenty-sixth active layer AT26 and the first region of the twenty-seventh active layer AT27 are interconnected.
  • forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a second insulating layer covering the semiconductor layer, and a second conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 19, 20, and 21, wherein FIG. 19 is a structure of region A in FIG. 7, FIG. 20 is an enlarged view of a circuit unit in FIG. 19, and FIG. 21 is an enlarged view of a gate drive circuit in FIG. 19.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern of each circuit unit includes at least: a fourth electrode plate CF4, a fifth electrode plate CF5, a sixth electrode plate CF6, a first scan signal line S1, a second scan signal line S2, a light emitting signal line EM, a second control line CT2, an initial signal line Vint, a high-frequency connecting line Hf-C, a high-voltage connecting line VDD-C, a low-voltage connecting line VSS-C, a plurality of gate electrodes, and a plurality of connecting electrodes.
  • the shape of the fourth plate CF4, the fifth plate CF5 and the sixth plate CF6 can be a rectangular shape with a notch at one corner.
  • the orthographic projection of the fourth plate CF4 on the substrate overlaps at least partially with the orthographic projection of the first plate CF1 on the substrate, and the fourth plate CF4 can be used as another plate of the first capacitor, and the first plate CF1 and the fourth plate CF4 constitute a first capacitor of the pixel driving circuit.
  • the orthographic projection of the fifth plate CF5 on the substrate overlaps at least partially with the orthographic projection of the second plate CF2 on the substrate, and the fifth plate CF5 can be used as another plate of the second capacitor, and the second plate CF2 and the fifth plate CF5 constitute a second capacitor of the pixel driving circuit.
  • the orthographic projection of the sixth plate CF6 on the substrate overlaps at least partially with the orthographic projection of the third plate CF3 on the substrate, and the sixth plate CF6 can be used as another plate of the storage capacitor, and the third plate CF3 and the sixth plate CF6 constitute a storage capacitor of the pixel driving circuit.
  • the positions, shapes, and sizes of the fourth plate CF4 , the fifth plate CF5 , and the sixth plate CF6 in the first circuit unit Q1 , the second circuit unit Q2 , and the third circuit unit Q3 may be substantially the same.
  • the shapes of the first scan signal line S1, the second scan signal line S2, the light emitting signal line EM, the second control line CT2, the initial signal line Vint, the high-frequency connection line Hf-C, the high-voltage connection line VDD-C, and the low-voltage connection line VSS-C may be a straight line or a folded line with the main body extending along the first direction X.
  • the first scan signal line S1 may be located on a side of the sixth electrode plate CF6 away from the fourth electrode plate CF4 and the fifth electrode plate CF5, the high-frequency connection line Hf-C and the low-voltage connection line VSS-C may be located on a side of the fourth electrode plate CF4 and the fifth electrode plate CF5 away from the sixth electrode plate CF6, and the second scan signal line S2, the light emitting signal line EM, the second control line CT2, the initial signal line Vint, and the high-voltage connection line VDD-C may be located between the fourth electrode plate CF4 and the sixth electrode plate CF6.
  • the low voltage connection line VSS-C may be located on a side of the fourth and fifth plates CF4 and CF5 away from the sixth plate CF6, and the high frequency connection line Hf-C may be located on a side of the low voltage connection line VSS-C away from the fourth and fifth plates CF4 and CF5.
  • one of the first circuit regions 210 located on both sides of the second circuit region 220 in the second direction Y may be provided with a high-frequency connection line Hf-C, and the other first circuit region 210 may not be provided with a high-frequency connection line Hf-C.
  • one of the low-voltage connection lines VSS-C located on both sides of the second direction Y of the second circuit area 220 may be provided with a bending section, and the bending section may be located in the area where the blank unit KB is located, and the bending section bends in a direction away from the second circuit area 220 to leave corresponding space for the gate drive circuit.
  • one of the low-voltage connection lines VSS-C located on both sides of the second circuit area 220 in the second direction Y can be provided with a plurality of connection bars, the first ends of the plurality of connection bars are connected to the low-voltage connection line VSS-C, and the second ends of the plurality of connection bars extend along the second direction Y toward the second circuit area 220.
  • the initial signal line Vint may be located on a side of the fourth plate CF4 and the fifth plate CF5 close to the sixth plate CF6, the second control line CT2 may be located on a side of the initial signal line Vint close to the sixth plate CF6, the second scan signal line S2 may be located on a side of the second control line CT2 close to the sixth plate CF6, the high-voltage connection line VDD-C may be located on a side of the second scan signal line S2 close to the sixth plate CF6, and the light-emitting signal line EM may be located on a side of the high-voltage connection line VDD-C close to the sixth plate CF6.
  • the second scan signal line S2 may be multiplexed as a first control line to control the turning on and off of the eighth transistor T8.
  • the high-voltage connection line VDD-C is configured to be connected to a subsequently formed high-voltage power line to form a mesh-like connection structure.
  • the low-voltage connection line VSS-C is configured to be connected to a subsequently formed low-voltage power line to form a mesh-like connection structure.
  • the high-frequency connection line Hf-C is configured to be connected to a subsequently formed high-frequency signal line to form a mesh-like connection structure.
  • the multiple gate electrodes of each circuit unit may include at least a first gate electrode Gate1, a second gate electrode Gate2, a third top gate electrode Gate3-T, a fourth gate electrode Gate4, a fifth gate electrode Gate5, a sixth gate electrode Gate6, a seventh gate electrode Gate7, an eighth gate electrode Gate8, a ninth gate electrode Gate9, a tenth gate electrode Gate10 and an eleventh gate electrode Gate11.
  • the second gate electrode Gate2 and the fourth gate electrode Gate4 may be disposed on a side of the first scan signal line S1 close to the sixth electrode plate CF6.
  • the second gate electrode Gate2 serves as the gate electrode of the second transistor T2, and the orthographic projection of the second gate electrode Gate2 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate.
  • the fourth gate electrode Gate4 serves as the gate electrode of the fourth transistor T4, and the orthographic projection of the fourth gate electrode Gate4 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer on the substrate.
  • the first scan signal line S1, the second gate electrode Gate2, and the fourth gate electrode Gate4 may be an integrated structure connected to each other.
  • the first gate electrode Gate1, the seventh gate electrode Gate7, and the eighth gate electrode Gate8 may be disposed on a side of the second scan signal line S2 away from the initial signal line Vint.
  • the first gate electrode Gate1 serves as the gate electrode of the first transistor T1, and the orthographic projection of the first gate electrode Gate1 on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate.
  • the seventh gate electrode Gate7 serves as the gate electrode of the seventh transistor T7, and the orthographic projection of the seventh gate electrode Gate7 on the substrate at least partially overlaps with the orthographic projection of the seventh active layer on the substrate.
  • the eighth gate electrode Gate8 serves as the gate electrode of the eighth transistor T8, and the orthographic projection of the eighth gate electrode Gate8 on the substrate at least partially overlaps with the orthographic projection of the eighth active layer on the substrate.
  • the second scan signal line S2, the first gate electrode Gate1, the seventh gate electrode Gate7, and the eighth gate electrode Gate8 may be an integrated structure connected to each other.
  • the tenth gate electrode Gate10 may be disposed on a side of the second control line CT2 close to the initial signal line Vint.
  • the tenth gate electrode Gate10 serves as a gate electrode of the tenth transistor T10, and the orthographic projection of the tenth gate electrode Gate10 on the substrate at least partially overlaps with the orthographic projection of the tenth active layer on the substrate.
  • the second control line CT2 and the tenth gate electrode Gate10 may be an integral structure connected to each other.
  • the third top gate electrode Gate3-T can serve as the top gate electrode of the third transistor T3, the orthographic projection of the third top gate electrode Gate3-T on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate, and the orthographic projection of the third top gate electrode Gate3-T on the substrate at least partially overlaps with the orthographic projection of the third bottom gate electrode Gate3-B on the substrate.
  • the fifth gate electrode Gate5 can be used as the gate electrode of the fifth transistor T5, and the orthographic projection of the fifth gate electrode Gate5 on the substrate at least partially overlaps with the orthographic projection of the fifth active layer on the substrate.
  • the fifth gate electrode Gate5 can be located between the light emitting signal line EM and the third top gate electrode Gate3-T, and the shape of the fifth gate electrode Gate5 can be comb-shaped.
  • the sixth gate electrode Gate6 can be used as the gate electrode of the sixth transistor T6, and the orthographic projection of the sixth gate electrode Gate6 on the substrate at least partially overlaps with the orthographic projection of the sixth active layer on the substrate.
  • the sixth gate electrode Gate6 can be located between the light emitting signal line EM and the third top gate electrode Gate3-T, and the shape of the sixth gate electrode Gate6 can be comb-shaped.
  • the ninth gate electrode Gate9 can serve as the gate electrode of the ninth transistor T9, and the orthographic projection of the ninth gate electrode Gate9 on the substrate at least partially overlaps with the orthographic projection of the ninth active layer on the substrate.
  • the ninth gate electrode Gate9 can be located between the second scan signal line S2 and the high-voltage connection line VDD-C, and the shape of the ninth gate electrode Gate9 can be rectangular.
  • the eleventh gate electrode Gate11 may serve as a gate electrode of the eleventh transistor T11, and an orthographic projection of the eleventh gate electrode Gate11 on the substrate at least partially overlaps an orthographic projection of the eleventh active layer on the substrate.
  • the eleventh gate electrode Gate11 may be between the second scan signal line S2 and the high-voltage connection line VDD-C, and the shape of the eleventh gate electrode Gate11 may be a strip shape.
  • the plurality of connection electrodes of each circuit unit include at least first, second, third, fourth, fifth, sixth, seventh, and eighth connection electrodes CO1, CO2, CO3, CO4, CO6, CO7, and CO8.
  • the first connection electrode CO1 may be in a strip shape extending along the first direction X and may be disposed between the second scan signal line S2 and the high voltage connection line VDD-C.
  • the first connection electrode CO1 is configured to be connected to the subsequently formed high frequency signal line Hf and the twenty-fourth connection electrode.
  • the second connection electrode CO2 may be in a strip shape extending along the first direction X and may be disposed between the second scan signal line S2 and the high voltage connection line VDD-C.
  • the second connection electrode CO2 is configured to be connected to a subsequently formed twenty-second connection electrode and a twenty-third connection electrode.
  • the third connection electrode CO3 may be rectangular in shape and may be disposed on a side of the second connection electrode CO2 close to the second scan signal line S2 .
  • the third connection electrode CO3 is configured to be connected to a subsequently formed twenty-fifth connection electrode.
  • the fourth connection electrode CO4 may be in the shape of a folded line extending along the second direction Y, and may be disposed on a side of the third top gate electrode Gate3-T close to the sixth electrode plate CF6, a first end of the fourth connection electrode CO4 is connected to the third top gate electrode Gate3-T, and a second end of the fourth connection electrode CO4 is connected to the sixth electrode plate CF6.
  • the third top gate electrode Gate3-T, the sixth electrode plate CF6, and the fourth connection electrode CO4 may be an integrated structure connected to each other.
  • the fifth connection electrode CO5 may be in a strip shape extending along the second direction Y, and may be disposed on a side of the fifth gate electrode Gate5 close to the light emitting signal line EM, a first end of the fifth connection electrode CO5 is connected to the fifth gate electrode Gate5, and a second end of the fifth connection electrode CO5 is connected to the light emitting signal line EM, thereby realizing that the light emitting signal line EM can control the conduction or disconnection of the fifth transistor T5.
  • the light emitting signal line EM, the fifth gate electrode Gate5, and the fifth connection electrode CO5 may be an integrated structure connected to each other.
  • the sixth connection electrode CO6 may be in the shape of a strip extending along the second direction Y, and may be disposed on a side of the sixth gate electrode Gate6 close to the light emitting signal line EM, a first end of the sixth connection electrode CO6 is connected to the sixth gate electrode Gate6, a second end of the sixth connection electrode CO6 is close to the light emitting signal line EM, and the sixth connection electrode CO6 is configured to be connected to a subsequently formed twenty-third connection electrode.
  • the seventh connection electrode CO7 may be in a strip shape extending along the first direction X, may be disposed between the second scan signal line S2 and the high voltage connection line VDD-C, and the seventh connection electrode CO7 and the ninth gate electrode Gate9 may be an integral structure connected to each other.
  • the eighth connection electrode CO8 may be in a strip shape extending along the first direction X, may be disposed between the second scan signal line S2 and the high voltage connection line VDD-C, and the eighth connection electrode CO8 and the eleventh gate electrode Gate11 may be an integral structure connected to each other.
  • the partial circuit unit may further include a first anode connection line 11 configured to be connected to an anode connection block to be formed subsequently.
  • the second conductive layer patterns located at both sides of the second circuit region 220 in the second direction Y may be substantially mirror-symmetrical with respect to the reference line.
  • the second conductive layer pattern of each gate driving circuit may include at least: a thirteenth plate CF13, a fourteenth plate CF14, an upper-level output signal line G(n-1), a current-level output signal line G(n), a plurality of gate electrodes, and a plurality of gate blocks.
  • the shape of the thirteenth plate CF13 and the fourteenth plate CF14 may be rectangular.
  • the orthographic projection of the thirteenth plate CF13 on the substrate overlaps at least partially with the orthographic projection of the eleventh plate CF11 on the substrate, and the thirteenth plate CF13 may serve as another plate of the third capacitor, and the eleventh plate CF11 and the thirteenth plate CF13 constitute the third capacitor of the gate drive circuit.
  • the orthographic projection of the fourteenth plate CF14 on the substrate overlaps at least partially with the orthographic projection of the twelfth plate CF12 on the substrate, and the fourteenth plate CF14 may serve as another plate of the fourth capacitor, and the twelfth plate CF12 and the fourteenth plate CF14 constitute the fourth capacitor of the gate drive circuit.
  • the shape of the previous stage output signal line G(n-1) and the current stage output signal line G(n) may be a straight line or a folded line with the main part extending along the first direction X, the previous stage output signal line G(n-1) is configured to be connected to at least the first scanning signal line in the n-1th row, and the current stage output signal line G(n) is configured to be connected to at least the first scanning signal line in the nth row.
  • the previous stage output signal line G(n-1) may be located on one side of the fourteenth plate CF14 in the first direction X, and the current stage output signal line G(n) may be located on one side of the thirteenth plate CF13 in the opposite direction of the first direction X.
  • the previous stage output signal line G(n-1) and the current stage output signal line G(n) may be located on one side of the thirteenth plate CF13 and the fourteenth plate CF14 in the second direction Y.
  • the plurality of gate electrodes of the gate driving circuit may include a twenty-first gate electrode Gate21, a twenty-second gate electrode Gate22, a twenty-third gate electrode Gate23, a twenty-fourth gate electrode Gate24, a twenty-fifth gate electrode Gate25, a twenty-sixth gate electrode Gate26, a twenty-seventh gate electrode Gate27, and a twenty-eighth gate electrode Gate28.
  • the twenty-fourth gate electrode Gate24 can be arranged on a side of the fourteenth plate CF14 in the opposite direction of the first direction X, and the twenty-fourth gate electrode Gate24 serves as the gate electrode of the twenty-fourth transistor T24, and the orthographic projection of the twenty-fourth gate electrode Gate24 on the substrate at least partially overlaps with the orthographic projection of the twenty-fourth active layer on the substrate.
  • the twenty-fourth gate electrode Gate24 may include a plurality of sub-electrodes, each of which may be in the shape of a strip extending along the first direction X, and the plurality of sub-electrodes may be spaced apart along the second direction Y to form a comb-like structure and connected to the fourteenth plate CF14.
  • the twenty-fourth gate electrode Gate24 and the fourteenth electrode plate CF14 may be an integral structure connected to each other.
  • the twenty-fifth gate electrode Gate25 can be disposed on one side of the thirteenth plate CF13 in the second direction Y, and the twenty-fifth gate electrode Gate25 serves as the gate electrode of the twenty-fifth transistor T25, and the orthographic projection of the twenty-fifth gate electrode Gate25 on the substrate at least partially overlaps with the orthographic projection of the twenty-fifth active layer on the substrate.
  • the twenty-fifth gate electrode Gate25 may include a plurality of sub-electrodes, each of which may be in the shape of a strip extending along the first direction X, and the plurality of sub-electrodes may be spaced apart along the second direction Y to form a comb-like structure and connected to the thirteenth plate CF13.
  • the twenty-fifth gate electrode Gate25 and the thirteenth electrode plate CF13 may be an integral structure connected to each other.
  • the twenty-sixth gate electrode Gate26 may be disposed on one side of the fourteenth plate CF14 in the second direction Y and connected to the fourteenth plate CF14.
  • the twenty-sixth gate electrode Gate26 serves as a gate electrode of the twenty-sixth transistor T26, and an orthographic projection of the twenty-sixth gate electrode Gate26 on the substrate at least partially overlaps an orthographic projection of the twenty-sixth active layer on the substrate.
  • the twenty-fourth gate electrode Gate24, the twenty-sixth gate electrode Gate26, and the fourteenth gate plate CF14 may be an integral structure connected to each other.
  • the twenty-seventh gate electrode Gate27 can be disposed on one side of the twenty-sixth gate electrode Gate26 in the second direction Y, and the twenty-seventh gate electrode Gate27 serves as the gate electrode of the twenty-seventh transistor T27, and the orthographic projection of the twenty-seventh gate electrode Gate27 on the substrate at least partially overlaps with the orthographic projection of the twenty-seventh active layer on the substrate.
  • the twenty-second gate electrode Gate22 can be disposed on one side of the twenty-seventh gate electrode Gate27 in the second direction Y, and the twenty-second gate electrode Gate22 serves as the gate electrode of the twenty-second transistor T22, and the orthographic projection of the twenty-second gate electrode Gate22 on the substrate at least partially overlaps with the orthographic projection of the twenty-second active layer on the substrate.
  • the twenty-first gate electrode Gate21 and the twenty-third gate electrode Gate23 may be disposed on one side of the twenty-second gate electrode Gate22 in the second direction Y, and the two are an integral structure connected to each other.
  • the twenty-first gate electrode Gate21 serves as the gate electrode of the twenty-first transistor T21, and the orthographic projection of the twenty-first gate electrode Gate21 on the substrate at least partially overlaps with the orthographic projection of the twenty-first active layer on the substrate.
  • the twenty-third gate electrode Gate23 serves as the gate electrode of the twenty-third transistor T23, and the orthographic projection of the twenty-third gate electrode Gate23 on the substrate at least partially overlaps with the orthographic projection of the twenty-third active layer on the substrate.
  • the twenty-eighth gate electrode Gate28 can be disposed on one side of the twenty-second gate electrode Gate22 in the second direction Y, and the twenty-eighth gate electrode Gate28 serves as the gate electrode of the twenty-eighth transistor T28, and the orthographic projection of the twenty-eighth gate electrode Gate28 on the substrate at least partially overlaps with the orthographic projection of the twenty-eighth active layer on the substrate.
  • the plurality of gate blocks of the gate driving circuit may include a first gate block GK1 , a second gate block GK2 , a third gate block GK3 , and a fourth gate block GK4 .
  • the first gate block GK1 may be rectangular in shape and may be disposed on one side of the twenty-first gate electrode Gate21 in the first direction X, and the first gate block GK1 and the twenty-first gate electrode Gate21 are an integral structure connected to each other, and the first gate block GK1 is configured to be connected to a first clock signal line formed subsequently.
  • the second gate block GK2 may be rectangular in shape and may be disposed on one side of the twenty-seventh gate electrode Gate27 in the first direction X, and the second gate block GK2 and the twenty-seventh gate electrode Gate27 are an integral structure connected to each other, and the second gate block GK2 is configured to be connected to a second clock signal line formed subsequently.
  • the third gate block GK3 may be in a strip shape extending along the first direction X, may be disposed on one side of the fourteenth plate CF14 in the first direction X, and is configured to be connected to a subsequently formed high voltage line.
  • the shape of the fourth gate block GK4 can be rectangular and can be arranged on one side of the first direction X of the twenty-eighth gate electrode Gate28, and the fourth gate block GK4 and the twenty-eighth gate electrode Gate28 are an integral structure connected to each other, and the fourth gate block GK4 is configured to be connected to a low voltage line formed subsequently.
  • the second conductive layer can be used as a shield to perform conductorization on the semiconductor layer.
  • the semiconductor layer in the area shielded by the second conductive layer forms the channel region of the first transistor T1 to the eleventh transistor T11, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of the first transistor T1 to the eleventh transistor T11 and the twenty-first transistor T2 to the twenty-eighth transistor T28 are all conductorized.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIGS. 22 , 23 and 24 , wherein FIG. 22 is a structure of region A in FIG. 7 , FIG. 23 is an enlarged view of a circuit unit in FIG. 22 , and FIG. 24 is an enlarged view of a gate drive circuit in FIG. 22 .
  • the plurality of via holes of each circuit unit includes at least an eleventh via hole V11 to a fifty-fourth via hole V54 .
  • the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the third insulating layer and the second insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first region of the first active layer, and the eleventh via hole V11 is configured to connect a subsequently formed eleventh connecting electrode to the first region of the first active layer through the via hole.
  • the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second region of the first active layer on the substrate, the third insulating layer and the second insulating layer in the twelfth via hole V12 are etched away to expose the surface of the second region of the first active layer, and the twelfth via hole V12 is configured to connect a subsequently formed fourteenth connecting electrode to the second region of the first active layer through the via hole.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate, the third insulating layer and the second insulating layer in the thirteenth via hole V13 are etched away, exposing the surface of the first region of the second active layer, and the thirteenth via hole V13 is configured to connect the fifteenth connecting electrode formed subsequently to the first region of the second active layer through the via hole.
  • the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the third insulating layer and the second insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the second region of the second active layer, and the fourteenth via hole V14 is configured to connect a subsequently formed sixteenth connecting electrode to the second region of the second active layer through the via hole.
  • the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the first region of the third active layer on the substrate, the third insulating layer and the second insulating layer in the fifteenth via hole V15 are etched away to expose the surface of the first region of the third active layer, and the fifteenth via hole V15 is configured to connect the subsequently formed seventeenth connecting electrode to the first region of the third active layer through the via hole.
  • the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the second region of the third active layer on the substrate, the third insulating layer and the second insulating layer in the sixteenth via hole V16 are etched away to expose the surface of the second region of the third active layer, and the sixteenth via hole V16 is configured to connect a subsequently formed sixteenth connecting electrode to the second region of the third active layer through the via hole.
  • the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, the third insulating layer and the second insulating layer in the seventeenth via hole V17 are etched away to expose the surface of the first region of the fourth active layer, and the seventeenth via hole V17 is configured to connect a subsequently formed data signal line to the first region of the fourth active layer through the via hole.
  • the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the second region of the fourth active layer on the substrate, the third insulating layer and the second insulating layer in the eighteenth via hole V18 are etched away to expose the surface of the second region of the fourth active layer, and the eighteenth via hole V18 is configured to connect the subsequently formed seventeenth connecting electrode to the second region of the fourth active layer through the via hole.
  • the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the third insulating layer and the second insulating layer in the nineteenth via hole V19 are etched away to expose the surface of the first region of the fifth active layer, and the nineteenth via hole V19 is configured to connect the subsequently formed eighteenth connecting electrode to the first region of the fifth active layer through the via hole.
  • the orthographic projection of the twentieth via hole V20 on the substrate is located within the range of the orthographic projection of the second region of the fifth active layer on the substrate, the third insulating layer and the second insulating layer in the twentieth via hole V20 are etched away to expose the surface of the second region of the fifth active layer, and the twentieth via hole V20 is configured to connect the subsequently formed seventeenth connecting electrode to the second region of the fifth active layer through the via hole.
  • the nineteenth via hole V19 and the twentieth via hole V20 are both in plural, and the plurality of the nineteenth via holes V19 and the plurality of the twentieth via holes V20 are alternately arranged in the second direction Y.
  • the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the first region of the sixth active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-first via hole V21 are etched away to expose the surface of the first region of the sixth active layer, and the twenty-first via hole V21 is configured to connect the subsequently formed sixteenth connecting electrode to the first region of the sixth active layer through the via hole.
  • the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the second region of the sixth active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-second via hole V22 are etched away to expose the surface of the second region of the sixth active layer, and the twenty-second via hole V22 is configured to connect the subsequently formed twenty-sixth connecting electrode to the second region of the sixth active layer through the via hole.
  • both the twenty-first via hole V21 and the twenty-second via hole V22 are in plural, and the plurality of the twenty-first via holes V21 and the plurality of the twenty-second via holes V22 are alternately arranged in the second direction Y.
  • the orthographic projection of the twenty-third via hole V23 on the substrate is within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-third via hole V23 are etched away, exposing the surface of the seventh region of the seventh active layer, and the twenty-third via hole V23 is configured to connect the eleventh connection electrode formed subsequently to the first region of the seventh active layer through the via hole. Since the first region of the first active layer is connected to the first region of the seventh active layer, the eleventh via hole V11 and the twenty-third via hole V23 are common via holes.
  • the orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the second region of the seventh active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-fourth via hole V24 are etched away to expose the surface of the second region of the seventh active layer, and the twenty-fourth via hole V24 is configured to connect the subsequently formed twenty-sixth connecting electrode to the second region of the seventh active layer through the via hole.
  • the orthographic projection of the twenty-fifth via hole V25 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-fifth via hole V25 are etched away to expose the surface of the ninth region of the eighth active layer, and the twenty-fifth via hole V25 is configured to connect a subsequently formed data signal line to the first region of the eighth active layer through the via hole.
  • the orthographic projection of the twenty-sixth via hole V26 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-sixth via hole V26 are etched away to expose the surface of the second region of the eighth active layer, and the twenty-sixth via hole V26 is configured to connect the subsequently formed twentieth connecting electrode to the second region of the eighth active layer through the via hole.
  • the orthographic projection of the twenty-seventh via hole V27 on the substrate is located within the range of the orthographic projection of the first region of the ninth active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-seventh via hole V27 are etched away to expose the surface of the first region of the ninth active layer, and the twenty-seventh via hole V27 is configured to connect the subsequently formed twenty-fifth connecting electrode to the first region of the ninth active layer through the via hole.
  • the orthographic projection of the twenty-eighth via hole V28 on the substrate is located within the range of the orthographic projection of the second region of the ninth active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-eighth via hole V28 are etched away to expose the surface of the second region of the ninth active layer, and the twenty-eighth via hole V28 is configured to connect the subsequently formed twenty-second connecting electrode to the second region of the ninth active layer through the via hole.
  • the orthographic projection of the twenty-ninth via V29 on the substrate is located within the range of the orthographic projection of the first region of the tenth active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-ninth via V29 are etched away to expose the surface of the first region of the tenth active layer, and the twenty-ninth via V29 is configured to connect a subsequently formed data signal line to the first region of the tenth active layer through the via.
  • the orthographic projection of the thirtieth via hole V30 on the substrate is located within the range of the orthographic projection of the second region of the tenth active layer on the substrate, the third insulating layer and the second insulating layer in the thirtieth via hole V30 are etched away to expose the surface of the second region of the tenth active layer, and the thirtieth via hole V30 is configured to connect the subsequently formed twenty-first connecting electrode to the second region of the tenth active layer through the via hole.
  • the orthographic projection of the thirty-first via hole V31 on the substrate is located within the range of the orthographic projection of the first region of the eleventh active layer on the substrate, the third insulating layer and the second insulating layer in the thirty-first via hole V31 are etched away to expose the surface of the first region of the eleventh active layer, and the thirty-first via hole V31 is configured to connect the subsequently formed twenty-fourth connecting electrode to the first region of the eleventh active layer through the via hole.
  • the orthographic projection of the thirty-second via hole V32 on the substrate is located within the range of the orthographic projection of the second region of the eleventh active layer on the substrate, the third insulating layer and the second insulating layer in the thirty-second via hole V32 are etched away to expose the surface of the second region of the eleventh active layer, and the thirty-second via hole V32 is configured to connect a subsequently formed twenty-second connecting electrode to the second region of the eleventh active layer through the via hole.
  • the orthographic projection of the thirty-third via hole V33 on the substrate is located within the range of the orthographic projection of the first electrode plate CF1 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the thirty-third via hole V33 are etched away to expose the surface of the first electrode plate CF1, and the thirty-third via hole V33 is configured to connect the subsequently formed seventh electrode plate to the first electrode plate CF1 through the via hole.
  • the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the second electrode plate CF2 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the thirty-fourth via V34 are etched away to expose the surface of the second electrode plate CF2, and the thirty-fourth via V34 is configured to connect the subsequently formed eighth electrode plate to the second electrode plate CF2 through the via.
  • the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the third electrode plate CF3 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the thirty-fifth via V35 are etched away to expose the surface of the third electrode plate CF3, and the thirty-fifth via V35 is configured to connect the subsequently formed ninth electrode plate to the third electrode plate CF3 through the via.
  • the orthographic projection of the thirty-sixth via hole V36 on the substrate is located within the range of the orthographic projection of the fourth electrode plate CF4 on the substrate, the third insulating layer in the thirty-sixth via hole V36 is etched away to expose the surface of the fourth electrode plate CF4, and the thirty-sixth via hole V36 is configured to connect the subsequently formed nineteenth connecting electrode to the fourth electrode plate CF4 through the via hole.
  • the orthographic projection of the thirty-seventh via hole V37 on the substrate is located within the range of the orthographic projection of the fifth electrode plate CF5 on the substrate, the third insulating layer in the thirty-seventh via hole V37 is etched away to expose the surface of the fifth electrode plate CF5, and the thirty-seventh via hole V37 is configured to connect the subsequently formed twenty-first connecting electrode to the fifth electrode plate CF5 through the via hole.
  • the orthographic projection of the thirty-eighth via hole V38 on the substrate is located within the range of the orthographic projection of the sixth electrode plate CF6 on the substrate, the third insulating layer in the thirty-eighth via hole V38 is etched away to expose the surface of the sixth electrode plate CF6, and the thirty-eighth via hole V38 is configured to connect the subsequently formed fourteenth connecting electrode to the sixth electrode plate CF6 through the via hole.
  • the orthographic projection of the thirty-ninth via V39 on the substrate is located within the range of the orthographic projection of the high-voltage connecting line VDD-C on the substrate, the third insulating layer in the thirty-ninth via V39 is etched away to expose the surface of the high-voltage connecting line VDD-C, and the thirty-ninth via V39 is configured to connect the subsequently formed thirteenth connecting electrode to the high-voltage connecting line VDD-C through the via.
  • the orthographic projection of the 40th via hole V40 on the substrate is located within the range of the orthographic projection of the high-frequency connecting line Hf-C on the substrate, the third insulating layer in the 40th via hole V40 is etched away to expose the surface of the high-frequency connecting line Hf-C, and the 40th via hole V40 is configured to connect a subsequently formed high-frequency signal line to the high-frequency connecting line Hf-C through the via hole.
  • the orthographic projection of the forty-first via hole V41 on the substrate is located within the range of the orthographic projection of the luminous signal line EM on the substrate, the third insulating layer in the forty-first via hole V41 is etched away to expose the surface of the luminous signal line EM, and the forty-first via hole V41 is configured to connect the subsequently formed twenty-fifth connecting electrode to the luminous signal line EM through the via hole.
  • the orthographic projections of the forty-second via V42 and the forty-third via V43 on the substrate are respectively located within the range of the orthographic projections of the initial signal line Vint on the substrate, the third insulating layer in the forty-second via V42 and the forty-third via V43 is etched away to expose the surfaces of the initial signal line Vint, respectively, and the forty-second via V42 and the forty-third via V43 are configured to connect the subsequently formed eleventh connecting electrode and the twelfth connecting electrode to the initial signal line Vint through the above-mentioned vias, respectively.
  • the orthographic projection of the forty-fourth via hole V44 on the substrate is located within the range of the orthographic projection of the first end of the first connection electrode CO1 on the substrate, the third insulating layer in the forty-fourth via hole V44 is etched away to expose the surface of the first end of the first connection electrode CO1, and the forty-fourth via hole V44 is configured to connect a subsequently formed high-frequency connection line to the first connection electrode CO1 through the via hole.
  • the orthographic projection of the forty-fifth via hole V45 on the substrate is located within the range of the orthographic projection of the second end of the first connection electrode CO1 on the substrate, the third insulating layer in the forty-fifth via hole V45 is etched away to expose the surface of the second end of the first connection electrode CO1, and the forty-fifth via hole V45 is configured to connect the subsequently formed twenty-fourth connection electrode to the second end of the first connection electrode CO1 through the via hole.
  • the orthographic projection of the forty-sixth via hole V46 on the substrate is located within the range of the orthographic projection of the first end of the second connection electrode CO2 on the substrate, the third insulating layer in the forty-sixth via hole V46 is etched away to expose the surface of the first end of the second connection electrode CO2, and the forty-sixth via hole V46 is configured to connect the subsequently formed twenty-second connection electrode to the first end of the second connection electrode CO2 through the via hole.
  • the orthographic projection of the forty-seventh via hole V47 on the substrate is located within the range of the orthographic projection of the second end of the second connecting electrode CO2 on the substrate, the third insulating layer in the forty-seventh via hole V47 is etched away to expose the surface of the second end of the second connecting electrode CO2, and the forty-seventh via hole V47 is configured to connect the subsequently formed twenty-third connecting electrode to the second end of the second connecting electrode CO2 through the via hole.
  • the orthographic projection of the forty-eight via hole V48 on the substrate is located within the range of the orthographic projection of the third connecting electrode CO3 on the substrate, the third insulating layer in the forty-eight via hole V48 is etched away to expose the surface of the third connecting electrode CO3, and the forty-eight via hole V48 is configured to connect the subsequently formed twenty-fifth connecting electrode to the third connecting electrode CO3 through the via hole.
  • the orthographic projection of the forty-ninth via hole V49 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode CO4 on the substrate, the third insulating layer in the forty-ninth via hole V49 is etched away to expose the surface of the fourth connecting electrode CO4, and the forty-ninth via hole V49 is configured to connect the subsequently formed fifteenth connecting electrode to the fourth connecting electrode CO4 through the via hole.
  • the orthographic projection of the fiftieth via hole V50 on the substrate is located within the range of the orthographic projection of the third bottom gate electrode Gate3-B on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the fiftieth via hole V50 are etched away to expose the surface of the third bottom gate electrode Gate3-B, and the fiftieth via hole V50 is configured to connect the subsequently formed fifteenth connecting electrode to the third bottom gate electrode Gate3-B through the via hole.
  • the orthographic projection of the fifty-first via hole V51 on the substrate is located within the range of the orthographic projection of the sixth connection electrode CO6 on the substrate, the third insulating layer in the fifty-first via hole V51 is etched away to expose the surface of the sixth connection electrode CO6, and the fifty-first via hole V51 is configured to connect the subsequently formed twenty-third connection electrode to the sixth connection electrode CO6 through the via hole.
  • the orthographic projection of the fifty-second via hole V52 on the substrate is located within the range of the orthographic projection of the first end of the seventh connection electrode CO7 on the substrate, the third insulating layer in the fifty-second via hole V52 is etched away to expose the surface of the first end of the seventh connection electrode CO7, and the fifty-second via hole V52 is configured to connect the subsequently formed twentieth connection electrode to the first end of the seventh connection electrode CO7 through the via hole.
  • the orthographic projection of the fifty-third via hole V53 on the substrate is located within the range of the orthographic projection of the second end of the seventh connection electrode CO7 on the substrate, the third insulating layer in the fifty-third via hole V53 is etched away to expose the surface of the second end of the seventh connection electrode CO7, and the fifty-third via hole V53 is configured to connect the subsequently formed nineteenth connection electrode to the second end of the seventh connection electrode CO7 through the via hole.
  • the orthographic projection of the fifty-fourth via hole V54 on the substrate is located within the range of the orthographic projection of the eighth connecting electrode CO8 on the substrate, the third insulating layer in the fifty-fourth via hole V54 is etched away to expose the surface of the eighth connecting electrode CO8, and the fifty-fourth via hole V54 is configured to connect the subsequently formed twenty-first connecting electrode to the eighth connecting electrode CO8 through the via hole.
  • the partial circuit unit may further include a fifty-fifth via hole V55.
  • the orthographic projection of the fifty-fifth via hole V55 on the substrate is located within the range of the orthographic projection of the low-voltage connection line VSS-C on the substrate, the third insulating layer in the fifty-fifth via hole V55 is etched away, exposing the surface of the low-voltage connection line VSS-C, and the fifty-fifth via hole V55 is configured to connect the subsequently formed twenty-seventh connection electrode to the low-voltage connection line VSS-C through the via hole.
  • the partial circuit unit may further include a plurality of connection line vias, which may be provided at both ends of the first anode connection line 11 , and the connection line vias 11 are configured to connect a subsequently formed anode connection block to the first anode connection line 11 through the vias.
  • the first scan signal line S1, the second scan signal line S2 and the light emitting signal line EM located in the blank cell area are further provided with gate line vias (not shown) configured to be connected to corresponding output signal lines formed subsequently.
  • the plurality of vias of each gate driving circuit may include at least a sixty-first via V61 to a ninetieth via V90 .
  • the orthographic projection of the sixty-first via hole V61 on the substrate is within the range of the orthographic projection of the first region of the twenty-first active layer on the substrate, the third insulating layer and the second insulating layer in the sixty-first via hole V61 are etched away to expose the surface of the first region of the twenty-first active layer, and the sixty-first via hole V61 is configured to connect the subsequently formed thirty-first connecting electrode to the first region of the twenty-first active layer through the via hole.
  • the orthographic projection of the sixty-second via hole V62 on the substrate is located within the range of the orthographic projection of the second region of the twenty-first active layer on the substrate, the third insulating layer and the second insulating layer in the sixty-second via hole V62 are etched away to expose the surface of the second region of the twenty-first active layer, and the sixty-second via hole V62 is configured to connect the subsequently formed thirty-second connecting electrode to the second region of the twenty-first active layer through the via hole.
  • the orthographic projection of the sixty-third via hole V63 on the substrate is located within the range of the orthographic projection of the first region of the twenty-second active layer on the substrate, the third insulating layer and the second insulating layer in the sixty-third via hole V63 are etched away to expose the surface of the first region of the twenty-second active layer, and the sixty-third via hole V63 is configured to connect the subsequently formed thirty-third connecting electrode to the first region of the twenty-second active layer through the via hole.
  • the orthographic projection of the sixty-fourth via hole V64 on the substrate is located within the range of the orthographic projection of the second region of the twenty-second active layer on the substrate, the third insulating layer and the second insulating layer in the sixty-fourth via hole V64 are etched away to expose the surface of the second region of the twenty-second active layer, and the sixty-fourth via hole V64 is configured to connect the subsequently formed thirty-fourth connecting electrode to the second region of the twenty-second active layer through the via hole.
  • the orthographic projection of the sixty-fifth via V65 on the substrate is located within the range of the orthographic projection of the first region of the twenty-third active layer on the substrate, the third insulating layer and the second insulating layer within the sixty-fifth via V65 are etched away to expose the surface of the first region of the twenty-third active layer, and the sixty-fifth via V65 is configured to connect a subsequently formed low voltage line to the first region of the twenty-third active layer through the via.
  • the orthographic projection of the sixty-sixth via hole V66 on the substrate is located within the range of the orthographic projection of the second region of the twenty-third active layer on the substrate, the third insulating layer and the second insulating layer in the sixty-sixth via hole V66 are etched away to expose the surface of the second region of the twenty-third active layer, and the sixty-sixth via hole V66 is configured to connect the subsequently formed thirty-fourth connecting electrode to the second region of the twenty-third active layer through the via hole.
  • the orthographic projection of the sixty-seventh via hole V67 on the substrate is located within the range of the orthographic projection of the first region of the twenty-fourth active layer on the substrate, the third insulating layer and the second insulating layer in the sixty-seventh via hole V67 are etched away to expose the surface of the first region of the twenty-fourth active layer, and the sixty-seventh via hole V67 is configured to connect the subsequently formed thirty-seventh connecting electrode to the first region of the twenty-fourth active layer through the via hole.
  • the orthographic projection of the sixty-eight via hole V68 on the substrate is located within the range of the orthographic projection of the second region of the twenty-fourth active layer on the substrate, the third insulating layer and the second insulating layer in the sixty-eight via hole V68 are etched away to expose the surface of the second region of the twenty-fourth active layer, and the sixty-eighth via hole V68 is configured to connect the subsequently formed thirty-eighth connecting electrode to the second region of the twenty-fourth active layer through the via hole.
  • the orthographic projection of the sixty-ninth via hole V69 on the substrate is located within the range of the orthographic projection of the first region of the twenty-fifth active layer on the substrate, the third insulating layer and the second insulating layer in the sixty-ninth via hole V69 are etched away to expose the surface of the first region of the twenty-fifth active layer, and the sixty-ninth via hole V69 is configured to connect the subsequently formed thirty-ninth connecting electrode to the first region of the twenty-fifth active layer through the via hole.
  • the orthographic projection of the seventieth via hole V70 on the substrate is located within the range of the orthographic projection of the second region of the twenty-fifth active layer on the substrate, the third insulating layer and the second insulating layer in the seventieth via hole V70 are etched away to expose the surface of the second region of the twenty-fifth active layer, and the seventieth via hole V70 is configured to connect the subsequently formed thirty-eighth connecting electrode to the second region of the twenty-fifth active layer through the via hole.
  • the orthographic projection of the seventy-first via hole V71 on the substrate is within the range of the orthographic projection of the first region of the twenty-sixth active layer on the substrate, the third insulating layer and the second insulating layer in the seventy-first via hole V71 are etched away to expose the surface of the first region of the twenty-sixth active layer, and the seventy-first via hole V71 is configured to connect the subsequently formed thirty-fifth connecting electrode to the first region of the twenty-sixth active layer through the via hole.
  • the orthographic projection of the seventy-second via hole V72 on the substrate is located within the range of the orthographic projection of the second region of the twenty-sixth active layer on the substrate, the third insulating layer and the second insulating layer in the seventy-second via hole V72 are etched away to expose the surface of the second region of the twenty-sixth active layer, and the seventy-second via hole V72 is configured to connect the subsequently formed thirty-sixth connecting electrode to the second region of the twenty-sixth active layer through the via hole.
  • the orthographic projection of the seventy-third via hole V73 on the substrate is within the range of the orthographic projection of the first region of the twenty-seventh active layer on the substrate, the third insulating layer and the second insulating layer in the seventy-third via hole V73 are etched away, exposing the surface of the first region of the twenty-seventh active layer, and the seventy-third via hole V73 is configured to connect the subsequently formed thirty-sixth connection electrode to the first region of the twenty-seventh active layer through the via hole. Since the second region of the twenty-sixth active layer and the first region of the twenty-seventh active layer are connected to each other, the seventy-second via hole V72 and the seventy-third via hole V73 are shared.
  • the orthographic projection of the seventy-fourth via V74 on the substrate is located within the range of the orthographic projection of the second region of the twenty-seventh active layer on the substrate, the third insulating layer and the second insulating layer in the seventy-fourth via V74 are etched away to expose the surface of the second region of the twenty-seventh active layer, and the seventy-fourth via V74 is configured to connect the subsequently formed thirty-second connecting electrode to the second region of the twenty-seventh active layer through the via.
  • the orthographic projection of the seventy-fifth via hole V75 on the substrate is located within the range of the orthographic projection of the first region of the twenty-eighth active layer on the substrate, the third insulating layer and the second insulating layer in the seventy-fifth via hole V75 are etched away to expose the surface of the first region of the twenty-eighth active layer, and the seventy-fifth via hole V75 is configured to connect the subsequently formed fortieth connecting electrode CO40 to the first region of the twenty-eighth active layer through the via hole.
  • the orthographic projection of the seventy-sixth via V76 on the substrate is located within the range of the orthographic projection of the second region of the twenty-eighth active layer on the substrate, the third insulating layer and the second insulating layer in the seventy-sixth via V76 are etched away to expose the surface of the second region of the twenty-eighth active layer, and the seventy-sixth via V76 is configured to connect the subsequently formed forty-first connecting electrode to the second region of the twenty-eighth active layer through the via.
  • the orthographic projection of the seventy-seventh via V77 on the substrate is located within the range of the orthographic projection of the twenty-second gate electrode Gate22 on the substrate, the third insulating layer in the seventy-seventh via V77 is etched away to expose the surface of the twenty-second gate electrode Gate22, and the seventy-seventh via V77 is configured to connect the subsequently formed fortieth connecting electrode to the twenty-second gate electrode Gate22 through the via.
  • the orthographic projection of the seventy-eight via hole V78 on the substrate is located within the range of the orthographic projection of the twenty-third gate electrode Gate23 on the substrate, the third insulating layer in the seventy-eight via hole V78 is etched away to expose the surface of the twenty-third gate electrode Gate23, and the seventy-eight via hole V78 is configured to connect the subsequently formed thirty-third connecting electrode to the twenty-third gate electrode Gate23 through the via hole.
  • the orthographic projection of the seventy-ninth via V79 on the substrate is located within the range of the orthographic projection of the twenty-fifth gate electrode Gate25 on the substrate, the third insulating layer in the seventy-ninth via V79 is etched away to expose the surface of the twenty-fifth gate electrode Gate25, and the seventy-ninth via V79 is configured to connect the subsequently formed forty-first connecting electrode to the twenty-fifth gate electrode Gate25 through the via.
  • the orthographic projection of the eightieth via V80 on the substrate is located within the range of the orthographic projection of the twenty-sixth gate electrode Gate26 on the substrate, the third insulating layer in the eightieth via V80 is etched away to expose the surface of the twenty-sixth gate electrode Gate26, and the eightieth via V80 is configured to connect the subsequently formed thirty-fourth connecting electrode to the twenty-sixth gate electrode Gate26 through the via.
  • the orthographic projection of the eighty-first via V81 on the substrate is located within the range of the orthographic projection of the twenty-seventh gate electrode Gate27 on the substrate, the third insulating layer in the eighty-first via V81 is etched away to expose the surface of the twenty-seventh gate electrode Gate27, and the eighty-first via V81 is configured to connect the subsequently formed thirty-ninth connecting electrode to the twenty-seventh gate electrode Gate27 through the via.
  • the orthographic projection of the eighty-second via hole V82 on the substrate is located within the range of the orthographic projection of the eleventh electrode plate CF11 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the eighty-second via hole V82 are etched away to expose the surface of the eleventh electrode CF11, and the eighty-second via hole V82 is configured to connect the subsequently formed thirty-eighth connecting electrode to the eleventh electrode CF11 through the via hole.
  • the orthographic projection of the eighty-third via hole V83 on the substrate is located within the range of the orthographic projection of the twelfth electrode plate CF12 on the substrate, and the third insulating layer, the second insulating layer, and the first insulating layer in the eighty-third via hole V83 are etched away to expose the surface of the twelfth electrode plate CF12.
  • the eighty-third via hole V83 can be set at two positions, and the eighty-third via holes V83 at the two positions are configured to respectively connect the subsequently formed thirty-fifth connection electrode and the thirty-seventh connection electrode CO37 to the twelfth electrode plate CF12 through the via hole.
  • the orthographic projection of the eighty-fourth via V84 on the substrate is located within the range of the orthographic projection of the first end of the third gate block GK3 on the substrate, the third insulating layer in the eighty-fourth via V84 is etched away to expose the surface of the first end of the third gate block GK3, and the eighty-fourth via V84 is configured to connect the subsequently formed thirty-fifth connecting electrode to the first end of the third gate block GK3 through the via.
  • the orthographic projection of the eighty-fifth via V85 on the substrate is located within the range of the orthographic projection of the first gate block GK1 on the substrate, the third insulating layer in the eighty-fifth via V85 is etched away to expose the surface of the first gate block GK1, and the eighty-fifth via V85 is configured to connect a subsequently formed first clock signal line to the first gate block GK1 through the via.
  • the orthographic projection of the eighty-sixth via V86 on the substrate is located within the range of the orthographic projection of the second gate block GK2 on the substrate, the third insulating layer in the eighty-sixth via V86 is etched away to expose the surface of the second gate block GK2, and the eighty-sixth via V86 is configured to connect a subsequently formed second clock signal line to the second gate block GK2 through the via.
  • the orthographic projection of the eighty-seventh via V87 on the substrate is located within the range of the orthographic projection of the second end of the third gate block GK3 on the substrate, the third insulating layer in the eighty-seventh via V87 is etched away to expose the surface of the second end of the third gate block GK3, and the eighty-seventh via V87 is configured to connect a subsequently formed high voltage line to the second end of the third gate block GK3 through the via.
  • the orthographic projection of the eighty-eighth via V88 on the substrate is located within the range of the orthographic projection of the fourth gate block GK4 on the substrate, the third insulating layer in the eighty-eighth via V88 is etched away to expose the surface of the fourth gate block GK4, and the eighty-eighth via V88 is configured to connect a subsequently formed low voltage line to the fourth gate block GK4 through the via.
  • the orthographic projection of the eighty-ninth via hole V89 on the substrate is located within the range of the orthographic projection of the previous-level output signal line G(n-1) on the substrate, the third insulating layer in the eighty-ninth via hole V89 is etched away to expose the surface of the previous-level output signal line G(n-1), and the eighty-ninth via hole V89 is configured to connect the subsequently formed thirty-first connecting electrode to the previous-level output signal line G(n-1) through the via hole.
  • the orthographic projection of the ninetieth via hole V90 on the substrate is located within the range of the orthographic projection of the output signal line G(n) of the current stage on the substrate, the third insulating layer in the ninetieth via hole V90 is etched away to expose the surface of the output signal line G(n) of the current stage, and the ninetieth via hole V90 is configured to connect the subsequently formed thirty-eighth connecting electrode to the output signal line G(n) of the current stage through the via hole.
  • forming the third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 25, 26, 27, and 28, wherein FIG. 25 is a structure of region A in FIG. 7, FIG. 26 is an enlarged view of a circuit unit in FIG. 25, FIG. 27 is an enlarged view of a gate driving circuit in FIG. 25, and FIG. 28 is a structure of region B in FIG. 7.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer pattern of each circuit unit includes at least: a data signal line DataI, a high-frequency signal line Hf, a seventh electrode plate CF7, an eighth electrode plate CF8, a ninth electrode plate CF9, an anode connection block 13, and a plurality of connection electrodes.
  • the shape of the data signal line DataI can be a line shape in which the main part extends along the second direction Y, and can be located on the side opposite to the first direction X of the circuit unit.
  • the data signal line DataI is connected to the first area of the fourth active layer through the seventeenth via V17 on the one hand, and is connected to the first area of the eighth active layer through the twenty-fifth via V25 on the other hand. On the other hand, it is connected to the first area of the tenth active layer through the twenty-ninth via V29, thereby realizing that the data signal line DataI writes the data signal into the first electrode of the fourth transistor T4, the first electrode of the eighth transistor T8, and the first electrode of the tenth transistor T10 respectively.
  • the data signal line DataI may be multiplexed as a duration signal line DataT.
  • the data signal line DataI is used to provide a duration signal to the first electrode of the eighth transistor T8 and the first electrode of the tenth transistor T10, respectively.
  • the high-frequency signal line Hf may be shaped as a line having a main portion extending along the second direction Y, and may be located on a side opposite to the first direction X of the data signal line DataI.
  • the high-frequency signal line Hf is connected to the first end of the first connection electrode CO1 through the forty-fourth via hole V44.
  • the high-frequency signal line Hf is connected to the high-frequency connection line Hf-C through the fortieth via hole V40, thereby realizing the connection between the high-frequency connection line Hf-C extending along the first direction X and the high-frequency signal line Hf extending along the second direction Y, thereby forming a mesh connection structure for transmitting high-frequency signals.
  • the shape of the seventh plate CF7 can be rectangular, the orthographic projection of the seventh plate CF7 on the substrate overlaps at least partially with the orthographic projection of the fourth plate CF4 on the substrate, and the seventh plate CF7 is connected to the first plate CF1 through the thirty-third via V33.
  • the seventh plate CF7 can be used as another plate of the first capacitor, and the fourth plate CF4 and the seventh plate CF7 constitute another first capacitor of the pixel driving circuit.
  • the seventh plate CF7 is connected to the first plate CF1 through the via, the first plate CF1 and the seventh plate CF7 have the same initial signal potential, so that the first plate CF1, the fourth plate CF4 and the third plate 97 constitute a first capacitor of a parallel structure, the first plate CF1 and the fourth plate CF4 constitute a first capacitor of the pixel driving circuit, the fourth plate CF4 and the seventh plate CF7 constitute another first capacitor of the pixel driving circuit, and the two first capacitors are connected in parallel.
  • the shape of the eighth plate CF8 can be rectangular, the orthographic projection of the eighth plate CF8 on the substrate overlaps at least partially with the orthographic projection of the fifth plate CF5 on the substrate, and the eighth plate CF8 is connected to the second plate CF2 through the thirty-fourth via V34.
  • the eighth plate CF8 can be used as another plate of the second capacitor, and the fifth plate CF5 and the eighth plate CF8 constitute another second capacitor of the pixel driving circuit.
  • the eighth plate CF8 is connected to the second plate CF2 through the via, the second plate CF2 and the eighth plate CF8 have the same initial signal potential, so that the second plate CF2, the fifth plate CF5 and the eighth plate CF8 constitute a second capacitor of a parallel structure, the second plate CF2 and the fifth plate CF5 constitute a second capacitor of the pixel driving circuit, the fifth plate CF5 and the eighth plate CF8 constitute another second capacitor of the pixel driving circuit, and the two second capacitors are connected in parallel.
  • the shape of the ninth plate CF9 may be rectangular, the orthographic projection of the ninth plate CF9 on the substrate at least partially overlaps the orthographic projection of the sixth plate CF6 on the substrate, and the ninth plate CF9 is connected to the third plate CF3 through the thirty-fifth via hole V35.
  • the ninth plate CF9 may be used as another plate of the storage capacitor, and the sixth plate CF6 and the ninth plate CF9 constitute another storage capacitor of the pixel driving circuit.
  • the ninth plate CF9 is connected to the third plate CF3 through the via hole, the third plate CF3 and the ninth plate CF9 have the same first power supply potential, so that the third plate CF3, the sixth plate CF6 and the ninth plate CF9 constitute a storage capacitor of a parallel structure, the third plate CF3 and the sixth plate CF6 constitute a storage capacitor of the pixel driving circuit, the sixth plate CF6 and the ninth plate CF9 constitute another storage capacitor of the pixel driving circuit, and the two storage capacitors are connected in parallel.
  • the plurality of connection electrodes in each circuit unit may include at least eleventh to twenty-sixth connection electrodes CO11 to CO26 .
  • the shape of the eleventh connection electrode CO11 can be a strip shape extending along the second direction Y, the first end of the eleventh connection electrode CO11 is connected to the first area of the first active layer (also the first area of the seventh active layer) through the eleventh via hole V11, and the second end of the eleventh connection electrode CO11 is connected to the initial signal line Vint through the forty-second via hole V42, thereby realizing that the initial signal line Vint writes the initial signal into the first electrode of the first transistor T1 and the first electrode of the seventh transistor T7 respectively.
  • the eleventh connection electrode CO11 is also connected to the seventh plate CF7. Since the first plate CF1 and the seventh plate CF7 are connected through a via, the initial signal line Vint writes the initial signal into the first plate CF1 and the seventh plate CF7 of the first capacitor.
  • the eleventh connection electrode CO11 and the seventh electrode plate CF7 may be an integral structure connected to each other.
  • the twelfth connection electrode CO12 may be in the shape of a strip extending along the second direction Y, a first end of the twelfth connection electrode CO12 is connected to the initial signal line Vint through a forty-third via hole V43, and a second end of the twelfth connection electrode CO12 is connected to the eighth electrode plate CF8. Since the second electrode plate CF2 and the eighth electrode plate CF8 are connected through the via hole, the initial signal line Vint writes the initial signal into the second electrode plate CF2 and the eighth electrode plate CF8 of the second capacitor.
  • the twelfth connection electrode CO12 and the eighth electrode plate CF8 may be an integral structure connected to each other.
  • the thirteenth connection electrode CO13 may be in the shape of a strip extending along the second direction Y, a first end of the thirteenth connection electrode CO13 is connected to the high-voltage connection line VDD-C through a thirty-ninth via hole V39, and a second end of the thirteenth connection electrode CO13 is connected to the ninth electrode plate CF9. Since the third electrode plate CF3 and the ninth electrode plate CF9 are connected through the via hole, the high-voltage connection line VDD-C is configured to be connected to the high-voltage power line, thereby realizing that the high-voltage power line writes the high-voltage signal to the third electrode plate CF3 and the ninth electrode plate CF9 of the storage capacitor.
  • the thirteenth connection electrode CO13 and the ninth electrode plate CF9 may be an integral structure connected to each other.
  • the shape of the fourteenth connection electrode CO14 can be a zigzag line extending along the second direction Y, the first end of the fourteenth connection electrode CO14 is connected to the second region of the first active layer through the twelfth via hole V12, and the second end of the fourteenth connection electrode CO14 is connected to the sixth electrode plate CF6 through the thirty-eighth via hole V38.
  • the fourteenth connection electrode CO14 enables the second electrode of the first transistor T1 and the sixth electrode plate CF6 to have the same potential.
  • the shape of the fifteenth connection electrode CO15 may be a zigzag shape, the first end of the fifteenth connection electrode CO15 is connected to the first region of the second active layer through the thirteenth via hole V13, the second end of the fifteenth connection electrode CO15 is connected to the fourth connection electrode CO4 through the forty-ninth via hole V49, and the portion between the first end and the second end of the fifteenth connection electrode CO15 is connected to the third bottom gate electrode Gate3-B through the fiftieth via hole V50.
  • the fifteenth connection electrode CO15 not only connects the third top gate electrode Gate3-T and the third bottom gate electrode Gate3-B to each other, but also makes the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the sixth electrode plate CF6 have the same potential.
  • the sixth electrode plate CF6 is connected to the first electrode of the second transistor T2 and the gate electrode of the third transistor T3, and on the other hand, the sixth electrode plate CF6 is connected to the second electrode of the first transistor T1, so that the fourteenth connection electrode CO14 and the fifteenth connection electrode CO15 make the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3 and the sixth electrode plate CF6 have the same potential (i.e., the third node N3 of the pixel driving circuit).
  • the shape of the sixteenth connection electrode CO16 is a zigzag line, the first end of the sixteenth connection electrode CO16 is connected to the second area of the second active layer through the fourteenth via hole V14, the second end of the sixteenth connection electrode CO16 is connected to the second area of the third active layer through the sixteenth via hole V16, and the portion between the first end and the second end of the sixteenth connection electrode CO16 is connected to the first area of the sixth active layer through the twenty-first via hole V21.
  • the sixteenth connection electrode CO16 enables the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential (i.e., the fourth node N4 of the pixel driving circuit).
  • the shape of the seventeenth connection electrode CO17 can be a zigzag shape, the first end of the seventeenth connection electrode CO17 is connected to the first area of the third active layer through the fifteenth via hole V15, the second end of the seventeenth connection electrode CO17 is connected to the second area of the fifth active layer through the twentieth via hole V20, and the portion between the first end and the second end of the seventeenth connection electrode CO17 is connected to the second area of the fourth active layer through the eighteenth via hole V18.
  • the seventeenth connection electrode CO17 enables the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5 to have the same potential (i.e., the fifth node N5 of the pixel driving circuit).
  • the shape of the eighteenth connection electrode CO18 may be a zigzag line, the first end of the eighteenth connection electrode CO18 is connected to the first region of the fifth active layer through the nineteenth via hole V19, the second end of the eighteenth connection electrode CO18 is connected to the ninth electrode plate CF9, and the eighteenth connection electrode CO18 enables the first electrode of the fifth transistor T5 and the ninth electrode plate CF9 to have the same potential.
  • the ninth electrode plate CF9 is connected to the thirteenth connection electrode CO13
  • the thirteenth connection electrode CO13 is connected to the high-voltage connection line VDD-C
  • the high-voltage connection line VDD-C is configured to be connected to the high-voltage power line, thereby realizing that the high-voltage power line writes the high-voltage signal into the first electrode of the fifth transistor T5 of each circuit unit.
  • the eighteenth connection electrode CO18 and the ninth electrode plate CF9 may be an integral structure connected to each other.
  • the nineteenth connection electrode CO19 may be shaped like a strip extending along the second direction Y, a first end of the nineteenth connection electrode CO19 is connected to a second end of the seventh connection electrode CO7 through a fifty-third via hole V53, a second end of the nineteenth connection electrode CO19 is connected to the fourth electrode plate CF4 through a thirty-sixth via hole V36, and the nineteenth connection electrode CO19 enables the gate electrode of the ninth transistor T9 and the fourth electrode plate CF4 to have the same potential.
  • the shape of the twentieth connection electrode CO20 may be a strip shape extending along the first direction X, the first end of the twentieth connection electrode CO20 is connected to the second region of the eighth active layer through the twenty-sixth via hole V26, and the second end of the twentieth connection electrode CO20 is connected to the first end of the seventh connection electrode CO7 through the fifty-second via hole V52. Since the seventh connection electrode CO7 is connected to the ninth gate electrode Gate9, the nineteenth connection electrode CO19 and the twentieth connection electrode CO12 make the second electrode of the eighth transistor T8, the gate electrode of the ninth transistor T9, and the fourth electrode plate CF4 have the same potential (i.e., the sixth node N6 of the pixel driving circuit).
  • the shape of the twenty-first connection electrode CO21 may be a strip shape extending along the second direction Y, the first end of the twenty-first connection electrode CO21 is connected to the eighth connection electrode CO8 through the fifty-fourth via hole V54, the second end of the twenty-first connection electrode CO21 is connected to the fifth electrode plate CF5 through the thirty-seventh via hole V37, and the portion between the first end and the second end of the twenty-first connection electrode CO21 is connected to the second region of the tenth active layer through the thirtieth via hole V30.
  • the twenty-first connection electrode CO21 enables the second electrode of the tenth transistor T10, the gate electrode of the eleventh transistor T11, and the fifth electrode plate CF5 to have the same potential (i.e., the seventh node N7 of the pixel driving circuit).
  • the shape of the twenty-second connection electrode CO22 can be a zigzag line extending along the first direction X, the first end of the twenty-second connection electrode CO22 is connected to the second region of the eleventh active layer through the thirty-second via hole V32, the second end of the twenty-second connection electrode CO22 is connected to the first end of the second connection electrode CO2 through the forty-sixth via hole V46, and the portion between the first end and the second end of the twenty-second connection electrode CO22 is connected to the second region of the ninth active layer through the twenty-eighth via hole V28, and the twenty-second connection electrode CO22 connects the second electrode of the ninth transistor T9 and the second electrode of the eleventh transistor T11 to each other.
  • the shape of the twenty-third connection electrode CO23 may be a strip shape extending along the second direction Y, the first end of the twenty-third connection electrode CO23 is connected to the second end of the second connection electrode CO2 through the forty-seventh via hole V47, and the second end of the twenty-third connection electrode CO23 is connected to the sixth connection electrode CO6 through the fifty-first via hole V51.
  • the twenty-second connection electrode CO22 and the twenty-third connection electrode CO23 are connected through the second connection electrode CO2, and the sixth connection electrode CO6 is connected to the sixth gate electrode Gate6, the twenty-second connection electrode CO22 and the twenty-third connection electrode CO23 make the sixth gate electrode Gate6, the second electrode of the ninth transistor T9, and the second electrode of the eleventh transistor T11 have the same potential (i.e., the first node N1 of the pixel driving circuit).
  • the shape of the twenty-fourth connection electrode CO24 may be an "L" shape
  • the first end of the twenty-fourth connection electrode CO24 is connected to the first region of the eleventh active layer through the thirty-first via hole V31
  • the second end of the twenty-fourth connection electrode CO24 is connected to the second end of the first connection electrode CO1 through the forty-fifth via hole V45. Since the first end of the first connection electrode CO1 is connected to the high-frequency signal line Hf through the via hole, the high-frequency signal line Hf is connected to the first electrode of the eleventh transistor T11, thereby realizing the high-frequency signal being written into the first electrode of the eleventh transistor T11.
  • the shape of the twenty-fifth connection electrode CO25 can be an "L" shape
  • the first end of the twenty-fifth connection electrode CO25 is connected to the first area of the ninth active layer through the twenty-seventh via hole V27
  • the second end of the twenty-fifth connection electrode CO25 is connected to the light emitting signal line EM through the forty-first via hole V41
  • the portion between the first end and the second end of the twenty-fifth connection electrode CO25 is connected to the third connection electrode CO3 through the forty-eighth via hole V48, thereby realizing that the light emitting signal line EM writes the light emitting signal into the first electrode of the ninth transistor T9.
  • the shape of the twenty-sixth connection electrode CO26 can be a strip shape extending along the second direction Y, the first end of the twenty-sixth connection electrode CO26 is connected to the second area of the sixth active layer through the twenty-second via hole V22, and the second end of the twenty-sixth connection electrode CO26 is connected to the second area of the seventh active layer through the twenty-fourth via hole V24, so that the twenty-sixth connection electrode CO26 makes the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 have the same potential (i.e., the second node N2 of the pixel driving circuit).
  • the third conductive layer may further include a twenty-seventh connection electrode CO27.
  • the twenty-seventh connection electrode CO27 may be in a strip shape extending along the second direction Y, the twenty-seventh connection electrode CO27 may be disposed in a portion of the circuit unit, the twenty-seventh connection electrode CO27 is connected to the low voltage connection line VSS-C through the fifty-fifth via hole V55, and the twenty-seventh connection electrode CO27 is configured to be connected to a low voltage power supply line formed subsequently.
  • the partial circuit unit may further include a second anode connection line 12 and an anode connection block 13.
  • the first end of the second anode connection line 12 is configured to be connected to the first anode connection line 11 through a connection line via, and the second end of the second anode connection line 12 is configured to be directly connected to the anode connection block 13.
  • the anode connection blocks 13 of some circuit units are directly connected to the twenty-sixth connection electrode CO26, and the anode connection blocks 13 of some circuit units are connected to the anode connection blocks 13 through the first anode connection line 11 and the second anode connection line 12, so as to realize the connection between the anode connection block 13 and the twenty-sixth connection electrode CO26 in each circuit unit, which is not limited in the present disclosure.
  • the third conductive layer pattern of each gate driving circuit includes at least a first clock signal line CLK, a second clock signal line CLKB, a high voltage line VGH, a low voltage line VG, and a plurality of connection electrodes.
  • the first clock signal line CLK may be in the shape of a line whose main part extends along the second direction Y, and may be located on the side of the fourteenth electrode plate CF14 away from the thirteenth electrode plate CF13, and the first clock signal line CLK is connected to the first gate block GK1 through the eighty-fifth via hole V85. Since the first gate block GK1 is connected to the twenty-first gate electrode Gate21, and the twenty-first gate electrode Gate21 is connected to the twenty-third gate electrode Gate23, the first clock signal line CLK can control the conduction and disconnection of the twenty-first transistor T21 and the twenty-third transistor T23.
  • the second clock signal line CLKB may be in the shape of a line whose main part extends along the second direction Y, and may be located on the side of the first clock signal line CLK away from the fourteenth electrode plate CF14, and the second clock signal line CLKB is connected to the second gate block GK2 through the eighty-sixth via hole V86. Since the second gate block GK2 is connected to the twenty-seventh gate electrode Gate27, the second clock signal line CLKB can control the conduction and disconnection of the twenty-seventh transistor T27.
  • the high voltage line VGH can be shaped like a line with a main portion extending along the second direction Y, and can be located on the side of the second clock signal line CLKB away from the fourteenth plate CF14, and the high voltage line VGH is connected to the second end of the third gate block GK3 through the eighty-seventh via V87.
  • the low voltage line VGL may be in the shape of a line whose main part extends along the second direction Y, and may be located between the thirteenth electrode plate CF13 and the fourteenth electrode plate CF14.
  • the low voltage line VGL is connected to the fourth gate block GK4 through the eighty-eighth via hole V88 on the one hand, and is connected to the first region of the twenty-third active layer through the ninetieth via hole V90 on the other hand. Since the fourth gate block GK4 is connected to the twenty-eighth gate electrode Gate28, the low voltage line VGL can control the conduction and disconnection of the twenty-eighth transistor T28, and write the low voltage signal into the first electrode of the twenty-third transistor T23.
  • an orthographic projection of the gate driving circuit on the plane of the display substrate does not overlap with an orthographic projection of the data signal line DataI on the plane of the display substrate.
  • the data signal line DataI can be arranged in the area where the repeating unit columns are located, so that there is no overlap between the data signal line DataI and the first clock signal line CLK and the second clock signal line CLKB, so that there is no overlap between the data signal line DataI and the first clock signal line CLK and the second clock signal line CLKB, the orthographic projection of the first clock signal line CLK on the display substrate plane does not overlap with the orthographic projection of the data signal line DataI on the display substrate plane, and the orthographic projection of the second clock signal line CLKB on the display substrate plane does not overlap with the orthographic projection of the data signal line DataI on the display substrate plane.
  • the first clock signal line CLK may be substantially parallel to the data signal line DataI
  • the second clock signal line CLKB may be substantially parallel to the data signal line DataI
  • the orthographic projection of the first clock signal line CLK on the display substrate plane may be substantially parallel to the orthographic projection of the data signal line DataI on the display substrate plane
  • the orthographic projection of the second clock signal line CLKB on the display substrate plane may be substantially parallel to the orthographic projection of the data signal line DataI on the display substrate plane.
  • the first clock signal line CLK and the second clock signal line CLKB can be arranged between the high voltage line VGH and the low voltage line VGL, so that the data signal line DataI is located on the side of the high voltage line VGH away from the first clock signal line CLK, and the data signal line DataI is located on the side of the low voltage line VGL away from the second clock signal line CLKB, and the high voltage line VGH and the low voltage line VGL that transmit the constant voltage signal can play a shielding role, effectively reducing the coupling capacitance between the clock signal line and the data signal line.
  • an edge of the high voltage line VGH close to the data signal line DataI has a first distance L from an edge of the data signal line DataI close to the high voltage line VGH, and an edge of the low voltage line VGL close to the data signal line DataI has a second distance L2 from an edge of the data signal line DataI close to the low voltage line VGL, and the second distance L2 may be greater than the first distance L1.
  • the first distance L1 may be greater than or equal to 25 ⁇ m, and the second distance L2 may be greater than or equal to 25 ⁇ m.
  • the first distance L1 may be about 28.5 ⁇ m.
  • a third distance L3 is provided between an edge of the first clock signal line CLK close to the low voltage line VGL and an edge of the low voltage line VGL close to the first clock signal line CLK
  • a fourth distance L4 is provided between an edge of the second clock signal line CLKB close to the high voltage line VGH and an edge of the high voltage line VGH close to the second clock signal line CLKB, and the third distance L3 may be greater than the fourth distance L4.
  • a fifth distance L5 between an edge of the gate driving circuit close to the data signal line DataI and an edge of the data signal line DataI close to the gate driving circuit may be greater than or equal to 50 ⁇ m, for example, the fifth distance L5 may be about 55.5 ⁇ m.
  • the fifth distance L5 may be a dimension in the first direction X.
  • the plurality of connection electrodes of each gate driving circuit may include at least thirty-first to forty-first connection electrodes CO31 to CO41.
  • the shape of the thirty-first connection electrode CO31 can be a strip shape, the first end of the thirty-first connection electrode CO31 is connected to the first area of the twenty-first active layer through the sixty-first via hole V61, and the second end of the thirty-first connection electrode CO31 is connected to the previous-level output signal line G(n-1) through the eighty-ninth via hole V89, so that the previous-level output signal transmitted by the previous-level output signal line G(n-1) can be written into the first electrode of the twenty-first transistor T21.
  • the shape of the thirty-second connection electrode CO32 can be a strip shape, the first end of the thirty-second connection electrode CO32 is connected to the second region of the twenty-first active layer through the sixty-second via hole V62, and the second end of the thirty-second connection electrode CO32 is connected to the second region of the twenty-seventh active layer through the seventy-fourth via hole V74, so that the second electrode of the twenty-first transistor T21 and the second electrode of the twenty-seventh transistor T27 are connected to each other (the eleventh node N11 of the gate driving circuit).
  • the shape of the thirty-third connection electrode CO33 may be a strip shape, a first end of the thirty-third connection electrode CO33 is connected to the first region of the twenty-second active layer through a sixty-third via hole V63, and a second end of the thirty-third connection electrode CO33 is connected to the twenty-third gate electrode Gate23 through a seventy-eight via hole V78. Since the twenty-third gate electrode Gate23 is connected to the first clock signal line CLK, the first clock signal line CLK writes the first clock signal to the first electrode of the twenty-second transistor T22.
  • the shape of the thirty-fourth connection electrode CO34 may be a zigzag line, the first end of the thirty-fourth connection electrode CO34 is connected to the twenty-sixth gate electrode Gate26 through the eightieth via hole V80, the second end of the thirty-fourth connection electrode CO34 is connected to the second region of the twenty-third active layer through the sixty-sixth via hole V66, and the portion between the first end and the second end of the thirty-fourth connection electrode CO34 is connected to the second region of the twenty-second active layer through the sixty-fourth via hole V64.
  • the thirty-fourth connection electrode CO34 enables the second electrode of the twenty-second transistor T22, the second electrode of the twenty-third transistor T23, the gate electrode of the twenty-fourth transistor T24, the gate electrode of the twenty-sixth transistor T26, and the fourteenth electrode plate CF14 to have the same potential (the eleventh node N12 of the gate driving circuit).
  • the shape of the thirty-fifth connection electrode CO35 may be a strip shape, the first end of the thirty-fifth connection electrode CO35 is connected to the first region of the twenty-sixth active layer through the seventy-first via hole V71, the second end of the thirty-fifth connection electrode CO35 is connected to the twelfth electrode plate CF12 through the eighty-third via hole V83 on the one hand, and is connected to the first end of the third gate block GK3 through the eighty-fourth via hole V84 on the other hand.
  • the high voltage line VGH Since the third gate block GK3 is connected to the high voltage line VGH, the high voltage line VGH writes the high voltage signal to the first electrode of the twenty-sixth transistor T26, and the twelfth electrode plate CF12 has the same potential as the high voltage line VGH.
  • the shape of the thirty-sixth connecting electrode CO36 can be rectangular, and the thirty-sixth connecting electrode CO36 is connected to the second area of the twenty-sixth active layer (also the first area of the twenty-seventh active layer) through the seventy-second via hole V72 (also the seventy-third via hole V73), thereby realizing the connection between the second electrode of the twenty-sixth transistor T26 and the first electrode of the twenty-seventh transistor T27 (the thirteenth node N13 of the gate drive circuit).
  • the shape of the thirty-seventh connection electrode CO37 may be a comb shape, and on the one hand, the thirty-seventh connection electrode CO37 is connected to the first region of the twenty-fourth active layer through the sixty-seventh via hole V67, and on the other hand, the thirty-seventh connection electrode CO37 is connected to the twelfth electrode plate CF12 through the eighty-third via hole V83. Since the twelfth electrode plate CF12 is connected to the high voltage line VGH, the high voltage line VGH writes a high voltage signal to the first electrode of the twenty-fourth transistor T24.
  • the shape of the thirty-eighth connection electrode CO38 may be a comb shape.
  • the thirty-eighth connection electrode CO38 is connected to the second region of the twenty-fourth active layer through the sixty-eighth via hole V68.
  • the thirty-eighth connection electrode CO38 is connected to the second region of the twenty-fifth active layer through the seventyth via hole V70.
  • the thirty-eighth connection electrode CO38 is connected to the output signal line G(n) of the current stage through the ninetieth via hole V90.
  • the thirty-eighth connection electrode CO38 is connected to the eleventh electrode plate CF11 through the eighty-second via hole V82, so that the second electrode of the twenty-fourth transistor T24, the second electrode of the twenty-fifth transistor T25 and the eleventh electrode plate CF11 have the same potential.
  • the thirty-eighth connection electrode CO38 may be used as an output line of the current stage. After the end of the thirty-eighth connection electrode CO38 away from the gate drive circuit extends to the first circuit region, it is connected to the second scanning signal line S2 (or the first scanning signal line S1, the light emitting signal line EM) through the gate line via hole.
  • the shape of the thirty-ninth connection electrode CO39 may be a comb shape.
  • the thirty-ninth connection electrode CO39 is connected to the first region of the twenty-fifth active layer through the sixty-ninth via hole V69, and on the other hand, the thirty-ninth connection electrode CO39 is connected to the twenty-seventh gate electrode Gate27 through the eighty-first via hole V81. Since the twenty-seventh gate electrode Gate27 is connected to the second clock signal line CLKB, the second clock signal line CLKB writes the second clock signal to the first electrode of the twenty-fifth transistor T25.
  • the shape of the fortieth connection electrode CO40 can be a strip shape.
  • the fortieth connection electrode CO40 is connected to the first region of the twenty-eighth active layer through the seventy-fifth via hole V75, and on the other hand, the fortieth connection electrode CO40 is connected to the twenty-second gate electrode Gate22 through the seventy-seventh via hole V77, so that the gate electrode of the twenty-second transistor T22 and the first electrode of the twenty-eighth transistor T28 are connected to each other (the eleventh node N11 of the gate driving circuit).
  • the forty-first connection electrode CO41 may be in a strip shape.
  • the forty-first connection electrode CO41 is connected to the second region of the twenty-eighth active layer through the seventy-sixth via hole V76, and on the other hand, the forty-first connection electrode CO41 is connected to the twenty-fifth gate electrode Gate25 through the seventy-ninth via hole V79. Since the twenty-fifth gate electrode Gate25 is connected to the thirteenth electrode plate CF13, the gate electrode of the twenty-fifth transistor T25, the second electrode of the twenty-eighth transistor T28, and the thirteenth electrode plate CF13 have the same potential (the fourteenth node N14 of the gate driving circuit).
  • the third conductive layer pattern of the second circuit area 220 may further include a first mark MARK1, and the first mark MARK1 may be located at one side edge or both side edges of the second circuit area 220 in the first direction X.
  • the first mark MARK1 is configured as a splicing mark, and positioning is performed by the first mark MARK1 when splicing display substrates.
  • the shape of the first mark MARK1 can be a cross, and the setting position of at least one first mark MARK1 in the second circuit area 220 can basically correspond to the setting position of at least one blank cell KB in the first circuit area 210, that is, the first mark MARK1 can be set in the area where the blank column is located, and the positive projection of at least one first mark MARK1 on the reference line O1 at least partially overlaps with the positive projection of at least one blank cell KB on the reference line O1.
  • the data signal line and the high-frequency connection line adjacent to the first mark MARK1 may be provided with a bending section, and the bending section may be bent in a direction away from the first mark MARK1 to leave a corresponding space for the first mark MARK1.
  • the pixel driving circuit and its corresponding signal lines, the gate driving circuit and its corresponding signal lines all avoid the first mark MARK1, the orthographic projection of the first mark MARK1 on the substrate does not overlap with the orthographic projections of the pixel driving circuit and the gate driving circuit on the substrate, and the orthographic projection of the first mark MARK1 on the substrate does not overlap with the orthographic projections of the first scanning signal line, the second scanning signal line, the light-emitting signal line, the high-frequency signal line, the initial signal line, the data signal line, the first clock signal line, the second clock signal line, the high voltage line and the low voltage line on the substrate.
  • forming the fourth insulating layer and the first planar layer pattern may include: first coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process, then depositing a fourth insulating film, patterning the fourth insulating film using a patterning process, forming a first planar layer covering the third conductive layer pattern and a fourth insulating layer disposed on a side of the first planar layer away from the substrate, and a plurality of vias are disposed on the fourth insulating layer and the first planar layer, as shown in FIGS. 29, 30 and 31, wherein FIG. 29 is a structure of region A in FIG. 7, FIG. 30 is an enlarged view of a circuit unit in FIG. 29, and FIG. 31 is a structure of region B in FIG. 7.
  • the plurality of via holes of each circuit unit may include at least a ninety-first via hole V91 .
  • the orthographic projection of the ninety-first via hole V91 on the substrate is within the range of the orthographic projection of the anode connection block 13 on the substrate, the fourth insulating film and the first flat film in the ninety-first via hole V91 are removed to expose the surface of the anode connection block 13, and the ninety-first via hole V91 is configured to connect a subsequently formed anode connection electrode to the anode connection block 13 through the via hole.
  • the partial circuit unit may further include a ninety-second via hole V92.
  • the orthographic projection of the ninety-second via hole V92 on the substrate is located within the range of the orthographic projection of the twenty-seventh connection electrode CO27 on the substrate, the fourth insulating film and the first flat film in the ninety-second via hole V92 are removed, exposing the surface of the twenty-seventh connection electrode CO27, and the ninety-second via hole V92 is configured to connect a subsequently formed low-voltage power line to the twenty-seventh connection electrode CO27 through the via hole.
  • the partial circuit unit may further include a ninety-third via hole V93.
  • the orthographic projection of the ninety-third via hole V93 on the substrate is located within the range of the orthographic projection of the thirteenth connection electrode CO13 on the substrate, the fourth insulating film and the first flat film in the ninety-third via hole V93 are removed, exposing the surface of the thirteenth connection electrode CO13, and the ninety-third via hole V93 is configured to connect a subsequently formed high-voltage power line to the thirteenth connection electrode CO13 through the via hole.
  • no via hole is disposed on the fourth insulating layer and the first planar layer in the region where the gate driving circuit is located.
  • a first mark hole B1 is provided on the first planar layer in the area where the first mark MARK1 is located.
  • a first mark hole B1 is provided in the region where the first mark MARK1 is located, and the first flat layer in the first mark hole B1 is removed to expose the first mark MARK1.
  • the shape of the first mark hole B1 may be rectangular, and the orthographic projection of the first mark hole B1 on the substrate may include the orthographic projection of the first mark MARK1 on the substrate.
  • the region where the first mark hole B1 is located is covered by the fourth insulating layer, so that the fourth insulating layer covers the first mark MARK1, that is, the first mark MARK1 is only covered with the fourth insulating layer (also referred to as the first passivation layer) to protect the first mark MARK1.
  • the fourth insulating layer also referred to as the first passivation layer
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer pattern disposed on the fourth insulating layer, as shown in FIGS. 32 and 33 , where FIG. 32 is a structure of region A in FIG. 7 , and FIG. 33 is a structure of region B in FIG. 7 .
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fourth conductive layer pattern of each circuit unit may include at least an anode connection electrode 14, a high voltage power line VDD, and a low voltage power line VSS, the high voltage power line may be referred to as a first power line, and the low voltage power line may be referred to as a second power line.
  • the shape of the anode connection electrode 14 may be rectangular, and the anode connection electrode 14 is connected to the anode connection block 13 through the ninety-first via hole V91, and the anode connection electrode 14 is configured to be bound and connected to the first electrode of the light emitting diode. Since the anode connection block 13 is connected to the twenty-sixth connection electrode CO26, and the twenty-sixth connection electrode CO26 is respectively connected to the second region of the sixth active layer and the second region of the seventh active layer, the connection between the anode connection electrode 14 and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 is realized, and the pixel driving circuit can drive the light emitting diode to emit light.
  • the high-voltage power line VDD may be in the shape of a line extending along the second direction Y, and the high-voltage power line VDD is connected to the thirteenth connection electrode CO13 through the ninety-third via hole V93 in the partial circuit unit.
  • the high-voltage connection line VDD-C extending along the first direction X and the high-voltage power line VDD extending along the second direction Y form a mesh connection structure, which can not only minimize the resistance of the power transmission line, reduce the voltage drop of the power supply voltage, effectively improve the uniformity of the power supply voltage in the display substrate, effectively improve the uniformity within the signal plane, effectively improve the display uniformity, and improve the display quality and display quality.
  • a portion of the low-voltage power line VSS may be in the shape of a line extending along the second direction Y, and another portion of the low-voltage power line VSS may be in the shape of a "T", and the low-voltage power line VSS is connected to the twenty-seventh connection electrode CO27 through the ninety-second via hole V92.
  • the low-voltage connection line VSS-C extending along the first direction X and the low-voltage power line VSS extending along the second direction Y form a mesh connection structure, which can not only minimize the resistance of the power transmission line, reduce the voltage drop of the power supply voltage, effectively improve the uniformity of the power supply voltage in the display substrate, effectively improve the uniformity within the signal plane, effectively improve the display uniformity, and improve the display quality and display quality.
  • the fourth conductive layer pattern of the second circuit area 220 may further include a second mark MARK2, which may be located at one side edge or both side edges of the second circuit area 220 in the first direction X and located at a side of the first mark MARK1 close to the gate driving circuit.
  • the second mark MARK2 is configured as a binding mark, and positioning is performed by the second mark MARK2 when performing light emitting diode binding connection.
  • the second mark MARK2 may be circular in shape, and the setting position of at least one second mark MARK2 in the second circuit area 220 may substantially correspond to the setting position of at least one blank cell KB in the first circuit area 210, that is, the second mark MARK2 may be set in the area where the blank column is located.
  • the pixel driving circuit and its corresponding signal line, the gate driving circuit and its corresponding signal line all avoid the second mark MARK2, the orthographic projection of the second mark MARK2 on the substrate does not overlap with the orthographic projection of the pixel driving circuit and the gate driving circuit on the substrate, and the orthographic projection of the second mark MARK2 on the substrate does not overlap with the orthographic projection of the first scanning signal line, the second scanning signal line, the light-emitting signal line, the high-frequency signal line, the initial signal line, the data signal line, the first clock signal line, the second clock signal line, the high voltage line and the low voltage line on the substrate.
  • Forming a fifth insulating layer and a second planar layer pattern may include: first depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the fourth conductive layer pattern, then coating a second planar film, patterning the second planar film using a patterning process to form a second planar layer disposed on a side of the fifth insulating layer away from the substrate, and providing a plurality of vias on the fifth insulating layer and the second planar layer, as shown in FIGS. 34 and 35 , where FIG. 34 is the structure of region A in FIG. 7 , and FIG. 35 is the structure of region B in FIG. 7 .
  • a first binding hole K1 and a second binding hole K2 are provided on the fifth insulating layer and the second planar layer in each circuit unit.
  • the shape of the first binding hole K1 can be rectangular, and the orthographic projection of the first binding hole K1 on the substrate is located within the range of the orthographic projection of the anode connecting electrode 14 on the substrate.
  • the second flat film and the fifth insulating film in the first binding hole K1 are removed to expose the surface of the anode connecting electrode 14.
  • the area of the anode connecting electrode 14 exposed by the first binding hole K1 can be used as an anode pad.
  • the first binding hole K1 is configured to enable the first pole of the light-emitting diode to be bound and connected to the anode connecting electrode 14 through the binding hole.
  • the shape of the second binding hole K2 can be rectangular, and the orthographic projection of the second binding hole K2 on the substrate is located within the range of the orthographic projection of the low-voltage power line VSS on the substrate.
  • the second flat film and the fifth insulating film in the second binding hole K2 are removed to expose the surface of the low-voltage power line VSS, and the area of the low-voltage power line VSS exposed by the second binding hole K2 can be used as a cathode pad.
  • the second binding hole K2 is configured to connect the second pole of the light-emitting diode to the low-voltage power line VSS through the binding hole.
  • a second mark hole B2 and a third mark hole B3 are provided on the second planar layer in the area where the first mark MARK1 and the second mark MARK2 are located.
  • the fifth insulating layer covers the second mark MARK2 on one hand, and covers the fourth insulating layer located on the first mark MARK1 on the other hand.
  • the second mark hole B2 is provided in the area where the second mark MARK2 is located
  • the third mark hole B3 is provided in the area where the first mark MARK1 is located. The second flat layer in the second mark MARK2 and the third mark hole B3 is removed, and the fifth insulating layer covering the first mark MARK1 and the second mark MARK2 is exposed respectively.
  • the first mark MARK1 is covered with the fourth insulating layer and the fifth insulating layer, respectively, and the second mark MARK2 is covered with the fifth insulating layer (also called the second passivation layer) to protect the first mark MARK1 and the second mark MARK2.
  • the fifth insulating layer also called the second passivation layer
  • the shape of the second marking hole B2 may be a circle, and the orthographic projection of the second marking hole B2 on the substrate may include the orthographic projection of the second mark MARK2 on the substrate.
  • the shape of the third marking hole B3 may be rectangular, and the orthographic projection of the third marking hole B3 on the substrate may include the orthographic projection of the first mark MARK1 on the substrate.
  • the driving structure layer of this exemplary embodiment is prepared on the substrate.
  • the driving structure layer may include at least a plurality of circuit units, each of which may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a light-emitting signal line, an initial signal line, a high-frequency signal line, a data signal line, and a high-voltage power supply line connected to the pixel driving circuit.
  • the driving structure layer may include at least a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a first flat layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, and a second flat layer sequentially arranged on the substrate.
  • the substrate may be a flexible substrate or a rigid substrate.
  • the rigid substrate may include, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer.
  • the first planar layer and the second planar layer may be made of organic materials, such as resin, etc.
  • the semiconductor layer may be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.
  • the material of the semiconductor layer may be polycrystalline silicon (p-Si).
  • the subsequent preparation process may include: first, using a dispensing machine to add binding materials (such as solder paste) into a plurality of first binding holes and a plurality of second binding holes, and binding and connecting the first poles of a plurality of light-emitting diodes to the anode connection electrode through the first binding holes by a transfer die bonding process, and binding and connecting the second poles of a plurality of light-emitting diodes to the low-voltage power line through the second binding holes, thereby completing the connection between the light-emitting diodes and the corresponding pixel driving circuit.
  • binding materials such as solder paste
  • a covering film is coated on the substrate forming the aforementioned structure to form a covering layer, and the covering layer covers the plurality of light-emitting diodes.
  • the plurality of light-emitting diodes and the covering layer may constitute a light-emitting structure layer.
  • the display substrate provided by the exemplary embodiment of the present disclosure, by setting the first clock signal line and the second clock signal line in the area where the blank column is located, so that the orthographic projection of the first clock signal line and the second clock signal line on the display substrate plane does not overlap with the orthographic projection of the data signal line on the display substrate plane, effectively avoiding the generation of overlapping capacitance between the clock signal line and the data signal line, and the overlapping capacitance between the two signal lines can be basically about 0, effectively avoiding the data voltage jump on the data signal line, and improving the display quality.
  • the exemplary embodiment of the present disclosure sets the high voltage line and the low voltage line on the outside of the first clock signal line and the second clock signal line, which is equivalent to setting a shielding line between the clock signal line and the data signal line, effectively reducing the lateral capacitance between the clock signal line and the data signal line.
  • the clock signal line and the data signal line with a width of 10 ⁇ m and a length of 715 ⁇ m, when the distance between the two signal lines is 5 ⁇ m, the lateral capacitance between the two signal lines is about 2.8fF.
  • the capacitance between the two signal lines is about 3.3*10 -5 fF.
  • the present disclosure not only effectively reduces RC delay and increases charging time by setting the position of the gate drive circuit, but also avoids the routing pads and anti-static circuits on both sides of the display substrate, effectively avoiding mutual interference between the anti-static circuits of the gate drive circuit.
  • the present disclosure adopts a first capacitor, a second capacitor and a storage capacitor in a parallel structure, and minimizes the occupied space of the first capacitor, the second capacitor and the storage capacitor under the premise of ensuring the capacitance, which is conducive to achieving high-resolution display.
  • the present disclosure can minimize the resistance of the power transmission line and reduce the voltage drop of the power supply voltage by forming a high-voltage power line and a low-voltage power line of a network connection structure, effectively improve the uniformity of the power supply voltage in the display substrate, effectively improve the uniformity within the signal surface, effectively improve the display uniformity, and improve the display quality and display quality.
  • the preparation process disclosed in the present disclosure can be well compatible with the existing preparation process, the process is simple to implement, easy to implement, high production efficiency, low production cost, and high yield rate.
  • the display substrate provided by the exemplary embodiments of the present disclosure can be applicable to any LED driving pixel circuit, including P-type PAM, P-type PAM+PWM, N-type PAM, N-type PAM+PWM, and LTPO-type PAM and PAM+PWM circuits.
  • FIG36 is a schematic diagram of another gate drive circuit routing of an exemplary embodiment of the present disclosure.
  • the pixel drive circuit in the circuit unit Q is connected to the data signal line and the drive signal line
  • the gate drive circuit in the gate unit G is connected to the first clock signal line, the second clock signal line, the high voltage line and the low voltage line.
  • the shapes of the first clock signal line CLK, the second clock signal line CLKB, the high voltage line VGH and the low voltage line VGL may be lines extending along the second direction Y
  • the shape of the data signal line DataI may be a line extending along the second direction Y
  • the orthographic projections of the first clock signal line CLK and the second clock signal line CLKB on the display substrate plane do not overlap with the orthographic projection of the data signal line DataI on the display substrate plane
  • the first clock signal line CLK and the second clock signal line CLKB and the data signal line DataI may be substantially parallel.
  • the driving signal lines of a unit row in the first circuit area 210 may include at least a first scan signal line S1, a second scan signal line S2 and a light emitting signal line EM
  • the gate driving circuit in a gate unit G may include at least a first GOA circuit G1, a second GOA circuit G2 and an EOA circuit G3, the first GOA circuit G1 is connected to the first scan signal line S1 through the first output line OUT1, the second GOA circuit G2 is connected to the second scan signal line S2 through the second output line OUT2, and the EOA circuit G3 is connected to the light emitting signal line EM through the third output line OUT3.
  • the first GOA circuit G1, the second GOA circuit G2 and the EOA circuit G3 in one gate unit G may be sequentially arranged along the first direction X, and respectively connected to the first clock signal line CLK through the first clock connection line CK1, and respectively connected to the second clock signal line CLKB through the second clock connection line CK2.
  • orthographic projections of the first GOA circuit G1 , the second GOA circuit G2 , and/or the EOA circuit G3 on the reference line O1 at least partially overlap with an orthographic projection of at least one pixel driving circuit on the reference line O1 .
  • the orthographic projections of the first GOA circuit G1, the second GOA circuit G2 and/or the EOA circuit G3 on the display substrate plane do not overlap with the orthographic projection of the data signal line DataI on the display substrate plane.
  • the orthographic projections of the first GOA circuit G1, the second GOA circuit G2 and/or the EOA circuit G3 on the display substrate plane do not overlap with the orthographic projection of the data signal line DataI on the display substrate plane.
  • the shapes of the first clock connection line CK1 and the second clock connection line CK2 can be line shapes extending along the first direction X, and the orthographic projections of the first clock connection line CK1 and the second clock connection line CK2 on the display substrate plane at least partially overlap with the orthographic projections of the data signal line DataI on the display substrate plane.
  • the first clock connection line CK1 and the second clock connection line CK2 transmit clock signals, there is an overlap capacitance between the clock signal line and the data signal line of the present embodiment. If the voltage variation of the clock signal line is VGH/VGL, the coupling capacitance between the clock signal line and the data signal line is C ck_cp , and the load capacitance of the data signal line is C data , then the voltage jump of the data signal line affected by the coupling of the clock signal line is ⁇ V data ,
  • Vstep is typically about 2 mV to 3 mV
  • the VGH-VGL difference is typically about 20 V
  • the coupling capacitor C ck_cp should be smaller than C data /10 fF.
  • the exemplary embodiments of the present disclosure propose a solution for splitting the gate unit, which is suitable for scenarios where the space of the second circuit area is limited. Although there is an overlapping capacitance between the clock signal line and the data signal line in this solution, as long as the setting requirement of the coupling capacitance Cck_cp is less than Cdata /10fF is met, the data voltage jump on the data signal line can be effectively avoided to ensure the display quality.
  • the exemplary embodiment of the present disclosure also provides a method for preparing a display substrate to prepare the aforementioned display substrate.
  • the display substrate includes a plurality of first circuit areas and a plurality of second circuit areas alternately arranged along a second direction
  • the first circuit area includes a plurality of repeating units and a plurality of blank units alternately arranged along the first direction
  • the repeating unit includes a plurality of circuit units
  • the second circuit area includes at least one gate unit
  • the preparation method may include:
  • a pixel driving circuit and a data signal line and a driving signal line connected to the pixel driving circuit are formed in the circuit unit, and at least one gate driving circuit and a clock signal line connected to the gate driving circuit are formed in the gate unit.
  • the gate driving circuit is connected to the driving signal line in an adjacent circuit unit, and the orthographic projection of the data signal line on the display substrate plane does not overlap with the orthographic projection of the clock signal line on the display substrate plane.
  • the exemplary embodiments of the present disclosure further provide a display device, including the display substrate of the above-mentioned embodiment.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator.

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Abstract

一种显示基板及其制备方法、显示装置。显示基板包括沿着第二方向交替设置的多个第一电路区(210)和多个第二电路区(220)，第一电路区(210)包括沿着第一方向交替设置的多个重复单元(RU)和多个空白单元(KB)，重复单元(RU)包括多个电路单元(Q)，电路单元(Q)包括像素驱动电路以及与像素驱动电路连接的数据信号线(DataI)，第二电路区(220)包括至少一个栅极单元(G)，栅极单元(Q)包括至少一个栅极驱动电路，栅极驱动电路在显示基板平面上的正投影与数据信号线(DataI)在显示基板平面上的正投影没有交叠。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
半导体发光二极管(Light Emitting Diode，LED)技术发展了近三十年，从最初的固态照明电源到显示领域的背光源再到LED显示屏，为其更广泛的应用提供了坚实的基础。其中，随着芯片制作及封装技术的发展，次毫米发光二极管(Mini Light Emitting Diode，Mini LED)显示和微型发光二极管(Micro Light Emitting Diode，Micro LED)显示逐渐成为显示面板的一个热点，可以应用在AR/VR、TV及户外显示等领域。
虽然目前显示市场以液晶显示(Liquid Crystal Display，LCD)和有机发光二极管显示(Organic Light Emitting Diode，OLED)两种技术为主，但受基板尺寸、制备设备和工艺等限制，LCD和OLED均难以实现大尺寸显示，特别是110寸以上的大尺寸显示。相比之下，Micro LED显示/Mini LED显示可以通过拼接方式实现大尺寸显示，能够突破尺寸限制。由于LED具有自发光、广视角、快速响应、结构简单、体积小、轻薄、节能、高效、长寿、光线清晰等优点，更容易实现高分辨率(Pixels Per Inch，PPI)，被认为是最具竞争力的下一代显示技术。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开实施例提供一种显示基板，包括沿着第二方向交替设置的多个第一电路区和多个第二电路区，所述第一电路区包括沿着第一方向交替设置的多个重复单元和多个空白单元，所述第一方向和第二方向交叉；所 述重复单元包括多个电路单元，所述电路单元包括像素驱动电路以及与所述像素驱动电路连接的数据信号线和驱动信号线；所述第二电路区包括至少一个栅极单元，所述栅极单元包括至少一个栅极驱动电路，所述栅极驱动电路与相邻电路单元中的驱动信号线连接，所述栅极驱动电路在显示基板平面上的正投影与所述数据信号线在显示基板平面上的正投影没有交叠。
在示例性实施方式中，至少一个第二电路区具有基准线，所述基准线为在所述第二方向上平分所述第二电路区且沿着所述第一方向延伸的直线；至少一个栅极驱动电路在所述基准线上的正投影与至少一个空白单元在所述基准线上的正投影至少部分交叠。
在示例性实施方式中，至少一个栅极驱动电路还与时钟信号线、高电压线和低电压线连接，在所述第一方向上，所述时钟信号线设置在所述高电压线和所述低电压线之间，所述时钟信号线在显示基板平面上的正投影与所述数据信号线在显示基板平面上的正投影没有交叠。
在示例性实施方式中，在所述第一方向上，所述数据信号线设置在所述高电压线远离所述时钟信号线的一侧，或者，所述数据信号线设置在所述低电压线远离所述时钟信号线的一侧。
在示例性实施方式中，在所述第一方向上，在所述第一方向上，所述高电压线靠近所述数据信号线一侧的边缘与所述数据信号线靠近所述高电压线一侧的边缘之间具有第一距离，所述低电压线靠近所述数据信号线一侧的边缘与所述数据信号线靠近所述低电压线一侧的边缘之间具有第二距离，所述第二距离大于所述第一距离。
在示例性实施方式中，所述第一距离大于或等于25μm，所述第二距离大于或等于25μm。
在示例性实施方式中，所述时钟信号线包括第一时钟信号线和第二时钟信号线，所述第二时钟信号线设置在所述第一时钟信号线远离所述低电压线的一侧；所述第一时钟信号线靠近所述低电压线一侧的边缘与所述低电压线靠近所述第一时钟信号线一侧的边缘之间具有第三距离，所述第二时钟信号线靠近所述高电压线一侧的边缘与所述高电压线靠近所述第二时钟信号线一侧的边缘之间具有第四距离，所述第三距离大于所述第四距离。
在示例性实施方式中，至少一条驱动信号线与一个栅极驱动电路连接，所述栅极驱动电路设置在所述第二电路区的第一中线区，所述栅极驱动电路通过输出线与所述驱动信号线的第一中点区连接；所述第一中线区为包含第一中线的区域，所述第一中点区为包含第一中点的区域，所述第一中线区和所述第一中点区在所述第一方向上的宽度为显示基板宽度的1％至10％，所述第一中线为在所述第一方向上平分所述第二电路区且沿着所述第二方向延伸的直线，所述第一中点为在所述第一方向上平分所述驱动信号线的点，所述显示基板宽度为所述显示基板所述第一方向的尺寸。
在示例性实施方式中，至少一条驱动信号线分别与第一栅极驱动电路和第二栅极驱动电路连接，所述第一栅极驱动电路设置在所述第二电路区的第二中线区，且通过输出线与所述驱动信号线的第二中点区连接，所述第二栅极驱动电路设置在所述第二电路区的第三中线区，且通过输出线与所述驱动信号线的第三中点区连接；所述第二中线区为包含第二中线的区域，所述第三中线区为包含第三中线的区域，所述第二中点区为包含第二中点的区域，所述第三中点区为包含第三中点的区域，所述第二中线区、所述第三中线区、所述第二中点区和所述第三中点区在第一方向X上的宽度为显示基板宽度的1％至10％；所述第二电路区包括在所述第一方向上平分所述第二电路区且沿着所述第二方向延伸的第一中线，所述第一中线将所述第二电路区划分为第一区域和第二区域，所述第二中线为在所述第一方向上平分所述第一区域且沿着所述第二方向延伸的直线，所述第三中线为在所述第一方向上平分所述第二区域且沿着所述第二方向延伸的直线；所述驱动信号线包括在所述第一方向上平分所述驱动信号线的第一中点，所述第一中点将所述驱动信号线划分为第一线段和第二线段，所述第二中点为在所述第一方向上平分所述第一线段的点，所述第三中点为在所述第一方向上平分所述第二线段的点。
在示例性实施方式中，至少一个第二电路区具有基准线，所述基准线为在所述第二方向上平分所述第二电路区且沿着所述第一方向延伸的直线，所述第二电路区所述第二方向两侧的第一电路区中的像素驱动电路相对于所述基准线镜像对称。
在示例性实施方式中，至少一个第二电路区还包括至少一个第一标记， 至少一个第一标记在所述基准线上的正投影与至少一个空白单元在所述基准线上的正投影至少部分交叠。
在示例性实施方式中，至少一个第二电路区还包括至少一个第二标记，至少一个第二标记在所述基准线上的正投影与至少一个空白单元在所述基准线上的正投影至少部分交叠。
在示例性实施方式中，所述第二标记在显示基板平面上的正投影与所述数据信号线、驱动信号线和时钟信号线在显示基板平面上的正投影没有交叠。
在示例性实施方式中，在垂直于显示基板的平面上，所述显示基板包括在基底上依次设置的第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层，所述驱动信号线设置在所述第二栅金属层中，所述数据信号线和所述时钟信号线设置在所述第一源漏金属层中。
在示例性实施方式中，至少一个第二电路区还包括至少一个第一标记和至少一个第二标记，所述第一标记设置在所述第一源漏金属层中，所述第二标记设置在所述第二源漏金属层中。
在示例性实施方式中，所述显示基板还包括第一平坦层和第一钝化层，所述第一平坦层设置在所述第一源漏金属层远离所述基底的一侧，所述第一钝化层设置在所述第一平坦层远离所述基底的一侧，所述第二源漏金属层设置在所述第一钝化层远离所述基底的一侧；所述第一平坦层上设置有暴露出所述第一标记的第一标记孔，所述第一标记孔在所述基底平面上的正投影包含所述第一标记在所述基底平面上的正投影，所述第一钝化层覆盖所述第一标记孔内的第一标记。
在示例性实施方式中，所述显示基板还包括第二钝化层和第二平坦层，所述第二钝化层设置在所述第二源漏金属层远离所述基底的一侧，所述第二平坦层设置在所述第二钝化层远离所述基底的一侧；所述第二平坦层上设置有第二标记孔和第三标记孔，所述第二标记孔暴露出覆盖所述第二标记的第二钝化层，所述第二标记孔在所述基底平面上的正投影包含所述第二标记在所述基底平面上的正投影，所述第三标记孔暴露出覆盖所述第一标记的第二钝化层，所述第三标记孔在所述基底平面上的正投影包含所述第一标记在所述基底平面上的正投影。
另一方面，本公开还提供一种显示装置，包括如上所述的显示基板。
又一方面，本公开还提供一种显示基板的制备方法，包括：所述显示基板包括沿着第二方向交替设置的多个第一电路区和多个第二电路区，所述第一电路区包括沿着第一方向交替设置的多个重复单元和多个空白单元，所述重复单元包括多个电路单元，所述第二电路区包括至少一个栅极单元，所述第一方向和第二方向交叉；所述制备方法包括：
在所述电路单元内形成像素驱动电路以及与所述像素驱动电路连接的数据信号线和驱动信号线，在所述栅极单元形成至少一个栅极驱动电路以及与所述栅极驱动电路连接的时钟信号线，所述栅极驱动电路与相邻电路单元中的驱动信号线连接，所述数据信号线在显示基板平面上的正投影与所述时钟信号线在显示基板平面上的正投影没有交叠。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示装置的结构示意图；
图2为一种显示基板中发光结构层的平面结构示意图；
图3为一种显示基板中驱动结构层的平面结构示意图；
图4为一种像素驱动电路的等效电路图；
图5为一种栅极驱动装置的结构示意图；
图6为一种栅极驱动电路的等效电路图；
图7为本公开示例性实施例一种显示基板的平面结构示意图；
图8为本公开示例性实施例一种栅极驱动电路走线的示意图；
图9为本公开示例性实施例一种栅极单元的排布示意图；
图10为本公开示例性实施例另一种栅极单元的排布示意图；
图11和图12为本公开示例性实施例一种显示基板的平面结构示意图；
图13至图15为本公开显示基板形成第一导电层图案后的示意图；
图16至图18为本公开显示基板形成半导体层图案后的示意图；
图19至图21为本公开显示基板形成第二导电层图案后的示意图；
图22至图24为本公开显示基板形成第三绝缘层图案后的示意图；
图25至图28为本公开显示基板形成第三导电层图案后的示意图；
图29至图31为本公开显示基板形成第一平坦层图案后的示意图；
图32和图33为本公开显示基板形成第四导电层图案后的示意图；
图34和图35为本公开显示基板形成第二平坦层图案后的示意图；
图36为本公开示例性实施例另一种栅极驱动电路走线的示意图。
附图标记说明:
AT1—第一有源层；         AT2—第二有源层；         AT3—第三有源层；
AT4—第四有源层；         AT5—第五有源层；         AT6—第六有源层；
AT7—第七有源层；         AT8—第八有源层；         AT9—第九有源层；
AT10—第十有源层；        AT11—第十一有源层；      AT21—第二十一有源层；
AT22—第二十二有源层；    AT23—第二十三有源层；    AT24—第二十四有源层；
AT25—第二十五有源层；    AT26—第二十六有源层；    AT27—第二十七有源层；
AT28—第二十八有源层；    CF1—第一极板；           CF2—第二极板；
CF3—第三极板；           CF4—第四极板；           CF5—第五极板；
CF6—第六极板；           CF7—第七极板；           CF8—第八极板；
CF9—第九极板；           CF11—第十一极板；        CF12—第十二极板；
CF13—第十三极板；        CF14—第十四极板；        Cs—存储电容；
C1—第一电容；            C2—第二电容；            CT1—第一控制线；
CT2—第二控制线；         CLK—第一时钟信号线；     CLKB—第二时钟信号线；
DataI—数据信号线；       DataT—时长信号线；       EM—发光信号线；
Gate1—第一栅电极；       Gate2—第二栅电极；       Gate3-B—第三底栅电极；
Gate3-T—第三顶栅电极；   Gate4—第四栅电极；       Gate5—第五栅电极；
Gate6—第六栅电极；       Gate7—第七栅电极；       Gate8—第八栅电极；
Gate9—第九栅电极；        Gate10—第十栅电极；       Gate11—第十一栅电极；
Gate21—第二十一栅电极；   Gate22—第二十二栅电极；   Gate23—第二十三栅电极；
Gate24—第二十四栅电极；   Gate25—第二十五栅电极；   Gate26—第二十六栅电极；
Gate27—第二十七栅电极；   Gate28—第二十八栅电极；   Hf—高频信号线；
Hf-C—高频连接线；         MARK1—第一标记；          MARK2—第二标记；
S1—第一扫描信号线；       S2—第二扫描信号线；       VDD—高压电源线；
VDD-C—高压连接线；        VSS—低压电源线；          VSS-C—低压连接线；
Vint—初始信号线；         VGH—高电压线；            VGL—低电压线；
10—基底；                 11—第一阳极连接线；       12—第二阳极连接线；
13—阳极连接块；           14—阳极连接电极；         20—驱动结构层；
30—发光结构层；           40—发光二极管；           100—母板；
200—显示基板；            210—第一电路区；          220—第二电路区。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参 照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本公开中，“厚度”、“高度”，是指膜层远离基底一侧表面至靠近基底一侧表面之间的垂直距离。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图，如图1所示，大尺寸显示装置的主体结构可以包括在母板100上设置的多个显示基板200，多个显示基板200紧密拼接在一起以进行图像显示。在垂直于显示基板的平面上，至少一个显示基板200可以至少包括设置在基底10上的驱动结构层20以及设置在驱动结构层20远离基底一侧的发光结构层30。在平行于显示基板的平面上，驱动结构层20可以包括多个电路单元，至少一个电路单元可以包括像素驱动电路以及与像素驱动电路连接的多条信号线，像素驱动电路被配置为在信号线的控制下接收数据电压，并输出相应的电流。发光结构层30可以包括多个发光单元，至少一个发光单元可以包括发光二极管40，多个发光单元中的发光二极管40与多个电路单元中的像素驱动电路对应连接，发光二极管40被配置为在对应像素驱动电路输出电流的驱动下发出相应亮度的光线。
在示例性实施方式中，本公开中所说的电路单元是指按照像素驱动电路划分的区域，本公开中所说的发光单元是指按照发光二极管划分的区域。在示例性实施方式中，发光单元与电路单元两者的位置可以是对应的，或者，发光单元与电路单元两者的位置可以是不对应的，本公开在此不做限定。
图2为一种显示基板中发光结构层的平面结构示意图。如图2所示，在平行于显示基板的平面内，发光结构层可以包括出射第一颜色光线的第一发光单元P1、出射第二颜色光线的第二发光单元P2和出射第三颜色光线的第三发光单元P3。在示例性实施方式中，第一发光单元P1可以是出射红色光 线的红色发光单元，形成红色(R)子像素，第二发光单元P2可以是出射绿色光线的绿色发光单元，形成绿色(G)子像素，第三发光单元P3可以是出射蓝色光线的蓝色发光单元，形成蓝色(B)子像素。
在示例性实施方式中，红色子像素、蓝色子像素和绿色子像素可以组成一个像素单元P。子像素的形状可以是矩形状、菱形、五边形或六边形，一个像素单元P中三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括四个子像素，四个子像素可以采用水平并列、竖直并列、正方形或钻石形等方式排列。
在示例性实施方式中，发光二极管40可以是次毫米发光二极管Mini LED或者微型发光二极管Micro LED。
图3为一种显示基板中驱动结构层的平面结构示意图，示意了一种栅极驱动电路设置在显示区域(Gate Driver In AA，简称GIA)的结构。如图3所示，在平行于显示基板的平面内，驱动结构层可以至少包括第一电路区210和第二电路区220，第二电路区220的形状可以为沿着第二方向Y延伸的条形状，第二电路区220可以设置在第一电路区210第一方向X的一侧或者第一方向X的反方向的一侧，第一方向X和第二方向Y交叉。
在示例性实施方式中，第一电路区210可以包括形成多个单元行和多个单元列的多个电路单元Q，单元行可以包括沿着第一方向X依次设置的多个电路单元Q，单元列可以包括沿着第二方向Y依次设置的多个电路单元Q。至少一个电路单元Q可以至少包括像素驱动电路，一个单元行中的多个像素驱动电路与该单元行中的驱动信号线连接，像素驱动电路被配置为在驱动信号线的控制下，接收数据电压，向所连接的发光二极管输出相应的电流。
在示例性实施方式中，第二电路区220可以至少包括栅极驱动装置，栅极驱动装置可以至少包括沿着第二方向Y依次设置且级联的多个栅极单元G，至少一个栅极单元G可以包括至少一个栅极驱动电路，栅极驱动电路与对应单元行中的驱动信号线连接，栅极驱动电路被配置为向对应单元行中的驱动信号线输出行驱动信号。
在示例性实施方式中，驱动信号线可以至少包括扫描信号线和发光信号线，栅极单元G可以至少包括第一栅极驱动电路(GOA电路)和第二栅极驱动电路(EOA电路)，第一栅极驱动电路可以与扫描信号线连接，第二栅极驱动电路可以与发光信号线连接。
图4为一种像素驱动电路的等效电路图，示意了一种11T3C的像素驱动电路结构。在示例性实施方式中，显示基板中的多个发光二极管可以采用电流型驱动。由于在较低电流密度驱动下电流型发光二极管会出现色坐标漂移和外量子效率较低的问题，从而导致亮度均一性较差，因而仅通过控制电流的幅值大小难以准确表现低灰阶。一种显示基板采用的像素驱动电路中，像素驱动电路至少包括两类数据端：电流数据端和时长数据端，电流数据端被配置为向发光二极管提供不同幅值大小的电流信号，而时长数据端被配置为向发光二极管提供上述电流信号的时间长度。
如图4所示，像素驱动电路可以至少包括电流控制子电路DK和时长控制子电路SK。电流控制子电路DK可以至少包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和存储电容Cs，时长控制子电路SK可以至少包括第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第一电容C1和第二电容C2。
在示例性实施方式中，像素驱动电路可以至少包括第一节点N1、第二节点N2、第三节点N3、第四节点N4、第五节点N5、第六节点N6和第七节点N7。第一节点N1分别与第六晶体管T6的栅电极、第九晶体管T9的第二极和第十一晶体管T11的第二极连接，第二节点N2分别与第六晶体管T6的第二极、第七晶体管T7的第二极和发光二极管EL的阳极连接，第三节点N3分别与第一晶体管T1的第二极、第二晶体管T2的第一极、第三晶体管T3的栅电极和存储电容Cs的第一端连接，第四节点N4分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接，第五节点N5分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第六节点N6分别与第八晶体管T8的第二极、第九晶体管T9的栅电极和第一电容C1的第一端连接，第七节点N7分别与第 十晶体管T10的第二极、第十一晶体管T11的栅电极和第二电容C2的第一端连接。
在示例性实施方式中，第一晶体管T1的栅电极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线Vint连接，第一晶体管T1的第二极与第三节点N3连接。
在示例性实施方式中，第二晶体管T2的栅电极与第一扫描信号线S1连接，第二晶体管T2的第一极与第三节点N3连接，第二晶体管T2的第二极与第四节点N4连接。
在示例性实施方式中，第三晶体管T3的栅电极与第三节点N3连接，第三晶体管T3的第一极与第五节点N5连接，第三晶体管T3的第二极与第四节点N4连接。
在示例性实施方式中，第四晶体管T4的栅电极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线DataI连接，第四晶体管T4的第二极与第五节点N5连接。
在示例性实施方式中，第五晶体管T5的栅电极与发光信号线EM连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第五节点N5连接。
在示例性实施方式中，第六晶体管T6的栅电极与第一节点N1连接，第六晶体管T6的第一极与第四节点N4连接，第六晶体管T6的第二极与第二节点N2连接。
在示例性实施方式中，第七晶体管T7的栅电极与第二扫描信号线S2连接，第七晶体管T7的第一极与初始信号线Vint连接，第七晶体管T7的第二极与第二节点N2连接。
在示例性实施方式中，第八晶体管T8的栅电极与第一控制线CT1连接，第八晶体管T8的第一极与时长信号线DataT连接，第八晶体管T8的第二极与第六节点N6连接。
在示例性实施方式中，第九晶体管T9的栅电极与第六节点N6连接，第九晶体管T9的第一极与发光信号线EM连接，第九晶体管T9的第二极与第 一节点N1连接。
在示例性实施方式中，第十晶体管T10的栅电极与第二控制线CT2连接，第十晶体管T10的第一极与时长信号线DataT连接，第十晶体管T10的第二极与第七节点N7连接。
在示例性实施方式中，第十一晶体管T11的栅电极与第七节点N7连接，第十一晶体管T11的第一极与高频信号线Hf连接，第十一晶体管T11的第二极与第一节点N1连接。
在示例性实施方式中，存储电容Cs的第一端与第三节点N3连接，存储电容Cs的第二端与第一电源线VDD连接。
在示例性实施方式中，第一电容C1的第一端与第六节点N6连接，第一电容C1的第二端与初始信号线Vint连接。
在示例性实施方式中，第二电容C2的第一端与第七节点N7连接，第二电容C2的第二端与初始信号线Vint连接。
在示例性实施方式中，第一晶体管T1、第二晶体管T2、第四晶体管T4至第十一晶体管T11可以为开关晶体管，第三晶体管T3可以为驱动晶体管。
在示例性实施方式中，发光二极管EL可以是Mini LED或者Micro LED。发光二极管EL的第一极与第二节点N2连接，发光二极管EL的第二极与第二电源线VSS连接，第二电源线VSS的信号为持续提供的低电平信号，如直流低电压。第一电源线VDD的信号为持续提供的高电平信号，如直流高电压。
在示例性实施方式中，第一晶体管T1至第十一晶体管T11可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1至第十一晶体管T11可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1至第十一晶体管T11可以采用低温多晶硅晶体管，或者可以采用氧化物晶体管，或者可以采用低温多晶硅晶体管和金属氧化物晶体管。低温多晶硅晶体管的有源层采用低温多晶硅(Low  Temperature Poly-Silicon，简称LTPS)，金属氧化物晶体管的有源层采用金属氧化物半导体(Oxide)。低温多晶硅晶体管具有迁移率高、充电快等优点，氧化物晶体管具有漏电流低等优点，将低温多晶硅晶体管和金属氧化物晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，以图4所示的像素驱动电路中第一晶体管T1和第十一晶体管T11均为P型晶体管为例，像素驱动电路的工作过程可以包括：
在示例性实施方式中，当像素驱动电路所连接的发光二极管显示的灰阶大于阈值灰阶时，像素驱动电路的工作过程可以包括初始化阶段、写入阶段和发光阶段，初始化阶段可以包括第一子阶段和第二子阶段。
第一子阶段和第二子阶段中，第一扫描信号线S1和发光信号线EM的信号为高电平信号，第二扫描信号线S2的信号为低电平信号，第一晶体管T1和第七晶体管T7导通。第一晶体管T1导通使得初始信号线Vint的信号写入第三节点N3，对存储电容Cs进行初始化(复位)，清除存储电容Cs中原有电荷。由于存储电容C的第一端为低电平，因此第三晶体管T3导通。第七晶体管T7导通使得初始信号线Vint的信号写入第二节点N2，对发光二极管EL的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光二极管EL不发光。
第一子阶段中，时长信号线DataT的信号为高电平信号，第二控制线CT2的信号为低电平信号，第十晶体管T10导通，使得时长信号线DataT的信号写入第七节点N7，并对第二电容C2进行充电。由于此时时长信号线DataT的信号为高电平信号，因而第十一晶体管T11断开，高频信号线Hf的信号无法写入第一节点N1。
第二子阶段中，时长信号线DataT的信号为低电平信号，第一控制线CT1的信号为低电平信号，第八晶体管T8导通，使得时长信号线DataT的信号写入第六节点N6，并对第一电容C1进行充电。由于此时时长信号线DataT的信号为低电平信号，因而第九晶体管T9导通，发光信号线EM的信号写入第一节点N1。
写入阶段，数据信号线DataI输出数据电压，第二扫描信号线S2和发光信号线E的信号为高电平信号，第一扫描信号线S1的信号为低电平信号，第二晶体管T2和第四晶体管T4导通。第二晶体管T2和第四晶体管T4导通使得数据信号线DataI输出的数据电压经过第五节点N5、导通的第三晶体管T3、第四节点N4、导通的第二晶体管T2提供至第三节点N3，并将数据信号线DataI输出的数据电压Vd与第三晶体管T3的阈值电压Vth之差充入存储电容Cs，存储电容Cs的第一端(第三节点N3)的电压为Vd-|Vth|。第一电容C1保持第六节点N6的信号的电位不变，第九晶体管T9保持导通，发光信号线EM的信号写入第一节点N1。
发光阶段，发光信号线EM的信号为低电平信号，第五晶体管T5导通，第一电容C1保持第六节点N6的信号的电位，第九晶体管T9保持导通，发光信号线EM的信号写入第一节点N1，第六晶体管T6导通。第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光二极管EL的第一极提供驱动电压，驱动发光二极管EL发光。
在示例性实施方式中，当像素驱动电路所连接的发光二极管显示的灰阶小于阈值灰阶时，像素驱动电路的工作过程包括：初始化阶段、写入阶段和发光阶段，初始化阶段可以包括第一子阶段和第二子阶段。
第一子阶段和第二子阶段中，第一扫描信号线S1和发光信号线EM的信号为高电平信号，第二扫描信号线S2的信号为低电平信号，第一晶体管T1和第七晶体管T7导通。第一晶体管T1导通使得初始信号线Vint的信号写入第三节点N3，对存储电容Cs进行初始化(复位)，清除存储电容Cs中原有电荷。由于存储电容C的第一端为低电平，因此第三晶体管T3导通。第七晶体管T7导通使得初始信号线Vint的信号写入第二节点N2，对发光二极管EL的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光二极管EL不发光。
第一子阶段中，时长信号线DataT的信号为低电平信号，第二控制线CT2的信号为低电平信号，第十晶体管T10导通，使得时长信号线DataT的信号写入第七节点N7，并对第二电容C2进行充电。由于此时时长信号线DataT的信号为低电平信号，因而第十一晶体管T11导通，高频信号线Hf的信号 写入第一节点N1。
第二子阶段中，时长信号线DataT的信号为高电平信号，第一控制线CT1的信号为低电平信号，第八晶体管T8导通，使得时长信号线DataT的信号写入第六节点N6，并对第一电容C1进行充电。由于此时时长信号线DataT的信号为高电平信号，因而第九晶体管T9断开，发光信号线EM的信号无法写入第一节点N1。
写入阶段，数据信号线DataI输出数据电压，第二扫描信号线S2和发光信号线E的信号为高电平信号，第一扫描信号线S1的信号为低电平信号，第二晶体管T2和第四晶体管T4导通。第二晶体管T2和第四晶体管T4导通使得数据信号线DataI输出的数据电压经过第五节点N5、导通的第三晶体管T3、第四节点N4、导通的第二晶体管T2提供至第三节点N3，并将数据信号线DataI输出的数据电压Vd与第三晶体管T3的阈值电压Vth之差充入存储电容Cs，存储电容Cs的第一端(第三节点N3)的电压为Vd-|Vth|。第二电容C2保持第七节点N7的信号电位不变，第十一晶体管T11始终导通，高频信号线Hf的信号写入第一节点N1。
发光阶段，发光信号线EM的信号为低电平信号，第五晶体管T5导通，第二电容C2保持第七节点N7的信号电位不变，第十一晶体管T11始终导通，高频信号线Hf的信号写入第一节点N1，第六晶体管T6导通。第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光二极管EL的第一极提供驱动电压，驱动发光二极管EL发光。
在示例性实施方式中，在发光阶段，像素驱动电路中第三晶体管T3所输出的驱动电流不受第三晶体管T3的阈值电压的影响，只与数据信号线的电压和第一电源线的电压有关，消除了第三晶体管T3的阈值电压对驱动电流的影响，确保了显示产品的显示亮度均匀，提升了显示效果。
在示例性实施方式中，当像素驱动电路所连接的发光二极管显示的灰阶大于阈值灰阶时，通过发光信号线向第一节点N1提供控制信号，使得发光二极管的灰阶通过驱动电流来控制。当像素驱动电路所连接的发光二极管显示的灰阶小于阈值灰阶时，通过高频信号线向第一节点N1提供控制信号，使得发光二极管的灰阶通过驱动电流和发光时长来控制。
在示例性实施方式中，高频信号线Hf的信号为脉冲信号，在一图像帧内，高频信号线Hf的信号具有多个脉冲。在示例性实施方式中，高频信号线Hf的信号的频率可以大于发光信号线EM的信号的频率。例如，高频信号线Hf的信号的频率可以在3000Hz～60000Hz之间，发光信号线EM的频率可以在60Hz～120Hz之间。本公开通过高频信号线的高频脉冲信号控制发光时长，将短发光时长分散到一帧时间里，减少像素驱动电路所连接的发光二极管显示的灰阶小于阈值灰阶时出现的闪烁，提升了显示产品的显示效果。
图5为一种栅极驱动装置的结构示意图。在示例性实施方式中，栅极驱动装置可以至少包括多个级联的GOA电路(第一栅极驱动电路)。如图5示，多个GOA电路可以包括第一级GOA电路、第二级GOA电路、第三级GOA电路、……第i级GOA电路、……，第一级GOA电路可以根据初始信号线STV提供的初始信号、第一时钟信号线CLK和第二时钟信号线CLKB提供的时钟信号等产生第一单元行中像素驱动电路的扫描信号G(1)。第i级GOA电路可以根据第i-1级GOA电路产生的扫描信号G(i-1)、第i+1级GOA电路产生的扫描信号G(i+1)、第一时钟信号线CLK和第二时钟信号线CLKB提供的时钟信号等产生提供给第i单元行中像素驱动电路的扫描信号G(i)，i为大于1的正整数。
图6为一种栅极驱动电路的等效电路图，示意了一种8T2C的GOA电路结构。如图6所示，在示例性实施方式中，栅极驱动电路可以包括8个晶体管(第二十一晶体管T21到第二十八晶体管T28)和2个电容(第三电容C3和第四电容C4)，栅极驱动电路分别与6条信号线(第一时钟信号线CLK、第二时钟信号线CLKB、高电压线VGH、低电压线VGL、上一级信号输出线G(n-1)和本级信号输出线G(n))连接。
在示例性实施方式中，栅极驱动电路可以至少包括第十一节点N11、第十二节点N12、第十三节点N13和第十四节点N14。第十一节点N11分别与第二十一晶体管T21的第二极、第二十二晶体管T22的栅电极、第二十七晶体管T27的第二极和第二十八晶体管T28的第一极连接。第十二节点N12分别与第二十三晶体管T23的第二极、第二十二晶体管T22的第二极、第二十四晶体管T24的栅电极、第二十六晶体管T26的栅电极和第四电容C4的 第一端连接。第十三节点N13分别与第二十六晶体管T26的第二极和第二十七晶体管T27的第一极连接。第十四节点N14分别与第二十五晶体管T25的栅电极、第二十八晶体管T28的第二极和第三电容C3的第一端连接。
在示例性实施方式中，第二十一晶体管T21的栅电极与第一时钟信号线CLK连接，第二十一晶体管T21的第一极与上一级信号输出线G(n-1)连接，第二十一晶体管T21的第二极与第十一节点N11连接。
在示例性实施方式中，第二十二晶体管T22的栅电极与第十一节点N11连接，第二十二晶体管T22的第一极与第一时钟信号线CLK连接，第二十二晶体管T22的第二极与第十二节点N12连接。
在示例性实施方式中，第二十三晶体管T23的栅电极与第一时钟信号线CLK连接，第二十三晶体管T23的第一极与低电压线VGL连接，第二十三晶体管T23的第二极与第十二节点N12连接。
在示例性实施方式中，第二十四晶体管T24的栅电极与第十二节点N12连接，第二十四晶体管T24的第一极与高电压线VGH连接，第二十四晶体管T24的第二极与本级信号输出线G(n)连接。
在示例性实施方式中，第二十五晶体管T25的栅电极与第十四节点N14连接，第二十五晶体管T25的第一极与第二时钟信号线CLKB连接，第二十五晶体管T25的第二极与本级信号输出线G(n)连接。
在示例性实施方式中，第二十六晶体管T26的栅电极与第十二节点N12连接，第二十六晶体管T26的第一极与高电压线VGH连接，第二十六晶体管T26的第二极与第十三节点N13连接。
在示例性实施方式中，第二十七晶体管T27的栅电极与第二时钟信号线CLKB连接，第二十七晶体管T27的第一极与第十三节点N13连接，第二十七晶体管T27的第二极与第十一节点N11连接。
在示例性实施方式中，第二十八晶体管T28的栅电极与低电压线VGL连接，第二十八晶体管T28的第一极与第十一节点N11连接，第二十八晶体管T28的第二极与第十四节点N14连接。
在示例性实施方式中，第三电容C3的第一端与第十四节点N14连接，第三电容C3的第二端与本级信号输出线G(n)连接。第四电容C4的第一端与第十二节点N12连接，第四电容C4的第二端与高电压线VGH连接。
在示例性实施方式中，在第一时钟信号线CLK的电平为有效电平时，第二时钟信号线CLKB的电平为无效电平，在第二时钟信号线CLKB的电平为有效电平时，第一时钟信号线CLK的电平为无效电平，高电压线VGH持续提供高电平信号，低电压线VGL持续提供低电平信号。
在示例性实施方式中，第一时钟信号线CLK有效电平信号的脉冲持续时间与第二时钟信号线CLKB有效电平信号的脉冲持续时间可以基本上相等。
在示例性实施方式中，第二十一晶体管T21至第二十八晶体管T28可以均为N型薄膜晶体管，或者可以均为P型薄膜晶体管，可以统一工艺流程，能够减少工艺制程，有助于提高产品的良率。考虑到低温多晶硅薄膜晶体管的漏电流较小，第二十一晶体管T21至第二十八晶体管T28可以为低温多晶硅薄膜晶体管，薄膜晶体管可以采用底栅结构或者采用顶栅结构。
本公开示例性实施例提供了一种显示基板。在示例性实施方式中，显示基板包括沿着第二方向交替设置的多个第一电路区和多个第二电路区，所述第一电路区包括沿着第一方向交替设置的多个重复单元和多个空白单元，所述第一方向和第二方向交叉；所述重复单元包括多个电路单元，所述电路单元包括像素驱动电路以及与所述像素驱动电路连接的数据信号线和驱动信号线；所述第二电路区包括至少一个栅极单元，所述栅极单元包括至少一个栅极驱动电路，所述栅极驱动电路与相邻电路单元中的驱动信号线连接，所述栅极驱动电路在显示基板平面上的正投影与所述数据信号线在显示基板平面上的正投影没有交叠。。
在示例性实施方式中，至少一个第二电路区具有基准线，所述基准线为在所述第二方向上平分所述第二电路区且沿着所述第一方向延伸的直线；至少一个栅极驱动电路在所述基准线上的正投影与至少一个空白单元在所述基准线上的正投影至少部分交叠。
在示例性实施方式中，至少一个栅极驱动电路还与时钟信号线、高电压 线和低电压线连接，在所述第一方向上，所述时钟信号线设置在所述高电压线和所述低电压线之间，所述时钟信号线在显示基板平面上的正投影与所述数据信号线在显示基板平面上的正投影没有交叠。
在示例性实施方式中，在所述第一方向上，所述数据信号线设置在所述高电压线远离所述低电压线的一侧，或者，所述数据信号线设置在所述低电压线远离所述高电压线的一侧。
在示例性实施方式中，至少一个第二电路区还包括至少一个第一标记，至少一个第一标记在所述第二电路区的设置位置与至少一个空白单元在所述第一电路区的设置位置相对应。
在示例性实施方式中，至少一个第二电路区还包括至少一个第二标记，至少一个第二标记在所述第二电路区的设置位置与至少一个空白单元在所述第一电路区的设置位置相对应。
在示例性实施方式中，在垂直于显示基板的平面上，所述显示基板包括在基底上依次设置的第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层，所述驱动信号线设置在所述第二栅金属层中，所述数据信号线和所述时钟信号线设置在所述第一源漏金属层中。
在示例性实施方式中，至少一个第二电路区还包括至少一个第一标记和至少一个第二标记，所述第一标记设置在所述第一源漏金属层中，所述第二标记设置在所述第二源漏金属层中。
图7为本公开示例性实施例一种显示基板的平面结构示意图，示意了显示基板中驱动结构层的平面结构。在垂直于显示基板的平面上，显示基板200可以至少包括设置在基底上的驱动结构层以及设置在驱动结构层远离基底一侧的发光结构层。在平行于显示基板的平面上，驱动结构层可以至少包括多个第一电路区210和多个第二电路区220。如图7所示，每个第一电路区210和第二电路区220的形状可以为沿着第一方向X延伸的条形状，多个第一电路区210和多个第二电路区220可以沿着第二方向Y交替设置。在示例性实施方式中，第一电路区可以称为像素电路区，第二电路区可以称为栅极电路区。
在示例性实施方式中，第一电路区210可以包括多个重复单元RU和多个空白单元KB，多个重复单元RU和多个空白单元KB可以沿着第一方向X交替设置。至少一个重复单元RU可以包括m1*m2个电路单元Q，m1可以为重复单元RU包括单元行的数量，m2可以为重复单元RU包括单元列的数量，m1和m2可以大于或等于2的正整数。例如，重复单元RU可以包括2个单元行和3个单元列，重复单元RU形成2*3的电路单元阵列。又如，重复单元RU可以包括2个单元行和6个单元列，重复单元RU形成2*6的电路单元阵列。
在示例性实施方式中，重复单元RU可以是设置有像素驱动电路的区域，空白单元KB可以是没有设置像素驱动电路的区域。在示例性实施方式中，部分空白单元KB可以作为栅极驱动装置的走线区域，以减少信号线之间的干扰。部分空白单元KB可以作为显示基板的透光区域，使得外界光线可以透过显示基板，形成透明显示。在示例性实施方式中，空白单元KB的宽度可以大于重复单元RU内第一方向X相邻的电路单元Q之间的宽度，宽度可以是第一方向X的尺寸。
在示例性实施方式中，至少一个电路单元Q可以至少包括像素驱动电路、沿着第一方向X延伸的驱动信号线以及沿着第二方向Y延伸的数据信号线，像素驱动电路分别与驱动信号线和数据信号线连接，像素驱动电路被配置为在驱动信号线的控制下，接收数据信号线的数据电压，向所连接的发光二极管输出相应的电流。发光结构层可以包括多个发光单元，发光单元可以至少包括发光二极管，多个发光单元中的发光二极管与多个电路单元中的像素驱动电路对应连接，使得发光二极管在对应像素驱动电路输出电流的驱动下发出相应亮度的光线。
在示例性实施方式中，第二电路区220可以包括至少一个栅极单元G，至少一个栅极单元G可以包括栅极驱动电路，栅极驱动电路与相邻第一电路区210中的驱动信号线连接，栅极驱动电路被配置为向所连接的驱动信号线输出行驱动信号。
在示例性实施方式中，至少一个第二电路区220可以具有基准线O1，基准线O1可以为在第二方向Y上平分第二电路区220且沿着第一方向X延伸 的直线。在示例性实施方式中，至少一个栅极驱动电路在第二电路区220中的设置位置与至少一个空白单元KB在第一电路区210中的设置位置可以基本上相对应，至少一个栅极驱动电路在基准线O1上的正投影与至少一个空白单元KB在基准线O1上的正投影至少部分交叠。
在示例性实施方式中，至少一个第二电路区220还可以包括至少一个第一标记MARK1，第一标记MARK1可以位于第二电路区220第一方向X的一侧边缘或者两侧边缘。第一标记MARK1被配置为作为拼接标记，在进行显示基板拼接时通过第一标记MARK1进行定位。
在示例性实施方式中，第一标记MARK1的形状可以为十字形，至少一个第一标记MARK1在第二电路区220的设置位置与至少一个空白单元KB在第一电路区210中的设置位置可以基本上相对应，至少一个第一标记MARK1在基准线O1上的正投影与至少一个空白单元KB在基准线O1上的正投影至少部分交叠。
在示例性实施方式中，至少一个第二电路区220还可以包括至少一个第二标记MARK2，第二标记MARK2可以位于第二电路区220第一方向X的一侧边缘或者两侧边缘，且位于第一标记MARK1靠近栅极单元G的一侧。第二标记MARK2被配置为作为绑定标记，在进行发光二极管绑定连接时通过第二标记MARK2进行定位。
在示例性实施方式中，第二标记MARK2的形状可以为圆形，至少一个第二标记MARK2在第二电路区220的设置位置与至少一个空白单元KB在第一电路区210中的设置位置可以基本上相对应，至少一个第二标记MARK2在基准线O1上的正投影与至少一个空白单元KB在基准线O1上的正投影至少部分交叠。
图8为本公开示例性实施例一种栅极驱动电路走线的示意图。如图8所示，电路单元Q中的像素驱动电路连接有驱动信号线HL和数据信号线DataI。驱动信号线HL的形状可以为沿着第一方向X延伸的线形状，驱动信号线HL被配置为与一个单元行中的多个像素驱动电路连接。数据信号线DataI的形状可以为沿着第二方向Y延伸的线形状，数据信号线DataI被配置为与一个单元列中的多个像素驱动电路连接。栅极单元G中的栅极驱动电路连接 有第一时钟信号线CLK、第二时钟信号线CLKB、高电压线VGH和低电压线VGL，栅极驱动电路通过输出线OUT与相邻单元行中的驱动信号线HL连接。
在示例性实施方式中，第一时钟信号线CLK、第二时钟信号线CLKB、高电压线VGH和低电压线VGL的形状可以为沿着第二方向Y延伸的线形状，且沿着第一方向X依次设置，第一时钟信号线CLK、第二时钟信号线CLKB、高电压线VGH和低电压线VGL被配置为向所连接的栅极驱动电路分别提供第一时钟信号、第二时钟信号、高电压信号和低电压信号，第一时钟信号线CLK和第二时钟信号线CLKB构成本公开的时钟信号线。
在示例性实施方式中，栅极单元G中的栅极驱动电路在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影没有交叠，栅极驱动电路可以包括第二十一晶体管至第二十八晶体管、第三电容和第四电容。
在示例性实施方式中，第一时钟信号线CLK在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影没有交叠，第二时钟信号线CLKB在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影没有交叠。
在示例性实施方式中，第一时钟信号线CLK与数据信号线DataI可以基本上平行，第二时钟信号线CLKB与数据信号线DataI可以基本上平行，或者，第一时钟信号线CLK在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影可以基本上平行，第二时钟信号线CLKB在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影可以基本上平行。
在示例性实施方式中，沿着第二方向Y，多个第一电路区210的重复单元RU可以形成一个沿着第二方向Y延伸的重复单元列，多个第一电路区210的空白单元KB可以形成一个沿着第二方向Y延伸的空白列，数据信号线DataI可以设置在重复单元列所在区域，第一时钟信号线CLK和第二时钟信号线CLKB可以设置在空白列所在区域，使得数据信号线DataI与第一时钟信号线CLK和第二时钟信号线CLKB之间没有交叠。
在示例性实施方式中，沿着第一方向X，第一时钟信号线CLK和第二时 钟信号线CLKB可以设置在高电压线VGH和低电压线VGL之间，使得数据信号线DataI位于高电压线VGH远离第一时钟信号线CLK的一侧，数据信号线DataI位于低电压线VGL远离第二时钟信号线CLKB的一侧，传输恒压信号的高电压线VGH和低电压线VGL可以起到屏蔽作用，有效降低时钟信号线和数据信号线之间的耦合电容。
在示例性实施方式中，高电压线VGH靠近数据信号线DataI一侧的边缘与数据信号线DataI靠近高电压线VGH一侧的边缘具有第一距离L1，低电压线VGL靠近数据信号线DataI一侧的边缘与数据信号线DataI靠近低电压线VGL一侧的边缘之间具有第二距离L2，第二距离L2可以大于第一距离L1，第一距离L1和第二距离L2可以是第一方向X的尺寸。
在示例性实施方式中，第一距离L1可以大于或等于25μm，第二距离L2可以大于或等于25μm。
在示例性实施方式中，第二时钟信号线CLKB可以设置在第一时钟信号线CLK远离低电压线VGL的一侧，即低电压线VGL、第一时钟信号线CLK、第二时钟信号线CLKB和高电压线VGH可以沿着第一方向X依次设置。第一时钟信号线CLK靠近低电压线VGL一侧的边缘与低电压线VGL靠近第一时钟信号线CLK一侧的边缘之间具有第三距离L3，第二时钟信号线CLKB靠近高电压线VGH一侧的边缘与高电压线VGH靠近第二时钟信号线CLKB一侧的边缘之间具有第四距离L4，第三距离L3可以大于第四距离L4，第三距离L3和第四距离L4可以是第一方向X的尺寸。
在示例性实施方式中，至少一个重复单元RU中，相邻的数据信号线DataI之间可以具有第一宽度D1，至少一个空白单元KB可以具有第二宽度D2，第二宽度D2可以大于第一宽度D1，第一宽度D1和第二宽度D2可以是第一方向X的尺寸。
在示例性实施方式中，至少一个栅极单元G中，第一时钟信号线CLK和第二时钟信号线CLKB之间可以具有第三宽度D3，第一宽度D1可以大于第三宽度D3，第三宽度D3可以是第一方向X的尺寸。
图9为本公开示例性实施例一种栅极单元的排布示意图。如图9所示， 在示例性实施方式中，每个栅极电路区可以包括一个栅极单元G，即一个栅极单元G中的栅极驱动电路通过输出线OUT与一个单元行中的驱动信号线HL连接，栅极单元G可以设置在显示基板的中部位置区域。
在示例性实施方式中，一个栅极单元G中的栅极驱动电路通过输出线OUT与一个单元行中的驱动信号线HL连接是指，对于一个单元行中的驱动信号线包括扫描信号线和发光信号线，一个栅极单元G包括GOA电路和EOA电路，一个单元行中的扫描信号线通过扫描输出线与一个GOA电路连接，一个单元行中的发光信号线通过发光输出线与一个EOA电路连接。
在示例性实施方式中，至少一个栅极驱动电路可以设置在第二电路区220的第一中线区，该栅极驱动电路通过输出线OUT与驱动信号线HL的第一中点区连接。其中，第二电路区220可以具有第一中线，驱动信号线HL可以具有第一中点，第一中线可以为在第一方向X上平分第二电路区220且沿着第二方向Y延伸的直线，第一中点可以为在第一方向X上平分驱动信号线HL的点。第一中线区可以为包含第一中线的区域，第一中线区在第一方向X上的宽度可以约为显示基板宽度的1％至10％，第一中点区可以为包含第一中点的区域，第一中线区在第一方向X上的宽度可以约为显示基板宽度的1％至10％，显示基板宽度可以是显示基板第一方向X的尺寸。
研究表明，在栅极单元G设置在显示基板的一侧(如左侧)时，行驱动信号从显示基板的左侧(驱动信号线首端)向显示基板的右侧(驱动信号线末端)传输，行驱动信号的传输距离为L，则驱动信号线末端的RC延迟(delay)为驱动信号线总长度的RC延迟。本公开通过将栅极单元G设置在显示基板的中部区域，行驱动信号从显示基板的中部位置(驱动信号线首端)向显示基板的两侧(驱动信号线末端)传输，行驱动信号的传输距离为L/2，则相对于驱动信号线总长度的RC延迟，本公开驱动信号线末端的RC延迟可以减小一半，因而有效减小了RC延迟，可以增加充电时间。此外，将栅极单元G设置在显示基板的中部区域，可以避开显示基板两侧的走线焊盘和防静电电路，有效避免了栅极驱动电路防静电电路之间的相互干扰。
图10为本公开示例性实施例另一种栅极单元的排布示意图。如图10所示，在示例性实施方式中，每个栅极电路区可以包括两个栅极单元G，即两 个栅极单元G中的栅极驱动电路分别通过输出线OUT同时与一个单元行中的驱动信号线HL连接，两个栅极单元G可以分别设置在显示基板的1/4位置区域和3/4位置区域。
在示例性实施方式中，两个栅极单元G中的栅极驱动电路与一个单元行中的驱动信号线连接是指，一个栅极单元G包括第一栅极驱动电路，另一个栅极单元G包括第二栅极驱动电路，一个单元行中的驱动信号线分别通过输出线与第一栅极驱动电路和第二栅极驱动电路连接。
在示例性实施方式中，第一栅极驱动电路可以设置在第二电路区220的第二中线区，第一栅极驱动电路通过输出线与驱动信号线HL的第二中点区连接，第二栅极驱动电路可以设置在第二电路区220的第三中线区，第二栅极驱动电路通过输出线与驱动信号线HL的第三中点区连接。其中，第二电路区220可以具有在第一方向X上平分第二电路区220且沿着第二方向Y延伸的第一中线，第一中线将第二电路区220划分为第一区域和第二区域，第二中线可以为在第一方向X上平分第一区域且沿着第二方向Y延伸的直线，第三中线可以为在第一方向X上平分第二区域且沿着第二方向Y延伸的直线。第二中线区可以为包含第二中线的区域，第二中线区在第一方向X上的宽度可以约为显示基板宽度的1％至10％，第三中线区可以为包含第三中线的区域，第三中线区在第一方向X上的宽度可以约为显示基板宽度的1％至10％。驱动信号线HL可以具有在第一方向X上平分驱动信号线HL的点，第一中点将驱动信号线HL划分为第一线段和第二线段，第二中点可以为在第一方向X上平分第一线段的点，第三中点可以为在第一方向X上平分第二线段的点。第二中点区可以为包含第二中点的区域，第二中点区在第一方向X上的宽度可以约为显示基板宽度的1％至10％，第三中点区可以为包含第三中点的区域，第三中点区在第一方向X上的宽度可以约为显示基板宽度的1％至10％。
本公开通过将两个栅极单元G设置在显示基板的1/4位置区域和3/4位置区域，行驱动信号的传输距离为L/4，则相对于驱动信号线总长度的RC延迟，驱动信号线末端的RC延迟可以降低到1/4，可以进一步减小RC延迟，可以进一步增加充电时间。
图11和图12为本公开示例性实施例一种显示基板的平面结构示意图，图11示意了图7中A区域的平面结构，图12示意了图7中B区域的平面结构，电路单元包括图4所示的像素驱动电路，栅极单元包括图6所示的栅极驱动电路。如图11和图12所示，第一电路区210可以包括多个重复单元RU和多个空白单元KB，多个重复单元RU和多个空白单元KB可以沿着第一方向X交替设置。第二电路区220可以包括至少一个栅极驱动电路。至少一个重复单元RU包括形成2个单元行和6个单元列的12个电路单元，每个单元行可以包括沿着第一方向X周期性设置的第一电路单元Q1、第二电路单元Q2和第三电路单元Q3，第一电路单元Q1可以至少包括第一像素驱动电路，第二电路单元Q2可以至少包括第二像素驱动电路，第三电路单元Q3可以至少包括第三像素驱动电路，第一像素驱动电路被配置为与红色发光二极管连接，第二像素驱动电路被配置为与绿色发光二极管连接，第三像素驱动电路被配置为与蓝色发光二极管连接。
如图11所示，在示例性实施方式中，至少一个电路单元的像素驱动电路可以至少包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、存储电容Cs、第一电容C1和第二电容C2，像素驱动电路可以分别与第一扫描信号线S1、第二扫描信号线S2、发光信号线EM、初始信号线Vint、数据信号线DataI和高频信号线Hf连接。第一扫描信号线S1、第二扫描信号线S2、发光信号线EM和初始信号线Vint的形状可以为沿着第一方向X延伸的线形状，数据信号线DataI和高频信号线Hf的形状可以为沿着第二方向Y延伸的线形状，像素驱动电路被配置为在第一扫描信号线S1、第二扫描信号线S2、发光信号线EM和高频信号线Hf的控制下，接收数据信号线的数据电压和初始信号线Vint的初始电压，向所连接的发光二极管输出相应时长的相应电流。
在示例性实施方式中，至少一个第二电路区220可以具有基准线O1，基准线O1为在第二方向Y上平分第二电路区220且沿着第一方向X延伸的直线。该第二电路区220第二方向Y两侧的第一电路区210中的像素驱动电路可以相对于基准线O1镜像对称。
在示例性实施方式中，栅极驱动电路可以包括第二十一晶体管T21、第二十二晶体管T22、第二十三晶体管T23、第二十四晶体管T24、第二十五晶体管T25、第二十六晶体管T26、第二十七晶体管T27、第二十八晶体管T28、第三电容C3和第四电容C4，栅极驱动电路可以分别与第一时钟信号线CLK、第二时钟信号线CLKB、高电压线VGH和低电压线VGL连接。在示例性实施方式中，一个栅极单元可以包括第一GOA电路、第二GOA电路和EOA电路，第一GOA电路可以通过输出线与第一扫描信号线S1连接，第二GOA电路可以通过输出线与第二扫描信号线S2连接，EOA电路可以通过输出线与发光信号线EM连接，图12仅示意了第二GOA电路的结构。
在示例性实施方式中，栅极驱动电路的设置位置与至少一个空白单元KB在第一电路区210中的设置位置可以基本上相对应，栅极驱动电路在基准线O1上的正投影与至少一个空白单元KB在基准线O1上的正投影至少部分交叠。
在示例性实施方式中，栅极驱动电路在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影没有交叠。
在示例性实施方式中，第一时钟信号线CLK、第二时钟信号线CLKB、高电压线VGH和低电压线VGL的形状可以为沿着第二方向Y延伸的线形状，且沿着第一方向X依次设置。
在示例性实施方式中，第一时钟信号线CLK和第二时钟信号线CLKB在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影没有交叠。
在示例性实施方式中，第一时钟信号线CLK与数据信号线DataI可以基本上平行，第二时钟信号线CLKB与数据信号线DataI可以基本上平行，或者，第一时钟信号线CLK在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影可以基本上平行，第二时钟信号线CLKB在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影可以基本上平行。
在示例性实施方式中，第一时钟信号线CLK和第二时钟信号线CLKB在显示基板平面上的正投影与栅极驱动电路在显示基板平面上的正投影没有 交叠。
在示例性实施方式中，第一时钟信号线CLK和第二时钟信号线CLKB可以设置在高电压线VGH和低电压线VGL之间，使得传输恒压信号的高电压线VGH和低电压线VGL可以起到屏蔽作用，有效降低时钟信号线和数据信号线之间的耦合电容。
在示例性实施方式中，高电压线VGH靠近数据信号线DataI一侧的边缘与数据信号线DataI靠近高电压线VGH一侧的边缘之间具有第一距离L1，低电压线VGL靠近数据信号线DataI一侧的边缘与数据信号线DataI靠近低电压线VGL一侧的边缘之间具有第二距离L2，第二距离L2可以大于第一距离L1，第一距离L1和第二距离L2可以是第一方向X的尺寸。
在示例性实施方式中，第一距离L1可以大于或等于25μm，第二距离L2可以大于或等于25μm。
在示例性实施方式中，第一时钟信号线CLK靠近低电压线VGL一侧的边缘与低电压线VGL靠近第一时钟信号线CLK一侧的边缘之间具有第三距离L3，第二时钟信号线CLKB靠近高电压线VGH一侧的边缘与高电压线VGH靠近第二时钟信号线CLKB一侧的边缘之间具有第四距离L4，第三距离L3可以大于第四距离L4，第三距离L3和第四距离L4可以是第一方向X的尺寸。
如图12所示，在示例性实施方式中，第二电路区220还可以包括至少一个第一标记MARK1和至少一个第二标记MARK2。第一标记MARK1的形状可以为十字形状，第二标记MARK2的形状可以为圆形状。
在示例性实施方式中，第一标记MARK1在第二电路区220的设置位置与至少一个空白单元KB在第一电路区210中的设置位置可以基本上相对应，至少一个第一标记MARK1在基准线O1上的正投影与至少一个空白单元KB在基准线O1上的正投影至少部分交叠。
在示例性实施方式中，第二标记MARK2在第二电路区220的设置位置与至少一个空白单元KB在第一电路区210中的设置位置可以基本上相对应，至少一个第二标记MARK2在基准线O1上的正投影与至少一个空白单元KB在基准线O1上的正投影至少部分交叠。
在示例性实施方式中，第一标记MARK1和第二标记MARK2在显示基板平面上的正投影与第一扫描信号线S1、第二扫描信号线S2、发光信号线EM、高频信号线Hf、初始信号线Vint、数据信号线DataI、第一时钟信号线CLK、第二时钟信号线CLKB、高电压线VGH和低电压线VGL在显示基板平面上的正投影没有交叠。
在示例性实施方式中，在垂直于显示基板的平面上，显示基板可以包括在基底上依次设置的第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层，多个电容的一个极板可以设置在第一栅金属层中，第一扫描信号线S1、第二扫描信号线S2、发光信号线EM和多个电容的另一个极板可以设置在第二栅金属层中，数据信号线DataI、高频信号线Hf、第一时钟信号线CLK、第二时钟信号线CLKB、高电压线VGH和低电压线VGL可以设置在第一源漏金属层中，第二源漏金属层中可以设置高压电源线和低压电源线。
在示例性实施方式中，第一标记MARK1可以设置在第一源漏金属层中，第二标记MARK2可以设置在第二源漏金属层中。
在本公开中，结构A沿着方向B延伸是指，结构A可以包括主体部分和与主体部分连接的次要部分，主体部分大致呈沿某一个方向延伸的条状，次要部分的形状不限，主体部分至少为结构A的60％的部分；主体部分沿着方向B伸展，且主体部分沿着方向B伸展的尺寸大于沿着其它方向伸展的次要部分的尺寸。以下描述中所说的“结构A沿着方向B延伸”均是指“结构A的主体部分沿着方向B延伸”。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在 整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施方式中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，显示基板的制备过程可以包括如下操作。
(1)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在基底上沉积第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成设置在基底上的第一导电层图案，如图13、图14和图15所示，图13为图7中A区域的结构，图14为图13中一个电路单元的放大图，图15为图13中一个栅极驱动电路的放大图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
如图13和图14所示，在示例性实施方式中，每个电路单元的第一导电层图案可以至少包括：第一极板CF1、第二极板CF2、第三极板CF3和第三底栅电极Gate3-B。
在示例性实施方式中，第一极板CF1、第二极板CF2和第三极板CF3的形状可以为矩形状，矩形状的角部可以设置倒角。在第一方向X上，第一极板CF1可以设置在第二极板CF2第一方向X的一侧，在第二方向Y上，第一极板CF1和第二极板CF2可以设置在电路单元第二方向Y的一侧，第三极板CF3可以设置在电路单元第二方向Y的另一侧。
在示例性实施方式中，第一极板CF1可以作为像素驱动电路中第一电容的一个极板，第二极板CF2可以作为像素驱动电路中第二电容的一个极板，第三极板CF3可以作为像素驱动电路中存储电容的一个极板，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第一极板CF1、第二极板CF2和第三极板CF3的位置、形状和尺寸可以基本上相同。
在示例性实施方式中，第三极板CF3第一方向X的一侧或者第一方向X的反方向的一侧可以连接有板极连接线，板极连接线的形状可以为沿着第一 方向X延伸的条形状，板极连接线的第一端与本电路单元的第三极板CF3连接，板极连接线的第二端沿着第一方向X或者第一方向X的反方向延伸后，与相邻电路单元的第三极板CF3连接，将一个单元行中的第三极板CF3连接起来。
在示例性实施方式中，一个单元行中的多个第三极板CF3和多个板极连接线可以为相互连接的一体结构。在示例性实施方式中，由于每个电路单元中的第三极板CF3与后续形成的高压电源线连接，通过将相邻电路单元的第三极板CF3形成相互连接的一体结构，一体结构的第三极板CF3可以复用为高压电源信号线，可以保证一单元行中的多个第三极板CF3具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第三底栅电极Gate3-B可以作为第三晶体管(驱动晶体管)的底栅电极。第三底栅电极Gate3-B的形状可以为“L”形状，在第二方向Y上，第三底栅电极Gate3-B可以位于第三极板CF3远离第一极板CF1和第二极板CF2的一侧。
在示例性实施方式中，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第三底栅电极Gate3-B的位置、形状和尺寸可以基本上相同。
在示例性实施方式中，位于第二电路区220第二方向Y两侧的第一导电层图案可以相对于基准线镜像对称，基准线可以为在第二方向Y上平分第二电路区220且沿着第一方向X延伸的直线。
如图13和与15所示，在示例性实施方式中，每个栅极驱动电路的第一导电层图案可以至少包括：第十一极板CF11和第十二极板CF12。
在示例性实施方式中，第十一极板CF11和第十二极板CF12形状可以为矩形状，矩形状的角部可以设置倒角。在第一方向X上，第十二极板CF12可以设置在第十一极板CF11第一方向X的一侧。第十一极板CF11可以作为栅极驱动电路中第三电容的一个极板，第十二极板CF12可以作为栅极驱动电路中第四电容的一个极板。
(2)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以 包括：在基底上依次沉积第一绝缘薄膜和第一半导体薄膜，通过图案化工艺对第一半导体薄膜进行图案化，形成覆盖第一导电层的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，如图16、图17和图18所示，图16为图7中A区域的结构，图17为图16中一个电路单元的放大图，图18为图16中一个栅极驱动电路的放大图。
如图16和图17所示，在示例性实施方式中，每个电路单元的半导体层图案可以至少包括：第一有源层AT1至第十一有源层AT11。
在示例性实施方式中，第一有源层AT1可以作为第一晶体管T1的有源层，第二有源层AT2可以作为第二晶体管T2的有源层，第三有源层AT3可以作为第三晶体管T3的有源层，第四有源层AT4可以作为第四晶体管T4的有源层，第五有源层AT5可以作为第五晶体管T5的有源层，第六有源层AT6可以作为第六晶体管T6的有源层，第七有源层AT7可以作为第七晶体管T7的有源层，第八有源层AT8可以作为第八晶体管T8的有源层，第九有源层AT9可以作为第九晶体管T9的有源层，第十有源层AT10可以作为第十晶体管T10的有源层，第十一有源层AT11可以作为第十一晶体管T11的有源层。
在示例性实施方式中，第一有源层AT1、第二有源层AT2、第四有源层AT4、第七有源层AT7、第八有源层AT8、第九有源层AT9和第十有源层AT10的形状可以为沿着第一方向X延伸的条形状，第三有源层AT3、第五有源层AT5、第六有源层AT6和第十一有源层AT11的形状可以为矩形状。
在示例性实施方式中，第二有源层AT2至第六有源层AT6可以位于第三极板CF3远离第一极板CF1的一侧，第一有源层AT1、第七有源层AT7至第十一有源层AT11可以位于第一极板CF1与第三极板CF3之间。
在示例性实施方式中，第三有源层AT3可以位于第三极板CF3远离第一极板CF1的一侧，第三有源层AT3在基底上的正投影与第三底栅电极Gate3-B在基底上的正投影至少部分交叠。第二有源层AT2可以位于第三有源层AT3第一方向X的一侧，第四有源层AT4可以位于第三有源层AT3第一方向X的反方向的一侧。第五有源层AT5和第六有源层AT6可以位于第三极板CF3和第三有源层AT3之间，第六有源层AT6可以位于第五有源层 AT5第一方向X的一侧。
在示例性实施方式中，第十有源层AT10可以位于第一极板CF1靠近第三极板CF3的一侧，第八有源层AT8可以位于第十有源层AT10靠近第三极板CF3的一侧，第十一有源层AT11可以位于第十有源层AT10靠近第三极板CF3的一侧，第一有源层AT1和第七有源层AT7可以位于第八有源层AT8第一方向X的一侧，第一有源层AT1和第七有源层AT7可以为相互连接的一体结构，第九有源层AT9可以位于第十一有源层AT11第一方向X的一侧。
在示例性实施方式中，第一电路单元Q1中第三有源层AT3的宽度可以大于第二电路单元Q2和第三电路单元Q3中第三有源层AT3的宽度，宽度可以为第一方向X的尺寸，以使得第一电路单元Q1中驱动晶体管(第三晶体管T3)的宽长比大于第二电路单元Q2和第三电路单元Q3中驱动晶体管的宽长比。
在示例性实施方式中，第一有源层AT1至第十一有源层AT11可以均包括第一区、第二区以及位于第一区和第二区之间的沟道区，多个有源层的第一区和第二区均可以单独设置，第一有源层AT1的第一区和第七有源层AT7的第一区相互连接。
在示例性实施方式中，位于第二电路区220第二方向Y两侧的半导体层图案可以相对于基准线镜像对称。
如图16和图18所示，在示例性实施方式中，每个栅极驱动电路的半导体层图案可以至少包括：第二十一有源层AT21至第二十八有源层AT28。
在示例性实施方式中，第二十一有源层AT21可以作为第二十一晶体管T21的有源层，第二十二有源层AT22可以作为第二十二晶体管T22的有源层，第二十三有源层AT23可以作为第二十三晶体管T23的有源层，第二十四有源层AT24可以作为第二十四晶体管T24的有源层，第二十五有源层AT25可以作为第二十五晶体管T25的有源层，第二十六有源层AT26可以作为第二十六晶体管T26的有源层，第二十七有源层AT27可以作为第二十七晶体管T27的有源层，第二十八有源层AT28可以作为第二十八晶体管T28的有源层。
在示例性实施方式中，第二十一有源层AT21、第二十二有源层AT22、 第二十三有源层AT23、第二十六有源层AT26、第二十七有源层AT27和第二十八有源层AT28的形状可以为沿着第二方向Y延伸的条形状，第二十四有源层AT24和第二十五有源层AT25的形状可以为多个沿着第二方向Y延伸的条形状的并联结构。
在示例性实施方式中，第二十四有源层AT24可以位于第十一极板CF11第二方向Y的反方向的一侧，第二十五有源层AT25可以位于第十一极板CF11第二方向Y的一侧。第二十六有源层AT26和第二十七有源层AT27可以为相互连接的一体结构，可以位于第十二极板CF12第二方向Y的一侧，第二十一有源层AT21可以位于第二十七有源层AT27第二方向Y的一侧。第二十八有源层AT28可以位于第十一极板CF11第一方向X的一侧，第二十三有源层AT23可以位于第二十八有源层AT28第一方向X的一侧，第二十二有源层AT22可以位于第二十三有源层AT23第一方向X的一侧。
在示例性实施方式中，第二十一有源层AT21至第二十八有源层AT28可以均包括第一区、第二区以及位于第一区和第二区之间的沟道区，多个有源层的第一区和第二区均可以单独设置，第二十六有源层AT26的第二区和第二十七有源层AT27的第一区相互连接。
(3)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖半导体层的第二绝缘层，以及设置在第二绝缘层上的第二导电层图案，如图19、图20和图21，图19为图7中A区域的结构，图20为图19中一个电路单元的放大图，图21为图19中一个栅极驱动电路的放大图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
如图19和图20所示，在示例性实施方式中，每个电路单元的第二导电层图案至少包括：第四极板CF4、第五极板CF5、第六极板CF6、第一扫描信号线S1、第二扫描信号线S2、发光信号线EM、第二控制线CT2、初始信号线Vint、高频连接线Hf-C、高压连接线VDD-C、低压连接线VSS-C、多个栅电极和多个连接电极。
在示例性实施方式中，第四极板CF4、第五极板CF5和第六极板CF6 的形状可以为一个角部设置有缺口的矩形状。第四极板CF4在基底上的正投影与第一极板CF1在基底上的正投影至少部分交叠，第四极板CF4可以作为第一电容的另一个极板，第一极板CF1和第四极板CF4构成像素驱动电路的一个第一电容。第五极板CF5在基底上的正投影与第二极板CF2在基底上的正投影至少部分交叠，第五极板CF5可以作为第二电容的另一个极板，第二极板CF2和第五极板CF5构成像素驱动电路的一个第二电容。第六极板CF6在基底上的正投影与第三极板CF3在基底上的正投影至少部分交叠，第六极板CF6可以作为存储电容的另一个极板，第三极板CF3和第六极板CF6构成像素驱动电路的一个存储电容。
在示例性实施方式中，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第四极板CF4、第五极板CF5和第六极板CF6的位置、形状和尺寸可以基本上相同。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、发光信号线EM、第二控制线CT2、初始信号线Vint、高频连接线Hf-C、高压连接线VDD-C、低压连接线VSS-C的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状。第一扫描信号线S1可以位于第六极板CF6远离第四极板CF4和第五极板CF5的一侧，高频连接线Hf-C和低压连接线VSS-C可以位于第四极板CF4和第五极板CF5远离第六极板CF6的一侧，第二扫描信号线S2、发光信号线EM、第二控制线CT2、初始信号线Vint和高压连接线VDD-C可以位于第四极板CF4和第六极板CF6之间。
在示例性实施方式中，低压连接线VSS-C可以位于第四极板CF4和第五极板CF5远离第六极板CF6的一侧，高频连接线Hf-C可以位于低压连接线VSS-C远离第四极板CF4和第五极板CF5的一侧。
在示例性实施方式中，位于第二电路区220第二方向Y两侧第一电路区210中的一个可以设置有高频连接线Hf-C，另一个第一电路区210可以不设置高频连接线Hf-C。
在示例性实施方式中，位于第二电路区220第二方向Y两侧的的低压连接线VSS-C中的一个可以设置有弯折段，弯折段可以位于空白单元KB所在区域，弯折段向着远离第二电路区220的方向弯折，为栅极驱动电路留出相 应的空间。
在示例性实施方式中，位于第二电路区220第二方向Y两侧的的低压连接线VSS-C中的一个可以设置有多个连接条，多个连接条的第一端与低压连接线VSS-C连接，多个连接条的第二端沿着第二方向Y向着第二电路区220方向延伸。
在示例性实施方式中，初始信号线Vint可以位于第四极板CF4和第五极板CF5靠近第六极板CF6的一侧，第二控制线CT2可以位于初始信号线Vint靠近第六极板CF6的一侧，第二扫描信号线S2可以位于第二控制线CT2靠近第六极板CF6的一侧，高压连接线VDD-C可以位于第二扫描信号线S2靠近第六极板CF6的一侧，发光信号线EM可以位于高压连接线VDD-C靠近第六极板CF6的一侧。
在示例性实施方式中，第二扫描信号线S2可以复用为第一控制线，控制第八晶体管T8的导通和断开。
在示例性实施方式中，高压连接线VDD-C被配置为与后续形成的高压电源线连接，形成网状连通结构。低压连接线VSS-C被配置为与后续形成的低压电源线连接，形成网状连通结构。高频连接线Hf-C被配置为与后续形成的高频信号线连接，形成网状连通结构。
在示例性实施方式中，每个电路单元的多个栅电极可以至少包括第一栅电极Gate1、第二栅电极Gate2、第三顶栅电极Gate3-T、第四栅电极Gate4、第五栅电极Gate5、第六栅电极Gate6、第七栅电极Gate7、第八栅电极Gate8、第九栅电极Gate9、第十栅电极Gate10和第十一栅电极Gate11。
在示例性实施方式中，第二栅电极Gate2和第四栅电极Gate4可以设置在第一扫描信号线S1靠近第六极板CF6的一侧。第二栅电极Gate2作为第二晶体管T2的栅电极，第二栅电极Gate2在基底上的正投影与第二有源层在基底上的正投影至少部分交叠。第四栅电极Gate4作为第四晶体管T4的栅电极，第四栅电极Gate4在基底上的正投影与第四有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第一扫描信号线S1、第二栅电极Gate2和第四栅电极Gate4可以为相互连接的一体结构。
在示例性实施方式中，第一栅电极Gate1、第七栅电极Gate7和第八栅 电极Gate8可以设置在第二扫描信号线S2远离初始信号线Vint的一侧。第一栅电极Gate1作为第一晶体管T1的栅电极，第一栅电极Gate1在基底上的正投影与第一有源层在基底上的正投影至少部分交叠。第七栅电极Gate7作为第七晶体管T7的栅电极，第七栅电极Gate7在基底上的正投影与第七有源层在基底上的正投影至少部分交叠。第八栅电极Gate8作为第八晶体管T8的栅电极，第八栅电极Gate8在基底上的正投影与第八有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第二扫描信号线S2、第一栅电极Gate1、第七栅电极Gate7和第八栅电极Gate8可以为相互连接的一体结构。
在示例性实施方式中，第十栅电极Gate10可以设置在第二控制线CT2靠近初始信号线Vint的一侧。第十栅电极Gate10作为第十晶体管T10的栅电极，第十栅电极Gate10在基底上的正投影与第十有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第二控制线CT2和第十栅电极Gate10可以为相互连接的一体结构。
在示例性实施方式中，第三顶栅电极Gate3-T可以作为第三晶体管T3的顶栅电极，第三顶栅电极Gate3-T在基底上的正投影与第三有源层在基底上的正投影至少部分交叠，第三顶栅电极Gate3-T在基底上的正投影与第三底栅电极Gate3-B在基底上的正投影至少部分交叠。
在示例性实施方式中，第五栅电极Gate5可以作为第五晶体管T5的栅电极，第五栅电极Gate5在基底上的正投影与第五有源层在基底上的正投影至少部分交叠。第五栅电极Gate5可以位于发光信号线EM和第三顶栅电极Gate3-T之间，第五栅电极Gate5的形状可以为梳状。
在示例性实施方式中，第六栅电极Gate6可以作为第六晶体管T6的栅电极，第六栅电极Gate6在基底上的正投影与第六有源层在基底上的正投影至少部分交叠。第六栅电极Gate6可以位于发光信号线EM和第三顶栅电极Gate3-T之间，第六栅电极Gate6的形状可以为梳状。
在示例性实施方式中，第九栅电极Gate9可以作为第九晶体管T9的栅电极，第九栅电极Gate9在基底上的正投影与第九有源层在基底上的正投影至少部分交叠。第九栅电极Gate9可以位于第二扫描信号线S2与高压连接线VDD-C之间，第九栅电极Gate9的形状可以为矩形状。
在示例性实施方式中，第十一栅电极Gate11可以作为第十一晶体管T11的栅电极，第十一栅电极Gate11在基底上的正投影与第十一有源层在基底上的正投影至少部分交叠。第十一栅电极Gate11可以第二扫描信号线S2与高压连接线VDD-C之间，第十一栅电极Gate11的形状可以为条形状。
在示例性实施方式中，每个电路单元的多个连接电极至少包括第一连接电极CO1、第二连接电极CO2、第三连接电极CO3、第四连接电极CO4、第五连接电极CO、第六连接电极CO6、第七连接电极CO7和第八连接电极CO8。
在示例性实施方式中，第一连接电极CO1的形状可以为沿着第一方向X延伸的条形状，可以设置在第二扫描信号线S2和高压连接线VDD-C之间，第一连接电极CO1被配置为与后续形成的高频信号线Hf和第二十四连接电极连接。
在示例性实施方式中，第二连接电极CO2的形状可以为沿着第一方向X延伸的条形状，可以设置在第二扫描信号线S2和高压连接线VDD-C之间，第二连接电极CO2被配置为与后续形成的第二十二连接电极和第二十三连接电极连接。
在示例性实施方式中，第三连接电极CO3的形状可以为矩形状，可以设置在第二连接电极CO2靠近第二扫描信号线S2的一侧，第三连接电极CO3被配置为与后续形成的第二十五连接电极连接。
在示例性实施方式中，第四连接电极CO4的形状可以为沿着第二方向Y延伸的折线状，可以设置在第三顶栅电极Gate3-T靠近第六极板CF6的一侧，第四连接电极CO4的第一端与第三顶栅电极Gate3-T连接，第四连接电极CO4的第二端与第六极板CF6连接。在示例性实施方式中，第三顶栅电极Gate3-T、第六极板CF6和第四连接电极CO4可以为相互连接的一体结构。
在示例性实施方式中，第五连接电极CO5的形状可以为沿着第二方向Y延伸的条形状，可以设置在第五栅电极Gate5靠近发光信号线EM的一侧，第五连接电极CO5的第一端与第五栅电极Gate5连接，第五连接电极CO5的第二端与发光信号线EM连接，因而实现了发光信号线EM可以控制第五晶体管T5的导通或者断开。在示例性实施方式中，发光信号线EM、第五栅 电极Gate5和第五连接电极CO5可以为相互连接的一体结构。
在示例性实施方式中，第六连接电极CO6的形状可以为沿着第二方向Y延伸的条形状，可以设置在第六栅电极Gate6靠近发光信号线EM的一侧，第六连接电极CO6的第一端与第六栅电极Gate6连接，第六连接电极CO6的第二端靠近发光信号线EM，第六连接电极CO6被配置为与后续形成的第二十三连接电极连接。
在示例性实施方式中，第七连接电极CO7的形状可以为沿着第一方向X延伸的条形状，可以设置在第二扫描信号线S2和高压连接线VDD-C之间，第七连接电极CO7和第九栅电极Gate9可以为相互连接的一体结构。
在示例性实施方式中，第八连接电极CO8的形状可以为沿着第一方向X延伸的条形状，可以设置在第二扫描信号线S2和高压连接线VDD-C之间，第八连接电极CO8和第十一栅电极Gate11可以为相互连接的一体结构。
在示例性实施方式中，部分电路单元还可以包括第一阳极连接线11，第一阳极连接线11被配置为与后续形成的阳极连接块连接。
在示例性实施方式中，除了低压连接线VSS-C、高频连接线Hf-C和第一阳极连接线11，位于第二电路区220第二方向Y两侧的第二导电层图案可以相对于基准线基本上镜像对称。
如图19和图21所示，在示例性实施方式中，每个栅极驱动电路的第二导电层图案可以至少包括：第十三极板CF13、第十四极板CF14、上一级输出信号线G(n-1)、本级输出信号线G(n)、多个栅电极和多个栅极块。
在示例性实施方式中，第十三极板CF13和第十四极板CF14的形状可以为矩形状。第十三极板CF13在基底上的正投影与第十一极板CF11在基底上的正投影至少部分交叠，第十三极板CF13可以作为第三电容的另一个极板，第十一极板CF11和第十三极板CF13构成栅极驱动电路的第三电容。第十四极板CF14在基底上的正投影与第十二极板CF12在基底上的正投影至少部分交叠，第十四极板CF14可以作为第四电容的另一个极板，第十二极板CF12和第十四极板CF14构成栅极驱动电路的第四电容。
在示例性实施方式中，上一级输出信号线G(n-1)和本级输出信号线G (n)的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，上一级输出信号线G(n-1)被配置为至少与第n-1行中的第一扫描信号线连接，本级输出信号线G(n)被配置为至少与第n行中的第一扫描信号线连接。在第一方向X上，上一级输出信号线G(n-1)可以位于第十四极板CF14第一方向X的一侧，本级输出信号线G(n)可以位于第十三极板CF13第一方向X的反方向的一侧。在第二方向Y上，上一级输出信号线G(n-1)和本级输出信号线G(n)可以位于第十三极板CF13和第十四极板CF14第二方向Y的一侧。
在示例性实施方式中，栅极驱动电路的多个栅电极可以包括第二十一栅电极Gate21、第二十二栅电极Gate22、第二十三栅电极Gate23、第二十四栅电极Gate24、第二十五栅电极Gate25、第二十六栅电极Gate26、第二十七栅电极Gate27和第二十八栅电极Gate28。
在示例性实施方式中，第二十四栅电极Gate24可以设置在第十四极板CF14第一方向X的反方向的一侧，第二十四栅电极Gate24作为第二十四晶体管T24的栅电极，第二十四栅电极Gate24在基底上的正投影与第二十四有源层在基底上的正投影至少部分交叠。
在示例性实施方式中，第二十四栅电极Gate24可以包括多个子电极，每个子电极的形状可以为沿着第一方向X延伸的条形状，多个子电极可以沿着第二方向Y间隔设置，形成梳状结构，且与第十四极板CF14连接。
在示例性实施方式中，第二十四栅电极Gate24和第十四极板CF14可以为相互连接的一体结构。
在示例性实施方式中，第二十五栅电极Gate25可以设置在第十三极板CF13第二方向Y的一侧，第二十五栅电极Gate25作为第二十五晶体管T25的栅电极，第二十五栅电极Gate25在基底上的正投影与第二十五有源层在基底上的正投影至少部分交叠。
在示例性实施方式中，第二十五栅电极Gate25可以包括多个子电极，每个子电极的形状可以为沿着第一方向X延伸的条形状，多个子电极可以沿着第二方向Y间隔设置，形成梳状结构，且与第十三极板CF13连接。
在示例性实施方式中，第二十五栅电极Gate25和第十三极板CF13可以 为相互连接的一体结构。
在示例性实施方式中，第二十六栅电极Gate26可以设置在第十四极板CF14第二方向Y的一侧，且与第十四极板CF14连接。第二十六栅电极Gate26作为第二十六晶体管T26的栅电极，第二十六栅电极Gate26在基底上的正投影与第二十六有源层在基底上的正投影至少部分交叠。
在示例性实施方式中，第二十四栅电极Gate24、第二十六栅电极Gate26和第十四极板CF14可以为相互连接的一体结构。
在示例性实施方式中，第二十七栅电极Gate27可以设置在第二十六栅电极Gate26第二方向Y的一侧，第二十七栅电极Gate27作为第二十七晶体管T27的栅电极，第二十七栅电极Gate27在基底上的正投影与第二十七有源层在基底上的正投影至少部分交叠。
在示例性实施方式中，第二十二栅电极Gate22可以设置在第二十七栅电极Gate27第二方向Y的一侧，第二十二栅电极Gate22作为第二十二晶体管T22的栅电极，第二十二栅电极Gate22在基底上的正投影与第二十二有源层在基底上的正投影至少部分交叠。
在示例性实施方式中，第二十一栅电极Gate21和第二十三栅电极Gate23可以设置在第二十二栅电极Gate22第二方向Y的一侧，且两者为相互连接的一体结构。第二十一栅电极Gate21作为第二十一晶体管T21的栅电极，第二十一栅电极Gate21在基底上的正投影与第二十一有源层在基底上的正投影至少部分交叠。第二十三栅电极Gate23作为第二十三晶体管T23的栅电极，第二十三栅电极Gate23在基底上的正投影与第二十三有源层在基底上的正投影至少部分交叠。
在示例性实施方式中，第二十八栅电极Gate28可以设置在第二十二栅电极Gate22第二方向Y的一侧，第二十八栅电极Gate28作为第二十八晶体管T28的栅电极，第二十八栅电极Gate28在基底上的正投影与第二十八有源层在基底上的正投影至少部分交叠。
在示例性实施方式中，栅极驱动电路的多个多个栅极块可以包括第一栅极块GK1、第二栅极块GK2、第三栅极块GK3和第四栅极块GK4。
在示例性实施方式中，第一栅极块GK1的形状可以为矩形状，可以设置在第二十一栅电极Gate21第一方向X的一侧，且第一栅极块GK1和第二十一栅电极Gate21为相互连接的一体结构，第一栅极块GK1被配置为与后续形成的第一时钟信号线连接。
在示例性实施方式中，第二栅极块GK2的形状可以为矩形状，可以设置在第二十七栅电极Gate27第一方向X的一侧，且第二栅极块GK2和第二十七栅电极Gate27为相互连接的一体结构，第二栅极块GK2被配置为与后续形成的第二时钟信号线连接。
在示例性实施方式中，第三栅极块GK3的形状可以为沿着第一方向X延伸的条形状，可以设置在第十四极板CF14第一方向X的一侧，第三栅极块GK3被配置为与后续形成的高电压线连接。
在示例性实施方式中，第四栅极块GK4的形状可以为矩形状，可以设置在第二十八栅电极Gate28第一方向X的一侧，且第四栅极块GK4和第二十八栅电极Gate28为相互连接的一体结构，第四栅极块GK4被配置为与后续形成的低电压线连接。
在示例性实施方式中，形成第二导电层图案后，可以利用第二导电层作为遮挡，对半导体层进行导体化处理，被第二导电层遮挡区域的半导体层形成第一晶体管T1至第十一晶体管T11的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一晶体管T1至第十一晶体管T11、第二十一晶体管T2至第二十八晶体管T28的第一区和第二区均被导体化。
(4)形成第三绝缘层图案。在示例性实施方式中，形成第三绝缘层图案可以包括：在形成前述图案的基底上，沉积第三绝缘薄膜，采用图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第二导电层的第三绝缘层，第三绝缘层上设置有多个过孔，如图22、图23和图24所示，图22为图7中A区域的结构，图23为为图22中一个电路单元的放大图，图24为图22中一个栅极驱动电路的放大图。
如图22和图23所示，在示例性实施方式中，每个电路单元的多个过孔至少包括第十一过孔V11至第五十四过孔V54。
在示例性实施方式中，第十一过孔V11在基底上的正投影位于第一有源 层的第一区在基底上的正投影的范围之内，第十一过孔V11内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面，第十一过孔V11被配置为使后续形成的第十一连接电极通过该过孔与第一有源层的第一区连接。
在示例性实施方式中，第十二过孔V12在基底上的正投影位于第一有源层的第二区在基底上的正投影的范围之内，第十二过孔V12内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第二区的表面，第十二过孔V12被配置为使后续形成的第十四连接电极通过该过孔与第一有源层的第二区连接。
在示例性实施方式中，第十三过孔V13在基底上的正投影位于第二有源层的第一区在基底上的正投影的范围之内，第十三过孔V13内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层的第一区的表面，第十三过孔V13被配置为使后续形成的第十五连接电极通过该过孔与第二有源层的第一区连接。由于
在示例性实施方式中，第十四过孔V14在基底上的正投影位于第二有源层的第二区在基底上的正投影的范围之内，第十四过孔V14内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层的第二区的表面，第十四过孔V14被配置为使后续形成的第十六连接电极通过该过孔与第二有源层的第二区连接。
在示例性实施方式中，第十五过孔V15在基底上的正投影位于第三有源层的第一区在基底上的正投影的范围之内，第十五过孔V15内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第三有源层的第一区的表面，第十五过孔V15被配置为使后续形成的第十七连接电极通过该过孔与第三有源层的第一区连接。
在示例性实施方式中，第十六过孔V16在基底上的正投影位于第三有源层的第二区在基底上的正投影的范围之内，第十六过孔V16内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第三有源层的第二区的表面，第十六过孔V16被配置为使后续形成的第十六连接电极通过该过孔与第三有源层的第二区连接。
在示例性实施方式中，第十七过孔V17在基底上的正投影位于第四有源层的第一区在基底上的正投影的范围之内，第十七过孔V17内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面，第十七过孔V17被配置为使后续形成的数据信号线通过该过孔与第四有源层的第一区连接。
在示例性实施方式中，第十八过孔V18在基底上的正投影位于第四有源层的第二区在基底上的正投影的范围之内，第十八过孔V18内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第二区的表面，第十八过孔V18被配置为使后续形成的第十七连接电极通过该过孔与第四有源层的第二区连接。
在示例性实施方式中，第十九过孔V19在基底上的正投影位于第五有源层的第一区在基底上的正投影的范围之内，第十九过孔V19内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面，第十九过孔V19被配置为使后续形成的第十八连接电极通过该过孔与第五有源层的第一区连接。
在示例性实施方式中，第二十过孔V20在基底上的正投影位于第五有源层的第二区在基底上的正投影的范围之内，第二十过孔V20内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第二区的表面，第二十过孔V20被配置为使后续形成的第十七连接电极通过该过孔与第五有源层的第二区连接。
在示例性实施方式中，第十九过孔V19和第二十过孔V20均为多个，多个第十九过孔V19和多个第二十过孔V20在第二方向Y上交替设置。
在示例性实施方式中，第二十一过孔V21在基底上的正投影位于第六有源层的第一区在基底上的正投影的范围之内，第二十一过孔V21内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第一区的表面，第二十一过孔V21被配置为使后续形成的第十六连接电极通过该过孔与第六有源层的第一区连接。
在示例性实施方式中，第二十二过孔V22在基底上的正投影位于第六有源层的第二区在基底上的正投影的范围之内，第二十二过孔V22内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区的表面，第二十二 过孔V22被配置为使后续形成的第二十六连接电极通过该过孔与第六有源层的第二区连接。
在示例性实施方式中，第二十一过孔V21和第二十二过孔V22均为多个，多个第二十一过孔V21和多个第二十二过孔V22在第二方向Y上交替设置。
在示例性实施方式中，第二十三过孔V23在基底上的正投影位于第七有源层的第一区在基底上的正投影的范围之内，第二十三过孔V23内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第七区的表面，第二十三过孔V23被配置为使后续形成的第十一连接电极通过该过孔与第七有源层的第一区连接。由于第一有源层的第一区与第七有源层的第一区相互连接，因而第十一过孔V11和第二十三过孔V23为共用的过孔。
在示例性实施方式中，第二十四过孔V24在基底上的正投影位于第七有源层的第二区在基底上的正投影的范围之内，第二十四过孔V24内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第二区的表面，第二十四过孔V24被配置为使后续形成的第二十六连接电极通过该过孔与第七有源层的第二区连接。
在示例性实施方式中，第二十五过孔V25在基底上的正投影位于第八有源层的第一区在基底上的正投影的范围之内，第二十五过孔V25内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第八有源层的第九区的表面，第二十五过孔V25被配置为使后续形成的数据信号线通过该过孔与第八有源层的第一区连接。
在示例性实施方式中，第二十六过孔V26在基底上的正投影位于第八有源层的第二区在基底上的正投影的范围之内，第二十六过孔V26内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第八有源层的第二区的表面，第二十六过孔V26被配置为使后续形成的第二十连接电极通过该过孔与第八有源层的第二区连接。
在示例性实施方式中，第二十七过孔V27在基底上的正投影位于第九有源层的第一区在基底上的正投影的范围之内，第二十七过孔V27内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第九有源层的第一区的表面，第二十七过孔V27被配置为使后续形成的第二十五连接电极通过该过孔与第九有源层 的第一区连接。
在示例性实施方式中，第二十八过孔V28在基底上的正投影位于第九有源层的第二区在基底上的正投影的范围之内，第二十八过孔V28内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第九有源层的第二区的表面，第二十八过孔V28被配置为使后续形成的第二十二连接电极通过该过孔与第九有源层的第二区连接。
在示例性实施方式中，第二十九过孔V29在基底上的正投影位于第十有源层的第一区在基底上的正投影的范围之内，第二十九过孔V29内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第十有源层的第一区的表面，第二十九过孔V29被配置为使后续形成的数据信号线通过该过孔与第十有源层的第一区连接。
在示例性实施方式中，第三十过孔V30在基底上的正投影位于第十有源层的第二区在基底上的正投影的范围之内，第三十过孔V30内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第十有源层的第二区的表面，第三十过孔V30被配置为使后续形成的第二十一连接电极通过该过孔与第十有源层的第二区连接。
在示例性实施方式中，第三十一过孔V31在基底上的正投影位于第十一有源层的第一区在基底上的正投影的范围之内，第三十一过孔V31内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第十一有源层的第一区的表面，第三十一过孔V31被配置为使后续形成的第二十四连接电极通过该过孔与第十一有源层的第一区连接。
在示例性实施方式中，第三十二过孔V32在基底上的正投影位于第十一有源层的第二区在基底上的正投影的范围之内，第三十二过孔V32内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第十一有源层的第二区的表面，第三十二过孔V32被配置为使后续形成的第二十二连接电极通过该过孔与第十一有源层的第二区连接。
在示例性实施方式中，第三十三过孔V33在基底上的正投影位于第一极板CF1在基底上的正投影的范围之内，第三十三过孔V33内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第一极板CF1的表面，第三十三 过孔V33被配置为使后续形成的第七极板通过该过孔与第一极板CF1连接。
在示例性实施方式中，第三十四过孔V34在基底上的正投影位于第二极板CF2在基底上的正投影的范围之内，第三十四过孔V34内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第二极板CF2的表面，第三十四过孔V34被配置为使后续形成的第八极板通过该过孔与第二极板CF2连接。
在示例性实施方式中，第三十五过孔V35在基底上的正投影位于第三极板CF3在基底上的正投影的范围之内，第三十五过孔V35内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第三极板CF3的表面，第三十五过孔V35被配置为使后续形成的第九极板通过该过孔与第三极板CF3连接。
在示例性实施方式中，第三十六过孔V36在基底上的正投影位于第四极板CF4在基底上的正投影的范围之内，第三十六过孔V36内的第三绝缘层被刻蚀掉，暴露出第四极板CF4的表面，第三十六过孔V36被配置为使后续形成的第十九连接电极通过该过孔与第四极板CF4连接。
在示例性实施方式中，第三十七过孔V37在基底上的正投影位于第五极板CF5在基底上的正投影的范围之内，第三十七过孔V37内的第三绝缘层被刻蚀掉，暴露出第五极板CF5的表面，第三十七过孔V37被配置为使后续形成的第二十一连接电极通过该过孔与第五极板CF5连接。
在示例性实施方式中，第三十八过孔V38在基底上的正投影位于第六极板CF6在基底上的正投影的范围之内，第三十八过孔V38内的第三绝缘层被刻蚀掉，暴露出第六极板CF6的表面，第三十八过孔V38被配置为使后续形成的第十四连接电极通过该过孔与第六极板CF6连接。
在示例性实施方式中，第三十九过孔V39在基底上的正投影位于高压连接线VDD-C在基底上的正投影的范围之内，第三十九过孔V39内的第三绝缘层被刻蚀掉，暴露出高压连接线VDD-C的表面，第三十九过孔V39被配置为使后续形成的第十三连接电极通过该过孔与高压连接线VDD-C连接。
在示例性实施方式中，第四十过孔V40在基底上的正投影位于高频连接线Hf-C在基底上的正投影的范围之内，第四十过孔V40内的第三绝缘层被刻蚀掉，暴露出高频连接线Hf-C的表面，第四十过孔V40被配置为使后续形成的高频信号线通过该过孔与高频连接线Hf-C连接。
在示例性实施方式中，第四十一过孔V41在基底上的正投影位于发光信号线EM在基底上的正投影的范围之内，第四十一过孔V41内的第三绝缘层被刻蚀掉，暴露出发光信号线EM的表面，第四十一过孔V41被配置为使后续形成的第二十五连接电极通过该过孔与发光信号线EM连接。
在示例性实施方式中，第四十二过孔V42和第四十三过孔V43在基底上的正投影分别位于初始信号线Vint在基底上的正投影的范围之内，第四十二过孔V42和第四十三过孔V43内的第三绝缘层被刻蚀掉，分别暴露出初始信号线Vint的表面，第四十二过孔V42和第四十三过孔V43被配置为使后续形成的第十一连接电极和第十二连接电极分别通过上述过孔分别与初始信号线Vint连接。
在示例性实施方式中，第四十四过孔V44在基底上的正投影位于第一连接电极CO1的第一端在基底上的正投影的范围之内，第四十四过孔V44内的第三绝缘层被刻蚀掉，暴露出第一连接电极CO1的第一端的表面，第四十四过孔V44被配置为使后续形成的高频连接线通过该过孔与第一连接电极CO1连接。
在示例性实施方式中，第四十五过孔V45在基底上的正投影位于第一连接电极CO1的第二端在基底上的正投影的范围之内，第四十五过孔V45内的第三绝缘层被刻蚀掉，暴露出第一连接电极CO1的第二端的表面，第四十五过孔V45被配置为使后续形成的第二十四连接电极通过该过孔与第一连接电极CO1的第二端连接。
在示例性实施方式中，第四十六过孔V46在基底上的正投影位于第二连接电极CO2的第一端在基底上的正投影的范围之内，第四十六过孔V46内的第三绝缘层被刻蚀掉，暴露出第二连接电极CO2的第一端的表面，第四十六过孔V46被配置为使后续形成的第二十二连接电极通过该过孔与第二连接电极CO2的第一端连接。
在示例性实施方式中，第四十七过孔V47在基底上的正投影位于第二连接电极CO2的第二端在基底上的正投影的范围之内，第四十七过孔V47内的第三绝缘层被刻蚀掉，暴露出第二连接电极CO2的第二端的表面，第四十七过孔V47被配置为使后续形成的第二十三连接电极通过该过孔与第二连接 电极CO2的第二端连接。
在示例性实施方式中，第四十八过孔V48在基底上的正投影位于第三连接电极CO3在基底上的正投影的范围之内，第四十八过孔V48内的第三绝缘层被刻蚀掉，暴露出第三连接电极CO3的表面，第四十八过孔V48被配置为使后续形成的第二十五连接电极通过该过孔与第三连接电极CO3连接。
在示例性实施方式中，第四十九过孔V49在基底上的正投影位于第四连接电极CO4在基底上的正投影的范围之内，第四十九过孔V49内的第三绝缘层被刻蚀掉，暴露出第四连接电极CO4的表面，第四十九过孔V49被配置为使后续形成的第十五连接电极通过该过孔与第四连接电极CO4连接。
在示例性实施方式中，第五十过孔V50在基底上的正投影位于第三底栅电极Gate3-B在基底上的正投影的范围之内，第五十过孔V50内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第三底栅电极Gate3-B的表面，第五十过孔V50被配置为使后续形成的第十五连接电极通过该过孔与第三底栅电极Gate3-B连接。
在示例性实施方式中，第五十一过孔V51在基底上的正投影位于第六连接电极CO6在基底上的正投影的范围之内，第五十一过孔V51内的第三绝缘层被刻蚀掉，暴露出第六连接电极CO6的表面，第五十一过孔V51被配置为使后续形成的第二十三连接电极通过该过孔与第六连接电极CO6连接。
在示例性实施方式中，第五十二过孔V52在基底上的正投影位于第七连接电极CO7的第一端在基底上的正投影的范围之内，第五十二过孔V52内的第三绝缘层被刻蚀掉，暴露出第七连接电极CO7的第一端的表面，第五十二过孔V52被配置为使后续形成的第二十连接电极通过该过孔与第七连接电极CO7的第一端连接。
在示例性实施方式中，第五十三过孔V53在基底上的正投影位于第七连接电极CO7的第二端在基底上的正投影的范围之内，第五十三过孔V53内的第三绝缘层被刻蚀掉，暴露出第七连接电极CO7的第二端的表面，第五十三过孔V53被配置为使后续形成的第十九连接电极通过该过孔与第七连接电极CO7的第二端连接。
在示例性实施方式中，第五十四过孔V54在基底上的正投影位于第八连 接电极CO8在基底上的正投影的范围之内，第五十四过孔V54内的第三绝缘层被刻蚀掉，暴露出第八连接电极CO8的表面，第五十四过孔V54被配置为使后续形成的第二十一连接电极通过该过孔与第八连接电极CO8连接。
在示例性实施方式中，部分电路单元还可以包括第五十五过孔V55。第五十五过孔V55在基底上的正投影位于低压连接线VSS-C在基底上的正投影的范围之内，第五十五过孔V55内的第三绝缘层被刻蚀掉，暴露出低压连接线VSS-C的表面，第五十五过孔V55被配置为使后续形成的第二十七连接电极通过该过孔与低压连接线VSS-C连接。
在示例性实施方式中，部分电路单元还可以包括多个连接线过孔，连接线过孔可以设置在第一阳极连接线11的两端，连接线过孔11被配置为与后续形成的阳极连接块通过该过孔与第一阳极连接线11连接。
在示例性实施方式中，位于空白单元区域的第一扫描信号线S1、第二扫描信号线S2和发光信号线EM还设置有栅线过孔(未示出)，栅线过孔被配置为与后续形成的相应输出信号线连接。
如图22和图24所示，在示例性实施方式中，每个栅极驱动电路的多个过孔可以至少包括：第六十一过孔V61至第九十过孔V90。
在示例性实施方式中，第六十一过孔V61在基底上的正投影位于第二十一有源层的第一区在基底上的正投影的范围之内，第六十一过孔V61内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二十一有源层的第一区的表面，第六十一过孔V61被配置为使后续形成的第三十一连接电极通过该过孔与第二十一有源层的第一区连接。
在示例性实施方式中，第六十二过孔V62在基底上的正投影位于第二十一有源层的第二区在基底上的正投影的范围之内，第六十二过孔V62内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二十一有源层的第二区的表面，第六十二过孔V62被配置为使后续形成的第三十二连接电极通过该过孔与第二十一有源层的第二区连接。
在示例性实施方式中，第六十三过孔V63在基底上的正投影位于第二十二有源层的第一区在基底上的正投影的范围之内，第六十三过孔V63内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二十二有源层的第一区的表面， 第六十三过孔V63被配置为使后续形成的第三十三连接电极通过该过孔与第二十二有源层的第一区连接。
在示例性实施方式中，第六十四过孔V64在基底上的正投影位于第二十二有源层的第二区在基底上的正投影的范围之内，第六十四过孔V64内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二十二有源层的第二区的表面，第六十四过孔V64被配置为使后续形成的第三十四连接电极通过该过孔与第二十二有源层的第二区连接。
在示例性实施方式中，第六十五过孔V65在基底上的正投影位于第二十三有源层的第一区在基底上的正投影的范围之内，第六十五过孔V65内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二十三有源层的第一区的表面，第六十五过孔V65被配置为使后续形成的低电压线通过该过孔与第二十三有源层的第一区连接。
在示例性实施方式中，第六十六过孔V66在基底上的正投影位于第二十三有源层的第二区在基底上的正投影的范围之内，第六十六过孔V66内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二十三有源层的第二区的表面，第六十六过孔V66被配置为使后续形成的第三十四连接电极通过该过孔与第二十三有源层的第二区连接。
在示例性实施方式中，第六十七过孔V67在基底上的正投影位于第二十四有源层的第一区在基底上的正投影的范围之内，第六十七过孔V67内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二十四有源层的第一区的表面，第六十七过孔V67被配置为使后续形成的第三十七连接电极通过该过孔与第二十四有源层的第一区连接。
在示例性实施方式中，第六十八过孔V68在基底上的正投影位于第二十四有源层的第二区在基底上的正投影的范围之内，第六十八过孔V68内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二十四有源层的第二区的表面，第六十八过孔V68被配置为使后续形成的第三十八连接电极通过该过孔与第二十四有源层的第二区连接。
在示例性实施方式中，第六十九过孔V69在基底上的正投影位于第二十五有源层的第一区在基底上的正投影的范围之内，第六十九过孔V69内的第 三绝缘层和第二绝缘层被刻蚀掉，暴露出第二十五有源层的第一区的表面，第六十九过孔V69被配置为使后续形成的第三十九连接电极通过该过孔与第二十五有源层的第一区连接。
在示例性实施方式中，第七十过孔V70在基底上的正投影位于第二十五有源层的第二区在基底上的正投影的范围之内，第七十过孔V70内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二十五有源层的第二区的表面，第七十过孔V70被配置为使后续形成的第三十八连接电极通过该过孔与第二十五有源层的第二区连接。
在示例性实施方式中，第七十一过孔V71在基底上的正投影位于第二十六有源层的第一区在基底上的正投影的范围之内，第七十一过孔V71内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二十六有源层的第一区的表面，第七十一过孔V71被配置为使后续形成的第三十五连接电极通过该过孔与第二十六有源层的第一区连接。
在示例性实施方式中，第七十二过孔V72在基底上的正投影位于第二十六有源层的第二区在基底上的正投影的范围之内，第七十二过孔V72内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二十六有源层的第二区的表面，第七十二过孔V72被配置为使后续形成的第三十六连接电极通过该过孔与第二十六有源层的第二区连接。
在示例性实施方式中，第七十三过孔V73在基底上的正投影位于第二十七有源层的第一区在基底上的正投影的范围之内，第七十三过孔V73内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二十七有源层的第一区的表面，第七十三过孔V73被配置为使后续形成的第三十六连接电极通过该过孔与第二十七有源层的第一区连接。由于第二十六有源层的第二区与第二十七有源层的第一区相互连接，因而第七十二过孔V72和第七十三过孔V73共用。
在示例性实施方式中，第七十四过孔V74在基底上的正投影位于第二十七有源层的第二区在基底上的正投影的范围之内，第七十四过孔V74内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二十七有源层的第二区的表面，第七十四过孔V74被配置为使后续形成的第三十二连接电极通过该过孔与第二十七有源层的第二区连接。
在示例性实施方式中，第七十五过孔V75在基底上的正投影位于第二十八有源层的第一区在基底上的正投影的范围之内，第七十五过孔V75内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二十八有源层的第一区的表面，第七十五过孔V75被配置为使后续形成的第四十连接电极CO40通过该过孔与第二十八有源层的第一区连接。
在示例性实施方式中，第七十六过孔V76在基底上的正投影位于第二十八有源层的第二区在基底上的正投影的范围之内，第七十六过孔V76内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二十八有源层的第二区的表面，第七十六过孔V76被配置为使后续形成的第四十一连接电极通过该过孔与第二十八有源层的第二区连接。
在示例性实施方式中，第七十七过孔V77在基底上的正投影位于第二十二栅电极Gate22在基底上的正投影的范围之内，第七十七过孔V77内的第三绝缘层被刻蚀掉，暴露出第二十二栅电极Gate22的表面，第七十七过孔V77被配置为使后续形成的第四十连接电极通过该过孔与第二十二栅电极Gate22连接。
在示例性实施方式中，第七十八过孔V78在基底上的正投影位于第二十三栅电极Gate23在基底上的正投影的范围之内，第七十八过孔V78内的第三绝缘层被刻蚀掉，暴露出第二十三栅电极Gate23的表面，第七十八过孔V78被配置为使后续形成的第三十三连接电极通过该过孔与第二十三栅电极Gate23连接。
在示例性实施方式中，第七十九过孔V79在基底上的正投影位于第二十五栅电极Gate25在基底上的正投影的范围之内，第七十九过孔V79内的第三绝缘层被刻蚀掉，暴露出第二十五栅电极Gate25的表面，第七十九过孔V79被配置为使后续形成的第四十一连接电极通过该过孔与第二十五栅电极Gate25连接。
在示例性实施方式中，第八十过孔V80在基底上的正投影位于第二十六栅电极Gate26在基底上的正投影的范围之内，第八十过孔V80内的第三绝缘层被刻蚀掉，暴露出第二十六栅电极Gate26的表面，第八十过孔V80被配置为使后续形成的第三十四连接电极通过该过孔与第二十六栅电极 Gate26连接。
在示例性实施方式中，第八十一过孔V81在基底上的正投影位于第二十七栅电极Gate27在基底上的正投影的范围之内，第八十一过孔V81内的第三绝缘层被刻蚀掉，暴露出第二十七栅电极Gate27的表面，第八十一过孔V81被配置为使后续形成的第三十九连接电极通过该过孔与第二十七栅电极Gate27连接。
在示例性实施方式中，第八十二过孔V82在基底上的正投影位于第十一极板CF11在基底上的正投影的范围之内，第八十二过孔V82内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第十一极板CF11的表面，第八十二过孔V82被配置为使后续形成的第三十八连接电极通过该过孔与第十一极板CF11连接。
在示例性实施方式中，第八十三过孔V83在基底上的正投影位于第十二极板CF12在基底上的正投影的范围之内，第八十三过孔V83内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第十二极板CF12的表面。在示例性实施方式中，第八十三过孔V83可以设置在两个位置，两个位置的第八十三过孔V83被配置为分别使后续形成的第三十五连接电极和第三十七连接电极CO37通过该过孔与第十二极板CF12连接。
在示例性实施方式中，第八十四过孔V84在基底上的正投影位于第三栅极块GK3的第一端在基底上的正投影的范围之内，第八十四过孔V84内的第三绝缘层被刻蚀掉，暴露出第三栅极块GK3的第一端的表面，第八十四过孔V84被配置为使后续形成的第三十五连接电极通过该过孔与第三栅极块GK3的第一端连接。
在示例性实施方式中，第八十五过孔V85在基底上的正投影位于第一栅极块GK1在基底上的正投影的范围之内，第八十五过孔V85内的第三绝缘层被刻蚀掉，暴露出第一栅极块GK1的表面，第八十五过孔V85被配置为使后续形成的第一时钟信号线通过该过孔与第一栅极块GK1连接。
在示例性实施方式中，第八十六过孔V86在基底上的正投影位于第二栅极块GK2在基底上的正投影的范围之内，第八十六过孔V86内的第三绝缘层被刻蚀掉，暴露出第二栅极块GK2的表面，第八十六过孔V86被配置为 使后续形成的第二时钟信号线通过该过孔与第二栅极块GK2连接。
在示例性实施方式中，第八十七过孔V87在基底上的正投影位于第三栅极块GK3的第二端在基底上的正投影的范围之内，第八十七过孔V87内的第三绝缘层被刻蚀掉，暴露出第三栅极块GK3的第二端的表面，第八十七过孔V87被配置为使后续形成的高电压线通过该过孔与第三栅极块GK3的第二端连接。
在示例性实施方式中，第八十八过孔V88在基底上的正投影位于第四栅极块GK4在基底上的正投影的范围之内，第八十八过孔V88内的第三绝缘层被刻蚀掉，暴露出第四栅极块GK4的表面，第八十八过孔V88被配置为使后续形成的低电压线通过该过孔与第四栅极块GK4连接。
在示例性实施方式中，第八十九过孔V89在基底上的正投影位于上一级输出信号线G(n-1)在基底上的正投影的范围之内，第八十九过孔V89内的第三绝缘层被刻蚀掉，暴露出上一级输出信号线G(n-1)的表面，第八十九过孔V89被配置为使后续形成的第三十一连接电极通过该过孔与上一级输出信号线G(n-1)连接。
在示例性实施方式中，第九十过孔V90在基底上的正投影位于本级输出信号线G(n)在基底上的正投影的范围之内，第九十过孔V90内的第三绝缘层被刻蚀掉，暴露出本级输出信号线G(n)的表面，第九十过孔V90被配置为使后续形成的第三十八连接电极通过该过孔与本级输出信号线G(n)连接。
(5)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第三绝缘层上的第三导电层图案，如图25、图26、图27和图28所示，图25为图7中A区域的结构，图26为图25中一个电路单元的放大图，图27为图25中一个栅极驱动电路的放大图，图28为图7中B区域的结构。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
如图25和图26所示，在示例性实施方式中，每个电路单元的第三导电层图案至少包括：数据信号线DataI、高频信号线Hf、第七极板CF7、第八 极板CF8、第九极板CF9、阳极连接块13和多个连接电极。
在示例性实施方式中，数据信号线DataI的形状可以为主体部分沿着第二方向Y延伸的线形状，可以位于电路单元第一方向X的反方向的一侧，数据信号线DataI一方面通过第十七过孔V17与第四有源层的第一区连接，另一方面通过第二十五过孔V25与第八有源层的第一区连接，又一方面，通过第二十九过孔V29与第十有源层的第一区连接，因而实现了数据信号线DataI将数据信号分别写入第四晶体管T4的第一极、第八晶体管T8的第一极和第十晶体管T10的第一极。
在示例性实施方式中，数据信号线DataI可以复用为时长信号线DataT。利用数据信号线DataI分别向第八晶体管T8的第一极和第十晶体管T10的第一极提供时长信号。
在示例性实施方式中，高频信号线Hf的形状可以为主体部分沿着第二方向Y延伸的线形状，可以位于数据信号线DataI第一方向X的反方向的一侧，一方面，高频信号线Hf通过第四十四过孔V44与第一连接电极CO1的第一端连接，另一方面，高频信号线Hf通过第四十过孔V40与高频连接线Hf-C连接，实现了沿着第一方向X延伸的高频连接线Hf-C与沿着第二方向Y延伸的高频信号线Hf之间的连接，形成传输高频信号的网状连通结构。
在示例性实施方式中，第七极板CF7的形状可以为矩形状，第七极板CF7在基底上的正投影与第四极板CF4在基底上的正投影至少部分交叠，第七极板CF7通过第三十三过孔V33与第一极板CF1连接。第七极板CF7可以作为第一电容的又一个极板，第四极板CF4和第七极板CF7构成像素驱动电路的另一个第一电容。由于第七极板CF7通过过孔与第一极板CF1连接，因而第一极板CF1和第七极板CF7具有相同的初始信号电位，使得第一极板CF1、第四极板CF4和第三极板97构成并联结构的第一电容，第一极板CF1和第四极板CF4构成像素驱动电路的一个第一电容，第四极板CF4和第七极板CF7构成像素驱动电路的另一个第一电容，两个第一电容并联。
在示例性实施方式中，第八极板CF8的形状可以为矩形状，第八极板CF8在基底上的正投影与第五极板CF5在基底上的正投影至少部分交叠，第八极板CF8通过第三十四过孔V34与第二极板CF2连接。第八极板CF8可 以作为第二电容的又一个极板，第五极板CF5和第八极板CF8构成像素驱动电路的另一个第二电容。由于第八极板CF8通过过孔与第二极板CF2连接，因而第二极板CF2和第八极板CF8具有相同的初始信号电位，使得第二极板CF2、第五极板CF5和第八极板CF8构成并联结构的第二电容，第二极板CF2和第五极板CF5构成像素驱动电路的一个第二电容，第五极板CF5和第八极板CF8构成像素驱动电路的另一个第二电容，两个第二电容并联。
在示例性实施方式中，第九极板CF9的形状可以为矩形状，第九极板CF9在基底上的正投影与第六极板CF6在基底上的正投影至少部分交叠，第九极板CF9通过第三十五过孔V35与第三极板CF3连接。第九极板CF9可以作为存储电容的又一个极板，第六极板CF6和第九极板CF9构成像素驱动电路的另一个存储电容。由于第九极板CF9通过过孔与第三极板CF3连接，因而第三极板CF3和第九极板CF9具有相同的第一电源电位，使得第三极板CF3、第六极板CF6和第九极板CF9构成并联结构的存储电容，第三极板CF3和第六极板CF6构成像素驱动电路的一个存储电容，第六极板CF6和第九极板CF9构成像素驱动电路的另一个存储电容，两个存储电容并联。
在示例性实施方式中，每个电路单元中的多个连接电极可以至少包括第十一连接电极CO11至第二十六连接电极CO26。
在示例性实施方式中，第十一连接电极CO11的形状可以为沿着第二方向Y延伸的条形状，第十一连接电极CO11的第一端通过第十一过孔V11与第一有源层的第一区(也是第七有源层的第一区)连接，第十一连接电极CO11的第二端通过第四十二过孔V42与初始信号线Vint连接，因而实现了初始信号线Vint将初始信号分别写入第一晶体管T1的第一极和第七晶体管T7的第一极。
在示例性实施方式中，第十一连接电极CO11还与第七极板CF7连接，由于第一极板CF1和第七极板CF7通过过孔连接，因而实现了初始信号线Vint将初始信号写入第一电容的第一极板CF1和第七极板CF7。
在示例性实施方式中，第十一连接电极CO11和第七极板CF7可以为相互连接的一体结构。
在示例性实施方式中，第十二连接电极CO12的形状可以为沿着第二方 向Y延伸的条形状，第十二连接电极CO12的第一端通过第四十三过孔V43与初始信号线Vint连接，第十二连接电极CO12的第二端与第八极板CF8连接。由于第二极板CF2和第八极板CF8通过过孔连接，因而实现了初始信号线Vint将初始信号写入第二电容的第二极板CF2和第八极板CF8。
在示例性实施方式中，第十二连接电极CO12和第八极板CF8可以为相互连接的一体结构。
在示例性实施方式中，第十三连接电极CO13的形状可以为沿着第二方向Y延伸的条形状，第十三连接电极CO13的第一端通过第三十九过孔V39与高压连接线VDD-C连接，第十三连接电极CO13的第二端与第九极板CF9连接。由于第三极板CF3和第九极板CF9通过过孔连接，高压连接线VDD-C被配置为与高压电源线连接，因而实现了高压电源线将高压信号写入存储电容的第三极板CF3和第九极板CF9。
在示例性实施方式中，第十三连接电极CO13和第九极板CF9可以为相互连接的一体结构。
在示例性实施方式中，第十四连接电极CO14的形状可以为沿着第二方向Y延伸的折线状，第十四连接电极CO14的第一端通过第十二过孔V12与第一有源层的第二区连接，第十四连接电极CO14的第二端通过第三十八过孔V38与第六极板CF6连接，第十四连接电极CO14使得第一晶体管T1的第二极和第六极板CF6具有相同的电位。
在示例性实施方式中，第十五连接电极CO15的形状可以为折线状，第十五连接电极CO15的第一端通过第十三过孔V13与第二有源层的第一区连接，第十五连接电极CO15的第二端通过第四十九过孔V49与第四连接电极CO4连接，第十五连接电极CO15的第一端和第二端之间的部分，通过第五十过孔V50与第三底栅电极Gate3-B连接。在示例性实施方式中，由于第四连接电极CO4分别与第三顶栅电极Gate3-T和第六极板CF6连接，因而第十五连接电极CO15不仅使得第三顶栅电极Gate3-T与第三底栅电极Gate3-B相互连接，而且使得第二晶体管T2的第一极、第三晶体管T3的栅电极和第六极板CF6具有相同的电位。
在示例性实施方式中，一方面，第六极板CF6与第二晶体管T2的第一 极和第三晶体管T3的栅电极连接，另一方面，第六极板CF6与第一晶体管T1的第二极连接，因而第十四连接电极CO14和第十五连接电极CO15使得第一晶体管T1的第二极、第二晶体管T2的第一极、第三晶体管T3的栅电极和第六极板CF6具有相同的电位(即像素驱动电路的第三节点N3)。
在示例性实施方式中，第十六连接电极CO16的形状为折线状，第十六连接电极CO16的第一端通过第十四过孔V14与第二有源层的第二区连接，第十六连接电极CO16的第二端通过第十六过孔V16与第三有源层的第二区连接，第十六连接电极CO16的第一端和第二端之间的部分，通过第二十一过孔V21与第六有源层的第一区连接，第十六连接电极CO16使得第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极具有相同的电位(即像素驱动电路的第四节点N4)。
在示例性实施方式中，第十七连接电极CO17的形状可以为折线状，第十七连接电极CO17的第一端通过第十五过孔V15与第三有源层的第一区连接，第十七连接电极CO17的第二端通过第二十过孔V20与第五有源层的第二区连接，第十七连接电极CO17的第一端和第二端之间的部分，通过第十八过孔V18与第四有源层的第二区连接，第十七连接电极CO17使得第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极具有相同的电位(即像素驱动电路的第五节点N5)。
在示例性实施方式中，第十八连接电极CO18的形状可以为折线状，第十八连接电极CO18的第一端通过第十九过孔V19与第五有源层的第一区连接，第十八连接电极CO18的第二端与第九极板CF9连接，第十八连接电极CO18使得第五晶体管T5的第一极和第九极板CF9具有相同的电位。由于第九极板CF9与第十三连接电极CO13连接，第十三连接电极CO13与高压连接线VDD-C连接，高压连接线VDD-C被配置为与高压电源线连接，因而实现了高压电源线将高压信号写入写入每个电路单元的第五晶体管T5的第一极。
在示例性实施方式中，第十八连接电极CO18和第九极板CF9可以为相互连接的一体结构。
在示例性实施方式中，第十九连接电极CO19的形状可以为沿着第二方 向Y延伸的条形状，第十九连接电极CO19的第一端通过第五十三过孔V53与第七连接电极CO7的第二端，第十九连接电极CO19的第二端通过第三十六过孔V36与第四极板CF4连接，第十九连接电极CO19使得第九晶体管T9的栅电极和第四极板CF4具有相同的电位。
在示例性实施方式中，第二十连接电极CO20的形状可以为沿着第一方向X延伸的条形状，第二十连接电极CO20的第一端通过第二十六过孔V26与第八有源层的第二区连接，第二十连接电极CO20的第二端通过第五十二过孔V52与第七连接电极CO7的第一端连接。由于第七连接电极CO7和第九栅电极Gate9连接，因而第十九连接电极CO19和第二十连接电极CO12使得第八晶体管T8的第二极、第九晶体管T9的栅电极和第四极板CF4具有相同的电位(即像素驱动电路的第六节点N6)。
在示例性实施方式中，第二十一连接电极CO21的形状可以为沿着第二方向Y延伸的条形状，第二十一连接电极CO21的第一端通过第五十四过孔V54与第八连接电极CO8连接，第二十一连接电极CO21的第二端通过第三十七过孔V37与第五极板CF5连接，第二十一连接电极CO21的第一端和第二端之间的部分通过第三十过孔V30与第十有源层的第二区连接。由于第八连接电极CO8与第十一栅电极Gate11连接，因而第二十一连接电极CO21使得第十晶体管T10的第二极、第十一晶体管T11的栅电极和第五极板CF5具有相同的电位(即像素驱动电路的第七节点N7)。
在示例性实施方式中，第二十二连接电极CO22的形状可以为沿着第一方向X延伸的折线状，第二十二连接电极CO22的第一端通过第三十二过孔V32与第十一有源层的第二区连接，第二十二连接电极CO22的第二端通过第四十六过孔V46与第二连接电极CO2的第一端连接，第二十二连接电极CO22的第一端和第二端之间的部分通过第二十八过孔V28与第九有源层的第二区连接，第二十二连接电极CO22使得第九晶体管T9的第二极和第十一晶体管T11的第二极相互连接。
在示例性实施方式中，第二十三连接电极CO23的形状可以为沿着第二方向Y延伸的条形状，第二十三连接电极CO23的第一端通过第四十七过孔V47与第二连接电极CO2的第二端连接，第二十三连接电极CO23的第二端 通过第五十一过孔V51与第六连接电极CO6连接。由于第二十二连接电极CO22和第二十三连接电极CO23通过第二连接电极CO2连接，第六连接电极CO6与第六栅电极Gate6连接，因而第二十二连接电极CO22和第二十三连接电极CO23使得第六栅电极Gate6、第九晶体管T9的第二极和第十一晶体管T11的第二极具有相同的电位(即像素驱动电路的第一节点N1)。
在示例性实施方式中，第二十四连接电极CO24的形状可以为“L”形状，第二十四连接电极CO24的第一端通过第三十一过孔V31与第十一有源层的第一区连接，第二十四连接电极CO24的第二端通过第四十五过孔V45与第一连接电极CO1的第二端连接。由于第一连接电极CO1的第一端通过过孔与高频信号线Hf连接，高频信号线Hf，因而实现了将高频信号写入第十一晶体管T11的第一极。
在示例性实施方式中，第二十五连接电极CO25的形状可以为“L”形状，第二十五连接电极CO25的第一端通过第二十七过孔V27与第九有源层的第一区连接，第二十五连接电极CO25的第二端通过第四十一过孔V41与发光信号线EM连接，第二十五连接电极CO25的第一端和第二端之间的部分通过第四十八过孔V48与第三连接电极CO3连接，因而实现了发光信号线EM将发光信号写入第九晶体管T9的第一极。
在示例性实施方式中，第二十六连接电极CO26的形状可以为沿着第二方向Y延伸的条形状，第二十六连接电极CO26的第一端通过第二十二过孔V22与第六有源层的第二区连接，第二十六连接电极CO26的第二端通过第二十四过孔V24与第七有源层的第二区连接，因而第二十六连接电极CO26使得第六晶体管T6的第二极和第七晶体管T7的第二极具有相同的电位(即像素驱动电路的第二节点N2)。
在示例性实施方式中，第三导电层还可以包括第二十七连接电极CO27。第二十七连接电极CO27的形状可以为沿着第二方向Y延伸的条形状，第二十七连接电极CO27可以设置在部分电路单元中，第二十七连接电极CO27通过第五十五过孔V55与低压连接线VSS-C连接，第二十七连接电极CO27被配置为与后续形成的低压电源线连接。
在示例性实施方式中，部分电路单元还可以包括第二阳极连接线12和阳 极连接块13
在示例性实施方式中，第二阳极连接线12的第一端被配置为通过连接线过孔与第一阳极连接线11连接，第二阳极连接线12的第二端被配置为与阳极连接块13直接连接。部分电路单元的阳极连接块13与第二十六连接电极CO26直接连接，部分电路单元的阳极连接块13通过第一阳极连接线11和第二阳极连接线12与阳极连接块13连接，以实现了每个电路单元中的阳极连接块13与第二十六连接电极CO26之间的连接，本公开在此不做限定。
如图25和图27所示，在示例性实施方式中，每个栅极驱动电路的第三导电层图案至少包括：第一时钟信号线CLK、第二时钟信号线CLKB、高电压线VGH、低电压线VG和多个连接电极。
在示例性实施方式中，第一时钟信号线CLK的形状可以为主体部分沿着第二方向Y延伸的线形状，可以位于第十四极板CF14远离第十三极板CF13的一侧，第一时钟信号线CLK通过第八十五过孔V85与第一栅极块GK1连接。由于第一栅极块GK1与第二十一栅电极Gate21连接，第二十一栅电极Gate21和第二十三栅电极Gate23连接，因而实现了第一时钟信号线CLK可以控制第二十一晶体管T21和第二十三晶体管T23的导通和断开。
在示例性实施方式中，第二时钟信号线CLKB的形状可以为主体部分沿着第二方向Y延伸的线形状，可以位于第一时钟信号线CLK远离第十四极板CF14的一侧，第二时钟信号线CLKB通过第八十六过孔V86与第二栅极块GK2连接。由于第二栅极块GK2与第二十七栅电极Gate27连接，因而实现了第二时钟信号线CLKB可以控制第二十七晶体管T27的导通和断开。
在示例性实施方式中，高电压线VGH的形状可以为主体部分沿着第二方向Y延伸的线形状，可以位于第二时钟信号线CLKB远离第十四极板CF14的一侧，高电压线VGH通过第八十七过孔V87与第三栅极块GK3的第二端连接。
在示例性实施方式中，低电压线VGL的形状可以为主体部分沿着第二方向Y延伸的线形状，可以位于第十三极板CF13和第十四极板CF14之间，低电压线VGL一方面通过第八十八过孔V88与第四栅极块GK4连接，另一方面通过第九十过孔V90与第二十三有源层的第一区连接。由于第四栅极块 GK4与第二十八栅电极Gate28连接，因而实现了低电压线VGL可以控制第二十八晶体管T28的导通和断开，且将低电压信号写入第二十三晶体管T23的第一极。
在示例性实施方式中，栅极驱动电路在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影没有交叠。
在示例性实施方式中，由于第一时钟信号线CLK和第二时钟信号线CLKB设置在空白列所在区域，数据信号线DataI可以设置在重复单元列所在区域，使得数据信号线DataI与第一时钟信号线CLK和第二时钟信号线CLKB之间没有交叠，第一时钟信号线CLK在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影没有交叠，第二时钟信号线CLKB在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影没有交叠。
在示例性实施方式中，第一时钟信号线CLK与数据信号线DataI可以基本上平行，第二时钟信号线CLKB与数据信号线DataI可以基本上平行，或者，第一时钟信号线CLK在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影可以基本上平行，第二时钟信号线CLKB在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影可以基本上平行。
在示例性实施方式中，沿着第一方向X，第一时钟信号线CLK和第二时钟信号线CLKB可以设置在高电压线VGH和低电压线VGL之间，使得数据信号线DataI位于高电压线VGH远离第一时钟信号线CLK的一侧，数据信号线DataI位于低电压线VGL远离第二时钟信号线CLKB的一侧，传输恒压信号的高电压线VGH和低电压线VGL可以起到屏蔽作用，有效降低时钟信号线和数据信号线之间的耦合电容。
在示例性实施方式中，高电压线VGH靠近数据信号线DataI一侧的边缘与数据信号线DataI靠近高电压线VGH一侧的边缘具有第一距离L，低电压线VGL靠近数据信号线DataI一侧的边缘与数据信号线DataI靠近低电压线VGL一侧的边缘之间具有第二距离L2，第二距离L2可以大于第一距离L1。
在示例性实施方式中，第一距离L1可以大于或等于25μm，第二距离 L2可以大于或等于25μm。例如，第一距离L1可以约为28.5μm。
在示例性实施方式中，第一时钟信号线CLK靠近低电压线VGL一侧的边缘与低电压线VGL靠近第一时钟信号线CLK一侧的边缘之间具有第三距离L3，第二时钟信号线CLKB靠近高电压线VGH一侧的边缘与高电压线VGH靠近第二时钟信号线CLKB一侧的边缘之间具有第四距离L4，第三距离L3可以大于第四距离L4。
在示例性实施方式中，栅极驱动电路靠近数据信号线DataI一侧的边缘与数据信号线DataI靠近栅极驱动电路一侧的边缘之间的第五距离L5可以大于或等于50μm，例如，第五距离L5可以约为55.5μm。第五距离L5可以是第一方向X的尺寸。
在示例性实施方式中，每个栅极驱动电路的多个连接电极可以至少包括第三十一连接电极CO31至第四十一连接电极CO41。
在示例性实施方式中，第三十一连接电极CO31的形状可以为条形状，第三十一连接电极CO31的第一端通过第六十一过孔V61与第二十一有源层的第一区连接，第三十一连接电极CO31的第二端通过第八十九过孔V89与上一级输出信号线G(n-1)连接，使得上一级输出信号线G(n-1)传输的上一级输出信号可以写入第二十一晶体管T21的第一极。
在示例性实施方式中，第三十二连接电极CO32的形状可以为条形状，第三十二连接电极CO32的第一端通过第六十二过孔V62与第二十一有源层的第二区连接，第三十二连接电极CO32的第二端通过第七十四过孔V74与第二十七有源层的第二区连接，使得第二十一晶体管T21的第二极和第二十七晶体管T27的第二极相互连接(栅极驱动电路的第十一节点N11)。
在示例性实施方式中，第三十三连接电极CO33的形状可以为条形状，第三十三连接电极CO33的第一端通过第六十三过孔V63与第二十二有源层的第一区连接，第三十三连接电极CO33的第二端通过第七十八过孔V78与第二十三栅电极Gate23连接。由于第二十三栅电极Gate23与第一时钟信号线CLK连接，因而实现了第一时钟信号线CLK将第一时钟信号写入第二十二晶体管T22的第一极。
在示例性实施方式中，第三十四连接电极CO34的形状可以为折线状， 第三十四连接电极CO34的第一端通过第八十过孔V80与第二十六栅电极Gate26连接，第三十四连接电极CO34的第二端通过第六十六过孔V66与第二十三有源层的第二区连接，第三十四连接电极CO34的第一端和第二端之间的部分通过第六十四过孔V64与第二十二有源层的第二区连接。由于第二十六栅电极Gate26与第十四极板CF14连接，第十四极板CF14与第二十四栅电极Gate24连接，因而第三十四连接电极CO34使得第二十二晶体管T22的第二极、第二十三晶体管T23的第二极、第二十四晶体管T24的栅电极、第二十六晶体管T26的栅电极和第十四极板CF14具有相同的电位(栅极驱动电路的第十一节点N12)。
在示例性实施方式中，第三十五连接电极CO35的形状可以为条形状，第三十五连接电极CO35的第一端通过第七十一过孔V71与第二十六有源层的第一区连接，第三十五连接电极CO35的第二端一方面通过第八十三过孔V83与第十二极板CF12连接，另一方面通过第八十四过孔V84与第三栅极块GK3的第一端连接。由于第三栅极块GK3与高电压线VGH连接，因而实现了高电压线VGH将高电压信号写入第二十六晶体管T26的第一极，且第十二极板CF12与高电压线VGH具有相同的电位。
在示例性实施方式中，第三十六连接电极CO36的形状可以为矩形状，第三十六连接电极CO36通过第七十二过孔V72(也是第七十三过孔V73)与第二十六有源层的第二区(也是第二十七有源层的第一区)连接，实现了第二十六晶体管T26的第二极和第二十七晶体管T27的第一极的连接(栅极驱动电路的第十三节点N13)。
在示例性实施方式中，第三十七连接电极CO37的形状可以为梳形状，一方面，第三十七连接电极CO37通过第六十七过孔V67与第二十四有源层的第一区连接，另一方面，第三十七连接电极CO37通过第八十三过孔V83与第十二极板CF12连接。由于第十二极板CF12与高电压线VGH连接，因而实现了高电压线VGH将高电压信号写入第二十四晶体管T24的第一极。
在示例性实施方式中，第三十八连接电极CO38的形状可以为梳形状，一方面，第三十八连接电极CO38通过第六十八过孔V68与第二十四有源层的第二区连接，另一方面，第三十八连接电极CO38通过第七十过孔V70与 第二十五有源层的第二区连接，又一方面，第三十八连接电极CO38通过第九十过孔V90与本级输出信号线G(n)连接，又一方面，第三十八连接电极CO38通过第八十二过孔V82与第十一极板CF11连接，实现了第二十四晶体管T24的第二极、第二十五晶体管T25的第二极和第十一极板CF11具有相同的电位。在示例性实施方式中，第三十八连接电极CO38可以作为本级输出线，第三十八连接电极CO38远离栅极驱动电路的一端延伸到第一电路区后，通过栅线过孔与第二扫描信号线S2(或者第一扫描信号线S1、发光信号线EM)连接，
在示例性实施方式中，第三十九连接电极CO39的形状可以为梳形状，一方面，第三十九连接电极CO39通过第六十九过孔V69与第二十五有源层的第一区连接，另一方面，第三十九连接电极CO39通过第八十一过孔V81与第二十七栅电极Gate27连接。由于第二十七栅电极Gate27与第二时钟信号线CLKB连接，因而实现了第二时钟信号线CLKB将第二时钟信号写入第二十五晶体管T25的第一极。
在示例性实施方式中，第四十连接电极CO40的形状可以为条形状，一方面，第四十连接电极CO40通过第七十五过孔V75与第二十八有源层的第一区连接，另一方面，第四十连接电极CO40通过第七十七过孔V77与第二十二栅电极Gate22连接，使得第二十二晶体管T22的栅电极和第二十八晶体管T28的第一极相互连接(栅极驱动电路的第十一节点N11)。
在示例性实施方式中，第四十一连接电极CO41的形状可以为条形状，一方面，第四十一连接电极CO41通过第七十六过孔V76与第二十八有源层的第二区连接，另一方面，第四十一连接电极CO41通过第七十九过孔V79与第二十五栅电极Gate25连接。由于第二十五栅电极Gate25与第十三极板CF13连接，因而使得第二十五晶体管T25的栅电极、第二十八晶体管T28的第二极和第十三极板CF13具有相同的电位(栅极驱动电路的第十四节点N14)。
如图28所示，在示例性实施方式中，第二电路区220的第三导电层图案还可以包括第一标记MARK1，第一标记MARK1可以位于第二电路区220第一方向X的一侧边缘或者两侧边缘。第一标记MARK1被配置为作为拼接 标记，在进行显示基板拼接时通过第一标记MARK1进行定位。
在示例性实施方式中，第一标记MARK1的形状可以为十字形，至少一个第一标记MARK1在第二电路区220的设置位置与至少一个空白单元KB在第一电路区210中的设置位置可以基本上相对应，即第一标记MARK1可以设置在空白列所在区域，至少一个第一标记MARK1在基准线O1上的正投影与至少一个空白单元KB在基准线O1上的正投影至少部分交叠。
在示例性实施方式中，第一标记MARK1邻近的数据信号线和高频连接线可以设置弯折段，弯折段可以向着远离第一标记MARK1的方向弯折，为第一标记MARK1留出相应的空间。
在示例性实施方式中，像素驱动电路及其相应的信号线、栅极驱动电路及其相应的信号线均避让第一标记MARK1，第一标记MARK1在基底上的正投影与像素驱动电路和栅极驱动电路在基底上的正投影没有交叠，第一标记MARK1在基底上的正投影与第一扫描信号线、第二扫描信号线、发光信号线、高频信号线、初始信号线、数据信号线、第一时钟信号线、第二时钟信号线、高电压线和低电压线等在基底上的正投影没有交叠。
(6)形成第四绝缘层和第一平坦层图案。在示例性实施方式中，形成第四绝缘层和第一平坦层图案可以包括：在形成前述图案的基底上，先涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，随后沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第三导电层图案的第一平坦层以及设置在第一平坦层远离基底一侧的第四绝缘层，第四绝缘层和第一平坦层上设置有多个过孔，如图29、图30和图31所示，图29为图7中A区域的结构，图30为图29中一个电路单元的放大图，图31为图7中B区域的结构。
如图29和图30所示，在示例性实施方式中，每个电路单元的多个过孔可以至少包括第九十一过孔V91。
在示例性实施方式中，第九十一过孔V91在基底上的正投影位于阳极连接块13在基底上的正投影的范围之内，第九十一过孔V91内的第四绝缘薄膜和第一平坦薄膜被去掉，暴露出阳极连接块13的表面，第九十一过孔V91被配置为使后续形成的阳极连接电极通过该过孔与阳极连接块13连接。
在示例性实施方式中，部分电路单元还可以包括第九十二过孔V92。第九十二过孔V92在基底上的正投影位于第二十七连接电极CO27在基底上的正投影的范围之内，第九十二过孔V92内的第四绝缘薄膜和第一平坦薄膜被去掉，暴露出第二十七连接电极CO27的表面，第九十二过孔V92被配置为使后续形成的低压电源线通过该过孔与第二十七连接电极CO27连接。
在示例性实施方式中，部分电路单元还可以包括第九十三过孔V93。第九十三过孔V93在基底上的正投影位于第十三连接电极CO13在基底上的正投影的范围之内，第九十三过孔V93内的第四绝缘薄膜和第一平坦薄膜被去掉，暴露出第十三连接电极CO13的表面，第九十三过孔V93被配置为使后续形成的高压电源线通过该过孔与第十三连接电极CO13连接。
在示例性实施方式中，栅极驱动电路所在区域的第四绝缘层和第一平坦层上没有设置过孔。
如图31所示，在示例性实施方式中，第一标记MARK1所在区域的第一平坦层上设置有第一标记孔B1。
在示例性实施方式中，在通过图案化工艺形成第一平坦层的过程中，第一标记MARK1所在区域设置有第一标记孔B1，第一标记孔B1中的第一平坦层被去掉，暴露出第一标记MARK1。第一标记孔B1的形状可以为矩形状，第一标记孔B1在基底上的正投影可以包含第一标记MARK1在基底上的正投影。在形成第四绝缘层的过程中，第一标记孔B1所在区域被第四绝缘层覆盖，使得第四绝缘层覆盖第一标记MARK1，即第一标记MARK1上仅覆盖有第四绝缘层(也称为第一钝化层)，以保护第一标记MARK1。
(7)形成第四导电层图案。在示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第四绝缘层上的第四导电层图案，如图32和图33所示，图32为图7中A区域的结构，图33为图7中B区域的结构。在示例性实施方式中，第四导电层可以称为第二源漏金属(SD2)层。
如图32所示，在示例性实施方式中，每个电路单元的第四导电层图案可以至少包括阳极连接电极14、高压电源线VDD和低压电源线VSS，高压电 源线可以称为第一电源线，低压电源线可以称为第二电源线。
在示例性实施方式中，阳极连接电极14的形状可以为矩形状，阳极连接电极14通过第九十一过孔V91与阳极连接块13连接，阳极连接电极14被配置为与发光二极管的第一极绑定连接。由于阳极连接块13与第二十六连接电极CO26连接，第二十六连接电极CO26分别与第六有源层的第二区和第七有源层的第二区连接，因而实现了阳极连接电极14与第六晶体管T6的第二极和第七晶体管T7的第二极的连接，像素驱动电路可以驱动发光二极管发光。
在示例性实施方式中，高压电源线VDD的形状可以为沿着第二方向Y延伸的线形状，高压电源线VDD通过部分电路单元中的第九十三过孔V93与第十三连接电极CO13连接。由于第十三连接电极CO13通过过孔与高压连接线VDD-C连接，因而沿着第一方向X延伸的高压连接线VDD-C和沿着第二方向Y延伸的高压电源线VDD构成网状连通结构，不仅可以最大限度地降低了电源传输线的电阻，减小了电源电压的压降，有效提升了显示基板中电源电压的均一性，有效提升了信号面内的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，一部分低压电源线VSS的形状可以为沿着第二方向Y延伸的线形状，另一部分低压电源线VSS的形状可以为“T”形状，低压电源线VSS通过第九十二过孔V92与第二十七连接电极CO27连接。由于第二十七连接电极CO27通过过孔与低压连接线VSS-C连接，因而沿着第一方向X延伸的低压连接线VSS-C和沿着第二方向Y延伸的低压电源线VSS构成网状连通结构，不仅可以最大限度地降低了电源传输线的电阻，减小了电源电压的压降，有效提升了显示基板中电源电压的均一性，有效提升了信号面内的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
如图33所示，在示例性实施方式中，第二电路区220的第四导电层图案还可以包括第二标记MARK2，第二标记MARK2可以位于第二电路区220第一方向X的一侧边缘或者两侧边缘，且位于第一标记MARK1靠近栅极驱动电路的一侧。第二标记MARK2被配置为作为绑定标记，在进行发光二极管绑定连接时通过第二标记MARK2进行定位。
在示例性实施方式中，第二标记MARK2的形状可以为圆形，至少一个第二标记MARK2在第二电路区220的设置位置与至少一个空白单元KB在第一电路区210中的设置位置可以基本上相对应，即第二标记MARK2可以设置在空白列所在区域。
在示例性实施方式中，像素驱动电路及其相应的信号线、栅极驱动电路及其相应的信号线均避让第二标记MARK2，第二标记MARK2在基底上的正投影与像素驱动电路和栅极驱动电路在基底上的正投影没有交叠，第二标记MARK2在基底上的正投影与第一扫描信号线、第二扫描信号线、发光信号线、高频信号线、初始信号线、数据信号线、第一时钟信号线、第二时钟信号线、高电压线和低电压线等在基底上的正投影没有交叠。
(8)形成第五绝缘层和第二平坦层图案。在示例性实施方式中，形成形成第五绝缘层和第二平坦层图案可以包括：在形成前述图案的基底上，先沉积第五绝缘薄膜，采用图案化工艺对第五绝缘薄膜进行图案化，形成覆盖第四导电层图案的第五绝缘层，随后涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成设置在第五绝缘层远离基底一侧的第二平坦层，第五绝缘层和第二平坦层上设置有多个过孔，如图34和图35所示，图34为图7中A区域的结构，图35为图7中B区域的结构。
如图34所示，在示例性实施方式中，每个电路单元中第五绝缘层和第二平坦层上设置有第一绑定孔K1和第二绑定孔K2。
在示例性实施方式中，第一绑定孔K1的形状可以为矩形状，第一绑定孔K1在基底上的正投影位于阳极连接电极14在基底上的正投影的范围之内，第一绑定孔K1内的第二平坦薄膜和第五绝缘薄膜被去掉，暴露出阳极连接电极14的表面，阳极连接电极14被第一绑定孔K1暴露的区域可以作为阳极焊盘，第一绑定孔K1被配置为使发光二极管的第一极通过该绑定孔与阳极连接电极14绑定连接。
在示例性实施方式中，第二绑定孔K2的形状可以为矩形状，第二绑定孔K2在基底上的正投影位于低压电源线VSS在基底上的正投影的范围之内，第二绑定孔K2内的第二平坦薄膜和第五绝缘薄膜被去掉，暴露出低压电源线VSS的表面，低压电源线VSS被第二绑定孔K2暴露的区域可以作为阴极 焊盘，第二绑定孔K2被配置为使发光二极管的第二极通过该绑定孔与低压电源线VSS连接。
如图35所示，在示例性实施方式中，第一标记MARK1和第二标记MARK2所在区域的第二平坦层上设置有第二标记孔B2和第三标记孔B3。
在示例性实施方式中，在形成第五绝缘层的过程中，第五绝缘层一方面覆盖第二标记MARK2，另一方面覆盖位于第一标记MARK1上的第四绝缘层。在通过图案化工艺形成第二平坦层的过程中，第二标记MARK2所在区域设置有第二标记孔B2，第一标记MARK1所在区域设置有第三标记孔B3，第二标记MARK2和第三标记孔B3中的第二平坦层被去掉，分别暴露出覆盖第一标记MARK1和第二标记MARK2的第五绝缘层。在示例性实施方式中，第一标记MARK1上分别覆盖有第四绝缘层和第五绝缘层，第二标记MARK2上覆盖有第五绝缘层(也称为第二钝化层)，以保护第一标记MARK1和第二标记MARK2。
在示例性实施方式中，第二标记孔B2的形状可以为圆形状，第二标记孔B2在基底上的正投影可以包含第二标记MARK2在基底上的正投影。
在示例性实施方式中，第三标记孔B3的形状可以为矩形状，第三标记孔B3在基底上的正投影可以包含第一标记MARK1在基底上的正投影。
至此，在基底上制备完成本示例性实施例的驱动结构层。在平行于显示基板的平面内，驱动结构层可以至少包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、发光信号线、初始信号线、高频信号线、数据信号线和高压电源线。在垂直于显示基板的平面内，驱动结构层可以至少包括在基底上依次设置的第一导电层、第一绝缘层、半导体层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第一平坦层、第四绝缘层、第四导电层、第五绝缘层和第二平坦层。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性基底可以包括但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维 中的一种或多种。
在示例性实施方式中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一平坦层和第二平坦层可以采用有机材料，如树脂等。半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等一种或多种材料，即本公开适用于基于氧化物(Oxide)技术、硅技术以及有机物技术制造的晶体管。例如，半导体层的材料可以为多晶硅(p-Si)。
在示例性实施方式中，后续制备流程可以包括：先利用点胶机向多个第一绑定孔和多个第二绑定孔内加入绑定材料(例如锡膏)，通过转印固晶工艺将多个发光二极管的第一极通过第一绑定孔与阳极连接电极绑定连接，多个发光二极管的第二极通过第二绑定孔与低压电源线绑定连接，完成发光二极管与对应像素驱动电路的连接。随后，在形成前述结构的衬底上涂覆覆盖薄膜形成覆盖层，覆盖层覆盖多个发光二极管。在示例性实施方式中，多个发光二极管和覆盖层可以构成发光结构层。
从以上描述的显示基板的结构以及制备过程可以看出，本公开示例性实施例所提供的显示基板，通过将第一时钟信号线和第二时钟信号线设置在空白列所在区域，使得第一时钟信号线和第二时钟信号线在显示基板平面上的正投影与数据信号线在显示基板平面上的正投影没有交叠，有效避免了时钟信号线和数据信号线之间产生交叠电容，两条信号线之间的交叠电容可以基本上约为0，有效避免了数据信号线上数据电压发生跳变，提高了显示品质。本公开示例性实施例通过将高电压线和低电压线设置在第一时钟信号线和第二时钟信号线的外侧，相当于在时钟信号线与数据信号线之间设置了屏蔽线，有效降低了时钟信号线和数据信号线之间的侧间电容。对于宽度为10μm、 长度为715μm的时钟信号线和数据信号线，在两条信号线之间距离为5μm时，两条信号线之间侧向电容约为2.8fF。当在两条信号线之间设置一条作为屏蔽线的高电压线或者低电压线时，两条信号线之间侧间电容约为3.3*10 -5fF。
本公开通过栅极驱动电路的位置设置，不仅有效减小了RC延迟，增加了充电时间，而且避开了显示基板两侧的走线焊盘和防静电电路，有效避免了栅极驱动电路防静电电路之间的相互干扰。本公开通过采用并联结构的第一电容、第二电容和存储电容，在保证电容容量的前提下，最大限度地减小了第一电容、第二电容和存储电容的占用空间，有利于实现高分辨率显示。本公开通过形成网络连通结构的高压电源线和低压电源线，可以最大限度地降低了电源传输线的电阻，减小了电源电压的压降，有效提升了显示基板中电源电压的均一性，有效提升了信号面内的均一性，有效提升了显示均一性，提高了显示品质和显示质量。本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
需要说明的是，本公开示例性实施例所示结构及其制备过程仅仅是一种示例性说明，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开实施例在此不做具体的限定。
本公开示例性实施例所提供的显示基板可以适用于任何LED驱动像素电路，包括P型PAM、P型PAM+PWM、N型PAM、N型PAM+PWM、以及LTPO型PAM及PAM+PWM电路等。
图36为本公开示例性实施例另一种栅极驱动电路走线的示意图。如图36所示，电路单元Q中的像素驱动电路连接有数据信号线和驱动信号线，栅极单元G中的栅极驱动电路连接有第一时钟信号线、第二时钟信号线、高电压线和低电压线。
在示例性实施方式中，第一时钟信号线CLK、第二时钟信号线CLKB、高电压线VGH和低电压线VGL的形状可以为沿着第二方向Y延伸的线形状，数据信号线DataI的形状可以为沿着第二方向Y延伸的线形状，第一时钟信号线CLK和第二时钟信号线CLKB在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影没有交叠，第一时钟信号线CLK和第二时钟信号线CLKB与数据信号线DataI可以基本上平行。
在示例性实施方式中，第一电路区210中一个单元行的驱动信号线可以至少包括第一扫描信号线S1、第二扫描信号线S2和发光信号线EM，一个栅极单元G中的栅极驱动电路可以至少包括第一GOA电路G1、第二GOA电路G2和EOA电路G3，第一GOA电路G1通过第一输出线OUT1与第一扫描信号线S1连接，第二GOA电路G2通过第二输出线OUT2与第二扫描信号线S2连接，EOA电路G3通过第三输出线OUT3与发光信号线EM连接。
在示例性实施方式中，一个栅极单元G中的第一GOA电路G1、第二GOA电路G2和EOA电路G3可以沿着第一方向X依次设置，并分别通过第一时钟连接线CK1与第一时钟信号线CLK连接，分别通过第二时钟连接线CK2与第二时钟信号线CLKB连接。
在示例性实施方式中，第一GOA电路G1、第二GOA电路G2和/或EOA电路G3在基准线O1上的正投影与至少一个像素驱动电路在基准线O1上的正投影至少部分交叠。
在示例性实施方式中，第一GOA电路G1、第二GOA电路G2和/或EOA电路G3在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影没有交叠。
在示例性实施方式中，第一GOA电路G1、第二GOA电路G2和/或EOA电路G3在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影没有交叠。
在示例性实施方式中，第一时钟连接线CK1和第二时钟连接线CK2的形状可以为沿着第一方向X延伸的线形状，第一时钟连接线CK1和第二时钟连接线CK2在显示基板平面上的正投影与数据信号线DataI在显示基板平面上的正投影至少部分交叠。
在示例性实施方式中，由于第一时钟连接线CK1和第二时钟连接线CK2传输时钟信号，因而本实施例的时钟信号线和数据信号线之间存在交叠电容。如果时钟信号线的电压变化为VGH/VGL，时钟信号线与数据信号线的耦合电容为C ck_cp，数据信号线的负载电容为C data,则数据信号线受时钟信号线耦 合影响的电压跳变为ΔV data，
Figure PCTCN2022141002-appb-000001
在满足Gamma曲线后，在电压跳变ΔV data小于相邻两灰阶的电压级别Vstep时，不会出现因导致电压跳变引起的灰阶差异。即满足
Figure PCTCN2022141002-appb-000002
在示例性实施方式中，Vstep通常约为2mV至3mV，VGH-VGL差值通常约为20V，则耦合电容C ck_cp应小于C data/10fF。
本公开示例性实施例提出了一种将栅极单元进行拆分的方案，以适用于第二电路区空间有限等场景。虽然该方案中时钟信号线和数据信号线之间存在交叠电容，但只要满足耦合电容C ck_cp小于C data/10fF的设置要求，可以有效避免数据信号线上数据电压发生跳变，保证显示品质。
本公开示例性实施例还提供了一种显示基板的制备方法，以制备前述的显示基板。在示例性实施方式中，所述显示基板包括沿着第二方向交替设置的多个第一电路区和多个第二电路区，所述第一电路区包括沿着第一方向交替设置的多个重复单元和多个空白单元，所述重复单元包括多个电路单元，所述第二电路区包括至少一个栅极单元，所述第一方向和第二方向交叉；所述制备方法可以包括：
在所述电路单元内形成像素驱动电路以及与所述像素驱动电路连接的数据信号线和驱动信号线，在所述栅极单元形成至少一个栅极驱动电路以及与所述栅极驱动电路连接的时钟信号线，所述栅极驱动电路与相邻电路单元中的驱动信号线连接，所述数据信号线在显示基板平面上的正投影与所述时钟信号线在显示基板平面上的正投影没有交叠。
本公开示例性实施例还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。 在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (18)

  1. 一种显示基板，包括沿着第二方向交替设置的多个第一电路区和多个第二电路区，所述第一电路区包括沿着第一方向交替设置的多个重复单元和多个空白单元，所述第一方向和第二方向交叉；所述重复单元包括多个电路单元，所述电路单元包括像素驱动电路以及与所述像素驱动电路连接的数据信号线和驱动信号线；所述第二电路区包括至少一个栅极单元，所述栅极单元包括至少一个栅极驱动电路，所述栅极驱动电路与相邻电路单元中的驱动信号线连接，所述栅极驱动电路在显示基板平面上的正投影与所述数据信号线在显示基板平面上的正投影没有交叠。
  2. 根据权利要求1所述的显示基板，其中，至少一个第二电路区具有基准线，所述基准线为在所述第二方向上平分所述第二电路区且沿着所述第一方向延伸的直线；至少一个栅极驱动电路在所述基准线上的正投影与至少一个空白单元在所述基准线上的正投影至少部分交叠。
  3. 根据权利要求2所述的显示基板，其中，至少一个栅极驱动电路还与时钟信号线、高电压线和低电压线连接，在所述第一方向上，所述时钟信号线设置在所述高电压线和所述低电压线之间，所述时钟信号线在显示基板平面上的正投影与所述数据信号线在显示基板平面上的正投影没有交叠。
  4. 根据权利要求3所述的显示基板，其中，在所述第一方向上，所述数据信号线设置在所述高电压线远离所述时钟信号线的一侧，或者，所述数据信号线设置在所述低电压线远离所述时钟信号线的一侧。
  5. 根据权利要求4所述的显示基板，其中，在所述第一方向上，所述高电压线靠近所述数据信号线一侧的边缘与所述数据信号线靠近所述高电压线一侧的边缘之间具有第一距离，所述低电压线靠近所述数据信号线一侧的边缘与所述数据信号线靠近所述低电压线一侧的边缘之间具有第二距离，所述第二距离大于所述第一距离。
  6. 根据权利要求5所述的显示基板，其中，所述第一距离大于或等于25μm，所述第二距离大于或等于25μm。
  7. 根据权利要求3所述的显示基板，其中，所述时钟信号线包括第一时 钟信号线和第二时钟信号线，所述第二时钟信号线设置在所述第一时钟信号线远离所述低电压线的一侧；所述第一时钟信号线靠近所述低电压线一侧的边缘与所述低电压线靠近所述第一时钟信号线一侧的边缘之间具有第三距离，所述第二时钟信号线靠近所述高电压线一侧的边缘与所述高电压线靠近所述第二时钟信号线一侧的边缘之间具有第四距离，所述第三距离大于所述第四距离。
  8. 根据权利要求1所述的显示基板，其中，至少一条驱动信号线与一个栅极驱动电路连接，所述栅极驱动电路设置在所述第二电路区的第一中线区，所述栅极驱动电路通过输出线与所述驱动信号线的第一中点区连接；所述第一中线区为包含第一中线的区域，所述第一中点区为包含第一中点的区域，所述第一中线区和所述第一中点区在所述第一方向上的宽度为显示基板宽度的1％至10％，所述第一中线为在所述第一方向上平分所述第二电路区且沿着所述第二方向延伸的直线，所述第一中点为在所述第一方向上平分所述驱动信号线的点，所述显示基板宽度为所述显示基板所述第一方向的尺寸。
  9. 根据权利要求1所述的显示基板，其中，至少一条驱动信号线分别与第一栅极驱动电路和第二栅极驱动电路连接，所述第一栅极驱动电路设置在所述第二电路区的第二中线区，且通过输出线与所述驱动信号线的第二中点区连接，所述第二栅极驱动电路设置在所述第二电路区的第三中线区，且通过输出线与所述驱动信号线的第三中点区连接；所述第二中线区为包含第二中线的区域，所述第三中线区为包含第三中线的区域，所述第二中点区为包含第二中点的区域，所述第三中点区为包含第三中点的区域，所述第二中线区、所述第三中线区、所述第二中点区和所述第三中点区在第一方向X上的宽度为显示基板宽度的1％至10％；所述第二电路区包括在所述第一方向上平分所述第二电路区且沿着所述第二方向延伸的第一中线，所述第一中线将所述第二电路区划分为第一区域和第二区域，所述第二中线为在所述第一方向上平分所述第一区域且沿着所述第二方向延伸的直线，所述第三中线为在所述第一方向上平分所述第二区域且沿着所述第二方向延伸的直线；所述驱动信号线包括在所述第一方向上平分所述驱动信号线的第一中点，所述第一中点将所述驱动信号线划分为第一线段和第二线段，所述第二中点为在所述 第一方向上平分所述第一线段的点，所述第三中点为在所述第一方向上平分所述第二线段的点。
  10. 根据权利要求2所述的显示基板，其中，至少一个第二电路区具有基准线，所述基准线为在所述第二方向上平分所述第二电路区且沿着所述第一方向延伸的直线，所述第二电路区所述第二方向两侧的第一电路区中的像素驱动电路相对于所述基准线镜像对称。
  11. 根据权利要求2所述的显示基板，其中，至少一个第二电路区还包括至少一个第一标记，至少一个第一标记在所述基准线上的正投影与至少一个空白单元在所述基准线上的正投影至少部分交叠。
  12. 根据权利要求2所述的显示基板，其中，至少一个第二电路区还包括至少一个第二标记，至少一个第二标记在所述基准线上的正投影与至少一个空白单元在所述基准线上的正投影至少部分交叠。
  13. 根据权利要求1至12任一项所述的显示基板，其中，在垂直于显示基板的平面上，所述显示基板包括在基底上依次设置的第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层，所述驱动信号线设置在所述第二栅金属层中，所述数据信号线和所述时钟信号线设置在所述第一源漏金属层中。
  14. 根据权利要求13所述的显示基板，其中，至少一个第二电路区还包括至少一个第一标记和至少一个第二标记，所述第一标记设置在所述第一源漏金属层中，所述第二标记设置在所述第二源漏金属层中。
  15. 根据权利要求14所述的显示基板，其中，所述显示基板还包括第一平坦层和第一钝化层，所述第一平坦层设置在所述第一源漏金属层远离所述基底的一侧，所述第一钝化层设置在所述第一平坦层远离所述基底的一侧，所述第二源漏金属层设置在所述第一钝化层远离所述基底的一侧；所述第一平坦层上设置有暴露出所述第一标记的第一标记孔，所述第一标记孔在所述基底平面上的正投影包含所述第一标记在所述基底平面上的正投影，所述第一钝化层覆盖所述第一标记孔内的第一标记。
  16. 根据权利要求14所述的显示基板，其中，所述显示基板还包括第二 钝化层和第二平坦层，所述第二钝化层设置在所述第二源漏金属层远离所述基底的一侧，所述第二平坦层设置在所述第二钝化层远离所述基底的一侧；所述第二平坦层上设置有第二标记孔和第三标记孔，所述第二标记孔暴露出覆盖所述第二标记的第二钝化层，所述第二标记孔在所述基底平面上的正投影包含所述第二标记在所述基底平面上的正投影，所述第三标记孔暴露出覆盖所述第一标记的第二钝化层，所述第三标记孔在所述基底平面上的正投影包含所述第一标记在所述基底平面上的正投影。
  17. 一种显示装置，包括如权利要求1至16任一项所述的显示基板。
  18. 一种显示基板的制备方法，所述显示基板包括沿着第二方向交替设置的多个第一电路区和多个第二电路区，所述第一电路区包括沿着第一方向交替设置的多个重复单元和多个空白单元，所述重复单元包括多个电路单元，所述第二电路区包括至少一个栅极单元，所述第一方向和第二方向交叉；所述制备方法包括：
    在所述电路单元内形成像素驱动电路以及与所述像素驱动电路连接的数据信号线和驱动信号线，在所述栅极单元形成至少一个栅极驱动电路以及与所述栅极驱动电路连接的时钟信号线，所述栅极驱动电路与相邻电路单元中的驱动信号线连接，所述数据信号线在显示基板平面上的正投影与所述时钟信号线在显示基板平面上的正投影没有交叠。
PCT/CN2022/141002 2022-12-22 2022-12-22 显示基板及其制备方法、显示装置 Ceased WO2024130634A1 (zh)

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