WO2024130652A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2024130652A1
WO2024130652A1 PCT/CN2022/141082 CN2022141082W WO2024130652A1 WO 2024130652 A1 WO2024130652 A1 WO 2024130652A1 CN 2022141082 W CN2022141082 W CN 2022141082W WO 2024130652 A1 WO2024130652 A1 WO 2024130652A1
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Prior art keywords
electrode
exemplary embodiment
transistor
circuit unit
substrate
Prior art date
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Ceased
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PCT/CN2022/141082
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English (en)
French (fr)
Inventor
肖丽
郑皓亮
玄明花
赵蛟
郭玉珍
崔晓荣
张晨阳
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202280005221.0A priority Critical patent/CN118541803A/zh
Priority to JP2024569139A priority patent/JP2025539967A/ja
Priority to PCT/CN2022/141082 priority patent/WO2024130652A1/zh
Priority to US18/555,254 priority patent/US20250081609A1/en
Priority to EP22968948.4A priority patent/EP4513564A4/en
Priority to TW112128600A priority patent/TWI860802B/zh
Priority to TW113136159A priority patent/TW202503726A/zh
Publication of WO2024130652A1 publication Critical patent/WO2024130652A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors

Definitions

  • This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device.
  • LED Semiconductor light emitting diode
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • Micro LED display/Mini LED display can achieve large-size displays through splicing, which can break through size limitations. Because LED has the advantages of self-luminescence, wide viewing angle, fast response, simple structure, small size, light weight, energy saving, high efficiency, long life, clear light, etc., it is easier to achieve high resolution (Pixels Per Inch, PPI), and it is considered to be the most competitive next-generation display technology.
  • an embodiment of the present disclosure provides a display substrate, including a driving circuit layer arranged on a substrate, the driving circuit layer including multiple circuit units, the multiple circuit units including at least a first circuit unit, a second circuit unit and a third circuit unit, the first circuit unit including a first pixel driving circuit, the first pixel driving circuit including at least a first driving transistor, the second circuit unit including a second pixel driving circuit, the second pixel driving circuit including at least a second driving transistor, the third circuit unit including a third pixel driving circuit, the third pixel driving circuit including at least a third driving transistor; a channel width of the first driving transistor is greater than a channel width of the second driving transistor or the third driving transistor, and a channel length of the first driving transistor is the same as a channel length of the second driving transistor or the third driving transistor.
  • a ratio of a channel width of the first driving transistor to a channel width of the second driving transistor or the third driving transistor is 2 to 6.
  • a channel width of the second driving transistor is substantially the same as a channel width of the third driving transistor, and a channel length of the second driving transistor is substantially the same as a channel length of the third driving transistor.
  • the first pixel driving circuit further includes a first storage capacitor
  • the second pixel driving circuit further includes a second storage capacitor
  • the third pixel driving circuit further includes a third storage capacitor; the capacitance value of the first storage capacitor is greater than or equal to the capacitance value of the second storage capacitor or the third storage capacitor.
  • an area of an orthographic projection of the first storage capacitor on the substrate is larger than an area of an orthographic projection of the second storage capacitor or the third storage capacitor on the substrate.
  • a first length of the orthographic projection of the first storage capacitor on the substrate is the same as the first length of the orthographic projection of the second storage capacitor or the third storage capacitor on the substrate, a second length of the orthographic projection of the first storage capacitor on the substrate is greater than or equal to the second length of the orthographic projection of the second storage capacitor or the third storage capacitor on the substrate, the first length is a dimension in a first direction, the second length is a dimension in a second direction, and the first direction intersects with the second direction.
  • a ratio of a second length of a projection of the first storage capacitor on the substrate to a second length of a projection of the second storage capacitor or the third storage capacitor on the substrate is 1 to 2.
  • a first length of the orthographic projection of the second storage capacitor on the substrate is substantially the same as a first length of the orthographic projection of the third storage capacitor on the substrate
  • a second length of the orthographic projection of the second storage capacitor on the substrate is substantially the same as a second length of the orthographic projection of the third storage capacitor on the substrate.
  • the display substrate further includes a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the light-emitting structure layer including a plurality of light-emitting units, the plurality of light-emitting diodes including at least a red light-emitting diode emitting red light, a green light-emitting diode emitting green light, and a blue light-emitting diode emitting blue light, the red light-emitting diode being connected to the first pixel driving circuit, the green light-emitting diode being connected to the second pixel driving circuit, and the blue light-emitting diode being connected to the third pixel driving circuit.
  • the light-emitting structure layer including a plurality of light-emitting units, the plurality of light-emitting diodes including at least a red light-emitting diode emitting red light, a green light-emitting diode emitting green light, and a blue light-emit
  • At least one circuit unit includes a high-voltage connection line extending along a first direction and a high-voltage power line extending along a second direction, wherein the high-voltage power line is connected to the high-voltage connection line through a via to form a mesh connection structure for transmitting a high-voltage power signal, and the first direction intersects with the second direction.
  • At least one circuit unit includes a low-voltage connection line extending along a first direction and a low-voltage power line extending along a second direction, the low-voltage power line is connected to the low-voltage connection line through a via to form a mesh connection structure for transmitting a low-voltage power signal, and the first direction intersects with the second direction.
  • the low voltage power line includes a first low voltage power line and a second low voltage power line, the first low voltage power line is connected to a red light emitting diode, and the second low voltage power line is connected to a green light emitting diode and a blue light emitting diode.
  • At least one circuit unit includes a first low voltage connection line extending along the first direction, and the first low voltage power line is connected to the first low voltage connection line through a via to form a mesh connection structure for transmitting a first low voltage power signal.
  • At least one circuit unit includes a second low voltage connection line extending along the first direction, and the second low voltage power line is connected to the second low voltage connection line through a via to form a mesh connection structure for transmitting a second low voltage power signal.
  • At least one circuit unit includes a high-frequency connecting line extending along a first direction and a high-frequency signal line extending along a second direction, wherein the high-frequency signal line is connected to the high-frequency connecting line through a via to form a mesh connection structure for transmitting a high-frequency signal, and the first direction intersects with the second direction.
  • the display substrate further includes a test circuit and a plurality of data signal lines extending along a unit column direction, the data signal lines are connected to the pixel driving circuit, the detection circuit includes at least a plurality of detection units and a plurality of transmission lines, the plurality of detection units are correspondingly connected to the plurality of data signal lines through the plurality of transmission lines, a shielding line is arranged between at least one transmission line and an adjacent transmission line, and the shielding line is connected to a constant voltage signal line or a ground signal line.
  • a distance between at least one transmission line and an adjacent shielding line is 10 ⁇ m to 20 ⁇ m.
  • the transmission line and the shielding line are disposed in the same layer.
  • the present disclosure further provides a display device, comprising the display substrate as described above.
  • the present disclosure further provides a method for preparing a display substrate, comprising:
  • a driving circuit layer is formed on a substrate, the driving circuit layer includes a plurality of circuit units, the plurality of circuit units include at least a first circuit unit, a second circuit unit and a third circuit unit, the first circuit unit includes a first pixel driving circuit, the first pixel driving circuit includes at least a first driving transistor, the second circuit unit includes a second pixel driving circuit, the second pixel driving circuit includes at least a second driving transistor, the third circuit unit includes a third pixel driving circuit, the third pixel driving circuit includes at least a third driving transistor; a channel width of the first driving transistor is greater than a channel width of the second driving transistor or the third driving transistor, and a channel length of the first driving transistor is the same as a channel length of the second driving transistor or the third driving transistor.
  • FIG1 is a schematic structural diagram of a display device
  • FIG2 is a schematic diagram of a planar structure of a display substrate
  • FIG3 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • FIG4 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure.
  • FIG5A is a schematic structural diagram of a first driving transistor according to the present disclosure.
  • FIG5B is a schematic diagram of the structure of a second driving transistor according to the present disclosure.
  • FIG6A is a schematic diagram of the structure of a first storage capacitor according to the present disclosure.
  • FIG6B is a schematic diagram of the structure of a second storage capacitor according to the present disclosure.
  • FIG7 is a schematic diagram of a display substrate after a first conductive layer pattern is formed according to the present disclosure
  • FIGS. 8A and 8B are schematic diagrams of a display substrate after a semiconductor layer pattern is formed according to the present disclosure
  • FIG9 is a schematic diagram of a display substrate after a second insulating layer pattern is formed according to the present disclosure.
  • FIGS. 10A and 10B are schematic diagrams of a display substrate after a second conductive layer pattern is formed according to the present disclosure
  • FIG11 is a schematic diagram of a display substrate after a third insulating layer pattern is formed according to the present disclosure.
  • FIGS. 12A and 12B are schematic diagrams of a display substrate after a third conductive layer pattern is formed according to the present disclosure
  • FIG13 is a schematic diagram of a display substrate after forming a first flat layer pattern according to the present disclosure.
  • FIGS. 14A and 14B are schematic diagrams of a display substrate after a fourth conductive layer pattern is formed according to the present disclosure
  • FIG15 is a schematic diagram of a display substrate after a second flat layer pattern is formed according to the present disclosure.
  • FIG16 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • FIG17 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG18A is a schematic structural diagram of another first driving transistor disclosed in the present invention.
  • FIG18B is a schematic diagram of the structure of another second driving transistor disclosed in the present invention.
  • FIG19A is a schematic diagram of the structure of another first storage capacitor disclosed in the present invention.
  • FIG19B is a schematic diagram of the structure of another second storage capacitor disclosed in the present invention.
  • FIG20 is a schematic diagram of another display substrate after forming a first conductive layer pattern according to the present disclosure.
  • 21A and 21B are schematic diagrams of another display substrate after a semiconductor layer pattern is formed in the present disclosure.
  • 22A and 22B are schematic diagrams of another display substrate after forming a second conductive layer pattern according to the present disclosure
  • FIG23 is a schematic diagram of another display substrate after a third insulating layer pattern is formed in the present disclosure.
  • 24A and 24B are schematic diagrams of another display substrate after forming a third conductive layer pattern according to the present disclosure.
  • FIG25 is a schematic diagram of another display substrate after forming a first flat layer pattern according to the present disclosure.
  • 26A and 26B are schematic diagrams of another display substrate after a fourth conductive layer pattern is formed in the present disclosure.
  • FIG26C is a schematic diagram of a power supply routing according to an exemplary embodiment of the present disclosure.
  • FIG27 is a schematic diagram of another display substrate after forming a second planar layer pattern according to the present disclosure.
  • FIG28 is a schematic structural diagram of yet another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG29 is a schematic diagram of another display substrate after forming a first conductive layer pattern according to the present disclosure.
  • FIG30 is a schematic diagram of another display substrate after a semiconductor layer pattern is formed in the present disclosure.
  • FIG31 is a schematic diagram of another display substrate after forming a second conductive layer pattern according to the present disclosure.
  • FIG32 is a schematic diagram of another display substrate after a third insulating layer pattern is formed in the present disclosure.
  • FIG33 is a schematic diagram of another display substrate after a third conductive layer pattern is formed in the present disclosure.
  • FIG34 is a schematic diagram of another display substrate after forming a first flat layer pattern according to the present disclosure.
  • FIG35A is a schematic diagram of another display substrate after a fourth conductive layer pattern is formed in the present disclosure.
  • FIG35B is a schematic diagram of another power supply routing according to an exemplary embodiment of the present disclosure.
  • FIG36 is a schematic diagram of another display substrate after forming a second flat layer pattern according to the present disclosure.
  • FIG37 is a schematic diagram showing a substrate undergoing CT testing
  • FIG38 is a schematic diagram of the structure of a detection circuit of an exemplary embodiment of the present disclosure.
  • FIG. 39 is a schematic diagram of a connection between a shielding line and a constant voltage signal line according to an exemplary embodiment of the present disclosure.
  • AA display area
  • AT1 first active layer
  • AT2 second active layer
  • AT3 third active layer
  • AT4 fourth active layer
  • AT5 sixth active layer
  • AT6 singleth active layer
  • AT7 singleth active layer
  • AT8 epiighth active layer
  • AT9 noth active layer
  • AT10 tenth active layer
  • AT11 eleventh active layer
  • AT12 the twelfth active layer
  • CF1 the first electrode plate
  • CF2 the second electrode plate
  • CF3 third plate
  • CF4 fourth plate
  • CF5 sixth plate
  • CF6 ixth plate
  • CF7 sineth plate
  • CF8 eighth plate
  • CF9 ninth plate
  • Cs1 first storage capacitor
  • Cs2 second storage capacitor
  • Cs3 third storage capacitor
  • CT1 first control line
  • CT2 second control line
  • C1 first capacitor
  • C2 second capacitor
  • DTFT1 first driving transistor
  • DTFT2 second driving transistor
  • DTFT3 third driving transistor
  • DataI data signal line
  • DataT duration signal line
  • EM luminous signal line
  • FA binding area
  • Gate1 first gate electrode
  • Gate2 second gate electrode
  • Gate3-B third bottom gate electrode
  • Gate3-T the third top gate electrode
  • Gate4 the fourth gate electrode
  • Gate5 the fifth gate electrode
  • Gate6 the sixth gate electrode
  • Gate7 the seventh gate electrode
  • Gate8 the eighth gate electrode
  • Gate9 the ninth gate electrode
  • Gate10 the tenth gate electrode
  • Gate11 the eleventh gate electrode
  • Gate12 the twelfth gate electrode; Hf—high-frequency signal line; Hf-C—high-frequency connecting line;
  • S1 first scanning signal line
  • S2 second scanning signal line
  • VDD high voltage power line
  • VDD-C high voltage connection line
  • VSS low voltage power line
  • VSS-C low voltage connection line
  • Vint initial signal line
  • 10 substrate
  • 11 power electrode
  • 200 display substrate
  • 210 detection unit
  • 220 control line
  • 230 Detection line
  • 240 Transmission line
  • 250 shielding line.
  • the proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values shown in the drawings.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed should be understood in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the “source electrode” and the “drain electrode” may be interchanged, and the “source terminal” and the “drain terminal” may be interchanged.
  • connection includes the case where components are connected together through an element having some kind of electrical function.
  • element having some kind of electrical function There is no particular limitation on the "element having some kind of electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • Examples of “element having some kind of electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • thickness and “height” refer to the vertical distance between the surface of the film layer away from the substrate and the surface of the film layer close to the substrate.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • FIG1 is a schematic diagram of the structure of a display device.
  • the main structure of a large-size display device may include a plurality of display substrates 200 arranged on a motherboard 100, and the plurality of display substrates 100 are closely spliced together for image display.
  • at least one display substrate 200 may include at least a driving circuit layer 20 arranged on a substrate 10 and a light emitting structure layer 30 arranged on a side of the driving circuit layer 20 away from the substrate.
  • the driving circuit layer 20 may include a plurality of circuit units, at least one circuit unit may include a pixel driving circuit and a plurality of signal lines connected to the pixel driving circuit, and the pixel driving circuit is configured to receive a data voltage under the control of the signal line and output a corresponding current.
  • the light emitting structure layer 30 may include a plurality of light emitting units, at least one light emitting unit may include a light emitting diode 40, the light emitting diode 40 in the plurality of light emitting units is correspondingly connected to the pixel driving circuit in the plurality of circuit units, and the light emitting diode 40 is configured to emit light of corresponding brightness under the drive of the output current of the corresponding pixel driving circuit.
  • the circuit unit mentioned in the present disclosure refers to an area divided according to a pixel driving circuit
  • the light-emitting unit mentioned in the present disclosure refers to an area divided according to a light-emitting diode.
  • the positions of the light-emitting unit and the circuit unit may correspond, or the positions of the light-emitting unit and the circuit unit may not correspond, and the present disclosure does not limit this.
  • the light emitting diode 40 may be a sub-millimeter light emitting diode Mini LED or a micro light emitting diode Micro LED.
  • FIG. 2 is a schematic diagram of a planar structure of a display substrate.
  • the display substrate may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light.
  • each sub-pixel may include a circuit unit and a light-emitting unit.
  • the first sub-pixel P1 may include a first circuit unit and a first light-emitting unit, the first light-emitting unit may include at least a first light-emitting diode emitting a first color light, and the first circuit unit may include at least a first pixel driving circuit connected to the first light-emitting diode.
  • the second sub-pixel P2 may include a second circuit unit and a second light-emitting unit, the second light-emitting unit may include at least a second light-emitting diode emitting a second color light, and the second circuit unit may include at least a second pixel driving circuit connected to the second light-emitting diode.
  • the third sub-pixel P3 may include a third circuit unit and a third light-emitting unit, the third light-emitting unit may include at least a third light-emitting diode emitting a third color light, and the third circuit unit may include at least a third pixel driving circuit connected to the third light-emitting diode.
  • the first sub-pixel P1 may be a red (R) sub-pixel emitting red light
  • the second sub-pixel P2 may be a green sub-pixel (G) emitting green light
  • the third sub-pixel P3 may be a blue (B) sub-pixel emitting blue light
  • the R sub-pixel, the G sub-pixel, and the B sub-pixel may form a pixel unit P.
  • the three sub-pixels in the pixel unit P may be arranged in a horizontal parallel, vertical parallel, or in a triangular pattern, which is not limited in the present disclosure.
  • the pixel unit P may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, a square shape, a diamond shape, etc., which is not limited in the present disclosure.
  • R chips for short red light-emitting diodes
  • G/B chips for short blue and green light-emitting diodes
  • the driving transistor (DTFT) in the pixel driving circuit is designed according to the current demand of the G/B chip, the required current value of 4 ⁇ A can be achieved when the gate-source voltage Vgs is 5V, but under the same cross-voltage, the driving transistor of the R chip cannot reach the required current value of 20 ⁇ A when the gate-source voltage Vgs is 5V, so that the R chip cannot meet the brightness demand. If the driving transistor is designed according to the current requirement of the R chip, the G/B chip will reach its required current at a smaller gate-source voltage Vgs, resulting in a small data range and inability to achieve more grayscales.
  • the present disclosure provides a display substrate, and pixel driving circuits for driving red light emitting diodes, green light emitting diodes and blue light emitting diodes adopt different structures to avoid defects such as brightness not meeting requirements or not being able to achieve more grayscales.
  • the display substrate includes a driving circuit layer disposed on a substrate and a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the driving circuit layer includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the light emitting structure layer includes a plurality of light emitting units, the circuit units include at least a pixel driving circuit, and the light emitting units include at least a light emitting diode; the plurality of circuit units include at least a first circuit unit provided with a first pixel driving circuit, a second circuit unit provided with a second pixel driving circuit, and a third circuit unit provided with a third pixel driving circuit, and the plurality of light emitting diodes include at least a first light emitting diode emitting a first color light, a second light emitting diode emitting a second color light, and a third light emitting diode emitting a third color light.
  • a light-emitting diode and a third light-emitting diode emitting a third color light the first pixel driving circuit is connected to the first light-emitting diode, the second pixel driving circuit is connected to the second light-emitting diode, and the third pixel driving circuit is connected to the third light-emitting diode;
  • the first pixel driving circuit at least includes a first driving transistor and a first storage capacitor
  • the second pixel driving circuit at least includes a second driving transistor and a second storage capacitor
  • the third pixel driving circuit at least includes a third driving transistor and a third storage capacitor
  • the width-to-length ratio of the first driving transistor is greater than the width-to-length ratio of the second driving transistor or the third driving transistor
  • the capacitance value of the first storage capacitor is greater than or equal to the capacitance value of the second storage capacitor or the third storage capacitor.
  • a channel width of the first driving transistor is greater than a channel width of the second driving transistor or the third driving transistor, and a channel length of the first driving transistor is substantially the same as a channel length of the second driving transistor or the third driving transistor.
  • an area of an orthographic projection of the first storage capacitor on the substrate is larger than an area of an orthographic projection of the second storage capacitor or the third storage capacitor on the substrate.
  • the display substrate of the present disclosure is illustrated below through multiple examples.
  • FIG3 is an equivalent circuit diagram of a pixel driving circuit of an exemplary embodiment of the present disclosure, illustrating a 12T3C pixel driving circuit structure.
  • multiple light-emitting diodes in a display substrate may be driven by current mode. Since current-mode light-emitting diodes may have problems of color coordinate drift and low external quantum efficiency when driven at a lower current density, resulting in poor brightness uniformity, it is difficult to accurately represent low grayscale by only controlling the amplitude of the current.
  • the pixel driving circuit of an exemplary embodiment of the present disclosure includes at least two types of data terminals: a current data terminal and a duration data terminal.
  • the current data terminal is configured to provide current signals of different amplitudes to the light-emitting diodes
  • the duration data terminal is configured to provide the light-emitting diodes with the time length of the above-mentioned current signal.
  • the pixel driving circuit provided by the present exemplary embodiment may include at least a current control subcircuit DK and a duration control subcircuit SK.
  • the current control subcircuit DK may include at least a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a twelfth transistor T12 and a storage capacitor Cs
  • the duration control subcircuit SK may include at least an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a first capacitor C1 and a second capacitor C2.
  • the pixel driving circuit may include at least a first node N1, a second node N2, a third node N3, a fourth node N4, a fifth node N5, a sixth node N6, and a seventh node N7.
  • the first node N1 is connected to the second electrode of the ninth transistor T9, the second electrode of the eleventh transistor T11 and the gate electrode of the twelfth transistor T12, respectively;
  • the second node N2 is connected to the second electrode of the seventh transistor T7, the second electrode of the twelfth transistor T12 and the anode of the light emitting diode EL, respectively;
  • the third node N3 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3 and the first end of the storage capacitor Cs, respectively;
  • the fourth node N4 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6, respectively;
  • the fifth node N5 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4 and the second electrode of the fifth transistor T5, respectively;
  • the sixth node N6 is connected to the second electrode of the eighth transistor T8, the gate electrode
  • a gate electrode of the first transistor T1 is connected to the second scan signal line S2 , a first electrode of the first transistor T1 is connected to the initial signal line Vint, and a second electrode of the first transistor T1 is connected to the third node N3 .
  • a gate electrode of the second transistor T2 is connected to the first scan signal line S1 , a first electrode of the second transistor T2 is connected to the third node N3 , and a second electrode of the second transistor T2 is connected to the fourth node N4 .
  • a gate electrode of the third transistor T3 is connected to the third node N3
  • a first electrode of the third transistor T3 is connected to the fifth node N5
  • a second electrode of the third transistor T3 is connected to the fourth node N4 .
  • a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1
  • a first electrode of the fourth transistor T4 is connected to the data signal line Data1
  • a second electrode of the fourth transistor T4 is connected to the fifth node N5.
  • a gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the fifth node N5.
  • a gate electrode of the sixth transistor T6 is connected to the light emitting signal line EM, a first electrode of the sixth transistor T6 is connected to the fourth node N4, and a second electrode of the sixth transistor T6 is connected to a first electrode of the twelfth transistor T12.
  • a gate electrode of the seventh transistor T7 is connected to the second scan signal line S2 , a first electrode of the seventh transistor T7 is connected to the initial signal line Vint, and a second electrode of the seventh transistor T7 is connected to the second node N2 .
  • a gate electrode of the eighth transistor T8 is connected to the first control line CT1
  • a first electrode of the eighth transistor T8 is connected to the duration signal line DataT
  • a second electrode of the eighth transistor T8 is connected to the sixth node N6.
  • a gate electrode of the ninth transistor T9 is connected to the sixth node N6 , a first electrode of the ninth transistor T9 is connected to the light emitting signal line EM, and a second electrode of the ninth transistor T9 is connected to the first node N1 .
  • a gate electrode of the tenth transistor T10 is connected to the second control line CT2 , a first electrode of the tenth transistor T10 is connected to the duration signal line DataT, and a second electrode of the tenth transistor T10 is connected to the seventh node N7 .
  • a gate electrode of the eleventh transistor T11 is connected to the seventh node N7 , a first electrode of the eleventh transistor T11 is connected to the high-frequency signal line Hf, and a second electrode of the eleventh transistor T11 is connected to the first node N1 .
  • a gate electrode of the twelfth transistor T12 is connected to the first node N1
  • a first electrode of the twelfth transistor T12 is connected to the second electrode of the sixth transistor T6
  • a second electrode of the twelfth transistor T12 is connected to the second node N2 .
  • a first end of the storage capacitor Cs is connected to the third node N3 , and a second end of the storage capacitor Cs is connected to the first power line VDD.
  • a first end of the first capacitor C1 is connected to the sixth node N6 , and a second end of the first capacitor C1 is connected to the initial signal line Vint.
  • a first end of the second capacitor C2 is connected to the seventh node N7, and a second end of the second capacitor C2 is connected to the initial signal line Vint.
  • the first transistor T1 , the second transistor T2 , and the fourth transistor T4 to the twelfth transistor T12 may be switching transistors, and the third transistor T3 may be a driving transistor.
  • the light emitting diode EL may be a Mini LED or a Micro LED.
  • a first electrode of the light emitting diode EL is connected to a second node N2, and a second electrode of the light emitting diode EL is connected to a second power line VSS, and a signal of the second power line VSS is a continuously provided low-level signal, such as a DC low voltage.
  • a signal of the first power line VDD is a continuously provided high-level signal, such as a DC high voltage.
  • the first transistor T1 to the twelfth transistor T12 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the twelfth transistor T12 may include a P-type transistor and an N-type transistor.
  • the first transistor T1 to the twelfth transistor T12 may be low-temperature polysilicon transistors, or oxide transistors, or low-temperature polysilicon transistors and metal oxide transistors.
  • the active layer of the low-temperature polysilicon transistor uses low-temperature polysilicon (LTPS), and the active layer of the metal oxide transistor uses metal oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • Oxide metal oxide semiconductor
  • Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, and oxide transistors have advantages such as low leakage current.
  • Low-temperature polysilicon transistors and metal oxide transistors are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • the operation process of the pixel driving circuit may include:
  • the operation process of the pixel driving circuit may include an initialization phase, a writing phase and a light-emitting phase, and the initialization phase may include a first sub-phase and a second sub-phase.
  • the signals of the first scanning signal line S1 and the light-emitting signal line EM are high-level signals
  • the signal of the second scanning signal line S2 is a low-level signal
  • the first transistor T1 and the seventh transistor T7 are turned on.
  • the first transistor T1 is turned on so that the signal of the initial signal line Vint is written into the third node N3, the storage capacitor Cs is initialized (reset), and the original charge in the storage capacitor Cs is cleared. Since the first end of the storage capacitor C is at a low level, the third transistor T3 is turned on.
  • the seventh transistor T7 is turned on so that the signal of the initial signal line Vint is written into the second node N2, the first pole of the light-emitting diode EL is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed to ensure that the light-emitting diode EL does not emit light.
  • the signal of the time length signal line DataT is a high level signal
  • the signal of the second control line CT2 is a low level signal
  • the tenth transistor T10 is turned on, so that the signal of the time length signal line DataT is written into the seventh node N7, and the second capacitor C2 is charged. Since the signal of the time length signal line DataT is a high level signal at this time, the eleventh transistor T11 is turned off, and the signal of the high frequency signal line Hf cannot be written into the first node N1.
  • the signal of the duration signal line DataT is a low level signal
  • the signal of the first control line CT1 is a low level signal
  • the eighth transistor T8 is turned on, so that the signal of the duration signal line DataT is written into the sixth node N6, and the first capacitor C1 is charged. Since the signal of the duration signal line DataT is a low level signal at this time, the ninth transistor T9 is turned on, and the signal of the light emitting signal line EM is written into the first node N1.
  • the data signal line DataI outputs a data voltage
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals
  • the signal of the first scanning signal line S1 is a low-level signal
  • the second transistor T2 and the fourth transistor T4 are turned on.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line DataI is provided to the third node N3 through the fifth node N5, the turned-on third transistor T3, the fourth node N4, and the turned-on second transistor T2, and the difference between the data voltage Vd output by the data signal line DataI and the threshold voltage Vth of the third transistor T3 is charged into the storage capacitor Cs, and the voltage of the first end (third node N3) of the storage capacitor Cs is Vd-
  • the first capacitor C1 keeps the potential of the signal of the sixth node N6 unchanged, the ninth transistor T9 remains turned on, and the signal of the light-emitting signal line EM is written into the first node N1.
  • the signal of the light emitting signal line EM is a low level signal
  • the fifth transistor T5 and the sixth transistor T6 are turned on
  • the first capacitor C1 maintains the potential of the signal of the sixth node N6
  • the ninth transistor T9 remains turned on
  • the signal of the light emitting signal line EM is written into the first node N1
  • the twelfth transistor T12 is turned on.
  • the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light emitting diode EL through the turned-on fifth transistor T5, the third transistor T3, the sixth transistor T6 and the twelfth transistor T12, driving the light emitting diode EL to emit light.
  • the operation process of the pixel driving circuit includes: an initialization phase, a writing phase and a light-emitting phase, and the initialization phase may include a first sub-phase and a second sub-phase.
  • the signals of the first scanning signal line S1 and the light-emitting signal line EM are high-level signals
  • the signal of the second scanning signal line S2 is a low-level signal
  • the first transistor T1 and the seventh transistor T7 are turned on.
  • the first transistor T1 is turned on so that the signal of the initial signal line Vint is written into the third node N3, the storage capacitor Cs is initialized (reset), and the original charge in the storage capacitor Cs is cleared. Since the first end of the storage capacitor C is at a low level, the third transistor T3 is turned on.
  • the seventh transistor T7 is turned on so that the signal of the initial signal line Vint is written into the second node N2, the first pole of the light-emitting diode EL is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed to ensure that the light-emitting diode EL does not emit light.
  • the signal of the time length signal line DataT is a low level signal
  • the signal of the second control line CT2 is a low level signal
  • the tenth transistor T10 is turned on, so that the signal of the time length signal line DataT is written into the seventh node N7, and the second capacitor C2 is charged. Since the signal of the time length signal line DataT is a low level signal at this time, the eleventh transistor T11 is turned on, and the signal of the high frequency signal line Hf is written into the first node N1.
  • the signal of the duration signal line DataT is a high level signal
  • the signal of the first control line CT1 is a low level signal
  • the eighth transistor T8 is turned on, so that the signal of the duration signal line DataT is written into the sixth node N6, and the first capacitor C1 is charged. Since the signal of the duration signal line DataT is a high level signal at this time, the ninth transistor T9 is turned off, and the signal of the light emitting signal line EM cannot be written into the first node N1.
  • the data signal line DataI outputs a data voltage
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals
  • the signal of the first scanning signal line S1 is a low-level signal
  • the second transistor T2 and the fourth transistor T4 are turned on.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line DataI is provided to the third node N3 through the fifth node N5, the turned-on third transistor T3, the fourth node N4, and the turned-on second transistor T2, and the difference between the data voltage Vd output by the data signal line DataI and the threshold voltage Vth of the third transistor T3 is charged into the storage capacitor Cs, and the voltage of the first end (third node N3) of the storage capacitor Cs is Vd-
  • the second capacitor C2 keeps the signal potential of the seventh node N7 unchanged, the eleventh transistor T11 is always turned on, and the signal of the high-frequency signal line Hf is written into the first node N1.
  • the signal of the light-emitting signal line EM is a low-level signal
  • the fifth transistor T5 and the sixth transistor T6 are turned on
  • the second capacitor C2 keeps the signal potential of the seventh node N7 unchanged
  • the eleventh transistor T11 is always turned on
  • the signal of the high-frequency signal line Hf is written into the first node N1
  • the twelfth transistor T12 is turned on.
  • the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting diode EL through the turned-on fifth transistor T5, the third transistor T3, the sixth transistor T6 and the twelfth transistor T12, driving the light-emitting diode EL to emit light.
  • the driving current output by the third transistor T3 in the pixel driving circuit is not affected by the threshold voltage of the third transistor T3, but is only related to the voltage of the data signal line and the voltage of the first power line, thereby eliminating the influence of the threshold voltage of the driving transistor on the driving current, ensuring uniform display brightness of the display product and improving the display effect.
  • a control signal is provided to the first node N1 through the light-emitting signal line, so that the grayscale of the light-emitting diode is controlled by the driving current.
  • a control signal is provided to the first node N1 through the high-frequency signal line, so that the grayscale of the light-emitting diode is controlled by the driving current and the light-emitting duration.
  • the signal of the high-frequency signal line Hf is a pulse signal, and within an image frame, the signal of the high-frequency signal line Hf has multiple pulses.
  • the frequency of the signal of the high-frequency signal line Hf may be greater than the frequency of the signal of the light-emitting signal line EM.
  • the frequency of the signal of the high-frequency signal line Hf may be between 3000Hz and 60000Hz, and the frequency of the light-emitting signal line EM may be between 60Hz and 120Hz.
  • the present disclosure controls the light-emitting duration through the high-frequency pulse signal of the high-frequency signal line, disperses the short light-emitting duration into one frame time, reduces the flicker that occurs when the grayscale displayed by the light-emitting diode connected to the pixel driving circuit is less than the threshold grayscale, and improves the display effect of the display product.
  • FIG4 is a schematic diagram of the structure of a display substrate of an exemplary embodiment of the present disclosure, illustrating the structure of three circuit units, and the circuit unit includes the pixel driving circuit shown in FIG3.
  • the display substrate may include at least a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate.
  • the driving circuit layer may include at least a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the circuit unit may include at least a pixel driving circuit, the light-emitting structure layer may include a plurality of light-emitting units, the light-emitting units may include at least light-emitting diodes, and the light-emitting diodes in the plurality of light-emitting units are correspondingly connected to the pixel driving circuits in the plurality of circuit units, so that the light-emitting diodes emit light of corresponding brightness under the drive of the output current of the corresponding pixel driving circuit.
  • the plurality of circuit units may include at least a first circuit unit Q1, a second circuit unit Q2, and a third circuit unit Q3 sequentially arranged along the first direction X
  • the plurality of light emitting units may include at least a first light emitting unit, a second light emitting unit, and a third light emitting unit.
  • the first circuit unit Q1 may include at least a first pixel driving circuit
  • the second circuit unit Q2 may include at least a second pixel driving circuit
  • the third circuit unit Q3 may include at least a third pixel driving circuit
  • the first light emitting unit may include at least a first light emitting diode
  • the second light emitting unit may include at least a second light emitting diode
  • the third light emitting unit may include at least a third light emitting diode.
  • the first pixel driving circuit is configured to be connected to the first light emitting diode
  • the second pixel driving circuit is configured to be connected to the second light emitting diode
  • the third pixel driving circuit is configured to be connected to the third light emitting diode.
  • the first light emitting diode may be a red light emitting diode
  • the second light emitting diode may be a green light emitting diode
  • the third light emitting diode may be a blue light emitting diode.
  • the first pixel driving circuit in the first circuit unit Q1 may include at least a first driving transistor DTFT1 and a first storage capacitor Cs1
  • the second pixel driving circuit in the second circuit unit Q2 may include at least a second driving transistor DTFT2 and a second storage capacitor Cs2
  • the third pixel driving circuit in the third circuit unit Q3 may include at least a third driving transistor DTFT3 and a third storage capacitor Cs3.
  • the width-to-length ratio (W/L) of the first driving transistor DTFT1 may be greater than that of the second driving transistor DTFT2 , and the width-to-length ratio of the first driving transistor DTFT1 may be greater than that of the third driving transistor DTFT3 .
  • the capacitance value of the first storage capacitor Cs1 may be greater than the capacitance value of the second storage capacitor Cs2 , and the capacitance value of the first storage capacitor Cs1 may be greater than the capacitance value of the third storage capacitor Cs3 .
  • At least one circuit unit may include a high-voltage connection line VDD-C extending along a first direction X (unit row direction) and a high-voltage power line VDD extending along a second direction Y (unit column direction), the high-voltage connection line VDD is connected to a corresponding pixel driving circuit, the high-voltage power line VDD may be connected to the high-voltage connection line VDD-C through a via to form a mesh connection structure for transmitting a high-voltage power signal, and the first direction X and the second direction Y may intersect each other.
  • At least one circuit unit may include a low voltage connection line VSS-C extending along a first direction X and a low voltage power line VSS extending along a second direction Y, the low voltage power line VSS being connected to a corresponding light emitting diode, and the low voltage power line VSS may be connected to the low voltage connection line VSS-C through a via to form a mesh connection structure for transmitting a low voltage power signal.
  • structure A extends along direction B means that structure A may include a main part and a secondary part connected to the main part, the main part is roughly in the shape of a strip extending along a certain direction, the secondary part has no limitation on shape, and the main part is at least 60% of structure A; the main part extends along direction B, and the size of the main part extending along direction B is greater than the size of the secondary part extending along other directions.
  • structure A extends along direction B means “the main part of structure A extends along direction B".
  • FIG5A is a schematic diagram of the structure of a first driving transistor of the present disclosure
  • FIG5B is a schematic diagram of the structure of a second driving transistor of the present disclosure
  • the first driving transistor DTFT1 and the second driving transistor DTFT2 may each include an active layer Active, a gate electrode Gate, a first electrode Source, and a second electrode Drain
  • the active layer Active includes a channel region and a source connection region and a drain connection region located on both sides of the channel region, the overlapping region of the gate electrode Gate and the active layer Active forms a channel region
  • the first electrode Source is connected to the source connection region
  • the second electrode Drain is connected to the drain connection region.
  • the first driving transistor DTFT1 has a first width-to-length ratio
  • the second driving transistor DTFT2 has a second width-to-length ratio
  • the first width-to-length ratio may be greater than the second width-to-length ratio.
  • the gate electrode Gate, the first electrode Source, and the second electrode Drain of the first driving transistor DTFT1 are all comb-shaped.
  • the first sub-transistor has a first channel length L1 and a first sub-width z1
  • the second sub-transistor has a first channel length L1 and a second sub-width z2
  • the third sub-transistor has a first channel length L1 and a third sub-width z3
  • the fourth sub-transistor has a first channel length L1 and a fourth sub-width z4.
  • the first driving transistor DTFT1 has a first channel length L1 and a first channel width W1, and the first channel width W1 is the sum of the first sub-width z1, the second sub-width z2, the third sub-width z3, and the fourth sub-width z4.
  • the gate electrode Gate, the first electrode Source, and the second electrode Drain of the second driving transistor DTFT2 are all strip-shaped, so the second driving transistor DTFT2 has a second channel length L2 and a second channel width W2.
  • the first channel length L1 may be substantially the same as the second channel length L2 , and the first channel width W1 may be greater than the second channel width W2 .
  • a ratio of the first channel width W1 to the second channel width W2 may be approximately 2 to 6.
  • W1/W2 may be approximately 4.
  • the second channel width of the second driving transistor DTFT2 and the third channel width of the third driving transistor DTFT3 may be substantially the same, and the second channel length of the second driving transistor DTFT2 and the third channel length of the third driving transistor DTFT3 may be substantially the same.
  • Fig. 6A is a schematic diagram of the structure of a first storage capacitor of the present disclosure
  • Fig. 6B is a schematic diagram of the structure of a second storage capacitor of the present disclosure.
  • the first storage capacitor Cs1 has a first area
  • the second storage capacitor Cs2 has a second area
  • the first area can be larger than the second area.
  • the first area and the second area may be the areas of the positive projections of the first storage capacitor Cs1 and the second storage capacitor Cs2 on the display substrate plane.
  • the first storage capacitor Cs1 and the second storage capacitor Cs2 may include a plurality of stacked plates, the first area may be the minimum area of the positive projections of the plurality of plates in the first storage capacitor Cs1 on the display substrate plane, and the second area may be the minimum area of the positive projections of the plurality of plates in the second storage capacitor Cs2 on the display substrate plane.
  • the shape of the first storage capacitor Cs1 and the second storage capacitor Cs2 may be polygonal, and the first storage capacitor Cs1 and the second storage capacitor Cs2 may have a first length M1 and a second length M2, respectively.
  • the first length M1 may be the maximum dimension of the first storage capacitor Cs1 and the second storage capacitor Cs2 in the first direction X
  • the second length M2 may be the maximum dimension of the first storage capacitor Cs1 and the second storage capacitor Cs2 in the second direction Y.
  • the first length M1 and the second length M2 may be the projection lengths of the first storage capacitor Cs1 and the second storage capacitor Cs2 when projected onto the plane of the display substrate.
  • the first length M1 of the first storage capacitor Cs1 may be substantially the same as the first length M1 of the second storage capacitor Cs2 , and the second length M2 of the first storage capacitor Cs1 may be greater than the second length M2 of the second storage capacitor Cs2 .
  • the ratio of the second length M2 of the first storage capacitor Cs1 to the second length M2 of the second storage capacitor Cs2 may be approximately 1 to 2.
  • the ratio of the second length M2 of the first storage capacitor Cs1 to the second length M2 of the second storage capacitor Cs2 may be approximately 1.3.
  • the first length M1 of the second storage capacitor Cs2 may be substantially the same as the first length M1 of the third storage capacitor Cs3
  • the second length M2 of the second storage capacitor Cs2 may be substantially the same as the second length M2 of the third storage capacitor Cs3 .
  • the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be sequentially arranged along the first direction X, and the positions of the first light-emitting diode, the second light-emitting diode, and the third light-emitting diode and the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may correspond or may not correspond, which is not limited in the present disclosure.
  • the following is an exemplary explanation through the preparation process of the display substrate.
  • the "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A” or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • the preparation process of the driving circuit layer may include the following operations.
  • Forming a first conductive layer pattern may include: depositing a first conductive film on a substrate, patterning the first conductive film through a patterning process, and forming a first conductive layer pattern disposed on the substrate, as shown in FIG7.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern of each circuit unit may include at least a first electrode plate CF1, a second electrode plate CF2, a third electrode plate CF3, and a third bottom gate electrode Gate3-B.
  • the first plate CF1 may be in an “L” shape, and the first plate CF1 may be disposed at one side of the circuit unit in the second direction Y. In an exemplary embodiment, the first plate CF1 may serve as one plate of the first capacitor.
  • the position, shape, and size of the first plate CF1 in the first circuit unit Q1 , the second circuit unit Q2 , and the third circuit unit Q3 may be substantially the same.
  • the second plate CF2 may be rectangular, the corners of the rectangle may be chamfered, and the second plate CF2 may be disposed in the middle of the circuit unit in the second direction Y. In an exemplary embodiment, the second plate CF2 may serve as a plate of the second capacitor.
  • the position, shape, and size of the second plate CF2 in the first circuit unit Q1 , the second circuit unit Q2 , and the third circuit unit Q3 may be substantially the same.
  • the third plate CF3 may be rectangular, the corners of the rectangle may be chamfered, and the third plate CF3 may be disposed on one side of the circuit unit in the opposite direction of the second direction Y. In an exemplary embodiment, the third plate CF3 may serve as a plate of a storage capacitor.
  • the second electrode plate CF2 in the second direction Y, may be located between the first electrode plate CF1 and the third electrode plate CF3.
  • the position, shape, and size of the third plate CF3 in the second circuit unit Q2 and the third circuit unit Q3 may be substantially the same, but different from the shape and size of the third plate CF3 in the first circuit unit Q1.
  • the area of the third plate CF3 in the first circuit unit Q1 may be greater than the area of the third plate CF3 in the second circuit unit Q2, and the area of the third plate CF3 in the first circuit unit Q1 may be greater than the area of the third plate CF3 in the third circuit unit Q3, so that the capacitance value of the storage capacitor in the first circuit unit Q1 is greater than the capacitance values of the storage capacitors in the second circuit unit Q2 and the third circuit unit Q3.
  • the first length M1 of the third plate CF3 in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be substantially the same, and the second length M2 of the third plate CF3 in the first circuit unit Q1 may be greater than the second length M2 of the third plate CF3 in the second circuit unit Q2 and the third circuit unit Q3, so that the area of the third plate CF3 in the first circuit unit Q1 is greater than the area of the third plate CF3 in the second circuit unit Q2 and the third circuit unit Q3.
  • the first length M1 may be the maximum dimension in the first direction X
  • the second length M2 may be the maximum dimension in the second direction Y.
  • the ratio of the second length M2 of the third plate CF3 in the first circuit unit Q1 to the second length M2 of the third plate CF3 in the second and third circuit units Q2 and Q3 may be about 1 to 2.
  • the ratio may be about 1.3.
  • the edge of the third plate CF3 close to the second plate CF2 in the first circuit unit Q1, the second circuit unit Q2 and the third circuit unit Q3 may be substantially flush, and the distance between the edge of the third plate CF3 close to the second plate CF2 and the edge of the second plate CF2 close to the third plate CF3 in each circuit unit may be substantially the same.
  • the third bottom gate electrode Gate3-B may be used as a bottom gate electrode of a third transistor (driving transistor).
  • the third bottom gate electrode Gate3-B may be located on one side of the first electrode plate CF1 in the opposite direction of the first direction X, and in the second direction Y, the third bottom gate electrode Gate3-B may be located on one side of the second electrode plate CF2 in the second direction Y.
  • the third bottom gate electrode Gate3-B in the first circuit unit Q1 may include a plurality of sub-electrodes, each of which may be in the shape of a strip extending along the first direction X, and the plurality of sub-electrodes may be arranged at intervals along the second direction Y to form a comb-like structure.
  • the third bottom gate electrode Gate3-B in the second circuit unit Q2 and the second circuit unit Q3 may include one sub-electrode to form an "L"-shaped structure.
  • the width-to-length ratio of the driving transistor in the first circuit unit Q1 may be greater than the width-to-length ratio of the driving transistor in the second circuit unit Q2 and the third circuit unit Q3.
  • each sub-electrode in the first circuit unit Q1 may form a first channel length L1 of the transistor
  • the sub-electrodes in the second circuit unit Q2 may form a second channel length L2 of the transistor, and the first channel length L1 and the second channel length L2 may be substantially the same.
  • multiple sub-electrodes in the first circuit unit Q1 can form multiple sub-widths z of the transistor, and the sub-electrodes in the second circuit unit Q2 can form a sub-width z of the transistor.
  • the first channel width of the third transistor in the first circuit unit Q1 4*sub-width z
  • the second channel width of the third transistor in the second circuit unit Q2 sub-width z, so the width-to-length ratio of the third transistor in the first circuit unit Q1 is approximately 4 times the width-to-length ratio of the third transistor in the second circuit unit Q2.
  • the edge of the third bottom gate electrode Gate3-B close to the second electrode plate CF2 in the first circuit unit Q1, the second circuit unit Q2 and the third circuit unit Q3 can be basically flush, and the distance between the edge of the third bottom gate electrode Gate3-B close to the second electrode plate CF2 and the edge of the second electrode plate CF2 close to the third bottom gate electrode Gate3-B in each circuit unit can be basically the same.
  • a plate connection line may be connected to one side of the third electrode plate CF3 in the first direction X or in the opposite direction of the first direction X.
  • the plate connection line may be in the shape of a strip extending along the first direction X.
  • a first end of the plate connection line is connected to the third electrode plate CF3 of the circuit unit.
  • a second end of the plate connection line is connected to the third electrode plate CF3 of the adjacent circuit unit after extending along the first direction X or in the opposite direction of the first direction X, so as to connect the third electrode plates CF3 in a unit row.
  • the plurality of third plates CF3 and the plurality of plate connection lines in a unit row may be interconnected integral structures.
  • the third plate CF3 in each circuit unit is connected to a subsequently formed high-voltage power supply line, by forming the third plates CF3 of adjacent circuit units into an integral structure interconnected, the third plates CF3 of the integral structure may be reused as a high-voltage power supply signal line, and the plurality of third plates CF3 in a unit row may be ensured to have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the first conductive layer pattern may further include a power electrode 11 disposed in the third circuit unit Q3, the power electrode 11 may be in a strip shape extending along the second direction Y, and may be disposed on one side of the third electrode plate CF3 in the first direction X.
  • the power electrode 11 is configured to be connected to a subsequently formed high-voltage power line to achieve connection between the third electrode plate and the high-voltage power line.
  • the third electrode plate CF3 and the power electrode 11 may be an integral structure connected to each other.
  • forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the first conductive layer, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIGS. 8A and 8B , where FIG. 8B is a plan view schematic diagram of the semiconductor layer in FIG. 8A .
  • the semiconductor layer pattern of each circuit unit may include at least the first active layer AT1 of the first transistor T1 to the twelfth active layer AT12 of the twelfth transistor T12 .
  • the first active layer AT1, the second active layer AT2, the fourth active layer AT4, the seventh active layer AT7 and the tenth active layer AT10 may have a strip shape extending along the first direction X
  • the third active layer AT3, the fifth active layer AT5, the sixth active layer AT6, the eighth active layer AT8, the ninth active layer AT9 and the twelfth active layer AT12 may have a strip shape extending along the second direction Y
  • the eleventh active layer AT11 may have a rectangular shape.
  • the first active layer AT1 may be located between the second electrode plate CF2 and the third electrode plate CF3, and the first active layer AT1 may serve as the active layer of the first transistor T1.
  • the second active layer AT2 may be located between the second electrode plate CF2 and the third bottom gate electrode Gate3-B, and the second active layer AT2 may serve as the active layer of the second transistor T2.
  • the orthographic projection of the third active layer AT3 on the substrate at least partially overlaps with the orthographic projection of the third bottom gate electrode Gate3-B on the substrate, and the third active layer AT3 may serve as the active layer of the third transistor T3.
  • the fourth active layer AT4 may be located between the second electrode plate CF2 and the third bottom gate electrode Gate3-B, and located on the side of the second active layer AT2 in the opposite direction of the first direction X, and the fourth active layer AT4 may serve as the active layer of the fourth transistor T4.
  • the fifth active layer AT5 may be located between the third active layer AT3 and the fourth active layer AT4, and the fifth active layer AT5 may serve as the active layer of the fifth transistor T5.
  • the sixth active layer AT6 may be located between the first electrode plate CF1 and the third bottom gate electrode Gate3-B, and the sixth active layer AT6 may be used as the active layer of the sixth transistor T6.
  • the seventh active layer AT7 may be located on one side of the first active layer AT1 in the first direction X, and the seventh active layer AT7 may be used as the active layer of the seventh transistor T7.
  • the eighth active layer AT8 may be located on one side of the first electrode plate CF1 in the opposite direction of the second direction Y, and the eighth active layer AT8 may be used as the active layer of the eighth transistor T8.
  • the ninth active layer AT9 may be located between the first electrode plate CF1 and the eighth active layer AT8, and the ninth active layer AT9 may be used as the active layer of the ninth transistor T9.
  • the tenth active layer AT10 may be located on one side of the seventh active layer AT7 in the second direction Y, and the tenth active layer AT10 may be used as the active layer of the tenth transistor T10.
  • the eleventh active layer AT11 may be located on one side of the tenth active layer AT10 in the second direction Y, and the eleventh active layer AT11 may be used as the active layer of the eleventh transistor T11.
  • the twelfth active layer AT12 may be located between the second active layer AT2 and the third active layer AT3 and at one side of the fifth active layer AT5 in the first direction X.
  • the twelfth active layer AT12 may serve as an active layer of the twelfth transistor T12.
  • the first active layer AT1 and the seventh active layer AT7 may be located on a straight line extending along the first direction X
  • the second active layer AT2 and the fourth active layer AT4 may be located on a straight line extending along the first direction X
  • the fifth active layer AT5 and the twelfth active layer AT12 may be located on a straight line extending along the first direction X.
  • the extension length of the third active layer AT3 in the first circuit unit Q1 may be greater than the extension length of the third active layer AT3 in the second circuit unit Q2 and the third circuit unit Q3, so that the width-to-length ratio of the driving transistor in the first circuit unit Q1 is greater than the width-to-length ratio of the driving transistor in the second circuit unit Q2 and the third circuit unit Q3.
  • the first to twelfth active layers AT1 to AT12 may each include a first region, a second region, and a channel region between the first and second regions, and the first and second regions of a plurality of active layers may each be separately provided.
  • Forming a second insulating layer pattern may include: depositing a second insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film using a patterning process to form a second insulating layer covering the semiconductor layer, wherein a plurality of vias are disposed on the second insulating layer, as shown in FIG. 9 .
  • the plurality of via holes on the second insulating layer in each circuit unit may include at least a first via hole V1 , a second via hole V2 , a third via hole V3 , and a fourth via hole V4 .
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first electrode plate CF1 on the substrate, the second insulating layer and the first insulating layer in the first via hole V1 are etched away to expose the surface of the first electrode plate CF1, and the first via hole V1 is configured to connect a subsequently formed first connecting electrode to the first electrode plate CF1 through the via hole.
  • the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second electrode plate CF2 on the substrate, the second insulating layer and the first insulating layer in the second via hole V2 are etched away to expose the surface of the second electrode plate CF2, and the second via hole V2 is configured to connect a subsequently formed second connecting electrode to the second electrode plate CF2 through the via hole.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the third electrode plate CF3 on the substrate, the second insulating layer and the first insulating layer in the third via hole V3 are etched away to expose the surface of the third electrode plate CF3, and the third via hole V3 is configured to connect a subsequently formed third connecting electrode to the third electrode plate CF3 through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the third bottom gate electrode Gate3-B on the substrate, the second insulating layer and the first insulating layer in the fourth via hole V4 are etched away to expose the surface of the third bottom gate electrode Gate3-B, and the fourth via hole V4 is configured to connect a subsequently formed third top gate electrode to the third bottom gate electrode Gate3-B through the via hole.
  • the plurality of vias on the second insulating layer may further include a fifth via V5.
  • the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the power electrode 11 on the substrate, the second insulating layer and the first insulating layer in the fifth via V5 are etched away, exposing the surface of the power electrode 11, and the fifth via V5 is configured to connect a subsequently formed seventh connection electrode to the power electrode 11 through the via.
  • the first to fifth via holes V1 to V5 may be plural in order to increase connection reliability.
  • Forming a second conductive layer pattern may include: depositing a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming a second conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 10A and 10B , where FIG. 10B is a plan view schematically showing the second conductive layer in FIG. 10A .
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern of each circuit unit includes at least: a fourth electrode plate CF4, a fifth electrode plate CF5, a sixth electrode plate CF6, a first scanning signal line S1, a second scanning signal line S2, a light emitting signal line EM, an initial signal line Vint, a high-frequency signal line Hf, a high-voltage connecting line VDD-C, a low-voltage connecting line VSS-C, a plurality of gate electrodes, and a plurality of connecting electrodes.
  • the shape of the fourth plate CF4 can be an "L" shape, and a notch is provided at one corner.
  • the orthographic projection of the fourth plate CF4 on the substrate at least partially overlaps with the orthographic projection of the first plate CF1 on the substrate.
  • the fourth plate CF4 can serve as another plate of the first capacitor.
  • the first plate CF1 and the fourth plate CF4 constitute a first capacitor of the pixel driving circuit.
  • the position, shape, and size of the fourth plate CF4 in the first circuit unit Q1 , the second circuit unit Q2 , and the third circuit unit Q3 may be substantially the same.
  • the shape of the fifth plate CF5 can be a rectangle with a notch at a corner, the orthographic projection of the fifth plate CF5 on the substrate at least partially overlaps with the orthographic projection of the second plate CF2 on the substrate, the fifth plate CF5 can serve as another plate of the second capacitor, and the second plate CF2 and the fifth plate CF5 constitute a second capacitor of the pixel driving circuit.
  • the position, shape, and size of the fifth plate CF5 in the first circuit unit Q1 , the second circuit unit Q2 , and the third circuit unit Q3 may be substantially the same.
  • the shape of the sixth plate CF6 can be a rectangle with a notch at a corner, the orthographic projection of the sixth plate CF6 on the substrate at least partially overlaps with the orthographic projection of the third plate CF3 on the substrate, the sixth plate CF6 can serve as another plate of the storage capacitor, and the third plate CF3 and the sixth plate CF6 constitute a storage capacitor of the pixel driving circuit.
  • the position, shape, and size of the sixth plate CF6 in the second circuit unit Q2 and the third circuit unit Q3 may be substantially the same, but different from the shape and size of the sixth plate CF6 in the first circuit unit Q1.
  • the area of the sixth plate CF6 in the first circuit unit Q1 may be greater than the area of the sixth plate CF6 in the second circuit unit Q2, and the area of the sixth plate CF6 in the first circuit unit Q1 may be greater than the area of the sixth plate CF6 in the third circuit unit Q3, so that the capacitance value of the storage capacitor in the first circuit unit Q1 is greater than the capacitance values of the storage capacitors in the second circuit unit Q2 and the third circuit unit Q3.
  • the first length M1 of the sixth plate CF6 in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be substantially the same, and the second length M2 of the sixth plate CF6 in the first circuit unit Q1 may be greater than the second length M2 of the sixth plate CF6 in the second circuit unit Q2 and the third circuit unit Q3, so that the area of the sixth plate CF6 in the first circuit unit Q1 is greater than the area of the sixth plate CF6 in the second circuit unit Q2 and the third circuit unit Q3.
  • the ratio of the second length M2 of the sixth plate CF6 in the first circuit unit Q1 to the second length M2 of the sixth plate CF6 in the second circuit unit Q2 and the third circuit unit Q3 may be about 1 to 2.
  • the ratio may be about 1.3.
  • the shapes of the first scan signal line S1, the second scan signal line S2, the light emitting signal line EM, the initial signal line Vint, the high frequency signal line Hf, the high voltage connection line VDD-C and the low voltage connection line VSS-C may be straight lines or folded lines with the main parts extending along the first direction X.
  • the first scan signal line S1, the light emitting signal line EM and the high frequency signal line Hf may be located between the fourth plate CF4 and the fifth plate CF5, the high frequency signal line Hf may be located on one side of the fourth plate CF4 in the second direction Y, the light emitting signal line EM may be located on one side of the high frequency signal line Hf in the second direction Y, and the first scan signal line S1 may be located on one side of the light emitting signal line EM in the second direction Y.
  • the second scan signal line S2 and the initial signal line Vint may be located between the fifth plate CF5 and the sixth plate CF6, the initial signal line Vint may be located on one side of the sixth plate CF6 in the second direction Y, and the second scan signal line S2 may be located on one side of the initial signal line Vint in the second direction Y.
  • the high voltage connection line VDD-C may be located on a side of the third plate CF3 away from the fourth plate CF4
  • the low voltage connection line VSS-C may be located on a side of the sixth plate CF6 away from the fifth plate CF5 .
  • a high-frequency connection block is provided on a side of the high-frequency signal line Hf away from the light-emitting signal line EM, and the high-frequency connection block is configured to be connected to a twenty-sixth connection electrode formed subsequently.
  • a high voltage connection block is disposed on one side of the high voltage connection line VDD-C close to the fourth electrode plate CF4 , and the high voltage connection block is configured to be connected to a sixteenth connection electrode formed subsequently.
  • a low voltage connection block is provided on one side of the low voltage connection line VSS-C close to the sixth electrode plate CF6, and the low voltage connection block is configured to be connected to the subsequently formed thirty-second connection electrode.
  • the low voltage connection block can be provided in the first circuit unit Q1 and the second circuit unit Q2, and the third circuit unit Q3 is not provided with a low voltage connection block.
  • the first scan signal line S1 may be multiplexed as a first control line to control the on and off of the eighth transistor T8
  • the second scan signal line S2 may be multiplexed as a second control line to control the on and off of the tenth transistor T10 .
  • the multiple gate electrodes of each circuit unit may include at least a first gate electrode Gate1, a second gate electrode Gate2, a third top gate electrode Gate3-T, a fourth gate electrode Gate4, a fifth gate electrode Gate5, a sixth gate electrode Gate6, a seventh gate electrode Gate7, an eighth gate electrode Gate8, a ninth gate electrode Gate9, a tenth gate electrode Gate10, an eleventh gate electrode Gate11 and a twelfth gate electrode Gate12.
  • the second gate electrode Gate2, the fourth gate electrode Gate4, and the eighth gate electrode Gate8 may be disposed on a side of the first scan signal line S1 away from the light emitting signal line EM.
  • the second gate electrode Gate2 serves as a gate electrode of the second transistor T2, and an orthographic projection of the second gate electrode Gate2 on the substrate at least partially overlaps with an orthographic projection of the second active layer on the substrate.
  • the fourth gate electrode Gate4 serves as a gate electrode of the fourth transistor T4, and an orthographic projection of the fourth gate electrode Gate4 on the substrate at least partially overlaps with an orthographic projection of the fourth active layer on the substrate.
  • the eighth gate electrode Gate8 serves as a gate electrode of the eighth transistor T8, and an orthographic projection of the eighth gate electrode Gate8 on the substrate at least partially overlaps with an orthographic projection of the eighth active layer on the substrate.
  • the first scan signal line S1 , the second gate electrode Gate2 , the fourth gate electrode Gate4 , and the eighth gate electrode Gate8 may be an integral structure connected to each other.
  • the first gate electrode Gate1 and the seventh gate electrode Gate7 may be disposed on a side of the second scan signal line S2 close to the initial signal line Vint, and the tenth gate electrode Gate10 may be disposed on a side of the second scan signal line S2 away from the initial signal line Vint.
  • the first gate electrode Gate1 serves as a gate electrode of the first transistor T1, and an orthographic projection of the first gate electrode Gate1 on the substrate at least partially overlaps with an orthographic projection of the first active layer on the substrate
  • the seventh gate electrode Gate7 serves as a gate electrode of the seventh transistor T7
  • an orthographic projection of the seventh gate electrode Gate7 on the substrate at least partially overlaps with an orthographic projection of the seventh active layer on the substrate
  • the tenth gate electrode Gate10 serves as a gate electrode of the tenth transistor T10, and an orthographic projection of the tenth gate electrode Gate10 on the substrate at least partially overlaps with an orthographic projection of the tenth active layer on the substrate.
  • the second scan signal line S2 , the first gate electrode Gate1 , the seventh gate electrode Gate7 , and the tenth gate electrode Gate10 may be an integral structure connected to each other.
  • the first gate electrode Gate1, the second gate electrode Gate2, the seventh gate electrode Gate7, the eighth gate electrode Gate8 and the tenth gate electrode Gate10 can be two, forming a first transistor T1, a second transistor T2, a seventh transistor T7, an eighth transistor T8 and a tenth transistor T10 of a double-gate structure, which can enhance the driving capability, improve the current saturation of the light-emitting diode, and prevent and reduce the occurrence of leakage current.
  • the third top gate electrode Gate3-T may serve as the top gate electrode of the third transistor T3, and the orthographic projection of the third top gate electrode Gate3-T on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate.
  • the shape of the third top gate electrode Gate3-T may be substantially the same as the shape of the third bottom gate electrode Gate3-B, the orthographic projection of the third top gate electrode Gate3-T on the substrate at least partially overlaps with the orthographic projection of the third bottom gate electrode Gate3-B on the substrate, and the third top gate electrode Gate3-T is connected to the third bottom gate electrode Gate3-B through the fourth via hole V4.
  • a third gate block 103 is disposed on one side of the third top gate electrode Gate3-T close to the fourth electrode plate CF4.
  • the shape of the third gate block 103 can be a broken line extending along the first direction X.
  • the third gate block 103 is configured to be connected to a twelfth connecting electrode formed subsequently.
  • the fifth gate electrode Gate5 may serve as a gate electrode of the fifth transistor T5, and an orthographic projection of the fifth gate electrode Gate5 on the substrate at least partially overlaps an orthographic projection of the fifth active layer on the substrate.
  • the fifth gate electrode Gate5 may be located between the first scan signal line S1 and the third top gate electrode Gate3-T, and the shape of the fifth gate electrode Gate5 may be a comb shape.
  • a fifth gate block 105 is disposed on one side of the fifth gate electrode Gate5 close to the first scan signal line S1.
  • the fifth gate block 105 may be in the shape of a strip extending along the second direction Y.
  • the fifth gate block 105 is configured to be connected to the subsequently formed twenty-seventh connection electrode.
  • the sixth gate electrode Gate6 can be used as the gate electrode of the sixth transistor T6, and the orthographic projection of the sixth gate electrode Gate6 on the substrate at least partially overlaps with the orthographic projection of the sixth active layer on the substrate.
  • the sixth gate electrode Gate6 can be located between the fourth plate CF4 and the third top gate electrode Gate3-T, and the shape of the sixth gate electrode Gate6 can be comb-shaped.
  • a sixth gate block 106 is disposed on one side of the sixth gate electrode Gate6 close to the first scan signal line S1.
  • the sixth gate block 106 may be shaped like a zigzag line extending along the second direction Y.
  • the sixth gate block 106 is configured to be connected to a subsequently formed twenty-second connection electrode.
  • the ninth gate electrode Gate9 can serve as the gate electrode of the ninth transistor T9, and the orthographic projection of the ninth gate electrode Gate9 on the substrate at least partially overlaps with the orthographic projection of the ninth active layer on the substrate.
  • the ninth gate electrode Gate9 can be located on a side of the fourth plate CF4 close to the first scan signal line S1 and connected to the fourth plate CF4.
  • the fourth plate CF4 and the ninth gate electrode Gate9 may be an integral structure connected to each other.
  • the eleventh gate electrode Gate11 may serve as a gate electrode of the eleventh transistor T11, and an orthographic projection of the eleventh gate electrode Gate11 on the substrate at least partially overlaps an orthographic projection of the eleventh active layer on the substrate.
  • the eleventh gate electrode Gate11 may be located on one side of the fifth plate CF5 in the first direction X, and the shape of the eleventh gate electrode Gate11 may be a folded line extending along the first direction X.
  • the twelfth gate electrode Gate12 may serve as a gate electrode of the twelfth transistor T12, and an orthographic projection of the twelfth gate electrode Gate12 on the substrate at least partially overlaps an orthographic projection of the twelfth active layer on the substrate.
  • the twelfth gate electrode Gate12 may be located between the first scan signal line S1 and the third top gate electrode Gate3-T, and the shape of the twelfth gate electrode Gate12 may be a comb shape.
  • a twelfth gate block 112 is disposed on a side of the twelfth gate electrode Gate12 away from the fifth gate electrode Gate5.
  • the twelfth gate block 112 may be in the shape of a strip extending along the first direction X.
  • the twelfth gate block 112 is configured to be connected to a subsequently formed twenty-third connection electrode.
  • the plurality of connection electrodes of each circuit unit includes at least a first connection electrode CO1 , a second connection electrode CO2 , a third connection electrode CO3 , a fourth connection electrode CO4 , a fifth connection electrode CO5 , and a sixth connection electrode CO6 .
  • the first connection electrode CO1 may be rectangular in shape and may be located at the notch of the fourth electrode plate CF4 .
  • the first connection electrode CO1 is connected to the first electrode plate CF1 through the first via hole V1 .
  • the second connection electrode CO2 may be rectangular in shape and may be located at the notch of the fifth electrode plate CF5 .
  • the second connection electrode CO2 may be connected to the second electrode plate CF2 through the second via hole V2 and may be connected to the eleventh gate electrode Gate11 .
  • the second connection electrode CO2 and the eleventh gate electrode Gate11 may be an integral structure connected to each other.
  • the third connection electrode CO3 may be rectangular in shape and may be located at the notch of the sixth electrode plate CF6 .
  • the third connection electrode CO3 is connected to the third electrode plate CF3 through the third via hole V3 .
  • the shape of the fourth connection electrode CO4 may be a zigzag line extending along the second direction Y.
  • the fourth connection electrode CO4 may be disposed between the fifth gate electrode Gate5 and the twelfth gate electrode Gate12.
  • the fourth connection electrode CO4 may be disposed on one side of the first scan signal line S1 in the second direction Y.
  • the fourth connection electrode CO4 is configured to be connected to the thirteenth connection electrode and the fifteenth connection electrode formed subsequently.
  • the fifth connection electrode CO5 may be in a zigzag shape extending along the first direction X, may be disposed between the first scan signal line S1 and the twelfth gate electrode Gate12 , and is configured to be connected to the nineteenth and twentieth connection electrodes formed subsequently.
  • the sixth connection electrode CO6 may be in a strip shape extending along the first direction X, may be disposed between the second scan signal line S2 and the high-frequency signal line Hf, and is configured to be connected to subsequently formed twenty-fifth and twenty-sixth connection electrodes.
  • the second conductive layer pattern may further include a seventh connection electrode CO7 disposed in the third circuit unit Q3.
  • the shape of the seventh connection electrode CO7 may be rectangular.
  • the seventh connection electrode CO7 is connected to the power electrode 11 through a fifth via hole V5.
  • the seventh connection electrode CO7 is configured to be connected to a thirty-third connection electrode formed subsequently.
  • the second conductive layer can be used as a shield to perform conductorization on the semiconductor layer.
  • the semiconductor layer in the area shielded by the second conductive layer forms the channel region of the first transistor T1 to the twelfth transistor T12, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of the first transistor T1 to the twelfth transistor T12 are both conductorized.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein a plurality of vias are disposed on the third insulating layer, as shown in FIG. 11 .
  • the plurality of via holes on the third insulating layer in each circuit unit includes at least an eleventh via hole V11 to a fifty-eighth via hole V58 .
  • the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the third insulating layer and the second insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first region of the first active layer, and the eleventh via hole V11 is configured to connect a subsequently formed eleventh connecting electrode to the first region of the first active layer through the via hole.
  • the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second region of the first active layer on the substrate, the third insulating layer and the second insulating layer in the twelfth via hole V12 are etched away to expose the surface of the second region of the first active layer, and the twelfth via hole V12 is configured to connect a subsequently formed twelfth connecting electrode to the second region of the first active layer through the via hole.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate, the third insulating layer and the second insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the first region of the second active layer, and the thirteenth via hole V13 is configured to connect a subsequently formed twelfth connecting electrode to the first region of the second active layer through the via hole.
  • the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the third insulating layer and the second insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the second region of the second active layer, and the fourteenth via hole V14 is configured to connect a subsequently formed thirteenth connecting electrode to the second region of the second active layer through the via hole.
  • the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the first area of the third active layer on the substrate, the third insulating layer and the second insulating layer in the fifteenth via hole V15 are etched away to expose the surface of the first area of the third active layer, and the fifteenth via hole V15 is configured to connect a subsequently formed fourteenth connecting electrode to the first area of the third active layer through the via hole.
  • the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the second region of the third active layer on the substrate, the third insulating layer and the second insulating layer in the sixteenth via hole V16 are etched away to expose the surface of the second region of the third active layer, and the sixteenth via hole V16 is configured to connect the subsequently formed fifteenth connecting electrode to the second region of the third active layer through the via hole.
  • the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, the third insulating layer and the second insulating layer in the seventeenth via hole V17 are etched away to expose the surface of the first region of the fourth active layer, and the seventeenth via hole V17 is configured to connect a subsequently formed data signal line to the first region of the fourth active layer through the via hole.
  • the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the second region of the fourth active layer on the substrate, the third insulating layer and the second insulating layer in the eighteenth via hole V18 are etched away to expose the surface of the second region of the fourth active layer, and the eighteenth via hole V18 is configured to connect a subsequently formed fourteenth connecting electrode to the second region of the fourth active layer through the via hole.
  • the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the third insulating layer and the second insulating layer in the nineteenth via hole V19 are etched away to expose the surface of the first region of the fifth active layer, and the nineteenth via hole V19 is configured to connect the subsequently formed sixteenth connecting electrode to the first region of the fifth active layer through the via hole.
  • the orthographic projection of the twentieth via hole V20 on the substrate is located within the range of the orthographic projection of the second region of the fifth active layer on the substrate, the third insulating layer and the second insulating layer in the twentieth via hole V20 are etched away to expose the surface of the second region of the fifth active layer, and the twentieth via hole V20 is configured to connect a subsequently formed fourteenth connecting electrode to the second region of the fifth active layer through the via hole.
  • the nineteenth via hole V19 and the twentieth via hole V20 are both in plural, and the plurality of the nineteenth via holes V19 and the plurality of the twentieth via holes V20 are alternately arranged in the second direction Y.
  • the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the first region of the sixth active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-first via hole V21 are etched away to expose the surface of the first region of the sixth active layer, and the twenty-first via hole V21 is configured to connect the subsequently formed fifteenth connecting electrode to the first region of the sixth active layer through the via hole.
  • the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the second region of the sixth active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-second via hole V22 are etched away to expose the surface of the second region of the sixth active layer, and the twenty-second via hole V22 is configured to connect the subsequently formed seventeenth electrode to the second region of the sixth active layer through the via hole.
  • both the twenty-first via hole V21 and the twenty-second via hole V22 are in plural, and the plurality of the twenty-first via holes V21 and the plurality of the twenty-second via holes V22 are alternately arranged in the second direction Y.
  • the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-third via hole V23 are etched away to expose the surface of the seventh region of the seventh active layer, and the twenty-third via hole V23 is configured to connect the subsequently formed eighteenth connecting electrode to the first region of the seventh active layer through the via hole.
  • the orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the second region of the seventh active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-fourth via hole V24 are etched away to expose the surface of the second region of the seventh active layer, and the twenty-fourth via hole V24 is configured to connect the subsequently formed nineteenth connecting electrode to the second region of the seventh active layer through the via hole.
  • the orthographic projection of the twenty-fifth via hole V25 on the substrate is located within the range of the orthographic projection of the first region of the twelfth active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-fifth via hole V25 are etched away to expose the surface of the first region of the twelfth active layer, and the twenty-fifth via hole V25 is configured to connect the subsequently formed seventeenth electrode to the first region of the twelfth active layer through the via hole.
  • the orthographic projection of the twenty-sixth via hole V26 on the substrate is located within the range of the orthographic projection of the second region of the twelfth active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-sixth via hole V26 are etched away to expose the surface of the second region of the twelfth active layer, and the twenty-sixth via hole V26 is configured to connect a subsequently formed twentieth connecting electrode to the second region of the twelfth active layer through the via hole.
  • both the twenty-fifth via hole V25 and the twenty-sixth via hole V26 are in plural, and the plurality of the twenty-fifth via holes V25 and the plurality of the twenty-sixth via holes V26 are alternately arranged in the second direction Y.
  • the orthographic projection of the twenty-seventh via V27 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-seventh via V27 are etched away to expose the surface of the ninth region of the eighth active layer, and the twenty-seventh via V27 is configured to connect a subsequently formed time-length signal line to the first region of the eighth active layer through the via.
  • the orthographic projection of the twenty-eighth via hole V28 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-eighth via hole V28 are etched away to expose the surface of the second region of the eighth active layer, and the twenty-eighth via hole V28 is configured to connect the subsequently formed twenty-first connecting electrode to the second region of the eighth active layer through the via hole.
  • the orthographic projection of the twenty-ninth via hole V29 on the substrate is located within the range of the orthographic projection of the first region of the ninth active layer on the substrate, the third insulating layer and the second insulating layer in the twenty-ninth via hole V29 are etched away to expose the surface of the first region of the ninth active layer, and the twenty-ninth via hole V29 is configured to connect the subsequently formed twenty-second connecting electrode to the first region of the ninth active layer through the via hole.
  • the orthographic projection of the thirtieth via hole V30 on the substrate is located within the range of the orthographic projection of the second region of the ninth active layer on the substrate, the third insulating layer and the second insulating layer in the thirtieth via hole V30 are etched away to expose the surface of the second region of the ninth active layer, and the thirtieth via hole V30 is configured to connect the subsequently formed twenty-third connecting electrode to the second region of the ninth active layer through the via hole.
  • the orthographic projection of the thirty-first via V31 on the substrate is located within the range of the orthographic projection of the first region of the tenth active layer on the substrate, the third insulating layer and the second insulating layer in the thirty-first via V31 are etched away to expose the surface of the first region of the tenth active layer, and the thirty-first via V31 is configured to connect a subsequently formed time-length signal line to the first region of the tenth active layer through the via.
  • the orthographic projection of the thirty-second via hole V32 on the substrate is located within the range of the orthographic projection of the second region of the tenth active layer on the substrate, the third insulating layer and the second insulating layer in the thirty-second via hole V32 are etched away to expose the surface of the second region of the tenth active layer, and the thirty-second via hole V32 is configured to connect the subsequently formed twenty-fourth connecting electrode to the second region of the tenth active layer through the via hole.
  • the orthographic projection of the thirty-third via hole V33 on the substrate is located within the range of the orthographic projection of the first region of the eleventh active layer on the substrate, the third insulating layer and the second insulating layer in the thirty-third via hole V33 are etched away to expose the surface of the first region of the eleventh active layer, and the thirty-third via hole V33 is configured to connect the subsequently formed twenty-fifth connecting electrode to the first region of the eleventh active layer through the via hole.
  • the orthographic projection of the thirty-fourth via hole V34 on the substrate is located within the range of the orthographic projection of the second region of the eleventh active layer on the substrate, the third insulating layer and the second insulating layer in the thirty-fourth via hole V34 are etched away to expose the surface of the second region of the eleventh active layer, and the thirty-fourth via hole V34 is configured to connect the subsequently formed twenty-third connecting electrode to the second region of the eleventh active layer through the via hole.
  • the orthographic projections of the thirty-fifth via hole V35 and the thirty-sixth via hole V36 on the substrate are located within the range of the orthographic projections of the light-emitting signal line EM on the substrate, the third insulating layer in the thirty-fifth via hole V35 and the thirty-sixth via hole V36 is etched away to expose the surfaces of the light-emitting signal line EM, respectively, and the thirty-fifth via hole V35 and the thirty-sixth via hole V36 are configured to connect the subsequently formed twenty-second connecting electrode and the twenty-seventh connecting electrode to the light-emitting signal line EM, respectively, through the above-mentioned via holes.
  • the orthographic projections of the thirty-seventh via V37, the thirty-eighth via V38 and the thirty-ninth via V39 on the substrate are respectively located within the range of the orthographic projections of the initial signal line Vint on the substrate, the third insulating layer in the thirty-seventh via V37, the thirty-eighth via V38 and the thirty-ninth via V39 is etched away to expose the surfaces of the initial signal line Vint, respectively, and the thirty-seventh via V37, the thirty-eighth via V38 and the thirty-ninth via V39 are configured to connect the subsequently formed eleventh connecting electrode, the eighteenth connecting electrode and the twenty-eighth connecting electrode to the initial signal line Vint through the above-mentioned vias, respectively.
  • the orthographic projection of the 40th via hole V40 on the substrate is located within the range of the orthographic projection of the high-frequency connecting block of the high-frequency signal line Hf on the substrate, the third insulating layer in the 40th via hole V40 is etched away to expose the surface of the high-frequency connecting block, and the 40th via hole V40 is configured to connect the subsequently formed twenty-sixth connecting electrode to the high-frequency signal line Hf through the via hole.
  • the orthographic projection of the forty-first via V41 on the substrate is located within the range of the orthographic projection of the high-voltage connection block of the high-voltage connection line VDD-C on the substrate, the third insulating layer in the forty-first via V41 is etched away to expose the surface of the high-voltage connection block, and the forty-first via V41 is configured to connect the subsequently formed sixteenth connection electrode to the high-voltage connection line VDD-C through the via.
  • the orthographic projection of the forty-second via hole V42 on the substrate is located within the range of the orthographic projection of the fifth electrode plate CF5 on the substrate, the third insulating layer in the forty-second via hole V42 is etched away to expose the surface of the fifth electrode plate CF5, and the forty-second via hole V42 is configured to connect the subsequently formed twenty-eighth connecting electrode to the fifth electrode plate CF5 through the via hole.
  • the orthographic projection of the forty-third via hole V43 on the substrate is located within the range of the orthographic projection of the sixth electrode plate CF6 on the substrate, the third insulating layer in the forty-third via hole V43 is etched away to expose the surface of the sixth electrode plate CF6, and the forty-third via hole V43 is configured to connect the subsequently formed twelfth connecting electrode to the sixth electrode plate CF6 through the via hole.
  • the orthographic projection of the forty-fourth via hole V44 on the substrate is located within the range of the orthographic projection of the first connection electrode CO1 on the substrate, the third insulating layer in the forty-fourth via hole V44 is etched away to expose the surface of the first connection electrode CO1, and the forty-fourth via hole V44 is configured to connect the subsequently formed seventh electrode plate to the first connection electrode CO1 through the via hole.
  • the orthographic projection of the forty-fifth via hole V45 on the substrate is located within the range of the orthographic projection of the second connection electrode CO2 on the substrate, the third insulating layer in the forty-fifth via hole V45 is etched away to expose the surface of the second connection electrode CO2, and the forty-fifth via hole V45 is configured to connect the subsequently formed eighth electrode plate to the second connection electrode CO2 through the via hole.
  • the orthographic projection of the forty-sixth via hole V46 on the substrate is located within the range of the orthographic projection of the third connecting electrode CO3 on the substrate, the third insulating layer in the forty-sixth via hole V46 is etched away to expose the surface of the third connecting electrode CO3, and the forty-sixth via hole V46 is configured to connect the subsequently formed ninth electrode plate to the third connecting electrode CO3 through the via hole.
  • the orthographic projection of the forty-seventh via hole V47 on the substrate is located within the range of the orthographic projection of the first end of the fourth connection electrode CO4 on the substrate, the third insulating layer in the forty-seventh via hole V47 is etched away to expose the surface of the first end of the fourth connection electrode CO4, and the forty-seventh via hole V47 is configured to connect the subsequently formed thirteenth connection electrode to the first end of the fourth connection electrode CO4 through the via hole.
  • the orthographic projection of the forty-eight via hole V48 on the substrate is located within the range of the orthographic projection of the second end of the fourth connection electrode CO4 on the substrate, the third insulating layer in the forty-eight via hole V48 is etched away to expose the surface of the second end of the fourth connection electrode CO4, and the forty-eight via hole V48 is configured to connect the subsequently formed fifteenth connection electrode to the second end of the fourth connection electrode CO4 through the via hole.
  • the orthographic projection of the forty-ninth via hole V49 on the substrate is located within the range of the orthographic projection of the first end of the fifth connection electrode CO5 on the substrate, the third insulating layer in the forty-ninth via hole V49 is etched away to expose the surface of the first end of the fifth connection electrode CO5, and the forty-ninth via hole V49 is configured to connect the subsequently formed twentieth connection electrode to the first end of the fifth connection electrode CO5 through the via hole.
  • the orthographic projection of the fiftieth via hole V50 on the substrate is located within the range of the orthographic projection of the second end of the fifth connecting electrode CO5 on the substrate, the third insulating layer in the fiftieth via hole V50 is etched away to expose the surface of the second end of the fifth connecting electrode CO5, and the fiftieth via hole V50 is configured to connect the subsequently formed nineteenth connecting electrode to the second end of the fifth connecting electrode CO5 through the via hole.
  • the orthographic projection of the fifty-first via hole V51 on the substrate is located within the range of the orthographic projection of the first end of the sixth connection electrode CO6 on the substrate, the third insulating layer in the fifty-first via hole V51 is etched away to expose the surface of the first end of the sixth connection electrode CO6, and the fifty-first via hole V51 is configured to connect the subsequently formed twenty-fifth connection electrode to the first end of the sixth connection electrode CO6 through the via hole.
  • the orthographic projection of the fifty-second via hole V52 on the substrate is located within the range of the orthographic projection of the second end of the sixth connection electrode CO6 on the substrate, the third insulating layer in the fifty-second via hole V52 is etched away to expose the surface of the second end of the sixth connection electrode CO6, and the fifty-second via hole V52 is configured to connect the subsequently formed twenty-sixth connection electrode to the second end of the sixth connection electrode CO6 through the via hole.
  • the orthographic projection of the fifty-third via V53 on the substrate is located within the range of the orthographic projection of the third gate block 103 of the third top gate electrode Gate3-T on the substrate, the third insulating layer in the fifty-third via V53 is etched away to expose the surface of the third gate block 103, and the fifty-third via V53 is configured to connect the subsequently formed twelfth connecting electrode to the third top gate electrode Gate3-T through the via.
  • the orthographic projection of the fifty-fourth via V54 on the substrate is located within the range of the orthographic projection of the fifth gate block 105 of the fifth gate electrode Gate5 on the substrate, the third insulating layer in the fifty-fourth via V54 is etched away to expose the surface of the fifth gate block 105, and the fifty-fourth via V54 is configured to connect the subsequently formed twenty-seventh connecting electrode to the fifth gate electrode Gate5 through the via.
  • the orthographic projection of the fifty-fifth via V55 on the substrate is located within the range of the orthographic projection of the sixth gate block 106 of the sixth gate electrode Gate6 on the substrate, the third insulating layer in the fifty-fifth via V55 is etched away to expose the surface of the sixth gate block 106, and the fifty-fifth via V55 is configured to connect the subsequently formed twenty-second connecting electrode to the sixth gate electrode Gate6 through the via.
  • the orthographic projection of the fifty-sixth via V56 on the substrate is located within the range of the orthographic projection of the twelfth gate block 112 of the twelfth gate electrode Gate12 on the substrate, the third insulating layer in the fifty-sixth via V56 is etched away to expose the surface of the twelfth gate block 112, and the fifty-sixth via V56 is configured to connect a subsequently formed twenty-third connecting electrode to the twelfth gate electrode Gate12 through the via.
  • the orthographic projection of the fifty-seventh via V57 on the substrate is located within the range of the orthographic projection of the ninth gate electrode Gate9 on the substrate, the third insulating layer in the fifty-seventh via V57 is etched away to expose the surface of the ninth gate electrode Gate9, and the fifty-seventh via V57 is configured to connect the subsequently formed twenty-first connecting electrode to the ninth gate electrode Gate9 through the via.
  • the orthographic projection of the fifty-eight via hole V58 on the substrate is located within the range of the orthographic projection of the eleventh gate electrode Gate11 on the substrate, the third insulating layer in the fifty-eight via hole V58 is etched away to expose the surface of the eleventh gate electrode Gate11, and the fifty-eight via hole V58 is configured to connect the subsequently formed twenty-fourth connecting electrode to the eleventh gate electrode Gate11 through the via hole.
  • the plurality of via holes on the third insulating layer may further include fifty-ninth to sixty-second via holes V59 to V62 .
  • the orthographic projection of the fifty-ninth via V59 on the substrate is located within the range of the orthographic projection of the high-voltage connecting line VDD-C in the third circuit unit Q3 on the substrate, the third insulating layer in the fifty-ninth via V59 is etched away to expose the surface of the high-voltage connecting line VDD-C, and the fifty-ninth via V59 is configured to connect the subsequently formed thirty-first connecting electrode to the high-voltage connecting line VDD-C through the via.
  • the orthographic projection of the sixtieth via hole V60 on the substrate is located within the range of the orthographic projection of the low-voltage connection block of the low-voltage connection line VSS-C in the first circuit unit Q1 and the second circuit unit Q2 on the substrate, the third insulating layer in the sixtieth via hole V60 is etched away to expose the surface of the low-voltage connection block, and the sixtieth via hole V60 is configured to connect the subsequently formed thirty-second connection electrode to the low-voltage connection line VSS-C through the via hole.
  • the orthographic projection of the sixty-first via hole V61 on the substrate is located within the range of the orthographic projection of the seventh connection electrode CO7 in the third circuit unit Q3 on the substrate, the third insulating layer in the sixty-first via hole V61 is etched away to expose the surface of the seventh connection electrode CO7, and the sixty-first via hole V61 is configured to connect the subsequently formed thirty-third connection electrode to the seventh connection electrode CO7 through the via hole.
  • the orthographic projection of the sixty-second via hole V62 on the substrate is located within the range of the orthographic projection of the power electrode 11 in the third circuit unit Q3 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the sixty-second via hole V62 are etched away to expose the surface of the power electrode 11, and the sixty-second via hole V62 is configured to connect the subsequently formed thirty-third connecting electrode to the power electrode 11 through the via hole.
  • forming the third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 12A and 12B, wherein FIG. 12B is a plan view schematically showing the third conductive layer in FIG. 12A.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer pattern of each circuit unit includes at least: a data signal line DataI, a time signal line DataT, a seventh electrode plate CF7, an eighth electrode plate CF8, a ninth electrode plate CF9, an anode connection block 12, and an eleventh connection electrode CO11 to a twenty-eighth connection electrode CO28.
  • the shape of the data signal line DataI can be a line shape in which the main part extends along the second direction Y, and can be located on the side opposite to the first direction X of the circuit unit.
  • the data signal line DataI is connected to the first area of the fourth active layer through the seventeenth via hole V17, thereby realizing that the data signal line DataI writes the data signal into the first electrode of the fourth transistor T4.
  • the shape of the time length signal line DataT can be a line shape in which the main part extends along the second direction Y, and can be located on one side of the first direction X of the circuit unit.
  • the time length signal line DataT is connected to the first area of the eighth active layer through the twenty-seventh via V27, and on the other hand, the time length signal line DataT is connected to the first area of the tenth active layer through the thirty-first via V31, thereby realizing that the time length signal line DataT writes the time length signal into the first electrode of the eighth transistor T8 and the first electrode of the tenth transistor T10 respectively.
  • the shape of the seventh electrode plate CF7 may be an "L" shape
  • the orthographic projection of the seventh electrode plate CF7 on the substrate at least partially overlaps the orthographic projection of the fourth electrode plate CF4 on the substrate
  • the seventh electrode plate CF7 is connected to the first connection electrode CO1 through the forty-fourth via hole V44.
  • the seventh electrode plate CF7 may serve as another electrode plate of the first capacitor, and the fourth electrode plate CF4 and the seventh electrode plate CF7 constitute another first capacitor of the pixel driving circuit.
  • the seventh plate CF7 is connected to the first connection electrode CO1 through the forty-fourth via V44, and the first connection electrode CO1 is connected to the first plate CF1 through the via, the first plate CF1 and the seventh plate CF7 have the same potential, so that the first plate CF1, the fourth plate CF4 and the third plate 97 constitute a first capacitor of a parallel structure, the first plate CF1 and the fourth plate CF4 constitute a first capacitor of the pixel driving circuit, the fourth plate CF4 and the seventh plate CF7 constitute another first capacitor of the pixel driving circuit, and the two first capacitors are connected in parallel.
  • the shape of the eighth electrode plate CF8 can be rectangular, the orthographic projection of the eighth electrode plate CF8 on the substrate overlaps at least partially with the orthographic projection of the fifth electrode plate CF5 on the substrate, and the eighth electrode plate CF8 is connected to the second connection electrode CO2 through the forty-fifth via hole V45.
  • the eighth electrode plate CF8 can serve as another electrode plate of the second capacitor, and the fifth electrode plate CF5 and the eighth electrode plate CF8 constitute another second capacitor of the pixel driving circuit.
  • the eighth electrode plate CF8 is connected to the second connecting electrode CO2 through the forty-fifth via V45, and the second connecting electrode CO2 is connected to the second electrode plate CF2 through the via, the second electrode plate CF2 and the eighth electrode plate CF8 have the same potential, so that the second electrode plate CF2, the fifth electrode plate CF5 and the eighth electrode plate CF8 constitute a second capacitor in a parallel structure, the second electrode plate CF2 and the fifth electrode plate CF5 constitute a second capacitor of the pixel driving circuit, the fifth electrode plate CF5 and the eighth electrode plate CF8 constitute another second capacitor of the pixel driving circuit, and the two second capacitors are connected in parallel.
  • the shape of the ninth electrode plate CF9 may be rectangular, the orthographic projection of the ninth electrode plate CF9 on the substrate at least partially overlaps the orthographic projection of the sixth electrode plate CF6 on the substrate, and the ninth electrode plate CF9 is connected to the third connection electrode CO3 through the forty-sixth via hole V46.
  • the ninth electrode plate CF9 may serve as another electrode plate of the storage capacitor, and the sixth electrode plate CF6 and the ninth electrode plate CF9 constitute another storage capacitor of the pixel driving circuit.
  • the ninth plate CF9 is connected to the third connection electrode CO3 through the forty-sixth via V46, and the third connection electrode CO3 is connected to the third plate CF3 through the via, the third plate CF3 and the ninth plate CF9 have the same potential, so that the third plate CF3, the sixth plate CF6 and the ninth plate CF9 constitute a storage capacitor in a parallel structure, the third plate CF3 and the sixth plate CF6 constitute a storage capacitor of the pixel driving circuit, the sixth plate CF6 and the ninth plate CF9 constitute another storage capacitor of the pixel driving circuit, and the two storage capacitors are connected in parallel.
  • the position, shape, and size of the ninth plate CF9 in the second circuit unit Q2 and the third circuit unit Q3 may be substantially the same, but different from the shape and size of the ninth plate CF9 in the first circuit unit Q1.
  • the area of the ninth plate CF9 in the first circuit unit Q1 may be greater than the area of the ninth plate CF9 in the second circuit unit Q2, and the area of the ninth plate CF9 in the first circuit unit Q1 may be greater than the area of the ninth plate CF9 in the third circuit unit Q3, so that the capacitance value of the storage capacitor in the first circuit unit Q1 is greater than the capacitance values of the storage capacitors in the second circuit unit Q2 and the third circuit unit Q3.
  • the first length M1 of the ninth plate CF9 in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be substantially the same, and the second length M2 of the ninth plate CF9 in the first circuit unit Q1 may be greater than the second length M2 of the ninth plate CF9 in the second circuit unit Q2 and the third circuit unit Q3, so that the area of the ninth plate CF9 in the first circuit unit Q1 is greater than the area of the ninth plate CF9 in the second circuit unit Q2 and the third circuit unit Q3.
  • the ratio of the second length M2 of the ninth plate CF9 in the first circuit unit Q1 to the second length M2 of the ninth plate CF9 in the second circuit unit Q2 and the third circuit unit Q3 may be about 1 to 2.
  • the ratio may be about 1.3.
  • the shape of the eleventh connection electrode CO11 can be a strip shape extending along the second direction Y, the first end of the eleventh connection electrode CO11 is connected to the first region of the first active layer through the eleventh via hole V11, and the second end of the eleventh connection electrode CO11 is connected to the initial signal line Vint through the thirty-seventh via hole V37, thereby enabling the initial signal line Vint to write the initial signal into the first electrode of the first transistor T1.
  • the shape of the twelfth connection electrode CO12 may be a strip shape extending along the second direction Y, the first end of the twelfth connection electrode CO12 close to the ninth electrode plate CF9 is connected to the sixth electrode plate CF6 through the forty-third via hole V43, the second end of the twelfth connection electrode CO12 close to the seventh electrode plate CF7 is connected to the third gate block 103 through the fifty-third via hole V53, and the portion between the first end and the second end of the twelfth connection electrode CO12 is connected to the second region of the first active layer through the twelfth via hole V12 on the one hand, and is connected to the first region of the second active layer through the thirteenth via hole V13 on the other hand.
  • the twelfth connection electrode CO12 makes the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the sixth electrode plate CF6 have the same potential (i.e., the third node N3 of the pixel driving circuit), and the twelfth connection electrode CO12 may be referred to as a third node electrode.
  • the thirteenth connection electrode CO13 may have a strip shape extending along the first direction X, a first end of the thirteenth connection electrode CO13 is connected to the second region of the second active layer through a fourteenth via hole V14, and a second end of the thirteenth connection electrode CO13 is connected to a first end of the fourth connection electrode CO4 through a forty-seventh via hole V47.
  • the shape of the fourteenth connection electrode CO14 may be a zigzag line extending along the second direction Y, the first end of the fourteenth connection electrode CO14 is connected to the first region of the third active layer through the fifteenth via hole V15, the second end of the fourteenth connection electrode CO14 is connected to the second region of the fourth active layer through the eighteenth via hole V18, and the portion between the first end and the second end of the fourteenth connection electrode CO14 is connected to the second region of the fifth active layer through the twentieth via hole V20.
  • the fourteenth connection electrode CO14 enables the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5 to have the same potential (i.e., the fifth node N5 of the pixel driving circuit), and the fourteenth connection electrode CO14 may be referred to as a fifth node electrode.
  • the shape of the fifteenth connection electrode CO15 may be a zigzag shape extending along the first direction X, the first end of the fifteenth connection electrode CO15 is connected to the second region of the third active layer through the sixteenth via hole V16, the second end of the fifteenth connection electrode CO15 is connected to the first region of the sixth active layer through the twenty-first via hole V21, and the portion between the first end and the second end of the fifteenth connection electrode CO15 is connected to the second end of the fourth connection electrode CO4 through the forty-eighth via hole V48.
  • the fifteenth connection electrode CO15 enables the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential (i.e., the fourth node N4 of the pixel driving circuit), and the fifteenth connection electrode CO15 may be referred to as a fourth node electrode.
  • the shape of the sixteenth connection electrode CO16 can be a zigzag line extending along the second direction Y, the first end of the sixteenth connection electrode CO16 is connected to the first area of the fifth active layer through the nineteenth via hole V19, and the second end of the sixteenth connection electrode CO16 is connected to the high-voltage connection line VDD-C through the forty-first via hole V41.
  • the shape of the seventeenth connection electrode CO17 can be a zigzag line extending along the second direction Y, the first end of the seventeenth connection electrode CO17 is connected to the second region of the sixth active layer through the twenty-second via hole V22, and the second end of the seventeenth connection electrode CO17 is connected to the first region of the twelfth active layer through the twenty-fifth via hole V25, thereby realizing the connection between the second electrode of the sixth transistor T6 and the first electrode of the twelfth transistor T12.
  • the shape of the eighteenth connection electrode CO18 can be a zigzag line extending along the second direction Y, the first end of the eighteenth connection electrode CO18 is connected to the initial signal line Vint through the thirty-eighth via hole V38, the second end of the eighteenth connection electrode CO18 is connected to the seventh electrode plate CF7, and the portion between the first end and the second end of the eighteenth connection electrode CO18 is connected to the first region of the seventh active layer through the twenty-third via hole V23, so that the initial signal line Vint writes the initial signal into the first electrode of the seventh transistor T7 and one electrode plate of the first capacitor.
  • the shape of the nineteenth connection electrode CO19 can be a zigzag line extending along the second direction Y, the first end of the nineteenth connection electrode CO19 is connected to the second region of the seventh active layer through the twenty-fourth via hole V24, and the second end of the nineteenth connection electrode CO19 is connected to the second end of the fifth connection electrode CO5 through the fiftieth via hole V50.
  • the shape of the twentieth connection electrode CO20 may be a zigzag shape extending along the second direction Y, the first end of the twentieth connection electrode CO20 is connected to the second region of the twelfth active layer through the twenty-sixth via hole V26, and the second end of the twentieth connection electrode CO20 is connected to the first end of the fifth connection electrode CO5 through the forty-ninth via hole V49.
  • the twentieth connection electrode CO20 is connected to the first end of the fifth connection electrode CO5 and the nineteenth connection electrode CO19 is connected to the second end of the fifth connection electrode CO5, the nineteenth connection electrode CO19, the fifth connection electrode CO5 and the twentieth connection electrode CO20 that are connected to each other make the second electrode of the seventh transistor T7 and the second electrode of the twelfth transistor T12 have the same potential (i.e., the second node N2 of the pixel driving circuit).
  • the anode connection block 12 may be disposed on a side of the nineteenth connection electrode CO19 away from the seventh electrode plate CF7 and connected to the nineteenth connection electrode CO19 via a connection line.
  • the anode connection block 12 is configured to be connected to a subsequently formed anode connection electrode.
  • the anode connection block 12 of the first circuit unit Q1 may be located on one side of the ninth plate CF9 in the first direction X
  • the anode connection blocks 12 of the second circuit unit Q2 and the third circuit unit Q3 may be located on one side of the ninth plate CF9 in the opposite direction of the second direction Y.
  • the shape of the twenty-first connection electrode CO21 may be a strip shape extending along the second direction Y, the first end of the twenty-first connection electrode CO21 is connected to the second region of the eighth active layer through the twenty-eighth via hole V28, and the second end of the twenty-first connection electrode CO21 is connected to the ninth gate electrode Gate9 through the fifty-seventh via hole V57. Since the ninth gate electrode Gate9 is connected to the fourth electrode plate CF4, the twenty-first connection electrode CO21 enables the second electrode of the eighth transistor T8, the gate electrode of the ninth transistor T9, and the fourth electrode plate CF4 to have the same potential (i.e., the sixth node N6 of the pixel driving circuit).
  • the shape of the twenty-second connection electrode CO22 can be a strip shape extending along the second direction Y, the first end of the twenty-second connection electrode CO22 is connected to the first area of the ninth active layer through the twenty-ninth via hole V29, the second end of the twenty-second connection electrode CO22 is connected to the light emitting signal line EM through the thirty-fifth via hole V35, and the portion between the first end and the second end of the twenty-second connection electrode CO22 is connected to the sixth gate block 106 of the sixth gate electrode Gate6 through the fifty-fifth via hole V55, thereby realizing that the light emitting signal line EM controls the conduction or disconnection of the sixth transistor T6, and writes the light emitting signal into the first electrode of the ninth transistor T9.
  • the shape of the twenty-third connecting electrode CO23 can be a strip shape extending along the second direction Y, the first end of the twenty-third connecting electrode CO23 is connected to the second area of the ninth active layer through the thirtieth via hole V30, the second end of the twenty-third connecting electrode CO23 is connected to the second area of the eleventh active layer through the thirty-fourth via hole V34, and the portion between the first end and the second end of the twenty-third connecting electrode CO23 is connected to the twelfth gate block 112 of the twelfth gate electrode Gate12 through the fifty-sixth via hole V56, thereby achieving the second electrode of the ninth transistor T9, the second electrode of the eleventh transistor T11 and the gate electrode of the twelfth transistor T12 having the same potential (i.e., the first node N1 of the pixel driving circuit).
  • the shape of the twenty-fourth connection electrode CO24 may be a strip shape extending along the second direction Y, the first end of the twenty-fourth connection electrode CO24 is connected to the second region of the tenth active layer through the thirty-second via hole V32, and the second end of the twenty-fourth connection electrode CO24 is connected to the eleventh gate electrode Gate11 through the fifty-eight via hole V58.
  • the twenty-fourth connection electrode CO24 enables the second electrode of the tenth transistor T10, the gate electrode of the eleventh transistor T11, and the second electrode plate CF2 to have the same potential (i.e., the seventh node N7 of the pixel driving circuit).
  • the shape of the twenty-fifth connection electrode CO25 may be an “L” shape, a first end of the twenty-fifth connection electrode CO25 is connected to the first region of the eleventh active layer through the thirty-third via hole V33, and a second end of the twenty-fifth connection electrode CO25 is connected to the first end of the sixth connection electrode CO6 through the fifty-first via hole V51.
  • the shape of the twenty-sixth connection electrode CO26 may be a strip shape extending along the second direction Y, the first end of the twenty-sixth connection electrode CO26 is connected to the high-frequency signal line Hf through the fortieth via hole V40, and the second end of the twenty-sixth connection electrode CO26 is connected to the second end of the sixth connection electrode CO6 through the fifty-second via hole V52. Since the high-frequency signal line Hf is connected to the first region of the eleventh active layer through the twenty-sixth connection electrode CO26, the sixth connection electrode CO6, and the twenty-fifth connection electrode CO25, the high-frequency signal line Hf writes the high-frequency signal into the first electrode of the eleventh transistor T11.
  • the shape of the twenty-seventh connecting electrode CO27 can be a strip shape extending along the second direction Y, the first end of the twenty-seventh connecting electrode CO27 is connected to the light emitting signal line EM through the thirty-sixth via hole V36, and the second end of the twenty-seventh connecting electrode CO27 is connected to the fifth gate block 105 of the fifth gate electrode Gate5 through the fifty-fourth via hole V54, thereby realizing the light emitting signal line EM controlling the conduction or disconnection of the fifth transistor T5.
  • the shape of the twenty-eighth connecting electrode CO28 can be a strip shape extending along the second direction Y, the first end of the twenty-eighth connecting electrode CO28 is connected to the initial signal line Vint through the thirty-ninth via hole V39, and the second end of the twenty-eighth connecting electrode CO28 is connected to the fifth electrode plate CF5 through the forty-second via hole V42, thereby realizing that the initial signal line Vint writes the initial signal to one electrode plate of the second capacitor.
  • the third conductive layer may further include a thirty-first connection electrode CO31 , a thirty-second connection electrode CO32 , and a thirty-third connection electrode CO33 .
  • the thirty-first connection electrode CO31 may be rectangular in shape and may be disposed in the third circuit unit Q3.
  • the thirty-first connection electrode CO31 is connected to the high-voltage connection line VDD-C in the third circuit unit Q3 through the fifty-ninth via hole V59.
  • the thirty-first connection electrode CO31 is configured to be connected to a high-voltage power supply line formed subsequently.
  • the shape of the thirty-second connection electrode CO32 may be rectangular, and may be disposed in the first circuit unit Q1 and the second circuit unit Q2.
  • the thirty-second connection electrode CO32 is connected to the low voltage connection block of the low voltage connection line VSS-C in the first circuit unit Q1 and the second circuit unit Q2 through the sixtieth via hole V60.
  • the thirty-second connection electrode CO32 is configured to be connected to a low voltage power supply line formed subsequently.
  • the thirty-third connection electrode CO33 may be rectangular in shape and may be disposed in the third circuit unit Q3. On one hand, the thirty-third connection electrode CO33 is connected to the seventh connection electrode CO7 through the sixty-first via hole V61, and on the other hand, the thirty-third connection electrode CO33 is connected to the power electrode 11 through the sixty-second via hole V62. In an exemplary embodiment, the thirty-third connection electrode CO33 is configured to be connected to a high-voltage power line formed subsequently.
  • Forming a fourth insulating layer and a first planar layer pattern may include: first coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process, then depositing a fourth insulating film, patterning the first planar film using a patterning process, forming a first planar layer covering the third conductive layer pattern and a fourth insulating layer disposed on a side of the first planar layer away from the substrate, and a plurality of vias are disposed on the fourth insulating layer and the first planar layer, as shown in FIG. 13 .
  • the plurality of via holes on the fourth insulating layer and the first planarizing layer in each circuit unit includes at least a sixty-fifth via hole V65.
  • the orthographic projection of the sixty-fifth via hole V65 on the substrate is located within the range of the orthographic projection of the anode connection block 12 on the substrate, the fourth insulating film and the first flat film in the sixty-fifth via hole V65 are removed to expose the surface of the anode connection block 12, and the sixty-fifth via hole V65 is configured to connect a subsequently formed anode connection electrode to the anode connection block 12 through the via hole.
  • the plurality of via holes on the fourth insulating layer and the first planar layer may further include a sixty-sixth via hole V66 , a sixty-seventh via hole V67 , and a sixty-eighth via hole V68 .
  • the orthographic projection of the sixty-sixth via hole V66 on the substrate is located within the range of the orthographic projection of the thirty-first connecting electrode CO31 on the substrate, and can be set in the third circuit unit Q3.
  • the fourth insulating film and the first flat film in the sixty-sixth via hole V66 are removed to expose the surface of the thirty-first connecting electrode CO31.
  • the sixty-sixth via hole V66 is configured to connect a subsequently formed high-voltage power line to the thirty-first connecting electrode CO31 through the via hole.
  • the orthographic projection of the sixty-seventh via hole V67 on the substrate is located within the range of the orthographic projection of the thirty-second connecting electrode CO32 on the substrate, and can be respectively arranged in the first circuit unit Q1 and the second circuit unit Q2.
  • the fourth insulating film and the first flat film in the sixty-seventh via hole V67 are removed to expose the surface of the thirty-second connecting electrode CO32.
  • the sixty-seventh via hole V67 is configured to connect a subsequently formed low-voltage power line to the thirty-second connecting electrode CO32 through the via hole.
  • the orthographic projection of the sixty-eight via hole V68 on the substrate is located within the range of the orthographic projection of the thirty-third connecting electrode CO33 on the substrate, and can be set in the third circuit unit Q3.
  • the fourth insulating film and the first flat film in the sixty-eight via hole V68 are removed to expose the surface of the thirty-third connecting electrode CO33.
  • the sixty-eight via hole V68 is configured to connect a subsequently formed high-voltage power line to the thirty-third connecting electrode CO33 through the via hole.
  • forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer pattern disposed on the fourth insulating layer, as shown in FIGS. 14A and 14B , where FIG. 14B is a plan view of the fourth conductive layer in FIG. 14A .
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • the fourth conductive layer pattern of each circuit unit includes at least the anode connection electrode 13 .
  • the shape of the anode connection electrode 13 may be rectangular, and the anode connection electrode 13 is connected to the anode connection block 12 through the sixty-fifth via hole V65, and the anode connection electrode 13 is configured to be bound and connected to the first electrode of the light-emitting diode.
  • the anode connection block 12 is connected to the nineteenth connection electrode CO19, the nineteenth connection electrode CO19 is connected to the twentieth connection electrode CO20 through the fifth connection electrode CO5, and the twentieth connection electrode CO20 is connected to the second region of the twelfth active layer through the via hole, the connection between the anode connection electrode 13 and the second electrode of the seventh transistor T7 and the second electrode of the twelfth transistor T12 is realized, and the pixel driving circuit can drive the light-emitting diode to emit light.
  • the fourth conductive layer pattern may further include at least a high voltage power line VDD and a low voltage power line VSS, the high voltage power line may be referred to as a first power line, and the low voltage power line may be referred to as a second power line.
  • the high-voltage power line VDD may be shaped like a line extending along the second direction Y and may be disposed in the third circuit unit Q3.
  • the high-voltage power line VDD is connected to the thirty-first connection electrode CO31 through the sixty-sixth via hole V66.
  • the high-voltage power line VDD is connected to the thirty-third connection electrode CO33 through the sixty-eighth via hole V68.
  • the thirty-first connection electrode CO31 is connected to the high-voltage connection line VDD-C through a via
  • the high-voltage connection line VDD-C extending along the first direction X and the high-voltage power line VDD extending along the second direction Y form a mesh connection structure, which can not only minimize the resistance of the power transmission line and reduce the voltage drop of the power supply voltage, but also effectively improve the uniformity of the power supply voltage in the display substrate, effectively improve the uniformity within the signal surface, effectively improve the display uniformity, and improve the display quality and display quality.
  • the high-voltage connection line VDD-C is connected to the sixteenth connection electrode CO16 of each circuit unit through the via hole, and the sixteenth connection electrode CO16 is connected to the first area of the fifth active layer through the via hole, the high-voltage power line VDD writes the first power signal to the first electrode of the fifth transistor T5 of each circuit unit.
  • the thirty-third connection electrode CO33 is connected to the power electrode 11 through the seventh connection electrode CO7, the power electrode 11 is connected to the third electrode plate CF3 of the integrated structure, and the third electrode plate CF3 is connected to the ninth electrode plate CF9 through the third connection electrode CO3, the third electrode plate CF3 and the ninth electrode plate CF9 of the storage capacitor have the potential of the high-voltage power line VDD. Since the sixth electrode plate CF6 is connected to the twelfth connection electrode CO12 through the via hole, and the twelfth connection electrode CO12 is connected to the third top gate electrode Gate3-T through the via hole, the sixth electrode plate CF6 has the potential of the gate electrode of the third transistor T3.
  • the third electrode plate CF3 having the potential of the high-voltage power line VDD and the sixth electrode plate CF6 having the potential of the gate electrode of the third transistor T3 constitute a storage capacitor of the pixel driving circuit
  • the sixth electrode plate CF6 having the potential of the gate electrode of the third transistor T3 and the ninth electrode plate CF9 having the potential of the high-voltage power line VDD constitute another storage capacitor of the pixel driving circuit.
  • the positive projection of the high-voltage power line VDD on the substrate overlaps at least partially with the positive projection of the twelfth connection electrode CO12 on the substrate. Since the high-voltage power line VDD is a constant potential, the high-voltage power line VDD can not only effectively shield the influence of data voltage jumps and other signals on key nodes in the pixel driving circuit, but also avoid the influence of data voltage jumps and other signals on the potential of key nodes, effectively avoid crosstalk deterioration, and improve the display effect.
  • the low voltage power line VSS may be in a line shape extending along the second direction Y and may be respectively disposed in the first circuit unit Q1 and the second circuit unit Q2 , and is connected to the thirty-second connection electrode CO32 through the sixty-seventh via hole V67 .
  • the low-voltage connection line VSS-C extending along the first direction X and the low-voltage power line VSS extending along the second direction Y form a mesh connection structure, which can not only minimize the resistance of the power transmission line and reduce the voltage drop of the power supply voltage, but also effectively improve the uniformity of the power supply voltage in the display substrate, effectively improve the uniformity within the signal surface, effectively improve the display uniformity, and improve the display quality and display quality.
  • the positive projection of the low voltage power line VSS on the substrate overlaps at least partially with the positive projection of the twelfth connection electrode CO12 on the substrate. Since the low voltage power line VSS is a constant potential, the low voltage power line VSS can not only effectively shield the influence of data voltage jump and other signals on key nodes in the pixel driving circuit, but also avoid the influence of data voltage jump and other signals on the potential of key nodes, effectively avoid the deterioration of crosstalk, and improve the display effect.
  • forming the fifth insulating layer and the second flat layer pattern may include: first depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fifth insulating film by a patterning process, then coating a second flat film, then depositing a sixth insulating film, patterning the fifth insulating film, the second flat film, and the sixth insulating film by a patterning process to form a fifth insulating layer covering the fourth conductive layer pattern, a second flat layer disposed on a side of the fifth insulating layer away from the substrate, and a sixth insulating layer disposed on a side of the second flat layer away from the substrate, wherein a plurality of binding holes are disposed on the fifth insulating layer, the second flat layer, and the sixth insulating layer, as shown in FIG. 15 .
  • the plurality of binding holes in each circuit unit includes: a first binding hole K1 and a second binding hole K2 .
  • the shape of the first binding hole K1 can be rectangular, and the orthographic projection of the first binding hole K1 on the substrate is located within the range of the orthographic projection of the anode connecting electrode 13 on the substrate.
  • the sixth insulating film, the second flat film and the fifth insulating film in the first binding hole K1 are removed to expose the surface of the anode connecting electrode 13.
  • the area of the anode connecting electrode 13 exposed by the first binding hole K1 can be used as an anode pad.
  • the first binding hole K1 is configured to enable the first pole of the light-emitting diode to be bound and connected to the anode connecting electrode 13 through the binding hole.
  • the shape of the second binding hole K2 can be rectangular, and the orthographic projection of the second binding hole K2 on the substrate is located within the range of the orthographic projection of the low-voltage power line VSS on the substrate.
  • the sixth insulating film, the second flat film and the fifth insulating film in the second binding hole K2 are removed to expose the surface of the low-voltage power line VSS.
  • the area of the low-voltage power line VSS exposed by the second binding hole K2 can be used as a cathode pad, and the second binding hole K2 is configured to connect the second pole of the light-emitting diode to the low-voltage power line VSS through the binding hole.
  • the driving circuit layer of this exemplary embodiment is prepared on the substrate.
  • the driving circuit layer may include a plurality of circuit units, each of which may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a light emitting signal line, a data signal line, a duration signal line, an initial signal line, a high-frequency signal line, and a high-voltage power supply line connected to the pixel driving circuit.
  • the driving circuit layer may include at least a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a first planar layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, and a second planar layer sequentially arranged on the substrate.
  • the substrate may be a flexible substrate or a rigid substrate.
  • the rigid substrate may include, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer.
  • the first planar layer and the second planar layer may be made of organic materials, such as resin, etc.
  • the semiconductor layer may be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.
  • the material of the semiconductor layer may be polycrystalline silicon (p-Si).
  • the subsequent preparation process may include: first, using a dispensing machine to add binding materials (such as solder paste) into a plurality of first binding holes and a plurality of second binding holes, and binding and connecting the first poles of a plurality of light-emitting diodes to the anode connection electrode through the first binding holes by a transfer die bonding process, and binding and connecting the second poles of a plurality of light-emitting diodes to the low-voltage power line through the second binding holes, thereby completing the connection between the light-emitting diodes and the corresponding pixel driving circuit.
  • binding materials such as solder paste
  • a covering film is coated on the substrate forming the aforementioned structure to form a covering layer, and the covering layer covers the plurality of light-emitting diodes.
  • the plurality of light-emitting diodes and the covering layer may constitute a light-emitting structure layer.
  • the display substrate provided by the exemplary embodiment of the present disclosure can well adapt to the differences in light output efficiency and yield between red light-emitting diodes, blue light-emitting diodes and green light-emitting diodes by setting the width-to-length ratio of the third transistor in the first circuit unit to be greater than the width-to-length ratio of the third transistor in the second circuit unit and the third circuit unit. It can not only meet the current value required by the red light-emitting diode, but also achieve more gray scales, thereby avoiding the problem that the brightness of the existing structure does not meet the requirements or cannot achieve more gray scales.
  • the present disclosure can effectively reduce the jump amount of the gate voltage of the third transistor by increasing the capacitance value of the storage capacitor in the first circuit unit, and can ensure the correct writing of the gate voltage.
  • the parasitic capacitance of the third transistor such as the gate-source capacitance Cgs and the gate-drain capacitance Cgd
  • the gate voltage of the third transistor will jump when the gate electrode is disconnected and the light-emitting signal line is turned on due to capacitive coupling, thereby affecting the correct writing of the gate voltage. Since the jump amount of the gate voltage is inversely proportional to the capacitance value of the storage capacitor, increasing the capacitance value of the storage capacitor can effectively reduce the jump amount of the gate voltage of the third transistor.
  • the present disclosure adopts a first capacitor, a second capacitor and a storage capacitor in a parallel structure, and minimizes the occupied space of the first capacitor, the second capacitor and the storage capacitor under the premise of ensuring the capacitance, which is conducive to achieving high-resolution display.
  • the present disclosure forms a high-voltage power line and a low-voltage power line with a network connection structure, which can minimize the resistance of the power transmission line, reduce the voltage drop of the power supply voltage, effectively improve the uniformity of the power supply voltage in the display substrate, effectively improve the uniformity within the signal surface, effectively improve the display uniformity, and improve the display quality and display quality.
  • the preparation process disclosed in the present disclosure can be well compatible with the existing preparation process, the process is simple to implement, easy to implement, high production efficiency, low production cost, and high yield rate.
  • FIG16 is an equivalent circuit diagram of another pixel driving circuit of an exemplary embodiment of the present disclosure, illustrating a 11T3C pixel driving circuit structure.
  • the pixel driving circuit provided by the exemplary embodiment may include at least a current control subcircuit DK and a duration control subcircuit SK.
  • the current control subcircuit DK may include at least a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cs, and the duration control subcircuit SK may include at least an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a first capacitor C1 and a second capacitor C2. Different from the pixel driving circuit shown in FIG3, the twelfth transistor T12 is not provided in the present embodiment, and the duration control subcircuit SK is connected to the gate electrode of the sixth transistor T6.
  • the first node N1 of this embodiment is respectively connected to the gate electrode of the sixth transistor T6, the second electrode of the ninth transistor T9 and the second electrode of the eleventh transistor T11
  • the second node N2 is respectively connected to the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7 and the anode of the light emitting diode EL
  • the other nodes are substantially the same as the structure shown in FIG. 3 .
  • the gate electrode of the sixth transistor T6 is connected to the first node N1
  • the first electrode of the sixth transistor T6 is connected to the fourth node N4
  • the second electrode of the sixth transistor T6 is connected to the second node N2.
  • the connection relationship between the first transistor T1 to the fifth transistor T5, the seventh transistor T7 to the eleventh transistor T11, the first capacitor C1, the second capacitor C2 and the storage capacitor Cs is substantially the same as the structure shown in FIG3, and will not be repeated here.
  • FIG17 is a schematic diagram of the structure of another display substrate of an exemplary embodiment of the present disclosure, illustrating the structure of three circuit units, and the circuit unit includes the pixel driving circuit shown in FIG16.
  • the plurality of circuit units may include at least a first circuit unit Q1, a blank unit KB, a second circuit unit Q2, and a third circuit unit Q3 sequentially arranged along the first direction X, the blank unit KB is configured to set a light emitting diode and transmit light, and no pixel driving circuit is arranged in the blank unit KB.
  • the first pixel driving circuit in the first circuit unit Q1 is configured to be connected to the first light emitting diode
  • the second pixel driving circuit in the second circuit unit Q2 is configured to be connected to the second light emitting diode
  • the third pixel driving circuit in the third circuit unit Q3 is configured to be connected to the third light emitting diode.
  • the first light emitting diode may be a red light emitting diode
  • the second light emitting diode may be a green light emitting diode
  • the third light emitting diode may be a blue light emitting diode.
  • the first pixel driving circuit in the first circuit unit Q1 may include at least a first driving transistor DTFT1 and a first storage capacitor Cs1
  • the second pixel driving circuit in the second circuit unit Q2 may include at least a second driving transistor DTFT2 and a second storage capacitor Cs2
  • the third pixel driving circuit in the third circuit unit Q3 may include at least a third driving transistor DTFT3 and a third storage capacitor Cs3.
  • the width-to-length ratio (W/L) of the first driving transistor DTFT1 may be greater than the width-to-length ratios of the second driving transistor DTFT2 and the third driving transistor DTFT3, and the capacitance value of the first storage capacitor Cs1 may be greater than the capacitance values of the second storage capacitor Cs2 and the third storage capacitor Cs3.
  • At least one circuit unit may include a high-frequency connecting line Hf-C extending along a first direction X and a high-frequency signal line Hf extending along a second direction Y, and the high-frequency signal line Hf may be connected to the high-frequency connecting line Hf-C through a via to form a mesh connection structure for transmitting a high-frequency signal.
  • At least one circuit unit may include a high-voltage connection line VDD-C extending along a first direction X and a high-voltage power line VDD extending along a second direction Y, the high-voltage connection line VDD being connected to a corresponding pixel driving circuit, and the high-voltage power line VDD may be connected to the high-voltage connection line VDD-C through a via to form a mesh connection structure for transmitting a high-voltage power signal.
  • the low voltage connection line may include at least a first low voltage connection line VSS-C1 and a second low voltage connection line VSS-C2, and the low voltage power line may include at least a first low voltage power line VSS1 and a second low voltage power line VSS2.
  • At least one circuit unit may include a first low-voltage connection line VSS-C1 extending along a first direction X and a first low-voltage power line VSS1 extending along a second direction Y, the first low-voltage power line VSS1 being connected to a first light-emitting diode, and the first low-voltage power line VSS1 being connected to the first low-voltage connection line VSS-C1 through a via to form a mesh connection structure for transmitting a first low-voltage power signal.
  • At least one circuit unit may include a second low voltage connection line VSS-C2 extending along a first direction X and a second low voltage power line VSS2 extending along a second direction Y, the second low voltage power line VSS2 being connected to the second light emitting diode and the third light emitting diode, and the second low voltage power line VSS2 may be connected to the second low voltage connection line VSS-C2 through a via to form a mesh connection structure for transmitting a second low voltage power signal.
  • Fig. 18A is a schematic diagram of the structure of another first driving transistor of the present disclosure
  • Fig. 18B is a schematic diagram of the structure of another second driving transistor of the present disclosure.
  • the first driving transistor DTFT1 and the second driving transistor DTFT2 may both include an active layer Active, a gate electrode Gate, a first electrode Source and a second electrode Drain
  • the first driving transistor DTFT1 has a first width-to-length ratio
  • the second driving transistor DTFT2 has a second width-to-length ratio
  • the first width-to-length ratio may be greater than the second width-to-length ratio.
  • the gate electrode Gate, the first electrode Source, and the second electrode Drain are all in a strip shape extending along the first direction X
  • the active layer Active is all in a strip shape extending along the second direction Y
  • the first drive transistor DTFT1 has a first channel length L1 and a first channel width W1
  • the second drive transistor DTFT2 has a second channel length L2 and a second channel width W2
  • the first channel length L1 and the second channel length L2 may be substantially the same
  • the first channel width W1 may be greater than the second channel width W2.
  • a ratio of the first channel width W1 to the second channel width W2 may be approximately 3 or so.
  • the shapes and sizes of the gate electrodes Gate, the first electrodes Source, and the second electrodes Drain of the first driving transistor DTFT1 and the second driving transistor DTFT2 may be substantially the same, and the width of the active layer Active of the first driving transistor DTFT1 may be greater than the width of the active layer Active of the second driving transistor DTFT2, and the width may be the size of the active layer Active in the first direction X.
  • the second channel width of the second driving transistor DTFT2 and the third channel width of the third driving transistor DTFT3 may be substantially the same, and the second channel length of the second driving transistor DTFT2 and the third channel length of the third driving transistor DTFT3 may be substantially the same.
  • Fig. 19A is a schematic diagram of the structure of another first storage capacitor of the present disclosure
  • Fig. 19B is a schematic diagram of the structure of another second storage capacitor of the present disclosure.
  • the first storage capacitor Cs1 has a first area
  • the second storage capacitor Cs2 has a second area
  • the first area can be larger than the second area.
  • the first length M1 of the first storage capacitor Cs1 may be substantially the same as the first length M1 of the second storage capacitor Cs2 , and the second length M2 of the first storage capacitor Cs1 may be greater than the second length M2 of the second storage capacitor Cs2 .
  • a ratio of the second length M2 of the first storage capacitor Cs1 to the second length M2 of the second storage capacitor Cs2 may be approximately 1.8.
  • the first length M1 of the second storage capacitor Cs2 may be substantially the same as the first length M1 of the third storage capacitor Cs3
  • the second length M2 of the second storage capacitor Cs2 may be substantially the same as the second length M2 of the third storage capacitor Cs3 .
  • the process of preparing the driving circuit layer of this embodiment may include the following operations.
  • Forming a first conductive layer pattern may include: depositing a first conductive film on the substrate on which the aforementioned pattern is formed, and patterning the first conductive film through a patterning process to form a first conductive layer pattern disposed on the substrate, as shown in FIG. 20 .
  • the first conductive layer pattern of each circuit unit may include at least a first electrode plate CF1, a second electrode plate CF2, a third electrode plate CF3, and a third bottom gate electrode Gate3-B.
  • the shapes of the first electrode plate CF1, the second electrode plate CF2 and the third electrode plate CF3 can be rectangular, the corners of the rectangle can be chamfered, the first electrode plate CF1 and the second electrode plate CF2 can be arranged on the side of the circuit unit in the opposite direction of the second direction Y, the third bottom gate electrode Gate3-B can be arranged on the side of the circuit unit in the second direction Y, and the third electrode plate CF3 can be located between the first electrode plate CF1 and the third bottom gate electrode Gate3-B.
  • the area of the third plate CF3 in the first circuit unit Q1 may be greater than the area of the third plate CF3 in the second circuit unit Q2, the area of the third plate CF3 in the first circuit unit Q1 may be greater than the area of the third plate CF3 in the third circuit unit Q3, and the position, shape and size of the third plate CF3 in the second circuit unit Q2 and the third circuit unit Q3 may be substantially the same.
  • the first length M1 of the third plate CF3 in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be substantially the same, and the second length M2 of the third plate CF3 in the first circuit unit Q1 may be greater than the second length M2 of the third plate CF3 in the second circuit unit Q2 and the third circuit unit Q3, so that the area of the third plate CF3 in the first circuit unit Q1 is greater than the area of the third plate CF3 in the second circuit unit Q2 and the third circuit unit Q3.
  • the ratio of the second length M2 of the third plate CF3 in the first circuit unit Q1 to the second length M2 of the third plate CF3 in the second and third circuit units Q2 and Q3 may be about 1 to 2.
  • the ratio may be about 1.8.
  • the shape of the third bottom gate electrode Gate3 -B may be an “L” shape, and the shapes of the third bottom gate electrode Gate3 -B in the first circuit unit Q1 , the second circuit unit Q2 , and the third circuit unit Q3 may be substantially the same.
  • the third plates CF3 in one unit row may be connected to each other through plate connection lines, and a plurality of third plates CF3 and a plurality of plate connection lines in one unit row may be an integrated structure connected to each other.
  • forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the first conductive layer, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIGS. 21A and 21B , where FIG. 21B is a plan view schematic diagram of the semiconductor layer in FIG. 21A .
  • the semiconductor layer pattern of each circuit unit may include at least the first active layer AT1 of the first transistor T1 to the eleventh active layer AT11 of the eleventh transistor T11 .
  • the first active layer AT1, the second active layer AT2, the fourth active layer AT4, the seventh active layer AT7, the eighth active layer AT8, the ninth active layer AT9 and the tenth active layer AT10 may have a strip shape extending along the first direction X
  • the third active layer AT3 and the eleventh active layer AT11 may have a rectangular shape
  • the fifth active layer AT5 and the sixth active layer AT6 may have a strip shape extending along the second direction Y.
  • the first active layer AT1, the seventh active layer AT7 to the eleventh active layer AT118 may be located between the first electrode plate CF1 and the third electrode plate CF3.
  • the eighth active layer AT8 may be located on one side of the first electrode plate CF1 in the second direction Y
  • the tenth active layer AT10 may be located on one side of the eighth active layer AT8 in the second direction Y
  • the eleventh active layer AT11 may be located on one side of the tenth active layer AT10 in the second direction Y
  • the first active layer AT1 and the seventh active layer AT7 may be located on one side of the tenth active layer AT10 in the first direction X
  • the first active layer AT1 and the seventh active layer AT7 may be an integral structure connected to each other
  • the ninth active layer AT9 may be located on one side of the eleventh active layer AT11 in the first direction X.
  • the second active layer AT2 to the sixth active layer AT6 may be located on one side of the third electrode plate CF3 in the second direction Y, the orthographic projection of the third active layer AT3 on the substrate at least partially overlaps with the orthographic projection of the third bottom gate electrode Gate3-B on the substrate, the second active layer AT2 may be located on one side of the third active layer AT3 in the first direction X, the fourth active layer AT4 may be located on one side of the third active layer AT3 in the opposite direction of the first direction X, the fifth active layer AT5 and the sixth active layer AT6 may be located between the third electrode plate CF3 and the third active layer AT3, and the sixth active layer AT6 may be located on one side of the fifth active layer AT5 in the first direction X.
  • the width of the third active layer AT3 in the first circuit unit Q1 may be greater than the width of the third active layer AT3 in the second circuit unit Q2 and the third circuit unit Q3, and the width may be the dimension of the third active layer AT3 in the first direction X, so that the width-to-length ratio of the driving transistor in the first circuit unit Q1 is greater than the width-to-length ratio of the driving transistor in the second circuit unit Q2 and the third circuit unit Q3.
  • forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a second insulating layer covering the semiconductor layer, and a second conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 22A and 22B , wherein FIG. 22B is a plan view schematic diagram of the second conductive layer in FIG. 22A .
  • the second conductive layer pattern of each circuit unit includes at least: a fourth electrode plate CF4, a fifth electrode plate CF5, a sixth electrode plate CF6, a first scan signal line S1, a second scan signal line S2, a light emitting signal line EM, a first control line CT1, an initial signal line Vint, a high-frequency connecting line Hf-C, a high-voltage connecting line VDD-C, a first low-voltage connecting line VSS-C1, a second low-voltage connecting line VSS-C2, a plurality of gate electrodes, and a plurality of connecting electrodes.
  • the shape of the fourth plate CF4, the fifth plate CF5 and the sixth plate CF6 can be a rectangular shape with a notch at one corner.
  • the orthographic projection of the fourth plate CF4 on the substrate overlaps at least partially with the orthographic projection of the first plate CF1 on the substrate, and the fourth plate CF4 can be used as another plate of the first capacitor, and the first plate CF1 and the fourth plate CF4 constitute a first capacitor of the pixel driving circuit.
  • the orthographic projection of the fifth plate CF5 on the substrate overlaps at least partially with the orthographic projection of the second plate CF2 on the substrate, and the fifth plate CF5 can be used as another plate of the second capacitor, and the second plate CF2 and the fifth plate CF5 constitute a second capacitor of the pixel driving circuit.
  • the orthographic projection of the sixth plate CF6 on the substrate overlaps at least partially with the orthographic projection of the third plate CF3 on the substrate, and the sixth plate CF6 can be used as another plate of the storage capacitor, and the third plate CF3 and the sixth plate CF6 constitute a storage capacitor of the pixel driving circuit.
  • the position, shape and size of the sixth plate CF6 in the second circuit unit Q2 and the third circuit unit Q3 may be substantially the same, the area of the sixth plate CF6 in the first circuit unit Q1 may be greater than the area of the sixth plate CF6 in the second circuit unit Q2, and the area of the sixth plate CF6 in the first circuit unit Q1 may be greater than the area of the sixth plate CF6 in the third circuit unit Q3, so that the capacitance value of the storage capacitor in the first circuit unit Q1 is greater than the capacitance values of the storage capacitors in the second circuit unit Q2 and the third circuit unit Q3.
  • the first length M1 of the sixth plate CF6 in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be substantially the same, and the second length M2 of the sixth plate CF6 in the first circuit unit Q1 may be greater than the second length M2 of the sixth plate CF6 in the second circuit unit Q2 and the third circuit unit Q3, so that the area of the sixth plate CF6 in the first circuit unit Q1 is greater than the area of the sixth plate CF6 in the second circuit unit Q2 and the third circuit unit Q3.
  • the ratio of the second length M2 of the sixth plate CF6 in the first circuit unit Q1 to the second length M2 of the sixth plate CF6 in the second circuit unit Q2 and the third circuit unit Q3 may be about 1 to 2.
  • the ratio may be about 1.8.
  • the first scan signal line S1, the second scan signal line S2, the light emitting signal line EM, the first control line CT1, the initial signal line Vint, the high frequency connection line Hf-C, the high voltage connection line VDD-C, the first low voltage connection line VSS-C1, and the second low voltage connection line VSS-C may be in a straight line shape or a folded line shape with the main part extending along the first direction X.
  • the first scan signal line S1 may be located on one side of the sixth electrode plate CF6 in the second direction Y
  • the high frequency connection line Hf-C, the first low voltage connection line VSS-C1, and the second low voltage connection line VSS-C may be located on one side of the fourth electrode plate CF4 and the fifth electrode plate CF5 in the opposite direction of the second direction Y
  • the second scan signal line S2 the light emitting signal line EM, the first control line CT1, the initial signal line Vint, and the high voltage connection line VDD-C may be located between the fourth electrode plate CF4 and the sixth electrode plate CF6.
  • the first low voltage connection line VSS-C1 may be located on a side of the fourth electrode plate CF4 and the fifth electrode plate CF5 in an opposite direction to the second direction Y
  • the second low voltage connection line VSS-C may be located on a side of the first low voltage connection line VSS-C1 away from the fourth electrode plate CF4 and the fifth electrode plate CF5
  • the high frequency connection line Hf-C may be located on a side of the second low voltage connection line VSS-C away from the fourth electrode plate CF4 and the fifth electrode plate CF5.
  • the high-voltage connection line VDD-C is configured to be connected to a subsequently formed high-voltage power line to form a mesh-like connection structure.
  • the first low-voltage connection line VSS-C1 is configured to be connected to a subsequently formed first low-voltage power line to form a mesh-like connection structure.
  • the second low-voltage connection line VSS-C2 is configured to be connected to a subsequently formed second low-voltage power line to form a mesh-like connection structure.
  • the high-frequency connection line Hf-C is configured to be connected to a subsequently formed high-frequency signal line to form a mesh-like connection structure.
  • the initial signal line Vint may be located on one side of the fourth electrode plate CF4 and the fifth electrode plate CF5 in the second direction Y
  • the first control line CT1 may be located on one side of the initial signal line Vint in the second direction Y
  • the second scan signal line S2 may be located on one side of the first control line CT1 in the second direction Y
  • the high-voltage connection line VDD-C may be located on one side of the second scan signal line S2 in the second direction Y
  • the light-emitting signal line EM may be located on one side of the second direction Y of the high-voltage connection line VDD-C.
  • the second scan signal line S2 may be multiplexed as a second control line to control turning on and off of the tenth transistor T10 .
  • the multiple gate electrodes of each circuit unit may include at least a first gate electrode Gate1, a second gate electrode Gate2, a third top gate electrode Gate3-T, a fourth gate electrode Gate4, a fifth gate electrode Gate5, a sixth gate electrode Gate6, a seventh gate electrode Gate7, an eighth gate electrode Gate8, a ninth gate electrode Gate9, a tenth gate electrode Gate10 and an eleventh gate electrode Gate11.
  • the second gate electrode Gate2 and the fourth gate electrode Gate4 may be disposed on a side of the first scan signal line S1 close to the sixth electrode plate CF6.
  • the second gate electrode Gate2 serves as the gate electrode of the second transistor T2, and the orthographic projection of the second gate electrode Gate2 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate.
  • the fourth gate electrode Gate4 serves as the gate electrode of the fourth transistor T4, and the orthographic projection of the fourth gate electrode Gate4 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer on the substrate.
  • the first scan signal line S1, the second gate electrode Gate2, and the fourth gate electrode Gate4 may be an integrated structure connected to each other.
  • the first gate electrode Gate1, the seventh gate electrode Gate7, and the tenth gate electrode Gate10 may be disposed on a side of the second scan signal line S2 away from the initial signal line Vint.
  • the first gate electrode Gate1 serves as the gate electrode of the first transistor T1
  • the orthographic projection of the first gate electrode Gate1 on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate
  • the seventh gate electrode Gate7 serves as the gate electrode of the seventh transistor T7
  • the orthographic projection of the seventh gate electrode Gate7 on the substrate at least partially overlaps with the orthographic projection of the seventh active layer on the substrate
  • the tenth gate electrode Gate10 serves as the gate electrode of the tenth transistor T10, and the orthographic projection of the tenth gate electrode Gate10 on the substrate at least partially overlaps with the orthographic projection of the tenth active layer on the substrate.
  • the second scan signal line S2, the first gate electrode Gate1, the seventh gate electrode Gate7, and the tenth gate electrode Gate10 may be an
  • the eighth gate electrode Gate8 may be disposed on a side of the first control line CT1 close to the initial signal line Vint.
  • the eighth gate electrode Gate8 serves as a gate electrode of the eighth transistor T8, and the orthographic projection of the eighth gate electrode Gate8 on the substrate at least partially overlaps with the orthographic projection of the eighth active layer on the substrate.
  • the first control line CT1 and the eighth gate electrode Gate8 may be an integral structure connected to each other.
  • the third top gate electrode Gate3-T can serve as the top gate electrode of the third transistor T3, the orthographic projection of the third top gate electrode Gate3-T on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate, and the orthographic projection of the third top gate electrode Gate3-T on the substrate at least partially overlaps with the orthographic projection of the third bottom gate electrode Gate3-B on the substrate.
  • a third gate block 103 is disposed on one side of the third top gate electrode Gate3-T close to the sixth electrode plate CF6, and the shape of the third gate block 103 may be a folded line extending along the second direction Y, and a first end of the third gate block 103 is connected to the third top gate electrode Gate3-T, and a second end of the third gate block 103 is connected to the sixth electrode plate CF6.
  • the third top gate electrode Gate3-T, the sixth electrode plate CF6, and the third gate block 103 may be an integrated structure connected to each other.
  • the fifth gate electrode Gate5 may be used as a gate electrode of the fifth transistor T5, and the orthographic projection of the fifth gate electrode Gate5 on the substrate at least partially overlaps with the orthographic projection of the fifth active layer on the substrate.
  • the fifth gate electrode Gate5 may be located between the light emitting signal line EM and the third top gate electrode Gate3-T, and located on one side of the third gate block 103 in the opposite direction of the first direction X, and the shape of the fifth gate electrode Gate5 may be comb-shaped.
  • a fifth gate block 105 is disposed on one side of the fifth gate electrode Gate5 close to the light emitting signal line EM, and the fifth gate block 105 may be in the shape of a strip extending along the second direction Y.
  • a first end of the fifth gate block 105 is connected to the fifth gate electrode Gate5, and a second end of the fifth gate block 105 is connected to the light emitting signal line EM, thereby realizing that the light emitting signal line EM can control the conduction or disconnection of the fifth transistor T5.
  • the light emitting signal line EM, the fifth gate electrode Gate5, and the fifth gate block 105 may be an integrated structure connected to each other.
  • the sixth gate electrode Gate6 may be used as a gate electrode of the sixth transistor T6, and the orthographic projection of the sixth gate electrode Gate6 on the substrate at least partially overlaps with the orthographic projection of the sixth active layer on the substrate.
  • the sixth gate electrode Gate6 may be located between the light emitting signal line EM and the third top gate electrode Gate3-T, and located on one side of the third gate block 103 in the first direction X, and the shape of the sixth gate electrode Gate6 may be a comb shape.
  • a sixth gate block 106 is disposed on a side of the sixth gate electrode Gate6 close to the light-emitting signal line EM.
  • the shape of the sixth gate block 106 may be a strip shape extending along the second direction Y.
  • the first end of the sixth gate block 106 is connected to the sixth gate electrode Gate6.
  • the second end of the sixth gate block 106 is close to the light-emitting signal line EM.
  • the sixth gate block 106 is configured to be connected to a sixty-second connecting electrode formed subsequently.
  • the ninth gate electrode Gate9 may serve as a gate electrode of the ninth transistor T9, and an orthographic projection of the ninth gate electrode Gate9 on the substrate at least partially overlaps an orthographic projection of the ninth active layer on the substrate.
  • the ninth gate electrode Gate9 may be located between the second scan signal line S2 and the high-voltage connection line VDD-C, and the shape of the ninth gate electrode Gate9 may be a strip extending along the second direction Y.
  • the eleventh gate electrode Gate11 may serve as a gate electrode of the eleventh transistor T11, and the orthographic projection of the eleventh gate electrode Gate11 on the substrate at least partially overlaps with the orthographic projection of the eleventh active layer on the substrate.
  • the eleventh gate electrode Gate11 may be between the second scan signal line S2 and the high-voltage connection line VDD-C, and the shape of the eleventh gate electrode Gate11 may be a folded line extending along the second direction Y.
  • the plurality of connection electrodes of each circuit unit includes at least a forty-first connection electrode CO41 , a forty-second connection electrode CO42 , a forty-third connection electrode CO43 , a forty-fourth connection electrode CO44 , and a forty-fifth connection electrode CO45 .
  • the forty-first connection electrode CO41 may be in the shape of a strip extending along the first direction X and may be disposed between the second scan signal line S2 and the high-voltage connection line VDD-C.
  • the forty-first connection electrode CO41 is configured to be connected to a subsequently formed high-frequency signal line and a sixty-third connection electrode.
  • the forty-second connection electrode CO42 may be in the shape of a line extending along the first direction X and may be disposed between the second scan signal line S2 and the high voltage connection line VDD-C.
  • the forty-second connection electrode CO42 is configured to be connected to the sixty-first connection electrode and the sixty-second connection electrode formed subsequently.
  • the forty-third connecting electrode CO43 may be in the shape of a line extending along the first direction X, and may be disposed on a side of the high-frequency connecting line Hf-C away from the fourth electrode plate CF4 and the fifth electrode plate CF5, and the forty-third connecting electrode CO43 is configured to be connected to the anode connecting block 12 of the second circuit unit Q2 formed subsequently and the fifty-second connecting electrode of the second circuit unit Q2.
  • the forty-fourth connection electrode CO44 may be in the shape of a line extending along the first direction X, and may be disposed on a side of the forty-third connection electrode CO43 away from the high-frequency connection line Hf-C, and the forty-fourth connection electrode CO44 is configured to be connected to the anode connection block 12 of the third circuit unit Q3 formed subsequently and the fifty-second connection electrode of the third circuit unit Q3.
  • the forty-fifth connection electrode CO45 may be rectangular in shape and may be disposed on one side of the forty-second connection electrode CO42 in the opposite direction of the second direction Y.
  • the forty-fifth connection electrode CO45 is configured to be connected to a sixty-fourth connection electrode formed subsequently.
  • the second conductive layer can be used as a shield to perform conductorization on the semiconductor layer.
  • the semiconductor layer in the area shielded by the second conductive layer forms the channel region of the first transistor T1 to the twelfth transistor T12, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of the first transistor T1 to the eleventh transistor T11 are both conductorized.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein a plurality of vias are disposed on the third insulating layer, as shown in FIG. 23 .
  • the plurality of vias on the third insulating layer in each circuit unit includes at least eleventh to twenty-fourth vias V11 to V24 , twenty-seventh to V27 to V34 , and seventy-seventh to V77 to V99 .
  • the structures of the eleventh to twenty-fourth via holes V11 to V24 and the twenty-seventh to V27 to V34 are substantially the same as those of the aforementioned embodiment, wherein the eleventh to twenty-third via holes V11 and V23 are shared via holes.
  • the orthographic projections of the seventy-seventh via V77 and the seventy-eighth via V78 on the substrate are located within the range of the orthographic projections of the eleventh gate electrode Gate11 on the substrate, the third insulating layer in the seventy-seventh via V77 and the seventy-eighth via V78 is etched away to expose the surface of the eleventh gate electrode Gate11, and the seventy-seventh via V77 and the seventy-eighth via V78 are configured to connect the subsequently formed fifty-ninth connecting electrode and the sixtieth connecting electrode to the eleventh gate electrode Gate11 through the above-mentioned vias, respectively.
  • the orthographic projections of the seventy-ninth via hole V79 and the eightieth via hole V80 on the substrate are located within the range of the orthographic projections of the forty-second connecting electrode CO42 on the substrate, the third insulating layer in the seventy-ninth via hole V79 and the eightieth via hole V80 is etched away to expose the surfaces of the first end and the second end of the forty-second connecting electrode CO42, respectively, and the seventy-ninth via hole V79 and the eightieth via hole V80 are configured to connect the subsequently formed sixty-first connecting electrode and the sixty-second connecting electrode to the forty-second connecting electrode CO42 through the above-mentioned via holes, respectively.
  • the orthographic projection of the eighty-first via hole V81 on the substrate is located within the range of the orthographic projection of the luminous signal line EM on the substrate, the third insulating layer in the eighty-first via hole V81 is etched away to expose the surface of the luminous signal line EM, and the eighty-first via hole V81 is configured to enable the subsequently formed sixty-fourth connecting electrode to be respectively connected to the luminous signal line EM through the via hole.
  • the orthographic projections of the eighty-second via V82, the eighty-third via V83 and the eighty-fourth via V84 on the substrate are respectively located within the range of the orthographic projections of the initial signal line Vint on the substrate, the third insulating layers in the eighty-second via V82, the eighty-third via V83 and the eighty-fourth via V84 are etched away to expose the surfaces of the initial signal line Vint, respectively, and the eighty-second via V82, the eighty-third via V83 and the eighty-fourth via V84 are configured to connect the subsequently formed seventh electrode plate, eighth electrode plate and fifty-first connecting electrode to the initial signal line Vint through the above-mentioned vias, respectively.
  • the orthographic projection of the eighty-fifth via V85 on the substrate is located within the range of the orthographic projection of the high-frequency connecting line Hf-C on the substrate, the third insulating layer in the eighty-fifth via V85 is etched away to expose the surface of the high-frequency connecting line Hf-C, and the eighty-fifth via V85 is configured to connect a subsequently formed high-frequency signal line to the high-frequency connecting line Hf-C through the via.
  • the orthographic projection of the eighty-sixth via V86 on the substrate is located within the range of the orthographic projection of the high-voltage connecting line VDD-C on the substrate, the third insulating layer in the eighty-sixth via V86 is etched away to expose the surface of the high-voltage connecting line VDD-C, and the eighty-sixth via V86 is configured to connect the subsequently formed ninth electrode plate to the high-voltage connecting line VDD-C through the via.
  • the orthographic projection of the eighty-seventh via V87 on the substrate is located within the range of the orthographic projection of the first electrode plate CF1 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the eighty-seventh via V87 are etched away to expose the surface of the first electrode plate CF1, and the eighty-seventh via V87 is configured to connect the subsequently formed seventh electrode plate to the first electrode plate CF1 through the via.
  • the orthographic projection of the eighty-eighth via V88 on the substrate is located within the range of the orthographic projection of the second electrode plate CF2 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the eighty-eighth via V88 are etched away to expose the surface of the second electrode plate CF2, and the eighty-eighth via V88 is configured to connect the subsequently formed eighth electrode plate to the second electrode plate CF2 through the via.
  • the orthographic projection of the eighty-ninth via V89 on the substrate is located within the range of the orthographic projection of the third electrode plate CF3 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the eighty-ninth via V89 are etched away to expose the surface of the third electrode plate CF3, and the eighty-ninth via V89 is configured to connect the subsequently formed ninth electrode plate to the third electrode plate CF3 through the via.
  • the orthographic projection of the ninetieth via hole V90 on the substrate is located within the range of the orthographic projection of the fourth electrode plate CF4 on the substrate, the third insulating layer in the ninetieth via hole V90 is etched away to expose the surface of the fourth electrode plate CF4, and the ninetieth via hole V90 is configured to connect the fifty-eighth connecting electrode formed subsequently to the fourth electrode plate CF4 through the via hole.
  • the orthographic projection of the ninety-first via hole V91 on the substrate is within the range of the orthographic projection of the fifth electrode plate CF5 on the substrate, the third insulating layer in the ninety-first via hole V91 is etched away to expose the surface of the fifth electrode plate CF5, and the ninety-first via hole V91 is configured to connect the subsequently formed fifty-ninth connecting electrode to the fifth electrode plate CF5 through the via hole.
  • the orthographic projection of the ninety-second via hole V92 on the substrate is located within the range of the orthographic projection of the sixth electrode plate CF6 on the substrate, the third insulating layer in the ninety-second via hole V92 is etched away to expose the surface of the sixth electrode plate CF6, and the ninety-second via hole V92 is configured to connect the subsequently formed fifty-seventh connecting electrode to the sixth electrode plate CF6 through the via hole.
  • the orthographic projection of the ninety-third via hole V93 on the substrate is located within the range of the orthographic projection of the first end of the forty-first connecting electrode CO41 on the substrate, the third insulating layer in the ninety-third via hole V93 is etched away to expose the surface of the first end of the forty-first connecting electrode CO41, and the ninety-third via hole V93 is configured to connect a subsequently formed high-frequency connecting line to the forty-first connecting electrode CO41 through the via hole.
  • the orthographic projection of the ninety-fourth via hole V94 on the substrate is located within the range of the orthographic projection of the second end of the forty-first connecting electrode CO41 on the substrate, the third insulating layer in the ninety-fourth via hole V94 is etched away to expose the surface of the second end of the forty-first connecting electrode CO41, and the ninety-fourth via hole V94 is configured to connect the subsequently formed sixty-third connecting electrode to the second end of the forty-first connecting electrode CO41 through the via hole.
  • the orthographic projection of the ninety-fifth via V95 on the substrate is located within the range of the orthographic projection of the third top gate electrode Gate3-T on the substrate, the third insulating layer in the ninety-fifth via V95 is etched away to expose the surface of the third top gate electrode Gate3-T, and the ninety-fifth via V95 is configured to connect the subsequently formed fifty-fifth connecting electrode to the third top gate electrode Gate3-T through the via.
  • the orthographic projection of the ninety-sixth via V96 on the substrate is located within the range of the orthographic projection of the third bottom gate electrode Gate3-B on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the ninety-sixth via V96 are etched away to expose the surface of the third bottom gate electrode Gate3-B, and the ninety-sixth via V96 is configured to connect the subsequently formed fifty-fifth connecting electrode to the third bottom gate electrode Gate3-B through the via.
  • the orthographic projection of the ninety-seventh via V97 on the substrate is located within the range of the orthographic projection of the sixth gate block 106 of the sixth gate electrode Gate6 on the substrate, the third insulating layer in the ninety-seventh via V97 is etched away to expose the surface of the sixth gate block 106, and the ninety-seventh via V97 is configured to connect the subsequently formed sixty-second connecting electrode to the sixth gate electrode Gate6 through the via.
  • the orthographic projection of the ninety-eight via hole V98 on the substrate is located within the range of the orthographic projection of the ninth gate electrode Gate9 on the substrate, the third insulating layer in the ninety-eight via hole V98 is etched away to expose the surface of the ninth gate electrode Gate9, and the ninety-eighth via hole V98 is configured to connect the subsequently formed fifty-eighth connecting electrode to the ninth gate electrode Gate9 through the via hole.
  • the orthographic projection of the ninety-ninth via hole V99 on the substrate is within the range of the orthographic projection of the forty-fifth connecting electrode CO45 on the substrate, the third insulating layer in the ninety-ninth via hole V99 is etched away to expose the surface of the forty-fifth connecting electrode CO45, and the ninety-ninth via hole V99 is configured to connect the subsequently formed sixty-fourth connecting electrode to the forty-fifth connecting electrode CO45.
  • the plurality of via holes on the third insulating layer may further include 101st to 106th via holes V101 to V106.
  • the one-hundred-first via V101 can be arranged in the second circuit unit Q2, the orthographic projection of the one-hundred-first via V101 on the substrate is located within the range of the orthographic projection of the first low-voltage connecting line VSS-C1 on the substrate, the third insulating layer in the one-hundred-first via V101 is etched away to expose the surface of the first low-voltage connecting line VSS-C1, and the one-hundred-first via V101 is configured to connect the seventy-first connecting electrode formed subsequently to the first low-voltage connecting line VSS-C1 through the via.
  • the one-hundred-second via V102 can be arranged in the first circuit unit Q1, the orthographic projection of the one-hundred-second via V102 on the substrate is located within the range of the orthographic projection of the second low-voltage connecting line VSS-C2 on the substrate, the third insulating layer in the one-hundred-second via V102 is etched away to expose the surface of the second low-voltage connecting line VSS-C2, and the one-hundred-second via V102 is configured to connect the seventy-second connecting electrode formed subsequently to the second low-voltage connecting line VSS-C2 through the via.
  • the orthographic projection of the one-hundred and third via hole V103 on the substrate is located within the range of the orthographic projection of the first end of the forty-third connecting electrode CO43 on the substrate, the third insulating layer in the one-hundred and third via hole V103 is etched away to expose the surface of the first end of the forty-third connecting electrode CO43, and the one-hundred and third via hole V103 is configured to connect the anode connecting block of the second circuit unit Q2 formed subsequently to the first end of the forty-third connecting electrode CO43 through the via hole.
  • the orthographic projection of the 104th via hole V104 on the substrate is located within the range of the orthographic projection of the second end of the 43rd connecting electrode CO43 on the substrate, the third insulating layer in the 104th via hole V104 is etched away to expose the surface of the second end of the 43rd connecting electrode CO43, and the 104th via hole V104 is configured to connect the 52nd connecting electrode of the subsequently formed second circuit unit Q2 to the second end of the 43rd connecting electrode CO43 through the via hole.
  • the orthographic projection of the one-hundred-and-fifth via hole V105 on the substrate is located within the range of the orthographic projection of the first end of the forty-fourth connecting electrode CO44 on the substrate, the third insulating layer in the one-hundred-and-fifth via hole V105 is etched away to expose the surface of the first end of the forty-fourth connecting electrode CO44, and the one-hundred-and-fifth via hole V105 is configured to connect the anode connecting block of the subsequently formed third circuit unit Q3 to the first end of the forty-fourth connecting electrode CO44 through the via hole.
  • the orthographic projection of the one-hundred-sixth via hole V106 on the substrate is located within the range of the orthographic projection of the second end of the forty-fourth connecting electrode CO44 on the substrate, the third insulating layer in the one-hundred-sixth via hole V106 is etched away to expose the surface of the second end of the forty-fourth connecting electrode CO44, and the one-hundred-sixth via hole V106 is configured to connect the fifty-second connecting electrode of the third circuit unit Q3 formed subsequently to the second end of the forty-fourth connecting electrode CO44 through the via hole.
  • forming the third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 24A and 24B , where FIG. 24B is a plan view schematic diagram of the third conductive layer in FIG. 24A .
  • the third conductive layer pattern of each circuit unit includes at least: a data signal line DataI, a high-frequency signal line Hf, a seventh electrode plate CF7, an eighth electrode plate CF8, a ninth electrode plate CF9, an anode connection block 12, and a fifty-first connection electrode CO51 to a sixty-fourth connection electrode CO64.
  • the shape of the data signal line DataI can be a line shape in which the main part extends along the second direction Y, and can be located on the side opposite to the first direction X of the circuit unit.
  • the data signal line DataI is connected to the first area of the fourth active layer through the seventeenth via V17 on the one hand, and is connected to the first area of the eighth active layer through the twenty-seventh via V27 on the other hand, and is connected to the first area of the tenth active layer through the thirty-first via V31 on the other hand, thereby realizing that the data signal line DataI writes the data signal into the first electrode of the fourth transistor T4, the first electrode of the eighth transistor T8, and the first electrode of the tenth transistor T10 respectively.
  • the data signal line DataI may be multiplexed as a duration signal line DataT.
  • the data signal line DataI is used to provide a duration signal to the first electrode of the eighth transistor T8 and the first electrode of the tenth transistor T10, respectively.
  • the shape of the high-frequency signal line Hf can be a line shape in which the main part extends along the second direction Y, and can be located on the side opposite to the first direction X of the data signal line DataI.
  • the high-frequency signal line Hf is connected to the first end of the forty-first connecting electrode CO41 through the ninety-third via hole V93, and on the other hand, the high-frequency signal line Hf is connected to the high-frequency connecting line Hf-C through the eighty-fifth via hole V85, thereby realizing the connection between the high-frequency connecting line Hf-C extending along the first direction X and the high-frequency signal line Hf extending along the second direction Y, forming a mesh connection structure for transmitting high-frequency signals.
  • the shape of the seventh plate CF7 can be rectangular, and the orthographic projection of the seventh plate CF7 on the substrate overlaps at least partially with the orthographic projection of the fourth plate CF4 on the substrate.
  • the seventh plate CF7 is connected to the first plate CF1 through the eighty-seventh via hole V87, and on the other hand, the seventh plate CF7 is connected to the initial signal line Vint through the eighty-second via hole V82.
  • the seventh plate CF7 can be used as another plate of the first capacitor, and the fourth plate CF4 and the seventh plate CF7 constitute another first capacitor of the pixel driving circuit.
  • the seventh plate CF7 is connected to the first plate CF1 through the via hole, the first plate CF1 and the seventh plate CF7 have the same initial signal potential, so that the first plate CF1, the fourth plate CF4 and the third plate 97 constitute a first capacitor of a parallel structure, the first plate CF1 and the fourth plate CF4 constitute a first capacitor of the pixel driving circuit, the fourth plate CF4 and the seventh plate CF7 constitute another first capacitor of the pixel driving circuit, and the two first capacitors are connected in parallel.
  • the shape of the eighth plate CF8 can be rectangular, and the orthographic projection of the eighth plate CF8 on the substrate overlaps at least partially with the orthographic projection of the fifth plate CF5 on the substrate.
  • the eighth plate CF8 is connected to the second plate CF2 through the eighty-eighth via hole V88, and on the other hand, the eighth plate CF8 is connected to the initial signal line Vint through the eighty-third via hole V83.
  • the eighth plate CF8 can be used as another plate of the second capacitor, and the fifth plate CF5 and the eighth plate CF8 constitute another second capacitor of the pixel driving circuit.
  • the eighth plate CF8 is connected to the second plate CF2 through the via hole, the second plate CF2 and the eighth plate CF8 have the same initial signal potential, so that the second plate CF2, the fifth plate CF5 and the eighth plate CF8 constitute a second capacitor of a parallel structure, the second plate CF2 and the fifth plate CF5 constitute a second capacitor of the pixel driving circuit, the fifth plate CF5 and the eighth plate CF8 constitute another second capacitor of the pixel driving circuit, and the two second capacitors are connected in parallel.
  • the shape of the ninth electrode plate CF9 can be rectangular, and the orthographic projection of the ninth electrode plate CF9 on the substrate overlaps at least partially with the orthographic projection of the sixth electrode plate CF6 on the substrate.
  • the ninth electrode plate CF9 is connected to the third electrode plate CF3 through the eighty-ninth via hole V89, and on the other hand, the ninth electrode plate CF9 is connected to the high-voltage connection line VDD-C through the eighty-sixth via hole V86.
  • the ninth electrode plate CF9 can be used as another electrode plate of the storage capacitor, and the sixth electrode plate CF6 and the ninth electrode plate CF9 constitute another storage capacitor of the pixel driving circuit.
  • the ninth electrode plate CF9 is connected to the third electrode plate CF3 through the via hole, the third electrode plate CF3 and the ninth electrode plate CF9 have the same first power supply potential, so that the third electrode plate CF3, the sixth electrode plate CF6 and the ninth electrode plate CF9 constitute a storage capacitor of a parallel structure, the third electrode plate CF3 and the sixth electrode plate CF6 constitute a storage capacitor of the pixel driving circuit, the sixth electrode plate CF6 and the ninth electrode plate CF9 constitute another storage capacitor of the pixel driving circuit, and the two storage capacitors are connected in parallel.
  • the position, shape, and size of the ninth plate CF9 in the second circuit unit Q2 and the third circuit unit Q3 may be substantially the same, but different from the shape and size of the ninth plate CF9 in the first circuit unit Q1.
  • the area of the ninth plate CF9 in the first circuit unit Q1 may be greater than the areas of the ninth plate CF9 in the second circuit unit Q2 and the third circuit unit Q3, so that the capacitance value of the storage capacitor in the first circuit unit Q1 is greater than the capacitance value of the storage capacitor in the second circuit unit Q2 and the third circuit unit Q3.
  • the first length M1 of the ninth plate CF9 in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be substantially the same, and the second length M2 of the ninth plate CF9 in the first circuit unit Q1 may be greater than the second length M2 of the ninth plate CF9 in the second circuit unit Q2 and the third circuit unit Q3, so that the area of the ninth plate CF9 in the first circuit unit Q1 is greater than the area of the ninth plate CF9 in the second circuit unit Q2 and the third circuit unit Q3.
  • the ratio of the second length M2 of the ninth plate CF9 in the first circuit unit Q1 to the second length M2 of the ninth plate CF9 in the second circuit unit Q2 and the third circuit unit Q3 may be about 1 to 2.
  • the ratio may be about 1.8.
  • the shape of the fifty-first connection electrode CO51 can be a strip shape extending along the second direction Y, the first end of the fifty-first connection electrode CO51 is connected to the first area of the first active layer (also the first area of the seventh active layer) through the eleventh via hole V11, and the second end of the fifty-first connection electrode CO51 is connected to the initial signal line Vint through the eighty-fourth via hole V84, thereby realizing that the initial signal line Vint writes the initial signal into the first electrode of the first transistor T1 and the first electrode of the seventh transistor T7.
  • the shape of the fifty-second connection electrode CO52 can be a strip shape extending along the second direction Y, the first end of the fifty-second connection electrode CO52 is connected to the second area of the sixth active layer through the twenty-second via hole V22, and the second end of the fifty-second connection electrode CO52 is connected to the second area of the seventh active layer through the twenty-fourth via hole V24, so that the fifty-second connection electrode CO52 makes the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 have the same potential (i.e., the second node N2 of the pixel driving circuit).
  • the anode connection block 12 of the first circuit unit Q1 can be set on a side of the fifty-second connection electrode CO52 of the first circuit unit Q1 away from the ninth electrode plate CF9, and connected to the fifty-second connection electrode CO52 of the first circuit unit Q1 through a connecting wire, thereby realizing the connection between the anode connection block 12 and the fifty-second connection electrode CO52 in the first circuit unit Q1.
  • the anode connection block 12 of the second circuit unit Q2 can be arranged on a side in the opposite direction of the first direction X of the forty-third connection electrode CO43, and the anode connection block 12 is connected to the first end of the forty-third connection electrode CO43 through the one-hundred-and-third via hole V103, and the fifty-second connection electrode CO52 of the second circuit unit Q2 is connected to the second end of the forty-third connection electrode CO43 through the one-hundred-and-fourth via hole V104, thereby realizing the connection between the anode connection block 12 and the fifty-second connection electrode CO52 in the second circuit unit Q2.
  • the anode connection block 12 of the third circuit unit Q3 can be arranged on a side in the opposite direction of the first direction X of the forty-fourth connection electrode CO44, and the anode connection block 12 is connected to the first end of the forty-fourth connection electrode CO44 through the one-hundred-and-fifth via hole V105, and the fifty-second connection electrode CO52 of the third circuit unit Q3 is connected to the second end of the forty-fourth connection electrode CO44 through the one-hundred-and-sixth via hole V106, thereby realizing the connection between the anode connection block 12 and the fifty-second connection electrode CO52 in the third circuit unit Q3.
  • the shape of the fifty-third connecting electrode CO53 is a zigzag line, the first end of the fifty-third connecting electrode CO53 is connected to the second area of the second active layer through the fourteenth via hole V14, the second end of the fifty-third connecting electrode CO53 is connected to the second area of the third active layer through the sixteenth via hole V16, and the portion between the first end and the second end of the fifty-third connecting electrode CO53 is connected to the first area of the sixth active layer through the twenty-first via hole V21.
  • the fifty-third connecting electrode CO53 enables the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential (i.e., the fourth node N4 of the pixel driving circuit).
  • the shape of the fifty-fourth connecting electrode CO54 can be a zigzag line, the first end of the fifty-fourth connecting electrode CO54 is connected to the first area of the third active layer through the fifteenth via hole V15, the second end of the fifty-fourth connecting electrode CO54 is connected to the second area of the fifth active layer through the twentieth via hole V20, and the portion between the first end and the second end of the fifty-fourth connecting electrode CO54 is connected to the second area of the fourth active layer through the eighteenth via hole V18.
  • the fifty-fourth connecting electrode CO54 enables the first electrode of the third transistor T3, the second electrode of the fourth transistor T4 and the second electrode of the fifth transistor T5 to have the same potential (i.e., the fifth node N5 of the pixel driving circuit).
  • the shape of the fifty-fifth connection electrode CO55 may be a zigzag shape, the first end of the fifty-fifth connection electrode CO55 is connected to the first region of the second active layer through the thirteenth via hole V13, the second end of the fifty-fifth connection electrode CO55 is connected to the third top gate electrode Gate3-T through the ninety-fifth via hole V95, and the portion between the first end and the second end of the fifty-fifth connection electrode CO55 is connected to the third bottom gate electrode Gate3-B through the ninety-sixth via hole V96.
  • the fifty-fifth connection electrode CO55 connects the third top gate electrode Gate3-T and the third bottom gate electrode Gate3-B to each other, so that the first electrode of the second transistor T2 and the gate electrode of the third transistor T3 are connected to each other.
  • the shape of the fifty-sixth connecting electrode CO56 can be a zigzag line, the first end of the fifty-sixth connecting electrode CO56 is connected to the first region of the fifth active layer through the nineteenth via hole V19, the second end of the fifty-sixth connecting electrode CO56 is connected to the ninth electrode plate CF9, and the fifty-sixth connecting electrode CO56 enables the first electrode of the fifth transistor T5 and the ninth electrode plate CF9 to have the same potential.
  • the fifty-sixth connection electrode CO56 and the ninth electrode plate CF9 may be an integral structure connected to each other.
  • the shape of the fifty-seventh connection electrode CO57 may be a zigzag extending along the second direction Y, the first end of the fifty-seventh connection electrode CO57 is connected to the second region of the first active layer through the twelfth via hole V12, the second end of the fifty-seventh connection electrode CO57 is connected to the sixth electrode plate CF6 through the ninety-second via hole V92, and the fifty-seventh connection electrode CO57 enables the second electrode of the first transistor T1 and the sixth electrode plate CF6 to have the same potential.
  • the sixth electrode plate CF6 and the third gate block 103 may be an integrated structure connected to each other, the second electrode of the first transistor T1 is connected to the sixth electrode plate CF6, and the first electrode of the second transistor T2 is connected to the gate electrode of the third transistor T3, the fifty-fifth connection electrode CO55 and the fifty-seventh connection electrode CO57 enable the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3 and the sixth electrode plate CF6 to have the same potential (i.e., the third node N3 of the pixel driving circuit).
  • the shape of the fifty-eighth connecting electrode CO58 can be a zigzag line extending along the second direction Y, the first end of the fifty-eighth connecting electrode CO58 is connected to the ninth gate electrode Gate9 through the ninety-eighth via hole V98, the second end of the fifty-eighth connecting electrode CO58 is connected to the fourth electrode plate CF4 through the ninetieth via hole V90, and the portion between the first end and the second end of the fifty-eighth connecting electrode CO58 is connected to the second region of the eighth active layer through the twenty-eighth via hole V28.
  • the fifty-eighth connecting electrode CO58 makes the second electrode of the eighth transistor T8, the gate electrode of the ninth transistor T9 and the fourth electrode plate CF4 have the same potential (i.e., the sixth node N6 of the pixel driving circuit).
  • the shape of the fifty-ninth connecting electrode CO59 can be a strip shape extending along the second direction Y, the first end of the fifty-ninth connecting electrode CO59 is connected to the eleventh gate electrode Gate11 through the seventy-seventh via hole V77, the second end of the fifty-ninth connecting electrode CO59 is connected to the fifth electrode plate CF5 through the ninety-first via hole V91, and the fifty-ninth connecting electrode CO59 enables the gate electrode of the eleventh transistor T11 and the fifth electrode plate CF5 to have the same potential.
  • the shape of the sixtieth connection electrode CO60 may be a strip shape extending along the first direction X, the first end of the sixtieth connection electrode CO60 is connected to the second region of the tenth active layer through the thirty-second via hole V32, the second end of the sixtieth connection electrode CO60 is connected to the eleventh gate electrode Gate11 through the seventy-eighth via hole V78, and the sixtieth connection electrode CO60 enables the gate electrode of the eleventh transistor T11 and the second electrode of the tenth transistor T10 to have the same potential.
  • the fifty-ninth connection electrode CO59 and the sixtieth connection electrode CO60 enable the second electrode of the tenth transistor T10, the gate electrode of the eleventh transistor T11, and the fifth electrode plate CF5 to have the same potential (i.e., the seventh node N7 of the pixel driving circuit).
  • the shape of the sixty-first connection electrode CO61 may be a strip shape extending along the first direction X, the first end of the sixty-first connection electrode CO61 is connected to the second region of the eleventh active layer through the thirty-fourth via hole V34, the second end of the sixty-first connection electrode CO61 is connected to the first end of the forty-second connection electrode CO42 through the seventy-ninth via hole V79, the portion between the first end and the second end of the sixty-first connection electrode CO61 is connected to the second region of the ninth active layer through the thirtieth via hole V30, the sixty-first connection electrode CO61, the sixty-first connection electrode CO61 connects the second electrode of the ninth transistor T9 and the second electrode of the eleventh transistor T11 to each other.
  • the sixty-second connection electrode CO62 may be in a strip shape extending along the second direction Y, a first end of the sixty-second connection electrode CO62 is connected to a second end of the forty-second connection electrode CO42 through an eightieth via hole V80, and a second end of the sixty-second connection electrode CO62 is connected to the sixth gate block 106 through a ninety-seventh via hole V97.
  • the sixth gate block 106 is connected to the sixth gate electrode Gate6, the sixty-first connection electrode CO61 and the sixty-second connection electrode CO62 are connected through the forty-second connection electrode CO42, and thus the sixty-first connection electrode CO61 and the sixty-second connection electrode CO62 make the sixth gate electrode Gate6, the second electrode of the ninth transistor T9, and the second electrode of the eleventh transistor T11 have the same potential (i.e., the first node N1 of the pixel driving circuit).
  • the sixty-third connection electrode CO63 may be in an "L" shape, a first end of the sixty-third connection electrode CO63 is connected to the first region of the eleventh active layer through the thirty-third via hole V33, and a second end of the sixty-third connection electrode CO63 is connected to the second end of the forty-first connection electrode CO41 through the ninety-fourth via hole V94. Since the first end of the forty-first connection electrode CO41 is connected to the high-frequency signal line Hf through the via hole, the high-frequency signal is written into the first electrode of the eleventh transistor T11.
  • the shape of the sixty-fourth connecting electrode CO64 can be an "L" shape
  • the first end of the sixty-fourth connecting electrode CO64 is connected to the first area of the ninth active layer through the twenty-ninth via hole V29
  • the second end of the sixty-fourth connecting electrode CO64 is connected to the light-emitting signal line EM through the eighty-first via hole V81
  • the area between the first end and the second end of the sixty-fourth connecting electrode CO64 is connected to the forty-fifth connecting electrode CO45 through the ninety-ninth via hole V99, thereby realizing the writing of the light-emitting signal into the first pole of the ninth transistor T9.
  • the third conductive layer may further include a seventy-first connection electrode CO71 and a seventy-second connection electrode CO72 .
  • the seventy-first connection electrode CO71 may be in the shape of a strip extending along the second direction Y, the seventy-first connection electrode CO71 may be disposed in the second circuit unit Q2, one end of the seventy-first connection electrode CO71 is connected to the first low-voltage connection line VSS-C1 through the one hundred and first via hole V101, and the seventy-first connection electrode CO71 is configured to be connected to a first power supply low-voltage line formed subsequently.
  • the shape of the seventy-second connection electrode CO72 can be a strip shape extending along the second direction Y, the seventy-second connection electrode CO72 can be set in the first circuit unit Q1, one end of the seventy-second connection electrode CO72 is connected to the second low-voltage connection line VSS-C2 through the one hundred and second via hole V102, and the seventy-second connection electrode CO72 is configured to be connected to the second low-voltage power supply line formed subsequently.
  • Forming a fourth insulating layer and a first planar layer pattern may include: first coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process, then depositing a fourth insulating film, patterning the fourth insulating film using a patterning process, forming a first planar layer covering the third conductive layer pattern and a fourth insulating layer disposed on a side of the first planar layer away from the substrate, and a plurality of vias are disposed on the fourth insulating layer and the first planar layer, as shown in FIG. 25 .
  • the plurality of via holes may include at least a sixty-fifth via hole V65 , a seventieth via hole V70 , a seventy-first via hole V71 , and a seventy-second via hole V72 .
  • the sixty-fifth via hole V65 can be arranged in each circuit unit, the orthographic projection of the sixty-fifth via hole V65 on the substrate is located within the range of the orthographic projection of the anode connection block 12 on the substrate, the fourth insulating film and the first flat film in the sixty-fifth via hole V65 are removed to expose the surface of the anode connection block 12, and the sixty-fifth via hole V65 is configured to connect a subsequently formed anode connection electrode to the anode connection block 12 through the via hole.
  • the orthographic projection of the seventieth via hole V70 on the substrate is located within the range of the orthographic projection of the seventy-first connecting electrode CO71 on the substrate, the fourth insulating film and the first flat film in the seventieth via hole V70 are removed to expose the surface of the seventy-first connecting electrode CO71, and the seventieth via hole V70 is configured to connect a first low-voltage power line formed subsequently to the seventy-first connecting electrode CO71 through the via hole.
  • the orthographic projection of the seventy-first via hole V71 on the substrate is located within the range of the orthographic projection of the seventy-second connecting electrode CO72 on the substrate, the fourth insulating film and the first flat film in the seventy-first via hole V71 are removed to expose the surface of the seventy-second connecting electrode CO72, and the seventy-first via hole V71 is configured to connect a second low-voltage power line formed subsequently to the seventy-second connecting electrode CO72 through the via hole.
  • the orthographic projection of the seventy-second via hole V72 on the substrate is within the range of the orthographic projection of the high-voltage connecting line VDD-C on the substrate, the fourth insulating film, the first flat film and the third insulating layer in the seventy-second via hole V72 are removed to expose the surface of the high-voltage connecting line VDD-C, and the seventy-second via hole V72 is configured to connect a subsequently formed high-voltage power line to the high-voltage connecting line VDD-C through the via hole.
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer pattern disposed on the fourth insulating layer, as shown in FIGS. 26A and 26B , where FIG. 26B is a plan view schematic diagram of the fourth conductive layer in FIG. 26A .
  • the fourth conductive layer pattern may include at least the anode connection electrode 13 , the high voltage power line VDD, the first low voltage power line VSS1 , and the second low voltage power line VSS2 .
  • the shape of the anode connection electrode 13 may be rectangular, the anode connection electrode 13 is connected to the anode connection block 12 through the sixty-fifth via hole V65, and the anode connection electrode 13 is configured to be bound and connected to the first electrode of the light emitting diode.
  • the high-voltage power line VDD may be in the shape of a line extending along the second direction Y, and the high-voltage power line VDD is connected to the high-voltage connection line VDD-C through the seventy-second via V72, thereby realizing the connection between the high-voltage connection line VDD-C extending along the first direction X and the high-voltage power line VDD extending along the second direction Y, thereby forming a mesh connection structure for transmitting a high-voltage power signal.
  • the first low voltage power line VSS1 may be in the shape of a line extending along the second direction Y, and the first low voltage power line VSS1 is connected to the seventy-first connection electrode CO71 through the seventieth via hole V70. Since the seventy-first connection electrode CO71 is connected to the first low voltage connection line VSS-C1 through the via hole, the connection between the first low voltage connection line VSS-C1 extending along the first direction X and the first low voltage power line VSS1 extending along the second direction Y is achieved, forming a mesh connection structure for transmitting the first low voltage power signal.
  • the second low voltage power line VSS2 may be in the shape of a line extending along the second direction Y, and the second low voltage power line VSS2 is connected to the seventy-second connection electrode CO72 through the seventy-first via hole V71. Since the seventy-second connection electrode CO72 is connected to the second low voltage connection line VSS-C2 through the via hole, the connection between the second low voltage connection line VSS-C2 extending along the first direction X and the second low voltage power line VSS2 extending along the second direction Y is realized, forming a mesh connection structure for transmitting the second low voltage power signal.
  • FIG26C is a schematic diagram of a power supply line of an exemplary embodiment of the present disclosure, illustrating the structure of high-voltage power lines and low-voltage power lines in multiple circuit units.
  • the high-voltage power line VDD, the first low-voltage power line VSS1, and the second low-voltage power line VSS2 may be in the shape of a line extending along the second direction Y, and the first low-voltage power line VSS1 and the second low-voltage power line VSS2 are arranged between adjacent high-voltage power lines VDD, and multiple anode connection electrodes 13 may be arranged between the first low-voltage power line VSS1 and the second low-voltage power line VSS2.
  • a first pad block is provided on a side of the first low-voltage power line VSS1 close to the second low-voltage power line VSS2, and the first pad block is configured to connect the second electrode of the first light-emitting diode.
  • a second pad block is provided on a side of the second low-voltage power line VSS2 close to the first low-voltage power line VSS1, and the second pad block is configured to connect the second electrodes of the second light-emitting diode and the third light-emitting diode.
  • the low-voltage power line may include a first low-voltage power line, a second low-voltage power line, and a third low-voltage power line, which respectively provide low-voltage power signals to the first light-emitting diode, the second light-emitting diode, and the third light-emitting diode to minimize power consumption.
  • forming the fifth insulating layer and the second flat layer pattern may include: first depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, then coating a second flat film, then depositing a sixth insulating film, patterning the fifth insulating film, the second flat film, and the sixth insulating film using a patterning process to form a fifth insulating layer covering the fourth conductive layer pattern, a second flat layer disposed on a side of the fifth insulating layer away from the substrate, and a sixth insulating layer disposed on a side of the second flat layer away from the substrate, wherein a plurality of binding holes are disposed on the fifth insulating layer, the second flat layer, and the sixth insulating layer, as shown in FIG. 27 .
  • the plurality of binding holes at least include a plurality of first binding holes K1 and a plurality of second binding holes K2 , and the plurality of first binding holes K1 and the plurality of second binding holes K2 are both located in the region where the blank unit KB is located.
  • the shape of the first binding hole K1 can be rectangular, and the orthographic projection of the first binding hole K1 on the substrate is located within the range of the orthographic projection of the anode connecting electrode 13 on the substrate.
  • the sixth insulating film, the second flat film and the fifth insulating film in the first binding hole K1 are removed to expose the surface of the anode connecting electrode 13.
  • the area of the anode connecting electrode 13 exposed by the first binding hole K1 can be used as an anode pad.
  • the first binding hole K1 is configured to enable the first pole of the light-emitting diode to be bound and connected to the anode connecting electrode 13 through the binding hole.
  • the shape of the second binding hole K2 may be rectangular.
  • the orthographic projection of the second binding hole K2 of the first circuit unit Q1 on the substrate is located within the range of the orthographic projection of the first low-voltage power line VSS1 on the substrate, the sixth insulating film, the second flat film, and the fifth insulating film in the second binding hole K2 are removed, exposing the surface of the first low-voltage power line VSS1, and the area of the first low-voltage power line VSS1 exposed by the second binding hole K2 can be used as a cathode pad connected to the first light-emitting diode, and the second binding hole K2 is configured to connect the second pole of the first light-emitting diode to the first low-voltage power line VSS1 through the binding hole.
  • the orthographic projections of the second binding holes K2 of the second circuit unit Q2 and the second circuit unit Q3 on the substrate are within the range of the orthographic projections of the second low-voltage power line VSS2 on the substrate, the sixth insulating film, the second flat film and the fifth insulating film in the second binding hole K2 are removed to expose the surface of the second low-voltage power line VSS2, and the area of the second low-voltage power line VSS2 exposed by the second binding hole K2 can be used as a cathode pad connecting the second light-emitting diode and the second light-emitting diode, and the second binding hole K2 is configured to connect the second poles of the second light-emitting diode and the third light-emitting diode to the second low-voltage power line VSS2 respectively through the binding hole.
  • the driving circuit layer of this exemplary embodiment is prepared on the substrate.
  • the display substrate provided by the exemplary embodiment of the present disclosure can not only meet the current value required by the red light-emitting diode and realize more gray scales, but also avoid the defects of the existing structure such as the brightness not meeting the requirements or not being able to realize more gray scales, but also effectively reduce the jump amount of the gate voltage of the third transistor, and ensure the correct writing of the gate voltage, by setting the width-to-length ratio of the third transistor in the first circuit unit to be greater than the width-to-length ratio of the third transistor in the second circuit unit and the third circuit unit, and setting the capacitance value of the storage capacitor in the first circuit unit to be greater than the capacitance value of the storage capacitor in the second circuit unit and the third circuit unit.
  • the present disclosure adopts a first capacitor, a second capacitor and a storage capacitor in a parallel structure, and on the premise of ensuring the capacitance, minimizes the occupied space of the first capacitor, the second capacitor and the storage capacitor, which is conducive to achieving high-resolution display.
  • the present disclosure forms a high-frequency signal line with a network connection structure, which can minimize the resistance of the high-frequency signal line, reduce the voltage drop of the high-frequency signal, effectively improve the uniformity of the power supply voltage in the display substrate, and effectively improve the uniformity within the signal surface.
  • the present disclosure forms a high-voltage power line and a low-voltage power line with a network connection structure, which can minimize the resistance of the power transmission line, reduce the voltage drop of the power supply voltage, effectively improve the uniformity of the power supply voltage in the display substrate, effectively improve the uniformity within the signal surface, effectively improve the display uniformity, and improve the display quality and display quality.
  • the present disclosure can effectively reduce power consumption and minimize power consumption by adding a first low-voltage power line and a second low-voltage power line.
  • Studies have shown that when the light-emitting diode is driven to emit light, there is a certain difference in the voltage at both ends of the R chip, the G chip and the B chip. For example, when the emission brightness is the same, the voltage required at both ends of the R chip is about 2V lower than the voltage required at both ends of the B chip. If the low-voltage power supply voltage is designed according to the cross-voltage requirement of the B chip, the cross-voltage of the R chip will exceed the cross-voltage requirement, thereby increasing power consumption.
  • the present disclosure independently designs the low-voltage power supplies of the R chip and the G/B chip, uses the first low-voltage power line to provide the R chip with a first low-voltage power signal, and the second low-voltage power line to provide the G/B chip with a second low-voltage power signal, and controls the low-voltage power supply voltages of different chips respectively. While ensuring the normal driving of the pixel driving circuit, it can effectively reduce power consumption and minimize power consumption.
  • FIG28 is a schematic diagram of the structure of another display substrate of an exemplary embodiment of the present disclosure, illustrating the structure of three circuit units, wherein the circuit units include the pixel driving circuit shown in FIG16.
  • the plurality of circuit units may include at least a first circuit unit Q1, a second circuit unit Q2, and a third circuit unit Q3 sequentially arranged along the first direction X, wherein the first pixel driving circuit in the first circuit unit Q1 is configured to be connected to the first light emitting diode, the second pixel driving circuit in the second circuit unit Q2 is configured to be connected to the second light emitting diode, the third pixel driving circuit in the third circuit unit Q3 is configured to be connected to the third light emitting diode, the first light emitting diode may be a red light emitting diode, the second light emitting diode may be a green light emitting diode, and the third light emitting diode may be a blue light emitting diode.
  • the aspect ratio of the first driving transistor DTFT1 may be greater than that of the second driving transistor DTFT2 and the third driving transistor DTFT3, and the capacitance value of the first storage capacitor Cs1 may be substantially the same as that of the second storage capacitor Cs2 and the third storage capacitor Cs3.
  • At least one circuit unit may include a high-frequency connecting line Hf-C extending along a first direction X and a high-frequency signal line Hf extending along a second direction Y, and the high-frequency signal line Hf may be connected to the high-frequency connecting line Hf-C through a via to form a mesh connection structure for transmitting a high-frequency signal.
  • At least one circuit unit may include a high-voltage connection line VDD-C extending along a first direction X and a high-voltage power line VDD extending along a second direction Y, the high-voltage connection line VDD being connected to a corresponding pixel driving circuit, and the high-voltage power line VDD may be connected to the high-voltage connection line VDD-C through a via to form a mesh connection structure for transmitting a high-voltage power signal.
  • At least one circuit unit may include a low voltage connection line VSS-C extending along a first direction X and a low voltage power line VSS extending along a second direction Y, and the low voltage power line VSS may be connected to the low voltage connection line VSS-C through a via to form a mesh connection structure for transmitting a low voltage power signal.
  • the structure of the driving transistor of this embodiment can be substantially the same as the structure of the driving transistor shown in FIG. 17
  • the structure of the storage capacitor of this embodiment can be substantially the same as the structure of the storage capacitor shown in FIG. 17 , except that the areas of the first storage capacitor Cs1, the second storage capacitor Cs2, and the third storage capacitor Cs3 can be substantially the same.
  • the process of preparing the driving circuit layer of this embodiment may include the following operations.
  • the first conductive layer pattern of each circuit unit may include at least: a first electrode plate CF1, a second electrode plate CF2, a third electrode plate CF3 and a third bottom gate electrode Gate3-B, as shown in FIG. 29 .
  • the shapes of the first electrode plate CF1, the second electrode plate CF2 and the third electrode plate CF3 may be rectangular, the corners of the rectangular shape may be chamfered, the first electrode plate CF1 and the second electrode plate CF2 may be arranged on one side of the circuit unit in the opposite direction of the second direction Y, the third bottom gate electrode Gate3-B may be arranged on one side of the circuit unit in the second direction Y, and the third electrode plate CF3 may be located between the first electrode plate CF1 and the third bottom gate electrode Gate3-B.
  • the first electrode plate CF1 is arranged on one side of the second electrode plate CF2 in the first direction X.
  • the position and shape of the third plate CF3 in the three circuit units may be substantially the same, the first length M1 and the second length M2 of the third plate CF3 in the three circuit units may be substantially the same, and the area of the third plate CF3 in the three circuit units may be substantially the same.
  • the position, shape, and size of the third bottom gate electrode Gate3 -B may be substantially the same as the structure shown in FIG. 20 .
  • each circuit unit may include at least the first active layer AT1 of the first transistor T1 to the eleventh active layer AT11 of the eleventh transistor T11 , as shown in FIG. 30 .
  • the positions and shapes of the first to eleventh active layers AT1 to AT11 may be substantially the same as those of the structures shown in FIGS. 21A and 21B , except that the tenth active layer AT10 may be located on one side of the second direction Y of the second electrode plate CF2, and the eighth active layer AT8 may be located on one side of the second direction Y of the tenth active layer AT10.
  • the second conductive layer pattern of each circuit unit at least includes: a fourth electrode plate CF4, a fifth electrode plate CF5, a sixth electrode plate CF6, a first scanning signal line S1, a second scanning signal line S2, a light emitting signal line EM, a second control line CT2, an initial signal line Vint, a high-frequency connection line Hf-C, a high-voltage connection line VDD-C, a low-voltage connection line VSS-C, a plurality of gate electrodes and a plurality of connection electrodes, as shown in FIG. 31 .
  • the positions of the fourth electrode plate CF4, the fifth electrode plate CF5 and the sixth electrode plate CF6 can be substantially the same as the structures shown in Figures 22A and 22B, except that the fourth electrode plate CF4 is arranged on one side of the fifth electrode plate CF5 in the first direction X, and the position, shape and size of the sixth electrode plate CF6 in the first circuit unit Q1, the second circuit unit Q2 and the third circuit unit Q3 can be substantially the same.
  • the positions and shapes of the first scan signal line S1, the second scan signal line S2, the light emitting signal line EM, the second control line CT2, the initial signal line Vint, the high-frequency connection line Hf-C, the high-voltage connection line VDD-C and the low-voltage connection line VSS-C may be substantially the same as those of the structures shown in FIGS. 22A and 22B , except that only one low-voltage connection line VSS-C is provided in the present embodiment, and the second scan signal line S2 is multiplexed as the first control line to control the conduction and disconnection of the eighth transistor T8.
  • the multiple gate electrodes of each circuit unit may include at least a first gate electrode Gate1, a second gate electrode Gate2, a third top gate electrode Gate3-T, a fourth gate electrode Gate4, a fifth gate electrode Gate5, a sixth gate electrode Gate6, a seventh gate electrode Gate7, an eighth gate electrode Gate8, a ninth gate electrode Gate9, a tenth gate electrode Gate10 and an eleventh gate electrode Gate11.
  • the plurality of connection electrodes of each circuit unit include at least a forty-first connection electrode CO41, a forty-second connection electrode CO42, and a forty-fifth connection electrode CO45, and positions and shapes of the forty-first connection electrode CO41, the forty-second connection electrode CO42, and the forty-first connection electrode CO41 may be substantially the same as those shown in FIGS. 22A and 22B.
  • the positions and functions of the multiple vias can be basically the same as the structure shown in Figure 23. The difference is that since the forty-third connecting electrode and the forty-fourth connecting electrode are not provided, and the shapes of the ninth gate electrode Gate9 and the eleventh gate electrode Gate11 are different, the positions of the corresponding vias are different, which will not be repeated here.
  • the third conductive layer pattern at least includes: a data signal line DataI, a high-frequency signal line Hf, a seventh electrode plate CF7, an eighth electrode plate CF8, a ninth electrode plate CF9, an anode connection block 12 and a plurality of connection electrodes, as shown in FIG. 33 .
  • the positions, shapes and connection structures of the data signal line DataI, the high-frequency signal line Hf, the seventh electrode plate CF7, the eighth electrode plate CF8 and the ninth electrode plate CF9 may be substantially the same as those shown in FIGS. 24A and 24B , except that the seventh electrode plate CF7 is disposed on one side of the eighth electrode plate CF8 in the first direction X, and the size and area of the ninth electrode plate CF9 in the first circuit unit Q1, the second circuit unit Q2 and the third circuit unit Q3 may be substantially the same.
  • the plurality of connecting electrodes may include at least a fifty-first connecting electrode CO51, a fifty-second connecting electrode CO52, a fifty-third connecting electrode CO53, a fifty-fourth connecting electrode CO54, a fifty-fifth connecting electrode CO55, a fifty-sixth connecting electrode CO56, a fifty-seventh connecting electrode CO57, a fifty-eighth connecting electrode CO58, a fifty-ninth connecting electrode CO59, a sixty-first connecting electrode CO60, a sixty-first connecting electrode CO61, a sixty-second connecting electrode CO62, a sixty-third connecting electrode CO63 and a sixty-fourth connecting electrode CO64, and the positions, shapes and connection structures of the above connecting electrodes may be substantially the same as those shown in FIGS.
  • the fifty-first connecting electrode CO51 is further connected to the seventh electrode plate CF7 through a via
  • the fifty-eighth connecting electrode CO58 is connected to the eleventh gate electrode Gate11
  • the fifty-ninth connecting electrode CO59 is connected to the ninth gate electrode Gate9, and so on, which will not be repeated here.
  • the anode connection block 12 of each circuit unit and the fifty-second connection electrode CO52 are an integral structure connected to each other.
  • the third conductive layer may further include a seventy-first connection electrode CO71.
  • the seventy-first connection electrode CO71 may be in a strip shape extending along the second direction Y, the seventy-first connection electrode CO71 may be disposed in the second circuit unit Q2, one end of the seventy-first connection electrode CO71 is connected to the low voltage connection line VSS-C through a via hole, and the seventy-first connection electrode CO71 is configured to be connected to a power low voltage line formed subsequently.
  • Patterns of the fourth insulating layer and the first planar layer are formed.
  • a plurality of via holes are arranged on the fourth insulating layer and the first planar layer in each circuit unit, as shown in FIG. 34 .
  • the plurality of vias may include at least a sixty-fifth via V65, a seventieth via V70, and a seventy-second via V72, and positions and functions of the plurality of vias may be substantially the same as those of the structure shown in FIG. 25 .
  • the fourth conductive layer pattern may include at least the anode connection electrode 13, the high voltage power line VDD and the low voltage power line VSS, as shown in FIGS. 35A and 35B , wherein FIG. 35B is a schematic diagram of another power routing of an exemplary embodiment of the present disclosure, illustrating the structure of the high voltage power line and the low voltage power line in multiple circuit units.
  • the high voltage power line VDD and the low voltage power line VSS may be in the shape of a line extending along the second direction Y, the high voltage connection line VDD-C extending along the first direction X is connected to the high voltage power line VDD extending along the second direction Y through a via hole to form a mesh connection structure for transmitting a high voltage power signal, and the low voltage connection line VSS-C extending along the first direction X is connected to the low voltage power line VSS extending along the second direction Y through a via hole to form a mesh connection structure for transmitting a low voltage power signal.
  • a high voltage opening and a low voltage opening are respectively provided on the high voltage power line VDD and the low voltage power line VSS.
  • a "T"-shaped low voltage power line and three anode connection electrodes 13 may be provided in the high voltage opening.
  • Two anode connection electrodes 13 may be provided in the low voltage opening.
  • the low voltage power line is configured to connect to the second pole of the light emitting diode.
  • a pad block is provided on one side of the low voltage power line VSS close to the high voltage power line VDD. The pad block is configured to connect to the second pole of the light emitting diode.
  • the position, shape and connection structure of the anode connection electrode 13 may be substantially the same as those shown in FIGS. 26A and 26B , and will not be described in detail herein.
  • the fifth insulating layer and the second planar layer are patterned.
  • the fifth insulating layer, the second planar layer and the sixth insulating layer in each circuit unit are provided with first binding holes K1 and second binding holes K2, as shown in FIG. 36 .
  • the location and function of the binding hole can be substantially the same as the structure shown in FIG. 27 .
  • the driving circuit layer of this exemplary embodiment is prepared on the substrate.
  • the display substrate provided by the exemplary embodiment of the present disclosure can meet the current value required by the red light-emitting diode and achieve more gray scales by setting the width-to-length ratio of the third transistor in the first circuit unit to be greater than the width-to-length ratio of the third transistor in the second circuit unit and the third circuit unit, thereby avoiding the problem that the brightness of the existing structure does not meet the requirements or cannot achieve more gray scales.
  • the present disclosure adopts a first capacitor, a second capacitor and a storage capacitor in a parallel structure, and on the premise of ensuring the capacitance, minimizes the occupied space of the first capacitor, the second capacitor and the storage capacitor, which is conducive to achieving high-resolution display.
  • the present disclosure forms a high-frequency signal line with a network connection structure, which can minimize the resistance of the high-frequency signal line, reduce the voltage drop of the high-frequency signal, effectively improve the uniformity of the power supply voltage in the display substrate, and effectively improve the uniformity within the signal surface.
  • the present disclosure forms a high-voltage power line and a low-voltage power line with a network connection structure, which can minimize the resistance of the power transmission line, reduce the voltage drop of the power supply voltage, effectively improve the uniformity of the power supply voltage in the display substrate, effectively improve the uniformity within the signal surface, effectively improve the display uniformity, and improve the display quality and display quality.
  • the display substrate preparation process needs to perform multiple tests, one of which is an important test using a test circuit CT to perform a screen test, also known as CT test.
  • CT test is to input a test signal to the display substrate to make the light-emitting diodes emit light, and to check whether each light-emitting diode is good through a defect detection device to confirm whether the display substrate has defects.
  • FIG37 is a schematic diagram of a display substrate for CT detection.
  • the display substrate may include a display area AA and a binding area FA located on one side of the display area AA.
  • the display area AA may include multiple circuit units and multiple light-emitting units.
  • the circuit unit may include at least a pixel driving circuit.
  • the light-emitting unit may include at least a light-emitting diode.
  • the light-emitting diode may be connected to the pixel driving circuit of the corresponding circuit unit.
  • the display area AA may also include multiple data signal lines DataI, each of which is connected to multiple pixel driving circuits in a unit column.
  • the binding area FA may include a detection circuit
  • the detection circuit may include at least a plurality of detection units 210, at least one control line 220, and at least one detection line 230.
  • the plurality of detection units 210 may be sequentially arranged at set intervals along the first direction X, and the positions of the plurality of detection units 210 may correspond one-to-one to the positions of the plurality of data signal lines DataI in the display area AA.
  • Each detection unit 210 may include a control terminal, an input terminal, and an output terminal, one end of the control line 220 is connected to a pin of the binding pin area, and the other end of the control line 220 may be connected to a control terminal of the plurality of detection units 210, and the control line 220 is configured to control the conduction or disconnection of the plurality of detection units 210.
  • One end of the detection line 230 is connected to a pin of the binding pin area, and the other end of the detection line 230 can be connected to an input end of a plurality of detection units 210.
  • the output ends of the plurality of detection units 210 can be connected to a plurality of data signal lines DataI of the display area AA.
  • the detection unit 210 is configured to output the signal output by the detection line 230 to the data signal line DataI of the display area AA under the control of the control line 220, so as to realize CT detection of the display substrate.
  • Fig. 38 is a schematic diagram of the structure of the detection circuit of the exemplary embodiment of the present disclosure.
  • the detection circuit may include at least a plurality of detection units 210, a control line 220 and a detection line 230, and the output ends of the plurality of detection units 210 may be connected to a plurality of data signal lines DataI of the display area through a plurality of transmission lines 240, and the shape of the plurality of transmission lines 240 may be a folded line extending toward the display area, and the spacing between adjacent transmission lines 240 may be substantially the same.
  • a shielding line 250 may be disposed between at least one transmission line 240 and an adjacent transmission line 240 , and the shape of the shielding line 250 may be substantially the same as that of the transmission line 240 .
  • the transmission line 240 and the shielding line 250 may be disposed in the same layer and simultaneously formed through the same patterning process.
  • the distance between the edge of the shielding wire 250 close to the transmission line 240 and the edge of the transmission line 240 close to the shielding wire 250 may be about 10 ⁇ m to 20 ⁇ m.
  • the distance between the edge of the shielding wire 250 close to the transmission line 240 and the edge of the transmission line 240 close to the shielding wire 250 may be about 15 ⁇ m.
  • the shielding line 250 may be connected to a constant voltage signal line or a ground signal line, and the shielding line 250 is configured to reduce a data voltage jump of the transmission line 240 caused by a coupling capacitance.
  • the constant voltage signal line may be a high voltage power line, or may be a low voltage power line, or may be an initial signal line.
  • Fig. 39 is a schematic diagram of a shielding line connected to a constant voltage signal line in an exemplary embodiment of the present disclosure.
  • the constant voltage signal line can be an initial signal line Vint
  • the shielding line 250 and the initial signal line Vint can be arranged in different conductive layers
  • the shielding line 250 can be connected to the initial signal line Vint through a via K0.
  • the initial signal line Vint may be connected to the plurality of shielding lines 250 through the plurality of vias K0 , respectively, to provide a constant voltage signal to the plurality of shielding lines 250 .
  • the present disclosure sets a shielding line between the transmission lines of the detection circuit, which can effectively shield the coupling capacitance between adjacent transmission lines and reduce data voltage jumps. Studies have shown that when the detection circuit performs CT detection, due to the existence of coupling capacitance between adjacent transmission lines, the coupling capacitance will cause data voltage jumps, resulting in test errors.
  • the present disclosure sets a shielding line between the transmission lines of the detection circuit, and the shielding line is connected to the constant voltage signal line.
  • the constant voltage shielding line can effectively shield the coupling capacitance between adjacent transmission lines, thereby effectively reducing data voltage jumps, which can not only improve the accuracy of test data, but also does not require the addition of additional signals and will not affect the data voltage.
  • the display substrate provided by the exemplary embodiments of the present disclosure can be applicable to any LED driving pixel circuit, including P-type PAM, P-type PAM+PWM, N-type PAM, N-type PAM+PWM, and LTPO-type PAM and PAM+PWM circuits.
  • the exemplary embodiment of the present disclosure also provides a method for preparing a display substrate to prepare the aforementioned display substrate.
  • the preparation method may include:
  • a driving circuit layer is formed on a substrate, the driving circuit layer includes a plurality of circuit units, the plurality of circuit units include at least a first circuit unit, a second circuit unit and a third circuit unit, the first circuit unit includes a first pixel driving circuit, the first pixel driving circuit includes at least a first driving transistor, the second circuit unit includes a second pixel driving circuit, the second pixel driving circuit includes at least a second driving transistor, the third circuit unit includes a third pixel driving circuit, the third pixel driving circuit includes at least a third driving transistor; a channel width of the first driving transistor is greater than a channel width of the second driving transistor or the third driving transistor, and a channel length of the first driving transistor is the same as a channel length of the second driving transistor or the third driving transistor.
  • the exemplary embodiments of the present disclosure further provide a display device, including the display substrate of the above-mentioned embodiment.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator.

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Abstract

一种显示基板及其制备方法、显示装置。显示基板包括多个电路单元(Q)，多个电路单元(Q)至少包括第一电路单元(Q1)、第二电路单元(Q2)和第三电路单元(Q3)，第一电路单元(Q1)至少包括第一驱动晶体管(DTFT1)，第二电路单元(Q2)至少包括第二驱动晶体管(DTFT2)，第三电路单元(Q3)至少包括第三驱动晶体管(DTFT3)；第一驱动晶体管(DTFT1)的沟道宽度大于第二驱动晶体管(DTFT2)或者第三驱动晶体管(DTFT3)的沟道宽度，第一驱动晶体管(DTFT1)的沟道长度与第二驱动晶体管(DTFT2)或者第三驱动晶体管(DTFT3)的沟道长度相同。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
半导体发光二极管(Light Emitting Diode，LED)技术发展了近三十年，从最初的固态照明电源到显示领域的背光源再到LED显示屏，为其更广泛的应用提供了坚实的基础。其中，随着芯片制作及封装技术的发展，次毫米发光二极管(Mini Light Emitting Diode，Mini LED)显示和微型发光二极管(Micro Light Emitting Diode，Micro LED)显示逐渐成为显示面板的一个热点，可以应用在AR/VR、TV及户外显示等领域。
虽然目前显示市场以液晶显示(Liquid Crystal Display，LCD)和有机发光二极管显示(Organic Light Emitting Diode，OLED)两种技术为主，但受基板尺寸、制备设备和工艺等限制，LCD和OLED均难以实现大尺寸显示，特别是110寸以上的大尺寸显示。相比之下，Micro LED显示/Mini LED显示可以通过拼接方式实现大尺寸显示，能够突破尺寸限制。由于LED具有自发光、广视角、快速响应、结构简单、体积小、轻薄、节能、高效、长寿、光线清晰等优点，更容易实现高分辨率(Pixels Per Inch，PPI)，被认为是最具竞争力的下一代显示技术。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开实施例提供一种显示基板，包括设置在基底上的驱动电路层，所述驱动电路层包括多个电路单元，所述多个电路单元至少包括第一电路单元、第二电路单元和第三电路单元，所述第一电路单元包括第一像素 驱动电路，所述第一像素驱动电路至少包括第一驱动晶体管，所述第二电路单元包括第二像素驱动电路，所述第二像素驱动电路至少包括第二驱动晶体管，所述第三电路单元包括第三像素驱动电路，所述第三像素驱动电路至少包括第三驱动晶体管；所述第一驱动晶体管的沟道宽度大于所述第二驱动晶体管或者所述第三驱动晶体管的沟道宽度，所述第一驱动晶体管的沟道长度与所述第二驱动晶体管或者所述第三驱动晶体管的沟道长度相同。
在示例性实施方式中，所述第一驱动晶体管的沟道宽度与所述第二驱动晶体管或者所述第三驱动晶体管的沟道宽度的比值为2至6。
在示例性实施方式中，所述第二驱动晶体管的沟道宽度与所述第三驱动晶体管的沟道宽度基本上相同，所述第二驱动晶体管的沟道长度与所述第三驱动晶体管的沟道长度基本上相同。
在示例性实施方式中，所述第一像素驱动电路还包括第一存储电容，所述第二像素驱动电路还包括第二存储电容，所述第三像素驱动电路还包括第三存储电容；所述第一存储电容的电容值大于或等于所述第二存储电容或者所述第三存储电容的电容值。
在示例性实施方式中，所述第一存储电容在所述基底上正投影的面积大于所述第二存储电容或者所述第三存储电容在所述基底上正投影的面积。
在示例性实施方式中，所述第一存储电容在所述基底上正投影的第一长度与所述第二存储电容或者所述第三存储电容在所述基底上正投影的第一长度相同，所述第一存储电容在所述基底上正投影的第二长度大于或等于所述第二存储电容或者所述第三存储电容在所述基底上正投影的第二长度，所述第一长度为第一方向的尺寸，所述第二长度为第二方向尺寸，所述第一方向与所述第二方向交叉。
在示例性实施方式中，所述第一存储电容在所述基底上正投影的第二长度与所述第二存储电容或者所述第三存储电容在所述基底上正投影的第二长度的比值为1至2。
在示例性实施方式中，所述第二存储电容在所述基底上正投影的第一长度与所述第三存储电容在所述基底上正投影的第一长度基本上相同，所述第二存储电容在所述基底上正投影的第二长度与所述第三存储电容在所述基底 上正投影的第二长度基本上相同。
在示例性实施方式中，所述显示基板还包括设置在所述驱动电路层远离所述基底一侧的发光结构层，所述发光结构层包括多个发光单元，所述多个发光二极管至少包括出射红色光线的红色发光二极管、出射绿色光线的绿色发光二极管和出射蓝色光线的蓝色发光二极管，所述红色发光二极管与所述第一像素驱动电路连接，所述绿色发光二极管与所述第二像素驱动电路连接，所述蓝色发光二极管与所述第三像素驱动电路连接。
在示例性实施方式中，至少一个电路单元包括沿着第一方向延伸的高压连接线和沿着第二方向延伸的高压电源线，所述高压电源线通过过孔与所述高压连接线连接，形成传输高压电源信号的网状连通结构，所述第一方向与所述第二方向交叉。
在示例性实施方式中，至少一个电路单元包括沿着第一方向延伸的低压连接线和沿着第二方向延伸的低压电源线，所述低压电源线通过过孔与所述低压连接线连接，形成传输低压电源信号的网状连通结构，所述第一方向与所述第二方向交叉。
在示例性实施方式中，所述低压电源线包括第一低压电源线和第二低压电源线，所述第一低压电源线与红色发光二极管连接，所述第二低压电源线与绿色发光二极管和蓝色发光二极管连接。
在示例性实施方式中，至少一个电路单元包括沿着所述第一方向延伸的第一低压连接线，所述第一低压电源线通过过孔与所述第一低压连接线连接，形成传输第一低压电源信号的网状连通结构。
在示例性实施方式中，至少一个电路单元包括沿着所述第一方向延伸的第二低压连接线，所述第二低压电源线通过过孔与所述第二低压连接线连接，形成传输第二低压电源信号的网状连通结构。
在示例性实施方式中，至少一个电路单元包括沿着第一方向延伸的高频连接线和沿着第二方向延伸的高频信号线，所述高频信号线通过过孔与所述高频连接线连接，形成传输高频信号的网状连通结构，所述第一方向与所述第二方向交叉。
在示例性实施方式中，所述显示基板还包括测试电路和多条沿着单元列方向延伸的数据信号线，所述数据信号线与所述像素驱动电路连接，所述检测电路至少包括多个检测单元和多条传输线，所述多个检测单元通过所述多条传输线与所述多条数据信号线对应连接，至少一条传输线与相邻的传输线之间设置有屏蔽线，所述屏蔽线与恒压信号线或者接地信号线连接。
在示例性实施方式中，至少一条传输线与相邻的屏蔽线之间的距离为10μm至20μm。
在示例性实施方式中，所述传输线和所述屏蔽线同层设置。
另一方面，本公开还提供一种显示装置，包括如上所述的显示基板。
又一方面，本公开还提供一种显示基板的制备方法，包括：
在基底上形成驱动电路层，所述驱动电路层包括多个电路单元，所述多个电路单元至少包括第一电路单元、第二电路单元和第三电路单元，所述第一电路单元包括第一像素驱动电路，所述第一像素驱动电路至少包括第一驱动晶体管，所述第二电路单元包括第二像素驱动电路，所述第二像素驱动电路至少包括第二驱动晶体管，所述第三电路单元包括第三像素驱动电路，所述第三像素驱动电路至少包括第三驱动晶体管；所述第一驱动晶体管的沟道宽度大于所述第二驱动晶体管或者所述第三驱动晶体管的沟道宽度，所述第一驱动晶体管的沟道长度与所述第二驱动晶体管或者所述第三驱动晶体管的沟道长度相同。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为本公开示例性实施例一种像素驱动电路的等效电路图；
图4为本公开示例性实施例一种显示基板的结构示意图；
图5A为本公开一种第一驱动晶体管的结构示意图；
图5B为本公开一种第二驱动晶体管的结构示意图；
图6A为本公开一种第一存储电容的结构示意图；
图6B为本公开一种第二存储电容的结构示意图；
图7为本公开一种显示基板形成第一导电层图案后的示意图；
图8A和图8B为本公开一种显示基板形成半导体层图案后的示意图；
图9为本公开一种显示基板形成第二绝缘层图案后的示意图；
图10A和图10B为本公开一种显示基板形成第二导电层图案后的示意图；
图11为本公开一种显示基板形成第三绝缘层图案后的示意图；
图12A和图12B为本公开一种显示基板形成第三导电层图案后的示意图；
图13为本公开一种显示基板形成第一平坦层图案后的示意图；
图14A和图14B为本公开一种显示基板形成第四导电层图案后的示意图；
图15为本公开一种显示基板形成第二平坦层图案后的示意图；
图16为本公开示例性实施例另一种像素驱动电路的等效电路图；
图17为本公开示例性实施例另一种显示基板的结构示意图；
图18A为本公开另一种第一驱动晶体管的结构示意图；
图18B为本公开另一种第二驱动晶体管的结构示意图；
图19A为本公开另一种第一存储电容的结构示意图；
图19B为本公开另一种第二存储电容的结构示意图；
图20为本公开另一种显示基板形成第一导电层图案后的示意图；
图21A和图21B为本公开另一种显示基板形成半导体层图案后的示意图；
图22A和图22B为本公开另一种显示基板形成第二导电层图案后的示意图；
图23为本公开另一种显示基板形成第三绝缘层图案后的示意图；
图24A和图24B为本公开另一种显示基板形成第三导电层图案后的示意图；
图25为本公开另一种显示基板形成第一平坦层图案后的示意图；
图26A和图26B为本公开另一种显示基板形成第四导电层图案后的示意图；
图26C为本公开示例性实施例一种电源走线的示意图；
图27为本公开另一种显示基板形成第二平坦层图案后的示意图；
图28为本公开示例性实施例又一种显示基板的结构示意图；
图29为本公开又一种显示基板形成第一导电层图案后的示意图；
图30为本公开又一种显示基板形成半导体层图案后的示意图；
图31为本公开又一种显示基板形成第二导电层图案后的示意图；
图32为本公开又一种显示基板形成第三绝缘层图案后的示意图；
图33为本公开又一种显示基板形成第三导电层图案后的示意图；
图34为本公开又一种显示基板形成第一平坦层图案后的示意图；
图35A为本公开又一种显示基板形成第四导电层图案后的示意图；
图35B为本公开示例性实施例另一种电源走线的示意图；
图36为本公开又一种显示基板形成第二平坦层图案后的示意图；
图37为一种显示基板进行CT检测的示意图；
图38为本公开示例性实施例检测电路的结构示意图；
图39为本公开示例性实施例一种屏蔽线与恒压信号线连接的示意图。
附图标记说明:
AA—显示区域；        AT1—第一有源层；     AT2—第二有源层；
AT3—第三有源层；     AT4—第四有源层；     AT5—第五有源层；
AT6—第六有源层；     AT7—第七有源层；     AT8—第八有源层；
AT9—第九有源层；     AT10—第十有源层；    AT11—第十一有源层；
AT12—第十二有源层；    CF1—第一极板；         CF2—第二极板；
CF3—第三极板；         CF4—第四极板；         CF5—第五极板；
CF6—第六极板；         CF7—第七极板；         CF8—第八极板；
CF9—第九极板；         Cs1—第一存储电容；     Cs2—第二存储电容；
Cs3—第三存储电容；     CT1—第一控制线；       CT2—第二控制线；
C1—第一电容；          C2—第二电容；          DTFT1—第一驱动晶体管；
DTFT2—第二驱动晶体管； DTFT3—第三驱动晶体管； DataI—数据信号线；
DataT—时长信号线；     EM—发光信号线；        FA—绑定区域；
Gate1—第一栅电极；     Gate2—第二栅电极；     Gate3-B—第三底栅电极；
Gate3-T—第三顶栅电极； Gate4—第四栅电极；     Gate5—第五栅电极；
Gate6—第六栅电极；     Gate7—第七栅电极；     Gate8—第八栅电极；
Gate9—第九栅电极；     Gate10—第十栅电极；    Gate11—第十一栅电极；
Gate12—第十二栅电极；  Hf—高频信号线；        Hf-C—高频连接线；
S1—第一扫描信号线；    S2—第二扫描信号线；    VDD—高压电源线；
VDD-C—高压连接线；     VSS—低压电源线；       VSS-C—低压连接线；
Vint—初始信号线；      10—基底；              11—电源电极；
12—阳极连接块；        13—阳极连接电极；      20—驱动电路层；
30—发光结构层；        40—发光二极管；        100—母板；
200—显示基板；         210—检测单元；         220—控制线；
230—检测线；           240—传输线；           250—屏蔽线。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本公开中，“厚度”、“高度”，是指膜层远离基底一侧表面至靠近基底一侧表面之间的垂直距离。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图，如图1所示，大尺寸显示装置的主体结构可以包括在母板100上设置的多个显示基板200，多个显示基板100紧密拼接在一起以进行图像显示。在垂直于显示基板的平面上，至少一个显示基板200可以至少包括设置在基底10上的驱动电路层20以及设置在驱动电路层20远离基底一侧的发光结构层30。在平行于显示基板的平面上，驱动电路层20可以包括多个电路单元，至少一个电路单元可以包括像素驱动电路以及与像素驱动电路连接的多条信号线，像素驱动电路被配置为在信号线的控制下接收数据电压，并输出相应的电流。发光结构层30可以包括多个发光单元，至少一个发光单元可以包括发光二极管40，多个发光单元中的发光二极管40与多个电路单元中的像素驱动电路对应连接，发光二极管40被配 置为在对应像素驱动电路输出电流的驱动下发出相应亮度的光线。
在示例性实施方式中，本公开中所说的电路单元是指按照像素驱动电路划分的区域，本公开中所说的发光单元是指按照发光二极管划分的区域。在示例性实施方式中，发光单元与电路单元两者的位置可以是对应的，或者，发光单元与电路单元两者的位置可以是不对应的，本公开在此不做限定。
在示例性实施方式中，发光二极管40可以是次毫米发光二极管Mini LED或者微型发光二极管Micro LED。
图2为一种显示基板的平面结构示意图。如图2所示，在平行于显示基板的平面内，显示基板可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3。在示例性实施方式中，每个子像素均可以包括电路单元和发光单元。第一子像素P1可以包括第一电路单元和第一发光单元，第一发光单元可以至少包括出射第一颜色光线的第一发光二极管，第一电路单元可以至少包括与第一发光二极管连接的第一像素驱动电路。第二子像素P2可以包括第二电路单元和第二发光单元，第二发光单元可以至少包括出射第二颜色光线的第二发光二极管，第二电路单元可以至少包括与第二发光二极管连接的第二像素驱动电路。第三子像素P3可以包括第三电路单元和第三发光单元，第三发光单元可以至少包括出射第三颜色光线的第三发光二极管，第三电路单元可以至少包括与第三发光二极管连接的第三像素驱动电路。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色(R)子像素，第二子像素P2可以是出射绿色光线的绿色子像素(G)，第三子像素P3可以是出射蓝色光线的蓝色(B)子像素，R子像素、G子像素和B子像素可以组成一个像素单元P。在示例性实施方式中，像素单元P中的三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元P可以包括四个子像素，四个子像素可以采用水平并列、竖直并列、正方形或钻石形等方式排列，本公开在此不做限定。
研究发现，次毫米发光二极管Mini LED和微型发光二极管Micro LED受材料及工艺等限制，红色发光二极管(简称R芯片)与蓝色发光二极管和绿色发光二极管(简称G/B芯片)的出光效率及良率差异较大。例如，在白光亮度为1000nit时,一种规格的R芯片/G芯片/B芯片应达到的亮度分别为300nit/600nit/100nit，此时R芯片驱动电流需达到20μA左右，而G/B芯片驱动电流仅需4μA左右。如果按照G/B芯片的电流需求设计像素驱动电路中的驱动晶体管(DTFT)，栅源电压Vgs为5V时可达到其需求的4μA电流值，但在相同跨压下，R芯片的驱动晶体管在栅源电压Vgs为5V时无法达到需求的20μA电流值，使得R芯片不能满足亮度需求。如果按照R芯片的电流需求设计驱动晶体管，则G/B芯片会在较小的栅源电压Vgs就能达到其需求电流，造成数据范围小，不能实现更多的灰阶。
本公开提供了一种显示基板，驱动红色发光二极管、绿色发光二极管和蓝色发光二极管的像素驱动电路采用不同的结构，以避免亮度不满足需求或者不能实现更多灰阶等不良。
在示例性实施方式中，显示基板包括设置在基底上的驱动电路层以及设置在所述驱动电路层远离所述基底一侧的发光结构层，所述驱动电路层包括形成多个单元行和多个单元列的多个电路单元，所述发光结构层包括多个发光单元，所述电路单元中至少包括像素驱动电路，所述发光单元中至少包括发光二极管；所述多个电路单元至少包括设置有第一像素驱动电路的第一电路单元、设置有第二像素驱动电路的第二电路单元和设置有第三像素驱动电路的第三电路单元，所述多个发光二极管至少包括出射第一颜色光线的第一发光二极管、出射第二颜色光线的第二发光二极管和出射第三颜色光线的第三发光二极管，所述第一像素驱动电路与所述第一发光二极管连接，所述第二像素驱动电路与所述第二发光二极管连接，所述第三像素驱动电路与所述第三发光二极管连接；所述第一像素驱动电路至少包括第一驱动晶体管和第一存储电容，所述第二像素驱动电路至少包括第二驱动晶体管和第二存储电容，所述第三像素驱动电路至少包括第三驱动晶体管和第三存储电容，所述第一驱动晶体管的宽长比大于所述第二驱动晶体管或者所述第三驱动晶体管的宽长比，所述第一存储电容的电容值大于或等于所述第二存储电容或者所 述第三存储电容的电容值。
在示例性实施方式中，所述第一驱动晶体管的沟道宽度大于所述第二驱动晶体管或者所述第三驱动晶体管的沟道宽度，所述第一驱动晶体管的沟道长度与所述第二驱动晶体管或者所述第三驱动晶体管的沟道长度基本上相同。
在示例性实施方式中，所述第一存储电容在所述基底上正投影的面积大于所述第二存储电容或者所述第三存储电容在所述基底上正投影的面积。
下面通过多个示例对本公开的显示基板进行举例说明。
图3为本公开示例性实施例一种像素驱动电路的等效电路图，示意了一种12T3C的像素驱动电路结构。在示例性实施方式中，显示基板中的多个发光二极管可以采用电流型驱动。由于在较低电流密度驱动下电流型发光二极管会出现色坐标漂移和外量子效率较低的问题，从而导致亮度均一性较差，因而仅通过控制电流的幅值大小难以准确表现低灰阶。本公开示例性实施例像素驱动电路至少包括两类数据端：电流数据端和时长数据端，电流数据端被配置为向发光二极管提供不同幅值大小的电流信号，而时长数据端被配置为向发光二极管提供上述电流信号的时间长度。
如图3所示，本示例性实施例提供的像素驱动电路可以至少包括电流控制子电路DK和时长控制子电路SK。电流控制子电路DK可以至少包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第十二晶体管T12和存储电容Cs，时长控制子电路SK可以至少包括第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第一电容C1和第二电容C2。
在示例性实施方式中，像素驱动电路可以至少包括第一节点N1、第二节点N2、第三节点N3、第四节点N4、第五节点N5、第六节点N6和第七节点N7。第一节点N1分别与第九晶体管T9的第二极、第十一晶体管T11的第二极和第十二晶体管T12的栅电极连接，第二节点N2分别与第七晶体管T7的第二极、第十二晶体管T12的第二极和发光二极管EL的阳极连接，第三节点N3分别与第一晶体管T1的第二极、第二晶体管T2的第一极、第三晶体管T3的栅电极和存储电容Cs的第一端连接，第四节点N4分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连 接，第五节点N5分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第六节点N6分别与第八晶体管T8的第二极、第九晶体管T9的栅电极和第一电容C1的第一端连接，第七节点N7分别与第十晶体管T10的第二极、第十一晶体管T11的栅电极和第二电容C2的第一端连接。
在示例性实施方式中，第一晶体管T1的栅电极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线Vint连接，第一晶体管T1的第二极与第三节点N3连接。
在示例性实施方式中，第二晶体管T2的栅电极与第一扫描信号线S1连接，第二晶体管T2的第一极与第三节点N3连接，第二晶体管T2的第二极与第四节点N4连接。
在示例性实施方式中，第三晶体管T3的栅电极与第三节点N3连接，第三晶体管T3的第一极与第五节点N5连接，第三晶体管T3的第二极与第四节点N4连接。
在示例性实施方式中，第四晶体管T4的栅电极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线DataI连接，第四晶体管T4的第二极与第五节点N5连接。
在示例性实施方式中，第五晶体管T5的栅电极与发光信号线EM连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第五节点N5连接。
在示例性实施方式中，第六晶体管T6的栅电极与发光信号线EM连接，第六晶体管T6的第一极与第四节点N4连接，第六晶体管T6的第二极与第十二晶体管T12的第一极连接。
在示例性实施方式中，第七晶体管T7的栅电极与第二扫描信号线S2连接，第七晶体管T7的第一极与初始信号线Vint连接，第七晶体管T7的第二极与第二节点N2连接。
在示例性实施方式中，第八晶体管T8的栅电极与第一控制线CT1连接，第八晶体管T8的第一极与时长信号线DataT连接，第八晶体管T8的第二极 与第六节点N6连接。
在示例性实施方式中，第九晶体管T9的栅电极与第六节点N6连接，第九晶体管T9的第一极与发光信号线EM连接，第九晶体管T9的第二极与第一节点N1连接。
在示例性实施方式中，第十晶体管T10的栅电极与第二控制线CT2连接，第十晶体管T10的第一极与时长信号线DataT连接，第十晶体管T10的第二极与第七节点N7连接。
在示例性实施方式中，第十一晶体管T11的栅电极与第七节点N7连接，第十一晶体管T11的第一极与高频信号线Hf连接，第十一晶体管T11的第二极与第一节点N1连接。
在示例性实施方式中，第十二晶体管T12的栅电极与第一节点N1连接，第十二晶体管T12的第一极电与第六晶体管T6的第二极连接，第十二晶体管T12的第二极与第二节点N2连接。
在示例性实施方式中，存储电容Cs的第一端与第三节点N3连接，存储电容Cs的第二端与第一电源线VDD连接。
在示例性实施方式中，第一电容C1的第一端与第六节点N6连接，第一电容C1的第二端与初始信号线Vint连接。
在示例性实施方式中，第二电容C2的第一端与第七节点N7连接，第二电容C2的第二端与初始信号线Vint连接。
在示例性实施方式中，第一晶体管T1、第二晶体管T2、第四晶体管T4至第十二晶体管T12可以为开关晶体管，第三晶体管T3可以为驱动晶体管。
在示例性实施方式中，发光二极管EL可以是Mini LED或者Micro LED。发光二极管EL的第一极与第二节点N2连接，发光二极管EL的第二极与第二电源线VSS连接，第二电源线VSS的信号为持续提供的低电平信号，如直流低电压。第一电源线VDD的信号为持续提供的高电平信号，如直流高电压。
在示例性实施方式中，第一晶体管T1至第十二晶体管T12可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可 以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1至第十二晶体管T12可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1至第十二晶体管T12可以采用低温多晶硅晶体管，或者可以采用氧化物晶体管，或者可以采用低温多晶硅晶体管和金属氧化物晶体管。低温多晶硅晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，金属氧化物晶体管的有源层采用金属氧化物半导体(Oxide)。低温多晶硅晶体管具有迁移率高、充电快等优点，氧化物晶体管具有漏电流低等优点，将低温多晶硅晶体管和金属氧化物晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，以图3所示的像素驱动电路中第一晶体管T1和第十二晶体管T12均为P型晶体管为例，像素驱动电路的工作过程可以包括：
在示例性实施方式中，当像素驱动电路所连接的发光二极管显示的灰阶大于阈值灰阶时，像素驱动电路的工作过程可以包括初始化阶段、写入阶段和发光阶段，初始化阶段可以包括第一子阶段和第二子阶段。
第一子阶段和第二子阶段中，第一扫描信号线S1和发光信号线EM的信号为高电平信号，第二扫描信号线S2的信号为低电平信号，第一晶体管T1和第七晶体管T7导通。第一晶体管T1导通使得初始信号线Vint的信号写入第三节点N3，对存储电容Cs进行初始化(复位)，清除存储电容Cs中原有电荷。由于存储电容C的第一端为低电平，因此第三晶体管T3导通。第七晶体管T7导通使得初始信号线Vint的信号写入第二节点N2，对发光二极管EL的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光二极管EL不发光。
第一子阶段中，时长信号线DataT的信号为高电平信号，第二控制线CT2的信号为低电平信号，第十晶体管T10导通，使得时长信号线DataT的信号写入第七节点N7，并对第二电容C2进行充电。由于此时时长信号线DataT的信号为高电平信号，因而第十一晶体管T11断开，高频信号线Hf的信号 无法写入第一节点N1。
第二子阶段中，时长信号线DataT的信号为低电平信号，第一控制线CT1的信号为低电平信号，第八晶体管T8导通，使得时长信号线DataT的信号写入第六节点N6，并对第一电容C1进行充电。由于此时时长信号线DataT的信号为低电平信号，因而第九晶体管T9导通，发光信号线EM的信号写入第一节点N1。
写入阶段，数据信号线DataI输出数据电压，第二扫描信号线S2和发光信号线E的信号为高电平信号，第一扫描信号线S1的信号为低电平信号，第二晶体管T2和第四晶体管T4导通。第二晶体管T2和第四晶体管T4导通使得数据信号线DataI输出的数据电压经过第五节点N5、导通的第三晶体管T3、第四节点N4、导通的第二晶体管T2提供至第三节点N3，并将数据信号线DataI输出的数据电压Vd与第三晶体管T3的阈值电压Vth之差充入存储电容Cs，存储电容Cs的第一端(第三节点N3)的电压为Vd-|Vth|。第一电容C1保持第六节点N6的信号的电位不变，第九晶体管T9保持导通，发光信号线EM的信号写入第一节点N1。
发光阶段，发光信号线EM的信号为低电平信号，第五晶体管T5和第六晶体管T6导通，第一电容C1保持第六节点N6的信号的电位，第九晶体管T9保持导通，发光信号线EM的信号写入第一节点N1，第十二晶体管T12导通。第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3、第六晶体管T6和第十二晶体管T12向发光二极管EL的第一极提供驱动电压，驱动发光二极管EL发光。
在示例性实施方式中，当像素驱动电路所连接的发光二极管显示的灰阶小于阈值灰阶时，像素驱动电路的工作过程包括：初始化阶段、写入阶段和发光阶段，初始化阶段可以包括第一子阶段和第二子阶段。
第一子阶段和第二子阶段中，第一扫描信号线S1和发光信号线EM的信号为高电平信号，第二扫描信号线S2的信号为低电平信号，第一晶体管T1和第七晶体管T7导通。第一晶体管T1导通使得初始信号线Vint的信号写入第三节点N3，对存储电容Cs进行初始化(复位)，清除存储电容Cs中原有电荷。由于存储电容C的第一端为低电平，因此第三晶体管T3导通。 第七晶体管T7导通使得初始信号线Vint的信号写入第二节点N2，对发光二极管EL的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光二极管EL不发光。
第一子阶段中，时长信号线DataT的信号为低电平信号，第二控制线CT2的信号为低电平信号，第十晶体管T10导通，使得时长信号线DataT的信号写入第七节点N7，并对第二电容C2进行充电。由于此时时长信号线DataT的信号为低电平信号，因而第十一晶体管T11导通，高频信号线Hf的信号写入第一节点N1。
第二子阶段中，时长信号线DataT的信号为高电平信号，第一控制线CT1的信号为低电平信号，第八晶体管T8导通，使得时长信号线DataT的信号写入第六节点N6，并对第一电容C1进行充电。由于此时时长信号线DataT的信号为高电平信号，因而第九晶体管T9断开，发光信号线EM的信号无法写入第一节点N1。
写入阶段，数据信号线DataI输出数据电压，第二扫描信号线S2和发光信号线E的信号为高电平信号，第一扫描信号线S1的信号为低电平信号，第二晶体管T2和第四晶体管T4导通。第二晶体管T2和第四晶体管T4导通使得数据信号线DataI输出的数据电压经过第五节点N5、导通的第三晶体管T3、第四节点N4、导通的第二晶体管T2提供至第三节点N3，并将数据信号线DataI输出的数据电压Vd与第三晶体管T3的阈值电压Vth之差充入存储电容Cs，存储电容Cs的第一端(第三节点N3)的电压为Vd-|Vth|。第二电容C2保持第七节点N7的信号电位不变，第十一晶体管T11始终导通，高频信号线Hf的信号写入第一节点N1。
发光阶段，发光信号线EM的信号为低电平信号，第五晶体管T5和第六晶体管T6导通，第二电容C2保持第七节点N7的信号电位不变，第十一晶体管T11始终导通，高频信号线Hf的信号写入第一节点N1，第十二晶体管T12导通。第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3、第六晶体管T6和第十二晶体管T12向发光二极管EL的第一极提供驱动电压，驱动发光二极管EL发光。
在示例性实施方式中，在发光阶段，像素驱动电路中第三晶体管T3所 输出的驱动电流不受第三晶体管T3的阈值电压的影响，只与数据信号线的电压和第一电源线的电压有关，消除了驱动晶体管的阈值电压对驱动电流的影响，确保了显示产品的显示亮度均匀，提升了显示效果。
在示例性实施方式中，当像素驱动电路所连接的发光二极管显示的灰阶大于阈值灰阶时，通过发光信号线向第一节点N1提供控制信号，使得发光二极管的灰阶通过驱动电流来控制。当像素驱动电路所连接的发光二极管显示的灰阶小于阈值灰阶时，通过高频信号线向第一节点N1提供控制信号，使得发光二极管的灰阶通过驱动电流和发光时长来控制。
在示例性实施方式中，高频信号线Hf的信号为脉冲信号，在一图像帧内，高频信号线Hf的信号具有多个脉冲。在示例性实施方式中，高频信号线Hf的信号的频率可以大于发光信号线EM的信号的频率。例如，高频信号线Hf的信号的频率可以在3000Hz～60000Hz之间，发光信号线EM的频率可以在60Hz～120Hz之间。本公开通过高频信号线的高频脉冲信号控制发光时长，将短发光时长分散到一帧时间里，减少像素驱动电路所连接的发光二极管显示的灰阶小于阈值灰阶时出现的闪烁，提升了显示产品的显示效果。
图4为本公开示例性实施例一种显示基板的结构示意图，示意了三个电路单元的结构，电路单元包括图3所示的像素驱动电路。在示例性实施方式中，在垂直于显示基板的平面上，显示基板可以至少包括设置在基底上的驱动电路层以及设置在驱动电路层远离基底一侧的发光结构层。在平行于显示基板的平面上，驱动电路层可以至少包括形成多个单元行和多个单元列的多个电路单元，电路单元可以至少包括像素驱动电路，发光结构层可以包括多个发光单元，发光单元可以至少包括发光二极管，多个发光单元中的发光二极管与多个电路单元中的像素驱动电路对应连接，使得发光二极管在对应像素驱动电路输出电流的驱动下发出相应亮度的光线。
如图4所示，多个电路单元可以至少包括沿着第一方向X依次设置的第一电路单元Q1、第二电路单元Q2和第三电路单元Q3，多个发光单元可以至少包括第一发光单元、第二发光单元和第三发光单元。第一电路单元Q1可以至少包括第一像素驱动电路，第二电路单元Q2可以至少包括第二像素驱动电路，第三电路单元Q3可以至少包括第三像素驱动电路，第一发光单 元可以至少包括第一发光二极管，第二发光单元可以至少包括第二发光二极管，第三发光单元可以至少包括第三发光二极管。在示例性实施方式中，第一像素驱动电路被配置为与第一发光二极管连接，第二像素驱动电路被配置为与第二发光二极管连接，第三像素驱动电路被配置为与第三发光二极管连接。
在示例性实施方式中，第一发光二极管可以为红色发光二极管，第二发光二极管可以为绿色发光二极管，第三发光二极管可以为蓝色发光二极管。
在示例性实施方式中，第一电路单元Q1中的第一像素驱动电路可以至少包括第一驱动晶体管DTFT1和第一存储电容Cs1，第二电路单元Q2中的第二像素驱动电路可以至少包括第二驱动晶体管DTFT2和第二存储电容Cs2，第三电路单元Q3中的第三像素驱动电路可以至少包括第三驱动晶体管DTFT3和第三存储电容Cs3。
在示例性实施方式中，第一驱动晶体管DTFT1的宽长比(W/L)可以大于第二驱动晶体管DTFT2的宽长比，第一驱动晶体管DTFT1的宽长比可以大于第三驱动晶体管DTFT3的宽长比。
在示例性实施方式中，第一存储电容Cs1的电容值可以大于第二存储电容Cs2的电容值，第一存储电容Cs1的电容值可以大于第三存储电容Cs3的电容值。
在示例性实施方式中，至少一个电路单元可以包括沿着第一方向X(单元行方向)延伸的高压连接线VDD-C和沿着第二方向Y(单元列方向)延伸的高压电源线VDD，高压连接线VDD与相应的像素驱动电路连接，高压电源线VDD可以通过过孔与高压连接线VDD-C连接，形成传输高压电源信号的网状连通结构，第一方向X和第二方向Y可以相互交叉。
在示例性实施方式中，至少一个电路单元可以包括沿着第一方向X延伸的低压连接线VSS-C和沿着第二方向Y延伸的低压电源线VSS，低压电源线VSS与相应的发光二极管连接，低压电源线VSS可以通过过孔与低压连接线VSS-C连接，形成传输低压电源信号的网状连通结构。
在本公开中，结构A沿着方向B延伸是指，结构A可以包括主体部分和与主体部分连接的次要部分，主体部分大致呈沿某一个方向延伸的条状， 次要部分的形状不限，主体部分至少为结构A的60％的部分；主体部分沿着方向B伸展，且主体部分沿着方向B伸展的尺寸大于沿着其它方向伸展的次要部分的尺寸。以下描述中所说的“结构A沿着方向B延伸”均是指“结构A的主体部分沿着方向B延伸”。
图5A为本公开一种第一驱动晶体管的结构示意图，图5B为本公开一种第二驱动晶体管的结构示意图。在示例性实施方式中，第一驱动晶体管DTFT1和第二驱动晶体管DTFT2均可以包括有源层Active、栅电极Gate、第一极Source和第二极Drain，有源层Active包括沟道区和位于沟道区两侧的源连接区和漏连接区，栅电极Gate与有源层Active的重叠区域形成沟道区，第一极Source与源连接区连接，第二极Drain与漏连接区连接。第一驱动晶体管DTFT1具有第一宽长比，第二驱动晶体管DTFT2具有第二宽长比，第一宽长比可以大于第二宽长比。
如图5A和图5B所示，第一驱动晶体管DTFT1的栅电极Gate、第一极Source和第二极Drain均为梳状，沿着有源层Active的延伸方向，第二极Drain、栅电极Gate和第一极Source交替设置，形成四个子晶体管，第一子晶体管具有第一沟道长度L1和第一子宽度z1，第二子晶体管具有第一沟道长度L1和第二子宽度z2，第三子晶体管具有第一沟道长度L1和第三子宽度z3，第四子晶体管具有第一沟道长度L1和第四子宽度z4，因而第一驱动晶体管DTFT1具有第一沟道长度L1和第一沟道宽度W1，第一沟道宽度W1为第一子宽度z1、第二子宽度z2、第三子宽度z3和第四子宽度z4之和。在示例性实施方式中，第二驱动晶体管DTFT2的栅电极Gate、第一极Source和第二极Drain均为条形状，因而第二驱动晶体管DTFT2具有第二沟道长度L2和第二沟道宽度W2。
在示例性实施方式中，第一沟道长度L1与第二沟道长度L2可以基本上相同，第一沟道宽度W1可以大于第二沟道宽度W2。
在示例性实施方式中，第一沟道宽度W1与第二沟道宽度W2的比值可以约为2至6。
在示例性实施方式中，z1＝z2＝z3＝z4＝W2，W1/W2可以约为4左右。
在示例性实施方式中，第二驱动晶体管DTFT2的第二沟道宽度与第三驱 动晶体管DTFT3的第三沟道宽度可以基本上相同，第二驱动晶体管DTFT2的第二沟道长度与第三驱动晶体管DTFT3的第三沟道长度可以基本上相同。
图6A为本公开一种第一存储电容的结构示意图，图6B为本公开一种第二存储电容的结构示意图。如图6A和图6B所示，第一存储电容Cs1具有第一面积，第二存储电容Cs2具有第二面积，第一面积可以大于第二面积。
在示例性实施方式中，第一面积和第二面积可以是第一存储电容Cs1和第二存储电容Cs2在显示基板平面上的正投影的面积。第一存储电容Cs1和第二存储电容Cs2可以包括叠设的多个极板，第一面积可以是第一存储电容Cs1中多个极板在显示基板平面上正投影的最小面积，第二面积可以是第二存储电容Cs2中多个极板在显示基板平面上正投影的最小面积。
在示例性实施方式中，第一存储电容Cs1和第二存储电容Cs2的形状可以为多边形状，第一存储电容Cs1和第二存储电容Cs2分别具有第一长度M1和第二长度M2，第一长度M1可以是第一存储电容Cs1和第二存储电容Cs2在第一方向X上的最大尺寸，第二长度M2可以是第一存储电容Cs1和第二存储电容Cs2在第二方向Y上的最大尺寸，第一长度M1和第二长度M2可以是第一存储电容Cs1和第二存储电容Cs2在显示基板平面上正投影的投影长度。
在示例性实施方式中，第一存储电容Cs1的第一长度M1与第二存储电容Cs2的第一长度M1可以基本上相同，第一存储电容Cs1的第二长度M2可以大于第二存储电容Cs2的第二长度M2。
在示例性实施方式中，第一存储电容Cs1的第二长度M2与第二存储电容Cs2的第二长度M2的比值可以约为1至2。例如，第一存储电容Cs1的第二长度M2与第二存储电容Cs2的第二长度M2的比值可以约为1.3左右。
在示例性实施方式中，第二存储电容Cs2的第一长度M1与第三存储电容Cs3的第一长度M1可以基本上相同，第二存储电容Cs2的第二长度M2与第三存储电容Cs3的第二长度M2可以基本上相同。
在示例性实施方式中，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3可以沿着第一方向X依次设置，第一发光二极管、第二发光二极管和第三发光二极管与第一电路单元Q1、第二电路单元Q2和第三电路单元 Q3的位置可以是对应的，或者可以是不对应的，本公开在此不做限定。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施方式中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以三个电路单元(第一电路单元Q1、第二电路单元Q2和第三电路单元Q3)为例，驱动电路层的制备过程可以包括如下操作。
(11)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在基底上沉积第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成设置在基底上的第一导电层图案，如图7所示。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，每个电路单元的第一导电层图案可以至少包括：第一极板CF1、第二极板CF2、第三极板CF3和第三底栅电极Gate3-B。
在示例性实施方式中，第一极板CF1的形状可以为“L”形状，第一极板CF1可以设置在电路单元第二方向Y的一侧。在示例性实施方式中，第一极板CF1可以作为第一电容的一个极板。
在示例性实施方式中，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第一极板CF1的位置、形状和尺寸可以基本上相同。
在示例性实施方式中，第二极板CF2的形状可以为矩形状，矩形状的角部可以设置倒角，第二极板CF2可以设置在电路单元第二方向Y的中部。在示例性实施方式中，第二极板CF2可以作为第二电容的一个极板。
在示例性实施方式中，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第二极板CF2的位置、形状和尺寸可以基本上相同。
在示例性实施方式中，第三极板CF3的形状可以为矩形状，矩形状的角部可以设置倒角，第三极板CF3可以设置在电路单元第二方向Y的反方向的一侧。在示例性实施方式中，第三极板CF3可以作为存储电容的一个极板。
在示例性实施方式中，在第二方向Y上，第二极板CF2可以位于第一极板CF1和第三极板CF3之间。
在示例性实施方式中，第二电路单元Q2和第三电路单元Q3中第三极板CF3的位置、形状和尺寸可以基本上相同，但与第一电路单元Q1中第三极板CF3的形状和尺寸不同。
在示例性实施方式中，第一电路单元Q1中第三极板CF3的面积可以大于第二电路单元Q2中第三极板CF3的面积，第一电路单元Q1中第三极板CF3的面积可以大于第三电路单元Q3中第三极板CF3的面积，以使第一电路单元Q1中存储电容的电容值大于第二电路单元Q2和第三电路单元Q3中存储电容的电容值。
在示例性实施方式中，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第三极板CF3的第一长度M1可以基本上相同，第一电路单元Q1中第三极板CF3的第二长度M2可以大于第二电路单元Q2和第三电路单元Q3中第三极板CF3的第二长度M2，以使第一电路单元Q1中第三极板CF3的面积大于第二电路单元Q2和第三电路单元Q3中第三极板CF3的面积。在示例性实施方式中，第一长度M1可以是第一方向X的最大尺寸，第二长度M2可以是第二方向Y的最大尺寸。
在示例性实施方式中，第一电路单元Q1中第三极板CF3的第二长度M2与第二电路单元Q2和第三电路单元Q3中第三极板CF3的第二长度M2的比值可以约为1至2。例如，比值可以约为1.3左右。
在示例性实施方式中，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第三极板CF3靠近第二极板CF2一侧的边缘可以基本上平齐，每个电路单元中第三极板CF3靠近第二极板CF2一侧的边缘与第二极板CF2靠近第三极板CF3一侧的边缘之间的距离可以基本上相同。
在示例性实施方式中，第三底栅电极Gate3-B可以作为第三晶体管(驱动晶体管)的底栅电极。在第一方向X上，第三底栅电极Gate3-B可以位于第一极板CF1第一方向X的反方向的一侧，在第二方向Y上，第三底栅电极Gate3-B可以位于第二极板CF2第二方向Y的一侧。
在示例性实施方式中，第一电路单元Q1中的第三底栅电极Gate3-B可以包括多个子电极，每个子电极的形状可以为沿着第一方向X延伸的条形状，多个子电极可以沿着第二方向Y间隔设置，形成梳状结构。第二电路单元Q2和第二电路单元Q3中的第三底栅电极Gate3-B可以包括一个子电极，形成“L”形结构。在示例性实施方式中，通过将第一电路单元Q1中的第三底栅电极Gate3-B设置成多个子电极结构，可以实现第一电路单元Q1中驱动晶体管的宽长比大于第二电路单元Q2和第三电路单元Q3中驱动晶体管的宽长比。
在示例性实施方式中，第一电路单元Q1中的每个子电极可以形成晶体管的第一沟道长度L1，第二电路单元Q2中的子电极可以形成晶体管的第二沟道长度L2，第一沟道长度L1与第二沟道长度L2可以基本上相同。
在示例性实施方式中，第一电路单元Q1中的多个子电极可以形成晶体管的多个子宽度z，第二电路单元Q2中的子电极可以形成晶体管的子宽度z，第一电路单元Q1中的第三晶体管的第一沟道宽度＝4*子宽度z，第二电路单元Q2中的第三晶体管的第二沟道宽度＝子宽度z，因而第一电路单元Q1中第三晶体管的宽长比约为第二电路单元Q2中第三晶体管的宽长比的4倍左右。
在示例性实施方式中，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第三底栅电极Gate3-B靠近第二极板CF2一侧的边缘可以基本上平齐，每个电路单元中第三底栅电极Gate3-B靠近第二极板CF2一侧的边缘与第二极板CF2靠近第三底栅电极Gate3-B一侧的边缘之间的距离可以基本 上相同。
在示例性实施方式中，第三极板CF3第一方向X的一侧或者第一方向X的反方向的一侧可以连接有板极连接线，板极连接线的形状可以为沿着第一方向X延伸的条形状，板极连接线的第一端与本电路单元的第三极板CF3连接，板极连接线的第二端沿着第一方向X或者第一方向X的反方向延伸后，与相邻电路单元的第三极板CF3连接，将一个单元行中的第三极板CF3连接起来。在示例性实施方式中，板极连接线可以是2条或者3条，以提高连接可靠性。
在示例性实施方式中，一个单元行中的多个第三极板CF3和多个板极连接线可以为相互连接的一体结构。在示例性实施方式中，由于每个电路单元中的第三极板CF3与后续形成的高压电源线连接，通过将相邻电路单元的第三极板CF3形成相互连接的一体结构，一体结构的第三极板CF3可以复用为高压电源信号线，可以保证一单元行中的多个第三极板CF3具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第一导电层图案还可以包括设置在第三电路单元Q3中的电源电极11，电源电极11的形状可以为沿着第二方向Y延伸的条形状，可以设置在第三极板CF3第一方向X的一侧。在示例性实施方式中，电源电极11被配置为与后续形成的高压电源线连接，实现第三极板与高压电源线之间的连接。
在示例性实施方式中，第三极板CF3和电源电极11可以为相互连接的一体结构。
(12)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和第一半导体薄膜，通过图案化工艺对第一半导体薄膜进行图案化，形成覆盖第一导电层的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，如图8A和图8B所示，图8B为图8A中半导体层的平面示意图。
在示例性实施方式中，每个电路单元的半导体层图案可以至少包括第一晶体管T1的第一有源层AT1至第十二晶体管T12的第十二有源层AT12。
在示例性实施方式中，第一有源层AT1、第二有源层AT2、第四有源层AT4、第七有源层AT7和第十有源层AT10的形状可以为沿着第一方向X延伸的条形状，第三有源层AT3、第五有源层AT5、第六有源层AT6、第八有源层AT8、第九有源层AT9和第十二有源层AT12的形状可以为沿着第二方向Y延伸的条形状，第十一有源层AT11的形状可以为矩形状。
在示例性实施方式中，第一有源层AT1可以位于第二极板CF2和第三极板CF3之间，第一有源层AT1可以作为第一晶体管T1的有源层。第二有源层AT2可以位于第二极板CF2和第三底栅电极Gate3-B之间，第二有源层AT2可以作为第二晶体管T2的有源层。第三有源层AT3在基底上的正投影与第三底栅电极Gate3-B在基底上的正投影至少部分交叠，第三有源层AT3可以作为第三晶体管T3的有源层。第四有源层AT4可以位于第二极板CF2和第三底栅电极Gate3-B之间，且位于第二有源层AT2第一方向X的反方向的一侧，第四有源层AT4可以作为第四晶体管T4的有源层。第五有源层AT5可以位于第三有源层AT3和第四有源层AT4之间，第五有源层AT5可以作为第五晶体管T5的有源层。第六有源层AT6可以位于第一极板CF1和第三底栅电极Gate3-B之间，第六有源层AT6可以作为第六晶体管T6的有源层。第七有源层AT7可以位于第一有源层AT1第一方向X的一侧，第七有源层AT7可以作为第七晶体管T7的有源层。第八有源层AT8可以位于第一极板CF1第二方向Y的反方向的一侧，第八有源层AT8可以作为第八晶体管T8的有源层。第九有源层AT9可以位于第一极板CF1和第八有源层AT8之间，第九有源层AT9可以作为第九晶体管T9的有源层。第十有源层AT10可以位于第七有源层AT7第二方向Y的一侧，第十有源层AT10可以作为第十晶体管T10的有源层。第十一有源层AT11可以位于第十有源层AT10第二方向Y的一侧，第十一有源层AT11可以作为第十一晶体管T11的有源层。第十二有源层AT12可以位于第二有源层AT2和第三有源层AT3之间，且位于第五有源层AT5第一方向X的一侧，第十二有源层AT12可以作为第十二晶体管T12的有源层。
在示例性实施方式中，第一有源层AT1和第七有源层AT7可以位于沿着第一方向X延伸的直线上，第二有源层AT2和第四有源层AT4可以位于 沿着第一方向X延伸的直线上，第五有源层AT5和第十二有源层AT12可以位于沿着第一方向X延伸的直线上。
在示例性实施方式中，沿着第二方向Y，第一电路单元Q1中第三有源层AT3的延伸长度可以大于第二电路单元Q2和第三电路单元Q3中第三有源层AT3的延伸长度，以使第一电路单元Q1中驱动晶体管的宽长比大于第二电路单元Q2和第三电路单元Q3中驱动晶体管的宽长比。
在示例性实施方式中，第一有源层AT1至第十二有源层AT12可以均包括第一区、第二区以及位于第一区和第二区之间的沟道区，多个有源层的第一区和第二区均可以单独设置。
(13)形成第二绝缘层图案。在示例性实施方式中，形成第二绝缘层图案可以包括：在形成前述图案的基底上，沉积第二绝缘薄膜，采用图案化工艺对第二绝缘薄膜进行图案化，形成覆盖半导体层的第二绝缘层，第二绝缘层上设置有多个过孔，如图9所示。
在示例性实施方式中，每个电路单元中第二绝缘层上的多个过孔可以至少包括：第一过孔V1、第二过孔V2、第三过孔V3和第四过孔V4。
在示例性实施方式中，第一过孔V1在基底上的正投影位于第一极板CF1在基底上的正投影的范围之内，第一过孔V1内的第二绝缘层和第一绝缘层被刻蚀掉，暴露出第一极板CF1的表面，第一过孔V1被配置为使后续形成的第一连接电极通过该过孔与第一极板CF1连接。
在示例性实施方式中，第二过孔V2在基底上的正投影位于第二极板CF2在基底上的正投影的范围之内，第二过孔V2内的第二绝缘层和第一绝缘层被刻蚀掉，暴露出第二极板CF2的表面，第二过孔V2被配置为使后续形成的第二连接电极通过该过孔与第二极板CF2连接。
在示例性实施方式中，第三过孔V3在基底上的正投影位于第三极板CF3在基底上的正投影的范围之内，第三过孔V3内的第二绝缘层和第一绝缘层被刻蚀掉，暴露出第三极板CF3的表面，第三过孔V3被配置为使后续形成的第三连接电极通过该过孔与第三极板CF3连接。
在示例性实施方式中，第四过孔V4在基底上的正投影位于第三底栅电 极Gate3-B在基底上的正投影的范围之内，第四过孔V4内的第二绝缘层和第一绝缘层被刻蚀掉，暴露出第三底栅电极Gate3-B的表面，第四过孔V4被配置为使后续形成的第三顶栅电极通过该过孔与第三底栅电极Gate3-B连接。
在示例性实施方式中，第二绝缘层上的多个过孔还可以包括第五过孔V5。第五过孔V5在基底上的正投影位于电源电极11在基底上的正投影的范围之内，第五过孔V5内的第二绝缘层和第一绝缘层被刻蚀掉，暴露出电源电极11的表面，第五过孔V5被配置为使后续形成的第七连接电极通过该过孔与电源电极11连接。
在示例性实施方式中，第一过孔V1至第五过孔V5可以为多个，以增加连接可靠性。
(14)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，沉积第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成设置在第二绝缘层上的第二导电层图案，如图10A和图10B所示，图10B为图10A中第二导电层的平面示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，每个电路单元的第二导电层图案至少包括：第四极板CF4、第五极板CF5、第六极板CF6、第一扫描信号线S1、第二扫描信号线S2、发光信号线EM、初始信号线Vint、高频信号线Hf、高压连接线VDD-C、低压连接线VSS-C、多个栅电极和多个连接电极。
在示例性实施方式中，第四极板CF4的形状可以为“L”形状，且一个角部设置有缺口，第四极板CF4在基底上的正投影与第一极板CF1在基底上的正投影至少部分交叠，第四极板CF4可以作为第一电容的另一个极板，第一极板CF1和第四极板CF4构成像素驱动电路的一个第一电容。
在示例性实施方式中，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第四极板CF4的位置、形状和尺寸可以基本上相同。
在示例性实施方式中，第五极板CF5的形状可以为一个角部设置有缺口的矩形状，第五极板CF5在基底上的正投影与第二极板CF2在基底上的正投影至少部分交叠，第五极板CF5可以作为第二电容的另一个极板，第二极板 CF2和第五极板CF5构成像素驱动电路的一个第二电容。
在示例性实施方式中，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第五极板CF5的位置、形状和尺寸可以基本上相同。
在示例性实施方式中，第六极板CF6的形状可以为一个角部设置有缺口的矩形状，第六极板CF6在基底上的正投影与第三极板CF3在基底上的正投影至少部分交叠，第六极板CF6可以作为存储电容的另一个极板，第三极板CF3和第六极板CF6构成像素驱动电路的一个存储电容。
在示例性实施方式中，第二电路单元Q2和第三电路单元Q3中第六极板CF6的位置、形状和尺寸可以基本上相同，但与第一电路单元Q1中第六极板CF6的形状和尺寸不同。
在示例性实施方式中，第一电路单元Q1中第六极板CF6的面积可以大于第二电路单元Q2中第六极板CF6的面积，第一电路单元Q1中第六极板CF6的面积可以大于第三电路单元Q3中第六极板CF6的面积，以使第一电路单元Q1中存储电容的电容值大于第二电路单元Q2和第三电路单元Q3中存储电容的电容值。
在示例性实施方式中，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第六极板CF6的第一长度M1可以基本上相同，第一电路单元Q1中第六极板CF6的第二长度M2可以大于第二电路单元Q2和第三电路单元Q3中第六极板CF6的第二长度M2，以使第一电路单元Q1中第六极板CF6的面积大于第二电路单元Q2和第三电路单元Q3中第六极板CF6的面积。
在示例性实施方式中，第一电路单元Q1中第六极板CF6的第二长度M2与第二电路单元Q2和第三电路单元Q3中第六极板CF6的第二长度M2的比值可以约为1至2。例如，比值可以约为1.3左右。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、发光信号线EM、初始信号线Vint、高频信号线Hf、高压连接线VDD-C和低压连接线VSS-C的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状。第一扫描信号线S1、发光信号线EM和高频信号线Hf可以位于第四极板CF4和第五极板CF5之间，高频信号线Hf可以位于第四极板CF4第二方向Y的一侧，发光信号线EM可以位于高频信号线Hf第二方向Y的一侧， 第一扫描信号线S1可以位于发光信号线EM第二方向Y的一侧。第二扫描信号线S2和初始信号线Vint可以位于第五极板CF5和第六极板CF6之间，初始信号线Vint可以位于第六极板CF6第二方向Y的一侧，第二扫描信号线S2可以位于初始信号线Vint第二方向Y的一侧。高压连接线VDD-C可以位于第三极板CF3远离第四极板CF4的一侧，低压连接线VSS-C可以位于第六极板CF6远离第五极板CF5的一侧。
在示例性实施方式中，高频信号线Hf远离发光信号线EM的一侧设置有高频连接块，高频连接块被配置为与后续形成的第二十六连接电极连接。
在示例性实施方式中，高压连接线VDD-C靠近第四极板CF4的一侧设置有高压连接块，高压连接块被配置为与后续形成的第十六连接电极连接。
在示例性实施方式中，低压连接线VSS-C靠近第六极板CF6的一侧设置有低压连接块，低压连接块被配置为与后续形成的第三十二连接电极连接。在示例性实施方式中，低压连接块可以设置在第一电路单元Q1和第二电路单元Q2，第三电路单元Q3没有设置低压连接块。
在示例性实施方式中，第一扫描信号线S1可以复用为第一控制线，控制第八晶体管T8的导通和断开，第二扫描信号线S2可以复用为第二控制线，控制第十晶体管T10的导通和断开。
在示例性实施方式中，每个电路单元的多个栅电极可以至少包括第一栅电极Gate1、第二栅电极Gate2、第三顶栅电极Gate3-T、第四栅电极Gate4、第五栅电极Gate5、第六栅电极Gate6、第七栅电极Gate7、第八栅电极Gate8、第九栅电极Gate9、第十栅电极Gate10、第十一栅电极Gate11和第十二栅电极Gate12。
在示例性实施方式中，第二栅电极Gate2、第四栅电极Gate4和第八栅电极Gate8可以设置在第一扫描信号线S1远离发光信号线EM的一侧。第二栅电极Gate2作为第二晶体管T2的栅电极，第二栅电极Gate2在基底上的正投影与第二有源层在基底上的正投影至少部分交叠，第四栅电极Gate4作为第四晶体管T4的栅电极，第四栅电极Gate4在基底上的正投影与第四有源层在基底上的正投影至少部分交叠，第八栅电极Gate8作为第八晶体管T8的栅电极，第八栅电极Gate8在基底上的正投影与第八有源层在基底上的正投影 至少部分交叠。
在示例性实施方式中，第一扫描信号线S1、第二栅电极Gate2、第四栅电极Gate4和第八栅电极Gate8可以为相互连接的一体结构。
在示例性实施方式中，第一栅电极Gate1和第七栅电极Gate7可以设置在第二扫描信号线S2靠近初始信号线Vint的一侧，第十栅电极Gate10可以设置在第二扫描信号线S2远离初始信号线Vint的一侧。第一栅电极Gate1作为第一晶体管T1的栅电极，第一栅电极Gate1在基底上的正投影与第一有源层在基底上的正投影至少部分交叠，第七栅电极Gate7作为第七晶体管T7的栅电极，第七栅电极Gate7在基底上的正投影与第七有源层在基底上的正投影至少部分交叠，第十栅电极Gate10作为第十晶体管T10的栅电极，第十栅电极Gate10在基底上的正投影与第十有源层在基底上的正投影至少部分交叠。
在示例性实施方式中，第二扫描信号线S2、第一栅电极Gate1、第七栅电极Gate7和第十栅电极Gate10可以为相互连接的一体结构。
在示例性实施方式中，第一栅电极Gate1、第二栅电极Gate2、第七栅电极Gate7、第八栅电极Gate8和第十栅电极Gate10可以为2个，形成双栅结构的第一晶体管T1、第二晶体管T2、第七晶体管T7、第八晶体管T8和第十晶体管T10，可以增强驱动能力，提高发光二极管的电流饱和度，防止和减少漏电流的发生。
在示例性实施方式中，第三顶栅电极Gate3-T可以作为第三晶体管T3的顶栅电极，第三顶栅电极Gate3-T在基底上的正投影与第三有源层在基底上的正投影至少部分交叠。第三顶栅电极Gate3-T的形状可以与第三底栅电极Gate3-B的形状基本上相同，第三顶栅电极Gate3-T在基底上的正投影与第三底栅电极Gate3-B在基底上的正投影至少部分交叠，且第三顶栅电极Gate3-T通过第四过孔V4与第三底栅电极Gate3-B连接。
在示例性实施方式中，第三顶栅电极Gate3-T靠近第四极板CF4的一侧设置有第三栅极块103，第三栅极块103的形状可以为沿着第一方向X延伸的折线状，第三栅极块103被配置为与后续形成的第十二连接电极连接。
在示例性实施方式中，第五栅电极Gate5可以作为第五晶体管T5的栅电 极，第五栅电极Gate5在基底上的正投影与第五有源层在基底上的正投影至少部分交叠。第五栅电极Gate5可以位于第一扫描信号线S1和第三顶栅电极Gate3-T之间，第五栅电极Gate5的形状可以为梳状。
在示例性实施方式中，第五栅电极Gate5靠近第一扫描信号线S1的一侧设置有第五栅极块105，第五栅极块105的形状可以为沿着第二方向Y延伸的条形状，第五栅极块105被配置为与后续形成的第二十七连接电极连接。
在示例性实施方式中，第六栅电极Gate6可以作为第六晶体管T6的栅电极，第六栅电极Gate6在基底上的正投影与第六有源层在基底上的正投影至少部分交叠。第六栅电极Gate6可以位于第四极板CF4和第三顶栅电极Gate3-T之间，第六栅电极Gate6的形状可以为梳状。
在示例性实施方式中，第六栅电极Gate6靠近第一扫描信号线S1的一侧设置有第六栅极块106，第六栅极块106的形状可以为沿着第二方向Y延伸的折线状，第六栅极块106被配置为与后续形成的第二十二连接电极连接。
在示例性实施方式中，第九栅电极Gate9可以作为第九晶体管T9的栅电极，第九栅电极Gate9在基底上的正投影与第九有源层在基底上的正投影至少部分交叠。第九栅电极Gate9可以位于第四极板CF4靠近第一扫描信号线S1的一侧，且与第四极板CF4连接。
在示例性实施方式中，第四极板CF4和第九栅电极Gate9可以为相互连接的一体结构。
在示例性实施方式中，第十一栅电极Gate11可以作为第十一晶体管T11的栅电极，第十一栅电极Gate11在基底上的正投影与第十一有源层在基底上的正投影至少部分交叠。第十一栅电极Gate11可以位于第五极板CF5第一方向X的一侧，第十一栅电极Gate11的形状可以为沿着第一方向X延伸的折线状。
在示例性实施方式中，第十二栅电极Gate12可以作为第十二晶体管T12的栅电极，第十二栅电极Gate12在基底上的正投影与第十二有源层在基底上的正投影至少部分交叠。第十二栅电极Gate12可以位于第一扫描信号线S1和第三顶栅电极Gate3-T之间，第十二栅电极Gate12的形状可以为梳状。
在示例性实施方式中，第十二栅电极Gate12远离第五栅电极Gate5的一侧设置有第十二栅极块112，第十二栅极块112的形状可以为沿着第一方向X延伸的条形状，第十二栅极块112被配置为与后续形成的第二十三连接电极连接。
在示例性实施方式中，每个电路单元的多个连接电极至少包括：第一连接电极CO1、第二连接电极CO2、第三连接电极CO3、第四连接电极CO4、第五连接电极CO5和第六连接电极CO6。
在示例性实施方式中，第一连接电极CO1的形状可以为矩形状，可以位于第四极板CF4的缺口处，第一连接电极CO1通过第一过孔V1与第一极板CF1连接。
在示例性实施方式中，第二连接电极CO2的形状可以为矩形状，可以位于第五极板CF5的缺口处，第二连接电极CO2通过第二过孔V2与第二极板CF2连接，且第二连接电极CO2可以与第十一栅电极Gate11连接。
在示例性实施方式中，第二连接电极CO2和第十一栅电极Gate11可以为相互连接的一体结构。
在示例性实施方式中，第三连接电极CO3的形状可以为矩形状，可以位于第六极板CF6的缺口处，第三连接电极CO3通过第三过孔V3与第三极板CF3连接。
在示例性实施方式中，第四连接电极CO4的形状可以为沿着第二方向Y延伸的折线状，在第一方向X上，第四连接电极CO4可以设置在第五栅电极Gate5和第十二栅电极Gate12之间，在第二方向Y上，第四连接电极CO4可以设置在第一扫描信号线S1第二方向Y的一侧，第四连接电极CO4被配置为与后续形成的第十三连接电极和第十五连接电极连接。
在示例性实施方式中，第五连接电极CO5的形状可以为沿着第一方向X延伸的折线状，可以设置在第一扫描信号线S1和第十二栅电极Gate12之间，第五连接电极CO5被配置为与后续形成的第十九连接电极和第二十连接电极连接。
在示例性实施方式中，第六连接电极CO6的形状可以为沿着第一方向X 延伸的条形状，可以设置在第二扫描信号线S2和高频信号线Hf之间，第六连接电极CO6被配置为与后续形成的第二十五连接电极和第二十六连接电极连接。
在示例性实施方式中，第二导电层图案还可以包括设置在第三电路单元Q3中的第七连接电极CO7，第七连接电极CO7的形状可以为矩形状，第七连接电极CO7通过第五过孔V5与电源电极11连接，第七连接电极CO7被配置为与后续形成的第三十三连接电极连接。
在示例性实施方式中，形成第二导电层图案后，可以利用第二导电层作为遮挡，对半导体层进行导体化处理，被第二导电层遮挡区域的半导体层形成第一晶体管T1至第十二晶体管T12的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一晶体管T1至第十二晶体管T12的第一区和第二区均被导体化。
(15)形成第三绝缘层图案。在示例性实施方式中，形成第三绝缘层图案可以包括：在形成前述图案的基底上，沉积第三绝缘薄膜，采用图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第二导电层的第三绝缘层，第三绝缘层上设置有多个过孔，如图11所示。
在示例性实施方式中，每个电路单元中第三绝缘层上的多个过孔至少包括第十一过孔V11至第五十八过孔V58。
在示例性实施方式中，第十一过孔V11在基底上的正投影位于第一有源层的第一区在基底上的正投影的范围之内，第十一过孔V11内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面，第十一过孔V11被配置为使后续形成的第十一连接电极通过该过孔与第一有源层的第一区连接。
在示例性实施方式中，第十二过孔V12在基底上的正投影位于第一有源层的第二区在基底上的正投影的范围之内，第十二过孔V12内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第二区的表面，第十二过孔V12被配置为使后续形成的第十二连接电极通过该过孔与第一有源层的第二区连接。
在示例性实施方式中，第十三过孔V13在基底上的正投影位于第二有源 层的第一区在基底上的正投影的范围之内，第十三过孔V13内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层的第一区的表面，第十三过孔V13被配置为使后续形成的第十二连接电极通过该过孔与第二有源层的第一区连接。
在示例性实施方式中，第十四过孔V14在基底上的正投影位于第二有源层的第二区在基底上的正投影的范围之内，第十四过孔V14内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层的第二区的表面，第十四过孔V14被配置为使后续形成的第十三连接电极通过该过孔与第二有源层的第二区连接。
在示例性实施方式中，第十五过孔V15在基底上的正投影位于第三有源层的第一区在基底上的正投影的范围之内，第十五过孔V15内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第三有源层的第一区的表面，第十五过孔V15被配置为使后续形成的第十四连接电极通过该过孔与第三有源层的第一区连接。
在示例性实施方式中，第十六过孔V16在基底上的正投影位于第三有源层的第二区在基底上的正投影的范围之内，第十六过孔V16内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第三有源层的第二区的表面，第十六过孔V16被配置为使后续形成的第十五连接电极通过该过孔与第三有源层的第二区连接。
在示例性实施方式中，第十七过孔V17在基底上的正投影位于第四有源层的第一区在基底上的正投影的范围之内，第十七过孔V17内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面，第十七过孔V17被配置为使后续形成的数据信号线通过该过孔与第四有源层的第一区连接。
在示例性实施方式中，第十八过孔V18在基底上的正投影位于第四有源层的第二区在基底上的正投影的范围之内，第十八过孔V18内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第二区的表面，第十八过孔V18被配置为使后续形成的第十四连接电极通过该过孔与第四有源层的第二区连接。
在示例性实施方式中，第十九过孔V19在基底上的正投影位于第五有源 层的第一区在基底上的正投影的范围之内，第十九过孔V19内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面，第十九过孔V19被配置为使后续形成的第十六连接电极通过该过孔与第五有源层的第一区连接。
在示例性实施方式中，第二十过孔V20在基底上的正投影位于第五有源层的第二区在基底上的正投影的范围之内，第二十过孔V20内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第二区的表面，第二十过孔V20被配置为使后续形成的第十四连接电极通过该过孔与第五有源层的第二区连接。
在示例性实施方式中，第十九过孔V19和第二十过孔V20均为多个，多个第十九过孔V19和多个第二十过孔V20在第二方向Y上交替设置。
在示例性实施方式中，第二十一过孔V21在基底上的正投影位于第六有源层的第一区在基底上的正投影的范围之内，第二十一过孔V21内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第一区的表面，第二十一过孔V21被配置为使后续形成的第十五连接电极通过该过孔与第六有源层的第一区连接。
在示例性实施方式中，第二十二过孔V22在基底上的正投影位于第六有源层的第二区在基底上的正投影的范围之内，第二十二过孔V22内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区的表面，第二十二过孔V22被配置为使后续形成的第十七接电极通过该过孔与第六有源层的第二区连接。
在示例性实施方式中，第二十一过孔V21和第二十二过孔V22均为多个，多个第二十一过孔V21和多个第二十二过孔V22在第二方向Y上交替设置。
在示例性实施方式中，第二十三过孔V23在基底上的正投影位于第七有源层的第一区在基底上的正投影的范围之内，第二十三过孔V23内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第七区的表面，第二十三过孔V23被配置为使后续形成的第十八连接电极通过该过孔与第七有源层的第一区连接。
在示例性实施方式中，第二十四过孔V24在基底上的正投影位于第七有 源层的第二区在基底上的正投影的范围之内，第二十四过孔V24内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第二区的表面，第二十四过孔V24被配置为使后续形成的第十九连接电极通过该过孔与第七有源层的第二区连接。
在示例性实施方式中，第二十五过孔V25在基底上的正投影位于第十二有源层的第一区在基底上的正投影的范围之内，第二十五过孔V25内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第十二有源层的第一区的表面，第二十五过孔V25被配置为使后续形成的第十七接电极通过该过孔与第十二有源层的第一区连接。
在示例性实施方式中，第二十六过孔V26在基底上的正投影位于第十二有源层的第二区在基底上的正投影的范围之内，第二十六过孔V26内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第十二有源层的第二区的表面，第二十六过孔V26被配置为使后续形成的第二十连接电极通过该过孔与第十二有源层的第二区连接。
在示例性实施方式中，第二十五过孔V25和第二十六过孔V26均为多个，多个第二十五过孔V25和多个第二十六过孔V26在第二方向Y上交替设置。
在示例性实施方式中，第二十七过孔V27在基底上的正投影位于第八有源层的第一区在基底上的正投影的范围之内，第二十七过孔V27内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第八有源层的第九区的表面，第二十七过孔V27被配置为使后续形成的时长信号线通过该过孔与第八有源层的第一区连接。
在示例性实施方式中，第二十八过孔V28在基底上的正投影位于第八有源层的第二区在基底上的正投影的范围之内，第二十八过孔V28内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第八有源层的第二区的表面，第二十八过孔V28被配置为使后续形成的第二十一连接电极通过该过孔与第八有源层的第二区连接。
在示例性实施方式中，第二十九过孔V29在基底上的正投影位于第九有源层的第一区在基底上的正投影的范围之内，第二十九过孔V29内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第九有源层的第一区的表面，第二十九 过孔V29被配置为使后续形成的第二十二连接电极通过该过孔与第九有源层的第一区连接。
在示例性实施方式中，第三十过孔V30在基底上的正投影位于第九有源层的第二区在基底上的正投影的范围之内，第三十过孔V30内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第九有源层的第二区的表面，第三十过孔V30被配置为使后续形成的第二十三连接电极通过该过孔与第九有源层的第二区连接。
在示例性实施方式中，第三十一过孔V31在基底上的正投影位于第十有源层的第一区在基底上的正投影的范围之内，第三十一过孔V31内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第十有源层的第一区的表面，第三十一过孔V31被配置为使后续形成的时长信号线通过该过孔与第十有源层的第一区连接。
在示例性实施方式中，第三十二过孔V32在基底上的正投影位于第十有源层的第二区在基底上的正投影的范围之内，第三十二过孔V32内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第十有源层的第二区的表面，第三十二过孔V32被配置为使后续形成的第二十四连接电极通过该过孔与第十有源层的第二区连接。
在示例性实施方式中，第三十三过孔V33在基底上的正投影位于第十一有源层的第一区在基底上的正投影的范围之内，第三十三过孔V33内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第十一有源层的第一区的表面，第三十三过孔V33被配置为使后续形成的第二十五连接电极通过该过孔与第十一有源层的第一区连接。
在示例性实施方式中，第三十四过孔V34在基底上的正投影位于第十一有源层的第二区在基底上的正投影的范围之内，第三十四过孔V34内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第十一有源层的第二区的表面，第三十四过孔V34被配置为使后续形成的第二十三连接电极通过该过孔与第十一有源层的第二区连接。
在示例性实施方式中，第三十五过孔V35和第三十六过孔V36在基底上的正投影位于发光信号线EM在基底上的正投影的范围之内，第三十五过孔 V35和第三十六过孔V36内的第三绝缘层被刻蚀掉，分别暴露出发光信号线EM的表面，第三十五过孔V35和第三十六过孔V36被配置为使后续形成的第二十二连接电极和第二十七连接电极分别通过上述过孔分别与发光信号线EM连接。
在示例性实施方式中，第三十七过孔V37、第三十八过孔V38和第三十九过孔V39在基底上的正投影分别位于初始信号线Vint在基底上的正投影的范围之内，第三十七过孔V37、第三十八过孔V38和第三十九过孔V39内的第三绝缘层被刻蚀掉，分别暴露出初始信号线Vint的表面，第三十七过孔V37、第三十八过孔V38和第三十九过孔V39被配置为使后续形成的第十一连接电极、第十八连接电极和第二十八连接电极分别通过上述过孔分别与初始信号线Vint连接。
在示例性实施方式中，第四十过孔V40在基底上的正投影位于高频信号线Hf的高频连接块在基底上的正投影的范围之内，第四十过孔V40内的第三绝缘层被刻蚀掉，暴露出高频连接块的表面，第四十过孔V40被配置为使后续形成的第二十六连接电极通过该过孔与高频信号线Hf连接。
在示例性实施方式中，第四十一过孔V41在基底上的正投影位于高压连接线VDD-C的高压连接块在基底上的正投影的范围之内，第四十一过孔V41内的第三绝缘层被刻蚀掉，暴露出高压连接块的表面，第四十一过孔V41被配置为使后续形成的第十六连接电极通过该过孔与高压连接线VDD-C连接。
在示例性实施方式中，第四十二过孔V42在基底上的正投影位于第五极板CF5在基底上的正投影的范围之内，第四十二过孔V42内的第三绝缘层被刻蚀掉，暴露出第五极板CF5的表面，第四十二过孔V42被配置为使后续形成的第二十八连接电极通过该过孔与第五极板CF5连接。
在示例性实施方式中，第四十三过孔V43在基底上的正投影位于第六极板CF6在基底上的正投影的范围之内，第四十三过孔V43内的第三绝缘层被刻蚀掉，暴露出第六极板CF6的表面，第四十三过孔V43被配置为使后续形成的第十二连接电极通过该过孔与第六极板CF6连接。
在示例性实施方式中，第四十四过孔V44在基底上的正投影位于第一连接电极CO1在基底上的正投影的范围之内，第四十四过孔V44内的第三绝 缘层被刻蚀掉，暴露出第一连接电极CO1的表面，第四十四过孔V44被配置为使后续形成的第七极板通过该过孔与第一连接电极CO1连接。
在示例性实施方式中，第四十五过孔V45在基底上的正投影位于第二连接电极CO2在基底上的正投影的范围之内，第四十五过孔V45内的第三绝缘层被刻蚀掉，暴露出第二连接电极CO2的表面，第四十五过孔V45被配置为使后续形成的第八极板通过该过孔与第二连接电极CO2连接。
在示例性实施方式中，第四十六过孔V46在基底上的正投影位于第三连接电极CO3在基底上的正投影的范围之内，第四十六过孔V46内的第三绝缘层被刻蚀掉，暴露出第三连接电极CO3的表面，第四十六过孔V46被配置为使后续形成的第九极板通过该过孔与第三连接电极CO3连接。
在示例性实施方式中，第四十七过孔V47在基底上的正投影位于第四连接电极CO4的第一端在基底上的正投影的范围之内，第四十七过孔V47内的第三绝缘层被刻蚀掉，暴露出第四连接电极CO4的第一端的表面，第四十七过孔V47被配置为使后续形成的第十三连接电极通过该过孔与第四连接电极CO4的第一端连接。
在示例性实施方式中，第四十八过孔V48在基底上的正投影位于第四连接电极CO4的第二端在基底上的正投影的范围之内，第四十八过孔V48内的第三绝缘层被刻蚀掉，暴露出第四连接电极CO4的第二端的表面，第四十八过孔V48被配置为使后续形成的第十五连接电极通过该过孔与第四连接电极CO4的第二端连接。
在示例性实施方式中，第四十九过孔V49在基底上的正投影位于第五连接电极CO5的第一端在基底上的正投影的范围之内，第四十九过孔V49内的第三绝缘层被刻蚀掉，暴露出第五连接电极CO5的第一端的表面，第四十九过孔V49被配置为使后续形成的第二十连接电极通过该过孔与第五连接电极CO5的第一端连接。
在示例性实施方式中，第五十过孔V50在基底上的正投影位于第五连接电极CO5的第二端在基底上的正投影的范围之内，第五十过孔V50内的第三绝缘层被刻蚀掉，暴露出第五连接电极CO5的第二端的表面，第五十过孔V50被配置为使后续形成的第十九连接电极通过该过孔与第五连接电极CO5 的第二端连接。
在示例性实施方式中，第五十一过孔V51在基底上的正投影位于第六连接电极CO6的第一端在基底上的正投影的范围之内，第五十一过孔V51内的第三绝缘层被刻蚀掉，暴露出第六连接电极CO6的第一端的表面，第五十一过孔V51被配置为使后续形成的第二十五连接电极通过该过孔与第六连接电极CO6的第一端连接。
在示例性实施方式中，第五十二过孔V52在基底上的正投影位于第六连接电极CO6的第二端在基底上的正投影的范围之内，第五十二过孔V52内的第三绝缘层被刻蚀掉，暴露出第六连接电极CO6的第二端的表面，第五十二过孔V52被配置为使后续形成的第二十六连接电极通过该过孔与第六连接电极CO6的第二端连接。
在示例性实施方式中，第五十三过孔V53在基底上的正投影位于第三顶栅电极Gate3-T的第三栅极块103在基底上的正投影的范围之内，第五十三过孔V53内的第三绝缘层被刻蚀掉，暴露出第三栅极块103的表面，第五十三过孔V53被配置为使后续形成的第十二连接电极通过该过孔与第三顶栅电极Gate3-T连接。
在示例性实施方式中，第五十四过孔V54在基底上的正投影位于第五栅电极Gate5的第五栅极块105在基底上的正投影的范围之内，第五十四过孔V54内的第三绝缘层被刻蚀掉，暴露出第五栅极块105的表面，第五十四过孔V54被配置为使后续形成的第二十七连接电极通过该过孔与第五栅电极Gate5连接。
在示例性实施方式中，第五十五过孔V55在基底上的正投影位于第六栅电极Gate6的第六栅极块106在基底上的正投影的范围之内，第五十五过孔V55内的第三绝缘层被刻蚀掉，暴露出第六栅极块106的表面，第五十五过孔V55被配置为使后续形成的第二十二连接电极通过该过孔与第六栅电极Gate6连接。
在示例性实施方式中，第五十六过孔V56在基底上的正投影位于第十二栅电极Gate12的第十二栅极块112在基底上的正投影的范围之内，第五十六过孔V56内的第三绝缘层被刻蚀掉，暴露出第十二栅极块112的表面，第五 十六过孔V56被配置为使后续形成的第二十三连接电极通过该过孔与第十二栅电极Gate12连接。
在示例性实施方式中，第五十七过孔V57在基底上的正投影位于第九栅电极Gate9在基底上的正投影的范围之内，第五十七过孔V57内的第三绝缘层被刻蚀掉，暴露出第九栅电极Gate9的表面，第五十七过孔V57被配置为使后续形成的第二十一连接电极通过该过孔与第九栅电极Gate9连接。
在示例性实施方式中，第五十八过孔V58在基底上的正投影位于第十一栅电极Gate11在基底上的正投影的范围之内，第五十八过孔V58内的第三绝缘层被刻蚀掉，暴露出第十一栅电极Gate11的表面，第五十八过孔V58被配置为使后续形成的第二十四连接电极通过该过孔与第十一栅电极Gate11连接。
在示例性实施方式中，第三绝缘层上的多个过孔还可以包括第五十九过孔V59至第六十二过孔V62。
在示例性实施方式中，第五十九过孔V59在基底上的正投影位于第三电路单元Q3中高压连接线VDD-C在基底上的正投影的范围之内，第五十九过孔V59内的第三绝缘层被刻蚀掉，暴露出高压连接线VDD-C的表面，第五十九过孔V59被配置为使后续形成的第三十一连接电极通过该过孔与高压连接线VDD-C连接。
在示例性实施方式中，第六十过孔V60在基底上的正投影位于第一电路单元Q1和第二电路单元Q2中低压连接线VSS-C的低压连接块在基底上的正投影的范围之内，第六十过孔V60内的第三绝缘层被刻蚀掉，暴露出低压连接块的表面，第六十过孔V60被配置为使后续形成的第三十二连接电极通过该过孔与低压连接线VSS-C连接。
在示例性实施方式中，第六十一过孔V61在基底上的正投影位于第三电路单元Q3中的第七连接电极CO7在基底上的正投影的范围之内，第六十一过孔V61内的第三绝缘层被刻蚀掉，暴露出第七连接电极CO7的表面，第六十一过孔V61被配置为使后续形成的第三十三连接电极通过该过孔与第七连接电极CO7连接。
在示例性实施方式中，第六十二过孔V62在基底上的正投影位于第三电 路单元Q3中的电源电极11在基底上的正投影的范围之内，第六十二过孔V62内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出电源电极11的表面，第六十二过孔V62被配置为使后续形成的第三十三连接电极通过该过孔与电源电极11连接。
(16)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第三绝缘层上的第三导电层图案，如图12A和图12B所示，图12B为图12A中第三导电层的平面示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，每个电路单元的第三导电层图案至少包括：数据信号线DataI、时长信号线DataT、第七极板CF7、第八极板CF8、第九极板CF9、阳极连接块12、第十一连接电极CO11至第二十八连接电极CO28。
在示例性实施方式中，数据信号线DataI的形状可以为主体部分沿着第二方向Y延伸的线形状，可以位于电路单元第一方向X的反方向的一侧，数据信号线DataI通过第十七过孔V17与第四有源层的第一区连接，因而实现了数据信号线DataI将数据信号写入第四晶体管T4的第一极。
在示例性实施方式中，时长信号线DataT的形状可以为主体部分沿着第二方向Y延伸的线形状，可以位于电路单元第一方向X的一侧，一方面，时长信号线DataT通过第二十七过孔V27与第八有源层的第一区连接，另一方面，时长信号线DataT通过第三十一过孔V31与第十有源层的第一区连接，因而实现了时长信号线DataT将时长信号分别写入第八晶体管T8的第一极和第十晶体管T10的第一极。
在示例性实施方式中，第七极板CF7的形状可以为“L”形状，第七极板CF7在基底上的正投影与第四极板CF4在基底上的正投影至少部分交叠，且第七极板CF7通过第四十四过孔V44与第一连接电极CO1连接。第七极板CF7可以作为第一电容的又一个极板，第四极板CF4和第七极板CF7构成像素驱动电路的另一个第一电容。
在示例性实施方式中，由于第七极板CF7通过第四十四过孔V44与第一连接电极CO1连接，而第一连接电极CO1通过过孔与第一极板CF1连接， 因而第一极板CF1和第七极板CF7具有相同的电位，使得第一极板CF1、第四极板CF4和第三极板97构成并联结构的第一电容，第一极板CF1和第四极板CF4构成像素驱动电路的一个第一电容，第四极板CF4和第七极板CF7构成像素驱动电路的另一个第一电容，两个第一电容并联。
在示例性实施方式中，第八极板CF8的形状可以为矩形状，第八极板CF8在基底上的正投影与第五极板CF5在基底上的正投影至少部分交叠，且第八极板CF8通过第四十五过孔V45与第二连接电极CO2连接。第八极板CF8可以作为第二电容的又一个极板，第五极板CF5和第八极板CF8构成像素驱动电路的另一个第二电容。
在示例性实施方式中，由于第八极板CF8通过第四十五过孔V45与第二连接电极CO2连接，而第二连接电极CO2通过过孔与第二极板CF2连接，因而第二极板CF2和第八极板CF8具有相同的电位，使得第二极板CF2、第五极板CF5和第八极板CF8构成并联结构的第二电容，第二极板CF2和第五极板CF5构成像素驱动电路的一个第二电容，第五极板CF5和第八极板CF8构成像素驱动电路的另一个第二电容，两个第二电容并联。
在示例性实施方式中，第九极板CF9的形状可以为矩形状，第九极板CF9在基底上的正投影与第六极板CF6在基底上的正投影至少部分交叠，且第九极板CF9通过第四十六过孔V46与第三连接电极CO3连接。第九极板CF9可以作为存储电容的又一个极板，第六极板CF6和第九极板CF9构成像素驱动电路的另一个存储电容。
在示例性实施方式中，由于第九极板CF9通过第四十六过孔V46与第三连接电极CO3连接，而第三连接电极CO3通过过孔与第三极板CF3连接，因而第三极板CF3和第九极板CF9具有相同的电位，使得第三极板CF3、第六极板CF6和第九极板CF9构成并联结构的存储电容，第三极板CF3和第六极板CF6构成像素驱动电路的一个存储电容，第六极板CF6和第九极板CF9构成像素驱动电路的另一个存储电容，两个存储电容并联。
在示例性实施方式中，第二电路单元Q2和第三电路单元Q3中第九极板CF9的位置、形状和尺寸可以基本上相同，但与第一电路单元Q1中第九极板CF9的形状和尺寸不同。
在示例性实施方式中，第一电路单元Q1中第九极板CF9的面积可以大于第二电路单元Q2中第九极板CF9的面积，第一电路单元Q1中第九极板CF9的面积可以大于第三电路单元Q3中第九极板CF9的面积，以使第一电路单元Q1中存储电容的电容值大于第二电路单元Q2和第三电路单元Q3中存储电容的电容值。
在示例性实施方式中，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第九极板CF9的第一长度M1可以基本上相同，第一电路单元Q1中第九极板CF9的第二长度M2可以大于第二电路单元Q2和第三电路单元Q3中第九极板CF9的第二长度M2，以使第一电路单元Q1中第九极板CF9的面积大于第二电路单元Q2和第三电路单元Q3中第九极板CF9的面积。
在示例性实施方式中，第一电路单元Q1中第九极板CF9的第二长度M2与第二电路单元Q2和第三电路单元Q3中第九极板CF9的第二长度M2的比值可以约为1至2。例如，比值可以约为1.3左右。
在示例性实施方式中，第十一连接电极CO11的形状可以为沿着第二方向Y延伸的条形状，第十一连接电极CO11的第一端通过第十一过孔V11与第一有源层的第一区连接，第十一连接电极CO11的第二端通过第三十七过孔V37与初始信号线Vint连接，因而实现了初始信号线Vint将初始信号写入第一晶体管T1的第一极。
在示例性实施方式中，第十二连接电极CO12的形状可以为沿着第二方向Y延伸的条形状，第十二连接电极CO12靠近第九极板CF9的第一端通过第四十三过孔V43与第六极板CF6连接，第十二连接电极CO12靠近第七极板CF7的第二端通过第五十三过孔V53与第三栅极块103连接，第十二连接电极CO12的第一端和第二端之间的部分，一方面通过第十二过孔V12与第一有源层的第二区连接，另一方面通过第十三过孔V13与第二有源层的第一区连接。在示例性实施方式中，由于第三栅极块103与第三顶栅电极Gate3-T连接，第三顶栅电极Gate3-T与第三底栅电极Gate3-B连接，因而第十二连接电极CO12使得第一晶体管T1的第二极、第二晶体管T2的第一极、第三晶体管T3的栅电极和第六极板CF6具有相同的电位(即像素驱动电路的第三节点N3)，第十二连接电极CO12可以称为第三节点电极。
在示例性实施方式中，第十三连接电极CO13的形状可以为沿着第一方向X延伸的条形状，第十三连接电极CO13的第一端通过第十四过孔V14与第二有源层的第二区连接，第十三连接电极CO13的第二端通过第四十七过孔V47与第四连接电极CO4的第一端连接。
在示例性实施方式中，第十四连接电极CO14的形状可以为沿着第二方向Y延伸的折线状，第十四连接电极CO14的第一端通过第十五过孔V15与第三有源层的第一区连接，第十四连接电极CO14的第二端通过第十八过孔V18与第四有源层的第二区连接，第十四连接电极CO14的第一端和第二端之间的部分，通过第二十过孔V20与第五有源层的第二区连接。在示例性实施方式中，第十四连接电极CO14使得第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极具有相同的电位(即像素驱动电路的第五节点N5)，第十四连接电极CO14可以称为第五节点电极。
在示例性实施方式中，第十五连接电极CO15的形状可以为沿着第一方向X延伸的折线状，第十五连接电极CO15的第一端通过第十六过孔V16与第三有源层的第二区连接，第十五连接电极CO15的第二端通过第二十一过孔V21与第六有源层的第一区连接，第十五连接电极CO15的第一端和第二端之间的部分通过第四十八过孔V48与第四连接电极CO4的第二端连接。在示例性实施方式中，由于第四连接电极CO4通过过孔与第十三连接电极CO13连接，而第十三连接电极CO13与第二有源层的第二区连接，因而第十五连接电极CO15使得第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极具有相同的电位(即像素驱动电路的第四节点N4)，第十五连接电极CO15可以称为第四节点电极。
在示例性实施方式中，第十六连接电极CO16的形状可以为沿着第二方向Y延伸的折线状，第十六连接电极CO16的第一端通过第十九过孔V19与第五有源层的第一区连接，第十六连接电极CO16的第二端通过第四十一过孔V41与高压连接线VDD-C连接。
在示例性实施方式中，第十七连接电极CO17的形状可以为沿着第二方向Y延伸的折线状，第十七连接电极CO17的第一端通过第二十二过孔V22与第六有源层的第二区连接，第十七连接电极CO17的第二端通过第二十五 过孔V25与第十二有源层的第一区连接，因而实现了第六晶体管T6的第二极和第十二晶体管T12的第一极的连接。
在示例性实施方式中，第十八连接电极CO18的形状可以为沿着第二方向Y延伸的折线状，第十八连接电极CO18的第一端通过第三十八过孔V38与初始信号线Vint连接，第十八连接电极CO18的第二端与第七极板CF7连接，第十八连接电极CO18的第一端和第二端之间的部分通过第二十三过孔V23与第七有源层的第一区连接，实现了初始信号线Vint将初始信号写入第七晶体管T7的第一极和第一电容的一个极板。
在示例性实施方式中，第十九连接电极CO19的形状可以为沿着第二方向Y延伸的折线状，第十九连接电极CO19的第一端通过第二十四过孔V24与第七有源层的第二区连接，第十九连接电极CO19的第二端通过第五十过孔V50与第五连接电极CO5的第二端连接。
在示例性实施方式中，第二十连接电极CO20的形状可以为沿着第二方向Y延伸的折线状，第二十连接电极CO20的第一端通过第二十六过孔V26与第十二有源层的第二区连接，第二十连接电极CO20的第二端通过第四十九过孔V49与第五连接电极CO5的第一端连接。
在示例性实施方式中，由于第二十连接电极CO20与第五连接电极CO5的第一端连接，第十九连接电极CO19与第五连接电极CO5的第二端连接，因而相互连接的第十九连接电极CO19、第五连接电极CO5和第二十连接电极CO20使得第七晶体管T7的第二极和第十二晶体管T12的第二极具有相同的电位(即像素驱动电路的第二节点N2)。
在示例性实施方式中，阳极连接块12可以设置在第十九连接电极CO19远离第七极板CF7的一侧，且通过连接线与第十九连接电极CO19连接，阳极连接块12被配置为与后续形成的阳极连接电极连接。
在示例性实施方式中，第一电路单元Q1的阳极连接块12可以位于第九极板CF9第一方向X的一侧，第二电路单元Q2和第三电路单元Q3的阳极连接块12可以位于第九极板CF9第二方向Y的反方向的一侧。
在示例性实施方式中，第二十一连接电极CO21的形状可以为沿着第二方向Y延伸的条形状，第二十一连接电极CO21的第一端通过第二十八过孔 V28与第八有源层的第二区连接，第二十一连接电极CO21的第二端通过第五十七过孔V57与第九栅电极Gate9连接。由于第九栅电极Gate9与第四极板CF4连接，因而第二十一连接电极CO21使得第八晶体管T8的第二极、第九晶体管T9的栅电极和第四极板CF4具有相同的电位(即像素驱动电路的第六节点N6)。
在示例性实施方式中，第二十二连接电极CO22的形状可以为沿着第二方向Y延伸的条形状，第二十二连接电极CO22的第一端通过第二十九过孔V29与第九有源层的第一区连接，第二十二连接电极CO22的第二端通过第三十五过孔V35与发光信号线EM连接，第二十二连接电极CO22的第一端和第二端之间的部分通过第五十五过孔V55与第六栅电极Gate6的第六栅极块106连接，因而实现了发光信号线EM控制第六晶体管T6的导通或断开，且将发光信号写入第九晶体管T9的第一极。
在示例性实施方式中，第二十三连接电极CO23的形状可以为沿着第二方向Y延伸的条形状，第二十三连接电极CO23的第一端通过第三十过孔V30与第九有源层的第二区连接，第二十三连接电极CO23的第二端通过第三十四过孔V34与第十一有源层的第二区连接，第二十三连接电极CO23的第一端和第二端之间的部分通过第五十六过孔V56与第十二栅电极Gate12的第十二栅极块112连接，因而实现了第九晶体管T9的第二极、第十一晶体管T11的第二极和第十二晶体管T12的栅电极具有相同的电位(即像素驱动电路的第一节点N1)。
在示例性实施方式中，第二十四连接电极CO24的形状可以为沿着第二方向Y延伸的条形状，第二十四连接电极CO24的第一端通过第三十二过孔V32与第十有源层的第二区连接，第二十四连接电极CO24的第二端通过第五十八过孔V58与第十一栅电极Gate11连接。由于第十一栅电极Gate11与第二连接电极CO2连接，第二连接电极CO2通过过孔与第二极板CF2连接，因而第二十四连接电极CO24使得第十晶体管T10的第二极、第十一晶体管T11的栅电极和第二极板CF2具有相同的电位(即像素驱动电路的第七节点N7)。
在示例性实施方式中，第二十五连接电极CO25的形状可以为“L”形状， 第二十五连接电极CO25的第一端通过第三十三过孔V33与第十一有源层的第一区连接，第二十五连接电极CO25的第二端通过第五十一过孔V51与第六连接电极CO6的第一端连接。
在示例性实施方式中，第二十六连接电极CO26的形状可以为沿着第二方向Y延伸的条形状，第二十六连接电极CO26的第一端通过第四十过孔V40与高频信号线Hf连接，第二十六连接电极CO26的第二端通过第五十二过孔V52与第六连接电极CO6的第二端连接。由于高频信号线Hf通过第二十六连接电极CO26、第六连接电极CO6和第二十五连接电极CO25与第十一有源层的第一区连接，因而实现了高频信号线Hf将高频信号写入第十一晶体管T11的第一极。
在示例性实施方式中，第二十七连接电极CO27的形状可以为沿着第二方向Y延伸的条形状，第二十七连接电极CO27的第一端通过第三十六过孔V36与发光信号线EM连接，第二十七连接电极CO27的第二端通过第五十四过孔V54与第五栅电极Gate5的第五栅极块105连接连接，因而实现了发光信号线EM控制第五晶体管T5的导通或断开。
在示例性实施方式中，第二十八连接电极CO28的形状可以为沿着第二方向Y延伸的条形状，第二十八连接电极CO28的第一端通过第三十九过孔V39与初始信号线Vint连接，第二十八连接电极CO28的第二端通过第四十二过孔V42与第五极板CF5连接，实现了初始信号线Vint将初始信号写入第二电容的一个极板。
在示例性实施方式中，第三导电层还可以包括第三十一连接电极CO31、第三十二连接电极CO32和第三十三连接电极CO33。
在示例性实施方式中，第三十一连接电极CO31的形状可以为矩形状，可以设置在第三电路单元Q3中，第三十一连接电极CO31通过第五十九过孔V59与第三电路单元Q3中的高压连接线VDD-C连接。在示例性实施方式中，第三十一连接电极CO31被配置为与后续形成的高压电源线连接。
在示例性实施方式中，第三十二连接电极CO32的形状可以为矩形状，可以设置在第一电路单元Q1和第二电路单元Q2中，第三十二连接电极CO32通过第六十过孔V60与第一电路单元Q1和第二电路单元Q2中的低压连接 线VSS-C的低压连接块连接。在示例性实施方式中，第三十二连接电极CO32被配置为与后续形成的低压电源线连接。
在示例性实施方式中，第三十三连接电极CO33的形状可以为矩形状，可以设置在第三电路单元Q3中，一方面，第三十三连接电极CO33通过第六十一过孔V61与第七连接电极CO7连接，另一方面，第三十三连接电极CO33通过第六十二过孔V62与电源电极11连接。在示例性实施方式中，第三十三连接电极CO33被配置为与后续形成的高压电源线连接。
(17)形成第四绝缘层和第一平坦层图案。在示例性实施方式中，形成第四绝缘层和第一平坦层图案可以包括：在形成前述图案的基底上，先涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，随后沉积第四绝缘薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成覆盖第三导电层图案的第一平坦层以及设置在第一平坦层远离基底一侧的第四绝缘层，第四绝缘层和第一平坦层上设置有多个过孔，如图13所示。
在示例性实施方式中，每个电路单元中第四绝缘层和第一平坦层上的多个过孔至少包括第六十五过孔V65。
在示例性实施方式中，第六十五过孔V65在基底上的正投影位于阳极连接块12在基底上的正投影的范围之内，第六十五过孔V65内的第四绝缘薄膜和第一平坦薄膜被去掉，暴露出阳极连接块12的表面，第六十五过孔V65被配置为使后续形成的阳极连接电极通过该过孔与阳极连接块12连接。
在示例性实施方式中，第四绝缘层和第一平坦层上的多个过孔还可以包括第六十六过孔V66、第六十七过孔V67和第六十八过孔V68。
在示例性实施方式中，第六十六过孔V66在基底上的正投影位于第三十一连接电极CO31在基底上的正投影的范围之内，可以设置在第三电路单元Q3中，第六十六过孔V66内的第四绝缘薄膜和第一平坦薄膜被去掉，暴露出第三十一连接电极CO31的表面，第六十六过孔V66被配置为使后续形成的高压电源线通过该过孔与第三十一连接电极CO31连接。
在示例性实施方式中，第六十七过孔V67在基底上的正投影位于第三十二连接电极CO32在基底上的正投影的范围之内，可以分别设置在第一电路单元Q1和第二电路单元Q2中，第六十七过孔V67内的第四绝缘薄膜和第 一平坦薄膜被去掉，暴露出第三十二连接电极CO32的表面，第六十七过孔V67被配置为使后续形成的低压电源线通过该过孔与第三十二连接电极CO32连接。
在示例性实施方式中，第六十八过孔V68在基底上的正投影位于第三十三连接电极CO33在基底上的正投影的范围之内，可以设置在第三电路单元Q3中，第六十八过孔V68内的第四绝缘薄膜和第一平坦薄膜被去掉，暴露出第三十三连接电极CO33的表面，第六十八过孔V68被配置为使后续形成的高压电源线通过该过孔与第三十三连接电极CO33连接。
(18)形成第四导电层图案。在示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第四绝缘层上的第四导电层图案，如图14A和图14B所示，图14B为图14A中第四导电层的平面示意图。在示例性实施方式中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，每个电路单元的第四导电层图案至少包括阳极连接电极13。
在示例性实施方式中，阳极连接电极13的形状可以为矩形状，阳极连接电极13通过第六十五过孔V65与阳极连接块12连接，阳极连接电极13被配置为与发光二极管的第一极绑定连接。由于阳极连接块12与第十九连接电极CO19连接，第十九连接电极CO19通过第五连接电极CO5与第二十连接电极CO20连接，第二十连接电极CO20通过过孔与第十二有源层的第二区连接，因而实现了阳极连接电极13与第七晶体管T7的第二极和第十二晶体管T12第二极的连接，像素驱动电路可以驱动发光二极管发光。
在示例性实施方式中，第四导电层图案还可以至少包括高压电源线VDD和低压电源线VSS，高压电源线可以称为第一电源线，低压电源线可以称为第二电源线。
在示例性实施方式中，高压电源线VDD的形状可以为沿着第二方向Y延伸的线形状，可以设置在第三电路单元Q3中，一方面，高压电源线VDD通过第六十六过孔V66与第三十一连接电极CO31连接，另一方面，高压电源线VDD通过第六十八过孔V68与第三十三连接电极CO33连接。
在示例性实施方式中，由于第三十一连接电极CO31通过过孔与高压连接线VDD-C连接，因而沿着第一方向X延伸的高压连接线VDD-C和沿着第二方向Y延伸的高压电源线VDD构成网状连通结构，不仅可以最大限度地降低了电源传输线的电阻，减小了电源电压的压降，有效提升了显示基板中电源电压的均一性，有效提升了信号面内的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，由于高压连接线VDD-C通过过孔分别与每个电路单元的第十六连接电极CO16连接，第十六连接电极CO16通过过孔与第五有源层的第一区连接，因而实现了高压电源线VDD将第一电源信号写入每个电路单元的第五晶体管T5的第一极。
在示例性实施方式中，由于第三十三连接电极CO33通过第七连接电极CO7与电源电极11连接，电源电极11与一体结构的第三极板CF3连接，第三极板CF3通过第三连接电极CO3与第九极板CF9连接，因而使得存储电容的第三极板CF3和第九极板CF9具有高压电源线VDD的电位。由于第六极板CF6通过过孔与第十二连接电极CO12连接，第十二连接电极CO12通过该过孔与第三顶栅电极Gate3-T连接，因而第六极板CF6具有第三晶体管T3的栅电极的电位。这样，具有高压电源线VDD电位的第三极板CF3和具有第三晶体管T3的栅电极电位的第六极板CF6构成像素驱动电路的一个存储电容，具有第三晶体管T3的栅电极电位的第六极板CF6和具有高压电源线VDD电位的第九极板CF9构成像素驱动电路的另一个存储电容。
在示例性实施方式中，在第三电路单元Q3中，高压电源线VDD在基底上的正投影与第十二连接电极CO12在基底上的正投影至少部分交叠。由于高压电源线VDD为恒定电位，因而高压电源线VDD不仅可以有效屏蔽数据电压跳变和其它信号对像素驱动电路中关键节点的影响，避免了数据电压跳变和其它信号影响关键节点的电位，有效避免了串扰恶化，提高了显示效果。
在示例性实施方式中，低压电源线VSS的形状可以为沿着第二方向Y延伸的线形状，可以分别设置在第一电路单元Q1和第二电路单元Q2中，低压电源线VSS通过第六十七过孔V67与第三十二连接电极CO32连接。
在示例性实施方式中，由于第三十二连接电极CO32通过过孔与低压连 接线VSS-C连接，因而因而沿着第一方向X延伸的低压连接线VSS-C和沿着第二方向Y延伸的低压电源线VSS构成网状连通结构，不仅可以最大限度地降低了电源传输线的电阻，减小了电源电压的压降，有效提升了显示基板中电源电压的均一性，有效提升了信号面内的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，在第二电路单元Q2中，低压电源线VSS在基底上的正投影与第十二连接电极CO12在基底上的正投影至少部分交叠。由于低压电源线VSS为恒定电位，因而低压电源线VSS不仅可以有效屏蔽数据电压跳变和其它信号对像素驱动电路中关键节点的影响，避免了数据电压跳变和其它信号影响关键节点的电位，有效避免了串扰恶化，提高了显示效果。
(19)形成第五绝缘层和第二平坦层图案。在示例性实施方式中，形成第五绝缘层和第二平坦层图案可以包括：在形成前述图案的基底上，先沉积第五绝缘薄膜，通过图案化工艺对第五绝缘薄膜进行图案化，随后涂覆第二平坦薄膜，随后沉积第六绝缘薄膜，采用图案化工艺对第五绝缘薄膜、第二平坦薄膜和第六绝缘薄膜进行图案化，形成覆盖第四导电层图案的第五绝缘层、设置在第五绝缘层远离基底一侧的第二平坦层、设置在第二平坦层远离基底一侧的第六绝缘层，第五绝缘层、第二平坦层和第六绝缘层上设置有多个绑定孔，如图15所示。
在示例性实施方式中，每个电路单元中的多个绑定孔包括：第一绑定孔K1和第二绑定孔K2。
在示例性实施方式中，第一绑定孔K1的形状可以为矩形状，第一绑定孔K1在基底上的正投影位于阳极连接电极13在基底上的正投影的范围之内，第一绑定孔K1内的第六绝缘薄膜、第二平坦薄膜和第五绝缘薄膜被去掉，暴露出阳极连接电极13的表面，阳极连接电极13被第一绑定孔K1暴露的区域可以作为阳极焊盘，第一绑定孔K1被配置为使发光二极管的第一极通过该绑定孔与阳极连接电极13绑定连接。
在示例性实施方式中，第二绑定孔K2的形状可以为矩形状，第二绑定孔K2在基底上的正投影位于低压电源线VSS在基底上的正投影的范围之内，第二绑定孔K2内的第六绝缘薄膜、第二平坦薄膜和第五绝缘薄膜被去掉， 暴露出低压电源线VSS的表面，低压电源线VSS被第二绑定孔K2暴露的区域可以作为阴极焊盘，第二绑定孔K2被配置为使发光二极管的第二极通过该绑定孔与低压电源线VSS连接。
至此，在基底上制备完成本示例性实施例的驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、发光信号线、数据信号线、时长信号线、初始信号线、高频信号线和高压电源线。在垂直于显示基板的平面内，驱动电路层可以至少包括在基底上依次设置的第一导电层、第一绝缘层、半导体层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第一平坦层、第四绝缘层、第四导电层、第五绝缘层和第二平坦层。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性基底可以包括但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在示例性实施方式中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一平坦层和第二平坦层可以采用有机材料，如树脂等。半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等一种或多种材料，即本公开适用于基于氧化物(Oxide)技术、硅技术以及有机物技术制造的晶体管。例如，半导体层的材料可以为多晶硅(p-Si)。
在示例性实施方式中，后续制备流程可以包括：先利用点胶机向多个第一绑定孔和多个第二绑定孔内加入绑定材料(例如锡膏)，通过转印固晶工 艺将多个发光二极管的第一极通过第一绑定孔与阳极连接电极绑定连接，多个发光二极管的第二极通过第二绑定孔与低压电源线绑定连接，完成发光二极管与对应像素驱动电路的连接。随后，在形成前述结构的衬底上涂覆覆盖薄膜形成覆盖层，覆盖层覆盖多个发光二极管。在示例性实施方式中，多个发光二极管和覆盖层可以构成发光结构层。
从以上描述的显示基板的结构以及制备过程可以看出，本公开示例性实施例所提供的显示基板，通过将第一电路单元中的第三晶体管的宽长比设置成大于第二电路单元和第三电路单元中的第三晶体管的宽长比，可以很好地适应红色发光二极管与蓝色发光二极管和绿色发光二极管的出光效率及良率差异，既可以满足红色发光二极管所需的电流值，又可以实现更多的灰阶，避免了现有结构亮度不满足需求或者不能实现更多灰阶等不良。
本公开通过增加第一电路单元中存储电容的电容值，可以有效减小第三晶体管栅极电压的跳变量，可以保证栅极电压的正确写入。研究发现，不同电路单元中第三晶体管的宽长比不同时，第三晶体管的寄生电容(如栅源电容Cgs和栅漏电容Cgd)也会随着的宽长比的增大而增大，第三晶体管的栅极电压会因为电容耦合在栅电极断开以及发光信号线导通时发生跳变，从而影响栅极电压的正确写入。由于栅极电压的跳变量与存储电容的电容值成反比，因而增加存储电容的电容值可以有效减小第三晶体管栅极电压的跳变量。
本公开通过采用并联结构的第一电容、第二电容和存储电容，在保证电容容量的前提下，最大限度地减小了第一电容、第二电容和存储电容的占用空间，有利于实现高分辨率显示。本公开通过形成网络连通结构的高压电源线和低压电源线，可以最大限度地降低了电源传输线的电阻，减小了电源电压的压降，有效提升了显示基板中电源电压的均一性，有效提升了信号面内的均一性，有效提升了显示均一性，提高了显示品质和显示质量。本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
图16为本公开示例性实施例另一种像素驱动电路的等效电路图，示意了一种11T3C的像素驱动电路结构。在示例性实施方式中，本示例性实施例提供的像素驱动电路可以至少包括电流控制子电路DK和时长控制子电路SK。 电流控制子电路DK可以至少包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和存储电容Cs，时长控制子电路SK可以至少包括第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第一电容C1和第二电容C2。与图3所示像素驱动电路不同的是，本实施例没有设置第十二晶体管T12，时长控制子电路SK与第六晶体管T6的栅电极连接。
在示例性实施方式中，本实施例第一节点N1分别与第六晶体管T6的栅电极、第九晶体管T9的第二极和第十一晶体管T11的第二极连接，第二节点N2分别与第六晶体管T6的第二极、第七晶体管T7的第二极和发光二极管EL的阳极连接，其它节点与图3所示结构基本上相同。
在示例性实施方式中，第六晶体管T6的栅电极与第一节点N1连接，第六晶体管T6的第一极与第四节点N4连接，第六晶体管T6的第二极与第二节点N2连接。第一晶体管T1至第五晶体管T5、第七晶体管T7第十一晶体管T11、第一电容C1、第二电容C2和存储电容Cs的连接关系与图3所示结构基本上相同，这里不再赘述。
图17为本公开示例性实施例另一种显示基板的结构示意图，示意了三个电路单元的结构，电路单元包括图16所示的像素驱动电路。如图17所示，多个电路单元可以至少包括沿着第一方向X依次设置的第一电路单元Q1、空白单元KB、第二电路单元Q2和第三电路单元Q3，空白单元KB被配置为设置发光二极管和透过光线，空白单元KB内没有设置像素驱动电路。第一电路单元Q1中的第一像素驱动电路被配置为与第一发光二极管连接，第二电路单元Q2中的第二像素驱动电路被配置为与第二发光二极管连接，第三电路单元Q3中的第三像素驱动电路被配置为与第三发光二极管连接。第一发光二极管可以为红色发光二极管，第二发光二极管可以为绿色发光二极管，第三发光二极管可以为蓝色发光二极管。
在示例性实施方式中，第一电路单元Q1中的第一像素驱动电路可以至少包括第一驱动晶体管DTFT1和第一存储电容Cs1，第二电路单元Q2中的第二像素驱动电路可以至少包括第二驱动晶体管DTFT2和第二存储电容Cs2，第三电路单元Q3中的第三像素驱动电路可以至少包括第三驱动晶体管 DTFT3和第三存储电容Cs3。第一驱动晶体管DTFT1的宽长比(W/L)可以大于第二驱动晶体管DTFT2和第三驱动晶体管DTFT3的宽长比，第一存储电容Cs1的电容值可以大于第二存储电容Cs2和第三存储电容Cs3的电容值。
在示例性实施方式中，至少一个电路单元可以包括沿着第一方向X延伸的高频连接线Hf-C和沿着第二方向Y延伸的高频信号线Hf，高频信号线Hf可以通过过孔与高频连接线Hf-C连接，形成传输高频信号的网状连通结构。
在示例性实施方式中，至少一个电路单元可以包括沿着第一方向X延伸的高压连接线VDD-C和沿着第二方向Y延伸的高压电源线VDD，高压连接线VDD与相应的像素驱动电路连接，高压电源线VDD可以通过过孔与高压连接线VDD-C连接，形成传输高压电源信号的网状连通结构。
在示例性实施方式中，低压连接线可以至少包括第一低压连接线VSS-C1和第二低压连接线VSS-C2，低压电源线可以至少包括第一低压电源线VSS1和第二低压电源线VSS2。
在示例性实施方式中，至少一个电路单元可以包括沿着第一方向X延伸的第一低压连接线VSS-C1和沿着第二方向Y延伸的第一低压电源线VSS1，第一低压电源线VSS1与第一发光二极管连接，第一低压电源线VSS1可以通过过孔与第一低压连接线VSS-C1连接，形成传输第一低压电源信号的网状连通结构。
在示例性实施方式中，至少一个电路单元可以包括沿着第一方向X延伸的第二低压连接线VSS-C2和沿着第二方向Y延伸的第二低压电源线VSS2，第二低压电源线VSS2与第二发光二极管和第三发光二极管连接，第二低压电源线VSS2可以通过过孔与第二低压连接线VSS-C2连接，形成传输第二低压电源信号的网状连通结构。
图18A为本公开另一种第一驱动晶体管的结构示意图，图18B为本公开另一种第二驱动晶体管的结构示意图。如图18A和图18B所示，第一驱动晶体管DTFT1和第二驱动晶体管DTFT2均可以包括有源层Active、栅电极Gate、第一极Source和第二极Drain，第一驱动晶体管DTFT1具有第一宽长比，第二驱动晶体管DTFT2具有第二宽长比，第一宽长比可以大于第二宽长比。
在示例性实施方式中，栅电极Gate、第一极Source和第二极Drain均为沿着第一方向X延伸的条形状，有源层Active均为沿着第二方向Y延伸的条形状，第一驱动晶体管DTFT1具有第一沟道长度L1和第一沟道宽度W1，第二驱动晶体管DTFT2具有第二沟道长度L2和第二沟道宽度W2，第一沟道长度L1与第二沟道长度L2可以基本上相同，第一沟道宽度W1可以大于第二沟道宽度W2。
在示例性实施方式中，第一沟道宽度W1与第二沟道宽度W2的比值可以约为3左右。
在示例性实施方式中，第一驱动晶体管DTFT1和第二驱动晶体管DTFT2的栅电极Gate、第一极Source和第二极Drain的形状和尺寸可以基本上相同，第一驱动晶体管DTFT1的有源层Active的宽度可以大于第二驱动晶体管DTFT2的有源层Active的宽度，宽度可以为有源层Active第一方向X的尺寸。
在示例性实施方式中，第二驱动晶体管DTFT2的第二沟道宽度与第三驱动晶体管DTFT3的第三沟道宽度可以基本上相同，第二驱动晶体管DTFT2的第二沟道长度与第三驱动晶体管DTFT3的第三沟道长度可以基本上相同。
图19A为本公开另一种第一存储电容的结构示意图，图19B为本公开另一种第二存储电容的结构示意图。如图19A和图19B所示，第一存储电容Cs1具有第一面积，第二存储电容Cs2具有第二面积，第一面积可以大于第二面积。
在示例性实施方式中，第一存储电容Cs1的第一长度M1与第二存储电容Cs2的第一长度M1可以基本上相同，第一存储电容Cs1的第二长度M2可以大于第二存储电容Cs2的第二长度M2。
在示例性实施方式中，第一存储电容Cs1的第二长度M2与第二存储电容Cs2的第二长度M2的比值可以约为1.8左右。
在示例性实施方式中，第二存储电容Cs2的第一长度M1与第三存储电容Cs3的第一长度M1可以基本上相同，第二存储电容Cs2的第二长度M2与第三存储电容Cs3的第二长度M2可以基本上相同。
在示例性实施方式中，本实施例驱动电路层的制备过程可以包括如下操作。
(21)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，沉积第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成设置在基底上的第一导电层图案，如图20所示。
在示例性实施方式中，每个电路单元的第一导电层图案可以至少包括：第一极板CF1、第二极板CF2、第三极板CF3和第三底栅电极Gate3-B。
在示例性实施方式中，第一极板CF1、第二极板CF2和第三极板CF3的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板CF1和第二极板CF2可以设置在电路单元第二方向Y的反方向的一侧，第三底栅电极Gate3-B可以设置在电路单元第二方向Y的一侧，第三极板CF3可以位于第一极板CF1与第三底栅电极Gate3-B之间。
在示例性实施方式中，第一电路单元Q1中第三极板CF3的面积可以大于第二电路单元Q2中第三极板CF3的面积，第一电路单元Q1中第三极板CF3的面积可以大于第三电路单元Q3中第三极板CF3的面积，第二电路单元Q2和第三电路单元Q3中第三极板CF3的位置、形状和尺寸可以基本上相同。
在示例性实施方式中，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第三极板CF3的第一长度M1可以基本上相同，第一电路单元Q1中第三极板CF3的第二长度M2可以大于第二电路单元Q2和第三电路单元Q3中第三极板CF3的第二长度M2，以使第一电路单元Q1中第三极板CF3的面积大于第二电路单元Q2和第三电路单元Q3中第三极板CF3的面积。
在示例性实施方式中，第一电路单元Q1中第三极板CF3的第二长度M2与第二电路单元Q2和第三电路单元Q3中第三极板CF3的第二长度M2的比值可以约为1至2。例如，比值可以约为1.8左右。
在示例性实施方式中，第三底栅电极Gate3-B的形状可以为“L”形状，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第三底栅电极Gate3-B的形状可以基本上相同。
在示例性实施方式中，一个单元行中的第三极板CF3可以通过板极连接线相互连接，一个单元行中的多个第三极板CF3和多个板极连接线可以为相互连接的一体结构。
(22)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和第一半导体薄膜，通过图案化工艺对第一半导体薄膜进行图案化，形成覆盖第一导电层的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，如图21A和图21B所示，图21B为图21A中半导体层的平面示意图。
在示例性实施方式中，每个电路单元的半导体层图案可以至少包括第一晶体管T1的第一有源层AT1至第十一晶体管T11的第十一有源层AT11。
在示例性实施方式中，第一有源层AT1、第二有源层AT2、第四有源层AT4、第七有源层AT7、第八有源层AT8、第九有源层AT9和第十有源层AT10的形状可以为沿着第一方向X延伸的条形状，第三有源层AT3和第十一有源层AT11的形状可以为矩形状，第五有源层AT5和第六有源层AT6的形状可以为沿着第二方向Y延伸的条形状。
在示例性实施方式中，第一有源层AT1、第七有源层AT7至第十一有源层AT118可以位于第一极板CF1与第三极板CF3之间。第八有源层AT8可以位于第一极板CF1第二方向Y的一侧，第十有源层AT10可以位于第八有源层AT8第二方向Y的一侧，第十一有源层AT11可以位于第十有源层AT10第二方向Y的一侧，第一有源层AT1和第七有源层AT7可以位于第十有源层AT10第一方向X的一侧，第一有源层AT1和第七有源层AT7可以为相互连接的一体结构，第九有源层AT9可以位于第十一有源层AT11第一方向X的一侧。
在示例性实施方式中，第二有源层AT2至第六有源层AT6可以位于第三极板CF3第二方向Y的一侧，第三有源层AT3在基底上的正投影与第三底栅电极Gate3-B在基底上的正投影至少部分交叠，第二有源层AT2可以位于第三有源层AT3第一方向X的一侧，第四有源层AT4可以位于第三有源层AT3第一方向X的反方向的一侧，第五有源层AT5和第六有源层AT6可以位于第三极板CF3和第三有源层AT3之间，第六有源层AT6可以位于第 五有源层AT5第一方向X的一侧。
在示例性实施方式中，第一电路单元Q1中第三有源层AT3的宽度可以大于第二电路单元Q2和第三电路单元Q3中第三有源层AT3的宽度，宽度可以为第三有源层AT3第一方向X的尺寸，以使得第一电路单元Q1中驱动晶体管的宽长比大于第二电路单元Q2和第三电路单元Q3中驱动晶体管的宽长比。
(23)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖半导体层的第二绝缘层，以及设置在第二绝缘层上的第二导电层图案，如图22A和图22B所示，图22B为图22A中第二导电层的平面示意图。
在示例性实施方式中，每个电路单元的第二导电层图案至少包括：第四极板CF4、第五极板CF5、第六极板CF6、第一扫描信号线S1、第二扫描信号线S2、发光信号线EM、第一控制线CT1、初始信号线Vint、高频连接线Hf-C、高压连接线VDD-C、第一低压连接线VSS-C1、第二低压连接线VSS-C2、多个栅电极和多个连接电极。
在示例性实施方式中，第四极板CF4、第五极板CF5和第六极板CF6的形状可以为一个角部设置有缺口的矩形状。第四极板CF4在基底上的正投影与第一极板CF1在基底上的正投影至少部分交叠，第四极板CF4可以作为第一电容的另一个极板，第一极板CF1和第四极板CF4构成像素驱动电路的一个第一电容。第五极板CF5在基底上的正投影与第二极板CF2在基底上的正投影至少部分交叠，第五极板CF5可以作为第二电容的另一个极板，第二极板CF2和第五极板CF5构成像素驱动电路的一个第二电容。第六极板CF6在基底上的正投影与第三极板CF3在基底上的正投影至少部分交叠，第六极板CF6可以作为存储电容的另一个极板，第三极板CF3和第六极板CF6构成像素驱动电路的一个存储电容。
在示例性实施方式中，第二电路单元Q2和第三电路单元Q3中第六极板CF6的位置、形状和尺寸可以基本上相同，第一电路单元Q1中第六极板CF6的面积可以大于第二电路单元Q2中第六极板CF6的面积，第一电路单元Q1 中第六极板CF6的面积可以大于第三电路单元Q3中第六极板CF6的面积，以使第一电路单元Q1中存储电容的电容值大于第二电路单元Q2和第三电路单元Q3中存储电容的电容值。
在示例性实施方式中，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第六极板CF6的第一长度M1可以基本上相同，第一电路单元Q1中第六极板CF6的第二长度M2可以大于第二电路单元Q2和第三电路单元Q3中第六极板CF6的第二长度M2，以使第一电路单元Q1中第六极板CF6的面积大于第二电路单元Q2和第三电路单元Q3中第六极板CF6的面积。
在示例性实施方式中，第一电路单元Q1中第六极板CF6的第二长度M2与第二电路单元Q2和第三电路单元Q3中第六极板CF6的第二长度M2的比值可以约为1至2。例如，比值可以约为1.8左右。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、发光信号线EM、第一控制线CT1、初始信号线Vint、高频连接线Hf-C、高压连接线VDD-C、第一低压连接线VSS-C1和第二低压连接线VSS-C的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状。第一扫描信号线S1可以位于第六极板CF6第二方向Y的一侧，高频连接线Hf-C、第一低压连接线VSS-C1和第二低压连接线VSS-C可以位于第四极板CF4和第五极板CF5第二方向Y的反方向的一侧，第二扫描信号线S2、发光信号线EM、第一控制线CT1、初始信号线Vint和高压连接线VDD-C可以位于第四极板CF4和第六极板CF6之间。
在示例性实施方式中，第一低压连接线VSS-C1可以位于第四极板CF4和第五极板CF5第二方向Y的反方向的一侧，第二低压连接线VSS-C可以位于第一低压连接线VSS-C1远离第四极板CF4和第五极板CF5的一侧，高频连接线Hf-C可以位于第二低压连接线VSS-C远离第四极板CF4和第五极板CF5的一侧。
在示例性实施方式中，高压连接线VDD-C被配置为与后续形成的高压电源线连接，形成网状连通结构。第一低压连接线VSS-C1被配置为与后续形成的第一低压电源线连接，形成网状连通结构。第二低压连接线VSS-C2被配置为与后续形成的第二低压电源线连接，形成网状连通结构。高频连接 线Hf-C被配置为与后续形成的高频信号线连接，形成网状连通结构。
在示例性实施方式中，初始信号线Vint可以位于第四极板CF4和第五极板CF5第二方向Y的一侧，第一控制线CT1可以位于初始信号线Vint第二方向Y的一侧，第二扫描信号线S2可以位于第一控制线CT1第二方向Y的一侧，高压连接线VDD-C可以位于第二扫描信号线S2第二方向Y的一侧，发光信号线EM可以位于高压连接线VDD-C第二方向Y的一侧。
在示例性实施方式中，第二扫描信号线S2可以复用为第二控制线，控制第十晶体管T10的导通和断开。
在示例性实施方式中，每个电路单元的多个栅电极可以至少包括第一栅电极Gate1、第二栅电极Gate2、第三顶栅电极Gate3-T、第四栅电极Gate4、第五栅电极Gate5、第六栅电极Gate6、第七栅电极Gate7、第八栅电极Gate8、第九栅电极Gate9、第十栅电极Gate10和第十一栅电极Gate11。
在示例性实施方式中，第二栅电极Gate2和第四栅电极Gate4可以设置在第一扫描信号线S1靠近第六极板CF6的一侧。第二栅电极Gate2作为第二晶体管T2的栅电极，第二栅电极Gate2在基底上的正投影与第二有源层在基底上的正投影至少部分交叠，第四栅电极Gate4作为第四晶体管T4的栅电极，第四栅电极Gate4在基底上的正投影与第四有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第一扫描信号线S1、第二栅电极Gate2和第四栅电极Gate4可以为相互连接的一体结构。
在示例性实施方式中，第一栅电极Gate1、第七栅电极Gate7和第十栅电极Gate10可以设置在第二扫描信号线S2远离初始信号线Vint的一侧。第一栅电极Gate1作为第一晶体管T1的栅电极，第一栅电极Gate1在基底上的正投影与第一有源层在基底上的正投影至少部分交叠，第七栅电极Gate7作为第七晶体管T7的栅电极，第七栅电极Gate7在基底上的正投影与第七有源层在基底上的正投影至少部分交叠，第十栅电极Gate10作为第十晶体管T10的栅电极，第十栅电极Gate10在基底上的正投影与第十有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第二扫描信号线S2、第一栅电极Gate1、第七栅电极Gate7和第十栅电极Gate10可以为相互连接的一体结构。
在示例性实施方式中，第八栅电极Gate8可以设置在第一控制线CT1靠 近初始信号线Vint的一侧。第八栅电极Gate8作为第八晶体管T8的栅电极，第八栅电极Gate8在基底上的正投影与第八有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第一控制线CT1和第八栅电极Gate8可以为相互连接的一体结构。
在示例性实施方式中，第三顶栅电极Gate3-T可以作为第三晶体管T3的顶栅电极，第三顶栅电极Gate3-T在基底上的正投影与第三有源层在基底上的正投影至少部分交叠，第三顶栅电极Gate3-T在基底上的正投影与第三底栅电极Gate3-B在基底上的正投影至少部分交叠。
在示例性实施方式中，第三顶栅电极Gate3-T靠近第六极板CF6的一侧设置有第三栅极块103，第三栅极块103的形状可以为沿着第二方向Y延伸的折线状，第三栅极块103的第一端与第三顶栅电极Gate3-T连接，第三栅极块103的第二端与第六极板CF6连接。在示例性实施方式中，第三顶栅电极Gate3-T、第六极板CF6和第三栅极块103可以为相互连接的一体结构。
在示例性实施方式中，第五栅电极Gate5可以作为第五晶体管T5的栅电极，第五栅电极Gate5在基底上的正投影与第五有源层在基底上的正投影至少部分交叠。第五栅电极Gate5可以位于发光信号线EM和第三顶栅电极Gate3-T之间，且位于第三栅极块103第一方向X的反方向的一侧，第五栅电极Gate5的形状可以为梳状。
在示例性实施方式中，第五栅电极Gate5靠近发光信号线EM的一侧设置有第五栅极块105，第五栅极块105的形状可以为沿着第二方向Y延伸的条形状，第五栅极块105的第一端与第五栅电极Gate5连接，第五栅极块105的第二端与发光信号线EM连接，因而实现了发光信号线EM可以控制第五晶体管T5的导通或者断开。在示例性实施方式中，发光信号线EM、第五栅电极Gate5和第五栅极块105可以为相互连接的一体结构。
在示例性实施方式中，第六栅电极Gate6可以作为第六晶体管T6的栅电极，第六栅电极Gate6在基底上的正投影与第六有源层在基底上的正投影至少部分交叠。第六栅电极Gate6可以位于发光信号线EM和第三顶栅电极Gate3-T之间，且位于第三栅极块103第一方向X的一侧，第六栅电极Gate6的形状可以为梳状。
在示例性实施方式中，第六栅电极Gate6靠近发光信号线EM的一侧设置有第六栅极块106，第六栅极块106的形状可以为沿着第二方向Y延伸的条形状，第六栅极块106的第一端与第六栅电极Gate6连接，第六栅极块106的第二端靠近发光信号线EM，第六栅极块106被配置为与后续形成的第六十二连接电极连接。
在示例性实施方式中，第九栅电极Gate9可以作为第九晶体管T9的栅电极，第九栅电极Gate9在基底上的正投影与第九有源层在基底上的正投影至少部分交叠。第九栅电极Gate9可以位于第二扫描信号线S2与高压连接线VDD-C之间，第九栅电极Gate9的形状可以为沿着第二方向Y延伸的条形状。
在示例性实施方式中，第十一栅电极Gate11可以作为第十一晶体管T11的栅电极，第十一栅电极Gate11在基底上的正投影与第十一有源层在基底上的正投影至少部分交叠。第十一栅电极Gate11可以第二扫描信号线S2与高压连接线VDD-C之间，第十一栅电极Gate11的形状可以为沿着第二方向Y延伸的折线状。
在示例性实施方式中，每个电路单元的多个连接电极至少包括第四十一连接电极CO41、第四十二连接电极CO42、第四十三连接电极CO43、第四十四连接电极CO44和第四十五连接电极CO45。
在示例性实施方式中，第四十一连接电极CO41的形状可以为沿着第一方向X延伸的条形状，可以设置在第二扫描信号线S2和高压连接线VDD-C之间，第四十一连接电极CO41被配置为与后续形成的高频信号线和第六十三连接电极连接。
在示例性实施方式中，第四十二连接电极CO42的形状可以为沿着第一方向X延伸的线形状，可以设置在第二扫描信号线S2和高压连接线VDD-C之间，第四十二连接电极CO42被配置为与后续形成的第六十一连接电极和第六十二连接电极连接。
在示例性实施方式中，第四十三连接电极CO43的形状可以为沿着第一方向X延伸的线形状，可以设置在高频连接线Hf-C远离第四极板CF4和第五极板CF5的一侧，第四十三连接电极CO43被配置为与后续形成的第二电 路单元Q2的阳极连接块12和第二电路单元Q2的第五十二连接电极连接。
在示例性实施方式中，第四十四连接电极CO44的形状可以为沿着第一方向X延伸的线形状，可以设置在第四十三连接电极CO43远离高频连接线Hf-C的一侧，第四十四连接电极CO44被配置为与后续形成的第三电路单元Q3的阳极连接块12和第三电路单元Q3的第五十二连接电极连接。
在示例性实施方式中，第四十五连接电极CO45的形状可以为矩形状，可以设置在第四十二连接电极CO42第二方向Y的反方向的一侧，第四十五连接电极CO45被配置为与后续形成的第六十四连接电极连接。
在示例性实施方式中，形成第二导电层图案后，可以利用第二导电层作为遮挡，对半导体层进行导体化处理，被第二导电层遮挡区域的半导体层形成第一晶体管T1至第十二晶体管T12的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一晶体管T1至第十一晶体管T11的第一区和第二区均被导体化。
(24)形成第三绝缘层图案。在示例性实施方式中，形成第三绝缘层图案可以包括：在形成前述图案的基底上，沉积第三绝缘薄膜，采用图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第二导电层的第三绝缘层，第三绝缘层上设置有多个过孔，如图23所示。
在示例性实施方式中，每个电路单元中第三绝缘层上的多个过孔至少包括第十一过孔V11至第二十四过孔V24、第二十七过孔V27至第三十四过孔V34、第七十七过孔V77至第九十九过孔V99。
在示例性实施方式中，第十一过孔V11至第二十四过孔V24、第二十七过孔V27至第三十四过孔V34的结构与前述实施例基本上相同，其中，第十一过孔V11和第二十三过孔V23为共用的过孔。
在示例性实施方式中，第七十七过孔V77和第七十八过孔V78在基底上的正投影位于第十一栅电极Gate11在基底上的正投影的范围之内，第七十七过孔V77和第七十八过孔V78内的第三绝缘层被刻蚀掉，暴露出第十一栅电极Gate11的表面，第七十七过孔V77和第七十八过孔V78被配置为使后续形成的第五十九连接电极和第六十连接电极分别通过上述过孔与第十一栅电极Gate11连接。
在示例性实施方式中，第七十九过孔V79和第八十过孔V80在基底上的正投影位于第四十二连接电极CO42在基底上的正投影的范围之内，第七十九过孔V79和第八十过孔V80内的第三绝缘层被刻蚀掉，分别暴露出第四十二连接电极CO42的第一端和第二端的表面，第七十九过孔V79和第八十过孔V80被配置为使后续形成的第六十一连接电极和第六十二连接电极分别通过上述过孔与第四十二连接电极CO42连接。
在示例性实施方式中，第八十一过孔V81在基底上的正投影位于发光信号线EM在基底上的正投影的范围之内，第八十一过孔V81内的第三绝缘层被刻蚀掉，暴露出发光信号线EM的表面，第八十一过孔V81被配置为使后续形成的第六十四连接电极通过该过孔分别与发光信号线EM连接。
在示例性实施方式中，第八十二过孔V82、第八十三过孔V83和第八十四过孔V84在基底上的正投影分别位于初始信号线Vint在基底上的正投影的范围之内，第八十二过孔V82、第八十三过孔V83和第八十四过孔V84内的第三绝缘层被刻蚀掉，分别暴露出初始信号线Vint的表面，第八十二过孔V82、第八十三过孔V83和第八十四过孔V84被配置为使后续形成的第七极板、第八极板和第五十一连接电极分别通过上述过孔分别与初始信号线Vint连接。
在示例性实施方式中，第八十五过孔V85在基底上的正投影位于高频连接线Hf-C在基底上的正投影的范围之内，第八十五过孔V85内的第三绝缘层被刻蚀掉，暴露出高频连接线Hf-C的表面，第八十五过孔V85被配置为使后续形成的高频信号线通过该过孔与高频连接线Hf-C连接。
在示例性实施方式中，第八十六过孔V86在基底上的正投影位于高压连接线VDD-C在基底上的正投影的范围之内，第八十六过孔V86内的第三绝缘层被刻蚀掉，暴露出高压连接线VDD-C的表面，第八十六过孔V86被配置为使后续形成的第九极板通过该过孔与高压连接线VDD-C连接。
在示例性实施方式中，第八十七过孔V87在基底上的正投影位于第一极板CF1在基底上的正投影的范围之内，第八十七过孔V87内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第一极板CF1的表面，第八十七过孔V87被配置为使后续形成的第七极板通过该过孔与第一极板CF1连接。
在示例性实施方式中，第八十八过孔V88在基底上的正投影位于第二极板CF2在基底上的正投影的范围之内，第八十八过孔V88内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第二极板CF2的表面，第八十八过孔V88被配置为使后续形成的第八极板通过该过孔与第二极板CF2连接。
在示例性实施方式中，第八十九过孔V89在基底上的正投影位于第三极板CF3在基底上的正投影的范围之内，第八十九过孔V89内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第三极板CF3的表面，第八十九过孔V89被配置为使后续形成的第九极板通过该过孔与第三极板CF3连接。
在示例性实施方式中，第九十过孔V90在基底上的正投影位于第四极板CF4在基底上的正投影的范围之内，第九十过孔V90内的第三绝缘层被刻蚀掉，暴露出第四极板CF4的表面，第九十过孔V90被配置为使后续形成的第五十八连接电极通过该过孔与第四极板CF4连接。
在示例性实施方式中，第九十一过孔V91在基底上的正投影位于第五极板CF5在基底上的正投影的范围之内，第九十一过孔V91内的第三绝缘层被刻蚀掉，暴露出第五极板CF5的表面，第九十一过孔V91被配置为使后续形成的第五十九连接电极通过该过孔与第五极板CF5连接。
在示例性实施方式中，第九十二过孔V92在基底上的正投影位于第六极板CF6在基底上的正投影的范围之内，第九十二过孔V92内的第三绝缘层被刻蚀掉，暴露出第六极板CF6的表面，第九十二过孔V92被配置为使后续形成的第五十七连接电极通过该过孔与第六极板CF6连接。
在示例性实施方式中，第九十三过孔V93在基底上的正投影位于第四十一连接电极CO41的第一端在基底上的正投影的范围之内，第九十三过孔V93内的第三绝缘层被刻蚀掉，暴露出第四十一连接电极CO41的第一端的表面，第九十三过孔V93被配置为使后续形成的高频连接线通过该过孔与第四十一连接电极CO41连接。
在示例性实施方式中，第九十四过孔V94在基底上的正投影位于第四十一连接电极CO41的第二端在基底上的正投影的范围之内，第九十四过孔V94内的第三绝缘层被刻蚀掉，暴露出第四十一连接电极CO41的第二端的表面，第九十四过孔V94被配置为使后续形成的第六十三连接电极通过该过孔与第 四十一连接电极CO41的第二端连接。
在示例性实施方式中，第九十五过孔V95在基底上的正投影位于第三顶栅电极Gate3-T在基底上的正投影的范围之内，第九十五过孔V95内的第三绝缘层被刻蚀掉，暴露出第三顶栅电极Gate3-T的表面，第九十五过孔V95被配置为使后续形成的第五十五连接电极通过该过孔与第三顶栅电极Gate3-T连接。
在示例性实施方式中，第九十六过孔V96在基底上的正投影位于第三底栅电极Gate3-B在基底上的正投影的范围之内，第九十六过孔V96内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第三底栅电极Gate3-B的表面，第九十六过孔V96被配置为使后续形成的第五十五连接电极通过该过孔与第三底栅电极Gate3-B连接。
在示例性实施方式中，第九十七过孔V97在基底上的正投影位于第六栅电极Gate6的第六栅极块106在基底上的正投影的范围之内，第九十七过孔V97内的第三绝缘层被刻蚀掉，暴露出第六栅极块106的表面，第九十七过孔V97被配置为使后续形成的第六十二连接电极通过该过孔与第六栅电极Gate6连接。
在示例性实施方式中，第九十八过孔V98在基底上的正投影位于第九栅电极Gate9在基底上的正投影的范围之内，第九十八过孔V98内的第三绝缘层被刻蚀掉，暴露出第九栅电极Gate9的表面，第九十八过孔V98被配置为使后续形成的第五十八连接电极通过该过孔与第九栅电极Gate9连接。
在示例性实施方式中，第九十九过孔V99在基底上的正投影位于第四十五连接电极CO45在基底上的正投影的范围之内，第九十九过孔V99内的第三绝缘层被刻蚀掉，暴露出第四十五连接电极CO45的表面，第九十九过孔V99被配置为使后续形成的第六十四连接电极与第四十五连接电极CO45连接。
在示例性实施方式中，第三绝缘层上的多个过孔还可以包括第一百零一过孔V101至第一百零六过孔V106。
在示例性实施方式中，第一百零一过孔V101可以设置在第二电路单元Q2中，第一百零一过孔V101在基底上的正投影位于第一低压连接线VSS-C1 在基底上的正投影的范围之内，第一百零一过孔V101内的第三绝缘层被刻蚀掉，暴露出第一低压连接线VSS-C1的表面，第一百零一过孔V101被配置为使后续形成的第七十一连接电极通过该过孔与第一低压连接线VSS-C1连接。
在示例性实施方式中，第一百零二过孔V102可以设置在第一电路单元Q1中，第一百零二过孔V102在基底上的正投影位于第二低压连接线VSS-C2在基底上的正投影的范围之内，第一百零二过孔V102内的第三绝缘层被刻蚀掉，暴露出第二低压连接线VSS-C2的表面，第一百零二过孔V102被配置为使后续形成的第七十二连接电极通过该过孔与第二低压连接线VSS-C2连接。
在示例性实施方式中，第一百零三过孔V103在基底上的正投影位于第四十三连接电极CO43的第一端在基底上的正投影的范围之内，第一百零三过孔V103内的第三绝缘层被刻蚀掉，暴露出第四十三连接电极CO43的第一端的表面，第一百零三过孔V103被配置为使后续形成的第二电路单元Q2的阳极连接块通过该过孔与第四十三连接电极CO43的第一端连接。
在示例性实施方式中，第一百零四过孔V104在基底上的正投影位于第四十三连接电极CO43的第二端在基底上的正投影的范围之内，第一百零四过孔V104内的第三绝缘层被刻蚀掉，暴露出第四十三连接电极CO43的第二端的表面，第一百零四过孔V104被配置为使后续形成的第二电路单元Q2的第五十二连接电极通过该过孔与第四十三连接电极CO43的第二端连接。
在示例性实施方式中，第一百零五过孔V105在基底上的正投影位于第四十四连接电极CO44的第一端在基底上的正投影的范围之内，第一百零五过孔V105内的第三绝缘层被刻蚀掉，暴露出第四十四连接电极CO44的第一端的表面，第一百零五过孔V105被配置为使后续形成的第三电路单元Q3的阳极连接块通过该过孔与第四十四连接电极CO44的第一端连接。
在示例性实施方式中，第一百零六过孔V106在基底上的正投影位于第四十四连接电极CO44的第二端在基底上的正投影的范围之内，第一百零六过孔V106内的第三绝缘层被刻蚀掉，暴露出第四十四连接电极CO44的第二端的表面，第一百零六过孔V106被配置为使后续形成的第三电路单元Q3 的第五十二连接电极通过该过孔与第四十四连接电极CO44的第二端连接。
(25)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第三绝缘层上的第三导电层图案，如图24A和图24B所示，图24B为图24A中第三导电层的平面示意图。
在示例性实施方式中，每个电路单元的第三导电层图案至少包括：数据信号线DataI、高频信号线Hf、第七极板CF7、第八极板CF8、第九极板CF9、阳极连接块12、第五十一连接电极CO51至第六十四连接电极CO64。
在示例性实施方式中，数据信号线DataI的形状可以为主体部分沿着第二方向Y延伸的线形状，可以位于电路单元第一方向X的反方向的一侧，数据信号线DataI一方面通过第十七过孔V17与第四有源层的第一区连接，另一方面通过第二十七过孔V27与第八有源层的第一区连接，又一方面通过第三十一过孔V31与第十有源层的第一区连接，因而实现了数据信号线DataI将数据信号分别写入第四晶体管T4的第一极、第八晶体管T8的第一极和第十晶体管T10的第一极。
在示例性实施方式中，数据信号线DataI可以复用为时长信号线DataT。利用数据信号线DataI分别向第八晶体管T8的第一极和第十晶体管T10的第一极提供时长信号。
在示例性实施方式中，高频信号线Hf的形状可以为主体部分沿着第二方向Y延伸的线形状，可以位于数据信号线DataI第一方向X的反方向的一侧，一方面，高频信号线Hf通过第九十三过孔V93与第四十一连接电极CO41的第一端连接，另一方面，高频信号线Hf通过第八十五过孔V85与高频连接线Hf-C连接，实现了沿着第一方向X延伸的高频连接线Hf-C与沿着第二方向Y延伸的高频信号线Hf之间的连接，形成传输高频信号的网状连通结构。
在示例性实施方式中，第七极板CF7的形状可以为矩形状，第七极板CF7在基底上的正投影与第四极板CF4在基底上的正投影至少部分交叠，一方面，第七极板CF7通过第八十七过孔V87与第一极板CF1连接，另一方面，第七极板CF7通过第八十二过孔V82与初始信号线Vint连接。第七极 板CF7可以作为第一电容的又一个极板，第四极板CF4和第七极板CF7构成像素驱动电路的另一个第一电容。由于第七极板CF7通过过孔与第一极板CF1连接，因而第一极板CF1和第七极板CF7具有相同的初始信号电位，使得第一极板CF1、第四极板CF4和第三极板97构成并联结构的第一电容，第一极板CF1和第四极板CF4构成像素驱动电路的一个第一电容，第四极板CF4和第七极板CF7构成像素驱动电路的另一个第一电容，两个第一电容并联。
在示例性实施方式中，第八极板CF8的形状可以为矩形状，第八极板CF8在基底上的正投影与第五极板CF5在基底上的正投影至少部分交叠，一方面，第八极板CF8通过第八十八过孔V88与第二极板CF2连接，另一方面，第八极板CF8通过第八十三过孔V83与初始信号线Vint连接。第八极板CF8可以作为第二电容的又一个极板，第五极板CF5和第八极板CF8构成像素驱动电路的另一个第二电容。由于第八极板CF8通过过孔与第二极板CF2连接，因而第二极板CF2和第八极板CF8具有相同的初始信号电位，使得第二极板CF2、第五极板CF5和第八极板CF8构成并联结构的第二电容，第二极板CF2和第五极板CF5构成像素驱动电路的一个第二电容，第五极板CF5和第八极板CF8构成像素驱动电路的另一个第二电容，两个第二电容并联。
在示例性实施方式中，第九极板CF9的形状可以为矩形状，第九极板CF9在基底上的正投影与第六极板CF6在基底上的正投影至少部分交叠，一方面，第九极板CF9通过第八十九过孔V89与第三极板CF3连接，另一方面，第九极板CF9通过第八十六过孔V86与高压连接线VDD-C连接。第九极板CF9可以作为存储电容的又一个极板，第六极板CF6和第九极板CF9构成像素驱动电路的另一个存储电容。由于第九极板CF9通过过孔与第三极板CF3连接，因而第三极板CF3和第九极板CF9具有相同的第一电源电位，使得第三极板CF3、第六极板CF6和第九极板CF9构成并联结构的存储电容，第三极板CF3和第六极板CF6构成像素驱动电路的一个存储电容，第六极板CF6和第九极板CF9构成像素驱动电路的另一个存储电容，两个存储电容并联。
在示例性实施方式中，第二电路单元Q2和第三电路单元Q3中第九极板CF9的位置、形状和尺寸可以基本上相同，但与第一电路单元Q1中第九极板CF9的形状和尺寸不同。
在示例性实施方式中，第一电路单元Q1中第九极板CF9的面积可以大于第二电路单元Q2和第三电路单元Q3中第九极板CF9的面积，以使第一电路单元Q1中存储电容的电容值大于第二电路单元Q2和第三电路单元Q3中存储电容的电容值。
在示例性实施方式中，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第九极板CF9的第一长度M1可以基本上相同，第一电路单元Q1中第九极板CF9的第二长度M2可以大于第二电路单元Q2和第三电路单元Q3中第九极板CF9的第二长度M2，以使第一电路单元Q1中第九极板CF9的面积大于第二电路单元Q2和第三电路单元Q3中第九极板CF9的面积。
在示例性实施方式中，第一电路单元Q1中第九极板CF9的第二长度M2与第二电路单元Q2和第三电路单元Q3中第九极板CF9的第二长度M2的比值可以约为1至2。例如，比值可以约为1.8左右。
在示例性实施方式中，第五十一连接电极CO51的形状可以为沿着第二方向Y延伸的条形状，第五十一连接电极CO51的第一端通过第十一过孔V11与第一有源层的第一区(也是第七有源层的第一区)连接，第五十一连接电极CO51的第二端通过第八十四过孔V84与初始信号线Vint连接，因而实现了初始信号线Vint将初始信号写入第一晶体管T1的第一极和第七晶体管T7的第一极。
在示例性实施方式中，第五十二连接电极CO52的形状可以为沿着第二方向Y延伸的条形状，第五十二连接电极CO52的第一端通过第二十二过孔V22与第六有源层的第二区连接，第五十二连接电极CO52的第二端通过第二十四过孔V24与第七有源层的第二区连接，因而第五十二连接电极CO52使得第六晶体管T6的第二极和第七晶体管T7的第二极具有相同的电位(即像素驱动电路的第二节点N2)。
在示例性实施方式中，第一电路单元Q1的阳极连接块12可以设置在第一电路单元Q1的第五十二连接电极CO52远离第九极板CF9的一侧，且通 过连接线与第一电路单元Q1的第五十二连接电极CO52连接，因而实现了第一电路单元Q1中阳极连接块12与第五十二连接电极CO52之间的连接。
在示例性实施方式中，第二电路单元Q2的阳极连接块12可以设置在第四十三连接电极CO43第一方向X的反方向的一侧，阳极连接块12通过第一百零三过孔V103与第四十三连接电极CO43的第一端连接，第二电路单元Q2的第五十二连接电极CO52通过第一百零四过孔V104与第四十三连接电极CO43的第二端连接，因而实现了第二电路单元Q2中阳极连接块12与第五十二连接电极CO52之间的连接。
在示例性实施方式中，第三电路单元Q3的阳极连接块12可以设置在第四十四连接电极CO44第一方向X的反方向的一侧，阳极连接块12通过第一百零五过孔V105与第四十四连接电极CO44的第一端连接，第三电路单元Q3的第五十二连接电极CO52通过第一百零六过孔V106与第四十四连接电极CO44的第二端连接，因而实现了第三电路单元Q3中阳极连接块12与第五十二连接电极CO52之间的连接。
在示例性实施方式中，第五十三连接电极CO53的形状为折线状，第五十三连接电极CO53的第一端通过第十四过孔V14与第二有源层的第二区连接，第五十三连接电极CO53的第二端通过第十六过孔V16与第三有源层的第二区连接，第五十三连接电极CO53的第一端和第二端之间的部分，通过第二十一过孔V21与第六有源层的第一区连接，第五十三连接电极CO53使得第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极具有相同的电位(即像素驱动电路的第四节点N4)。
在示例性实施方式中，第五十四连接电极CO54的形状可以为折线状，第五十四连接电极CO54的第一端通过第十五过孔V15与第三有源层的第一区连接，第五十四连接电极CO54的第二端通过第二十过孔V20与第五有源层的第二区连接，第五十四连接电极CO54的第一端和第二端之间的部分，通过第十八过孔V18与第四有源层的第二区连接，第五十四连接电极CO54使得第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极具有相同的电位(即像素驱动电路的第五节点N5)。
在示例性实施方式中，第五十五连接电极CO55的形状可以为折线状， 第五十五连接电极CO55的第一端通过第十三过孔V13与第二有源层的第一区连接，第五十五连接电极CO55的第二端通过第九十五过孔V95与第三顶栅电极Gate3-T连接，第五十五连接电极CO55的第一端和第二端之间的部分，通过第九十六过孔V96与第三底栅电极Gate3-B连接。在示例性实施方式中，第五十五连接电极CO55使得第三顶栅电极Gate3-T与第三底栅电极Gate3-B相互连接，使得第二晶体管T2的第一极与第三晶体管T3的栅电极相互连接。
在示例性实施方式中，第五十六连接电极CO56的形状可以为折线状，第五十六连接电极CO56的第一端通过第十九过孔V19与第五有源层的第一区连接，第五十六连接电极CO56的第二端与第九极板CF9连接，第五十六连接电极CO56使得第五晶体管T5的第一极和第九极板CF9具有相同的电位。
在示例性实施方式中，第五十六连接电极CO56和第九极板CF9可以为相互连接的一体结构。
在示例性实施方式中，第五十七连接电极CO57的形状可以为沿着第二方向Y延伸的折线状，第五十七连接电极CO57的第一端通过第十二过孔V12与第一有源层的第二区连接，第五十七连接电极CO57的第二端通过第九十二过孔V92与第六极板CF6连接，第五十七连接电极CO57使得第一晶体管T1的第二极和第六极板CF6具有相同的电位。由于第三顶栅电极Gate3-T、第六极板CF6和第三栅极块103可以为相互连接的一体结构，第一晶体管T1的第二极与第六极板CF6连接，第二晶体管T2的第一极与第三晶体管T3的栅电极连接，因而第五十五连接电极CO55和第五十七连接电极CO57使得第一晶体管T1的第二极、第二晶体管T2的第一极、第三晶体管T3的栅电极和第六极板CF6具有相同的电位(即像素驱动电路的第三节点N3)。
在示例性实施方式中，第五十八连接电极CO58的形状可以为沿着第二方向Y延伸的折线状，第五十八连接电极CO58的第一端通过第九十八过孔V98与第九栅电极Gate9连接，第五十八连接电极CO58的第二端通过第九十过孔V90与第四极板CF4连接，第五十八连接电极CO58的第一端和第二 端之间的部分通过第二十八过孔V28与第八有源层的第二区连接，第五十八连接电极CO58使得第八晶体管T8的第二极、第九晶体管T9的栅电极和第四极板CF4具有相同的电位(即像素驱动电路的第六节点N6)。
在示例性实施方式中，第五十九连接电极CO59的形状可以为沿着第二方向Y延伸的条形状，第五十九连接电极CO59的第一端通过第七十七过孔V77与第十一栅电极Gate11连接，第五十九连接电极CO59的第二端通过第九十一过孔V91与第五极板CF5连接，第五十九连接电极CO59使得第十一晶体管T11的栅电极和第五极板CF5具有相同的电位。
在示例性实施方式中，第六十连接电极CO60的形状可以为沿着第一方向X延伸的条形状，第六十连接电极CO60的第一端通过第三十二过孔V32与第十有源层的第二区连接，第六十连接电极CO60的第二端通过第七十八过孔V78与第十一栅电极Gate11连接，第六十连接电极CO60使得第十一晶体管T11的栅电极和第十晶体管T10的第二极具有相同的电位。由于第十一晶体管T11的栅电极分别与第五极板CF5和第十晶体管T10的第二极连接，因而第五十九连接电极CO59和第六十连接电极CO60使得第十晶体管T10的第二极、第十一晶体管T11的栅电极和第五极板CF5具有相同的电位(即像素驱动电路的第七节点N7)。
在示例性实施方式中，第六十一连接电极CO61的形状可以为沿着第一方向X延伸的条形状，第六十一连接电极CO61的第一端通过第三十四过孔V34与第十一有源层的第二区连接，第六十一连接电极CO61的第二端通过第七十九过孔V79与第四十二连接电极CO42的第一端连接，第六十一连接电极CO61的第一端和第二端之间的部分通过第三十过孔V30与第九有源层的第二区连接，第六十一连接电极CO61，第六十一连接电极CO61使得第九晶体管T9的第二极和第十一晶体管T11的第二极相互连接。
在示例性实施方式中，第六十二连接电极CO62的形状可以为沿着第二方向Y延伸的条形状，第六十二连接电极CO62的第一端通过第八十过孔V80与第四十二连接电极CO42的第二端连接，第六十二连接电极CO62的第二端通过第九十七过孔V97与第六栅极块106连接。由于第六栅极块106与第六栅电极Gate6连接，第六十一连接电极CO61和第六十二连接电极 CO62通过第四十二连接电极CO42连接，因而第六十一连接电极CO61和第六十二连接电极CO62使得第六栅电极Gate6、第九晶体管T9的第二极和第十一晶体管T11的第二极具有相同的电位(即像素驱动电路的第一节点N1)。
在示例性实施方式中，第六十三连接电极CO63的形状可以为“L”形状，第六十三连接电极CO63的第一端通过第三十三过孔V33与第十一有源层的第一区连接，第六十三连接电极CO63的第二端通过第九十四过孔V94与第四十一连接电极CO41的第二端连接。由于第四十一连接电极CO41的第一端通过过孔与高频信号线Hf连接，因而实现了将高频信号写入第十一晶体管T11的第一极。
在示例性实施方式中，第六十四连接电极CO64的形状可以为“L”形状，第六十四连接电极CO64的第一端通过第二十九过孔V29与第九有源层的第一区连接，第六十四连接电极CO64的第二端通过第八十一过孔V81与发光信号线EM连接，第六十四连接电极CO64的第一端与第二端之间的区域通过第九十九过孔V99与第四十五连接电极CO45连接，因而实现了将发光信号写入第九晶体管T9的第一极。
在示例性实施方式中，第三导电层还可以包括第七十一连接电极CO71和第七十二连接电极CO72。
在示例性实施方式中，第七十一连接电极CO71的形状可以为沿着第二方向Y延伸的条形状，第七十一连接电极CO71可以设置在第二电路单元Q2中，第七十一连接电极CO71的一端通过第一百零一过孔V101与第一低压连接线VSS-C1连接，第七十一连接电极CO71被配置为与后续形成的第一电源低压线连接。
在示例性实施方式中，第七十二连接电极CO72的形状可以为沿着第二方向Y延伸的条形状，第七十二连接电极CO72可以设置在第一电路单元Q1中，第七十二连接电极CO72的一端通过第一百零二过孔V102与第二低压连接线VSS-C2连接，第七十二连接电极CO72被配置为与后续形成的第二低压电源线连接。
(26)形成第四绝缘层和第一平坦层图案。在示例性实施方式中，形成第四绝缘层和第一平坦层图案可以包括：在形成前述图案的基底上，先涂覆 第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，随后沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第三导电层图案的第一平坦层以及设置在第一平坦层远离基底一侧的第四绝缘层，第四绝缘层和第一平坦层上设置有多个过孔，如图25所示。
在示例性实施方式中，多个过孔可以至少包括：第六十五过孔V65、第七十过孔V70、第七十一过孔V71和第七十二过孔V72。
在示例性实施方式中，第六十五过孔V65可以设置在每个电路单元中，第六十五过孔V65在基底上的正投影位于阳极连接块12在基底上的正投影的范围之内，第六十五过孔V65内的第四绝缘薄膜和第一平坦薄膜被去掉，暴露出阳极连接块12的表面，第六十五过孔V65被配置为使后续形成的阳极连接电极通过该过孔与阳极连接块12连接。
在示例性实施方式中，第七十过孔V70在基底上的正投影位于第七十一连接电极CO71在基底上的正投影的范围之内，第七十过孔V70内的第四绝缘薄膜和第一平坦薄膜被去掉，暴露出第七十一连接电极CO71的表面，第七十过孔V70被配置为使后续形成的第一低压电源线通过该过孔与第七十一连接电极CO71连接。
在示例性实施方式中，第七十一过孔V71在基底上的正投影位于第七十二连接电极CO72在基底上的正投影的范围之内，第七十一过孔V71内的第四绝缘薄膜和第一平坦薄膜被去掉，暴露出第七十二连接电极CO72的表面，第七十一过孔V71被配置为使后续形成的第二低压电源线通过该过孔与第七十二连接电极CO72连接。
在示例性实施方式中，第七十二过孔V72在基底上的正投影位于高压连接线VDD-C在基底上的正投影的范围之内，第七十二过孔V72内的第四绝缘薄膜、第一平坦薄膜被和第三绝缘层去掉，暴露出高压连接线VDD-C的表面，第七十二过孔V72被配置为使后续形成的高压电源线通过该过孔与高压连接线VDD-C连接。
(27)形成第四导电层图案。在示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第四绝缘层上的第四导电层图案， 如图26A和图26B所示，图26B为图26A中第四导电层的平面示意图。
在示例性实施方式中，第四导电层图案可以至少包括阳极连接电极13、高压电源线VDD、第一低压电源线VSS1和第二低压电源线VSS2。
在示例性实施方式中，阳极连接电极13的形状可以为矩形状，阳极连接电极13通过第六十五过孔V65与阳极连接块12连接，阳极连接电极13被配置为与发光二极管的第一极绑定连接。
在示例性实施方式中，高压电源线VDD的形状可以为沿着第二方向Y延伸的线形状，高压电源线VDD通过第七十二过孔V72与高压连接线VDD-C连接，实现了沿着第一方向X延伸的高压连接线VDD-C与沿着第二方向Y延伸的高压电源线VDD之间的连接，形成传输高压电源信号的网状连通结构。
在示例性实施方式中，第一低压电源线VSS1的形状可以为沿着第二方向Y延伸的线形状，第一低压电源线VSS1通过第七十过孔V70与第七十一连接电极CO71连接。由于第七十一连接电极CO71通过过孔与第一低压连接线VSS-C1连接，因而实现了沿着第一方向X延伸的第一低压连接线VSS-C1与沿着第二方向Y延伸的第一低压电源线VSS1之间的连接，形成传输第一低压电源信号的网状连通结构。
在示例性实施方式中，第二低压电源线VSS2的形状可以为沿着第二方向Y延伸的线形状，第二低压电源线VSS2通过第七十一过孔V71与第七十二连接电极CO72连接。由于第七十二连接电极CO72通过过孔与第二低压连接线VSS-C2连接，因而实现了沿着第一方向X延伸的第二低压连接线VSS-C2与沿着第二方向Y延伸的第二低压电源线VSS2之间的连接，形成传输第二低压电源信号的网状连通结构。
图26C为本公开示例性实施例一种电源走线的示意图，示意了多个电路单元中高压电源线和低压电源线的结构。如图26C所示，高压电源线VDD、第一低压电源线VSS1和第二低压电源线VSS2的形状可以为沿着第二方向Y延伸的线形状，且第一低压电源线VSS1和第二低压电源线VSS2设置在相邻的高压电源线VDD之间，多个阳极连接电极13可以设置在第一低压电源线VSS1和第二低压电源线VSS2之间。
在示例性实施方式中，第一低压电源线VSS1靠近第二低压电源线VSS2的一侧设置有第一焊盘块，第一焊盘块被配置为连接第一发光二极管的第二极。第二低压电源线VSS2靠近第一低压电源线VSS1的一侧设置有第二焊盘块，第二焊盘块被配置为连接第二发光二极管和第三发光二极管的第二极。
在示例性实施方式中，低压电源线可以包括第一低压电源线、第二低压电源线和第三低压电源线，三条低压电源线分别为第一发光二极管、第二发光二极管和第三发光二极管提供低压电源信号，以最大限度地降低功耗。
(28)形成第五绝缘层和第二平坦层图案。在示例性实施方式中，形成第五绝缘层和第二平坦层图案可以包括：在形成前述图案的基底上，先沉积第五绝缘薄膜，随后涂覆第二平坦薄膜，随后沉积第六绝缘薄膜，采用图案化工艺对第五绝缘薄膜、第二平坦薄膜和第六绝缘薄膜进行图案化，形成覆盖第四导电层图案的第五绝缘层、设置在第五绝缘层远离基底一侧的第二平坦层、设置在第二平坦层远离基底一侧的第六绝缘层，第五绝缘层、第二平坦层和第六绝缘层上设置有多个绑定孔，如图27所示。
在示例性实施方式中，多个绑定孔至少包括多个第一绑定孔K1和多个第二绑定孔K2，多个第一绑定孔K1和多个第二绑定孔K2均位于空白单元KB所在区域。
在示例性实施方式中，第一绑定孔K1的形状可以为矩形状，第一绑定孔K1在基底上的正投影位于阳极连接电极13在基底上的正投影的范围之内，第一绑定孔K1内的第六绝缘薄膜、第二平坦薄膜和第五绝缘薄膜被去掉，暴露出阳极连接电极13的表面，阳极连接电极13被第一绑定孔K1暴露的区域可以作为阳极焊盘，第一绑定孔K1被配置为使发光二极管的第一极通过该绑定孔与阳极连接电极13绑定连接。
在示例性实施方式中，第二绑定孔K2的形状可以为矩形状。第一电路单元Q1的第二绑定孔K2在基底上的正投影位于第一低压电源线VSS1在基底上的正投影的范围之内，第二绑定孔K2内的第六绝缘薄膜、第二平坦薄膜和第五绝缘薄膜被去掉，暴露出第一低压电源线VSS1的表面，第一低压电源线VSS1被第二绑定孔K2暴露的区域可以作为连接第一发光二极管的阴极焊盘，第二绑定孔K2被配置为使第一发光二极管的第二极通过该绑定 孔与第一低压电源线VSS1连接。第二电路单元Q2和第二电路单元Q3的第二绑定孔K2在基底上的正投影位于第二低压电源线VSS2在基底上的正投影的范围之内，第二绑定孔K2内的第六绝缘薄膜、第二平坦薄膜和第五绝缘薄膜被去掉，暴露出第二低压电源线VSS2的表面，第二低压电源线VSS2被第二绑定孔K2暴露的区域可以作为连接第二发光二极管和第二发光二极管的阴极焊盘，第二绑定孔K2被配置为使第二发光二极管和第三发光二极管的第二极通过该绑定孔分别与第二低压电源线VSS2连接。
至此，在基底上制备完成本示例性实施例的驱动电路层。
本公开示例性实施例所提供的显示基板，通过将第一电路单元中的第三晶体管的宽长比设置成大于第二电路单元和第三电路单元中的第三晶体管的宽长比，将第一电路单元中存储电容的电容值设置成大于第二电路单元和第三电路单元中储电容的电容值，不仅可以满足红色发光二极管所需的电流值，实现更多的灰阶，避免了现有结构亮度不满足需求或者不能实现更多灰阶等不良，而且可以有效减小第三晶体管栅极电压的跳变量，可以保证栅极电压的正确写入。
本公开通过采用并联结构的第一电容、第二电容和存储电容，在保证电容容量的前提下，最大限度地减小了第一电容、第二电容和存储电容的占用空间，有利于实现高分辨率显示。本公开通过形成网络连通结构的高频信号线，可以最大限度地降低了高频信号线的电阻，减小了高频信号的压降，有效提升了显示基板中电源电压的均一性，有效提升了信号面内的均一性。本公开通过形成网络连通结构的高压电源线和低压电源线，可以最大限度地降低了电源传输线的电阻，减小了电源电压的压降，有效提升了显示基板中电源电压的均一性，有效提升了信号面内的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
本公开通过采用增加第一低压电源线和第一低压电源线，可以有效减小功耗，实现功耗最小化。研究表明，驱动发光二极管发光时，R芯片、G芯片和B芯片两端的电压有一定差异。例如，出射亮度相同时，R芯片两端所需的电压较B芯片两端所需的电压低2V左右。如果按照B芯片满足跨压需求设计低压电源电压，则R芯片跨压会超出跨压需求，因而会增加功耗。本 公开通过将R芯片和G/B芯片的低压电源独立设计，利用第一低压电源线为R芯片提供第一低压电源信号，第二低压电源线为G/B芯片提供第二低压电源信号，分别控制不同芯片的低压电源电压，在保证像素驱动电路正常驱动情况下，可以有效降低功耗，实现功耗最小化。试验验证表明，相比于显示基板采用一条低压电源线的结构，本公开通过采用两条低压电源线，设置第一低压电源线的低压电源电压为6.6V，第二低压电源线的低压电源电压为4.6V，整体功耗可以减小12％以上。
图28为本公开示例性实施例又一种显示基板的结构示意图，示意了三个电路单元的结构，电路单元包括图16所示的像素驱动电路。如图28所示，多个电路单元可以至少包括沿着第一方向X依次设置的第一电路单元Q1、第二电路单元Q2和第三电路单元Q3，第一电路单元Q1中的第一像素驱动电路被配置为与第一发光二极管连接，第二电路单元Q2中的第二像素驱动电路被配置为与第二发光二极管连接，第三电路单元Q3中的第三像素驱动电路被配置为与第三发光二极管连接，第一发光二极管可以为红色发光二极管，第二发光二极管可以为绿色发光二极管，第三发光二极管可以为蓝色发光二极管。
在示例性实施方式中，第一驱动晶体管DTFT1的宽长比可以大于第二驱动晶体管DTFT2和第三驱动晶体管DTFT3的宽长比，第一存储电容Cs1的电容值与第二存储电容Cs2和第三存储电容Cs3的电容值可以基本上相同。
在示例性实施方式中，至少一个电路单元可以包括沿着第一方向X延伸的高频连接线Hf-C和沿着第二方向Y延伸的高频信号线Hf，高频信号线Hf可以通过过孔与高频连接线Hf-C连接，形成传输高频信号的网状连通结构。
在示例性实施方式中，至少一个电路单元可以包括沿着第一方向X延伸的高压连接线VDD-C和沿着第二方向Y延伸的高压电源线VDD，高压连接线VDD与相应的像素驱动电路连接，高压电源线VDD可以通过过孔与高压连接线VDD-C连接，形成传输高压电源信号的网状连通结构。
在示例性实施方式中，至少一个电路单元可以包括沿着第一方向X延伸的低压连接线VSS-C和沿着第二方向Y延伸的低压电源线VSS，低压电源 线VSS可以通过过孔与低压连接线VSS-C连接，形成传输低压电源信号的网状连通结构。
在示例性实施方式中，本实施例驱动晶体管的结构与图17所示驱动晶体管的结构可以基本上相同，本实施例存储电容的结构与图17所示存储电容的结构可以基本上相同，所不同的是，第一存储电容Cs1、第二存储电容Cs2和第三存储电容Cs3的面积可以基本上相同。
在示例性实施方式中，本实施例驱动电路层的制备过程可以包括如下操作。
(31)形成第一导电层图案。每个电路单元的第一导电层图案可以至少包括：第一极板CF1、第二极板CF2、第三极板CF3和第三底栅电极Gate3-B，如图29所示。
在示例性实施方式中，第一极板CF1、第二极板CF2和第三极板CF3的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板CF1和第二极板CF2可以设置在电路单元第二方向Y的反方向的一侧，第三底栅电极Gate3-B可以设置在电路单元第二方向Y的一侧，第三极板CF3可以位于第一极板CF1与第三底栅电极Gate3-B之间。与图20所示结构不同的是，第一极板CF1设置在第二极板CF2第一方向X的一侧。
在示例性实施方式中，三个电路单元中第三极板CF3位置和形状可以基本上相同，三个电路单元中第三极板CF3的第一长度M1和第二长度M2可以基本上相同，三个电路单元中第三极板CF3的面积可以基本上相同。
在示例性实施方式中，第三底栅电极Gate3-B的位置、形状和尺寸可以与图20所示结构基本上相同。
(32)形成半导体层图案。每个电路单元的半导体层图案可以至少包括第一晶体管T1的第一有源层AT1至第十一晶体管T11的第十一有源层AT11，如图30所示。
在示例性实施方式中，第一有源层AT1至第十一有源层AT11的位置和形状可以与图21A和图21B所示结构基本上相同，所不同的是，第十有源层AT10可以位于第二极板CF2第二方向Y的一侧，第八有源层AT8可以位于 第十有源层AT10第二方向Y的一侧。
(33)形成第二导电层图案。每个电路单元的第二导电层图案至少包括：第四极板CF4、第五极板CF5、第六极板CF6、第一扫描信号线S1、第二扫描信号线S2、发光信号线EM、第二控制线CT2、初始信号线Vint、高频连接线Hf-C、高压连接线VDD-C、低压连接线VSS-C、多个栅电极和多个连接电极，如图31所示。
在示例性实施方式中，第四极板CF4、第五极板CF5和第六极板CF6的位置可以与图22A和图22B所示结构基本上相同，所不同的是，第四极板CF4设置在第五极板CF5第一方向X的一侧，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第六极板CF6的位置、形状和尺寸可以基本上相同。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、发光信号线EM、第二控制线CT2、初始信号线Vint、高频连接线Hf-C、高压连接线VDD-C和低压连接线VSS-C的位置和形状可以与图22A和图22B所示结构基本上相同，所不同的是，本实施例只设置有一条低压连接线VSS-C，第二扫描信号线S2复用为第一控制线，控制第八晶体管T8的导通和断开。
在示例性实施方式中，每个电路单元的多个栅电极可以至少包括第一栅电极Gate1、第二栅电极Gate2、第三顶栅电极Gate3-T、第四栅电极Gate4、第五栅电极Gate5、第六栅电极Gate6、第七栅电极Gate7、第八栅电极Gate8、第九栅电极Gate9、第十栅电极Gate10和第十一栅电极Gate11。
在示例性实施方式中，每个电路单元的多个连接电极至少包括第四十一连接电极CO41、第四十二连接电极CO42和第四十五连接电极CO45，第四十一连接电极CO41、第四十二连接电极CO42和第四十一连接电极CO41的位置和形状可以与图22A和图22B所示结构基本上相同。
(34)形成第三绝缘层图案。每个电路单元中第三绝缘层上设置有多个过孔，如图32所示。
在示例性实施方式中，多个过孔的位置和作用可以与图23所示结构基本上相同，所不同的是，由于没有设置第四十三连接电极和第四十四连接电极，且第九栅电极Gate9和第十一栅电极Gate11的形状不同，因而相应过孔的位 置有所不同，这里不再赘述。
(35)形成第三导电层图案。第三导电层图案至少包括：数据信号线DataI、高频信号线Hf、第七极板CF7、第八极板CF8、第九极板CF9、阳极连接块12和多个连接电极，如图33所示。
在示例性实施方式中，数据信号线DataI、高频信号线Hf、第七极板CF7、第八极板CF8、第九极板CF9的位置、形状和连接结构可以与图24A和图24B所示结构基本上相同，所不同的是，第七极板CF7设置在第八极板CF8第一方向X的一侧，第一电路单元Q1、第二电路单元Q2和第三电路单元Q3中第九极板CF9的尺寸和面积可以基本上相同。
在示例性实施方式中，多个连接电极可以至少包括第五十一连接电极CO51、第五十二连接电极CO52、第五十三连接电极CO53、第五十四连接电极CO54、第五十五连接电极CO55、第五十六连接电极CO56、第五十七连接电极CO57、第五十八连接电极CO58、第五十九连接电极CO59、第六十连接电极CO60、第六十一连接电极CO61、第六十二连接电极CO62、第六十三连接电极CO63和第六十四连接电极CO64，上述连接电极的位置、形状和连接结构可以与图24A和图24B所示结构基本上相同，所不同的是，第五十一连接电极CO51还通过过孔与第七极板CF7连接，第五十八连接电极CO58与第十一栅电极Gate11连接，第五十九连接电极CO59与第九栅电极Gate9连接等等，这里不再赘述。
在示例性实施方式中，每个电路单元的阳极连接块12与第五十二连接电极CO52为相互连接的一体结构。
在示例性实施方式中，第三导电层还可以包括第七十一连接电极CO71。第七十一连接电极CO71的形状可以为沿着第二方向Y延伸的条形状，第七十一连接电极CO71可以设置在第二电路单元Q2中，第七十一连接电极CO71的一端通过过孔与低压连接线VSS-C连接，第七十一连接电极CO71被配置为与后续形成的电源低压线连接。
(36)形成第四绝缘层和第一平坦层图案。每个电路单元中第四绝缘层和第一平坦层上设置有多个过孔，如图34所示。
在示例性实施方式中，多个过孔可以至少包括：第六十五过孔V65、第 七十过孔V70和第七十二过孔V72，多个过孔的位置和作用可以与图25所示结构基本上相同。
(37)形成第四导电层图案。第四导电层图案可以至少包括阳极连接电极13、高压电源线VDD和低压电源线VSS，如图35A和图35B所示，图35B为本公开示例性实施例另一种电源走线的示意图，示意了多个电路单元中高压电源线和低压电源线的结构。
在示例性实施方式中，高压电源线VDD和低压电源线VSS的形状可以为沿着第二方向Y延伸的线形状，沿着第一方向X延伸的高压连接线VDD-C与沿着第二方向Y延伸的高压电源线VDD通过过孔连接，形成传输高压电源信号的网状连通结构，沿着第一方向X延伸的低压连接线VSS-C与沿着第二方向Y延伸的低压电源线VSS通过过孔的连接，形成传输低压电源信号的网状连通结构。
高压电源线VDD和低压电源线VSS上分别设置有高压开口和低压开口，高压开口中可以设置有一个“T”形的低压电源线和三个阳极连接电极13，低压开口中可以设置有两个阳极连接电极13，低压电源线被配置为连接发光二极管的第二极。低压电源线VSS靠近高压电源线VDD的一侧设置有焊盘块，焊盘块被配置为连接发光二极管的第二极。
在示例性实施方式中，阳极连接电极13的位置、形状和连接结构可以与图26A和图26B所示所示结构基本上相同，这里不再赘述。
(38)形成第五绝缘层和第二平坦层图案。每个电路单元中第五绝缘层、第二平坦层和第六绝缘层上设置有第一绑定孔K1和第二绑定孔K2，如图36所示。
在示例性实施方式中，绑定孔的位置和作用可以与图27所示结构基本上相同。
至此，在基底上制备完成本示例性实施例的驱动电路层。
本公开示例性实施例所提供的显示基板，通过将第一电路单元中的第三晶体管的宽长比设置成大于第二电路单元和第三电路单元中的第三晶体管的宽长比，可以满足红色发光二极管所需的电流值，实现更多的灰阶，避免了 现有结构亮度不满足需求或者不能实现更多灰阶等不良。
本公开通过采用并联结构的第一电容、第二电容和存储电容，在保证电容容量的前提下，最大限度地减小了第一电容、第二电容和存储电容的占用空间，有利于实现高分辨率显示。本公开通过形成网络连通结构的高频信号线，可以最大限度地降低了高频信号线的电阻，减小了高频信号的压降，有效提升了显示基板中电源电压的均一性，有效提升了信号面内的均一性。本公开通过形成网络连通结构的高压电源线和低压电源线，可以最大限度地降低了电源传输线的电阻，减小了电源电压的压降，有效提升了显示基板中电源电压的均一性，有效提升了信号面内的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，显示基板制备过程需要进行多个检测，其中一个重要的检测是利用检测电路CT进行画面检测，也称CT检测。CT检测是通过对显示基板输入检测信号，使发光二极管发光，通过缺陷检测装置检查各个发光二极管是否良好，以确认显示基板是否存在缺陷。
图37为一种显示基板进行CT检测的示意图。如图37所示，显示基板可以包括显示区域AA和位于显示区域AA一侧的绑定区域FA，显示区域AA可以包括多个电路单元和多个发光单元，电路单元可以至少包括像素驱动电路，发光单元可以至少包括发光二极管，发光二极管可以与对应电路单元的像素驱动电路连接。显示区域AA还可以包括多条数据信号线DataI，每条数据信号线DataI与一个单元列中的多个像素驱动电路连接。
在示例性实施方式中，绑定区域FA可以包括检测电路，检测电路可以至少包括多个检测单元210、至少一条控制线220和至少一条检测线230。多个检测单元210可以沿着第一方向X以设定的间隔依次设置，多个检测单元210的位置可以与显示区域AA中多条数据信号线DataI的位置一一对应。每个检测单元210可以包括控制端、输入端和输出端，控制线220的一端与绑定引脚区的引脚对应连接，控制线220的另一端可以与多个检测单元210的控制端对应连接，控制线220被配置为控制多个检测单元210的导通或者断开。检测线230的一端与绑定引脚区的引脚对应连接，检测线230的另一端可以与多个检测单元210的输入端对应连接，多个检测单元210的输出端可 以与显示区域AA的多条数据信号线DataI对应连接，检测单元210被配置为在控制线220的控制下，将检测线230输出的信号输出给显示区域AA的数据信号线DataI，实现显示基板的CT检测。
图38为本公开示例性实施例检测电路的结构示意图。如图38所示，检测电路可以至少包括多个检测单元210、控制线220和检测线230，多个检测单元210的输出端可以通过多条传输线240与显示区域的多条数据信号线DataI对应连接，多条传输线240的形状可以为向着显示区域延伸的折线状，相邻传输线240之间的间距可以基本上相同。
在示例性实施方式中，至少一条传输线240与相邻的传输线240之间可以设置有屏蔽线250，屏蔽线250的形状可以与传输线240的形状基本上相同。
在示例性实施方式中，传输线240和屏蔽线250可以同层设置，且通过同一次图案化工艺同步形成。
在示例性实施方式中，屏蔽线250靠近传输线240一侧的边缘与传输线240靠近屏蔽线250一侧的边缘之间的距离可以约为10μm至20μm。例如，屏蔽线250靠近传输线240一侧的边缘与传输线240靠近屏蔽线250一侧的边缘之间的距离可以约为15μm。
在示例性实施方式中，屏蔽线250可以与恒压信号线或者接地信号线连接，屏蔽线250被配置为降低因耦合电容导致传输线240的数据电压跳变。
在示例性实施方式中，恒压信号线可以是高压电源线，或者可以是低压电源线，或者可以是初始信号线。
图39为本公开示例性实施例一种屏蔽线与恒压信号线连接的示意图。如图39所示，恒压信号线可以是初始信号线Vint，屏蔽线250和初始信号线Vint可以设置在不同的导电层中，屏蔽线250可以通过过孔K0与初始信号线Vint连接。
在示例性实施方式中，初始信号线Vint可以通过多个过孔K0分别与多条屏蔽线250连接，为多条屏蔽线250提供恒压信号。
在示例性实施方式中，初始信号线Vint可以为多条，以提高连接可靠性。
本公开通过在检测电路的传输线之间设置屏蔽线，可以有效屏蔽相邻传输线之间的耦合电容，减小数据电压跳变。研究表明，检测电路在进行CT检测时，由于相邻传输线之间存在耦合电容，耦合电容会导致数据电压跳变，造成测试误差。本公开通过在检测电路的传输线之间设置屏蔽线，且屏蔽线与恒压信号线连接，恒压的屏蔽线可以有效屏蔽相邻传输线之间的耦合电容，因而有效减小数据电压跳变，不仅可以提高测试数据的准确性，而且不需要增加额外信号，不会对数据电压产生影响。
需要说明的是，本公开示例性实施例所示结构及其制备过程仅仅是一种示例性说明，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开实施例在此不做具体的限定。
本公开示例性实施例所提供的显示基板可以适用于任何LED驱动像素电路，包括P型PAM、P型PAM+PWM、N型PAM、N型PAM+PWM、以及LTPO型PAM及PAM+PWM电路等。
本公开示例性实施例还提供了一种显示基板的制备方法，以制备前述的显示基板。在示例性实施方式中，所述制备方法可以包括：
在基底上形成驱动电路层，所述驱动电路层包括多个电路单元，所述多个电路单元至少包括第一电路单元、第二电路单元和第三电路单元，所述第一电路单元包括第一像素驱动电路，所述第一像素驱动电路至少包括第一驱动晶体管，所述第二电路单元包括第二像素驱动电路，所述第二像素驱动电路至少包括第二驱动晶体管，所述第三电路单元包括第三像素驱动电路，所述第三像素驱动电路至少包括第三驱动晶体管；所述第一驱动晶体管的沟道宽度大于所述第二驱动晶体管或者所述第三驱动晶体管的沟道宽度，所述第一驱动晶体管的沟道长度与所述第二驱动晶体管或者所述第三驱动晶体管的沟道长度相同。
本公开示例性实施例还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到 新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (20)

  1. 一种显示基板，包括设置在基底上的驱动电路层，所述驱动电路层包括多个电路单元，所述多个电路单元至少包括第一电路单元、第二电路单元和第三电路单元，所述第一电路单元包括第一像素驱动电路，所述第一像素驱动电路至少包括第一驱动晶体管，所述第二电路单元包括第二像素驱动电路，所述第二像素驱动电路至少包括第二驱动晶体管，所述第三电路单元包括第三像素驱动电路，所述第三像素驱动电路至少包括第三驱动晶体管；所述第一驱动晶体管的沟道宽度大于所述第二驱动晶体管或者所述第三驱动晶体管的沟道宽度，所述第一驱动晶体管的沟道长度与所述第二驱动晶体管或者所述第三驱动晶体管的沟道长度相同。
  2. 根据权利要求1所述的显示基板，其中，所述第一驱动晶体管的沟道宽度与所述第二驱动晶体管或者所述第三驱动晶体管的沟道宽度的比值为2至6。
  3. 根据权利要求1所述的显示基板，其中，所述第二驱动晶体管的沟道宽度与所述第三驱动晶体管的沟道宽度相同，所述第二驱动晶体管的沟道长度与所述第三驱动晶体管的沟道长度相同。
  4. 根据权利要求1所述的显示基板，其中，所述第一像素驱动电路还包括第一存储电容，所述第二像素驱动电路还包括第二存储电容，所述第三像素驱动电路还包括第三存储电容；所述第一存储电容的电容值大于或等于所述第二存储电容或者所述第三存储电容的电容值。
  5. 根据权利要求4所述的显示基板，其中，所述第一存储电容在所述基底上正投影的面积大于所述第二存储电容或者所述第三存储电容在所述基底上正投影的面积。
  6. 根据权利要求5所述的显示基板，其中，所述第一存储电容在所述基底上正投影的第一长度与所述第二存储电容或者所述第三存储电容在所述基底上正投影的第一长度相同，所述第一存储电容在所述基底上正投影的第二长度大于或等于所述第二存储电容或者所述第三存储电容在所述基底上正投影的第二长度，所述第一长度为第一方向的尺寸，所述第二长度为第二方向尺寸，所述第一方向与所述第二方向交叉。
  7. 根据权利要求6所述的显示基板，其中，所述第一存储电容在所述基底上正投影的第二长度与所述第二存储电容或者所述第三存储电容在所述基底上正投影的第二长度的比值为1至2。
  8. 根据权利要求6所述的显示基板，其中，所述第二存储电容在所述基底上正投影的第一长度与所述第三存储电容在所述基底上正投影的第一长度相同，所述第二存储电容在所述基底上正投影的第二长度与所述第三存储电容在所述基底上正投影的第二长度相同。
  9. 根据权利要求1所述的显示基板，其中，所述显示基板还包括设置在所述驱动电路层远离所述基底一侧的发光结构层，所述发光结构层包括多个发光单元，所述多个发光二极管至少包括出射红色光线的红色发光二极管、出射绿色光线的绿色发光二极管和出射蓝色光线的蓝色发光二极管，所述红色发光二极管与所述第一像素驱动电路连接，所述绿色发光二极管与所述第二像素驱动电路连接，所述蓝色发光二极管与所述第三像素驱动电路连接。
  10. 根据权利要求1至9任一项所述的显示基板，其中，至少一个电路单元包括沿着第一方向延伸的高压连接线和沿着第二方向延伸的高压电源线，所述高压电源线通过过孔与所述高压连接线连接，形成传输高压电源信号的网状连通结构，所述第一方向与所述第二方向交叉。
  11. 根据权利要求1至9任一项所述的显示基板，其中，至少一个电路单元包括沿着第一方向延伸的低压连接线和沿着第二方向延伸的低压电源线，所述低压电源线通过过孔与所述低压连接线连接，形成传输低压电源信号的网状连通结构，所述第一方向与所述第二方向交叉。
  12. 根据权利要求11所述的显示基板，其中，所述低压电源线包括第一低压电源线和第二低压电源线，所述第一低压电源线与红色发光二极管连接，所述第二低压电源线与绿色发光二极管和蓝色发光二极管连接。
  13. 根据权利要求12所述的显示基板，其中，至少一个电路单元包括沿着所述第一方向延伸的第一低压连接线，所述第一低压电源线通过过孔与所述第一低压连接线连接，形成传输第一低压电源信号的网状连通结构。
  14. 根据权利要求12所述的显示基板，其中，至少一个电路单元包括沿着所述第一方向延伸的第二低压连接线，所述第二低压电源线通过过孔与所 述第二低压连接线连接，形成传输第二低压电源信号的网状连通结构。
  15. 根据权利要求1至9任一项所述的显示基板，其中，至少一个电路单元包括沿着第一方向延伸的高频连接线和沿着第二方向延伸的高频信号线，所述高频信号线通过过孔与所述高频连接线连接，形成传输高频信号的网状连通结构，所述第一方向与所述第二方向交叉。
  16. 根据权利要求1至9任一项所述的显示基板，其中，所述显示基板还包括测试电路和多条数据信号线，所述数据信号线与所述像素驱动电路连接，所述检测电路至少包括多个检测单元和多条传输线，所述多个检测单元通过所述多条传输线与所述多条数据信号线对应连接，至少一条传输线与相邻的传输线之间设置有屏蔽线，所述屏蔽线与恒压信号线或者接地信号线连接。
  17. 根据权利要求16所述的显示基板，其中，至少一条传输线与相邻的屏蔽线之间的距离为10μm至20μm。
  18. 根据权利要求16所述的显示基板，其中，所述传输线和所述屏蔽线同层设置。
  19. 一种显示装置，包括如权利要求1至18中任一项所述的显示基板。
  20. 一种显示基板的制备方法，包括：
    在基底上形成驱动电路层，所述驱动电路层包括多个电路单元，所述多个电路单元至少包括第一电路单元、第二电路单元和第三电路单元，所述第一电路单元包括第一像素驱动电路，所述第一像素驱动电路至少包括第一驱动晶体管，所述第二电路单元包括第二像素驱动电路，所述第二像素驱动电路至少包括第二驱动晶体管，所述第三电路单元包括第三像素驱动电路，所述第三像素驱动电路至少包括第三驱动晶体管；所述第一驱动晶体管的沟道宽度大于所述第二驱动晶体管或者所述第三驱动晶体管的沟道宽度，所述第一驱动晶体管的沟道长度与所述第二驱动晶体管或者所述第三驱动晶体管的沟道长度相同。
PCT/CN2022/141082 2022-12-22 2022-12-22 显示基板及其制备方法、显示装置 Ceased WO2024130652A1 (zh)

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US18/555,254 US20250081609A1 (en) 2022-12-22 2022-12-22 Display Substrate, Preparation Method Therefor, and Display Apparatus
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