WO2024148984A1 - 传输数据的方法、装置、设备、系统及存储介质 - Google Patents

传输数据的方法、装置、设备、系统及存储介质 Download PDF

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Publication number
WO2024148984A1
WO2024148984A1 PCT/CN2023/136552 CN2023136552W WO2024148984A1 WO 2024148984 A1 WO2024148984 A1 WO 2024148984A1 CN 2023136552 W CN2023136552 W CN 2023136552W WO 2024148984 A1 WO2024148984 A1 WO 2024148984A1
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Prior art keywords
data
fec code
encoding
padding
code
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PCT/CN2023/136552
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English (en)
French (fr)
Inventor
何向
王心远
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to EP23915742.3A priority Critical patent/EP4633070A4/en
Publication of WO2024148984A1 publication Critical patent/WO2024148984A1/zh
Priority to US19/266,843 priority patent/US20260031931A1/en
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
    • H04L1/0007—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length
    • H04L1/0008—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length by supplementing frame payload, e.g. with padding bits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H04L1/0042—Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0065—Serial concatenated codes

Definitions

  • the present application relates to the field of communications, and in particular to a method, device, equipment, system and storage medium for transmitting data.
  • the transmission rate of Ethernet on the physical link is usually selected as an integer multiple of the crystal oscillator.
  • additional padding data is usually required.
  • the present application proposes a method, apparatus, device, system and storage medium for transmitting data, which are used to improve the reliability and efficiency of transmitting fill data.
  • a method for transmitting data comprising: obtaining first data, the first data being obtained by encoding first reference data using a first forward error correction (FEC) code; encoding the first data according to a second FEC code to obtain a first encoding result; obtaining second data, the second data comprising the first encoding result and padding data for adjusting a frequency, the padding data carrying relevant information for data transmission, and the padding data being protected data; and transmitting the second data.
  • FEC forward error correction
  • the method improves the reliability and efficiency of transmitting the padding data by protecting the padding data, thereby enabling the relevant information of the data transmission carried by the padding data to be transmitted more reliably.
  • the first FEC code and the second FEC code include but are not limited to any one of Reed-Solomon (RS) code, Bose-Chaudhuri-Hocquenghem (BCH) code, Fire code, extended BCH code, Hamming code, extended Hamming code, turbo code, turbo product code (TPC), staircase code and low density parity check (LDPC) code.
  • RS Reed-Solomon
  • BCH Bose-Chaudhuri-Hocquenghem
  • Fire code extended BCH code
  • Hamming code extended Hamming code
  • turbo code turbo product code
  • TPC turbo product code
  • LDPC low density parity check
  • the protection process includes adding CRC
  • the padding data is the data for adding the CRC protection. If CRC protection is added to the padding data, it can be used to detect whether there is an error in the padding data within the CRC protection range after transmission. In order to add the CRC function, the length of the padding data needs to meet the length that can be inserted into the CRC.
  • the protection processing includes encoding using a third FEC code, and the padding data is data encoded using the third FEC code. Since the FEC code can not only detect errors but also correct bit errors, the packet loss rate is reduced. By encoding the padding data using the third FEC code, the reliability of the padding data can be further improved after being calculated by the third FEC code.
  • the protection processing includes adding a cyclic redundancy check (CRC) and encoding with a third FEC code
  • the padding data is data that adds the CRC protection and is encoded with the third FEC code.
  • CRC cyclic redundancy check
  • This protection method can be applied in scenarios where high reliability requirements are required for the relevant information of the data carried.
  • the third FEC code is the same as the second FEC code.
  • the encoder and decoder of the implemented second FEC code are reused as much as possible.
  • the length of the padding data is an integer multiple of the length of the second FEC code, thereby facilitating the fixing of the boundary of the second FEC.
  • obtaining the second data includes: inserting padding data for adjusting the frequency point into the first encoding result according to a reference density to obtain the second data, wherein the reference density is determined based on an overhead ratio of the first FEC code and the second FEC code and a frequency of a crystal oscillator used when encoding the first data according to the second FEC code.
  • the method further includes: acquiring at least one third data, wherein the third data is obtained by encoding the second reference data using a fourth FEC code; for any third data among the at least one third data, encoding the any third data according to a fifth FEC code to obtain a second encoding result; acquiring fourth data, wherein the fourth data includes the second encoding result and the padding data; and transmitting the fourth data.
  • both the fourth data and the second data include padding data
  • a method for transmitting data comprising: receiving second data, the second data comprising a first coding result and filling data for adjusting a frequency, the filling data carrying relevant information for data transmission, and the filling data being protected data, the first coding result being obtained by encoding first data based on a second FEC code, the first data being obtained by encoding first reference data using a first FEC code; obtaining the first coding result and the filling data from the second data; decoding the first coding result according to the second FEC code to obtain the first data; and obtaining relevant information for the data transmission based on the filling data.
  • the protection processing includes adding CRC
  • the padding data is data for adding the CRC protection
  • obtaining the relevant information of the data transmission based on the padding data includes: performing the CRC check on the padding data, and obtaining the relevant information of the data transmission after the CRC check passes.
  • the protection processing includes encoding using a third FEC code, and the padding data is data encoded using the third FEC code; obtaining relevant information of the data transmission based on the padding data includes: decoding the padding data using the third FEC code, and obtaining relevant information of the data transmission based on the decoding result.
  • the protection processing includes adding CRC and encoding with a third FEC code
  • the padding data is data to which the CRC protection is added and encoded with the third FEC code
  • obtaining relevant information of the data transmission based on the padding data includes: decoding the padding data with a third FEC code, performing the CRC check on the decoding result, and obtaining relevant information of the data transmission after the CRC check passes.
  • the third FEC code is the same as the second FEC code.
  • the length of the padding data is an integer multiple of the length of the second FEC code.
  • the method also includes: receiving at least one fourth data, the fourth data including a second encoding result and padding data, the second encoding result being obtained by encoding third data based on a fifth FEC code, and the third data being obtained by encoding second reference data using the fourth FEC code; obtaining the second encoding result and the padding data from each fourth data; decoding the second encoding result according to the fifth FEC code to obtain the third data; and obtaining relevant information of the data transmission based on the padding data, including: comparing the padding data obtained from each fourth data with the padding data obtained from the second data, and when it is determined according to the comparison result that the number of identical padding data reaches a threshold, the second module obtaining relevant information of the data transmission based on the padding data.
  • comparing the padding data obtained from each of the fourth data with the padding data obtained from the second data includes: segmenting the padding data obtained from each of the fourth data and the padding data obtained from the second data, respectively, and comparing the segmented data blocks.
  • the padding data comparison process is implemented by comparing data blocks, thereby improving comparison efficiency.
  • a device for transmitting data comprising: a first acquisition module, used to acquire first data, wherein the first data is obtained by encoding first reference data using a first FEC code; an encoding module, used to encode the first data according to a second FEC code to obtain a first encoding result; a second acquisition module, used to acquire second data, wherein the second data includes the first encoding result and padding data for adjusting the frequency, the padding data carries relevant information for data transmission, and the padding data is data that has been protected; and a transmission module, used to transmit the second data.
  • the protection process includes adding a CRC
  • the padding data is data for adding the CRC protection.
  • the protection processing includes encoding using a third FEC code, and the padding data is data encoded using the third FEC code.
  • the protection processing includes adding CRC and encoding with a third FEC code, and the padding data is data to which the CRC protection is added and encoded with the third FEC code.
  • the third FEC code is the same as the second FEC code.
  • the length of the padding data is an integer multiple of the length of the second FEC code.
  • the second acquisition module is used to insert padding data for adjusting the frequency point into the first encoding result according to a reference density to obtain the second data, and the reference density is determined based on the overhead ratio of the first FEC code and the second FEC code and the frequency of the crystal oscillator used when encoding the first data according to the second FEC code.
  • the first acquisition module is further used to acquire at least one third data, where the third data is obtained by encoding the second reference data using the fourth FEC code; the encoding module is further used to encode any third data among the at least one third data according to the fifth FEC code to obtain a second encoding result; the second acquisition module is further used to acquire fourth data, where the fourth data includes the second encoding result and the padding data; and the transmission module is further used to transmit the fourth data.
  • a device for transmitting data comprising: a receiving module, used to receive second data, the second data comprising a first coding result and padding data for adjusting a frequency, the padding data carrying relevant information for data transmission, and the padding data being protected data, the first coding result being obtained by encoding first data based on a second FEC code, the first data being obtained by encoding first reference data using a first FEC code; a first acquisition module, used to obtain the first coding result and the padding data from the second data; a decoding module, used to decode the first coding result according to the second FEC code to obtain the first data; and a second acquisition module, used to obtain relevant information for the data transmission based on the padding data.
  • the protection processing includes adding CRC
  • the filling data is data for adding the CRC protection
  • the second acquisition module is used to perform the CRC check on the filling data, and after the CRC check passes, obtain relevant information of the data transmission.
  • the protection processing includes encoding using a third FEC code, and the padding data is data encoded using the third FEC code; the second acquisition module is used to decode the padding data using the third FEC code, and obtain relevant information of the data transmission based on the decoding result.
  • the protection processing includes adding CRC and encoding with a third FEC code, and the padding data is data to which the CRC protection is added and encoded with the third FEC code; the second acquisition module is used to decode the padding data with the third FEC code, perform the CRC check on the decoding result, and obtain relevant information of the data transmission after the CRC check passes.
  • the third FEC code is the same as the second FEC code.
  • the length of the padding data is an integer multiple of the length of the second FEC code.
  • the receiving module is also used to receive at least one fourth data, the fourth data including a second encoding result and padding data, the second encoding result is obtained by encoding the third data based on the fifth FEC code, and the third data is obtained by encoding the second reference data using the fourth FEC code;
  • the first acquisition module is also used to obtain the second encoding result and the padding data from each fourth data;
  • the decoding module is also used to decode the second encoding result according to the fifth FEC code to obtain the third data;
  • the second acquisition module is used to compare the padding data obtained from each fourth data with the padding data obtained from the second data, and when it is determined according to the comparison result that the number of identical padding data reaches a threshold, obtain the relevant information of the data transmission based on the padding data.
  • the second acquisition module is used to segment the filling data obtained from the fourth data and the filling data obtained from the second data, respectively, and compare the data blocks obtained by segmentation.
  • a network device comprising: a processor, the processor being coupled to a memory, the memory storing at least one program instruction or code, the at least one program instruction or code being loaded and executed by the processor so that the network device implements any of the methods described in the first aspect or the second aspect above.
  • a data transmission system comprising a first module and a second module, the first module is used to execute any method described in the first aspect, and the second module is used to execute any method described in the second aspect.
  • a computer-readable storage medium stores at least one program instruction or code, and when the program instruction or code is loaded and executed by a processor, the computer implements any method described in the first aspect or the second aspect.
  • a chip comprising a processor, wherein the processor is used to implement the method described in any one of the first aspect or the second aspect.
  • a communication device which includes the chip described in the eighth aspect.
  • a computer program comprising a computer program or code, which, when executed by a computer, enables the The computer executes any of the methods described in the first aspect or the second aspect.
  • another communication device comprising: a transceiver, a memory and a processor.
  • the transceiver, the memory and the processor communicate with each other through an internal connection path, the memory is used to store instructions, the processor is used to execute the instructions stored in the memory to control the transceiver to receive signals and control the transceiver to send signals, and when the processor executes the instructions stored in the memory, the processor executes the method in the first aspect or any possible implementation of the first aspect, or executes the method in the second aspect or any possible implementation of the second aspect.
  • the number of the processors is one or more, and the number of the memories is one or more.
  • the memory may be integrated with the processor, or the memory may be provided separately from the processor.
  • the memory can be a non-transitory memory, such as a read-only memory (ROM), which can be integrated with the processor on the same chip or can be separately set on different chips.
  • ROM read-only memory
  • the embodiments of the present application do not limit the type of memory and the setting method of the memory and the processor.
  • a chip comprising a processor for calling and executing instructions stored in a memory from the memory, so that a communication device equipped with the chip executes the methods in the above aspects.
  • another chip comprising: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected via an internal connection path, and the processor is used to execute the code in the memory, and when the code is executed, the processor is used to execute the methods in the above aspects.
  • FIG1 is a schematic diagram of a cascade coding process provided by an embodiment of the present application.
  • FIG2 is a schematic diagram of an implementation scenario provided by an embodiment of the present application.
  • FIG3 is an interactive diagram of a method for transmitting data provided by an embodiment of the present application.
  • FIG4 is a schematic diagram of inserting filling data provided by an embodiment of the present application.
  • FIG5 is a schematic diagram of a structure of filling data provided in an embodiment of the present application.
  • FIG6 is a schematic diagram of a structure of filling data provided in an embodiment of the present application.
  • FIG7 is a schematic diagram of the structure of a device for transmitting data provided in an embodiment of the present application.
  • FIG8 is a schematic diagram of the structure of a device for transmitting data provided in an embodiment of the present application.
  • FIG9 is a schematic diagram of the structure of a communication device provided in an embodiment of the present application.
  • FIG10 is a schematic diagram of the structure of a communication device provided in an embodiment of the present application.
  • FIG. 11 is a schematic diagram of the structure of a communication device provided in an embodiment of the present application.
  • FEC forward error correction
  • RS Reed-Solomon
  • BCH Bose-Chaudhuri-Hocquenghem
  • Fire code extended BCH code
  • Hamming code extended Hamming code
  • turbo code turbo product code
  • LDPC low density parity check
  • the commonly used crystal oscillator frequency (also called the basic frequency) of Ethernet is 156.25 megahertz (MHz) or 312.5MHz.
  • the rate of each physical channel is 25.78125 gigabit per second (Gbps or Gb/s) non return to zero (NRZ) modulation, and the transmission baud rate is 165 times the basic frequency of 156.25MHz.
  • each physical channel The rate is 106.25Gb/s four-level (or four-level) pulse amplitude modulation (PAM4) modulation, and the baud rate is 53.125GBd, which is 340 times the basic frequency of 156.25MHz.
  • PAM4 pulse amplitude modulation
  • 200G/lane intensity-modulation direct detection (IMDD) optical link may adopt cascaded FEC.
  • RS 544, 514 code provided by the host application-specific integrated circuit (host ASIC) chip
  • the optical module performs a certain integration operation on the data stream without decoding, and then superimposes a layer of short code encoding, which can be any FEC code.
  • the cascade code can also be fully integrated into, for example, the host ASIC chip.
  • the cascade FEC includes an outer code and an inner code.
  • the outer code is the first FEC code and the inner code is the second FEC code.
  • the overhead of the inner code (the second FEC code) will be considered.
  • the selection can also support integer multiples of the base frequency.
  • the information bit length of the second FEC code is represented by k, and the length of the second FEC codeword is represented by n. k and n are positive integers, and the values of k and n are related to the code type.
  • the process diagram of cascade coding for example, in the case of nominal 200G/lane, the transmission rate after 64-bit (bit, B)/66B coding is 206.25Gb/s, and after transcoding to 256B/257B coding, the transmission rate is 200.78125Gb/s.
  • the actual transmission rate of nominal 200G/lane is 212.5Gb/s.
  • the baud rate is 106.25GBd.
  • the physical link rate can be increased to 225Gb/s, that is, 112.5GBd (112.5G baud rate), which is 720 times the base frequency.
  • 112.5GBd 112.5G baud rate
  • the operation of the second FEC code is shown in Figure 1.
  • the relevant information for data transmission may be some management and control information, which includes but is not limited to: adjusting optical device parameters, adjusting electrical characteristic parameters of optical modules, communicating with the opposite end about the quality of signal reception and transmission, negotiating the switch of the FEC interleaver, and so on.
  • the embodiment of the present application provides a method for transmitting data, which improves the reliability of transmitting the padding data by protecting the padding data, thereby enabling the relevant information of the data transmission carried by the padding data to be transmitted more reliably.
  • FIG2 is a schematic diagram of an implementation scenario of a method for transmitting data provided in an embodiment of the present application.
  • the implementation scenario includes a first module 101 and a second module 102, and the first module 101 and the second module 102 are communicatively connected.
  • the first module 101 and the second module 102 are communicatively connected via multiple physical links.
  • the first module 101 is included in a first device
  • the second module 102 is included in a second device.
  • the first module 101 and the second module 102 may also be included in the same device.
  • the device where any one or more of the first module 101 and the second module 102 are located may be a network device, or may be other devices that include an Ethernet interface or comply with the IEEE 802.3 standard.
  • other modules may also be included in the implementation scenario shown in FIG2, which is not limited in the embodiment of the present application.
  • the method for transmitting data provided in an embodiment of the present application may be shown in FIG. 3 , taking the first module executing the method as an example, including the following S301 - S304 .
  • a first module obtains first data, where the first data is obtained by encoding first reference data with a first FEC code.
  • the first module obtains the first data by encoding the first reference data using a first FEC code after obtaining the first reference data. In this manner, the first module is the source node of data transmission.
  • the first module may obtain the first data in such a way that other modules other than the first module encode the first reference data using the first FEC code to obtain the first data, and then send the first data to the first module, so that the first module obtains the first data.
  • the first module may be an intermediate node for data transmission.
  • the first reference data may also be scrambled before the first module or other modules encode the first reference data using the first FEC code.
  • the first FEC code includes but is not limited to any one of RS code, BCH code, fire code, extended BCH code, Hamming code, extended Hamming code, turbo code, TPC code, staircase code and LDPC code.
  • the first data may also undergo other processing.
  • the embodiment of the present application does not limit the processing methods of other processing.
  • the first data is data that encodes the first reference data using the first FEC code, passes through the physical medium access sublayer (physical medium attachment sublayer, PMA) and/or passes through the physical medium dependent layer interface (physical media dependent, PMD), or the first data is data that is encoded using the first FEC code, interleaved and PMA and/or PMD.
  • the interleaving process can be multiple times, for example, the first data is encoded using the first FEC code, interleaved, PMA and/or PMD, then interleaved, reconverged, and so on.
  • the first module encodes the first data according to the second FEC code to obtain a first encoding result.
  • the quality of data transmission can be improved.
  • the embodiment of the present application does not limit the second FEC code, including but not limited to any one of RS code, BCH code, fire code, extended BCH code, Hamming code, extended Hamming code, turbo code, TPC code, staircase code and LDPC code.
  • the second FEC code used can be self-negotiated by the first module and the second module receiving the data.
  • the self-negotiation process can be performed after the first module obtains the first data, or before executing the method.
  • the embodiment of the present application does not limit the timing of the self-negotiation.
  • the first data is data received by the first module and sent by other modules and obtained through scrambling
  • the first module encodes the first data according to the second FEC code
  • the scrambling code of the first data is removed, and the data after the scrambling code is removed is encoded according to the second FEC code to obtain a first encoding result.
  • the data after the scrambling code is removed is still data encoded using the first FEC code.
  • the first module obtains second data, the second data includes the first coding result and filling data for adjusting the frequency, the filling data carries relevant information of the data transmission, and the filling data is protected data.
  • the overhead of the inner code (second FEC code) is also considered, and the selection can also support integer multiples of the base frequency.
  • the overhead ratio of the second FEC code cannot support integer multiples, it is usually necessary to add additional padding (pad or padding) data to increase it to an integer multiple. Therefore, when obtaining the second data, the method provided in the embodiment of the present application can be implemented by inserting padding data in the first encoding result, and the padding data can be used to adjust the frequency point.
  • the first module obtains the second data, including: the first module inserts padding data for adjusting the frequency point in the first encoding result according to the reference density to obtain the second data.
  • the reference density includes but is not limited to the frequency determination based on the overhead ratio of the first FEC code and the second FEC code and the crystal oscillator used when encoding the first data according to the second FEC code.
  • the frequency of the crystal oscillator involved in determining the reference density is the frequency of the crystal oscillator used by the first module when encoding the first data according to the second FEC code.
  • the reference density of inserted padding data may also be referred to as the ratio of inserted padding data.
  • the 200G/lane physical channel rate encoded by the first FEC code RS (544, 514) code is 212.5Gb/s, which is 106.25GBd under PAM4 modulation
  • Z can also be greater than An integer.
  • the reference density (ratio) of the inserted padding data is 1/1088.
  • p bits are inserted every 1088*p bits.
  • p is the length of the inserted padding data.
  • the embodiment of the present application does not limit the length of the padding data. It is only necessary to ensure that the reference density (ratio) of the inserted padding data meets the requirement of 1/m.
  • the length of the padding data can be an integer multiple of the length of the second FEC code.
  • the present embodiment can protect the padding data.
  • the present application embodiment does not limit the protection processing method used for the padding data, which includes but is not limited to the following three methods.
  • Protection processing method 1 protection processing includes adding a cyclic redundancy check (CRC), and the padding data is the data to be protected by the CRC.
  • CRC cyclic redundancy check
  • the length p of the padding data needs to meet the length that can be inserted into the CRC.
  • the length of p is at least required to be N+1 bits.
  • the length p of the padding data can be 2N or longer, and N can be a positive integer greater than or equal to 3.
  • the length p of the padding data is an integer multiple of the second FEC codeword length n. Therefore, the length of the padding data must not only meet the requirement of being able to insert the CRC, but also meet the requirement of being an integer multiple of the second FEC codeword length n.
  • CRC is a verification mechanism that detects whether the data within its protection range (including the check bit) has errors after transmission. If CRC protection is added to the padding data, it can be used to detect whether the padding data within the CRC protection range has errors after transmission.
  • CRC-n means that the check bit length is n bits (bit). For the same length of check bits n bits, there are multiple calculation methods to generate the check bits, and the calculation method is determined by the polynomial corresponding to the CRC. The highest term of the CRC-n polynomial is the nth power, and different polynomials may have different verification capabilities.
  • the padding data after protection includes 112 bits of operations, administration and maintenance (OAM) information and CRC-16 check bits.
  • OAM operations, administration and maintenance
  • CRC-16 check bits.
  • the CRC polynomial 0x9eb2 is used, that is, x ⁇ 16+x ⁇ 13+x ⁇ 12+x ⁇ 11+x ⁇ 10+x ⁇ 8+x ⁇ 6+x ⁇ 5+x ⁇ 2+1, that is, x16+x13+x12+x11+x10+x8+x6+x5+x2+1.
  • the CRC can ensure that it is detected.
  • the receiving side verifies the CRC before receiving the information, which greatly increases the probability of receiving the correct information.
  • the probability of 6 or more bit errors within the 128-bit range is 2.8 x 10-5.
  • the reliability is increased by 20,000 times when CRC-16 is added.
  • Protection processing method 2 the protection processing includes encoding with a third FEC code, and the padding data is data encoded with the third FEC code.
  • the FEC code can not only detect errors, but also correct bit errors, thereby reducing the packet loss rate.
  • the reliability of the padding data can be further improved after the third FEC code is calculated.
  • the embodiment of the present application does not limit the third FEC code, including but not limited to any one of RS code, BCH code, fire code, extended BCH code, Hamming code, extended Hamming code, turbo code, TPC code, staircase code and LDPC code.
  • the third FEC code used can be self-negotiated by the first module and the second module receiving the data. The self-negotiation process can be performed after the first module obtains the first coding result, or it can be performed before executing the method.
  • the embodiment of the present application does not limit the timing of the self-negotiation.
  • the third FEC code used for the padding data may be the same as the second FEC code, or may be different from the second FEC code.
  • the decoder of the second FEC code will cause "empty beats", that is, there is no data to be processed in a certain clock cycle, which not only requires additional processing, but also wastes chip performance.
  • the encoder and decoder of the second FEC code that have been implemented are reused as much as possible.
  • the padding data after protection processing includes 120 bits (bits) of OAM information and 8 bits of check bits.
  • the 8-bit check bit can use a parity code. If the receiving side uses hard decision decoding to correct errors after adding the padding data after FEC protection, 1 bit error can be corrected, thereby increasing the correct probability of each padding data from 56.1% to 88.6%. If soft decision decoding and error correction are used, it can be increased to more than 98%.
  • Protection processing method three the protection processing includes adding CRC and using the third FEC code for encoding, and the padding data is the data to which CRC protection is added and encoded using the third FEC code.
  • the third protection processing method is a combination of the first protection processing method and the second protection processing method, and can be used in scenarios where high reliability requirements are placed on the relevant information of the data carried. For example, when the "mean time before first false acceptance" (also called mean time to false packet acceptance (MTTFPA)) is required to be greater than 1.3 x 109 years, a combination of multiple protection processing methods may be needed to protect the padding data.
  • MTTFPA mean time to false packet acceptance
  • the third protection processing method it is necessary to add CRC first and then use the third FEC code for encoding.
  • the CRC content can be protected by FEC. If the CRC content is wrong, it can be corrected, further improving the reliability and efficiency of transmitting the padding data.
  • the padding data is first protected by CRC, and the CRC content is FEC-encoded together with the padding data such as OAM information. FEC error correction is performed first on the receiving side, and then CRC check is performed.
  • the embodiment of the present application does not limit the manner in which the first module transmits the second data to the second module.
  • the first module transmits the second data to the second module through a physical link.
  • the first module transmits the second data through a logical channel, and the logical channel may be a physical coding sublayer (PCS) channel or an FEC channel.
  • PCS physical coding sublayer
  • FEC FEC channel
  • S305 The second module receives second data.
  • the second data includes the first coding result and filling data for adjusting the frequency.
  • the second data is obtained by the first module inserting the filling data for adjusting the frequency into the first coding result, the filling data carries relevant information of the data transmission, and the filling data is protected data.
  • the first coding result is obtained by encoding the first data based on the second FEC code, and the first data is obtained by encoding the first reference data using the first FEC code.
  • the embodiment of the present application does not limit the way in which the second module receives the second data transmitted by the first module, which can correspond to the way in which the first module transmits the second data to the second module.
  • the way in which the second data is obtained can refer to the above-mentioned process of S301-S304, which will not be repeated here.
  • the second module obtains the first encoding result and padding data from the second data.
  • the second module can obtain the first encoding result and the padding data from the second data after receiving the second data.
  • the embodiment of the present application does not limit the manner in which the second module obtains the first encoding result and the padding data from the second data.
  • the second module decodes the first encoding result according to the second FEC code to obtain the first data, and obtains relevant information of the data transmission based on the padding data.
  • the embodiment of the present application does not limit the manner in which the second module decodes the first coding result according to the second FEC code.
  • the second module can first decode the first coding result according to the second FEC code to obtain the first data, and then obtain the relevant information of the data transmission based on the padding data.
  • the second module can also first obtain the relevant information of the data transmission based on the padding data, and then decode the first coding result according to the second FEC code to obtain the first data.
  • the embodiment of the present application does not limit the order in which the second module obtains the first data and obtains the relevant information of the data transmission.
  • protection processing includes adding CRC, and the filling data is data with added CRC protection; the second module obtains relevant information of data transmission based on the filling data, including: the second module performs CRC check on the filling data, and obtains relevant information of data transmission after the CRC check passes.
  • the second module When the second module performs a CRC check on the padding data, the length of the CRC protection added to the padding data can be used to perform a CRC check on the padding data. If the CRC check passes, it means that the padding data is not wrong, and the relevant information obtained for data transmission is also accurate and reliable. In a possible implementation, when the second module performs a CRC check on the padding data, if the CRC check fails, the second module may not obtain the relevant information for data transmission, or obtain the correct relevant information for data transmission through other means. This application does not limit the processing process after the CRC check fails.
  • Acquisition method two, protection processing includes encoding with a third FEC code, and the padding data is data encoded with the third FEC code; the second module obtains relevant information of data transmission based on the padding data, including: the second module uses the third FEC code to decode the padding data, and obtains relevant information of data transmission according to the decoding result.
  • the third FEC code can be determined by negotiation between the first module and the second module, the second module can determine to use the third FEC code when decoding the padding data.
  • the third FEC code can be any type of FEC code, and the embodiment of the present application does not elaborate on the process of decoding the padding data using the third FEC code.
  • Acquisition method three, protection processing includes adding CRC and encoding with a third FEC code, and the padding data is data that adds CRC protection and is encoded with a third FEC code; the second module obtains relevant information about data transmission based on the padding data, including: the second module uses The third FEC code decodes the padding data, performs a CRC check on the decoding result, and obtains relevant information of the data transmission after the CRC check passes.
  • the third acquisition method can be understood as the reverse process of the third protection processing method in S303.
  • the third FEC code can be used to decode the padding data first, and after obtaining the decoding result, the decoding result is subjected to CRC check. If the CRC check passes, the relevant information of the data transmission is obtained. Optionally, if the third FEC code is used to decode the padding data unsuccessfully, the subsequent CRC check operation may not be performed.
  • the reliability of the padding data during transmission is improved by adding CRC protection to the padding data or using FEC coding protection or a combination of the two.
  • the method provided in the embodiment of the present application also supports multiple transmissions of the same padding data, so that the receiving end, i.e., the second module, can determine whether the correct padding data is received by majority voting, thereby obtaining relevant information for reliable data transmission.
  • the first module after the first module transmits the second data, it also includes: the first module obtains at least one third data, the third data is obtained by encoding the second reference data using the fourth FEC code; for any third data of the at least one third data, the first module encodes any third data according to the fifth FEC code to obtain a second coding result; obtains fourth data, the fourth data includes the second coding result and the padding data; and transmits the fourth data.
  • the fourth data when obtaining the fourth data, can be obtained by inserting padding data into the second encoding result.
  • the above-mentioned at least one third data can be one or more.
  • the embodiment of the present application does not limit the number of third data obtained by the first module. If the number of third data is multiple, the first module can obtain multiple third data at different times or simultaneously. The embodiment of the present application does not limit the way in which the first module obtains the third data.
  • the method for obtaining the first data in S301 can be referred to.
  • first reference data and the second reference data may be the same or different.
  • the fourth FEC code and the fifth FEC code may be the same as the first FEC code, the second FEC code or the third FEC code, or may be different from the first FEC code, the second FEC code or the third FEC code.
  • a third data is encoded by the fifth FEC code
  • a second encoding result can be obtained
  • the padding data is inserted into the second encoding result
  • a fourth data can be obtained.
  • the number of the third data and the fourth data can be the same.
  • the padding data inserted in the second encoding result can be the same as the padding data inserted in the first encoding result, that is, the same padding data will be transmitted to the second module multiple times through the second data and the fourth data.
  • the padding data inserted in the second encoding result is also protected.
  • the method for obtaining the padding data can refer to the relevant description of S303, and the method for transmitting the fourth data can refer to the relevant description of S304, which will not be repeated here.
  • the second module receives at least one fourth data, the fourth data includes a second coding result and padding data, the second coding result is obtained by encoding the third data based on the fifth FEC code, and the third data is obtained by encoding the second reference data using the fourth FEC code; the second module obtains the second coding result and padding data from each fourth data; and decodes the second coding result according to the fifth FEC code to obtain the third data.
  • the second module obtains the relevant information of the data transmission based on the padding data, including: the second module compares the padding data obtained from each fourth data with the padding data obtained from the second data, and when it is determined according to the comparison result that the number of identical padding data reaches a threshold, the second module obtains the relevant information of the data transmission based on the padding data.
  • the embodiment of the present application does not limit the threshold value reached by the number of identical filling data.
  • the threshold value can be set based on experience, can be flexibly set based on the application scenario, and can also be determined based on the number of times the filling data is sent. For example, the first module sends the same filling data three times in a row, and the second module determines whether there are two identical filling data. If there are two identical filling data, the relevant information of the data transmission is obtained. If no two filling data are identical, the received filling data is discarded.
  • the method provided in the embodiment of the present application supports dividing the longer padding data into smaller data blocks, and implements the padding data comparison process by comparing the data blocks, thereby improving the comparison efficiency.
  • the second module compares the padding data obtained from each fourth data with the padding data obtained from the second data, including: the second module divides the padding data obtained from each fourth data with the padding data obtained from the second data, and compares the divided data blocks.
  • the embodiment of the present application does not limit the granularity of the second module to divide the padding data, for example, it can be divided by bytes, and each byte is compared byte by byte.
  • the technical solution provided in the embodiment of the present application can improve the reliability and efficiency of transmitting the padding data by protecting the padding data when cascade coding is used and padding data needs to be inserted, thereby improving the reliability of the related information of the data transmission carried by the padding data.
  • there are various ways to protect the padding data which improves the flexibility of protecting the padding data and makes it more adaptable.
  • the FEC code used for FEC encoding of the padding data in the embodiment of the present application is the same as the inner code in the cascade coding, that is, the second FEC code, which can avoid wasting chip performance. By setting the length of the padding data to an integer multiple of the length of the second FEC code, it is convenient to fix the boundary of the second FEC code.
  • FIG7 is a schematic diagram of the structure of a device for transmitting data provided by the embodiment of the present application. Based on the multiple modules shown in FIG7, the device for transmitting data shown in FIG7 can perform all or part of the operations performed by the first module in the method embodiment shown in FIG3 above. It should be understood that the device may include more additional modules than the modules shown or omit some of the modules shown therein, and the embodiment of the present application does not limit this. As shown in FIG7, the device includes:
  • a first acquisition module 701 is used to acquire first data, where the first data is obtained by encoding first reference data using a first FEC code;
  • the encoding module 702 is used to encode the first data according to the second FEC code to obtain a first encoding result
  • a second acquisition module 703 is used to acquire second data, where the second data includes the first coding result and padding data for adjusting the frequency point, where the padding data carries relevant information of data transmission, and the padding data is protected data;
  • the transmission module 704 is configured to transmit the second data.
  • the protection process includes adding a CRC
  • the padding data is data to which the CRC protection is added.
  • the protection process includes encoding using a third FEC code, and the padding data is data encoded using the third FEC code.
  • the protection process includes adding CRC and encoding with a third FEC code, and the padding data is data to which CRC protection is added and encoded with the third FEC code.
  • the third FEC code is the same as the second FEC code.
  • the length of the padding data is an integer multiple of the second FEC code length.
  • the second acquisition module 703 is used to insert padding data for adjusting the frequency point in the first encoding result according to a reference density to obtain second data, and the reference density is determined based on the overhead ratio of the first FEC code and the second FEC code and the frequency of the crystal oscillator used when encoding the first data according to the second FEC code.
  • the first acquisition module 701 is also used to acquire at least one third data, where the third data is obtained by encoding the second reference data using the fourth FEC code; the encoding module 702 is also used to encode any third data among the at least one third data according to the fifth FEC code to obtain a second encoding result; the second acquisition module 703 is also used to acquire fourth data, where the fourth data includes the second encoding result and padding data; and the transmission module 704 is also used to transmit the fourth data.
  • FIG8 is a schematic diagram of the structure of a device for transmitting data provided by the embodiment of the present application. Based on the multiple modules shown in FIG8, the device for transmitting data shown in FIG8 can perform all or part of the operations performed by the second module in the method embodiment shown in FIG3 above. It should be understood that the device may include more additional modules than the modules shown or omit some of the modules shown therein, and the embodiment of the present application does not limit this. As shown in FIG8, the device includes:
  • the receiving module 801 is used to receive second data, where the second data includes a first coding result and padding data for adjusting the frequency, where the padding data carries relevant information of data transmission and is protected data, where the first coding result is obtained by encoding the first data based on the second FEC code, and the first data is obtained by encoding the first reference data using the first FEC code;
  • a first acquisition module 802 configured to acquire a first encoding result and padding data from second data
  • a decoding module 803, configured to decode the first encoding result according to the second FEC code to obtain first data
  • the second acquisition module 804 is used to acquire relevant information of data transmission based on the filling data.
  • the protection processing includes adding CRC, and the padding data is data to which CRC protection is added; the second acquisition module 804 is used to perform CRC check on the padding data, and after the CRC check passes, obtain relevant information of the data transmission.
  • the protection processing includes encoding using a third FEC code, and the padding data is data encoded using the third FEC code; the second acquisition module 804 is used to decode the padding data using the third FEC code, and obtain relevant information of the data transmission based on the decoding result.
  • the protection processing includes adding a cyclic redundancy check CRC and encoding with a third FEC code, and the padding data is data with added CRC protection and encoded with a third FEC code; the second acquisition module 804 is used to decode the padding data with the third FEC code, perform a CRC check on the decoding result, and obtain relevant information of the data transmission after the CRC check passes.
  • the third FEC code is the same as the second FEC code.
  • the length of the padding data is an integer multiple of the second FEC code length.
  • the receiving module 801 is further configured to receive at least one fourth data, the fourth data including the second encoding result and the padding data, the second encoding result is obtained by encoding the third data based on the fifth FEC code, and the third data is obtained by encoding the third data using the fourth FEC code.
  • the second reference data is encoded; the first acquisition module 802 is also used to obtain the second encoding result and padding data from each fourth data; the decoding module 803 is also used to decode the second encoding result according to the fifth FEC code to obtain the third data; the second acquisition module 804 is used to compare the padding data obtained from each fourth data with the padding data obtained from the second data, and when it is determined according to the comparison result that the number of identical padding data reaches a threshold, obtain relevant information of data transmission based on the padding data.
  • the second acquisition module 804 is used to segment the padding data acquired from each fourth data and the padding data acquired from the second data, respectively, and compare the data blocks obtained by segmentation.
  • the embodiment of the present application provides a communication device, the hardware structure of which is a communication device 1500 as shown in FIG9, including a transceiver 1501, a processor 1502 and a memory 1503.
  • the transceiver 1501, the processor 1502 and the memory 1503 are connected via a bus 1504.
  • the transceiver 1501 is used to receive and send messages
  • the memory 1503 is used to store instructions or program codes
  • the processor 1502 is used to call the instructions or program codes in the memory 1503 so that the device executes the relevant processing steps of the first module or the second module in the above-mentioned method embodiment.
  • the communication device 1500 of the embodiment of the present application may correspond to the first module or the second module in the above-mentioned various method embodiments, and the processor 1502 in the communication device 1500 reads the instructions or program codes in the memory 1503, so that the communication device 1500 shown in FIG9 can execute all or part of the operations performed by the first module or the second module.
  • the communication device 1500 can also correspond to the device shown in Figure 7 or 8 above.
  • the transmission module 704 and the receiving module 801 involved in Figure 7 and Figure 8 are equivalent to the transceiver 1501, and the first acquisition module 701, the encoding module 702, the second acquisition module 703, the first acquisition module 802, the decoding module 803, and the second acquisition module 804 are equivalent to the processor 1502.
  • Fig. 10 shows a schematic diagram of the structure of a communication device 2000 provided by an exemplary embodiment of the present application.
  • the communication device 2000 shown in Fig. 10 is used to perform the operations involved in the method for transmitting data shown in Fig. 3.
  • the communication device 2000 is, for example, a switch, a router, etc.
  • the communication device 2000 includes at least one processor 2001 , a memory 2003 , and at least one communication interface 2004 .
  • the processor 2001 is, for example, a general-purpose central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing units (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solution of the present application.
  • the processor 2001 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.
  • the PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.
  • the processor can implement or execute various logic blocks, modules, and circuits described in conjunction with the disclosure of the embodiments of the present invention.
  • the processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.
  • the communication device 2000 also includes a bus.
  • the bus is used to transmit information between the components of the communication device 2000.
  • the bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc.
  • PCI peripheral component interconnect
  • EISA extended industry standard architecture
  • the bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in FIG10, but it does not mean that there is only one bus or one type of bus.
  • the components of the communication device 2000 in FIG10 can also be connected in other ways, and the embodiment of the present invention does not limit the connection method of each component.
  • the memory 2003 is, for example, a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto.
  • the memory 2003 is, for example, independent and connected to the processor 2001 via a bus.
  • the memory 2003 can also be integrated with the processor 2001. together.
  • the communication interface 2004 uses any transceiver-like device for communicating with other devices or communication networks, and the communication network can be Ethernet, a radio access network (RAN) or a wireless local area network (WLAN), etc.
  • the communication interface 2004 can include a wired communication interface and a wireless communication interface.
  • the communication interface 2004 can be an Ethernet interface, a Fast Ethernet (FE) interface, a Gigabit Ethernet (GE) interface, an Asynchronous Transfer Mode (ATM) interface, a wireless local area network (WLAN) interface, a cellular network communication interface or a combination thereof.
  • the Ethernet interface can be an optical interface, an electrical interface or a combination thereof.
  • the communication interface 2004 can be used for the communication device 2000 to communicate with other devices.
  • the processor 2001 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG10 .
  • Each of these processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor.
  • the processor here may refer to one or more devices, circuits, and/or processing cores for processing data (e.g., computer program instructions).
  • the communication device 2000 may include multiple processors, such as the processor 2001 and the processor 2005 shown in FIG10. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU).
  • the processor here may refer to one or more devices, circuits, and/or processing cores for processing data (such as computer program instructions).
  • the communication device 2000 may also include an output device and an input device.
  • the output device communicates with the processor 2001 and may display information in a variety of ways.
  • the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector.
  • the input device communicates with the processor 2001 and may receive user input in a variety of ways.
  • the input device may be a mouse, a keyboard, a touch screen device, or a sensor device.
  • the memory 2003 is used to store the program code 2010 for executing the solution of the present application
  • the processor 2001 can execute the program code 2010 stored in the memory 2003. That is, the communication device 2000 can implement the message method provided by the method embodiment through the processor 2001 and the program code 2010 in the memory 2003.
  • the program code 2010 may include one or more software modules.
  • the processor 2001 itself can also store the program code or instruction for executing the solution of the present application.
  • the communication device 2000 of the embodiment of the present application may correspond to the first module or the second module in the above-mentioned method embodiments.
  • the processor 2001 in the communication device 2000 reads the program code 2010 in the memory 2003 or the program code or instructions stored in the processor 2001 itself, so that the communication device 2000 shown in Figure 10 can execute all or part of the operations performed by the first module or the second module.
  • the communication device 2000 may also correspond to the apparatus shown in FIG. 7 or FIG. 8, and each functional module in the apparatus shown in FIG. 7 or FIG. 8 is implemented by the software of the communication device 2000.
  • the functional modules included in the apparatus shown in FIG. 7 or FIG. 8 are generated after the processor 2001 of the communication device 2000 reads the program code 2010 stored in the memory 2003.
  • the transmission module 704 and the receiving module 801 involved in FIG. 7 or FIG. 8 are equivalent to the communication interface 2004, and the first acquisition module 701, the encoding module 702, the second acquisition module 703, the first acquisition module 802, the decoding module 803, and the second acquisition module 804 are equivalent to the processor 2001 and/or the processor 2005.
  • each step of the method shown in Figure 3 is completed by an integrated logic circuit of hardware or software instructions in the processor of the communication device 2000.
  • the steps of the method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor, or a combination of hardware and software modules in the processor.
  • the software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc.
  • the storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.
  • FIG. 11 shows a schematic diagram of the structure of a communication device 2100 provided by another exemplary embodiment of the present application.
  • the communication device 2100 shown in FIG. 11 is used to perform all or part of the operations involved in the method shown in FIG. 3 above.
  • the communication device 2100 is, for example, a switch, a router, etc., and the communication device 2100 can be implemented by a general bus architecture.
  • the communication device 2100 includes: a main control board 2110 and an interface board 2130 .
  • the main control board is also called the main processing unit (MPU) or route processor card.
  • the main control board 2110 is used to control and manage various components in the communication device 2100, including routing calculation, device management, device maintenance, and protocol processing functions.
  • the main control board 2110 includes: a central processing unit 2111 and a memory 2112.
  • the interface board 2130 is also called a line processing unit (LPU), a line card or a service board.
  • the interface board 2130 is used to provide various service interfaces and implement data packet forwarding.
  • Service interfaces include but are not limited to Ethernet interfaces, POS (Packet over SONET/SDH) interfaces, etc., and Ethernet interfaces are, for example, Flexible Ethernet Clients (FlexE Clients).
  • the interface board 2130 includes: a central processing unit 2131, a network processor 2132, a forwarding table entry memory 2134 and a physical interface card (PIC) 2133.
  • PIC physical interface card
  • the central processor 2131 on the interface board 2130 is used to control and manage the interface board 2130 and communicate with the central processor 2111 on the main control board 2110 .
  • the network processor 2132 is used to implement the message sending process.
  • the network processor 2132 may be in the form of a forwarding chip.
  • the forwarding chip may be a network processor (NP).
  • the forwarding chip may be implemented by an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA).
  • ASIC application-specific integrated circuit
  • FPGA field programmable gate array
  • the network processor 2132 is used to forward the received message based on the forwarding table stored in the forwarding table entry memory 2134.
  • the message is sent to the CPU (such as the central processor 2131) for processing; if the destination address of the message is not the address of the communication device 2100, the next hop and the output interface corresponding to the destination address are found from the forwarding table according to the destination address, and the message is forwarded to the output interface corresponding to the destination address.
  • the processing of the uplink message may include: processing of the message input interface, forwarding table search; the processing of the downlink message may include: forwarding table search, etc.
  • the central processing unit may also perform the functions of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, so that a forwarding chip is not required in the interface board.
  • the physical interface card 2133 is used to implement the physical layer docking function, whereby the original traffic enters the interface board 2130, and the processed message is sent out from the physical interface card 2133.
  • the physical interface card 2133 also called a daughter card, can be installed on the interface board 2130, and is responsible for converting the photoelectric signal into a message and forwarding the message to the network processor 2132 for processing after checking the legitimacy of the message.
  • the central processor 2131 can also perform the functions of the network processor 2132, such as implementing software forwarding based on a general-purpose CPU, so that the network processor 2132 is not required in the physical interface card 2133.
  • the communication device 2100 includes a plurality of interface boards, for example, the communication device 2100 further includes an interface board 2140, and the interface board 2140 includes: a central processor 2141, a network processor 2142, a forwarding table entry memory 2144, and a physical interface card 2143.
  • the functions and implementation methods of the components in the interface board 2140 are the same or similar to those of the interface board 2130, and are not described in detail herein.
  • the communication device 2100 further includes a switching fabric board 2120.
  • the switching fabric board 2120 may also be referred to as a switch fabric unit (SFU).
  • SFU switch fabric unit
  • the switching fabric board 2120 is used to complete data exchange between the interface boards.
  • the interface board 2130 and the interface board 2140 may communicate through the switching fabric board 2120.
  • the main control board 2110 is coupled to the interface board.
  • the main control board 2110, the interface board 2130, the interface board 2140, and the switching network board 2120 are connected to the system backplane through the system bus to achieve intercommunication.
  • an inter-process communication (IPC) channel is established between the main control board 2110 and the interface board 2130 and the interface board 2140, and the main control board 2110 and the interface board 2130 and the interface board 2140 communicate through the IPC channel.
  • IPC inter-process communication
  • the communication device 2100 includes a control plane and a forwarding plane.
  • the control plane includes a main control board 2110 and a central processing unit 2111.
  • the forwarding plane includes various components for performing forwarding, such as a forwarding table entry memory 2134, a physical interface card 2133, and a network processor 2132.
  • the control plane performs functions such as a router, generating a forwarding table, processing signaling and protocol messages, and configuring and maintaining the status of the communication device.
  • the control plane sends the generated forwarding table to the forwarding plane.
  • the network processor 2132 forwards the message received by the physical interface card 2133 based on the forwarding table sent by the control plane.
  • the forwarding table sent by the control plane can be stored in the forwarding table entry memory 2134. In some embodiments, the control plane and the forwarding plane can be completely separated and not on the same communication device.
  • main control boards there may be one or more main control boards, and when there are multiple boards, they may include a primary main control board and a backup main control board.
  • the communication equipment may not need a switching network board, and the interface board is responsible for the processing function of the service data of the entire system.
  • the communication equipment may have at least one switching network board, and the switching network board is used to realize data exchange between multiple interface boards, providing large-capacity data exchange and processing capabilities. Therefore, the data access and processing capabilities of the communication equipment with a distributed architecture are greater than those of the communication equipment with a centralized architecture.
  • the communication device may have only one board, that is, no switching network board, and the functions of the interface board and the main control board are integrated on the board.
  • the central processor on the interface board and the central processor on the main control board can be combined into one central processor on the board to perform the functions of the two.
  • This type of communication device has low data exchange and processing capabilities (for example, low-end switches or routers and other communication devices).
  • the specific architecture to be adopted depends on the specific networking deployment scenario, and no limitation is made here.
  • the communication device 2100 corresponds to the apparatus shown in FIG. 7 and FIG. 8.
  • the transmission module 704 and the receiving module 801 in the apparatus shown in FIG. 7 and FIG. 8 correspond to the physical interface card 2133 or the physical interface card 2143 in the communication device 2100.
  • the first acquisition module 701, the encoding module 702, the second acquisition module 703, the first acquisition module 802, the decoding module 803 in the apparatus shown in FIG. 7 or FIG. 8 correspond to the physical interface card 2133 or the physical interface card 2143 in the communication device 2100.
  • the code module 803 and the second acquisition module 804 are equivalent to at least one of the central processor 2111 , the network processor 2132 and the network processor 2142 in the communication device 2100 .
  • An embodiment of the present application also provides a network device, the network device comprising: a processor, the processor is coupled to a memory, the memory stores at least one program instruction or code, and the at least one program instruction or code is loaded and executed by the processor to enable the network device to implement any of the above-mentioned methods for transmitting data.
  • An embodiment of the present application also provides a system for transmitting data, which includes: a first module and a second module.
  • the methods executed by the first module and the second module can be found in the relevant description of the embodiment shown in Figure 3 above, and will not be repeated here.
  • An embodiment of the present application further provides a system for transmitting data, the system comprising: the device shown in FIG. 7 and the device shown in FIG. 8 .
  • the embodiment of the present application also provides a system for transmitting data, the system comprising: a first device and a second device.
  • the first device is the communication device 1500 shown in FIG. 9 or the communication device 2000 shown in FIG. 10 or the communication device 2100 shown in FIG. 11
  • the second device is the communication device 1500 shown in FIG. 9 or the communication device 2000 shown in FIG. 10 or the communication device 2100 shown in FIG. 11.
  • the method executed by the first device and the second device can refer to the relevant description of the embodiment shown in FIG3 above, and will not be described in detail here.
  • the above processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • the general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor supporting the advanced RISC machines (ARM) architecture.
  • the memory may include a read-only memory and a random access memory, and provide instructions and data to the processor.
  • the memory may also include a non-volatile random access memory.
  • the memory may also store information about the device type.
  • the memory may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory.
  • the nonvolatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory.
  • the volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available.
  • SRAM static RAM
  • DRAM dynamic random access memory
  • SDRAM synchronous DRAM
  • DDR SDRAM double data rate SDRAM
  • ESDRAM enhanced SDRAM
  • SLDRAM synchronous link DRAM
  • DR RAM direct rambus RAM
  • a computer-readable storage medium in which at least one program instruction or code is stored, and the program instruction or code is loaded and executed by a processor to enable a computer to implement any method of transmitting data as described in any one of FIG. 3 above.
  • the present application provides a computer program (product), which, when executed by a computer, can enable a processor or a computer to execute the corresponding steps and/or processes in the above method embodiments.
  • a chip comprising a processor, for calling and executing instructions stored in a memory from the memory, so that a communication device equipped with the chip executes the methods in the above aspects.
  • Another chip comprising: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected via an internal connection path, the processor is used to execute the code in the memory, and when the code is executed, the processor is used to execute the methods in the above aspects.
  • a communication device is also provided, the device comprising the above chip.
  • the device is a router, a switch or a server.
  • the computer program product includes one or more computer instructions.
  • the computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium.
  • the computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.) means.
  • the computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that includes one or more available media integrated.
  • the available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a Such as DVD), or semiconductor media (such as solid state disk).
  • the computer program product includes one or more computer program instructions.
  • the method of the embodiment of the present application can be described in the context of a machine executable instruction, and the machine executable instruction is such as included in the program module executed in the device on the real or virtual processor of the target.
  • a program module includes a routine, a program, a library, an object, a class, a component, a data structure, etc., which performs a specific task or realizes a specific abstract data structure.
  • the function of the program module can be merged or divided between the described program modules.
  • the machine executable instruction for the program module can be executed in a local or distributed device. In a distributed device, the program module can be located in both a local and a remote storage medium.
  • the computer program code for realizing the method for the embodiment of the present application can be written in one or more programming languages. These computer program codes can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device, so that the program code, when executed by a computer or other programmable data processing device, causes the function/operation specified in the flow chart and/or block diagram to be implemented.
  • the program code can be executed completely on a computer, partially on a computer, as an independent software package, partially on a computer and partially on a remote computer or completely on a remote computer or server.
  • computer program codes or related data may be carried by any appropriate carrier to enable a device, apparatus or processor to perform the various processes and operations described above.
  • Examples of carriers include signals, computer readable media, and the like.
  • Examples of signals may include electrical, optical, radio, acoustic or other forms of propagated signals, such as carrier waves, infrared signals, etc.
  • a machine-readable medium may be any tangible medium that contains or stores a program for or related to an instruction execution system, apparatus, or device.
  • a machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium.
  • a machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of machine-readable storage media include an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof.
  • the disclosed systems, devices and methods can be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the module is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or it can be an electrical, mechanical or other form of connection.
  • modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present application.
  • each functional module in each embodiment of the present application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or software functional modules.
  • the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or partly contributed to the prior art, or All or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method in each embodiment of the present application.
  • the aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.
  • first, second, etc. are used to distinguish between identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between “first”, “second”, and “nth”, nor is the quantity and execution order limited. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another.
  • the first network device may be referred to as the second network device, and similarly, the second network device may be referred to as the first network device.
  • the first network device and the second network device may both be network devices of any type, and in some cases, may be separate and different network devices.
  • the size of the serial number of each process does not mean the order of execution.
  • the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
  • determining B based on A does not mean determining B based only on A.
  • B can also be determined based on A and/or other information.
  • references to “one embodiment”, “an embodiment”, or “a possible implementation” throughout the specification mean that specific features, structures, or characteristics related to the embodiment or implementation are included in at least one embodiment of the present application. Therefore, the references to “in one embodiment” or “in an embodiment”, or “a possible implementation” throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

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Abstract

本申请公开了一种传输数据的方法、装置、设备、系统及存储介质，属于通信领域。方法包括：获取采用第一FEC码对第一参考数据进行编码得到的第一数据；按照第二FEC码对第一数据进行编码，得到第一编码结果；获取第二数据，其中，第二数据包括第一编码结果和用于调整频点的填充数据，填充数据携带数据传输的相关信息，且填充数据为经过保护处理的数据；传输第二数据。该方法通过对填充数据进行保护，以提高传输填充数据的可靠性和效率，进而使得填充数据所携带的数据传输的相关信息能够更加可靠的传输。

Description

传输数据的方法、装置、设备、系统及存储介质
本申请要求于2023年1月13日提交的申请号为202310200011.3、发明名称为“一种提高带内管理(OAM)通信可靠性的方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中；本申请还要求于2023年1月31日提交的申请号为202310119761.8、发明名称为“传输数据的方法、装置、设备、系统及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，尤其涉及一种传输数据的方法、装置、设备、系统及存储介质。
背景技术
在通信领域，以太网在物理链路上的传输速率通常选择晶振的整数倍频。在传输数据时，针对采用级联编码的情况，如果内码编码的开销比无法支持整数倍频，通常需要增加额外的填充数据。
发明内容
本申请提出一种传输数据的方法、装置、设备、系统及存储介质，用于提高传输填充数据的可靠性和效率。
第一方面，提供了一种传输数据的方法，该方法包括：获取第一数据，所述第一数据为采用第一前向纠错(forward error correction，FEC)码对第一参考数据进行编码得到；按照第二FEC码对所述第一数据进行编码，得到第一编码结果；获取第二数据，所述第二数据包括所述第一编码结果和用于调整频点的填充数据，所述填充数据携带数据传输的相关信息，且所述填充数据为经过保护处理的数据；传输所述第二数据。
该方法通过对填充数据进行保护，以提高传输填充数据的可靠性和效率，进而使得填充数据所携带的数据传输的相关信息能够更加可靠的传输。第一FEC码和第二FEC码包括但不限于里德-所罗门(Reed-Solomon，RS)码、博斯-乔赫里-霍克文黑姆(Bose-Chaudhuri-Hocquenghem，BCH)码、法尔(fire)码、扩展BCH码、汉明码、扩展汉明码、涡轮(turbo)码、涡轮乘积码(turbo product code，TPC)、阶梯(staircase)码以及低密度奇偶校验(low density parity check，LDPC)码中的任一种。
在一种可能的实现方式中，所述保护处理包括增加CRC，所述填充数据为增加所述CRC保护的数据。如果对填充数据增加CRC保护，则可以用于检测CRC保护范围内的填充数据在经过传输后是否存在错误。为了增加CRC功能，填充数据的长度需要满足可以插入CRC的长度。
在一种可能的实现方式中，所述保护处理包括采用第三FEC码进行编码，所述填充数据为采用所述第三FEC码进行编码的数据。由于FEC码不仅可以检错，还可以纠正比特错误，从而降低丢包率。通过采用第三FEC码对填充数据进行编码，填充数据经过第三FEC码计算之后可进一步提高可靠性。
在一种可能的实现方式中，所述保护处理包括增加循环冗余校验(cyclic redundancy check，CRC)以及采用第三FEC码进行编码，所述填充数据为增加所述CRC保护以及采用所述第三FEC码进行编码的数据。该种保护方式可应用在对携带的数据传输的相关信息有高可靠性要求的场景中，此外，需要按照先增加CRC，再采用第三FEC码进行编码的顺序。按照该顺序，CRC内容可以被FEC保护，如果CRC内容出错还能被纠正，进一步提高传输填充数据的可靠性和效率。
在一种可能的实现方式中，所述第三FEC码与所述第二FEC码相同。第三FEC码与第二FEC码相同的情况下，尽可能重用已经实现的第二FEC码的编码器和解码器。
在一种可能的实现方式中，所述填充数据的长度为所述第二FEC码长度的整数倍。由此，能够便于第二FEC的边界固定。
在一种可能的实现方式中，所述获取第二数据，包括：按照参考密度在所述第一编码结果中插入用于调整频点的填充数据，得到所述第二数据，所述参考密度基于所述第一FEC码和所述第二FEC码的开销比例以及按照所述第二FEC码对所述第一数据进行编码时使用的晶体振荡器的频率确定。
在一种可能的实现方式中，所述传输所述第二数据之后，所述方法还包括：获取至少一个第三数据，所述第三数据为采用第四FEC码对第二参考数据进行编码得到；对于所述至少一个第三数据中的任一第三数据，按照第五FEC码对所述任一第三数据进行编码，得到第二编码结果；获取第四数据，所述第四数据包括所述第二编码结果和所述填充数据；传输所述第四数据。
通过传输至少一个第四数据，第四数据和第二数据中均包括填充数据，从而实现支持多次传输相同填充数据，以使得接收端能够根据多数判决(majority voting)的方式来确定是否收到正确的填充数据，由此获取到可靠的数据传输的相关信息。
第二方面，提供了一种传输数据的方法，该方法包括：接收第二数据，所述第二数据包括第一编码结果和用于调整频点的填充数据，所述填充数据携带数据传输的相关信息，且所述填充数据为经过保护处理的数据，所述第一编码结果基于第二FEC码对第一数据进行编码得到，所述第一数据为采用第一FEC码对第一参考数据进行编码得到；从所述第二数据中获取所述第一编码结果和所述填充数据；按照所述第二FEC码对所述第一编码结果进行解码，得到所述第一数据；基于所述填充数据获取所述数据传输的相关信息。
在一种可能的实现方式中，所述保护处理包括增加CRC，所述填充数据为增加所述CRC保护的数据；所述基于所述填充数据获取所述数据传输的相关信息，包括：对所述填充数据进行所述CRC校验，在所述CRC校验通过后，获取所述数据传输的相关信息。
在一种可能的实现方式中，所述保护处理包括采用第三FEC码进行编码，所述填充数据为采用所述第三FEC码进行编码的数据；所述基于所述填充数据获取所述数据传输的相关信息，包括：采用所述第三FEC码对所述填充数据进行解码，根据解码结果获取所述数据传输的相关信息。
在一种可能的实现方式中，所述保护处理包括增加CRC以及采用第三FEC码进行编码，所述填充数据为增加所述CRC保护以及采用所述第三FEC码进行编码的数据；所述基于所述填充数据获取所述数据传输的相关信息，包括：采用第三FEC码对所述填充数据进行解码，对解码结果进行所述CRC校验，在所述CRC校验通过后，获取所述数据传输的相关信息。
在一种可能的实现方式中，所述第三FEC码与所述第二FEC码相同。
在一种可能的实现方式中，所述填充数据的长度为所述第二FEC码长度的整数倍。
在一种可能的实现方式中，所述方法还包括：接收至少一个第四数据，所述第四数据包括第二编码结果和填充数据，所述第二编码结果基于第五FEC码对第三数据进行编码得到，所述第三数据为采用第四FEC码对第二参考数据进行编码得到；从各个第四数据中获取所述第二编码结果和所述填充数据；按照所述第五FEC码对所述第二编码结果进行解码，得到所述第三数据；所述基于所述填充数据获取所述数据传输的相关信息，包括：将从所述各个第四数据中获取的填充数据与从所述第二数据中获取的填充数据进行比对，在根据比对结果确定相同填充数据的数量达到阈值的情况下，所述第二模块基于所述填充数据获取所述数据传输的相关信息。
在一种可能的实现方式中，所述将从所述各个第四数据中获取的填充数据与从所述第二数据中获取的填充数据进行比对，包括：将从所述各个第四数据中获取的填充数据与从所述第二数据中获取的填充数据分别进行切分，将切分得到的数据块进行比对。通过比对数据块的方式来实现填充数据的比对过程，提高比对效率。
第三方面，提供了一种传输数据的装置，所述装置包括：第一获取模块，用于获取第一数据，所述第一数据为采用第一FEC码对第一参考数据进行编码得到；编码模块，用于按照第二FEC码对所述第一数据进行编码，得到第一编码结果；第二获取模块，用于获取第二数据，所述第二数据包括所述第一编码结果和用于调整频点的填充数据，所述填充数据携带数据传输的相关信息，且所述填充数据为经过保护处理的数据；传输模块，用于传输所述第二数据。
在一种可能的实现方式中，所述保护处理包括增加CRC，所述填充数据为增加所述CRC保护的数据。
在一种可能的实现方式中，所述保护处理包括采用第三FEC码进行编码，所述填充数据为采用所述第三FEC码进行编码的数据。
在一种可能的实现方式中，所述保护处理包括增加CRC以及采用第三FEC码进行编码，所述填充数据为增加所述CRC保护以及采用所述第三FEC码进行编码的数据。
在一种可能的实现方式中，所述第三FEC码与所述第二FEC码相同。
在一种可能的实现方式中，所述填充数据的长度为所述第二FEC码长度的整数倍。
在一种可能的实现方式中，所述第二获取模块，用于按照参考密度在所述第一编码结果中插入用于调整频点的填充数据，得到所述第二数据，所述参考密度基于所述第一FEC码和所述第二FEC码的开销比例以及按照所述第二FEC码对所述第一数据进行编码时使用的晶体振荡器的频率确定。
在一种可能的实现方式中，所述第一获取模块，还用于获取至少一个第三数据，所述第三数据采用第四FEC码对第二参考数据进行编码得到；所述编码模块，还用于对于所述至少一个第三数据中的任一第三数据，按照第五FEC码对所述任一第三数据进行编码，得到第二编码结果；所述第二获取模块，还用于获取第四数据，所述第四数据包括所述第二编码结果和所述填充数据；所述传输模块，还用于传输所述第四数据。
第四方面，提供了一种传输数据的装置，所述装置包括：接收模块，用于接收第二数据，所述第二数据包括第一编码结果和用于调整频点的填充数据，所述填充数据携带数据传输的相关信息，且所述填充数据为经过保护处理的数据，所述第一编码结果基于第二FEC码对第一数据进行编码得到，所述第一数据为采用第一FEC码对第一参考数据进行编码得到；第一获取模块，用于从所述第二数据中获取所述第一编码结果和所述填充数据；解码模块，用于按照所述第二FEC码对所述第一编码结果进行解码，得到所述第一数据；第二获取模块，用于基于所述填充数据获取所述数据传输的相关信息。
在一种可能的实现方式中，所述保护处理包括增加CRC，所述填充数据为增加所述CRC保护的数据；所述第二获取模块，用于对所述填充数据进行所述CRC校验，在所述CRC校验通过后，获取所述数据传输的相关信息。
在一种可能的实现方式中，所述保护处理包括采用第三FEC码进行编码，所述填充数据为采用所述第三FEC码进行编码的数据；所述第二获取模块，用于采用所述第三FEC码对所述填充数据进行解码，根据解码结果获取所述数据传输的相关信息。
在一种可能的实现方式中，所述保护处理包括增加CRC以及采用第三FEC码进行编码，所述填充数据为增加所述CRC保护以及采用所述第三FEC码进行编码的数据；所述第二获取模块，用于采用第三FEC码对所述填充数据进行解码，对解码结果进行所述CRC校验，在所述CRC校验通过后，获取所述数据传输的相关信息。
在一种可能的实现方式中，所述第三FEC码与所述第二FEC码相同。
在一种可能的实现方式中，所述填充数据的长度为所述第二FEC码长度的整数倍。
在一种可能的实现方式中，所述接收模块，还用于接收至少一个第四数据，所述第四数据包括第二编码结果和填充数据，所述第二编码结果基于第五FEC码对第三数据进行编码得到，所述第三数据为采用第四FEC码对第二参考数据进行编码得到；所述第一获取模块，还用于从各个第四数据中获取所述第二编码结果和所述填充数据；所述解码模块，还用于按照所述第五FEC码对所述第二编码结果进行解码，得到所述第三数据；所述第二获取模块，用于将从所述各个第四数据中获取的填充数据与从所述第二数据中获取的填充数据进行比对，在根据比对结果确定相同填充数据的数量达到阈值的情况下，基于所述填充数据获取所述数据传输的相关信息。
在一种可能的实现方式中，所述第二获取模块，用于将从所述各个第四数据中获取的填充数据与从所述第二数据中获取的填充数据分别进行切分，将切分得到的数据块进行比对。
第五方面，提供了一种网络设备，所述网络设备包括：处理器，所述处理器与存储器耦合，所述存储器中存储有至少一条程序指令或代码，所述至少一条程序指令或代码由所述处理器加载并执行，以使所述网络设备实现上述第一方面或第二方面任一所述的方法。
第六方面，提供了一种数据传输系统，所述系统包括第一模块和第二模块，所述第一模块用于执行第一方面中任一所述的方法，所述第二模块用于执行第二方面中任一所述的方法。
第七方面，提供了一种计算机可读存储介质，所述存储介质中存储有至少一条程序指令或代码，所述程序指令或代码由处理器加载并执行时以使计算机实现上述第一方面或第二方面任一所述的方法。
第八方面，提供了一种芯片，包括处理器，所述处理器用于实现上述第一方面或第二方面任一所述的方法。
第九方面，还提供了一种通信设备，该通信设备包括第八方面所述的芯片。
第十方面，提供了一种计算机程序(产品)，包括计算机程序或代码，当其被计算机执行时，使得所述 计算机执行上述第一方面或第二方面任一所述的方法。
第十一方面，提供了另一种通信装置，该装置包括：收发器、存储器和处理器。其中，该收发器、该存储器和该处理器通过内部连接通路互相通信，该存储器用于存储指令，该处理器用于执行该存储器存储的指令，以控制收发器接收信号，并控制收发器发送信号，并且当该处理器执行该存储器存储的指令时，使得该处理器执行第一方面或第一方面的任一种可能的实施方式中的方法，或者执行第二方面或第二方面的任一种可能的实施方式中的方法。
作为一种示例性实施例，所述处理器为一个或多个，所述存储器为一个或多个。
作为一种示例性实施例，所述存储器可以与所述处理器集成在一起，或者所述存储器与处理器分离设置。
在具体实现过程中，存储器可以为非瞬时性(non-transitory)存储器，例如只读存储器(read only memory，ROM)，其可以与处理器集成在同一块芯片上，也可以分别设置在不同的芯片上，本申请实施例对存储器的类型以及存储器与处理器的设置方式不做限定。
第十二方面，提供了一种芯片，包括处理器，用于从存储器中调用并运行所述存储器中存储的指令，使得安装有所述芯片的通信设备执行上述各方面中的方法。
第十三方面，提供另一种芯片，包括：输入接口、输出接口、处理器和存储器，所述输入接口、输出接口、所述处理器以及所述存储器之间通过内部连接通路相连，所述处理器用于执行所述存储器中的代码，当所述代码被执行时，所述处理器用于执行上述各方面中的方法。
应当理解的是，本申请实施例的第二方面至第十三方面的技术方案及对应的可能的实现方式所取得的有益效果可以参见上述对第一方面及其对应的可能的实现方式的技术效果，此处不再赘述。
附图说明
图1是本申请实施例提供的一种级联编码的过程示意图；
图2是本申请实施例提供的一种实施场景示意图；
图3是本申请实施例提供的一种传输数据的方法交互示意图；
图4是本申请实施例提供的一种插入填充数据的示意图；
图5是本申请实施例提供的一种填充数据的结构示意图；
图6是本申请实施例提供的一种填充数据的结构示意图；
图7是本申请实施例提供的一种传输数据的装置的结构示意图；
图8是本申请实施例提供的一种传输数据的装置的结构示意图；
图9是本申请实施例提供的一种通信设备的结构示意图；
图10是本申请实施例提供的一种通信设备的结构示意图；
图11是本申请实施例提供的一种通信设备的结构示意图。
具体实施方式
本申请的实施方式部分使用的术语仅用于对本申请的实施例进行解释，而非旨在限定本申请。下面结合附图，对本申请的实施例进行描述。
随着通信技术的发展，数据传输方式越来越多，通过以太网链路传输数据便是其中的一种。在传输数据时，以太网在物理链路上的传输速率通常选择晶振的整数倍频。在使用前向纠错码(forward error correction，FEC)编码的以太网接口中，FEC开销选择上，也遵从传输速率通常选择晶振的整数倍频的规律。FEC码包括但不限于里德-所罗门(Reed-Solomon，RS)码、博斯-乔赫里-霍克文黑姆(Bose-Chaudhuri-Hocquenghem，BCH)码、法尔(fire)码、扩展BCH码、汉明码、扩展汉明码、涡轮(turbo)码、涡轮乘积码(turbo product code，TPC)、阶梯(staircase)码以及低密度奇偶校验(low density parity check，LDPC)码中的任一种。
例如，以太网常用晶振频率(也称为基础频率)为156.25兆赫(mega hertz，MHz)或312.5MHz等。以RS码为例，采用RS(528，514)的100GbE，100GBASE-KR4，每条物理通道速率为25.78125吉比特每秒(gigabit per second，Gbps或Gb/s)不归零码(non return to zero，NRZ)调制，传输的波特率为基础频率156.25MHz的165倍。又例如，采用RS(544，514)的400GbE，400GBASE-DR4，每条物理通道 速率为106.25Gb/s四电平(或四级)脉冲幅度调制(4-level pulse amplitude modulation，PAM4)调制，波特率为53.125GBd，为基础频率156.25MHz的340倍。
另外，在电气与电子工程师协会(Institute of Electrical and Electronics Engineers，IEEE)802.3以太接口标准讨论中，200G/通道(lane)直调直检(intensity-modulation direct detection，IMDD)光链路可能会采用级联FEC(concatenated FEC)。例如，以主专用集成电路(host application-specific integrated circuit，host ASIC)芯片提供RS(544，514)码为例，光模块在不解码的情况下，对数据流进行一定整合操作后，再叠加一层短码编码，该短码可以是任一种FEC码。其中，级联码也可以全部集成到比如host ASIC芯片中。当采用级联编码时，级联FEC包括外码和内码，以外码为第一FEC码，内码为第二FEC码为例，级联编码时会考虑内码(第二FEC码)的开销选择同样可以支持基频的整数倍频。以k来表示第二FEC码的信息位长度，以n来表示第二FEC码字长度，k和n为正整数，k和n的取值与码型有关。
如图1所示的级联编码的过程示意图，例如，在标称为200G/lane的情况下，64比特(bit,，B)/66B编码后的传输速率为206.25Gb/s，在转码为256B/257B编码后，传输速率为200.78125Gb/s，在RS(544，514)基础上，标称为200G/lane的实际传输速率为212.5Gb/s，采用PAM4调制时，波特率为106.25GBd，此时如果在此基础上采用开销比为n/k＝18/17的编码，可以将物理链路速率提高到225Gb/s,即112.5GBd(112.5G波特率)，为基频的720倍。当第二FEC码的开销比无法支持整数倍频时，通常需要增加额外的填充(pad或padding)数据，将其提高至最近的一个整数倍频。例如，如果第二FEC编码的开销比例为n/k＝16/15，上述106.25GBd传输波特率将被提高到113.333…GBd，不再是基频整数倍，而如果增加1/1088的填充数据，最终速率将会被调整到726倍基频，即113.4375GBd。第二FEC编码的操作如图1中2nd FEC编码所示。
虽然增加额外的填充数据会使得物理链路速率进一步提高，即使比例很低(例如1/1088，约0.09％)，但是对于带宽严重受限的系统也属于浪费了带宽。因此，可以采用填充数据携带数据传输的相关信息来利用该部分带宽。本申请实施例不对数据传输的相关信息进行限定，例如，数据传输的相关信息可以是一些管控信息，该管控信息包括但不限于：调整光器件参数、调整光模块电气特性参数、与对端交流信号收发质量、协商FEC交织器的开关等等。
无论通过填充数据携带哪种数据传输的相关信息，由于存在误码率，填充数据在传输过程中也会存在错误。参见下面的表1，列出了在4.5ⅹ10-3的误码率(bit error ratio，BER)的情况下，填充数据的长度和无误码传输概率的关系。
表1
基于上述表1不难看出，填充数据的长度越长，填充数据正确传输概率越低，如果采用填充数据来携带数据传输的相关信息，随着正确传输概率的降低，该数据传输的相关信息能被正确传输的可靠性不高。本申请实施例提供了一种传输数据的方法，该方法通过对填充数据进行保护，以提高传输填充数据的可靠性，进而使得填充数据所携带的数据传输的相关信息能够更加可靠的传输。
图2是本申请实施例提供的一种传输数据的方法的实施场景示意图，参见图2，该实施场景包括第一模块101和第二模块102，第一模块101和第二模块102通信连接。例如，第一模块101和第二模块102通过多条物理链路通信连接。示例性地，第一模块101包括在第一设备中，第二模块102包括在第二设备中，第一模块101和第二模块102也可以包括在同一个设备中。其中，第一模块101和第二模块102中任意一个或多个所在的设备可以是网络设备，也可以是其他包含以太网接口或符合IEEE 802.3标准的其他设备。此外，图2示出的实施场景中还可以包括其他模块，本申请实施例对此不加以限定。
本申请实施例提供的传输数据的方法可如图3所示，以第一模块执行该方法为例，包括如下S301-S304。
S301，第一模块获取第一数据，第一数据为采用第一FEC码对第一参考数据进行编码得到。
在本申请实施例中，第一模块获取第一数据的方式可以是第一模块获取到第一参考数据后，对该第一参考数据采用第一FEC码进行编码得到该第一数据，该方式下，第一模块是数据传输的源节点。
在一种可能的实施方式中，第一模块获取第一数据的方式也可以是第一模块之外的其他模块对第一参考数据采用第一FEC码进行编码得到该第一数据后，将该第一数据发送给第一模块，第一模块由此获取到第一数据。该种情况下，第一模块可以是数据传输的中间节点。可选地，第一模块或其他模块采用第一FEC码对第一参考数据进行编码之前，还可以对第一参考数据进行扰码。
无论是第一模块采用第一FEC码对第一参考数据进行编码还是其他模块采用第一FEC码对第一参考数据进行编码，第一FEC码均包括但不限于RS码、BCH码、fire码、扩展BCH码、汉明码、扩展汉明码、turbo码、TPC码、staircase码以及LDPC码中的任一种。
此外，第一数据除了为采用第一FEC码对第一参考数据进行编码得到外，还可以经过其他处理。本申请实施例不对其他处理的处理方式进行限定。例如，该第一数据为采用第一FEC码对第一参考数据进行编码、经过物理介质接入子层(physical medium attachment sublayer，PMA)和/或经过物理介质关联层接口(physical media dependent，PMD)的数据，或者，该第一数据为采用第一FEC码进行编码、经过交织处理及PMA和/或PMD的数据。其中，交织处理可以为多次，例如，第一数据为采用第一FEC码进行编码、经过交织处理、经过PMA和/或PMD、再经过交织处理、再汇聚等等。
S302，第一模块按照第二FEC码对第一数据进行编码，得到第一编码结果。
通过采用第二FEC码对第一数据再次编码，能够提高数据传输的质量。本申请实施例不对第二FEC码进行限定，包括但不限于RS码、BCH码、fire码、扩展BCH码、汉明码、扩展汉明码、turbo码、TPC码、staircase码以及LDPC码中的任一种。在一种可能的实现方式中，采用的第二FEC码可以由第一模块与接收数据的第二模块进行自协商，该自协商过程可以在第一模块获取到第一数据之后执行，也可以在执行该方法之前执行，本申请实施例不对自协商的时机进行限定。
另外，如S301所述，如果第一数据是第一模块接收的由其他模块发送的且经过扰码得到的数据，第一模块按照第二FEC码对第一数据进行编码时，去除该第一数据的扰码，对去除扰码后的数据按照第二FEC码进行编码，得到第一编码结果。其中，去除扰码后的数据仍为采用第一FEC码进行编码的数据。
S303，第一模块获取第二数据，第二数据包括第一编码结果和用于调整频点的填充数据，填充数据携带数据传输的相关信息，且填充数据为经过保护处理的数据。
如前文所述，当采用级联码编码时，也会考虑内码(第二FEC码)的开销选择同样可以支持基频的整数倍频。当第二FEC码的开销比无法支持整数倍频时，通常需要增加额外的填充(pad或padding)数据，将其提高至整数倍频。因此，本申请实施例提供的方法在获取第二数据时，可以通过在第一编码结果中插入填充数据来实现，该填充数据可用于调整频点。
在一种可能的实现方式中，第一模块获取第二数据，包括：第一模块按照参考密度在第一编码结果中插入用于调整频点的填充数据，得到第二数据。其中，参考密度包括但不限于基于第一FEC码和第二FEC码的开销比例以及按照第二FEC码对第一数据进行编码时使用的晶体振荡器的频率确定。也就是说，确定参考密度时涉及的晶体振荡器的频率是第一模块按照第二FEC码对第一数据进行编码时使用的晶体振荡器的频率。
在本申请实施例中，插入填充数据的参考密度也可以称为插入填充数据的比例。以第二FEC码为扩展汉明码(128，120)，插入填充数据的参考密度为1/m为例，对于扩展汉明码(128，120)，n＝128，k＝120。由于经过第一FEC码为RS(544，514)码进行编码的200G/lane物理通道速率为212.5Gb/s,在PAM4调制下为106.25GBd，所以对于该第二FEC码进行编码的输入信号是680倍频。此时需要使得680*n/k*(1+m)/m＝Z，其中Z是整数。为了更可能节约带宽，即对680*n/k向上取整得到Z的值。可选地，Z也可以为大于的整数。
其中，680*n/k＝725.333…,所以最接近的Z＝726，继而可以计算获得m＝1088，也即插入填充数据的参考密度(比例)为1/1088。如图4所示，每隔1088*p个比特，插入p个比特。p为插入的填充数据的长度，本申请实施例不对填充数据的长度进行限定，需要保证插入填充数据的参考密度(比例)符合1/m的要求即可。例如，为了便于第二FEC的边界固定，填充数据的长度可以为第二FEC码长度的整数倍。
无论插入填充数据的参考密度以及填充数据的长度为多少，本申请实施例均可以对填充数据进行保护 处理，以提高填充数据传输的可靠性。关于对填充数据采用的保护处理方式，本申请实施例不进行限定，包括但不限于如下三种方式。
保护处理方式一，保护处理包括增加循环冗余校验(cyclic redundancy check，CRC)，填充数据为增加CRC保护的数据。
针对该保护处理方式一，为了增加CRC功能，填充数据的长度p需要满足可以插入CRC的长度。例如，如果采用CRC-N，则至少要求p的长度为N+1比特。在本申请实施例中，考虑到效率问题，填充数据的长度p可以为2N或更长，N可以是大于或等于3的正整数。为了便于第二FEC码的边界固定，填充数据的长度p为第二FEC码字长度n的整数倍。因此，填充数据的长度既要满足可以插入CRC，也要满足第二FEC码字长度n的整数倍。
CRC是一种校验机制，CRC用于检测其保护范围内的数据(包括校验位在内)在经过传输后是否存在错误。如果对填充数据增加CRC保护，则可以用于检测CRC保护范围内的填充数据在经过传输后是否存在错误。CRC-n表示校验位长度为n比特(bit)。对于同样长度的校验位n bits，可以有多种计算方式生成校验位，计算方式由CRC对应的多项式决定。CRC-n的多项式最高项为n次方，不同多项式之间可能存在不同的校验能力。
如图5所示，以填充数据的长度p＝128，使用CRC-16对填充数据进行保护为例。经过保护处理的填充数据包括携带的112比特(bits)操作管理维护(operations,administration and maintenance，OAM)信息和CRC-16校验位。CRC-16选择有很多，在该数据长度128-16＝112bit范围，最大可保护汉明距离HD＝6。例如，采用CRC多项式0x9eb2，即x^16+x^13+x^12+x^11+x^10+x^8+x^6+x^5+x^2+1，即x16+x13+x12+x11+x10+x8+x6+x5+x2+1。当该128-bit范围内出现5比特错误时，该CRC可以确保将其检出，在接收侧校验CRC通过才收取信息，极大提高接收信息正确的概率。由于在同样4.5ⅹ10-3的BER情况下，128bit范围内出现6个或者更多比特错误的概率为：2.8ⅹ10-5。相比56.1％的出错概率，在增加CRC-16的情况下，可靠性提高了20000倍。
保护处理方式二，保护处理包括采用第三FEC码进行编码，填充数据为采用第三FEC码进行编码的数据。
FEC码不仅可以检错，还可以纠正比特错误，从而降低丢包率。通过采用第三FEC码对填充数据进行编码，填充数据经过第三FEC码计算之后可进一步提高可靠性。本申请实施例不对第三FEC码进行限定，包括但不限于RS码、BCH码、fire码、扩展BCH码、汉明码、扩展汉明码、turbo码、TPC码、staircase码以及LDPC码中的任一种。在一种可能的实现方式中，采用的第三FEC码可以由第一模块与接收数据的第二模块进行自协商，该自协商过程可以在第一模块得到第一编码结果之后执行，也可以在执行该方法之前执行，本申请实施例不对自协商的时机进行限定。
在该保护处理方式二中，对填充数据采用的第三FEC码，可以与第二FEC码相同，也可以与第二FEC码不相同。数据流水线处理的过程中，如果剔除填充数据不进入第二FEC码的解码器，会导致第二FEC码的解码器出现“空拍”，即某个时钟周期没有需要处理的数据，不仅需要额外处理，还将浪费芯片性能。在本申请的一种可能的实现方式中，第三FEC码与第二FEC码相同的情况下，尽可能重用已经实现的第二FEC码的编码器和解码器。
无论第三FEC码与第二FEC码是否相同，如图6所示，以采用的第三FEC码为扩展汉明码(128，120)，填充数据的长度p＝128为例，经过保护处理的填充数据包括携带的120比特(bits)OAM信息和8比特校验位。8比特校验位可采用奇偶校验(parity)码。增加FEC保护后的填充数据，接收侧如果采用硬判决译码方式纠错，则可以纠正1个比特错误，从而将每一个填充数据的正确概率从56.1％提高到了88.6％。如果采用软判决方式译码纠错，则可以提高到98％以上。
保护处理方式三，保护处理包括增加CRC以及采用第三FEC码进行编码，填充数据为增加CRC保护以及采用第三FEC码进行编码的数据。
该保护处理方式三是上述保护处理方式一和保护处理方式二的组合，可应用在对携带的数据传输的相关信息有高可靠性要求的场景中，例如要求达到“首次误接受前平均工作时间”(也称为平均误包接受时间(mean time to false packet acceptance，MTTFPA))>1.3ⅹ109年的情况下，可能需要搭配多种保护处理方式对填充数据进行保护。
针对该保护处理方式三，需要按照先增加CRC，再采用第三FEC码进行编码的顺序。按照该顺序， CRC内容可以被FEC保护，如果CRC内容出错还能被纠正，进一步提高传输填充数据的可靠性和效率。例如，对填充数据先进行CRC保护，将CRC内容与OAM信息等填充数据一并进行FEC编码。在接收侧先进行FEC纠错、再进行CRC校验。
S304，第一模块传输第二数据。
本申请实施例不对第一模块向第二模块传输第二数据的方式进行限定，例如第一模块通过物理链路向第二模块传输第二数据。又例如，第一模块通过逻辑通道传输第二数据，该逻辑通道可以为物理编码子层(physical coding sublayer，PCS)通道或FEC通道。示例性地，如果逻辑通道的数量为一条，第一模块通过该一条通道传输第二数据。如果逻辑通道的数量为大于或等于2的正整数，第一模块可以对第二数据进行分发之后，通过多条逻辑通道发送该第二数据。
上述S301-S304是以第一模块执行该方法为例进行说明，接下来，以第二模块执行传输数据的过程为例，包括如下S305-S307。
S305，第二模块接收第二数据。
其中，第二数据包括第一编码结果和用于调整频点的填充数据，例如，该第二数据由第一模块在第一编码结果中插入用于调整频点的填充数据得到，填充数据携带数据传输的相关信息，且填充数据为经过保护处理的数据，第一编码结果基于第二FEC码对第一数据进行编码得到，第一数据为采用第一FEC码对第一参考数据进行编码得到。
本申请实施例不对第二模块接收第一模块传输的第二数据的方式进行限定，与第一模块向第二模块传输第二数据的方式对应即可。第二数据的获取方式可参考上述S301-S304的过程，此处不再赘述。
S306，第二模块从第二数据中获取第一编码结果和填充数据。
由于第二数据包括第一编码结果和填充数据，因而第二模块接收到第二数据后，可从第二数据中分别获取第一编码结果和填充数据。本申请实施例不对第二模块从第二数据中获取第一编码结果和填充数据的方式进行限定。
S307，第二模块按照第二FEC码对第一编码结果进行解码，得到第一数据，基于填充数据获取数据传输的相关信息。
关于第二模块按照第二FEC码对第一编码结果进行解码的方式，本申请实施例不进行限定，此外，第二模块获取到第一编码结果和填充数据后，可以先按照第二FEC码对第一编码结果进行解码，得到第一数据，再基于填充数据获取数据传输的相关信息。可选地，第二模块也可以先基于填充数据获取数据传输的相关信息，再按照第二FEC码对第一编码结果进行解码，得到第一数据，本申请实施例也不对第二模块获取第一数据和获取数据传输的相关信息的先后顺序进行限定。
基于填充数据获取数据传输的相关信息时，可以基于保护处理的方式来实现，针对不同的保护处理方式，包括但不限于如下三种数据传输的相关信息的获取方式。
获取方式一，保护处理包括增加CRC，填充数据为增加CRC保护的数据；第二模块基于填充数据获取数据传输的相关信息，包括：第二模块对填充数据进行CRC校验，在CRC校验通过后，获取数据传输的相关信息。
第二模块对填充数据进行CRC校验时，可以采用填充数据增加的CRC保护的长度来对填充数据进行CRC校验。如果CRC校验通过，则说明填充数据未出错，则获取数据传输的相关信息也是准确可靠的。在一种可能的实施方式中，第二模块对填充数据进行CRC校验时，如果CRC校验未通过，第二模块可以不获取数据传输的相关信息，或者通过其他途径获取到正确的数据传输的相关信息，本申请不对CRC校验未通过之后的处理过程进行限定。
获取方式二，保护处理包括采用第三FEC码进行编码，填充数据为采用第三FEC码进行编码的数据；第二模块基于填充数据获取数据传输的相关信息，包括：第二模块采用第三FEC码对填充数据进行解码，根据解码结果获取数据传输的相关信息。
针对获取方式二，由于第三FEC码可以是第一模块和第二模块协商确定的，因而第二模块可以确定对填充数据进行解码时采用该第三FEC码。第三FEC码可以为FEC码中的任一种类型，本申请实施例不对采用第三FEC码对填充数据进行解码的过程加以赘述。
获取方式三，保护处理包括增加CRC以及采用第三FEC码进行编码，填充数据为增加CRC保护以及采用第三FEC码进行编码的数据；第二模块基于填充数据获取数据传输的相关信息，包括：第二模块采用 第三FEC码对填充数据进行解码，对解码结果进行CRC校验，在CRC校验通过后，获取数据传输的相关信息。
该获取方式三可以理解为是上述S303中保护处理方式三的逆过程，可以先采用第三FEC码对填充数据进行解码，得到解码结果之后，再对解码结果进行CRC校验，如果CRC校验通过，获取数据传输的相关信息。可选地，如果采用第三FEC码对填充数据进行解码未成功，可以不再进行后续的CRC校验操作。
以上通过对填充数据增加CRC保护或者使用FEC编码保护或者二者结合的方式来提高填充数据在传输过程中的可靠性，除此之外，本申请实施例提供的方法还支持多次传输相同填充数据的方式，以使得接收端即第二模块能够根据多数判决(majority voting)的方式来确定是否收到正确的填充数据，由此获取到可靠的数据传输的相关信息。在一种可能的实现方式中，第一模块传输第二数据之后，还包括：第一模块获取至少一个第三数据，第三数据为采用第四FEC码对第二参考数据进行编码得到；对于至少一个第三数据中的任一第三数据，第一模块按照第五FEC码对任一第三数据进行编码，得到第二编码结果；获取第四数据，第四数据包括第二编码结果和填充数据；传输第四数据。
其中，获取第四数据时，可以按照在第二编码结果中插入填充数据的方式，得到第四数据。上述至少一个第三数据可以是一个，也可以是多个，本申请实施例不对第一模块获取到的第三数据的数量进行限定，如果第三数据的数量是多个，第一模块可以是在不同时间获取多个第三数据，也可以是同时获取到多个第三数据。关于第一模块获取第三数据的方式，本申请实施例也不进行限定，可参考S301中获取第一数据的方式。
此外，第一参考数据和第二参考数据可以相同，也可以不同。第四FEC码和第五FEC码可以与第一FEC码、第二FEC码或第三FEC码相同，也可以与第一FEC码、第二FEC码或第三FEC码不同。一个第三数据经过第五FEC码进行编码后，均可得到一个第二编码结果，在该第二编码结果中插入填充数据后，均可以得到一个第四数据。也就是说，第三数据与第四数据的数量可以相同。其中，在第二编码结果中插入的填充数据可以与在第一编码结果中插入的填充数据相同，也即是同样的填充数据会通过第二数据和第四数据被多次传输到第二模块。在第二编码结果中插入的填充数据也是经过保护处理的，该填充数据的获取方式可参考S303的相关描述，传输第四数据的方式，可以参考S304的相关描述，此处不再赘述。
相应地，第二模块接收至少一个第四数据，第四数据包括第二编码结果和填充数据，第二编码结果基于第五FEC码对第三数据进行编码得到，第三数据为采用第四FEC码对第二参考数据进行编码得到；第二模块从各个第四数据中获取第二编码结果和填充数据；按照第五FEC码对第二编码结果进行解码，得到第三数据。该情况下，第二模块基于填充数据获取数据传输的相关信息，包括：第二模块将从各个第四数据中获取的填充数据与从第二数据中获取的填充数据进行比对，在根据比对结果确定相同填充数据的数量达到阈值的情况下，第二模块基于填充数据获取数据传输的相关信息。
本申请实施例不对相同填充数据的数量所达到的阈值进行限定，该阈值可以基于经验设置，也可以基于应用场景灵活设置，还可以基于填充数据的发送次数确定。例如，第一模块连续发送三次相同的填充数据，第二模块确定是否有两次填充数据相同，如果有两次填充数据相同，则获取数据传输的相关信息。如果没有任何两次填充数据是相同的，则丢弃接收到的填充数据。
在一种可能的实现方式中，对于较长的填充数据，在较高误码率下由于频繁出错，并且错误位置不一致，可能导致判据无法收敛，导致长时间无法接收成功。为此，本申请实施例提供的方法支持将较长的填充数据切分为较小的数据块，通过比对数据块的方式来实现填充数据的比对过程，提高比对效率。示例性地，第二模块将从各个第四数据中获取的填充数据与从第二数据中获取的填充数据进行比对，包括：第二模块将从各个第四数据中获取的填充数据与从第二数据中获取的填充数据分别进行切分，将切分得到的数据块进行比对。本申请实施例不对第二模块对填充数据进行切分的粒度进行限定，例如可以按字节切分，以每个字节为单位逐字节进行比对。
综上所述，本申请实施例提供的技术方案，在采用级联编码且需要插入填充数据的情况下，通过对填充数据进行保护处理，从而可以提高传输填充数据的可靠性和效率，进而提高了利用填充数据携带数据传输的相关信息的可靠性。此外，对填充数据的保护处理方式多种多样，提高了对填充数据进行保护的灵活性，适应性更强。再有，本申请实施例中对填充数据进行FEC编码采用的FEC码与级联编码中的内码也即第二FEC码相同，可以避免浪费芯片性能。通过将填充数据的长度设为第二FEC码长度的整数倍，可以便于第二FEC码的边界固定。
本申请实施例还提供了一种传输数据的装置，图7是本申请实施例提供的一种传输数据的装置的结构示意图，基于图7所示的多个模块，图7所示的传输数据的装置能够执行上述图3所示的方法实施例中第一模块所执行的全部或部分操作。应理解到，该装置可以包括比所示模块更多的附加模块或者省略其中所示的一部分模块，本申请实施例对此并不进行限制。如图7所示，该装置包括：
第一获取模块701，用于获取第一数据，第一数据为采用第一FEC码对第一参考数据进行编码得到；
编码模块702，用于按照第二FEC码对第一数据进行编码，得到第一编码结果；
第二获取模块703，用于获取第二数据，第二数据包括第一编码结果和用于调整频点的填充数据，填充数据携带数据传输的相关信息，且填充数据为经过保护处理的数据；
传输模块704，用于传输第二数据。
在一种可能的实现方式中，保护处理包括增加CRC，填充数据为增加CRC保护的数据。
在一种可能的实现方式中，保护处理包括采用第三FEC码进行编码，填充数据为采用第三FEC码进行编码的数据。
在一种可能的实现方式中，保护处理包括增加CRC以及采用第三FEC码进行编码，填充数据为增加CRC保护以及采用第三FEC码进行编码的数据。
在一种可能的实现方式中，第三FEC码与第二FEC码相同。
在一种可能的实现方式中，填充数据的长度为第二FEC码长度的整数倍。
在一种可能的实现方式中，第二获取模块703，用于按照参考密度在第一编码结果中插入用于调整频点的填充数据，得到第二数据，参考密度基于第一FEC码和第二FEC码的开销比例以及按照第二FEC码对第一数据进行编码时使用的晶体振荡器的频率确定。
在一种可能的实现方式中，第一获取模块701，还用于获取至少一个第三数据，第三数据采用第四FEC码对第二参考数据进行编码得到；编码模块702，还用于对于至少一个第三数据中的任一第三数据，按照第五FEC码对任一第三数据进行编码，得到第二编码结果；第二获取模块703，还用于获取第四数据，第四数据包括第二编码结果和填充数据；传输模块704，还用于传输第四数据。
本申请实施例还提供了一种传输数据的装置，图8是本申请实施例提供的一种传输数据的装置的结构示意图，基于图8所示的多个模块，图8所示的传输数据的装置能够执行上述图3所示的方法实施例中第二模块所执行的全部或部分操作。应理解到，该装置可以包括比所示模块更多的附加模块或者省略其中所示的一部分模块，本申请实施例对此并不进行限制。如图8所示，该装置包括：
接收模块801，用于接收第二数据，第二数据包括第一编码结果和用于调整频点的填充数据，填充数据携带数据传输的相关信息，且填充数据为经过保护处理的数据，第一编码结果基于第二FEC码对第一数据进行编码得到，第一数据为采用第一FEC码对第一参考数据进行编码得到；
第一获取模块802，用于从第二数据中获取第一编码结果和填充数据；
解码模块803，用于按照第二FEC码对第一编码结果进行解码，得到第一数据；
第二获取模块804，用于基于填充数据获取数据传输的相关信息。
在一种可能的实现方式中，保护处理包括增加CRC，填充数据为增加CRC保护的数据；第二获取模块804，用于对填充数据进行CRC校验，在CRC校验通过后，获取数据传输的相关信息。
在一种可能的实现方式中，保护处理包括采用第三FEC码进行编码，填充数据为采用第三FEC码进行编码的数据；第二获取模块804，用于采用第三FEC码对填充数据进行解码，根据解码结果获取数据传输的相关信息。
在一种可能的实现方式中，保护处理包括增加循环冗余校验CRC以及采用第三FEC码进行编码，填充数据为增加CRC保护以及采用第三FEC码进行编码的数据；第二获取模块804，用于采用第三FEC码对填充数据进行解码，对解码结果进行CRC校验，在CRC校验通过后，获取数据传输的相关信息。
在一种可能的实现方式中，第三FEC码与第二FEC码相同。
在一种可能的实现方式中，填充数据的长度为第二FEC码长度的整数倍。
在一种可能的实现方式中，接收模块801，还用于接收至少一个第四数据，第四数据包括第二编码结果和填充数据，第二编码结果基于第五FEC码对第三数据进行编码得到，第三数据为采用第四FEC码对 第二参考数据进行编码得到；第一获取模块802，还用于从各个第四数据中获取第二编码结果和填充数据；解码模块803，还用于按照第五FEC码对第二编码结果进行解码，得到第三数据；第二获取模块804，用于将从各个第四数据中获取的填充数据与从第二数据中获取的填充数据进行比对，在根据比对结果确定相同填充数据的数量达到阈值的情况下，基于填充数据获取数据传输的相关信息。
在一种可能的实现方式中，第二获取模块804，用于将从各个第四数据中获取的填充数据与从第二数据中获取的填充数据分别进行切分，将切分得到的数据块进行比对。
应理解的是，上述图7-图8提供的装置在实现其功能时，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将设备的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述实施例提供的装置与方法实施例属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。
本申请实施例提供一种通信设备，该通信设备的硬件结构如图9所示的通信设备1500，包括收发器1501、处理器1502和存储器1503。收发器1501、处理器1502和存储器1503之间通过总线1504连接。其中，收发器1501用于接收报文和发送报文，存储器1503用于存放指令或程序代码，处理器1502用于调用存储器1503中的指令或程序代码使得设备执行上述方法实施例中第一模块或第二模块的相关处理步骤。在具体实施例中，本申请实施例的通信设备1500可对应于上述各个方法实施例中的第一模块或第二模块，通信设备1500中的处理器1502读取存储器1503中的指令或程序代码，使图9所示的通信设备1500能够执行第一模块或第二模块所执行的全部或部分操作。
通信设备1500还可以对应于上述图7或图8所示的装置，例如，图7和图8中所涉及的传输模块704、接收模块801相当于收发器1501，第一获取模块701、编码模块702、第二获取模块703、第一获取模块802、解码模块803、第二获取模块804相当于处理器1502。
参见图10，图10示出了本申请一个示例性实施例提供的通信设备2000的结构示意图。图10所示的通信设备2000用于执行上述图3所示的传输数据的方法所涉及的操作。该通信设备2000例如是交换机、路由器等。
如图10所示，通信设备2000包括至少一个处理器2001、存储器2003以及至少一个通信接口2004。
处理器2001例如是通用中央处理器(central processing unit，CPU)、数字信号处理器(digital signal processor，DSP)、网络处理器(network processer，NP)、图形处理器(Graphics Processing Unit，GPU)、神经网络处理器(neural-network processing units，NPU)、数据处理单元(Data Processing Unit，DPU)、微处理器或者一个或多个用于实现本申请方案的集成电路。例如，处理器2001包括专用集成电路(application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。PLD例如是复杂可编程逻辑器件(complex programmable logic device，CPLD)、现场可编程逻辑门阵列(field-programmable gate array，FPGA)、通用阵列逻辑(generic array logic，GAL)或其任意组合。其可以实现或执行结合本发明实施例公开内容所描述的各种逻辑方框、模块和电路。所述处理器也可以是实现计算功能的组合，例如包括一个或多个微处理器组合，DSP和微处理器的组合等等。
可选的，通信设备2000还包括总线。总线用于在通信设备2000的各组件之间传送信息。总线可以是外设部件互连标准(peripheral component interconnect，简称PCI)总线或扩展工业标准结构(extended industry standard architecture，简称EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，图10中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。图10中通信设备2000的各组件之间除了采用总线连接，还可采用其他方式连接，本发明实施例不对各组件的连接方式进行限定。
存储器2003例如是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其它类型的静态存储设备，又如是随机存取存储器(random access memory，RAM)或者可存储信息和指令的其它类型的动态存储设备，又如是电可擦可编程只读存储器(electrically erasable programmable read-only Memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其它光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其它磁存储设备，或者是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其它介质，但不限于此。存储器2003例如是独立存在，并通过总线与处理器2001相连接。存储器2003也可以和处理器2001集成 在一起。
通信接口2004使用任何收发器一类的装置，用于与其它设备或通信网络通信，通信网络可以为以太网、无线接入网(RAN)或无线局域网(wireless local area networks，WLAN)等。通信接口2004可以包括有线通信接口，还可以包括无线通信接口。具体的，通信接口2004可以为以太(Ethernet)接口、快速以太(Fast Ethernet，FE)接口、千兆以太(Gigabit Ethernet，GE)接口，异步传输模式(Asynchronous Transfer Mode，ATM)接口，无线局域网(wireless local area networks，WLAN)接口，蜂窝网络通信接口或其组合。以太网接口可以是光接口，电接口或其组合。在本申请实施例中，通信接口2004可以用于通信设备2000与其他设备进行通信。
在具体实现中，作为一种实施例，处理器2001可以包括一个或多个CPU，如图10中所示的CPU0和CPU1。这些处理器中的每一个可以是一个单核(single-CPU)处理器，也可以是一个多核(multi-CPU)处理器。这里的处理器可以指一个或多个设备、电路、和/或用于处理数据(例如计算机程序指令)的处理核。
在具体实现中，作为一种实施例，通信设备2000可以包括多个处理器，如图10中所示的处理器2001和处理器2005。这些处理器中的每一个可以是一个单核处理器(single-CPU)，也可以是一个多核处理器(multi-CPU)。这里的处理器可以指一个或多个设备、电路、和/或用于处理数据(如计算机程序指令)的处理核。
在具体实现中，作为一种实施例，通信设备2000还可以包括输出设备和输入设备。输出设备和处理器2001通信，可以以多种方式来显示信息。例如，输出设备可以是液晶显示器(liquid crystal display，LCD)、发光二级管(light emitting diode，LED)显示设备、阴极射线管(cathode ray tube，CRT)显示设备或投影仪(projector)等。输入设备和处理器2001通信，可以以多种方式接收用户的输入。例如，输入设备可以是鼠标、键盘、触摸屏设备或传感设备等。
在一些实施例中，存储器2003用于存储执行本申请方案的程序代码2010，处理器2001可以执行存储器2003中存储的程序代码2010。也即是，通信设备2000可以通过处理器2001以及存储器2003中的程序代码2010，来实现方法实施例提供的报文方法。程序代码2010中可以包括一个或多个软件模块。可选地，处理器2001自身也可以存储执行本申请方案的程序代码或指令。
在具体实施例中，本申请实施例的通信设备2000可对应于上述各个方法实施例中的第一模块或第二模块，通信设备2000中的处理器2001读取存储器2003中的程序代码2010或处理器2001自身存储的程序代码或指令，使图10所示的通信设备2000能够执行第一模块或第二模块所执行的全部或部分操作。
通信设备2000还可以对应于上述图7或图8所示的装置，图7或图8所示的装置中的每个功能模块采用通信设备2000的软件实现。换句话说，图7或图8所示的装置包括的功能模块为通信设备2000的处理器2001读取存储器2003中存储的程序代码2010后生成的。例如，图7或图8中所涉及的传输模块704、接收模块801相当于通信接口2004，第一获取模块701、编码模块702、第二获取模块703、第一获取模块802、解码模块803、第二获取模块804相当于处理器2001和/或处理器2005。
其中，图3所示的方法的各步骤通过通信设备2000的处理器中的硬件的集成逻辑电路或者软件形式的指令完成。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤，为避免重复，这里不再详细描述。
参见图11，图11示出了本申请另一个示例性实施例提供的通信设备2100的结构示意图。图11所示的通信设备2100用于执行上述图3所示的方法所涉及的全部或部分操作。该通信设备2100例如是交换机、路由器等，该通信设备2100可以由一般性的总线体系结构来实现。
如图11所示，通信设备2100包括：主控板2110和接口板2130。
主控板也称为主处理单元(main processing unit，MPU)或路由处理卡(route processor card)，主控板2110用于对通信设备2100中各个组件的控制和管理，包括路由计算、设备管理、设备维护、协议处理功能。主控板2110包括：中央处理器2111和存储器2112。
接口板2130也称为线路接口单元卡(line processing unit，LPU)、线卡(line card)或业务板。接口板2130用于提供各种业务接口并实现数据包的转发。业务接口包括而不限于以太网接口、POS(Packet over SONET/SDH)接口等，以太网接口例如是灵活以太网业务接口(Flexible Ethernet Clients，FlexE Clients)。接 口板2130包括：中央处理器2131网络处理器2132、转发表项存储器2134和物理接口卡(ph10sical interface card，PIC)2133。
接口板2130上的中央处理器2131用于对接口板2130进行控制管理并与主控板2110上的中央处理器2111进行通信。
网络处理器2132用于实现报文的发送处理。网络处理器2132的形态可以是转发芯片。转发芯片可以是网络处理器(network processor，NP)。在一些实施例中，转发芯片可以通过专用集成电路(application-specific integrated circuit，ASIC)或现场可编程门阵列(field programmable gate array，FPGA)实现。具体而言，网络处理器2132用于基于转发表项存储器2134保存的转发表转发接收到的报文，如果报文的目的地址为通信设备2100的地址，则将该报文上送至CPU(如中央处理器2131)处理；如果报文的目的地址不是通信设备2100的地址，则根据该目的地址从转发表中查找到该目的地址对应的下一跳和出接口，将该报文转发到该目的地址对应的出接口。其中，上行报文的处理可以包括：报文入接口的处理，转发表查找；下行报文的处理可以包括：转发表查找等等。在一些实施例中，中央处理器也可执行转发芯片的功能，比如基于通用CPU实现软件转发，从而接口板中不需要转发芯片。
物理接口卡2133用于实现物理层的对接功能，原始的流量由此进入接口板2130，以及处理后的报文从该物理接口卡2133发出。物理接口卡2133也称为子卡，可安装在接口板2130上，负责将光电信号转换为报文并对报文进行合法性检查后转发给网络处理器2132处理。在一些实施例中，中央处理器2131也可执行网络处理器2132的功能，比如基于通用CPU实现软件转发，从而物理接口卡2133中不需要网络处理器2132。
可选地，通信设备2100包括多个接口板，例如通信设备2100还包括接口板2140，接口板2140包括：中央处理器2141、网络处理器2142、转发表项存储器2144和物理接口卡2143。接口板2140中各部件的功能和实现方式与接口板2130相同或相似，在此不再赘述。
可选地，通信设备2100还包括交换网板2120。交换网板2120也可以称为交换网板单元(switch fabric unit，SFU)。在通信设备有多个接口板的情况下，交换网板2120用于完成各接口板之间的数据交换。例如，接口板2130和接口板2140之间可以通过交换网板2120通信。
主控板2110和接口板耦合。例如。主控板2110、接口板2130和接口板2140，以及交换网板2120之间通过系统总线与系统背板相连实现互通。在一种可能的实现方式中，主控板2110和接口板2130及接口板2140之间建立进程间通信协议(inter-process communication，IPC)通道，主控板2110和接口板2130及接口板2140之间通过IPC通道进行通信。
在逻辑上，通信设备2100包括控制面和转发面，控制面包括主控板2110和中央处理器2111，转发面包括执行转发的各个组件，比如转发表项存储器2134、物理接口卡2133和网络处理器2132。控制面执行路由器、生成转发表、处理信令和协议报文、配置与维护通信设备的状态等功能，控制面将生成的转发表下发给转发面，在转发面，网络处理器2132基于控制面下发的转发表对物理接口卡2133收到的报文查表转发。控制面下发的转发表可以保存在转发表项存储器2134中。在有些实施例中，控制面和转发面可以完全分离，不在同一通信设备上。
值得说明的是，主控板可能有一块或多块，有多块的时候可以包括主用主控板和备用主控板。接口板可能有一块或多块，通信设备的数据处理能力越强，提供的接口板越多。接口板上的物理接口卡也可以有一块或多块。交换网板可能没有，也可能有一块或多块，有多块的时候可以共同实现负荷分担冗余备份。在集中式转发架构下，通信设备可以不需要交换网板，接口板承担整个系统的业务数据的处理功能。在分布式转发架构下，通信设备可以有至少一块交换网板，通过交换网板实现多块接口板之间的数据交换，提供大容量的数据交换和处理能力。所以，分布式架构的通信设备的数据接入和处理能力要大于集中式架构的通信设备。可选地，通信设备的形态也可以是只有一块板卡，即没有交换网板，接口板和主控板的功能集成在该一块板卡上，此时接口板上的中央处理器和主控板上的中央处理器在该一块板卡上可以合并为一个中央处理器，执行两者叠加后的功能，这种形态通信设备的数据交换和处理能力较低(例如，低端交换机或路由器等通信设备)。具体采用哪种架构，取决于具体的组网部署场景，此处不做任何限定。
在具体实施例中，通信设备2100对应于上述图7和图8所示的装置。在一些实施例中，图7-图8所示的装置中的传输模块704、接收模块801相当于通信设备2100中的物理接口卡2133或物理接口卡2143。图7或图8所示的装置中的第一获取模块701、编码模块702、第二获取模块703、第一获取模块802、解 码模块803、第二获取模块804相当于通信设备2100中的中央处理器2111、网络处理器2132和网络处理器2142中的至少一个。
本申请实施例还提供了一种网络设备，网络设备包括：处理器，处理器与存储器耦合，存储器中存储有至少一条程序指令或代码，至少一条程序指令或代码由处理器加载并执行，以使网络设备实现上述任一的传输数据的方法。
本申请实施例还提供了一种传输数据的系统，该系统包括：第一模块和第二模块，第一模块和第二模块所执行的方法可参见上述图3所示实施例的相关描述，此处不再加以赘述。
本申请实施例还提供了一种传输数据的系统，该系统包括：图7所示的装置和图8所示的装置。
本申请实施例还提供了一种传输数据的系统，该系统包括：第一设备及第二设备。可选的，第一设备为图9所示的通信设备1500或图10所示的通信设备2000或图11所示的通信设备2100，第二设备为图9所示的通信设备1500或图10所示的通信设备2000或图11所示的通信设备2100。
第一设备及第二设备所执行的方法可参见上述图3所示实施例的相关描述，此处不再加以赘述。
应理解的是，上述处理器可以是中央处理器(Central Processing Unit，CPU)，还可以是其他通用处理器、数字信号处理器(digital signal processing，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field－programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者是任何常规的处理器等。值得说明的是，处理器可以是支持进阶精简指令集机器(advanced RISC machines，ARM)架构的处理器。
进一步地，在一种可选的实施例中，上述存储器可以包括只读存储器和随机存取存储器，并向处理器提供指令和数据。存储器还可以包括非易失性随机存取存储器。例如，存储器还可以存储设备类型的信息。
该存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用。例如，静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic random access memory，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。
还提供了一种计算机可读存储介质，存储介质中存储有至少一条程序指令或代码，所述程序指令或代码由处理器加载并执行以使计算机实现如上图3中任一所述的传输数据的方法。
本申请提供了一种计算机程序(产品)，当计算机程序被计算机执行时，可以使得处理器或计算机执行上述方法实施例中对应的各个步骤和/或流程。
提供了一种芯片，包括处理器，用于从存储器中调用并运行所述存储器中存储的指令，使得安装有所述芯片的通信设备执行上述各方面中的方法。
提供另一种芯片，包括：输入接口、输出接口、处理器和存储器，所述输入接口、输出接口、所述处理器以及所述存储器之间通过内部连接通路相连，所述处理器用于执行所述存储器中的代码，当所述代码被执行时，处理器用于执行上述各方面中的方法。
还提供了一种通信设备，该设备包括上述芯片。示例性地，该设备为路由器或交换机或服务器。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线)或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例 如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk)等。
以上所述的具体实施方式，对本申请的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本申请的具体实施方式而已，并不用于限定本申请的保护范围，凡在本申请的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本申请的保护范围之内。
本领域普通技术人员可以意识到，结合本文中所公开的实施例中描述的各方法步骤和模块，能够以软件、硬件、固件或者其任意组合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各实施例的步骤及组成。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。本领域普通技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，该程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。该计算机程序产品包括一个或多个计算机程序指令。作为示例，本申请实施例的方法可以在机器可执行指令的上下文中被描述，机器可执行指令诸如包括在目标的真实或者虚拟处理器上的器件中执行的程序模块中。一般而言，程序模块包括例程、程序、库、对象、类、组件、数据结构等，其执行特定的任务或者实现特定的抽象数据结构。在各实施例中，程序模块的功能可以在所描述的程序模块之间合并或者分割。用于程序模块的机器可执行指令可以在本地或者分布式设备内执行。在分布式设备中，程序模块可以位于本地和远程存储介质二者中。
用于实现本申请实施例的方法的计算机程序代码可以用一种或多种编程语言编写。这些计算机程序代码可以提供给通用计算机、专用计算机或其他可编程的数据处理装置的处理器，使得程序代码在被计算机或其他可编程的数据处理装置执行的时候，引起在流程图和/或框图中规定的功能/操作被实施。程序代码可以完全在计算机上、部分在计算机上、作为独立的软件包、部分在计算机上且部分在远程计算机上或完全在远程计算机或服务器上执行。
在本申请实施例的上下文中，计算机程序代码或者相关数据可以由任意适当载体承载，以使得设备、装置或者处理器能够执行上文描述的各种处理和操作。载体的示例包括信号、计算机可读介质等等。
信号的示例可以包括电、光、无线电、声音或其它形式的传播信号，诸如载波、红外信号等。
机器可读介质可以是包含或存储用于或有关于指令执行系统、装置或设备的程序的任何有形介质。机器可读介质可以是机器可读信号介质或机器可读存储介质。机器可读介质可以包括但不限于电子的、磁的、光学的、电磁的、红外的或半导体系统、装置或设备，或其任意合适的组合。机器可读存储介质的更详细示例包括带有一根或多根导线的电气连接、便携式计算机磁盘、硬盘、随机存储存取器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM或闪存)、光存储设备、磁存储设备，或其任意合适的组合。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、设备和模块的具体工作过程，可以参见前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，该模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、设备或模块的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
该作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本申请实施例方案的目的。
另外，在本申请各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以是两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
该集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分，或者 该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例中方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
本申请中术语“第一”“第二”等字样用于对作用和功能基本相同的相同项或相似项进行区分，应理解，“第一”、“第二”、“第n”之间不具有逻辑或时序上的依赖关系，也不对数量和执行顺序进行限定。还应理解，尽管以下描述使用术语第一、第二等来描述各种元素，但这些元素不应受术语的限制。这些术语只是用于将一元素与另一元素区别分开。例如，在不脱离各种所述示例的范围的情况下，第一网络设备可以被称为第二网络设备，并且类似地，第二网络设备可以被称为第一网络设备。第一网络设备和第二网络设备都可以是任一类型的网络设备，并且在某些情况下，可以是单独且不同的网络设备。
还应理解，在本申请的各个实施例中，各个过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本申请中术语“至少一个”的含义是指一个或多个，本申请中术语“多个”的含义是指两个或两个以上，例如，多个第二报文是指两个或两个以上的第二报文。本文中术语“系统”和“网络”经常可互换使用。
应理解，在本文中对各种所述示例的描述中所使用的术语只是为了描述特定示例，而并非旨在进行限制。如在对各种所述示例的描述和所附权利要求书中所使用的那样，单数形式“一个(“a”，“an”)”和“该”旨在也包括复数形式，除非上下文另外明确地指示。
还应理解，术语“包括”(也称“includes”、“including”、“comprises”和/或“comprising”)当在本说明书中使用时指定存在所陈述的特征、整数、步骤、操作、元素、和/或部件，但是并不排除存在或添加一个或多个其他特征、整数、步骤、操作、元素、部件、和/或其分组。
还应理解，术语“若”和“如果”可被解释为意指“当...时”(“when”或“upon”)或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“若确定...”或“若检测到[所陈述的条件或事件]”可被解释为意指“在确定...时”或“响应于确定...”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
还应理解，说明书通篇中提到的“一个实施例”、“一实施例”、“一种可能的实现方式”意味着与实施例或实现方式有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”、“一种可能的实现方式”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。

Claims (37)

  1. 一种传输数据的方法，其特征在于，所述方法包括：
    获取第一数据，所述第一数据为采用第一前向纠错FEC码对第一参考数据进行编码得到；
    按照第二FEC码对所述第一数据进行编码，得到第一编码结果；
    获取第二数据，所述第二数据包括所述第一编码结果和用于调整频点的填充数据，所述填充数据携带数据传输的相关信息，且所述填充数据为经过保护处理的数据；
    传输所述第二数据。
  2. 根据权利要求1所述的方法，其特征在于，所述保护处理包括增加循环冗余校验CRC，所述填充数据为增加所述CRC保护的数据。
  3. 根据权利要求1所述的方法，其特征在于，所述保护处理包括采用第三FEC码进行编码，所述填充数据为采用所述第三FEC码进行编码的数据。
  4. 根据权利要求1所述的方法，其特征在于，所述保护处理包括增加循环冗余校验CRC以及采用第三FEC码进行编码，所述填充数据为增加所述CRC保护以及采用所述第三FEC码进行编码的数据。
  5. 根据权利要求3或4所述的方法，其特征在于，所述第三FEC码与所述第二FEC码相同。
  6. 根据权利要求1-5任一所述的方法，其特征在于，所述填充数据的长度为所述第二FEC码长度的整数倍。
  7. 根据权利要求1-6任一所述的方法，其特征在于，所述获取第二数据，包括：
    按照参考密度在所述第一编码结果中插入用于调整频点的填充数据，得到所述第二数据，所述参考密度基于所述第一FEC码和所述第二FEC码的开销比例以及按照所述第二FEC码对所述第一数据进行编码时使用的晶体振荡器的频率确定。
  8. 根据权利要求1-7任一所述的方法，其特征在于，所述传输所述第二数据之后，所述方法还包括：
    获取至少一个第三数据，所述第三数据为采用第四FEC码对第二参考数据进行编码得到；
    对于所述至少一个第三数据中的任一第三数据，按照第五FEC码对所述任一第三数据进行编码，得到第二编码结果；
    获取第四数据，所述第四数据包括所述第二编码结果和所述填充数据；
    传输所述第四数据。
  9. 一种传输数据的方法，其特征在于，所述方法包括：
    接收第二数据，所述第二数据包括第一编码结果和用于调整频点的填充数据，所述填充数据携带数据传输的相关信息，且所述填充数据为经过保护处理的数据，所述第一编码结果基于第二前向纠错码FEC码对第一数据进行编码得到，所述第一数据为采用第一FEC码对第一参考数据进行编码得到；
    从所述第二数据中获取所述第一编码结果和所述填充数据；
    按照所述第二FEC码对所述第一编码结果进行解码，得到所述第一数据；
    基于所述填充数据获取所述数据传输的相关信息。
  10. 根据权利要求9所述的方法，其特征在于，所述保护处理包括增加循环冗余校验CRC，所述填充数据为增加所述CRC保护的数据；
    所述基于所述填充数据获取所述数据传输的相关信息，包括：
    对所述填充数据进行所述CRC校验，在所述CRC校验通过后，获取所述数据传输的相关信息。
  11. 根据权利要求9所述的方法，其特征在于，所述保护处理包括采用第三FEC码进行编码，所述填充数据为采用所述第三FEC码进行编码的数据；
    所述基于所述填充数据获取所述数据传输的相关信息，包括：
    采用所述第三FEC码对所述填充数据进行解码，根据解码结果获取所述数据传输的相关信息。
  12. 根据权利要求9所述的方法，其特征在于，所述保护处理包括增加循环冗余校验CRC以及采用第三FEC码进行编码，所述填充数据为增加所述CRC保护以及采用所述第三FEC码进行编码的数据；
    所述基于所述填充数据获取所述数据传输的相关信息，包括：
    采用第三FEC码对所述填充数据进行解码，对解码结果进行所述CRC校验，在所述CRC校验通过后，获取所述数据传输的相关信息。
  13. 根据权利要求11或12所述的方法，其特征在于，所述第三FEC码与所述第二FEC码相同。
  14. 根据权利要求9-13任一所述的方法，其特征在于，所述填充数据的长度为所述第二FEC码长度的整数倍。
  15. 根据权利要求9-14任一所述的方法，其特征在于，所述方法还包括：
    接收至少一个第四数据，所述第四数据包括第二编码结果和填充数据，所述第二编码结果基于第五FEC码对第三数据进行编码得到，所述第三数据为采用第四FEC码对第二参考数据进行编码得到；
    从各个第四数据中获取所述第二编码结果和所述填充数据；按照所述第五FEC码对所述第二编码结果进行解码，得到所述第三数据；
    所述基于所述填充数据获取所述数据传输的相关信息，包括：
    将从所述各个第四数据中获取的填充数据与从所述第二数据中获取的填充数据进行比对，在根据比对结果确定相同填充数据的数量达到阈值的情况下，基于所述填充数据获取所述数据传输的相关信息。
  16. 根据权利要求15所述的方法，其特征在于，所述将从所述各个第四数据中获取的填充数据与从所述第二数据中获取的填充数据进行比对，包括：
    将从所述各个第四数据中获取的填充数据与从所述第二数据中获取的填充数据分别进行切分，将切分得到的数据块进行比对。
  17. 一种传输数据的装置，其特征在于，所述装置包括：
    第一获取模块，用于获取第一数据，所述第一数据为采用第一前向纠错FEC码对第一参考数据进行编码得到；
    编码模块，用于按照第二FEC码对所述第一数据进行编码，得到第一编码结果；
    第二获取模块，用于获取第二数据，所述第二数据包括所述第一编码结果和用于调整频点的填充数据，所述填充数据携带数据传输的相关信息，且所述填充数据为经过保护处理的数据；
    传输模块，用于传输所述第二数据。
  18. 根据权利要求17所述的装置，其特征在于，所述保护处理包括增加循环冗余校验CRC，所述填充数据为增加所述CRC保护的数据。
  19. 根据权利要求17所述的装置，其特征在于，所述保护处理包括采用第三FEC码进行编码，所述填充数据为采用所述第三FEC码进行编码的数据。
  20. 根据权利要求17所述的装置，其特征在于，所述保护处理包括增加循环冗余校验CRC以及采用第三 FEC码进行编码，所述填充数据为增加所述CRC保护以及采用所述第三FEC码进行编码的数据。
  21. 根据权利要求19或20所述的装置，其特征在于，所述第三FEC码与所述第二FEC码相同。
  22. 根据权利要求17-21任一所述的装置，其特征在于，所述填充数据的长度为所述第二FEC码长度的整数倍。
  23. 根据权利要求17-22任一所述的装置，其特征在于，所述第二获取模块，用于按照参考密度在所述第一编码结果中插入用于调整频点的填充数据，得到所述第二数据，所述参考密度基于所述第一FEC码和所述第二FEC码的开销比例以及按照所述第二FEC码对所述第一数据进行编码时使用的晶体振荡器的频率确定。
  24. 根据权利要求17-23任一所述的装置，其特征在于，所述第一获取模块，还用于获取至少一个第三数据，所述第三数据为采用第四FEC码对第二参考数据进行编码得到；
    所述编码模块，还用于对于所述至少一个第三数据中的任一第三数据，按照第五FEC码对所述任一第三数据进行编码，得到第二编码结果；
    所述第二获取模块，还用于获取第四数据，所述第四数据包括所述第二编码结果和所述填充数据；
    所述传输模块，还用于传输所述第四数据。
  25. 一种传输数据的装置，其特征在于，所述装置包括：
    接收模块，用于接收第二数据，所述第二数据包括第一编码结果和用于调整频点的填充数据，所述填充数据携带数据传输的相关信息，且所述填充数据为经过保护处理的数据，所述第一编码结果基于第二前向纠错码FEC码对第一数据进行编码得到，所述第一数据为采用第一FEC码对第一参考数据进行编码得到；
    第一获取模块，用于从所述第二数据中获取所述第一编码结果和所述填充数据；
    解码模块，用于按照所述第二FEC码对所述第一编码结果进行解码，得到所述第一数据；
    第二获取模块，用于基于所述填充数据获取所述数据传输的相关信息。
  26. 根据权利要求25所述的装置，其特征在于，所述保护处理包括增加循环冗余校验CRC，所述填充数据为增加所述CRC保护的数据；
    所述第二获取模块，用于对所述填充数据进行所述CRC校验，在所述CRC校验通过后，获取所述数据传输的相关信息。
  27. 根据权利要求25所述的装置，其特征在于，所述保护处理包括采用第三FEC码进行编码，所述填充数据为采用所述第三FEC码进行编码的数据；
    所述第二获取模块，用于采用所述第三FEC码对所述填充数据进行解码，根据解码结果获取所述数据传输的相关信息。
  28. 根据权利要求25所述的装置，其特征在于，所述保护处理包括增加循环冗余校验CRC以及采用第三FEC码进行编码，所述填充数据为增加所述CRC保护以及采用所述第三FEC码进行编码的数据；
    所述第二获取模块，用于采用第三FEC码对所述填充数据进行解码，对解码结果进行所述CRC校验，在所述CRC校验通过后，获取所述数据传输的相关信息。
  29. 根据权利要求27或28所述的装置，其特征在于，所述第三FEC码与所述第二FEC码相同。
  30. 根据权利要求25-29任一所述的装置，其特征在于，所述填充数据的长度为所述第二FEC码长度的整数倍。
  31. 根据权利要求25-30任一所述的装置，其特征在于，所述接收模块，还用于接收至少一个第四数据，所述第四数据包括第二编码结果和填充数据，所述第二编码结果基于第五FEC码对第三数据进行编码得到，所述第三数据采用第四FEC码对第二参考数据进行编码得到；
    所述第一获取模块，还用于从各个第四数据中获取所述第二编码结果和所述填充数据；
    所述解码模块，还用于按照所述第五FEC码对所述第二编码结果进行解码，得到所述第三数据；
    所述第二获取模块，用于将从所述各个第四数据中获取的填充数据与从所述第二数据中获取的填充数据进行比对，在根据比对结果确定相同填充数据的数量达到阈值的情况下，基于所述填充数据获取所述数据传输的相关信息。
  32. 根据权利要求31所述的装置，其特征在于，所述第二获取模块，用于将从所述各个第四数据中获取的填充数据与从所述第二数据中获取的填充数据分别进行切分，将切分得到的数据块进行比对。
  33. 一种网络设备，其特征在于，所述网络设备包括：处理器，所述处理器与存储器耦合，所述存储器中存储有至少一条程序指令或代码，所述至少一条程序指令或代码由所述处理器加载并执行，以使所述网络设备实现权利要求1-16中任一所述的方法。
  34. 一种数据传输系统，其特征在于，所述系统包括第一模块和第二模块，所述第一模块用于执行权利要求1-8中任一所述的方法，所述第二模块用于执行权利要求9-16中任一所述的方法。
  35. 一种计算机可读存储介质，其特征在于，所述存储介质中存储有至少一条程序指令或代码，所述程序指令或代码由处理器加载并执行以使计算机实现如权利要求1-16中任一所述的方法。
  36. 一种芯片，其特征在于，所述芯片包括处理器，所述处理器用于实现权利要求1-16中任一所述的方法。
  37. 一种通信设备，其特征在于，所述通信设备包括至少一个权利要求36所述的芯片。
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