WO2024149238A1 - 一种数据编解码方法及相关装置 - Google Patents

一种数据编解码方法及相关装置 Download PDF

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Publication number
WO2024149238A1
WO2024149238A1 PCT/CN2024/071323 CN2024071323W WO2024149238A1 WO 2024149238 A1 WO2024149238 A1 WO 2024149238A1 CN 2024071323 W CN2024071323 W CN 2024071323W WO 2024149238 A1 WO2024149238 A1 WO 2024149238A1
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information
value
probability
bit
symbol
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French (fr)
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康宁
张世枫
李震国
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to EP24741236.4A priority Critical patent/EP4637150A4/en
Priority to KR1020257025879A priority patent/KR20250134629A/ko
Priority to JP2025540186A priority patent/JP2026503281A/ja
Publication of WO2024149238A1 publication Critical patent/WO2024149238A1/zh
Priority to US19/262,813 priority patent/US20250358456A1/en
Priority to MX2025008015A priority patent/MX2025008015A/es
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/189—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding
    • H04N19/196—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding being specially adapted for the computation of encoding parameters, e.g. by averaging previously computed encoding parameters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3068—Precoding preceding compression, e.g. Burrows-Wheeler transformation
    • H03M7/3079—Context modeling
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
    • H03M7/4006—Conversion to or from arithmetic code
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/124—Quantisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/182—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a pixel
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H04N19/426—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements using memory downsizing methods
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder

Definitions

  • the present application relates to the field of data encoding and decoding, and in particular to a data encoding and decoding method and related devices.
  • Artificial intelligence is the theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results.
  • artificial intelligence is a branch of computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can respond in a similar way to human intelligence.
  • Artificial intelligence is to study the design principles and implementation methods of various intelligent machines, so that machines have the functions of perception, reasoning and decision-making.
  • Media compression typically includes one or more stages of prediction, frequency transform, and quantization, followed by entropy encoding.
  • the corresponding media decompression typically includes entropy decoding, followed by one or more stages of inverse quantization, inverse frequency transform, and prediction.
  • entropy encoding converts input symbols into encoded data with a lower bit rate by exploiting redundancy in the input symbols (e.g., exploiting a pattern of many input symbols with common values and multiple input symbols with rare values).
  • Entropy decoding converts the encoded data into output symbols corresponding to the input symbols.
  • Huffman encoding/decoding is computationally simple, but has poor compression efficiency for certain distributions of values of the input symbols.
  • arithmetic encoding/decoding typically has much better compression efficiency at the expense of much higher computational complexity.
  • Asymmetric number system (ANS) encoding/decoding potentially provides high compression efficiency and low computational complexity.
  • existing ANS-based encoding involves division, remainder operation, and judgment, and decoding involves binary search operations, all of which are time-consuming.
  • the present application provides a data encoding method and a data decoding method, which can achieve a balance between memory and latency.
  • the present application provides a data encoding method, the method comprising: obtaining a target symbol; obtaining first information and second information corresponding to the target symbol through a first mapping relationship; the first information and the second information are obtained according to probability information corresponding to the target symbol; obtaining first encoded data through a first operation according to the first information and the state information of the encoder; and obtaining second encoded data by updating the state information through a second operation according to the second information; wherein the first encoded data and the second encoded data are used to obtain the encoding result of the target symbol, and the first operation and the second operation do not include a division operation.
  • the index information in the coding table only includes symbols
  • the mapped objects only include the first information and the second information, which is equivalent to reducing the memory usage in the coding table and avoiding operations with high consumption, thereby achieving a balance between memory and latency.
  • the first information or the second information represents an integer value.
  • the first operation and the second operation do not include a judgment operation.
  • the first operation includes: performing an addition operation on the first information and the status information, and performing a bit shift operation on the addition result of the addition operation; selecting a portion of bits from the status information as first encoded data, and the positions of the portion of bits in the status information are determined according to the shift result of the bit shift operation.
  • the second operation includes: an addition operation on the state information and a numerical value M, and a bit shift operation on the addition result of the addition operation; wherein the probability information includes a quantization probability, and M is the denominator of the quantization probability; and an addition operation is performed on the shift result of the bit shift operation and the second information.
  • the probability information includes a value of a probability mass function PMF; the value of the PMF is constructed by sequentially determining a value of the PMF of each symbol in a plurality of symbols, the plurality of symbols including the target symbol; wherein,
  • the total value of the remaining PMF excluding the PMF of the determined symbol is multiplied by the probability of the target symbol, and the ratio between the product of the multiplication and the remaining probability excluding the determined symbol is calculated. Based on the relationship between the ratio and a preset fifth value, the PMF of the target symbol is determined.
  • the fifth value is 1, and the relationship is to take a larger value.
  • the probability information includes the value of the cumulative distribution function CDF; the value of the CDF is constructed in the following manner: based on a preset order, the value of the CDF of each symbol is determined in turn, wherein the preset order is determined according to the relationship between the values of PMFs corresponding to multiple symbols, and the multiple symbols include the target symbol; wherein, when the probability distribution corresponding to the probability information of the target symbol is a symmetrical distribution, the preset order is an order that is staggered along both sides of the peak point in the symmetrical distribution; or, when the probability distribution corresponding to the probability information of the target symbol is a discrete distribution, the preset order is specifically an order from large to small; or, when the probability distribution corresponding to the probability information of the target symbol is a discrete distribution, the preset order is specifically an order from small to large.
  • the target symbol is obtained by transforming the pixel data of the image, the data obtained by transforming the pixel data of the image satisfies a preset distribution, the transformation is also used to obtain the distribution characteristics of the pixel data, the distribution characteristics include a mean or a variance, and the method further includes: according to the distribution characteristics, determining the first mapping relationship corresponding to the distribution characteristics from multiple mapping relationships.
  • the multiple distribution features include a first distribution feature and a second distribution feature, the entropy of the first distribution feature is greater than the entropy of the second distribution feature; the value of the denominator of the quantization probability in the mapping relationship corresponding to the second distribution feature is greater than the denominator of the quantization probability in the mapping relationship corresponding to the first distribution feature.
  • different quantization probability denominators can be used to reduce the coding length.
  • a prediction model and entropy coding can be included.
  • the prediction model can input the original data, output the distribution index and the data to be encoded (such as the target symbol in this application). According to the distribution index, the entropy can be calculated. For a distribution with a smaller entropy, a larger quantization probability denominator can be used.
  • the first information in the first mapping relationship is constructed in the following manner: adding the number of consecutive highest bits of 0 in the numerical value of the PMF of the target symbol and a preset sixth numerical value; performing a bit shift operation on the sum result of the addition operation, and subtracting the shift result of the bit shift operation from the shift result of the bit shift operation on the numerical value of the PMF of the target symbol to obtain the first information; or, performing a bit shift operation on the sum result of the addition operation, and subtracting the shift result of the bit shift operation from the shift result of the bit shift operation on the numerical value of the PMF of the target symbol, and adding the result of the subtraction operation to the numerical value M to obtain the first information, wherein the probability information includes a quantization probability, and M is the denominator of the quantization probability.
  • the calculation method of PMF and CDF in the embodiment of the present application can ensure that the codeword length is reduced while the memory and delay remain unchanged.
  • the second information in the first mapping relationship is constructed in the following manner: subtracting the numerical value of the CDF of the target symbol from the numerical value of the PMF of the target symbol to obtain the second information; or subtracting the numerical value of the CDF of the target symbol from the numerical value of the PMF of the target symbol, and adding the result of the subtraction operation to the numerical value M to obtain the second information, wherein the probability information includes a quantization probability, and M is the denominator of the quantization probability.
  • the second information in the first mapping relationship is constructed in the following manner: when the result of the subtraction operation between the numerical value of the CDF of the target symbol and the numerical value of the PMF of the target symbol is greater than or equal to 0, the result of the subtraction operation is used as the second information; or, when the result of the subtraction operation between the numerical value of the CDF of the target symbol and the numerical value of the PMF of the target symbol is less than 0, the result of the subtraction operation is added to the numerical value M to obtain the second information, and the probability information includes a quantization probability, and M is the denominator of the quantization probability.
  • the first information and the second information may be combined and stored. After acquiring the combined data, the encoder may restore the first information and the second information based on certain operation rules.
  • an integer value corresponding to the target symbol can be obtained through the first mapping relationship; based on the third operation, the integer value is restored to the first information and the second information, and the first information and the second information are respectively an integer value.
  • multiple integer parameters (at most one of which is a signed integer) can be combined into a single parameter by placing the signed integer on the left, and then storing them bit by bit according to the number of bits of each parameter through shifting and bitwise OR operations; when reading the sign, the respective parameters are restored through shifting and bitwise AND operations.
  • the probability information includes PMF information corresponding to each symbol, the PMF information includes a first value and a second value; the sum of the first value and the second value is the value of the PMF; the probability information also includes CDF information corresponding to each symbol, the CDF information includes a third value and a fourth value; the third value and the fourth value are constructed in the following manner:
  • the fourth value corresponding to each symbol is determined in sequence by accumulation according to the second values and the third values of the plurality of symbols.
  • the second information includes first sub-information (also referred to as state addend 1), second sub-information (also referred to as state threshold) and third sub-information (also referred to as state addend 2);
  • the first sub-information in the first mapping relationship is constructed in the following manner: performing a subtraction operation on the third value of the target symbol and the value of the PMF of the target symbol to obtain the first sub-information;
  • the second sub-information in the first mapping relationship is constructed by: performing an addition operation on the third value of the target symbol and the first value of the target symbol, and performing a subtraction operation on the result of the addition operation and 1 to obtain the second sub-information;
  • the third sub-information in the first mapping relationship is constructed in the following manner: subtracting the fourth value of the target symbol from the third value of the target symbol, and subtracting the result of the subtraction operation from the first value of the target symbol to obtain the third sub-information.
  • the second operation includes:
  • the operation result of the addition operation is smaller than the second sub-information, the operation result of the addition operation is used as the second encoded data.
  • the above method can be applicable to, but not limited to, unimodal symmetrical distribution (such as Gaussian distribution, logistic distribution, Laplace distribution, etc.) to reduce the coding length, but the coding calculation amount will increase.
  • unimodal symmetrical distribution such as Gaussian distribution, logistic distribution, Laplace distribution, etc.
  • the first information is stored using 10 bits
  • the first sub-information is stored using 8 bits
  • the second sub-information is stored using 7 bits
  • the third sub-information is stored using 7 bits.
  • the sum of the first values of multiple symbols is 128, and the third sub-information is less than 128.
  • the present application also provides a data encoding method, which is applied to an encoder based on an asymmetric digital system ANS, and the method includes: obtaining a first symbol, the sum of the quantization probability corresponding to the first symbol and the quantization probability corresponding to the second symbol is 1, and the difference between the quantization probability corresponding to the first symbol and 1 is less than a threshold, and the difference between the quantization probability corresponding to the second symbol and 0 is less than a threshold; based on the relationship between the numerical size of the state information of the encoder and the numerical value M satisfying a first condition, performing a first operation between the state information and the numerical value M to obtain first encoded data, and updating the state information to 0; based on the relationship between the numerical size of the state information of the encoder and the numerical value M not satisfying the first condition, adding 1 to the state information.
  • the method further includes: acquiring the second symbol; using the state information of the encoder as the first encoded data, and updating the state information to the difference between the value M and 1.
  • the above embodiment can be directed to an encoding and decoding scheme when there are two symbols in total and the probability of a single symbol is close to 1.
  • This embodiment does not need to construct an encoding and decoding table, so no additional memory is required to store the table.
  • the present application provides a data decoding method, the method comprising: obtaining state information of the decoder and storing bit, the state information corresponds to the first bit, and the first bit is the bit to be decoded currently; according to the first mapping relationship, the first information, the second information and the third information corresponding to the state information are determined; the first information is the target symbol corresponding to the first bit, and the target symbol is the decoding result of the first bit, the second information represents the number of bits selected from the storage bits, the third information is used to perform an addition operation with the bits selected from the storage bits according to the third information, and the addition operation result is used to update the state information, the updated state information corresponds to the second bit, and the second bit is the bit to be decoded after the first bit.
  • the method further includes: removing the selected bits from the storage bits to obtain updated storage bits.
  • the first information, the second information or the third information represents an integer value.
  • the first information in the first mapping relationship is constructed in the following manner: taking x that satisfies C(x) ⁇ s ⁇ (C(x)+P(x)) as the first information; wherein C represents the value of CDF, P represents the value of PMF, and s represents the status information.
  • the first information in the first mapping relationship is constructed in the following manner:
  • C1 represents the third value corresponding to CDF
  • P1 represents the first value corresponding to PMF
  • C2 represents the fourth value corresponding to CDF
  • P2 represents the second value corresponding to PMF
  • s represents the status information
  • the sum of the first value and the second value is the value of PMF.
  • the second information in the first mapping relationship is constructed in the following manner:
  • clz(s′-C(x)+P(x))+X is used as the second information; wherein clz represents the number of bits whose highest bit is consecutively 0 in the value, X is a preset fifth value, and s′ is obtained as follows:
  • the third information in the first mapping relationship is constructed in the following manner: performing a bit shift operation on the value of s′-C(x)+P(x) to obtain the third information, and the shift amount of the bit shift operation is obtained according to the second information.
  • the second information in the first mapping relationship is constructed in the following manner: the value of clz(s-C(x)+P(x))+X is used as the second information; wherein, clz represents the number of consecutive bits whose highest bit in the value is 0, and X is a preset fifth value.
  • the third information in the first mapping relationship is constructed in the following manner:
  • a bit shift operation is performed on the value of s-C(x)+P(x), and a value M is subtracted from the operation result of the bit shift operation to obtain the third information, where M is the denominator of the quantization probability, and the shift amount of the bit shift operation is obtained based on the second information.
  • the first information, the second information or the third information is obtained based on probability information;
  • the probability information includes the value of a probability mass function PMF;
  • the value of the PMF is constructed in the following manner: sequentially determining the value of the PMF of each symbol in a plurality of symbols, the plurality of symbols including the target symbol; wherein, when determining the value of the PMF of the target symbol, the total value of the remaining PMF excluding the PMF of the determined symbol is multiplied by the probability of the target symbol, and the ratio between the product of the multiplication result and the remaining probability excluding the determined symbol is calculated, and the PMF of the target symbol is determined based on the relationship between the ratio and a preset value.
  • the preset value is 1, and the relationship is to take a larger value.
  • the first information, the second information or the third information is obtained according to probability information;
  • the probability information includes a value of a cumulative distribution function CDF;
  • the value of the CDF is constructed in the following manner:
  • the preset order is an order staggered along both sides of a peak point in the symmetrical distribution
  • the preset order is specifically an order from large to small; or,
  • the preset order is specifically an order from small to large.
  • the method further includes:
  • the coding result is obtained by encoding pixel data of an image, and the state information and the storage bit are obtained according to the coding result;
  • the distribution characteristics of the pixel data including mean or variance
  • the first mapping relationship corresponding to the distribution feature is determined from a plurality of mapping relationships.
  • the present application also provides a data decoding method, which is applied to a decoder based on an asymmetric digital system ANS, and the method comprises:
  • Acquire state information of the decoder where the state information corresponds to a first bit, and the first bit is a bit currently to be decoded;
  • state information is the difference between the value M and 1, determining that the decoding result of the first bit is a second symbol, and updating the state information to the result of reading the value M bits from the storage;
  • the decoding result of the first bit is determined to be the first symbol; if the status information is 0, the status information is updated to the sum of the difference between the numerical value M and 2 and the value of 1 bit read from the storage; if the status information is not 0, the status information is updated to the difference between the status information and 1; the updated status information corresponds to the second bit, and the second bit is the bit to be decoded after the first bit.
  • the present application provides a data encoding device, the device comprising:
  • An acquisition module used to acquire target symbols
  • An encoding module configured to obtain first information and second information corresponding to the target symbol through a first mapping relationship; the first information and the second information are obtained according to probability information corresponding to the target symbol;
  • the state information is updated through a second operation to obtain second coded data
  • the first coded data and the second coded data are used to obtain a coding result of the target symbol, and the first operation and the second operation do not include a division operation.
  • the first information or the second information represents an integer value.
  • the first operation and the second operation do not include a judgment operation.
  • the first operation includes:
  • a portion of bits is selected from the state information as first coded data, and positions of the portion of bits in the state information are determined according to a shift result of the bit shift operation.
  • the second operation includes:
  • the probability information includes a quantization probability
  • M is a denominator of the quantization probability
  • An addition operation is performed on a shift result of the bit shift operation and the second information.
  • the probability information includes a value of a probability mass function PMF; the value of the PMF is constructed in the following manner:
  • the total value of the remaining PMF excluding the PMF of the determined symbol is multiplied by the probability of the target symbol, and the ratio between the product of the multiplication result and the remaining probability excluding the determined symbol is calculated.
  • the PMF of the target symbol is determined according to the relationship between the ratio and a preset fifth value.
  • the fifth value is 1, and the relationship is to take a larger value.
  • the probability information includes a value of a cumulative distribution function CDF; the value of the CDF is constructed in the following manner:
  • the preset order is an order staggered along both sides of a peak point in the symmetrical distribution
  • the preset order is specifically an order from large to small; or,
  • the preset order is specifically an order from small to large.
  • the target symbol is obtained by transforming pixel data of an image
  • the data obtained by transforming the pixel data of the image satisfies a preset distribution
  • the transformation is further used to obtain a distribution feature of the pixel data
  • the distribution feature includes a mean or a variance
  • the acquisition module is further used to:
  • the first mapping relationship corresponding to the distribution feature is determined from a plurality of mapping relationships.
  • the multiple distribution features include a first distribution feature and a second distribution feature, and the entropy of the first distribution feature is greater than the entropy of the second distribution feature;
  • a value of a denominator of a quantization probability in a mapping relationship corresponding to the second distribution feature is greater than a value of a denominator of a quantization probability in a mapping relationship corresponding to the first distribution feature.
  • the first information in the first mapping relationship is constructed in the following manner:
  • a bit shift operation is performed on the sum result of the addition operation, and a subtraction operation is performed on the shift result of the bit shift operation and the shift result of the bit shift operation on the numerical value of the PMF of the target symbol, and the operation result of the subtraction operation is added to the numerical value M to obtain the first information, wherein the probability information includes a quantization probability, and M is the denominator of the quantization probability.
  • the second information in the first mapping relationship is constructed in the following manner:
  • the second information in the first mapping relationship is constructed in the following manner:
  • the result of the subtraction operation between the numerical value of the CDF of the target symbol and the numerical value of the PMF of the target symbol is less than 0, the result of the subtraction operation is added to the numerical value M to obtain the second information, where the probability information includes a quantization probability, and M is the denominator of the quantization probability.
  • the encoding module is specifically used to:
  • the integer value is restored to the first information and the second information, where the first information and the second information are respectively an integer value.
  • the probability information includes PMF information corresponding to each symbol, the PMF information includes a first value and a second value; the sum of the first value and the second value is the value of the PMF; the probability information also includes CDF information corresponding to each symbol, the CDF information includes a third value and a fourth value; the third value and the fourth value are constructed in the following manner:
  • the fourth value corresponding to each symbol is determined in sequence by accumulation according to the second values and the third values of the plurality of symbols.
  • the second information includes first sub-information, second sub-information and third sub-information
  • the first sub-information in the first mapping relationship is constructed in the following manner: performing a subtraction operation on the third value of the target symbol and the value of the PMF of the target symbol to obtain the first sub-information;
  • the second sub-information in the first mapping relationship is constructed by: performing an addition operation on the third value of the target symbol and the first value of the target symbol, and performing a subtraction operation on the result of the addition operation and 1 to obtain the second sub-information;
  • the third sub-information in the first mapping relationship is constructed in the following manner: subtracting the fourth value of the target symbol from the third value of the target symbol, and subtracting the result of the subtraction operation from the first value of the target symbol to obtain the third sub-information.
  • the second operation includes:
  • the operation result of the addition operation is smaller than the second sub-information, the operation result of the addition operation is used as the second encoded data.
  • the first information is stored using 10 bits
  • the first sub-information is stored using 8 bits
  • the second sub-information is stored using 7 bits
  • the third sub-information is stored using 7 bits.
  • the sum of the first values of multiple symbols is 128, and the third sub-information is less than 128.
  • the present application also provides a data encoding device, which is applied to an encoder based on an asymmetric digital system ANS, and the device comprises:
  • an acquisition module configured to acquire a first symbol, wherein the sum of a quantization probability corresponding to the first symbol and a quantization probability corresponding to the second symbol is 1, and a difference between the quantization probability corresponding to the first symbol and 1 is less than a threshold, and a difference between the quantization probability corresponding to the second symbol and 0 is less than a threshold;
  • An encoding module configured to perform a first operation between the state information and the value M of the encoder to obtain first encoded data, and update the state information to 0 according to a numerical relationship between the state information and the value M of the encoder satisfying a first condition
  • the acquisition module is further used to:
  • the encoding module is further configured to use the state information of the encoder as the first encoding data, and update the state information to the The difference between the value M and 1.
  • the present application provides a data decoding device, the device comprising:
  • An acquisition module used for acquiring state information of the decoder and a storage bit, wherein the state information corresponds to a first bit, and the first bit is a bit currently to be decoded;
  • a decoding module is used to determine the first information, second information and third information corresponding to the state information according to a first mapping relationship; the first information is a target symbol corresponding to the first bit, the target symbol is a decoding result of the first bit, the second information represents the number of bits selected from the storage bits, the third information is used to perform an addition operation with the bits selected from the storage bits according to the third information, the addition operation result is used to update the state information, the updated state information corresponds to the second bit, and the second bit is the bit to be decoded after the first bit.
  • the decoding module is further used to:
  • the selected bits are removed from the storage bits to obtain updated storage bits.
  • the first information, the second information or the third information represents an integer value.
  • the first information in the first mapping relationship is constructed in the following manner:
  • C represents the value of CDF
  • P represents the value of PMF
  • s represents the state information
  • C1 represents the third value corresponding to CDF
  • P1 represents the first value corresponding to PMF
  • C2 represents the fourth value corresponding to CDF
  • P2 represents the second value corresponding to PMF
  • s represents the status information
  • the sum of the first value and the second value is the value of PMF.
  • the second information in the first mapping relationship is constructed in the following manner:
  • clz(s-C(x)+P(x))+X is used as the second information; wherein clz represents the number of consecutive bits of the highest bit in the value being 0, and X is a preset fifth value; or,
  • clz(s′-C(x)+P(x))+X is used as the second information; wherein clz represents the number of bits whose highest bit is consecutively 0 in the value, X is a preset fifth value, and s′ is obtained as follows:
  • the third information in the first mapping relationship is constructed in the following manner:
  • a bit shift operation is performed on the value of s′-C(x)+P(x) to obtain the third information, and the shift amount of the bit shift operation is obtained according to the second information.
  • the first information, the second information or the third information is obtained according to probability information;
  • the rate information includes the value of the probability mass function PMF; the value of the PMF is constructed in the following manner:
  • the total value of the remaining PMF excluding the PMF of the determined symbol is multiplied by the probability of the target symbol, and the ratio between the product of the multiplication and the remaining probability excluding the determined symbol is calculated. Based on the relationship between the ratio and the preset value, the PMF of the target symbol is determined.
  • the preset value is 1, and the relationship is to take a larger value.
  • the first information, the second information or the third information is obtained according to probability information;
  • the probability information includes a value of a cumulative distribution function CDF;
  • the value of the CDF is constructed in the following manner:
  • the preset order is an order staggered along both sides of a peak point in the symmetrical distribution
  • the preset order is specifically an order from large to small; or,
  • the preset order is specifically an order from small to large.
  • the acquisition module is further used to:
  • the coding result is obtained by encoding pixel data of an image, and the state information and the storage bit are obtained according to the coding result;
  • the distribution characteristics of the pixel data including mean or variance
  • the first mapping relationship corresponding to the distribution feature is determined from a plurality of mapping relationships.
  • the present application also provides a data decoding device, which is applied to a decoder based on an asymmetric digital system ANS, and the device comprises:
  • An acquisition module configured to acquire state information of the decoder, wherein the state information corresponds to a first bit, and the first bit is a bit currently to be decoded;
  • a decoding module configured to determine, if the state information is a difference between a value M and 1, that a decoding result of the first bit is a second symbol, and update the state information to a result of reading the value M bits from a storage;
  • the decoding result of the first bit is determined to be the first symbol; if the status information is 0, the status information is updated to the sum of the difference between the numerical value M and 2 and the value of 1 bit read from the storage; if the status information is not 0, the status information is updated to the difference between the status information and 1; the updated status information corresponds to the second bit, and the second bit is the bit to be decoded after the first bit.
  • an embodiment of the present application provides a data encoding device, which may include a memory, a processor, and a bus system, wherein the memory is used to store programs, and the processor is used to execute the programs in the memory to execute any optional method such as the first aspect above.
  • an embodiment of the present application provides a data decoding device, which may include a memory, a processor, and a bus system, wherein the memory is used to store programs, and the processor is used to execute the programs in the memory to execute any optional method such as the second aspect above.
  • an embodiment of the present application provides a computer-readable storage medium, which stores a computer program.
  • the computer-readable storage medium When the computer-readable storage medium is run on a computer, it enables the computer to execute the above-mentioned first aspect and any optional method, and any optional method of the above-mentioned second aspect.
  • an embodiment of the present application provides a computer program product, comprising code, which, when executed, is used to implement the above-mentioned first aspect and any optional method, and any optional method of the above-mentioned second aspect.
  • the present application provides a chip system, which includes a processor for supporting an execution device or a training device to implement the functions involved in the above aspects, such as sending or processing the data involved in the above methods; or information.
  • the chip system also includes a memory, which is used to store program instructions and data necessary for the execution device or the training device.
  • the chip system can be composed of a chip, or it can include a chip and other discrete devices.
  • FIG1A is a block diagram of an example of a video decoding system for implementing an embodiment of the present invention.
  • FIG. 1B is a block diagram of another example of a video decoding system for implementing an embodiment of the present invention.
  • FIG2 is a block diagram of an example structure of an encoder for implementing an embodiment of the present invention.
  • FIG3 is a block diagram of an example structure of a decoder for implementing an embodiment of the present invention.
  • FIG4 is a block diagram of an example of a video decoding device for implementing an embodiment of the present invention.
  • FIG5 is a schematic diagram of a flow chart of a data encoding method provided in an embodiment of the present application.
  • FIG6 is a schematic diagram of a flow chart of a data encoding method provided in an embodiment of the present application.
  • FIG7 is a schematic diagram of a flow chart of a data encoding method provided in an embodiment of the present application.
  • FIG8 is a schematic diagram of a flow chart of a data encoding method provided in an embodiment of the present application.
  • FIG9 is a schematic diagram of a flow chart of a data decoding method provided in an embodiment of the present application.
  • FIG10A is a schematic diagram of a flow chart of a data decoding method provided in an embodiment of the present application.
  • FIG10B is a schematic diagram of a flow chart of a data decoding method provided in an embodiment of the present application.
  • FIG11 is a schematic diagram of the structure of a data encoding device provided in an embodiment of the present application.
  • FIG12 is a schematic diagram of the structure of a data decoding device provided in an embodiment of the present application.
  • FIG13 is a schematic diagram of an execution device provided in an embodiment of the present application.
  • FIG14 is a schematic diagram of a server provided in an embodiment of the present application.
  • FIG. 15 is a schematic diagram of a chip provided in an embodiment of the present application.
  • “at least one” refers to one or more, and “more than one” refers to two or more.
  • “And/or” describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and/or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural. The character “/” generally indicates that the associated objects before and after are in an "or” relationship. "At least one of the following” or similar expressions refers to any combination of these items, including any combination of single or plural items.
  • At least one of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c may be single or multiple.
  • a media encoder/decoder system such as a video encoder/decoder system, an audio encoder/decoder system, or a texture encoder/decoder system.
  • the techniques and tools described in the embodiments of the present application can generally be implemented in a data encoder/decoder system for use in encoding/decoding text data or other types of data.
  • video codec may also be audio, texture or image codec.
  • audio codec may also be audio, texture or image codec.
  • video codec may also be audio, texture or image codec.
  • Video coding generally refers to processing a sequence of pictures to form a video or video sequence.
  • the terms "picture”, "frame” or “image” can be used as synonyms.
  • Video coding as used in this article means video encoding or video decoding.
  • Video encoding is performed on the source side and typically involves processing (e.g., by compression) the original video picture to reduce the amount of data required to represent the video picture so that it can be stored and/or transmitted more efficiently.
  • Video decoding is performed on the destination side and typically involves inverse processing relative to the encoder to reconstruct the video picture.
  • Embodiments involving "encoding” of video pictures should be understood as involving "encoding” or "decoding” of video sequences.
  • the combination of an encoding part and a decoding part is also referred to as a codec (encoding and decoding).
  • a video sequence consists of a series of pictures, which are further divided into slices, which are further divided into blocks.
  • Video coding is performed in blocks.
  • the concept of blocks is further expanded.
  • MB macroblocks
  • partitions which can be used for predictive coding.
  • HEVC high efficiency video coding
  • basic concepts such as coding units (CU), prediction units (PU) and transform units (TU) are used to functionally divide various block units and describe them using a new tree-based structure.
  • CU can be divided into smaller CUs according to the quadtree, and the smaller CU can be further divided to form a quadtree structure.
  • CU is the basic unit for dividing and encoding the coded image.
  • PU can correspond to prediction blocks and is the basic unit of predictive coding.
  • CU is further divided into multiple PUs according to the division mode.
  • TU can correspond to a transform block, which is a basic unit for transforming a prediction residual.
  • CU, PU or TU they all essentially belong to the concept of a block (or image block).
  • the concept of an image block (e.g., a first image block and a second image block) involved in the embodiments of the present application can be specifically described herein.
  • a CTU is split into multiple CUs by using a quadtree structure represented as a coding tree.
  • the decision is made at the CU level whether to encode a picture area using inter-picture (temporal) or intra-picture (spatial) prediction.
  • Each CU can be further split into one, two, or four PUs based on the PU split type.
  • the same prediction process is applied within a PU, and the relevant information is transmitted to the decoder on a PU basis.
  • the CU can be split into transform units (TUs) according to other quadtree structures similar to the coding tree for the CU.
  • quad-tree and binary tree QTBT are used to split frames to split coding blocks.
  • the CU can be square or rectangular in shape.
  • the image block to be processed in the current encoded image (referred to as the image block to be processed) may be referred to as the current block.
  • the image block to be processed refers to the block currently being encoded; in decoding, the image block to be processed refers to the block currently being decoded.
  • the decoded image block in the reference image used to predict the current block is referred to as a reference block, that is, the reference block is a block that provides a reference signal for the current block, wherein the reference signal represents the pixel value in the image block.
  • the block in the reference image that provides a prediction signal for the current block may be referred to as a prediction block, wherein the prediction signal represents the pixel value or sampling value or sampling signal in the prediction block.
  • the best reference block is found. This best reference block will provide a prediction for the current block, and this block may be referred to as a prediction block.
  • the original video picture can be reconstructed, that is, the reconstructed video picture has the same quality as the original video picture (assuming no transmission loss or other data loss during storage or transmission).
  • further compression is performed by, for example, quantization to reduce the amount of data required to represent the video picture, but the decoder side cannot fully reconstruct the video picture, that is, the quality of the reconstructed video picture is lower or worse than the quality of the original video picture.
  • Video coding standards of H.261 belong to the category of "lossy hybrid video codecs" (i.e., combining spatial and temporal prediction in the sample domain with 2D transform coding in the transform domain for applying quantization).
  • Each picture of a video sequence is usually divided into a set of non-overlapping blocks, which are usually encoded at the block level.
  • the encoder side usually processes, i.e., encodes the video at the block (video block) level, for example, by generating a prediction block through spatial (intra-picture) prediction and temporal (inter-picture) prediction, subtracting the prediction block from the current block (currently processed or to be processed block) to obtain a residual block, transforming the residual block in the transform domain and quantizing the residual block to reduce the amount of data to be transmitted (compressed), while the decoder side applies the inverse processing part relative to the encoder to the coded or compressed block to reconstruct the current block for representation.
  • the encoder replicates the decoder processing cycle, so that the encoder and decoder generate the same prediction (e.g., intra-frame prediction and inter-frame prediction) and/or reconstruction for processing, i.e., encoding subsequent blocks.
  • FIG. 1A exemplarily shows a schematic block diagram of a video encoding and decoding system 10 used in the embodiments of the present invention.
  • the video encoding and decoding system 10 may include a source device 12 and a destination device 14.
  • the source device 12 generates encoded video data, and therefore, the source device 12 may be referred to as a video encoding device.
  • the destination device 14 may decode the encoded video data generated by the source device 12, and therefore, the destination device 14 may be referred to as a video decoding device.
  • the source device 12, the destination device 14, or both may include one or more processors and a memory coupled to the one or more processors.
  • the memory may include, but is not limited to, RAM, ROM, EEPROM, flash memory, or any other media that can be used to store desired program code in the form of instructions or data structures that can be accessed by a computer, as described herein.
  • the source device 12 and the destination device 14 may include a variety of devices, including a desktop computer, a mobile computing device, a notebook (e.g., laptop) computer, a tablet computer, a set-top box, a telephone handset such as a so-called "smart" phone, a television, a camera, a display device, a digital media player, a video game console, a vehicle computer, a wireless communication device, or the like.
  • FIG. 1A illustrates the source device 12 and the destination device 14 as separate devices
  • device embodiments may also include both the source device 12 and the destination device 14 or the functionality of both, i.e., the source device 12 or the corresponding functionality and the destination device 14 or the corresponding functionality.
  • the source device 12 or the corresponding functionality and the destination device 14 or the corresponding functionality may be implemented using the same hardware and/or software, or using separate hardware and/or software, or any combination thereof.
  • the source device 12 and the destination device 14 may be communicatively connected via a link 13, and the destination device 14 may receive the encoded video data from the source device 12 via the link 13.
  • the link 13 may include one or more media or devices capable of moving the encoded video data from the source device 12 to the destination device 14.
  • the link 13 may include one or more communication media that enable the source device 12 to transmit the encoded video data directly to the destination device 14 in real time.
  • the source device 12 may modulate the encoded video data according to a communication standard (e.g., a wireless communication protocol), and may transmit the modulated video data to the destination device 14.
  • the one or more communication media may include wireless and/or wired communication media, such as a radio frequency (RF) spectrum or one or more physical transmission lines.
  • RF radio frequency
  • the one or more communication media may form part of a packet-based network, such as a local area network, a wide area network, or a global network (e.g., the Internet).
  • the one or more communication media may include routers, switches, base stations, or other devices that facilitate communication from the source device 12 to the destination device 14.
  • the source device 12 includes an encoder 20.
  • the source device 12 may also include a picture source 16, a picture preprocessor 18, and a communication interface 22.
  • the encoder 20, the picture source 16, the picture preprocessor 18, and the communication interface 22 may be hardware components in the source device 12, or may be software programs in the source device 12. They are described as follows:
  • the image source 16 may include or may be any type of image capture device, for example, for capturing real-world images, and/or any type of images or comments (for screen content encoding, some text on the screen is also considered to be part of the image or image to be encoded) generation device, such as a computer graphics processor for generating computer animation images, or any type of device for acquiring and/or providing real-world images, computer animation images (e.g., screen content, virtual reality (VR) images), and/or any combination thereof (e.g., augmented reality (AR) images).
  • image capture device for example, for capturing real-world images, and/or any type of images or comments (for screen content encoding, some text on the screen is also considered to be part of the image or image to be encoded) generation device, such as a computer graphics processor for generating computer animation images, or any type of device for acquiring and/or providing real-world images, computer animation images (e.g., screen content, virtual reality (VR) images), and/or any combination thereof (e.
  • the image source 16 may be a camera for capturing images or a memory for storing images, and the image source 16 may also include any type of (internal or external) interface for storing previously captured or generated images and/or acquiring or receiving images.
  • the image source 16 may be, for example, a local or integrated camera integrated in the source device; when the image source 16 is a memory, the image source 16 may be, for example, a local or integrated memory integrated in the source device.
  • the interface may be, for example, an external interface for receiving pictures from an external video source, such as an external picture capture device, such as a camera, an external memory, or an external picture generating device, such as an external computer graphics processor, a computer, or a server.
  • the interface may be any type of interface according to any proprietary or standardized interface protocol, such as a wired or wireless interface, an optical interface.
  • a picture can be regarded as a two-dimensional array or matrix of pixels (picture element).
  • the pixels in the array can also be called sampling points.
  • the number of sampling points in the array or picture in the horizontal and vertical directions (or axes) defines the size and/or resolution of the picture.
  • three color components are usually used, that is, the picture can be represented as or include three sampling arrays.
  • the picture includes corresponding red, green and blue sampling arrays.
  • each pixel is usually represented in a brightness/chrominance format or color space, such as for a picture in the YUV format, including a brightness component indicated by Y (sometimes also indicated by L) and two chrominance components indicated by U and V.
  • the brightness (luma) component Y represents the brightness or grayscale level intensity (for example, the two are the same in a grayscale picture), while the two chrominance (chroma) components U and V represent the chrominance or color information components.
  • a picture in the YUV format includes a brightness sampling array of brightness sampling values (Y) and two chrominance sampling arrays of chrominance values (U and V).
  • RGB format can be converted or transformed into YUV format, and vice versa, which is also called color conversion or transformation. If the image is black and white, the image may only include a brightness sampling array.
  • the image transmitted from the image source 16 to the image processor may also be referred to as raw image data 17.
  • the image preprocessor 18 is used to receive the original image data 17 and perform preprocessing on the original image data 17 to obtain a preprocessed image 19 or preprocessed image data 19.
  • the preprocessing performed by the image preprocessor 18 may include refurbishment, color format conversion (e.g., from RGB format to YUV format), color adjustment, or denoising.
  • the encoder 20 (or encoder 20) is used to receive the pre-processed picture data 19, and process the pre-processed picture data 19 using the relevant prediction mode, so as to provide the encoded picture data 21 (the structural details of the encoder 20 will be further described below based on FIG. 2 or FIG. 4 or FIG. 5).
  • the encoder 20 can be used to execute the various embodiments described below to implement the present invention. The video encoding method described above.
  • the communication interface 22 can be used to receive the encoded picture data 21 and transmit the encoded picture data 21 to the destination device 14 or any other device (such as a memory) through the link 13 for storage or direct reconstruction.
  • the other device can be any device for decoding or storage.
  • the communication interface 22 can, for example, be used to encapsulate the encoded picture data 21 into a suitable format, such as a data packet, for transmission on the link 13.
  • the destination device 14 includes a decoder 30.
  • the destination device 14 may also include a communication interface 28, a picture post-processor 32, and a display device 34. They are described as follows:
  • the communication interface 28 can be used to receive the encoded picture data 21 from the source device 12 or any other source, such as a storage device, such as an encoded picture data storage device.
  • the communication interface 28 can be used to transmit or receive the encoded picture data 21 via the link 13 between the source device 12 and the destination device 14 or via any type of network, such as a direct wired or wireless connection, any type of network, such as a wired or wireless network or any combination thereof, or any type of private network and public network, or any combination thereof.
  • the communication interface 28 can be used, for example, to decapsulate the data packet transmitted by the communication interface 22 to obtain the encoded picture data 21.
  • Both communication interface 28 and communication interface 22 may be configured as unidirectional communication interfaces or bidirectional communication interfaces and may be used, for example, to send and receive messages to establish connections, confirm and exchange any other information related to communication links and/or data transmissions such as encoded picture data transmissions.
  • the decoder 30 (or decoder 30) is used to receive the encoded picture data 21 and provide decoded picture data 31 or decoded picture 31 (the structural details of the decoder 30 will be further described below based on FIG. 3 or FIG. 4 or FIG. 5). In some embodiments, the decoder 30 can be used to execute the various embodiments described below to implement the video decoding method described in the present invention.
  • the picture post-processor 32 is used to perform post-processing on the decoded picture data 31 (also called reconstructed picture data) to obtain post-processed picture data 33.
  • the post-processing performed by the picture post-processor 32 may include: color format conversion (for example, from YUV format to RGB format), color adjustment, repair or resampling, or any other processing, and can also be used to transmit the post-processed picture data 33 to the display device 34.
  • the display device 34 can be or include any type of display for presenting the reconstructed picture, such as an integrated or external display or monitor.
  • the display can include a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a plasma display, a projector, a micro-LED display, liquid crystal on silicon (LCoS), a digital light processor (DLP), or any other type of display.
  • FIG. 1A illustrates the source device 12 and the destination device 14 as separate devices
  • device embodiments may also include both the source device 12 and the destination device 14 or both functionalities, i.e., the source device 12 or corresponding functionalities and the destination device 14 or corresponding functionalities.
  • the source device 12 or corresponding functionalities and the destination device 14 or corresponding functionalities may be implemented using the same hardware and/or software, or using separate hardware and/or software, or any combination thereof.
  • the source device 12 and the destination device 14 may include any of a variety of devices, including any type of handheld or stationary device, such as a notebook or laptop computer, a mobile phone, a smart phone, a tablet or tablet computer, a camera, a desktop computer, a set-top box, a television, a camera, a car device, a display device, a digital media player, a video game console, a video streaming device (such as a content service server or a content distribution server), a broadcast receiver device, a broadcast transmitter device, etc., and may not use or use any type of operating system.
  • a handheld or stationary device such as a notebook or laptop computer, a mobile phone, a smart phone, a tablet or tablet computer, a camera, a desktop computer, a set-top box, a television, a camera, a car device, a display device, a digital media player, a video game console, a video streaming device (such as a content service server or a content distribution server), a broadcast receiver device,
  • Both the encoder 20 and the decoder 30 may be implemented as any of a variety of suitable circuits, such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, hardware, or any combination thereof.
  • DSPs digital signal processors
  • ASICs application-specific integrated circuits
  • FPGAs field-programmable gate arrays
  • the device may store the instructions of the software in a suitable non-transitory computer-readable storage medium, and may use one or more processors to execute the instructions in hardware to perform the technology of the present disclosure. Any of the foregoing (including hardware, software, a combination of hardware and software, etc.) may be considered one or more processors.
  • the video encoding and decoding system 10 shown in FIG. 1A is merely an example, and the techniques of the present invention may be applicable to video encoding settings (e.g., video encoding or video decoding) that do not necessarily include any data communication between the encoding and decoding devices.
  • data may be retrieved from local storage, streamed over a network, etc.
  • a video encoding device may encode data and store the data to storage, and/or a video decoding device may retrieve data from storage and decode the data.
  • the video encoding and decoding devices that do not communicate with each other may be used to perform the operations of the video encoding and decoding devices. Rather, the encoding and decoding is performed by a device that only encodes data to a memory and/or retrieves data from a memory and decodes data.
  • the encoder 20 can be deployed on a terminal device or a server on the cloud side
  • the decoder 30 can be deployed on a terminal device or a server on the cloud side
  • the encoder 20 and the decoder 30 can be deployed together on a terminal device or a server on the cloud side.
  • the encoder 20 and the decoder 30 can be deployed on a terminal device.
  • the encoder 20 can encode and compress the video on the terminal device, and perform secondary compression (or so-called incremental storage compression) based on the video encoding method provided in an embodiment of the present application, and store the compressed data.
  • secondary compression or so-called incremental storage compression
  • the encoder 20 and the decoder 30 can be deployed on multiple terminal devices.
  • the encoder 20 can encode and compress the video on the terminal device, and perform secondary compression (or incremental storage compression) based on the video encoding method provided in an embodiment of the present application, and transmit the compressed data to other terminal devices.
  • secondary compression or incremental storage compression
  • the encoder 20 and the decoder 30 can be deployed on a terminal device and a server on the cloud side.
  • the encoder 20 can encode and compress the video on the terminal device, and perform secondary compression (or incremental storage compression) based on the video encoding method provided in an embodiment of the present application, and transmit the compressed data to the server.
  • FIG. 1B is an illustrative diagram of an example of a video decoding system 40 including the encoder 20 of FIG. 2 and/or the decoder 30 of FIG. 3 according to an exemplary embodiment.
  • the video decoding system 40 may implement a combination of various techniques of the embodiments of the present invention.
  • the video decoding system 40 may include an imaging device 41, an encoder 20, a decoder 30 (and/or a video codec implemented by logic circuits of a processing unit 46), an antenna 42, one or more processors 43, one or more memories 44, and/or a display device 45.
  • imaging device 41, antenna 42, processing unit 46, logic circuit, encoder 20, decoder 30, processor 43, memory 44, and/or display device 45 are capable of communicating with each other.
  • video decoding system 40 is illustrated with encoder 20 and decoder 30, in different examples, video decoding system 40 may include only encoder 20 or only decoder 30.
  • antenna 42 can be used to transmit or receive encoded data of video data.
  • display device 45 can be used to present video data.
  • the logic circuit can be implemented by processing unit 46.
  • Processing unit 46 can include application-specific integrated circuit (ASIC) logic, graphics processor, general processor, etc.
  • Video decoding system 40 can also include optional processor 43, which can similarly include application-specific integrated circuit (ASIC) logic, graphics processor, general processor, etc.
  • the logic circuit can be implemented by hardware, such as video encoding dedicated hardware, etc., and processor 43 can be implemented by general software, operating system, etc.
  • memory 44 can be any type of memory, such as volatile memory (e.g., static random access memory (SRAM), dynamic random access memory (DRAM), etc.) or non-volatile memory (e.g., flash memory, etc.).
  • volatile memory e.g., static random access memory (SRAM), dynamic random access memory (DRAM), etc.
  • non-volatile memory e.g., flash memory, etc.
  • memory 44 may be implemented by cache memory.
  • logic circuitry may access memory 44 (e.g., for implementing an image buffer).
  • logic circuitry and/or processing unit 46 may include memory (e.g., cache memory, etc.) for implementing an image buffer, etc.
  • the encoder 20 implemented by logic circuits may include an image buffer (e.g., implemented by processing unit 46 or memory 44) and a graphics processing unit (e.g., implemented by processing unit 46).
  • the graphics processing unit may be communicatively coupled to the image buffer.
  • the graphics processing unit may include the encoder 20 implemented by logic circuits to implement the various modules discussed with reference to FIG. 2 and/or any other encoder system or subsystem described herein.
  • the logic circuits may be used to perform the various operations discussed herein.
  • the decoder 30 may be implemented by logic circuits in a similar manner to implement the various modules discussed with reference to the decoder 30 of FIG. 3 and/or any other decoder systems or subsystems described herein.
  • the decoder 30 implemented by logic circuits may include an image buffer (implemented by the processing unit 2820 or memory 44) and a graphics processing unit (implemented, for example, by the processing unit 46).
  • the graphics processing unit may be communicatively coupled to the image buffer.
  • the graphics processing unit may include the decoder 30 implemented by logic circuits to implement the various modules discussed with reference to FIG. 3 and/or any other decoder systems or subsystems described herein.
  • antenna 42 may be used to receive encoded encoding data of the video data.
  • the encoded encoding data may include data related to the encoded video frames discussed herein, indicators, index values, mode selection data, etc., such as data related to the encoding partition (e.g., transform coefficients or quantized transform coefficients, (as discussed) optional indicators, and/or data defining the encoding partition).
  • Video decoding system 40 may also include a decoder 30 coupled to antenna 42 and used to decode the encoded encoding data.
  • Display device 45 is used to present the video frames.
  • the decoder 30 can be used to perform the reverse process.
  • decoder 30 can be used to receive and parse such syntax elements and decode the relevant video data accordingly.
  • encoder 20 can entropy encode the syntax elements into encoded video encoding data.
  • decoder 30 can parse such syntax elements and decode the relevant video data accordingly.
  • FIG. 2 shows a schematic/conceptual block diagram of an example of an encoder 20 for implementing an embodiment of the present invention.
  • the encoder 20 includes a residual calculation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a buffer 216, a loop filter unit 220, a decoded picture buffer (DPB) 230, a prediction processing unit 260, and an entropy coding unit 270.
  • the prediction processing unit 260 may include an inter-frame prediction unit 244, an intra-frame prediction unit 254, and a mode selection unit 262.
  • the inter-frame prediction unit 244 may include a motion estimation unit and a motion compensation unit (not shown).
  • the encoder 20 shown in FIG. 2 may also be referred to as a hybrid video encoder or a video encoder according to a hybrid video codec.
  • the residual calculation unit 204, the transform processing unit 206, the quantization unit 208, the prediction processing unit 260 and the entropy coding unit 270 form a forward signal path of the encoder 20, while for example, the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the buffer 216, the loop filter 220, the decoded picture buffer (DPB) 230, and the prediction processing unit 260 form a backward signal path of the encoder, wherein the backward signal path of the encoder corresponds to the signal path of the decoder (see the decoder 30 in Figure 3).
  • the encoder 20 receives a picture 201 or an image block 203 of the picture 201, for example, a picture in a sequence of pictures forming a video or a video sequence, via, for example, an input 202.
  • the image block 203 may also be referred to as a current coding block or an image block to be processed, and the picture 201 may be referred to as a current picture or a picture to be coded (especially when the current picture is distinguished from other pictures in video coding, such as previously coded and/or decoded pictures in the same video sequence, i.e., a video sequence that also includes the current picture).
  • An embodiment of the encoder 20 may include a segmentation unit (not shown in FIG. 2 ) for segmenting the picture 201 into a plurality of blocks, such as image blocks 203 , typically into a plurality of non-overlapping blocks.
  • the segmentation unit may be used to use the same block size for all pictures in the video sequence and define a corresponding grid of block sizes, or to change the block size between pictures or subsets or groups of pictures and segment each picture into corresponding blocks.
  • prediction processing unit 260 of encoder 20 may be used to perform any combination of the above-described segmentation techniques.
  • the image block 203 is also or can be regarded as a two-dimensional array or matrix of sampling points with sample values, although its size is smaller than that of the picture 201.
  • the image block 203 may include, for example, one sampling array (e.g., a luminance array in the case of the black and white picture 201) or three sampling arrays (e.g., one luminance array and two chrominance arrays in the case of a color picture) or any other number and/or type of arrays depending on the color format applied.
  • the number of sampling points in the horizontal and vertical directions (or axes) of the image block 203 defines the size of the image block 203.
  • the encoder 20 shown in FIG. 2 is used to encode the picture 201 block by block, for example, performing encoding and prediction on each image block 203 .
  • the residual calculation unit 204 is used to calculate the residual block 205 based on the picture image block 203 and the prediction block 265 (other details of the prediction block 265 are provided below), for example, by subtracting the sample value of the prediction block 265 from the sample value of the picture image block 203 sample by sample (pixel by pixel) to obtain the residual block 205 in the sample domain.
  • the transform processing unit 206 is used to apply a transform such as discrete cosine transform (DCT) or discrete sine transform (DST) on the sample values of the residual block 205 to obtain a transform coefficient 207 in the transform domain.
  • the transform coefficient 207 may also be referred to as a transform residual coefficient and represents the residual block 205 in the transform domain.
  • the transform processing unit 206 can be used to apply an integer approximation of the DCT/DST, such as the transform specified for HEVC/H.265. Compared to the orthogonal DCT transform, such integer approximation is usually scaled by a certain factor. In order to maintain the norm of the residual block processed by the forward transform and the inverse transform, an additional scaling factor is applied as part of the transform process.
  • the scaling factor is usually selected based on certain constraints, such as whether the scaling factor is a power of 2 for the shift operation, the bit depth of the transform coefficients, the balance between accuracy and implementation cost, etc.
  • a specific scaling factor is specified for the inverse transform on the decoder 30 side by, for example, the inverse transform processing unit 212 (and for the corresponding inverse transform on the encoder 20 side by, for example, the inverse transform processing unit 212), and accordingly, a corresponding scaling factor can be specified for the forward transform on the encoder 20 side by the transform processing unit 206.
  • the quantization unit 208 is used to quantize the transform coefficients 207, for example, by applying scalar quantization or vector quantization to obtain quantized transform coefficients 209.
  • the quantized transform coefficients 209 may also be referred to as quantized residual coefficients 209.
  • the quantization process may reduce the bit depth associated with some or all of the transform coefficients 207. For example, an n-bit transform coefficient may be rounded down to an m-bit transform coefficient during quantization, where n is greater than m.
  • the degree of quantization may be modified by adjusting a quantization parameter (QP). For example, for scalar quantization, different scales may be applied to achieve finer or coarser quantization.
  • QP quantization parameter
  • a smaller quantization step size corresponds to finer quantization, while a larger quantization step size corresponds to coarser quantization.
  • the appropriate quantization step size may be indicated by a quantization parameter (QP).
  • the quantization parameter may be an appropriate quantization step size.
  • the index of the predefined set of lengths For example, a smaller quantization parameter may correspond to fine quantization (a smaller quantization step size), a larger quantization parameter may correspond to coarse quantization (a larger quantization step size), and vice versa.
  • Quantization may include division by the quantization step size and corresponding quantization or inverse quantization, for example, performed by inverse quantization 210, or may include multiplication by the quantization step size.
  • the quantization step size may be determined using a quantization parameter.
  • the quantization step size may be calculated based on the quantization parameter using a fixed-point approximation of an equation containing division. Additional scaling factors may be introduced for quantization and inverse quantization to recover the norm of the residual block that may be modified by the scale used in the fixed-point approximation of the equation for the quantization step size and the quantization parameter.
  • the scales of the inverse transform and inverse quantization may be merged.
  • a custom quantization table may be used and sent from the encoder to the decoder through a signal, for example in the encoded data. Quantization is a lossy operation, where the larger the quantization step size, the greater the loss.
  • the inverse quantization unit 210 is used to apply the inverse quantization of the quantization unit 208 on the quantized coefficients to obtain inverse quantized coefficients 211, for example, applying an inverse quantization scheme of the quantization scheme applied by the quantization unit 208 based on or using the same quantization step size as the quantization unit 208.
  • the inverse quantized coefficients 211 may also be referred to as inverse quantized residual coefficients 211, corresponding to the transform coefficients 207, although the loss due to quantization is generally different from that of the transform coefficients.
  • the inverse transform processing unit 212 is used to apply the inverse transform of the transform applied by the transform processing unit 206, for example, an inverse discrete cosine transform (DCT) or an inverse discrete sine transform (DST), to obtain an inverse transform block 213 in the sample domain.
  • the inverse transform block 213 may also be referred to as an inverse transform dequantized block 213 or an inverse transform residual block 213.
  • the reconstruction unit 214 (e.g., the summer 214) is used to add the inverse transform block 213 (i.e., the reconstructed residual block 213) to the prediction block 265 to obtain the reconstructed block 215 in the sample domain, for example, by adding the sample values of the reconstructed residual block 213 to the sample values of the prediction block 265.
  • a buffer unit 216 (or simply "buffer" 216), such as a line buffer 216, is used to buffer or store the reconstructed blocks 215 and corresponding sample values for, for example, intra-frame prediction.
  • the encoder can be used to use the unfiltered reconstructed blocks and/or corresponding sample values stored in the buffer unit 216 for any type of estimation and/or prediction, such as intra-frame prediction.
  • embodiments of the encoder 20 may be configured such that the buffer unit 216 is used not only to store the reconstructed blocks 215 for the intra-frame prediction 254, but also for the loop filter unit 220 (not shown in FIG. 2 ), and/or, for example, such that the buffer unit 216 and the decoded picture buffer unit 230 form one buffer.
  • Other embodiments may be used to use the filtered blocks 221 and/or blocks or samples from the decoded picture buffer 230 (neither shown in FIG. 2 ) as input or basis for the intra-frame prediction 254.
  • the loop filter unit 220 (or simply "loop filter” 220) is used to filter the reconstructed block 215 to obtain a filtered block 221, so as to smoothly perform pixel conversion or improve video quality.
  • the loop filter unit 220 is intended to represent one or more loop filters, such as a deblocking filter, a sample-adaptive offset (SAO) filter, or other filters, such as a bilateral filter, an adaptive loop filter (ALF), or a sharpening or smoothing filter, or a collaborative filter.
  • the loop filter unit 220 is shown as an in-loop filter in Figure 2, in other configurations, the loop filter unit 220 may be implemented as a post-loop filter.
  • the filtered block 221 may also be referred to as a filtered reconstructed block 221.
  • the decoded picture buffer 230 may store the reconstructed coding block after the loop filter unit 220 performs a filtering operation on the reconstructed coding block.
  • Embodiments of the encoder 20 can be used to output loop filter parameters (e.g., sample adaptive offset information), for example, directly or after entropy encoding by the entropy encoding unit 270 or any other entropy encoding unit, such that the decoder 30 can receive and apply the same loop filter parameters for decoding.
  • loop filter parameters e.g., sample adaptive offset information
  • the entropy coding unit 270 is configured to perform entropy coding according to the output (e.g., quantized transform coefficients) from the quantization unit 208 and the side information.
  • the entropy coding unit 270 may be configured to determine parameters representing the quantized transform coefficients, side information, etc.
  • the entropy coding unit 270 may be configured to predict the value of the parameter based on the context information, and then encode the difference between the actual value and the predicted value. For the target symbol representing the value to be encoded, the entropy coding unit 270 may be configured to perform entropy coding in various ways.
  • Typical entropy coding techniques include Exponential-Golomb coding, Golomb-Rice coding, context adaptive binary arithmetic coding ("CABAC”), differential coding, Huffman coding, run length coding, Lempel-Ziv (“LZ”) coding, dictionary coding, RANS coding, ANS coding, TANS coding or other variations of ANS coding, and combinations thereof.
  • CABAC context adaptive binary arithmetic coding
  • LZ LZiv
  • dictionary coding dictionary coding
  • RANS coding ANS coding
  • ANS coding ANS coding
  • TANS coding TANS coding or other variations of ANS coding, and combinations thereof.
  • the entropy coding unit 270 may perform one or more variations of ANS coding.
  • the decoded picture buffer (DPB) 230 may be a reference picture memory for storing reference picture data for use by the encoder 20 in encoding video data.
  • the DPB 230 may be formed by any of a variety of memory devices, such as a dynamic random access memory (DRAM) (including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM)) or other types of memory devices.
  • DRAM dynamic random access memory
  • SDRAM synchronous DRAM
  • MRAM magnetoresistive RAM
  • RRAM resistive RAM
  • the DPB 230 and the buffer 216 may be provided by the same memory device or by separate memory devices.
  • the decoded picture buffer (DPB) 230 is used to store the filtered block 221.
  • the decoded picture buffer 230 may further be used to store other previously filtered blocks of the same current picture or a different picture of a previously reconstructed picture, such as a previously reconstructed and filtered block 221, and may provide a complete previously reconstructed, i.e., decoded picture (and corresponding reference blocks and samples) and/or a partially reconstructed current picture (and corresponding reference blocks and samples), such as for inter-frame prediction.
  • a decoded picture buffer (DPB) 230 is used to store the reconstructed block 215.
  • the prediction processing unit 260 also referred to as the block prediction processing unit 260, is used to receive or obtain an image block 203 (a current image block 203 of a current picture 201) and reconstructed picture data, such as reference samples of the same (current) picture from a buffer 216 and/or reference picture data 231 of one or more previously decoded pictures from a decoded picture buffer 230, and to process such data for prediction, i.e., to provide a prediction block 265 which may be an inter-prediction block 245 or an intra-prediction block 255.
  • the mode selection unit 262 may be used to select a prediction mode (eg, intra or inter prediction mode) and/or a corresponding prediction block 245 or 255 for use as a prediction block 265 to calculate the residual block 205 and reconstruct the reconstructed block 215 .
  • a prediction mode eg, intra or inter prediction mode
  • a corresponding prediction block 245 or 255 for use as a prediction block 265 to calculate the residual block 205 and reconstruct the reconstructed block 215 .
  • Embodiments of the mode selection unit 262 may be used to select a prediction mode (e.g., from those prediction modes supported by the prediction processing unit 260) that provides the best match or minimum residual (minimum residual means better compression in transmission or storage), or provides minimum signaling overhead (minimum signaling overhead means better compression in transmission or storage), or both.
  • the mode selection unit 262 may be used to determine the prediction mode based on rate distortion optimization (RDO), i.e., select a prediction mode that provides minimum rate distortion optimization, or select a prediction mode whose associated rate distortion at least meets the prediction mode selection criteria.
  • RDO rate distortion optimization
  • the encoder 20 is used to determine or select the best or optimal prediction mode from a (predetermined) prediction mode set.
  • the prediction mode set may include, for example, an intra-frame prediction mode and/or an inter-frame prediction mode.
  • the intra-frame prediction mode set may include multiple different intra-frame prediction modes, for example, non-directional modes such as DC (or mean) mode and planar mode, or directional modes as defined in H.265, or may include 67 different intra-frame prediction modes, for example, non-directional modes such as DC (or mean) mode and planar mode, or directional modes as defined in H.266 under development.
  • the inter-frame prediction mode set depends on the available reference picture (i.e., at least part of the decoded picture stored in DBP230 as mentioned above) and other inter-frame prediction parameters, such as whether to use the entire reference picture or only a part of the reference picture, such as a search window area around the area of the current block, to search for the best matching reference block, and/or, for example, whether pixel interpolation such as half-pixel and/or quarter-pixel interpolation is applied.
  • the inter-frame prediction mode set may, for example, include an Advanced Motion Vector Prediction (AMVP) mode and a merge mode.
  • AMVP Advanced Motion Vector Prediction
  • the inter-frame prediction mode set may include the prediction mode based on the affine motion model described in the embodiment of the present invention, such as the advanced motion vector prediction mode (Affine AMVP mode) based on the affine motion model or the fusion mode (Affine Merge mode) based on the affine motion model, specifically, the control point-based AMVP mode (inherited control point motion vector prediction method or constructed control point motion vector prediction method), the control point-based merge mode (inherited control point motion vector prediction method or constructed control point motion vector prediction method); and, advanced temporal motion vector prediction (ATMVP) method, PLANAER method, etc.; or, a sub-block based merging mode (Sub-block based merging mode) formed by the combination of the above-mentioned affine motion model-based fusion mode, ATMVP and/or PLANAR method, etc.
  • Affine AMVP mode inherited control point motion vector prediction method or constructed control point motion vector prediction method
  • ATMVP advanced temporal motion vector prediction
  • inter-frame prediction of the image block to be processed can be applied to unidirectional prediction (forward or backward), bidirectional prediction (forward and backward) or multi-frame prediction.
  • bidirectional prediction generalized bi-prediction (GBi) at the bidirectional prediction block level, or weighted prediction method, can be adopted.
  • GBi generalized bi-prediction
  • the intra-frame prediction unit 254 can be used to perform any combination of the inter-frame prediction techniques described below.
  • embodiments of the present invention may also apply skip mode and/or direct mode.
  • the prediction processing unit 260 can be further used to partition the image block 203 into smaller block partitions or sub-blocks, for example, by iteratively using quad-tree (QT) partitioning, binary-tree (BT) partitioning or triple-tree (TT) partitioning, or any combination thereof, and for performing prediction for each of the block partitions or sub-blocks, for example, wherein the mode selection includes selecting a tree structure of the partitioned image block 203 and selecting a prediction mode to be applied to each of the block partitions or sub-blocks.
  • QT quad-tree
  • BT binary-tree
  • TT triple-tree
  • the inter-frame prediction unit 244 may include a motion estimation (ME) unit (not shown in FIG. 2 ) and a motion compensation unit.
  • the motion estimation unit is used to receive or obtain a picture image block 203 (the current picture image block 203 of the current picture 201) and a decoded picture 231, or at least one or more previously reconstructed blocks, for example, reconstructed blocks of one or more other/different previously decoded pictures 231, and perform motion estimation based on the determined inter-frame prediction mode.
  • a video sequence may include a current picture and a previously decoded picture 31, or in other words, the current picture and the previously decoded picture 31 may be part of a picture sequence forming a video sequence, or form the picture sequence.
  • the encoder 20 may be configured to select a reference block from a plurality of reference blocks of the same or different pictures in a plurality of other pictures (reference images), and provide the reference picture and/or provide an offset (spatial offset) between the position (X, Y coordinates) of the reference block and the position of the current block as an inter-frame prediction parameter to a motion estimation unit (not shown in FIG. 2 ).
  • the offset is also referred to as a motion vector (MV).
  • the motion compensation unit is used to obtain inter-frame prediction parameters and perform inter-frame prediction based on or using the inter-frame prediction parameters to obtain an inter-frame prediction block 245.
  • the motion compensation performed by the motion compensation unit may include retrieving or generating a prediction block (prediction value) based on a motion/block vector determined by motion estimation (possibly performing interpolation to sub-pixel accuracy). Interpolation filtering can generate additional pixel samples from known pixel samples, thereby potentially increasing the number of candidate prediction blocks that can be used to encode the picture block.
  • the motion compensation unit 246 can locate the prediction block pointed to by the motion vector in a reference picture list.
  • the motion compensation unit 246 can also generate syntax elements associated with blocks and video slices for use by the decoder 30 when decoding picture blocks of the video slice.
  • the inter-frame prediction unit 244 may transmit syntax elements to the entropy coding unit 270, and the syntax elements may include, for example, inter-frame prediction parameters (such as indication information of selecting an inter-frame prediction mode for current block prediction after traversing multiple inter-frame prediction modes), the index number of the candidate motion vector list, and optionally also the GBi index number, the reference frame index, etc.
  • inter-frame prediction parameters such as indication information of selecting an inter-frame prediction mode for current block prediction after traversing multiple inter-frame prediction modes
  • the index number of the candidate motion vector list such as indication information of selecting an inter-frame prediction mode for current block prediction after traversing multiple inter-frame prediction modes
  • the GBi index number the GBi index number
  • the reference frame index etc.
  • the inter-frame prediction unit 244 can be used to perform any combination of inter-frame prediction techniques.
  • the intra prediction unit 254 is used to obtain, for example, receive a picture block 203 (current picture block) of the same picture and one or more previously reconstructed blocks, for example, reconstructed adjacent blocks, for intra estimation.
  • the encoder 20 can be used to select an intra prediction mode from a plurality of (predetermined) intra prediction modes.
  • Embodiments of the encoder 20 may be configured to select an intra prediction mode based on an optimization criterion, such as minimum residual (eg, the intra prediction mode that provides a prediction block 255 most similar to the current picture block 203) or minimum rate distortion.
  • an optimization criterion such as minimum residual (eg, the intra prediction mode that provides a prediction block 255 most similar to the current picture block 203) or minimum rate distortion.
  • the intra prediction unit 254 is further configured to determine an intra prediction block 255 based on the intra prediction parameters of the selected intra prediction mode. In any case, after selecting the intra prediction mode for the block, the intra prediction unit 254 is further configured to provide the intra prediction parameters, i.e., information indicating the selected intra prediction mode for the block, to the entropy encoding unit 270. In one example, the intra prediction unit 254 can be configured to perform any combination of intra prediction techniques.
  • the intra prediction unit 254 may transmit a syntax element to the entropy coding unit 270, wherein the syntax element includes an intra prediction parameter (such as indication information of selecting an intra prediction mode for current block prediction after traversing multiple intra prediction modes).
  • the intra prediction parameter may not be carried in the syntax element, and the decoding end 30 may directly use the default prediction mode for decoding.
  • the entropy coding unit 270 is used to apply an entropy coding algorithm or scheme (e.g., a variable length coding (VLC) scheme, a context adaptive VLC (CAVLC) scheme, an arithmetic coding scheme, context adaptive binary arithmetic coding (CABAC), syntax-based context-adaptive binary arithmetic coding (SBAC), probability interval partitioning entropy (PIPE) coding or other entropy coding methods or techniques) to a single or all (or none) of the quantized residual coefficients 209, inter-frame prediction parameters, intra-frame prediction parameters and/or loop filter parameters to obtain encoded picture data 21 that can be output through an output 272 in the form of, for example, encoded coded data 21.
  • the encoded coded data can be transmitted to the decoder 30 or archived for later transmission or retrieval by the decoder 30.
  • Entropy encoding unit 270 may also be used to entropy encode other syntax elements for the current video slice
  • a non-transform based encoder 20 may directly quantize the residual signal without a transform processing unit 206 for certain blocks or frames.
  • the encoder 20 may have a quantization unit 208 and an inverse quantization unit 210 combined into a single unit.
  • the encoder 20 can directly quantize the residual signal without processing by the transform processing unit 206, and accordingly, there is no need to inverse transform.
  • the loop filter 220 is optional, and in the case of lossless compression encoding, the transform processing unit 206, the quantization unit 208, the inverse quantization unit 210 and the inverse transform processing unit 212 are optional. It should be understood that, according to different application scenarios, the inter-frame prediction unit 244 and the intra-frame prediction unit 254 can be selectively enabled.
  • the decoder 30 is configured to receive encoded picture data (e.g., encoded coding data) 21, for example, encoded by the encoder 20, to obtain a decoded picture 231.
  • encoded picture data e.g., encoded coding data
  • the decoder 30 receives video data from the encoder 20, such as encoded video coding data representing picture blocks of an encoded video slice and associated syntax elements.
  • decoder 30 includes an entropy decoding unit 304, an inverse quantization unit 310, an inverse transform processing unit 312, a reconstruction unit 314 (e.g., summer 314), a buffer 316, a loop filter 320, a decoded picture buffer 330, and a prediction processing unit 360.
  • Prediction processing unit 360 may include an inter-prediction unit 344, an intra-prediction unit 354, and a mode selection unit 362.
  • decoder 30 may perform a decoding pass that is generally reciprocal to the encoding pass described with reference to encoder 20 of FIG. 2 .
  • the entropy decoding unit 304 is used to perform entropy decoding on the encoded picture data 21 to obtain, for example, quantized coefficients 309 and/or decoded coding parameters (not shown in FIG. 3 ), such as any one or all of (decoded) inter-frame prediction, intra-frame prediction parameters, loop filter parameters, and/or other syntax elements.
  • the entropy decoding unit 304 is further used to forward the inter-frame prediction parameters, intra-frame prediction parameters, and/or other syntax elements to the prediction processing unit 360.
  • the decoder 30 may receive syntax elements at the video slice level and/or the video block level.
  • the entropy decoding unit 304 is configured to perform entropy decoding on the coded data, thereby generating output symbols for the parameters.
  • the entropy decoding unit 304 can be configured to reconstruct the parameters representing the quantized transform coefficients and side information.
  • the entropy decoding unit 304 can be configured to perform entropy decoding in various ways. Typical entropy decoding techniques include exponential Golomb decoding, Golomb-Rice decoding, context-adaptive binary arithmetic decoding, Huffman decoding, run-length decoding, Lempel-Ziv ("LZ") decoding, dictionary decoding, RANS decoding and ANS decoding, TANS decoding or other variants of ANS decoding, and combinations thereof. In the embodiment of the present application, the entropy decoding unit 304 can perform one or more variants of ANS decoding.
  • the inverse quantization unit 310 may be functionally the same as the inverse quantization unit 110
  • the inverse transform processing unit 312 may be functionally the same as the inverse transform processing unit 212
  • the reconstruction unit 314 may be functionally the same as the reconstruction unit 214
  • the buffer 316 may be functionally the same as the buffer 216
  • the loop filter 320 may be functionally the same as the loop filter 220
  • the decoded picture buffer 330 may be functionally the same as the decoded picture buffer 230.
  • the prediction processing unit 360 may include an inter-frame prediction unit 344 and an intra-frame prediction unit 354, wherein the inter-frame prediction unit 344 may be functionally similar to the inter-frame prediction unit 244, and the intra-frame prediction unit 354 may be functionally similar to the intra-frame prediction unit 254.
  • the prediction processing unit 360 is generally used to perform block prediction and/or obtain a prediction block 365 from the encoded data 21, and receive or obtain prediction related parameters and/or information about the selected prediction mode from, for example, the entropy decoding unit 304 (explicitly or implicitly).
  • the intra-prediction unit 354 of the prediction processing unit 360 is used to generate a prediction block 365 for a picture block of the current video slice based on the signaled intra-prediction mode and data from a previously decoded block of the current frame or picture.
  • the inter-prediction unit 344 e.g., motion compensation unit
  • the prediction block may be generated from one of the reference pictures within one of the reference picture lists. Decoder 30 may construct reference frame lists: List 0 and List 1 using a default construction technique based on the reference pictures stored in DPB 330.
  • the prediction processing unit 360 is configured to determine prediction information for a video block of a current video slice by parsing motion vectors and other syntax elements, and to generate a prediction block for the current video block being decoded using the prediction information.
  • the prediction processing unit 360 uses some of the received syntax elements to determine a prediction mode (e.g., intra-frame or inter-frame prediction) for encoding a video block of a video slice, an inter-frame prediction slice type (e.g., a B slice, a P slice, or a GPB slice), construction information for one or more of a reference picture list for the slice, a motion vector for each inter-frame coded video block of the slice, an inter-frame prediction state for each inter-frame coded video block of the slice, and other information to decode the video block of the current video slice.
  • the syntax elements received by the decoder 30 from the encoded data include syntax elements received in one or more of an adaptive parameter set (APS), a sequence parameter set (SPS),
  • Inverse quantization unit 310 may be used to inverse quantize (i.e., dequantize) quantized transform coefficients provided in the encoded data and decoded by entropy decoding unit 304.
  • the inverse quantization process may include using quantization parameters calculated by encoder 20 for each video block in a video slice to determine a degree of quantization that should be applied and likewise a degree of inverse quantization that should be applied.
  • the inverse transform processing unit 312 is used to apply an inverse transform (eg, an inverse DCT, an inverse integer transform, or a conceptually similar inverse transform process) to the transform coefficients to generate a residual block in the pixel domain.
  • an inverse transform eg, an inverse DCT, an inverse integer transform, or a conceptually similar inverse transform process
  • the reconstruction unit 314 (e.g., the summer 314) is used to add the inverse transform block 313 (i.e., the reconstructed residual block 313) to the prediction block 365 to obtain the reconstructed block 315 in the sample domain, for example, by adding the sample values of the reconstructed residual block 313 to the sample values of the prediction block 365.
  • the loop filter unit 320 (during or after the encoding cycle) is used to filter the reconstructed block 315 to obtain the filtered block 321, so as to smoothly perform pixel conversion or improve video quality.
  • the loop filter unit 320 can be used to perform any combination of the filtering techniques described below.
  • the loop filter unit 320 is intended to represent one or more loop filters, such as a deblocking filter, a sample adaptive offset (sample-adaptiveoffset, SAO) filter or other filters, such as a bilateral filter, an adaptive loop filter (adaptiveloopfilter, ALF), or a sharpening or smoothing filter, or a collaborative filter.
  • SAO sample adaptive offset
  • ALF adaptive loop filter
  • the loop filter unit 320 is shown as an in-loop filter in FIG. 3, in other configurations, the loop filter unit 320 can be implemented as a post-loop filter.
  • decoded video blocks 321 in a given frame or picture are then stored in a decoded picture buffer 330 which stores reference pictures for subsequent motion compensation.
  • Decoder 30 is operable to output decoded picture 31 , eg, via output 332 , for presentation to or viewing by a user.
  • the decoder 30 may be used to decode the compressed encoded data.
  • the decoder 30 may generate an output video stream without the loop filter unit 320.
  • a non-transform based decoder 30 may directly inverse quantize the residual signal without the inverse transform processing unit 312 for certain blocks or frames.
  • the decoder 30 may have the inverse quantization unit 310 and the inverse transform processing unit 312 combined into a single unit.
  • the decoder 30 may be used to implement the data decoding method described in the embodiment corresponding to FIG. 9 below.
  • the processing result of a certain link can be further processed and output to the next link.
  • the processing result of the corresponding link can be further subjected to operations such as Clip or shift.
  • FIG. 4 is a schematic diagram of the structure of a video decoding device 400 (e.g., a video encoding device 400 or a video decoding device 400) provided in an embodiment of the present invention.
  • the video decoding device 400 is suitable for implementing the embodiments described herein.
  • the video decoding device 400 may be a video decoder (e.g., the decoder 30 of FIG. 1A ) or a video encoder (e.g., the encoder 20 of FIG. 1A ).
  • the video decoding device 400 may be one or more components of the decoder 30 of FIG. 1A or the encoder 20 of FIG. 1A .
  • the video decoding device 400 includes: an inlet port 410 and a receiving unit (Rx) 420 for receiving data, a processor, a logic unit or a central processing unit (CPU) 430 for processing data, a transmitter unit (Tx) 440 and an outlet port 450 for transmitting data, and a memory 460 for storing data.
  • the video decoding device 400 may also include an optical-to-electrical conversion component and an electro-optical (EO) component coupled to the inlet port 410, the receiver unit 420, the transmitter unit 440 and the outlet port 450 for the outlet or inlet of an optical signal or an electrical signal.
  • EO electro-optical
  • the processor 430 is implemented by hardware and software.
  • the processor 430 can be implemented as one or more CPU chips, cores (e.g., multi-core processors), FPGAs, ASICs, and DSPs.
  • the processor 430 communicates with the inlet port 410, the receiver unit 420, the transmitter unit 440, the outlet port 450, and the memory 460.
  • the processor 430 includes a decoding module 470 (e.g., an encoding module 470 or a decoding module 470).
  • the encoding/decoding module 470 implements the embodiments disclosed herein to implement the chrominance block prediction method provided by the embodiments of the present invention. For example, the encoding/decoding module 470 implements, processes, or provides various encoding operations.
  • the encoding/decoding module 470 provides substantial improvements to the functions of the video decoding device 400 and affects the conversion of the video decoding device 400 to different states.
  • the encoding/decoding module 470 is implemented by instructions stored in the memory 460 and executed by the processor 430.
  • Memory 460 includes one or more disks, tape drives, and solid-state drives, and can be used as an overflow data storage device to store programs when these programs are selectively executed, and to store instructions and data read during program execution.
  • Memory 460 can be volatile and/or non-volatile, and can be read-only memory (ROM), random access memory (RAM), ternary content-addressable memory (TCAM), and/or static random access memory (SRAM).
  • ROM read-only memory
  • RAM random access memory
  • TCAM ternary content-addressable memory
  • SRAM static random access memory
  • FIG. 5 is a simplified block diagram of an apparatus that can be used as either or both of the source apparatus 12 and the destination apparatus 14 in FIG. 1A according to an exemplary embodiment.
  • the apparatus can implement the technology of the present invention.
  • FIG. 5 is a schematic block diagram of an implementation of an encoding apparatus or a decoding apparatus (hereinafter referred to as a decoding apparatus) according to an embodiment of the present invention.
  • the decoding apparatus may include a processor 510, a memory 530, and a decoder 540. and a bus system 550.
  • the processor and the memory are connected via the bus system, the memory is used to store instructions, and the processor is used to execute the instructions stored in the memory.
  • the memory of the decoding device stores program codes, and the processor can call the program codes stored in the memory to execute various video encoding or decoding methods described in the present invention. To avoid repetition, it will not be described in detail here.
  • the processor 510 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general-purpose processor may be a microprocessor or any conventional processor, etc.
  • the memory 530 may include a read-only memory (ROM) device or a random access memory (RAM) device. Any other suitable type of storage device may also be used as the memory 530.
  • the memory 530 may include code and data 531 accessed by the processor 510 using the bus 550.
  • the memory 530 may further include an operating system 533 and an application 535, which includes at least one program that allows the processor 510 to perform the video encoding or decoding method described in the present invention.
  • the application 535 may include applications 1 to N, which further include a video encoding or decoding application (referred to as a video decoding application) that executes the video encoding or decoding method described in the present invention.
  • the bus system 550 may include, in addition to the data bus, a power bus, a control bus, a status signal bus, etc. However, for the sake of clarity, various buses are labeled as the bus system 550 in the figure.
  • the decoding device may also include one or more output devices, such as a display 570.
  • the display 570 may be a touch-sensitive display that combines a display with a touch-sensitive unit operable to sense touch input.
  • the display 570 may be connected to the processor 510 via the bus 550.
  • processor 510 and memory 530 of the device are illustrated as being integrated in a single unit in FIG. 5 , other configurations may also be used.
  • the operation of the processor 510 may be distributed in a plurality of directly coupled machines (each machine having one or more processors), or distributed in a local area or other network.
  • the memory 530 may be distributed in a plurality of machines, such as a network-based memory or a memory in a plurality of machines running the device.
  • bus 550 of the device may be formed by a plurality of buses.
  • the memory 530 may be directly coupled to other components of the device or may be accessed through a network, and may include a single integrated unit, such as a memory card, or a plurality of units, such as a plurality of memory cards. Therefore, the device may be implemented in a variety of configurations.
  • FIG. 6 is a schematic diagram of an embodiment of a data encoding method provided in an embodiment of the present application.
  • a data encoding method provided in an embodiment of the present application includes:
  • the data encoding method corresponding to Figure 6 can be applied to an encoder based on an asymmetric digital system ANS.
  • the encoder based on ANS can be used as an entropy encoding unit in the data encoding process.
  • the encoder based on the asymmetric digital system ANS will be referred to as the ANS encoder below.
  • the ANS encoder may receive an input symbol stream (including a target symbol), encode the input symbol stream, and output encoded data (or may be referred to as an encoding result) as part of a bit stream.
  • the total number of bits output is less than the total number of bits input, thereby providing a compression effect.
  • the ANS encoder may include an input symbol buffer for storing input symbols to be encoded.
  • the target symbol may be a parameter for a quantized transform coefficient from a media (e.g., video, image, audio, graphic texture), a parameter for other residual data from the media, or other data.
  • the bits (or codewords) obtained by encoding the input symbol stream may include state information and storage bits, wherein the state information s is an integer, supporting operations such as addition, subtraction, multiplication, division, shift, and or non-or the like, and the storage (memory) bit is a first-in-last-out bit stream, supporting writing a specified number of bits (write) and reading a specified number of bits (read) operations. It is necessary to ensure that after any legal number is written to a specific number of bits, the number can be restored by reading the same number of bits. In the case of passing, the encoding order is opposite to the decoding order, for example, reverse encoding and forward decoding.
  • the probability information may include a quantization probability, a probability mass function (PMF), and a cumulative distribution function (CDF) corresponding to each input symbol among multiple input symbols.
  • PMF probability mass function
  • CDF cumulative distribution function
  • the probability mass function PMF of each symbol x is calculated based on the quantized probability: (denoted as P(x)) and the cumulative distribution function CDF (denoted as C(x)).
  • P(x) is the numerator of the quantized probability
  • C(x) is the sum of P(x) of the symbols less than x.
  • the multiple distribution features include a first distribution feature and a second distribution feature, the entropy of the first distribution feature is greater than the entropy of the second distribution feature; the value of the denominator of the quantization probability in the mapping relationship corresponding to the second distribution feature is greater than the denominator of the quantization probability in the mapping relationship corresponding to the first distribution feature.
  • different quantization probability denominators can be used to reduce the coding length.
  • a prediction model and entropy coding can be included.
  • the prediction model can input the original data, output the distribution index and the data to be encoded (such as the target symbol in this application). According to the distribution index, the entropy can be calculated. For a distribution with a smaller entropy, a larger quantization probability denominator can be used.
  • the probability information includes a value of a probability mass function PMF; the value of the PMF is constructed in the following manner: determining the value of the PMF of each symbol in turn among a plurality of symbols, the plurality of symbols including the target symbol; wherein, when determining the value of the PMF of the target symbol, the total value of the remaining PMF excluding the PMF of the determined symbol is multiplied by the probability of the target symbol, and the ratio between the product of the multiplication result and the remaining probability excluding the determined symbol is calculated, and the PMF of the target symbol is determined based on the relationship between the ratio and a preset fifth value.
  • the fifth value is 1, and the relationship is to take a larger value.
  • the remaining total PMF value can be initialized to M and the remaining total probability to 1; all symbols within the value range are sorted in ascending order of probability; for each symbol after sorting: its PMF value is: the remaining total PMF value, multiplied by the probability of this symbol, divided by the remaining total probability, rounded to the larger of 1; the remaining total PMF value is subtracted from the PMF of this symbol, and the remaining total probability is subtracted from the probability of this symbol.
  • the probability information includes a value of a cumulative distribution function CDF; the value of the CDF is constructed in the following manner:
  • the preset order is determined according to the relationship between the PMF values corresponding to multiple symbols, and the multiple symbols include the target symbol; wherein, when the probability distribution corresponding to the probability information of the target symbol is a symmetrical distribution, the preset order is an order staggered along both sides of the peak point in the symmetrical distribution; or, when the probability distribution corresponding to the probability information of the target symbol is a discrete distribution, the preset order is specifically an order from large to small; or, when the probability distribution corresponding to the probability information of the target symbol is a discrete distribution, the preset order is specifically an order from small to large.
  • C(x) 0 at the peak point x
  • the PMF values are accumulated from the peak point to both sides, that is, in the order of x, x-1, x+1, x-2, x+2,... to obtain the CDF value corresponding to each symbol.
  • all symbols within the value range can be sorted from large to small according to the PMF value, recorded as x(0), x(1), x(2), ..., where C(x(0)) of x(0) is 0.
  • the PMF values are accumulated in the order of x(1), x(2), ... to obtain the CDF value corresponding to each symbol.
  • the order from the middle to the two sides can also be x, x+1, x-1, x+2, x-2, ...; when the PMF values are equal, a variety of possible ways can be selected to break the tie, such as index from small to large (from large to small), random seed, etc.
  • the calculation method of PMF and CDF in the embodiment of the present application can ensure that the codeword length is reduced while the memory and delay remain unchanged.
  • a coding table that is, a mapping relationship in the embodiment of the present application, for example, a first mapping relationship.
  • the first mapping relationship may include a symbol and a corresponding bit addend (which may be referred to as first information) and a state addend (which may be referred to as second information).
  • the first information in the first mapping relationship is constructed in the following manner: adding the number of consecutive highest bits of 0 in the PMF value of the target symbol and a preset sixth value; performing a bit shift operation on the sum result of the addition operation, and subtracting the shift result of the bit shift operation from the shift result of the bit shift operation on the PMF value of the target symbol to obtain the first information.
  • the sixth value may be m-31, where m is an integer power of 2 in the denominator of the quantization probability.
  • performing a bit shift operation on the sum result of the addition operation may specifically be performing a bit shift operation on the sum result of the addition operation by m bits to the left
  • performing a bit shift operation on the value of the PMF of the target symbol may specifically be performing a bit shift operation on the value of the PMF of the target symbol by b(x) bits to the left, where b(x) may be the result of the addition operation of the number of consecutive highest bits in the value of the PMF of the target symbol being 0 and a preset sixth value.
  • b(x) clz(P(x)) + m-31.
  • the clz function calculates the number of consecutive 0 bits in the highest bit of a 32-bit integer.
  • the first information in the first mapping relationship is constructed in the following manner: performing a bit shift operation on the sum result of the addition operation, and subtracting the shift result of the bit shift operation from the shift result of the bit shift operation on the numerical value of the PMF of the target symbol, and performing an addition operation on the operation result of the subtraction operation and the numerical value M to obtain the first information, and the probability information includes a quantization probability, and M is the denominator of the quantization probability.
  • bit addend changes from (b(x) ⁇ m)-(P(x) ⁇ b(x))+M to (b(x) ⁇ m)-(P(x) ⁇ b(x)), and the range changes to [-M, (m-1) ⁇ M].
  • a signed integer representation of bits since the bit OR operation is reduced, the operation cost and complexity are reduced.
  • the coding efficiency can be further improved under the premise of adding a small amount of memory. It is suitable for scenarios with higher requirements for coding efficiency.
  • the second information in the first mapping relationship is constructed in the following manner (Method 1): subtracting the value of the CDF of the target symbol from the value of the PMF of the target symbol to obtain the second information.
  • the second information is constructed as follows:
  • the second information in the first mapping relationship is constructed in the following manner (Method 2): subtracting the numerical value of the CDF of the target symbol from the numerical value of the PMF of the target symbol, and adding the result of the subtraction operation to the numerical value M to obtain the second information, wherein the probability information includes a quantization probability, and M is the denominator of the quantization probability.
  • the calculation result of the "state addend” changes from C(x)-P(x) to "if C(x)-P(x) ⁇ 0, then the "state addend” is C(x)-P(x), otherwise it is C(x)-P(x)+M".
  • the value range of the "state addend” is [0,M-1], which can be represented by an m-bit unsigned integer.
  • the addition of one bit or operation increases the calculation overhead, which can further improve the coding efficiency while increasing a small amount of memory. It is suitable for scenarios with higher requirements for coding efficiency.
  • the second information in the first mapping relationship is constructed in the following manner (Method 3): when the result of the subtraction operation of the value of the CDF of the target symbol and the value of the PMF of the target symbol is greater than or equal to 0, the result of the subtraction operation is used as the second information.
  • the second information in the first mapping relationship is constructed in the following manner: when the result of the subtraction operation between the numerical value of the CDF of the target symbol and the numerical value of the PMF of the target symbol is less than 0, the result of the subtraction operation is added to the numerical value M to obtain the second information, and the probability information includes a quantization probability, and M is the denominator of the quantization probability.
  • the calculation result of the "state addend” changes from C(x)-P(x) to "if C(x)-P(x) ⁇ 0, then the "state addend” is C(x)-P(x), otherwise it is C(x)-P(x)+M".
  • the value range of the "state addend” is [0,M-1], which can be represented by an m-bit unsigned integer.
  • Table 3 is a schematic diagram of the first mapping relationship constructed based on the above-mentioned method 2:
  • Table 4 is a schematic diagram of the first mapping relationship constructed based on the above-mentioned method 3:
  • the first information or the second information may represent an integer value, that is, a single integer.
  • the first information may represent an integer value
  • the second information may represent an integer value.
  • the index information in the coding table includes only symbols
  • the mapped objects include only the first information and the second information, which reduces the memory usage in the coding table.
  • mapping relationships may also be configured for different probability distributions.
  • the target symbol is obtained by transforming pixel data of an image
  • the data obtained by transforming pixel data of the image satisfies a preset distribution
  • the transformation is also used to obtain distribution characteristics of the pixel data
  • the distribution characteristics include a mean or a variance
  • the first mapping relationship corresponding to the distribution characteristics can be determined from multiple mapping relationships based on the distribution characteristics.
  • the distribution characteristics can be used as an index to determine the first mapping relationship corresponding to the distribution characteristics from multiple mapping relationships.
  • FIG. 8 is a schematic diagram of an encoding process.
  • the model can include two parts. One is the image data processing module.
  • the model transforms the image data. The distribution of the transformed data is simpler, which is conducive to the entropy coding process.
  • the model can be a neural network, which processes the image data into transformed data and obtains the distribution index of each dimension of the transformed data.
  • the model can also be a preprocessing and quantization process for image color transformation, such as performing YUV and discrete Fourier transform on RGB images to obtain transformed data, and establish specific distribution indexes for these transformed data.
  • the second is to predefine several probability distributions (such as Gaussian distribution with different variances, logistic distribution, etc.), and establish corresponding distribution indexes and coding tables, where the coding table is established based on the calculated discrete PMF and CDF.
  • probability distributions such as Gaussian distribution with different variances, logistic distribution, etc.
  • the corresponding distribution index can be found, and the corresponding encoding table can be found, and entropy coding is used to form the encoded codeword and store it.
  • the codeword can also store basic header files, such as the length and width of the image, and some necessary parameters.
  • the first information and the second information may be combined and stored. After acquiring the combined data, the encoder may restore the first information and the second information based on certain operation rules.
  • an integer value corresponding to the target symbol can be obtained through the first mapping relationship; based on the third operation, the integer value is restored to the first information and the second information, and the first information and the second information are respectively an integer value.
  • multiple integer parameters (at most one of which is a signed integer) can be combined into a single parameter by placing the signed integer on the left, and then storing them bit by bit according to the number of bits of each parameter through shifting and bitwise OR operations; when reading the sign, the respective parameters are restored through shifting and bitwise AND operations.
  • Table 7 is an illustration of a coding table before information merging
  • Table 8 is an illustration of a coding table after information merging
  • Table 9 is a summary of the coding table parameter lengths.
  • the second information update the status information through a second operation to obtain second coded data; wherein the first coded data and the second coded data are used to obtain the coding result of the target symbol, and the first operation and the second operation do not include a division operation.
  • the first coded data may be a storage bit, and the second coded data may be a state s.
  • At least one of the first operation and the second operation may not include a division operation, thereby reducing the computation time. Calculate delay.
  • At least one of the first operation and the second operation may not include a judgment operation, thereby reducing calculation delay.
  • At least one of the first operation and the second operation may not include a binary search operation, thereby reducing calculation latency.
  • the first operation includes: performing an addition operation on the first information and the status information, and performing a bit shift operation on the addition result of the addition operation; selecting a portion of bits from the status information as first encoded data, and the positions of the portion of bits in the status information are determined according to the shift result of the bit shift operation.
  • the second operation includes: an addition operation on the state information and a numerical value M, and a bit shift operation on the addition result of the addition operation; wherein the probability information includes a quantization probability, and M is the denominator of the quantization probability; and an addition operation is performed on the shift result of the bit shift operation and the second information.
  • the binary representation of s as an m-bit unsigned integer can be combined with the stored bits to obtain the encoding result, that is, the codeword.
  • AAABA is encoded as 00101110 using the above method (wherein the first three bits 001 represent the state of 1, and 01110 are storage bits).
  • FIG. 7 is a flowchart illustrating the coding process of constructing a coding table through the above-mentioned method 1 and performing the coding process through the first operation and the second operation introduced above.
  • the second operation may include: performing a bit shift operation on the state information when the state information is initialized to the M; performing an addition operation on the shift result of the bit shift operation and the second information; and performing a subtraction operation on the addition result of the addition operation and the M.
  • AAABA is encoded as 00101110 using the above method (wherein the first three bits 001 represent the state of 1, and 01110 are storage bits).
  • the embodiment of the present application provides a data encoding method, which is applied to an encoder based on an asymmetric digital system ANS, and the method includes: obtaining a target symbol; obtaining first information and second information corresponding to the target symbol through a first mapping relationship; the first information and the second information are obtained according to the probability information corresponding to the target symbol; obtaining first coded data through a first operation according to the first information and the state information of the encoder; updating the state information through a second operation according to the second information to obtain second coded data; wherein the first coded data and the second coded data are used to obtain the coding result of the target symbol, and the first operation and the second operation do not include a division operation.
  • the index information in the coding table only includes symbols
  • the mapped objects only include the first information and the second information, which is equivalent to reducing the memory usage in the coding table and avoiding operations that consume a lot of memory, thereby achieving a balance between memory and latency.
  • the second information includes first sub-information (also referred to as state addend 1), second sub-information (also referred to as state threshold) and third sub-information (also referred to as state addend 2);
  • the first sub-information in the first mapping relationship is constructed in the following manner: performing a subtraction operation on the third value of the target symbol and the value of the PMF of the target symbol to obtain the first sub-information;
  • the second sub-information in the first mapping relationship is constructed by: performing an addition operation on the third value of the target symbol and the first value of the target symbol, and performing a subtraction operation on the result of the addition operation and 1 to obtain the second sub-information;
  • the third sub-information in the first mapping relationship is constructed in the following manner: subtracting the fourth value of the target symbol from the third value of the target symbol, and subtracting the result of the subtraction operation from the first value of the target symbol to obtain the third sub-information.
  • the second operation includes:
  • the operation result of the addition operation is smaller than the second sub-information, the operation result of the addition operation is used as the second encoded data.
  • the above method can be applicable to, but not limited to, unimodal symmetrical distribution (such as Gaussian distribution, logistic distribution, Laplace distribution, etc.) to reduce the coding length, but the coding calculation amount will increase.
  • unimodal symmetrical distribution such as Gaussian distribution, logistic distribution, Laplace distribution, etc.
  • C1(x) is the sum of P1(x) for symbols less than x;
  • C2(x) is the sum of P2(x) for symbols less than x plus all values of P1(x).
  • the following table shows a schematic diagram of a coding table:
  • a codeword may consist of a state s and a storage memory.
  • Codeword Combine s with the stored bits using the binary representation of an m-bit unsigned integer.
  • the first information is stored using 10 bits
  • the first sub-information is stored using 8 bits
  • the second sub-information is stored using 7 bits
  • the third sub-information is stored using 7 bits.
  • the sum of the first values of multiple symbols is 128, and the third sub-information is less than 128.
  • bit addend The "bit addend”, "state addend 1", “state threshold”, and “state addend 2" of each symbol require 10 bits, 8 bits, 7 bits, and 7 bits respectively, for a total of 32 bits.
  • the sum of all P1(x) is exactly 128, and the value of "state addend 2" is always less than 128.
  • bit addend B is an even number between [2, 2048], which requires 12 bits. 10 bits can be used to represent B/2-1.
  • bit addend the "bit addend", "state addend 1", “state threshold”, and “state addend 2" of each symbol require 10 bits, 8 bits, 7 bits, and 7 bits respectively, for a total of 32 bits.
  • the present application also provides a data encoding method, which is applied to an encoder based on an asymmetric digital system ANS, and the method includes: obtaining a first symbol, the sum of the quantization probability corresponding to the first symbol and the quantization probability corresponding to the second symbol is 1, and the difference between the quantization probability corresponding to the first symbol and 1 is less than a threshold, and the difference between the quantization probability corresponding to the second symbol and 0 is less than a threshold; based on the relationship between the numerical size of the state information of the encoder and the numerical value M satisfying a first condition, performing a first operation between the state information and the numerical value M to obtain first encoded data, and updating the state information to 0; based on the relationship between the numerical size of the state information of the encoder and the numerical value M not satisfying the first condition, adding 1 to the state information.
  • the method further includes: acquiring the second symbol; using the state information of the encoder as the first encoded data, and updating the state information to the difference between the value M and 1.
  • the above embodiment can be used for encoding and decoding schemes when there are two symbols and the probability of a single symbol is close to 1.
  • This embodiment does not need to build encoding and decoding tables, so no additional memory is required to store the tables. Assuming there are two symbols a and b, and the probability of symbol a is close to 1, the encoding algorithm is as follows:
  • Compression symbol a If the state s ⁇ M-2, write s-M+2 (0 or 1) to the storage as 1 bit, and then update s to 0; otherwise, update s to s+1;
  • Compress symbol b Write all m bits of s to storage and update s to M-1.
  • FIG. 9 is a schematic diagram of an embodiment of a data decoding method provided in an embodiment of the present application.
  • a data decoding method provided in an embodiment of the present application includes:
  • FIG. 10A is a specific schematic diagram of a data decoding method provided in an embodiment of the present application.
  • the state information (decoding state) may be obtained from the encoding side, or may be state information obtained by updating the state information during the decoding process.
  • the storage bit may be obtained from the encoding side, or may be a storage bit obtained by updating the storage bit during the decoding process.
  • the 902. Determine, based on the first mapping relationship, the first information, the second information and the third information corresponding to the status information; the first information is the target symbol corresponding to the first bit, the target symbol is the decoding result of the first bit, the second information represents the number of bits selected from the storage bits, the third information is used to perform an addition operation with the bits selected from the storage bits according to the third information, the addition operation result is used to update the status information, the updated status information corresponds to the second bit, and the second bit is the bit to be decoded after the first bit.
  • the first mapping relationship described in Figure 6 and the first mapping relationship described in Figure 9 are different mapping relationships.
  • the first mapping relationship described in Figure 9 is a decoding table.
  • the first information can be called a decoding symbol
  • the second information can be called a read bit number
  • the third information can be called a state base.
  • the first information, the second information or the third information is obtained based on probability information;
  • the probability information includes the value of a probability mass function PMF;
  • the value of the PMF is constructed in the following manner: sequentially determining the value of the PMF of each symbol in a plurality of symbols, the plurality of symbols including the target symbol; wherein, when determining the value of the PMF of the target symbol, the total value of the remaining PMF excluding the PMF of the determined symbol is multiplied by the probability of the target symbol, and the ratio between the product of the multiplication result and the remaining probability excluding the determined symbol is calculated, and the PMF of the target symbol is determined based on the relationship between the ratio and a preset value.
  • the first information, the second information or the third information is obtained based on probability information;
  • the probability information includes the value of the cumulative distribution function CDF;
  • the value of the CDF is constructed in the following manner: based on a preset order, the value of the CDF of each symbol is determined in turn, wherein the preset order is determined according to the relationship between the values of PMFs corresponding to multiple symbols, and the multiple symbols include the target symbol; wherein, when the probability distribution corresponding to the probability information of the target symbol is a symmetrical distribution, the preset order is an order staggered along both sides of the peak point in the symmetrical distribution; or, when the probability distribution corresponding to the probability information of the target symbol is a discrete distribution, the preset order is specifically an order from large to small; or, when the probability distribution corresponding to the probability information of the target symbol is a discrete distribution, the preset order is specifically an order from small to large.
  • the first information in the first mapping relationship is constructed in the following manner: x where C(x) ⁇ s ⁇ (C(x)+P(x)) is used as the first information; wherein C represents the value of CDF, P represents the value of PMF, and s represents the state information.
  • the second information in the first mapping relationship is constructed in the following manner: the value of clz(s-C(x)+P(x))+X is used as the second information; wherein, clz represents the number of consecutive bits whose highest bit in the value is 0, and X is a preset fifth value.
  • the third information in the first mapping relationship is constructed in the following manner: performing a bit shift operation on the numerical value of s-C(x)+P(x) to obtain the third information, and the shift amount of the bit shift operation is obtained according to the second information; or performing a bit shift operation on the numerical value of s-C(x)+P(x), and subtracting a numerical value M from the operation result of the bit shift operation to obtain the third information, wherein M is the denominator of the quantization probability, and the shift amount of the bit shift operation is obtained according to the second information.
  • the "decoding symbol” is the value of x that satisfies C(x) ⁇ s ⁇ C(x)+P(x); the value of the "number of bits read” is clz(s-C(x)+P(x))+m-31; the value of the "state cardinality” is the result of shifting the "number of bits read” left by s-C(x)+P(x), the difference between this and M.
  • Table 10 is a schematic diagram of a decoding table obtained using the above method:
  • the first information, the second information or the third information represents an integer value, that is, a single integer.
  • the first information may represent an integer value
  • the second information may represent an integer value
  • the third information may represent an integer value.
  • the index information in the decoding table only includes symbols
  • the mapped objects only include the first information, the second information and the third information, which reduces the memory usage in the encoding table.
  • mapping relationships may also be configured for different probability distributions.
  • a coding result can be obtained; the coding result is obtained by encoding pixel data of an image, and the status information and the storage bits are obtained based on the coding result; the coding result is processed, and the distribution characteristics of the pixel data include a mean or a variance; based on the distribution characteristics, the first mapping relationship corresponding to the distribution characteristics is determined from multiple mapping relationships.
  • FIG. 10B is a schematic diagram of a decoding process.
  • the model consists of three parts.
  • the first is to decode the header file in the codeword, such as the length and width of the image, some necessary parameters, etc. These parameters can establish the distribution index corresponding to the decoded data (transformed data) for the information in the codeword.
  • the second is to predefine several probability distributions (such as Gaussian distribution with different variances, logistic distribution, etc.), and establish corresponding distribution indexes and decoding tables, where the encoding table is established based on the calculated discrete PMF and CDF.
  • probability distributions such as Gaussian distribution with different variances, logistic distribution, etc.
  • the third is the image decoder, which decodes the transformed data and restores the image.
  • the decoder can be a neural network or a post-processing process of image color transformation, such as inverse Fourier transform, YUV to RGB, etc.
  • the model is first used to read the basic configuration in the header file, and the necessary distribution index of the decoded data is established according to the codeword.
  • the decoded data transformed data
  • the corresponding decoding table is found through the distribution index, and the decoded transformed data is obtained by entropy decoding.
  • the model is used to restore the transformed data to the original image.
  • an integer value corresponding to the state information can be obtained through a first mapping relationship; the integer value is restored to the first information, the second information and the third information, and the first information, the second information and the third information are respectively an integer value.
  • decoding symbol For example, "decoding symbol”, "number of read bits” and “state cardinality” can be combined according to the above rules.
  • the first information is a target symbol corresponding to the first bit
  • the target symbol is a decoding result of the first bit
  • the second information indicates the number of bits selected from the stored bits
  • the third information is used to perform an addition operation with the bits selected from the stored bits according to the third information
  • the addition operation result is used to update the state information
  • the updated state information corresponds to the second bit
  • the second bit is a bit to be decoded after the first bit.
  • the selected bits can be removed from the stored bits to obtain updated stored bits.
  • the "decoding symbol”, "read bit number” and “state cardinality” can be obtained by looking up a table according to the current state value; s is updated to: the sum of the number obtained by reading the "read bit number” bits from the storage and the "state cardinality".
  • decoding 00101110 (state 001 represents 1, 01110 is a storage bit), and the decoding result is AAABA.
  • Subtable 1 For each state s, find the "decoding symbol", the method and result are the same as the above decoding process;
  • Subtable 2 For each symbol x, find the "state addend", the method and result are the same as the "state addend" of method 1 described in the above encoding process;
  • Subtable 3 (all distributions share one table): For each integer i ⁇ [1,M ⁇ 2-1], find the “number of state bits” as clz(i)+m-31.
  • Update state s as follows: subtract the "state addend" from the current value of s, shift left by the number of bits of the "state bit number”, add the value of the "state bit number” read from the storage, and take the modulus of M.
  • Table 13 is a schematic diagram of a decoding table obtained using the above method:
  • the embodiment of the present application can achieve a shorter compression time. Compared with rANS, the encoding and decoding time is improved by 3-4 times.
  • the table memory of the embodiment of the present application is smaller. For the total number of symbols X and the number of states M, if each element of the table is stored with 32 bits, the encoding table size is 4X and the decoding table size is 3M; if compressed to 24 bits for storage, the encoding table size is 3X and the decoding table size is 3M.
  • the table memory usage is greatly reduced.
  • the first information in the first mapping relationship is constructed in the following manner:
  • C1 represents the third value corresponding to CDF
  • P1 represents the first value corresponding to PMF
  • C2 represents the fourth value corresponding to CDF
  • P2 represents the second value corresponding to PMF
  • s represents the status information
  • the sum of the first value and the second value is the value of PMF.
  • the second information in the first mapping relationship is constructed in the following manner:
  • clz(s′-C(x)+P(x))+X is used as the second information; wherein clz represents the number of bits whose highest bit is consecutively 0 in the value, X is a preset fifth value, and s′ is obtained as follows:
  • the third information in the first mapping relationship is constructed in the following manner: performing a bit shift operation on the value of s′-C(x)+P(x) to obtain the third information, and the shift amount of the bit shift operation is obtained according to the second information.
  • Decoding symbol is the value of x that satisfies C1(x) ⁇ s ⁇ C1(x)+P1(x) or C2(x) ⁇ s ⁇ C2(x)+P2(x);
  • each decoded symbol may correspond to 1 to 2 consecutive states s.
  • A corresponds to 0 to 2, and 4 to 5.
  • the "decoded symbol”, “number of read bits”, and “state cardinality” can be obtained by looking up the table according to the current state value s; s is updated to: the sum of the number obtained by reading the "number of read bits” bits from the storage and the "state cardinality";
  • the present application also provides a data decoding method, which is applied to a decoder based on an asymmetric digital system ANS, and the method comprises:
  • Acquire state information of the decoder where the state information corresponds to a first bit, and the first bit is a bit currently to be decoded;
  • state information is the difference between the value M and 1, determining that the decoding result of the first bit is a second symbol, and updating the state information to the result of reading the value M bits from the storage;
  • the decoding result of the first bit is determined to be the first symbol; if the status information is 0, the status information is updated to the sum of the difference between the numerical value M and 2 and the value of 1 bit read from the storage; if the status information is not 0, the status information is updated to the difference between the status information and 1; the updated status information corresponds to the second bit, and the second bit is the bit to be decoded after the first bit.
  • the above embodiment is an encoding and decoding scheme for a total of two symbols and when the probability of a single symbol is close to 1.
  • this embodiment does not need to construct encoding and decoding tables, so no additional memory is required to store the tables. Assuming there are two symbols a and b, and the probability of symbol a is close to 1, the encoding algorithm is as follows:
  • Compression symbol a If the state s ⁇ M-2, write s-M+2 (0 or 1) to the storage as 1 bit, and then update s to 0; otherwise, update s to s+1;
  • Compress symbol b Write all m bits of s to storage and update s to M-1.
  • a data encoding device 1100 provided by an embodiment of the present application includes:
  • An acquisition module 1101 is used to acquire a target symbol
  • An encoding module 1102 is configured to obtain first information and second information corresponding to the target symbol through a first mapping relationship; the first information and the second information are obtained according to probability information corresponding to the target symbol;
  • the state information is updated through a second operation to obtain second coded data
  • the first coded data and the second coded data are used to obtain a coding result of the target symbol, and the first operation and the second operation do not include a division operation.
  • step 602 For the specific description of the encoding module 1102, reference may be made to the description of step 602 in the above embodiment, which will not be repeated here.
  • the first information or the second information represents an integer value.
  • the first operation and the second operation do not include a judgment operation.
  • the first operation includes:
  • a portion of bits is selected from the state information as first coded data, and positions of the portion of bits in the state information are determined according to a shift result of the bit shift operation.
  • the second operation includes:
  • the probability information includes a quantization probability
  • M is a denominator of the quantization probability
  • An addition operation is performed on a shift result of the bit shift operation and the second information.
  • the probability information includes a value of a probability mass function PMF; the value of the PMF is constructed in the following manner:
  • the total value of the remaining PMF excluding the PMF of the determined symbol is multiplied by the probability of the target symbol, and the ratio between the product of the multiplication and the remaining probability excluding the determined symbol is calculated. Based on the relationship between the ratio and a preset fifth value, the PMF of the target symbol is determined.
  • the fifth value is 1, and the relationship is to take a larger value.
  • the probability information includes a value of a cumulative distribution function CDF; the value of the CDF is constructed in the following manner:
  • the preset order is an order staggered along both sides of a peak point in the symmetrical distribution
  • the preset order is specifically an order from large to small; or,
  • the preset order is specifically an order from small to large.
  • the target symbol is obtained by transforming pixel data of an image
  • the data obtained by transforming the pixel data of the image satisfies a preset distribution
  • the transformation is further used to obtain a distribution feature of the pixel data
  • the distribution feature includes a mean or a variance
  • the acquisition module is further used to:
  • the first mapping relationship corresponding to the distribution feature is determined from a plurality of mapping relationships.
  • the multiple distribution features include a first distribution feature and a second distribution feature, and the entropy of the first distribution feature is greater than the entropy of the second distribution feature;
  • a value of a denominator of a quantization probability in a mapping relationship corresponding to the second distribution feature is greater than a value of a denominator of a quantization probability in a mapping relationship corresponding to the first distribution feature.
  • the first information in the first mapping relationship is constructed in the following manner:
  • a bit shift operation is performed on the sum result of the addition operation, and a subtraction operation is performed on the shift result of the bit shift operation and the shift result of the bit shift operation on the numerical value of the PMF of the target symbol, and the operation result of the subtraction operation is added to the numerical value M to obtain the first information, wherein the probability information includes a quantization probability, and M is the denominator of the quantization probability.
  • the second information in the first mapping relationship is constructed in the following manner:
  • the second information in the first mapping relationship is constructed in the following manner:
  • the result of the subtraction operation between the numerical value of the CDF of the target symbol and the numerical value of the PMF of the target symbol is less than 0, the result of the subtraction operation is added to the numerical value M to obtain the second information, where the probability information includes a quantization probability, and M is the denominator of the quantization probability.
  • the encoding module is specifically used to:
  • the integer value is restored to the first information and the second information, where the first information and the second information are respectively an integer value.
  • the probability information includes PMF information corresponding to each symbol, the PMF information includes a first value and a second value; the sum of the first value and the second value is the value of the PMF; the probability information also includes CDF information corresponding to each symbol, the CDF information includes a third value and a fourth value; the third value and the fourth value are constructed in the following manner:
  • the fourth value corresponding to each symbol is determined in sequence by accumulation according to the second values and the third values of the plurality of symbols.
  • the second information includes first sub-information, second sub-information and third sub-information
  • the first sub-information in the first mapping relationship is constructed in the following manner: performing a subtraction operation on the third value of the target symbol and the value of the PMF of the target symbol to obtain the first sub-information;
  • the second sub-information in the first mapping relationship is constructed by: performing an addition operation on the third value of the target symbol and the first value of the target symbol, and performing a subtraction operation on the result of the addition operation and 1 to obtain the second sub-information;
  • the third sub-information in the first mapping relationship is constructed in the following manner: subtracting the fourth value of the target symbol from the third value of the target symbol, and subtracting the result of the subtraction operation from the first value of the target symbol to obtain the third sub-information.
  • the second operation includes:
  • An addition operation is performed on the state information and a value M, and a bit shift operation is performed on the addition result of the addition operation; wherein the probability information includes a quantization probability, and M is a denominator of the quantization probability; the shift result of the bit shift operation is The summing operation performed on the first sub-information;
  • the operation result of the addition operation is smaller than the second sub-information, the operation result of the addition operation is used as the second encoded data.
  • the first information is stored using 10 bits
  • the first sub-information is stored using 8 bits
  • the second sub-information is stored using 7 bits
  • the third sub-information is stored using 7 bits.
  • the sum of the first values of multiple symbols is 128, and the third sub-information is less than 128.
  • the present application also provides a data encoding device, which is applied to an encoder based on an asymmetric digital system ANS, and the device comprises:
  • an acquisition module configured to acquire a first symbol, wherein the sum of a quantization probability corresponding to the first symbol and a quantization probability corresponding to the second symbol is 1, and a difference between the quantization probability corresponding to the first symbol and 1 is less than a threshold, and a difference between the quantization probability corresponding to the second symbol and 0 is less than a threshold;
  • An encoding module configured to perform a first operation between the state information and the value M of the encoder to obtain first encoded data, and update the state information to 0 according to a numerical relationship between the state information and the value M of the encoder satisfying a first condition
  • the acquisition module is further used to:
  • the encoding module is further configured to use the state information of the encoder as the first encoding data, and update the state information to a difference between the value M and 1.
  • a data decoding device 1200 provided by an embodiment of the present application includes:
  • An acquisition module 1201 is used to acquire state information of the decoder and a storage bit, wherein the state information corresponds to a first bit, and the first bit is a bit currently to be decoded;
  • the decoding module 1202 is used to determine the first information, the second information and the third information corresponding to the status information according to the first mapping relationship; the first information is the target symbol corresponding to the first bit, the target symbol is the decoding result of the first bit, the second information represents the number of bits selected from the storage bits, the third information is used to perform an addition operation with the bits selected from the storage bits according to the third information, and the addition operation result is used to update the status information, the updated status information corresponds to the second bit, and the second bit is the bit to be decoded after the first bit.
  • decoding module 1202 For the specific description of the decoding module 1202, reference may be made to the description of step 902 in the above embodiment, which will not be repeated here.
  • the decoding module is further used to:
  • the selected bits are removed from the storage bits to obtain updated storage bits.
  • the first information, the second information or the third information represents an integer value.
  • the first information in the first mapping relationship is constructed in the following manner:
  • C represents the value of CDF
  • P represents the value of PMF
  • s represents the state information
  • C1 represents the third value corresponding to CDF
  • P1 represents the first value corresponding to PMF
  • C2 represents the fourth value corresponding to CDF
  • P2 represents the second value corresponding to PMF
  • s represents the status information
  • the sum of the first value and the second value is the value of PMF.
  • the second information in the first mapping relationship is constructed in the following manner:
  • clz(sC(x)+P(x))+X is used as the second information; wherein clz represents the number of consecutive bits of the highest bit in the value being 0, and X is a preset fifth value; or,
  • clz(s′-C(x)+P(x))+X is used as the second information; wherein clz represents the number of bits whose highest bit is consecutively 0 in the value, X is a preset fifth value, and s′ is obtained as follows:
  • the third information in the first mapping relationship is constructed in the following manner:
  • a bit shift operation is performed on the value of s′-C(x)+P(x) to obtain the third information, and the shift amount of the bit shift operation is obtained according to the second information.
  • the first information, the second information, or the third information is obtained according to probability information;
  • the probability information includes a value of a probability mass function PMF; and the value of the PMF is constructed in the following manner:
  • the total value of the remaining PMF excluding the PMF of the determined symbol is multiplied by the probability of the target symbol, and the ratio between the product of the multiplication and the remaining probability excluding the determined symbol is calculated. Based on the relationship between the ratio and the preset value, the PMF of the target symbol is determined.
  • the preset value is 1, and the relationship is to take a larger value.
  • the first information, the second information or the third information is obtained according to probability information;
  • the probability information includes a value of a cumulative distribution function CDF;
  • the value of the CDF is constructed in the following manner:
  • the preset order is an order staggered along both sides of a peak point in the symmetrical distribution
  • the preset order is specifically an order from large to small; or,
  • the preset order is specifically an order from small to large.
  • the acquisition module is further used to:
  • the coding result is obtained by encoding pixel data of an image, and the state information and the storage bit are obtained according to the coding result;
  • the distribution characteristics of the pixel data including mean or variance
  • the first mapping relationship corresponding to the distribution feature is determined from a plurality of mapping relationships.
  • the present application also provides a data decoding device, which is applied to a decoder based on an asymmetric digital system ANS, and the device comprises:
  • An acquisition module configured to acquire state information of the decoder, wherein the state information corresponds to a first bit, and the first bit is a bit currently to be decoded;
  • a decoding module configured to determine, if the state information is a difference between a value M and 1, that a decoding result of the first bit is a second symbol, and update the state information to a result of reading the value M bits from a storage;
  • the decoding result of the first bit is determined to be the first symbol; if the status information is 0, the status information is updated to the sum of the difference between the numerical value M and 2 and the value of 1 bit read from the storage; if the status information is not 0, the status information is updated to the difference between the status information and 1; the updated status information corresponds to the second bit, and the second bit is the bit to be decoded after the first bit.
  • Figure 13 is a structural schematic diagram of an execution device provided by an embodiment of the present application.
  • the execution device 1300 can be specifically expressed as a mobile phone, a tablet, a laptop computer, an intelligent wearable device, a server, etc., which is not limited here. Among them, the execution device 1300 implements the function of the data encoding and decoding method in the corresponding embodiments of Figures 6 and 9.
  • the execution device 1300 includes: a receiver 1301, a transmitter 1302, a processor 1303 and a memory 1304 (wherein the number of processors 1303 in the execution device 1300 can be one or more), wherein the processor 1303 may include an application processor 13031 and a communication processor 13032.
  • the receiver 1301, the transmitter 1302, the processor 1303 and the memory 1304 may be connected via a bus or other means.
  • the memory 1304 may include a read-only memory and a random access memory, and provides instructions and data to the processor 1303. A portion of the memory 1304 may also include a non-volatile random access memory (NVRAM).
  • NVRAM non-volatile random access memory
  • the memory 1304 stores processor and operation instructions, executable modules or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions may include various operation instructions for implementing various operations.
  • the processor 1303 controls the operation of the execution device.
  • the various components of the execution device are coupled together through a bus system, wherein the bus system includes not only a data bus but also a power bus, a control bus, and a status signal bus, etc.
  • the bus system includes not only a data bus but also a power bus, a control bus, and a status signal bus, etc.
  • various buses are referred to as bus systems in the figure.
  • the method disclosed in the above embodiment of the present application can be applied to the processor 1303, or implemented by the processor 1303.
  • the processor 1303 can be an integrated circuit chip with signal processing capabilities.
  • each step of the above method can be completed by the hardware integrated logic circuit or software instructions in the processor 1303.
  • the above processor 1303 can be a general-purpose processor, a digital signal processor (digital signal processing, DSP), a microprocessor or a microcontroller, and a vision processor (vision processing unit, VPU), a tensor processor (tensor processing unit, TPU) and other processors suitable for AI computing, and can further include an application specific integrated circuit (application specific integrated circuit, ASIC), a field programmable gate array (field-programmable gate array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • the processor 1303 can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application.
  • the general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.
  • the steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor, or a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc.
  • the storage medium is located in the memory 1304, and the processor 1303 reads the information in the memory 1304, and combines its hardware to complete the data encoding and decoding method in the above-mentioned embodiment of Figure 6 and the corresponding embodiment of Figure 9.
  • the receiver 1301 can be used to receive input digital or character information and generate signal input related to the relevant settings and function control of the execution device.
  • the transmitter 1302 can be used to output digital or character information through the first interface; the transmitter 1302 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group; the transmitter 1302 can also include a display device such as a display screen.
  • FIG 14 is a schematic diagram of a structure of a server provided by the embodiment of the present application, specifically, the server 1400 is implemented by one or more servers, and the server 1400 may have relatively large differences due to different configurations or performances, and may include one or more central processing units (CPU) 1414 (for example, one or more processors) and memory 1432, one or more storage media 1430 (for example, one or more mass storage devices) storing application programs 1442 or data 1444.
  • the memory 1432 and the storage medium 1430 can be short-term storage or permanent storage.
  • the program stored in the storage medium 1430 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations in the server. Furthermore, the central processor 1414 can be configured to communicate with the storage medium 1430 and execute a series of instruction operations in the storage medium 1430 on the server 1400.
  • the server 1400 may also include one or more power supplies 1426, one or more wired or wireless network interfaces 1450, one or more input and output interfaces 1458; or, one or more operating systems 1441, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, etc.
  • operating systems 1441 such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, etc.
  • the server may perform the steps related to model training in the above embodiments.
  • the present application also provides a computer program product which, when executed on a computer, enables the computer to execute the steps in FIG. And the data encoding and decoding method in the embodiment corresponding to FIG. 9 .
  • a computer-readable storage medium is also provided in an embodiment of the present application.
  • the computer-readable storage medium stores a program for signal processing.
  • the program When the program is run on a computer, the computer executes the data encoding and decoding method in the corresponding embodiments of Figures 6 and 9.
  • the execution device, training device or terminal device provided in the embodiments of the present application may specifically be a chip, and the chip includes: a processing unit and a communication unit, wherein the processing unit may be, for example, a processor, and the communication unit may be, for example, an input/output interface, a pin or a circuit, etc.
  • the processing unit may execute the computer execution instructions stored in the storage unit so that the chip in the execution device executes the data processing method described in the above embodiment, or so that the chip in the training device executes the data processing method described in the above embodiment.
  • the storage unit is a storage unit in the chip, such as a register, a cache, etc.
  • the storage unit may also be a storage unit located outside the chip in the wireless access device end, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM), etc.
  • ROM read-only memory
  • RAM random access memory
  • FIG. 15 is a schematic diagram of a structure of a chip provided in an embodiment of the present application.
  • the chip can be expressed as a neural network processor NPU 1500.
  • NPU 1500 is mounted on the host CPU (Host CPU) as a coprocessor, and tasks are assigned by the Host CPU.
  • the core part of the NPU is the operation circuit 1503, which is controlled by the controller 1504 to extract matrix data from the memory and perform multiplication operations.
  • NPU 1500 can implement the data encoding and decoding methods in the corresponding embodiments of Figures 6 and 9 through the mutual cooperation between various internal devices.
  • the operation circuit 1503 in the NPU 1500 includes multiple processing units (Process Engine, PE) inside.
  • the operation circuit 1503 is a two-dimensional systolic array.
  • the operation circuit 1503 can also be a one-dimensional systolic array or other electronic circuits capable of performing mathematical operations such as multiplication and addition.
  • the operation circuit 1503 is a general-purpose matrix processor.
  • the operation circuit takes the corresponding data of matrix B from the weight memory 1502 and caches it on each PE in the operation circuit.
  • the operation circuit takes the matrix A data from the input memory 1501 and performs matrix operation with matrix B, and the partial result or final result of the matrix is stored in the accumulator 1508.
  • Unified memory 1506 is used to store input data and output data. Weight data is directly transferred to weight memory 1502 through Direct Memory Access Controller (DMAC) 1505. Input data is also transferred to unified memory 1506 through DMAC.
  • DMAC Direct Memory Access Controller
  • BIU stands for Bus Interface Unit, that is, the bus interface unit 1510, which is used for the interaction between AXI bus and DMAC and instruction fetch buffer (IFB) 1509.
  • IOB instruction fetch buffer
  • the bus interface unit 1510 (Bus Interface Unit, BIU for short) is used for the instruction fetch memory 1509 to obtain instructions from the external memory, and is also used for the storage unit access controller 1505 to obtain the original data of the input matrix A or the weight matrix B from the external memory.
  • BIU Bus Interface Unit
  • DMAC is mainly used to transfer input data in the external memory DDR to the unified memory 1506 or to transfer weight data to the weight memory 1502 or to transfer input data to the input memory 1501.
  • the vector calculation unit 1507 includes multiple operation processing units, which further process the output of the operation circuit 1503 when necessary, such as vector multiplication, vector addition, exponential operation, logarithmic operation, size comparison, etc. It is mainly used for non-convolutional/fully connected layer network calculations in neural networks, such as Batch Normalization, pixel-level summation, upsampling of feature planes, etc.
  • the vector calculation unit 1507 can store the processed output vector to the unified memory 1506.
  • the vector calculation unit 1507 can apply a linear function; or a nonlinear function to the output of the operation circuit 1503, such as linear interpolation of the feature plane extracted by the convolution layer, and then, for example, a vector of accumulated values to generate an activation value.
  • the vector calculation unit 1507 generates a normalized value, a pixel-level summed value, or both.
  • the processed output vector can be used as an activation input to the operation circuit 1503, for example, for use in a subsequent layer in a neural network.
  • An instruction fetch buffer 1509 connected to the controller 1504 is used to store instructions used by the controller 1504;
  • Unified memory 1506, input memory 1501, weight memory 1502 and instruction fetch memory 1509 are all on-chip memories. External memories are private to the NPU hardware architecture.
  • the processor mentioned in any of the above places can be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more An integrated circuit for controlling the execution of the above program.
  • the device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.
  • the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines.
  • the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer floppy disk, a U disk, a mobile hard disk, a ROM, a RAM, a magnetic disk or an optical disk, etc., including a number of instructions to enable a computer device (which can be a personal computer, a training device, or a network device, etc.) to execute the methods described in each embodiment of the present application.
  • a computer device which can be a personal computer, a training device, or a network device, etc.
  • all or part of the embodiments may be implemented by software, hardware, firmware or any combination thereof.
  • all or part of the embodiments may be implemented in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium.
  • the computer instructions may be transmitted from a website site, a computer, a training device, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, training device, or data center.
  • the computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device, a data center, etc. that includes one or more available media integrations.
  • the available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc.
  • a magnetic medium e.g., a floppy disk, a hard disk, a tape
  • an optical medium e.g., a DVD
  • a semiconductor medium e.g., a solid-state drive (SSD)

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Abstract

一种数据编解码方法，应用于数据编解码领域，方法包括：获取目标符号；通过第一映射关系，得到目标符号对应的第一信息和第二信息；第一信息和第二信息为根据目标符号对应的概率信息得到；根据第一信息以及编码器的状态信息，通过第一运算，得到第一编码数据；根据第二信息，通过第二运算，更新状态信息，得到第二编码数据；其中，第一编码数据和第二编码数据用于得到目标符号的编码结果，且第一运算和第二运算不包括除法运算。本申请中，编码表中的索引信息仅包括符号，且映射的对象仅包括第一信息和第二信息，相当于降低了编码表中内存占用，且避免了消耗较大的操作，实现内存与时延的平衡。

Description

一种数据编解码方法及相关装置
本申请要求于2023年01月09日提交国家知识产权局、申请号为202310028884.0、发明名称为“一种数据编解码方法及相关装置”的中国专利申请的优先权，和要求于2023年03月22日提交国家知识产权局、申请号为202310295323.7、发明名称为“一种数据编解码方法及相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据编解码领域，尤其涉及数据编解码方法及其相关装置。
背景技术
人工智能(artificial intelligence，AI)是利用数字计算机或者数字计算机控制的机器模拟、延伸和扩展人的智能，感知环境、获取知识并使用知识获得最佳结果的理论、方法、技术及应用系统。换句话说，人工智能是计算机科学的一个分支，它企图了解智能的实质，并生产出一种新的能以人类智能相似的方式作出反应的智能机器。人工智能也就是研究各种智能机器的设计原理与实现方法，使机器具有感知、推理与决策的功能。
媒体压缩通常包括预测、频率变换和量化的一个或多个阶段，随后是熵编码。对应的媒体解压缩通常包括熵解码，随后是逆量化、逆频率变换和预测的一个或多个阶段。通常，熵编码通过利用输入符号中的冗余(例如，利用具有共同值的许多输入符号和具有罕见值的多个输入符号的模式)将输入符号转换成具有较低比特率的编码数据。熵解码将编码数据转换成对应于输入符号的输出符号。存在熵编码/解码的许多变型，其在压缩效率和计算复杂度方面提供不同的折衷。例如，霍夫曼编码/解码在计算上是简单的，但是对于输入符号的值的某些分布具有较差的压缩效率。另一方面，算术编码/解码通常具有好得多的压缩效率，代价是高得多的计算复杂度。
非对称数字系统(ANS)编码/解码潜在地提供了高的压缩效率和低的计算复杂度。然而现有基于ANS的编码有除法、取余操作、判断，解码有二分查找操作，均耗时较长。且编码和解码过程中使用的编码表、解码表的项目过多，在AI压缩等分布较多的场景上，用于编码表、解码表占用的内存消耗很大。
发明内容
本申请提供了一种数据编码方法以及数据解码方法，可以实现内存与时延的平衡。
第一方面，本申请提供了一种数据编码方法，所述方法包括：获取目标符号；通过第一映射关系，得到所述目标符号对应的第一信息和第二信息；所述第一信息和所述第二信息为根据所述目标符号对应的概率信息得到；根据所述第一信息以及所述编码器的状态信息，通过第一运算，得到第一编码数据；根据所述第二信息，通过第二运算，更新所述状态信息，得到第二编码数据；其中，所述第一编码数据和所述第二编码数据用于得到所述目标符号的编码结果，且所述第一运算和所述第二运算不包括除法运算。
本申请中，编码表中的索引信息仅包括符号，且映射的对象仅包括第一信息和第二信息，相当于降低了编码表中内存占用，且避免了消耗较大的操作，实现内存与时延的平衡。
在一种可能的实现中，所述第一信息或所述第二信息表示一个整数数值。
在一种可能的实现中，所述第一运算和所述第二运算不包括判断运算。
在一种可能的实现中，所述第一运算包括：对所述第一信息与所述状态信息进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；从所述状态信息中选择部分比特作为第一编码数据，所述部分比特在所述状态信息中的位置为根据所述比特移位操作的移位结果确定。
在一种可能的实现中，所述第二运算包括：对所述状态信息与数值M进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；其中，所述概率信息包括量化概率，所述M为所述量化概率的分母；对所述比特移位操作的移位结果与所述第二信息进行的加和操作。
在一种可能的实现中，所述概率信息包括概率质量函数PMF的数值；所述PMF的数值为通过如下方式构建的：依次确定多个符号中每个符号的PMF的数值，所述多个符号包括所述目标符号；其中，
在确定所述目标符号的PMF的数值时，将除去已确定的符号的PMF之外的剩余PMF的总数值与所述目标符号的概率进行乘积，并计算所述乘积的乘积结果与除去已确定的符号的剩余概率之间的比值，根据所述比值与预设的第五数值之间的关系，确定所述目标符号的PMF。
在一种可能的实现中，所述第五数值为1，所述关系为取较大值。
在一种可能的实现中，所述概率信息包括累积分布函数CDF的数值；所述CDF的数值为通过如下方式构建的：基于预设顺序，依次确定每个符号的CDF的数值，其中所述预设顺序为根据多个符号对应的PMF的数值之间的关系确定，所述多个符号包括所述目标符号；其中，在所述目标符号的概率信息对应的概率分布为对称分布时，所述预设顺序为沿着所述对称分布中峰值点的两侧相交错的顺序；或者，在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从大到小的顺序；或者，在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从小到大的顺序。
在一种可能的实现中，所述目标符号为对图像的像素数据进行变换得到，所述对图像的像素数据进行变换得到的数据满足预设分布，所述变换还用于得到所述像素数据的分布特征，所述分布特征包括均值或方差，所述方法还包括：根据所述分布特征，从多个映射关系中确定与所述分布特征对应的所述第一映射关系。
在一种可能的实现中，所述多个分布特征包括第一分布特征和第二分布特征，所述第一分布特征的熵大于所述第二分布特征的熵；所述第二分布特征对应的映射关系中的量化概率的分母的数值大于所述第一分布特征对应的映射关系中的量化概率的分母。
在多分布场景下，可以采用不同的量化概率分母，来减小编码长度，在进行数据编码时，可以包括预测模型和熵编码，预测模型可以输入原数据，输出分布索引以及待编码数据(例如本申请中的目标符号)。根据分布索引，可计算出熵。对于越小熵的分布，可以用越大的量化概率分母。
在一种可能的实现中，所述第一映射关系中的所述第一信息为通过如下方式构建的：将所述目标符号的PMF的数值中最高位连续为0的比特数量与预设的第六数值的加和运算；将所述加和运算的加和结果进行比特移位操作，并将所述比特移位操作的移位结果与对所述目标符号的PMF的数值进行比特移位操作的移位结果进行减法操作，得到所述第一信息；或者，将所述加和运算的加和结果进行比特移位操作，并将所述比特移位操作的移位结果与对所述目标符号的PMF的数值进行比特移位操作的移位结果进行减法操作，将所述减法操作的操作结果与数值M进行加和操作，得到所述第一信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
本申请实施例中PMF和CDF的计算方法可以保证在内存、时延不变的前提下，减小码字长度。
在一种可能的实现中，所述第一映射关系中的所述第二信息为通过如下方式构建的：将所述目标符号的CDF的数值和所述目标符号的PMF的数值进行减法运算，得到所述第二信息；或者，将所述目标符号的CDF的数值和所述目标符号的PMF的数值进行减法运算，将所述减法操作的操作结果与数值M进行加和操作，得到所述第二信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
在一种可能的实现中，所述第一映射关系中的所述第二信息为通过如下方式构建的：在所述目标符号的CDF的数值和所述目标符号的PMF的数值的减法运算的结果大于或等于0时，将所述减法运算的结果作为所述第二信息；或者，在所述目标符号的CDF的数值和所述目标符号的PMF的数值的减法运算的结果小于0时，将所述减法操作的操作结果与数值M进行加和操作，得到所述第二信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
在一种可能的实现中，为了进一步降低内存的占用，可以将第一信息和第二信息合并后存储，编码器可以在获取到合并的数据后，基于一定的运算规则还原得到第一信息和第二信息。
在一种可能的实现中，可以通过第一映射关系，得到所述目标符号对应的一个整数数值；基于第三运算，将所述整数数值还原为所述第一信息和所述第二信息，所述第一信息和所述第二信息分别为一个整数数值。通过上述方式，可减小内存消耗；减小内存读取时间，在部分硬件设备(如服务器)上可进一步提升吞吐率。
示例性的，可以将多整数参数(其中至多一个为有符号整数)合并成单个参数。方法为：将有符号整数放在最左边，之后通过移位、及比特或操作，按各自参数的比特数依次按比特存储；读取符号时，再通过移位、比特与操作，还原出各自参数。
在一种可能的实现中，所述概率信息包括每个符号对应的PMF信息，所述PMF信息包括第一数值和第二数值；所述第一数值和所述第二数值的加和为所述PMF的数值；所述概率信息还包括每个符号对应的CDF信息，所述CDF信息包括第三数值和第四数值；所述第三数值和第四数值为通过如下方式构建的：
基于预设顺序，根据多个符号的第一数值，通过累加依次确定每个符号的对应的第三数值；
基于所述预设顺序，根据多个符号的第二数值和第三数值，通过累加依次确定每个符号对应的第四数值。
在一种可能的实现中，所述第二信息包括第一子信息(也可以称之为状态加数1)、第二子信息(也可以称之为状态阈值)和第三子信息(也可以称之为状态加数2)；
所述第一映射关系中的所述第一子信息为通过如下方式构建的：将所述目标符号的第三数值和所述目标符号的PMF的数值进行减法运算，得到所述第一子信息；
所述第一映射关系中的所述第二子信息为通过如下方式构建的：将所述目标符号的第三数值和所述目标符号的第一数值进行加法运算，将所述加法运算的操作结果与1进行减法操作，得到所述第二子信息；
所述第一映射关系中的所述第三子信息为通过如下方式构建的：将所述目标符号的第四数值和所述目标符号的第三数值进行减法运算，将所述减法运算的操作结果与所述目标符号的第一数值进行减法操作，得到所述第三子信息。
在一种可能的实现中，所述第二运算包括：
对所述状态信息与数值M进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；其中，所述概率信息包括量化概率，所述M为所述量化概率的分母；对所述比特移位操作的移位结果与所述第一子信息进行的加和操作；
在所述加和操作的操作结果大于所述第二子信息时，将所述加和操作的操作结果与所述第三子信息的加和结果作为所述第二编码数据；
在所述加和操作的操作结果小于所述第二子信息时，将所述加和操作的操作结果作为所述第二编码数据。
上述方式可以但不限于适用于单峰对称分布(如高斯分布，逻辑斯谛分布，拉普拉斯分布等)，用于减小编码长度，但编码计算量会提升。
在一种可能的实现中，在所述数值M为256时，所述第一信息通过10比特存储，所述第一子信息通过8比特存储，所述第二子信息通过7比特存储，所述第三子信息通过7比特存储，多个符号的第一数值的加和为128，所述第三子信息小于128。
本申请还提供了一种数据编码方法，应用于基于非对称数字系统ANS的编码器，所述方法包括：获取第一符号，所述第一符号对应的量化概率和第二符号对应的量化概率的和为1，且所述第一符号对应的量化概率和1的差异小于阈值，所述第二符号对应的量化概率和0的差异小于阈值；根据所述编码器的状态信息和数值M之间的数值大小关系满足第一条件，将所述状态信息和所述数值M之间进行第一运算，得到第一编码数据，并将所述状态信息更新为0；根据所述编码器的状态信息和数值M之间的数值大小关系不满足所述第一条件，将所述状态信息加1。
在一种可能的实现中，所述方法还包括：获取所述第二符号；将所述编码器的状态信息作为第一编码数据，并将所述状态信息更新为所述数值M与1的差值。
上述实施例可以针对于共两种符号，且单一符号概率接近1时的编、解码方案。此实施例无需构建编码、解码表，因此无需额外内存存储表格。
第二方面，本申请提供了一种数据解码方法，所述方法包括：获取所述解码器的状态信息以及存储 比特，所述状态信息与第一比特相对应，所述第一比特为当前待解码的比特；根据第一映射关系，确定所述状态信息对应的第一信息、第二信息以及第三信息；所述第一信息为所述第一比特对应的目标符号，所述目标符号为所述第一比特的解码结果，所述第二信息表示从所述存储比特中选择的比特位数，所述第三信息用于和根据所述第三信息从所述存储比特中选择的比特进行加和运算，所述加和运算结果用于更新所述状态信息，更新后的状态信息与第二比特相对应，所述第二比特为所述第一比特之后的待解码比特。
在一种可能的实现中，所述方法还包括：从所述存储比特中剔除根据所述选择的比特，得到更新后的存储比特。
在一种可能的实现中，所述第一信息、所述第二信息或所述第三信息表示一个整数数值。
在一种可能的实现中，所述第一映射关系中的所述第一信息为通过如下方式构建的：将满足C(x)≤s＜(C(x)+P(x))的x作为所述第一信息；其中，所述C表示CDF的数值，所述P表示PMF的数值，所述s表示所述状态信息。
在一种可能的实现中，所述第一映射关系中的所述第一信息为通过如下方式构建的：
将满足C1(x)≤s＜C1(x)+P1(x)或C2(x)≤s＜C2(x)+P2(x)的x作为所述第一信息；其中，所述C1表示CDF对应的第三数值，所述P1表示PMF对应的第一数值，所述C2表示CDF对应的第四数值，所述P2表示PMF对应的第二数值，所述s表示所述状态信息；所述第一数值和所述第二数值的加和为所述PMF的数值。
在一种可能的实现中，所述第一映射关系中的所述第二信息为通过如下方式构建的：
将clz(s′-C(x)+P(x))+X的数值作为所述第二信息；其中，所述clz表示取数值中最高位连续为0的比特数量，所述X为预设的第五数值，所述s′为通过如下得到：
若C2(x)≤s，则s’＝P1(x)+s-C2(x)+P(x)，否则s’＝s-C1(x)+P(x)。
在一种可能的实现中，所述第一映射关系中的所述第三信息为通过如下方式构建的：将s′-C(x)+P(x)的数值进行比特移位操作，得到所述第三信息，所述比特移位操作的移位数量为根据所述第二信息得到。
一种可能的实现中，所述第一映射关系中的所述第二信息为通过如下方式构建的：将clz(s-C(x)+P(x))+X的数值作为所述第二信息；其中，所述clz表示取数值中最高位连续为0的比特数量，所述X为预设的第五数值。
在一种可能的实现中，所述第一映射关系中的所述第三信息为通过如下方式构建的：
将s-C(x)+P(x)的数值进行比特移位操作，得到所述第三信息，所述比特移位操作的移位数量为根据所述第二信息得到；或者，
将s-C(x)+P(x)的数值进行比特移位操作，并将所述比特移位操作的操作结果减去数值M，得到所述第三信息，所述M为所述量化概率的分母，所述比特移位操作的移位数量为根据所述第二信息得到。
在一种可能的实现中，所述第一信息、所述第二信息或所述第三信息为根据概率信息得到；所述概率信息包括概率质量函数PMF的数值；所述PMF的数值为通过如下方式构建的：依次确定多个符号中每个符号的PMF的数值，所述多个符号包括所述目标符号；其中，在确定所述目标符号的PMF的数值时，将除去已确定的符号的PMF之外的剩余PMF的总数值与所述目标符号的概率进行乘积，并计算所述乘积的乘积结果与除去已确定的符号的剩余概率之间的比值，根据所述比值与预设数值之间的关系，确定所述目标符号的PMF。
在一种可能的实现中，所述预设数值为1，所述关系为取较大值。
在一种可能的实现中，所述第一信息、所述第二信息或所述第三信息为根据概率信息得到；所述概率信息包括累积分布函数CDF的数值；所述CDF的数值为通过如下方式构建的：
基于预设顺序，依次确定每个符号的CDF的数值，其中所述预设顺序为根据多个符号对应的PMF的数值之间的关系确定，所述多个符号包括所述目标符号；其中，
在所述目标符号的概率信息对应的概率分布为对称分布时，所述预设顺序为沿着所述对称分布中峰值点的两侧相交错的顺序；或者，
在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从大到小的顺序； 或者，
在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从小到大的顺序。
在一种可能的实现中，所述方法还包括：
获取编码结果；所述编码结果为对图像的像素数据进行编码得到的，所述状态信息以及所述存储比特为根据所述编码结果得到；
对所述编码结果进行处理，所述像素数据的分布特征，所述分布特征包括均值或方差；
根据所述分布特征，从多个映射关系中确定与所述分布特征对应的所述第一映射关系。
本申请还提供了一种数据解码方法，应用于基于非对称数字系统ANS的解码器，所述方法包括：
获取所述解码器的状态信息，所述状态信息与第一比特相对应，所述第一比特为当前待解码的比特；
若所述状态信息为数值M与1的差值，则确定所述第一比特的解码结果为第二符号，并将所述状态信息更新为从存储中读取所述数值M位的结果；
若所述状态信息不为数值M与1的差值，则确定所述第一比特的解码结果为第一符号，若所述状态信息为0，则将所述状态信息更新为所述数值M与2的差值与从存储中读出1个比特的值的加和结果；若所述状态信息不为0，则将所述状态信息更新为所述状态信息与1的差值；更新后的状态信息与第二比特相对应，所述第二比特为所述第一比特之后的待解码比特。
第三方面，本申请提供了一种数据编码装置，所述装置包括：
获取模块，用于获取目标符号；
编码模块，用于通过第一映射关系，得到所述目标符号对应的第一信息和第二信息；所述第一信息和所述第二信息为根据所述目标符号对应的概率信息得到；
根据所述第一信息以及所述编码器的状态信息，通过第一运算，得到第一编码数据；
根据所述第二信息，通过第二运算，更新所述状态信息，得到第二编码数据；其中，
所述第一编码数据和所述第二编码数据用于得到所述目标符号的编码结果，且所述第一运算和所述第二运算不包括除法运算。
在一种可能的实现中，所述第一信息或所述第二信息表示一个整数数值。
在一种可能的实现中，所述第一运算和所述第二运算不包括判断运算。
在一种可能的实现中，所述第一运算包括：
对所述第一信息与所述状态信息进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；
从所述状态信息中选择部分比特作为第一编码数据，所述部分比特在所述状态信息中的位置为根据所述比特移位操作的移位结果确定。
在一种可能的实现中，所述第二运算包括：
对所述状态信息与数值M进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；其中，所述概率信息包括量化概率，所述M为所述量化概率的分母；
对所述比特移位操作的移位结果与所述第二信息进行的加和操作。
在一种可能的实现中，所述概率信息包括概率质量函数PMF的数值；所述PMF的数值为通过如下方式构建的：
依次确定多个符号中每个符号的PMF的数值，所述多个符号包括所述目标符号；其中，
在确定所述目标符号的PMF的数值时，将除去已确定的符号的PMF之外的剩余PMF的总数值与所述目标符号的概率进行乘积，并计算所述乘积的乘积结果与除去已确定的符号的剩余概率之间的比值，根 据所述比值与预设的第五数值之间的关系，确定所述目标符号的PMF。
在一种可能的实现中，所述第五数值为1，所述关系为取较大值。
在一种可能的实现中，所述概率信息包括累积分布函数CDF的数值；所述CDF的数值为通过如下方式构建的：
基于预设顺序，依次确定每个符号的CDF的数值，其中所述预设顺序为根据多个符号对应的PMF的数值之间的关系确定，所述多个符号包括所述目标符号；其中，
在所述目标符号的概率信息对应的概率分布为对称分布时，所述预设顺序为沿着所述对称分布中峰值点的两侧相交错的顺序；或者，
在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从大到小的顺序；或者，
在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从小到大的顺序。
在一种可能的实现中，所述目标符号为对图像的像素数据进行变换得到，所述对图像的像素数据进行变换得到的数据满足预设分布，所述变换还用于得到所述像素数据的分布特征，所述分布特征包括均值或方差，所述获取模块，还用于：
根据所述分布特征，从多个映射关系中确定与所述分布特征对应的所述第一映射关系。
在一种可能的实现中，所述多个分布特征包括第一分布特征和第二分布特征，所述第一分布特征的熵大于所述第二分布特征的熵；
所述第二分布特征对应的映射关系中的量化概率的分母的数值大于所述第一分布特征对应的映射关系中的量化概率的分母。
在一种可能的实现中，所述第一映射关系中的所述第一信息为通过如下方式构建的：
将所述目标符号的PMF的数值中最高位连续为0的比特数量与预设的第六数值的加和运算；
将所述加和运算的加和结果进行比特移位操作，并将所述比特移位操作的移位结果与对所述目标符号的PMF的数值进行比特移位操作的移位结果进行减法操作，得到所述第一信息；或者，
将所述加和运算的加和结果进行比特移位操作，并将所述比特移位操作的移位结果与对所述目标符号的PMF的数值进行比特移位操作的移位结果进行减法操作，将所述减法操作的操作结果与数值M进行加和操作，得到所述第一信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
在一种可能的实现中，所述第一映射关系中的所述第二信息为通过如下方式构建的：
将所述目标符号的CDF的数值和所述目标符号的PMF的数值进行减法运算，得到所述第二信息；或者，
将所述目标符号的CDF的数值和所述目标符号的PMF的数值进行减法运算，将所述减法操作的操作结果与数值M进行加和操作，得到所述第二信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
在一种可能的实现中，所述第一映射关系中的所述第二信息为通过如下方式构建的：
在所述目标符号的CDF的数值和所述目标符号的PMF的数值的减法运算的结果大于或等于0时，将所述减法运算的结果作为所述第二信息；或者，
在所述目标符号的CDF的数值和所述目标符号的PMF的数值的减法运算的结果小于0时，将所述减法操作的操作结果与数值M进行加和操作，得到所述第二信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
在一种可能的实现中，所述编码模块，具体用于：
通过第一映射关系，得到所述目标符号对应的一个整数数值；
基于第三运算，将所述整数数值还原为所述第一信息和所述第二信息，所述第一信息和所述第二信息分别为一个整数数值。
在一种可能的实现中，所述概率信息包括每个符号对应的PMF信息，所述PMF信息包括第一数值和第二数值；所述第一数值和所述第二数值的加和为所述PMF的数值；所述概率信息还包括每个符号对应的CDF信息，所述CDF信息包括第三数值和第四数值；所述第三数值和第四数值为通过如下方式构建的：
基于预设顺序，根据多个符号的第一数值，通过累加依次确定每个符号的对应的第三数值；
基于所述预设顺序，根据多个符号的第二数值和第三数值，通过累加依次确定每个符号对应的第四数值。
在一种可能的实现中，所述第二信息包括第一子信息、第二子信息和第三子信息；
所述第一映射关系中的所述第一子信息为通过如下方式构建的：将所述目标符号的第三数值和所述目标符号的PMF的数值进行减法运算，得到所述第一子信息；
所述第一映射关系中的所述第二子信息为通过如下方式构建的：将所述目标符号的第三数值和所述目标符号的第一数值进行加法运算，将所述加法运算的操作结果与1进行减法操作，得到所述第二子信息；
所述第一映射关系中的所述第三子信息为通过如下方式构建的：将所述目标符号的第四数值和所述目标符号的第三数值进行减法运算，将所述减法运算的操作结果与所述目标符号的第一数值进行减法操作，得到所述第三子信息。
在一种可能的实现中，所述第二运算包括：
对所述状态信息与数值M进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；其中，所述概率信息包括量化概率，所述M为所述量化概率的分母；对所述比特移位操作的移位结果与所述第一子信息进行的加和操作；
在所述加和操作的操作结果大于所述第二子信息时，将所述加和操作的操作结果与所述第三子信息的加和结果作为所述第二编码数据；
在所述加和操作的操作结果小于所述第二子信息时，将所述加和操作的操作结果作为所述第二编码数据。
在一种可能的实现中，在所述数值M为256时，所述第一信息通过10比特存储，所述第一子信息通过8比特存储，所述第二子信息通过7比特存储，所述第三子信息通过7比特存储，多个符号的第一数值的加和为128，所述第三子信息小于128。
本申请还提供了一种数据编码装置，应用于基于非对称数字系统ANS的编码器，所述装置包括：
获取模块，用于获取第一符号，所述第一符号对应的量化概率和第二符号对应的量化概率的和为1，且所述第一符号对应的量化概率和1的差异小于阈值，所述第二符号对应的量化概率和0的差异小于阈值；
编码模块，用于根据所述编码器的状态信息和数值M之间的数值大小关系满足第一条件，将所述状态信息和所述数值M之间进行第一运算，得到第一编码数据，并将所述状态信息更新为0；
根据所述编码器的状态信息和数值M之间的数值大小关系不满足所述第一条件，将所述状态信息加1；
在一种可能的实现中，所述获取模块，还用于：
获取所述第二符号；
所述编码模块，还用于将所述编码器的状态信息作为第一编码数据，并将所述状态信息更新为所述 数值M与1的差值。
第四方面，本申请提供了一种数据解码装置，所述装置包括：
获取模块，用于获取所述解码器的状态信息以及存储比特，所述状态信息与第一比特相对应，所述第一比特为当前待解码的比特；
解码模块，用于根据第一映射关系，确定所述状态信息对应的第一信息、第二信息以及第三信息；所述第一信息为所述第一比特对应的目标符号，所述目标符号为所述第一比特的解码结果，所述第二信息表示从所述存储比特中选择的比特位数，所述第三信息用于和根据所述第三信息从所述存储比特中选择的比特进行加和运算，所述加和运算结果用于更新所述状态信息，更新后的状态信息与第二比特相对应，所述第二比特为所述第一比特之后的待解码比特。
在一种可能的实现中，所述解码模块，还用于：
从所述存储比特中剔除根据所述选择的比特，得到更新后的存储比特。
在一种可能的实现中，所述第一信息、所述第二信息或所述第三信息表示一个整数数值。
在一种可能的实现中，所述第一映射关系中的所述第一信息为通过如下方式构建的：
将满足C(x)≤s＜(C(x)+P(x))的x作为所述第一信息；其中，所述C表示CDF的数值，所述P表示PMF的数值，所述s表示所述状态信息；或者，
将满足C1(x)≤s＜C1(x)+P1(x)或C2(x)≤s＜C2(x)+P2(x)的x作为所述第一信息；其中，所述C1表示CDF对应的第三数值，所述P1表示PMF对应的第一数值，所述C2表示CDF对应的第四数值，所述P2表示PMF对应的第二数值，所述s表示所述状态信息；所述第一数值和所述第二数值的加和为所述PMF的数值。
在一种可能的实现中，所述第一映射关系中的所述第二信息为通过如下方式构建的：
将clz(s-C(x)+P(x))+X的数值作为所述第二信息；其中，所述clz表示取数值中最高位连续为0的比特数量，所述X为预设的第五数值；或者，
将s-C(x)+P(x)的数值进行比特移位操作，得到所述第三信息，所述比特移位操作的移位数量为根据所述第二信息得到；或者，
将s-C(x)+P(x)的数值进行比特移位操作，并将所述比特移位操作的操作结果减去数值M，得到所述第三信息，所述M为所述量化概率的分母，所述比特移位操作的移位数量为根据所述第二信息得到；或者，
将clz(s′-C(x)+P(x))+X的数值作为所述第二信息；其中，所述clz表示取数值中最高位连续为0的比特数量，所述X为预设的第五数值，所述s′为通过如下得到：
若C2(x)≤s，则s’＝P1(x)+s-C2(x)+P(x)，否则s’＝s-C1(x)+P(x)。
在一种可能的实现中，所述第一映射关系中的所述第三信息为通过如下方式构建的：
将s-C(x)+P(x)的数值进行比特移位操作，得到所述第三信息，所述比特移位操作的移位数量为根据所述第二信息得到；或者，
将s-C(x)+P(x)的数值进行比特移位操作，并将所述比特移位操作的操作结果减去数值M，得到所述第三信息，所述M为所述量化概率的分母，所述比特移位操作的移位数量为根据所述第二信息得到；或者，
将s′-C(x)+P(x)的数值进行比特移位操作，得到所述第三信息，所述比特移位操作的移位数量为根据所述第二信息得到。
在一种可能的实现中，所述第一信息、所述第二信息或所述第三信息为根据概率信息得到；所述概 率信息包括概率质量函数PMF的数值；所述PMF的数值为通过如下方式构建的：
依次确定多个符号中每个符号的PMF的数值，所述多个符号包括所述目标符号；其中，
在确定所述目标符号的PMF的数值时，将除去已确定的符号的PMF之外的剩余PMF的总数值与所述目标符号的概率进行乘积，并计算所述乘积的乘积结果与除去已确定的符号的剩余概率之间的比值，根据所述比值与预设数值之间的关系，确定所述目标符号的PMF。
在一种可能的实现中，所述预设数值为1，所述关系为取较大值。
在一种可能的实现中，所述第一信息、所述第二信息或所述第三信息为根据概率信息得到；所述概率信息包括累积分布函数CDF的数值；所述CDF的数值为通过如下方式构建的：
基于预设顺序，依次确定每个符号的CDF的数值，其中所述预设顺序为根据多个符号对应的PMF的数值之间的关系确定，所述多个符号包括所述目标符号；其中，
在所述目标符号的概率信息对应的概率分布为对称分布时，所述预设顺序为沿着所述对称分布中峰值点的两侧相交错的顺序；或者，
在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从大到小的顺序；或者，
在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从小到大的顺序。
在一种可能的实现中，所述获取模块，还用于：
获取编码结果；所述编码结果为对图像的像素数据进行编码得到的，所述状态信息以及所述存储比特为根据所述编码结果得到；
对所述编码结果进行处理，所述像素数据的分布特征，所述分布特征包括均值或方差；
根据所述分布特征，从多个映射关系中确定与所述分布特征对应的所述第一映射关系。
本申请还提供了一种数据解码装置，应用于基于非对称数字系统ANS的解码器，所述装置包括：
获取模块，用于获取所述解码器的状态信息，所述状态信息与第一比特相对应，所述第一比特为当前待解码的比特；
解码模块，用于若所述状态信息为数值M与1的差值，则确定所述第一比特的解码结果为第二符号，并将所述状态信息更新为从存储中读取所述数值M位的结果；
若所述状态信息不为数值M与1的差值，则确定所述第一比特的解码结果为第一符号，若所述状态信息为0，则将所述状态信息更新为所述数值M与2的差值与从存储中读出1个比特的值的加和结果；若所述状态信息不为0，则将所述状态信息更新为所述状态信息与1的差值；更新后的状态信息与第二比特相对应，所述第二比特为所述第一比特之后的待解码比特。
第五方面，本申请实施例提供了一种数据编码装置，可以包括存储器、处理器以及总线系统，其中，存储器用于存储程序，处理器用于执行存储器中的程序，以执行如上述第一方面任一可选的方法。
第六方面，本申请实施例提供了一种数据解码装置，可以包括存储器、处理器以及总线系统，其中，存储器用于存储程序，处理器用于执行存储器中的程序，以执行如上述第二方面任一可选的方法。
第七方面，本申请实施例提供了一种计算机可读存储介质，计算机可读存储介质中存储有计算机程序，当其在计算机上运行时，使得计算机执行上述第一方面及任一可选的方法、以及上述第二方面任一可选的方法。
第八方面，本申请实施例提供了一种计算机程序产品，包括代码，当代码被执行时，用于实现上述第一方面及任一可选的方法、以及上述第二方面任一可选的方法。
第九方面，本申请提供了一种芯片系统，该芯片系统包括处理器，用于支持执行设备或训练设备实现上述方面中所涉及的功能，例如，发送或处理上述方法中所涉及的数据；或，信息。在一种可能的设计中，芯片系统还包括存储器，所述存储器，用于保存执行设备或训练设备必要的程序指令和数据。该芯片系统，可以由芯片构成，也可以包括芯片和其他分立器件。
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图1A为用于实现本发明实施例的视频译码系统实例的框图；
图1B为用于实现本发明实施例的另一种视频译码系统实例的框图；
图2为用于实现本发明实施例的编码器实例结构的框图；
图3为用于实现本发明实施例的解码器实例结构的框图；
图4为用于实现本发明实施例的视频译码设备实例的框图；
图5为本申请实施例提供的一种数据编码方法的流程示意图；
图6为本申请实施例提供的一种数据编码方法的流程示意图；
图7为本申请实施例提供的一种数据编码方法的流程示意图；
图8为本申请实施例提供的一种数据编码方法的流程示意图；
图9为本申请实施例提供的一种数据解码方法的流程示意图；
图10A为本申请实施例提供的一种数据解码方法的流程示意图；
图10B为本申请实施例提供的一种数据解码方法的流程示意图；
图11为本申请实施例提供的一种数据编码装置的结构示意图；
图12为本申请实施例提供的一种数据解码装置的结构示意图；
图13为本申请实施例提供的一种执行设备的示意图；
图14为本申请实施例提供的一种服务器的示意图；
图15为本申请实施例提供的一种芯片的示意图。
具体实施方式
下面结合本发明实施例中的附图对本发明实施例进行描述。本发明的实施方式部分使用的术语仅用于对本发明的具体实施例进行解释，而非旨在限定本发明。
下面结合附图，对本申请的实施例进行描述。本领域普通技术人员可知，随着技术的发展和新场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的术语在适当情况下可以互换，这仅仅是描述本申请的实施例中对相同属性的对象在描述时所采用的区分方式。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，以便包含一系列单元的过程、方法、系统、产品或设备不必限于那些单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它单元。
本发明实施例中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c，或a-b-c，其中a，b，c可以是单个，也可以是多个。
本申请实施例描述的技术和工具中的许多是参考媒体编码器/解码器系统来说明的，媒体编码器/解码器系统诸如是视频编码器/解码器系统、音频编码器/解码器系统、或纹理编码器/解码器系统。备选地，本申请实施例描述的技术和工具通常可以在用于在编码/解码文本数据或其它类型的数据中使用的数据编码器/解码器系统中实现。
本发明的实施方式部分使用的术语仅用于对本发明的具体实施例进行解释，而非旨在限定本发明。下面先对本发明实施例可能涉及的一些概念进行简单介绍。
应理解，本申请并不局限于视频编解码，还可以是音频、纹理或者是图像编解码，作为示例，下面以视频编解码为例进行说明。
视频编码通常是指处理形成视频或视频序列的图片序列。在视频编码领域，术语“图片(picture)”、“帧(frame)”或“图像(image)”可以用作同义词。本文中使用的视频编码表示视频编码或视频解码。 视频编码在源侧执行，通常包括处理(例如，通过压缩)原始视频图片以减少表示该视频图片所需的数据量，从而更高效地存储和/或传输。视频解码在目的地侧执行，通常包括相对于编码器作逆处理，以重构视频图片。实施例涉及的视频图片“编码”应理解为涉及视频序列的“编码”或“解码”。编码部分和解码部分的组合也称为编解码(编码和解码)。
视频序列包括一系列图像(picture)，图像被进一步划分为切片(slice)，切片再被划分为块(block)。视频编码以块为单位进行编码处理，在一些新的视频编码标准中，块的概念被进一步扩展。比如，在H.264标准中有宏块(macroblock，MB)，宏块可进一步划分成多个可用于预测编码的预测块(partition)。在高性能视频编码(high efficiency video coding，HEVC)标准中，采用编码单元(coding unit，CU)，预测单元(prediction unit，PU)和变换单元(transform unit，TU)等基本概念，从功能上划分了多种块单元，并采用全新的基于树结构进行描述。比如CU可以按照四叉树进行划分为更小的CU，而更小的CU还可以继续划分，从而形成一种四叉树结构，CU是对编码图像进行划分和编码的基本单元。对于PU和TU也有类似的树结构，PU可以对应预测块，是预测编码的基本单元。对CU按照划分模式进一步划分成多个PU。TU可以对应变换块，是对预测残差进行变换的基本单元。然而，无论CU，PU还是TU，本质上都属于块(或称图像块)的概念。本申请实施例中涉及图像块的概念(例如第一图像块和第二图像块)，具体可以参照此处描述。
例如在HEVC中，通过使用表示为编码树的四叉树结构将CTU拆分为多个CU。在CU层级处作出是否使用图片间(时间)或图片内(空间)预测对图片区域进行编码的决策。每个CU可以根据PU拆分类型进一步拆分为一个、两个或四个PU。一个PU内应用相同的预测过程，并在PU基础上将相关信息传输到解码器。在通过基于PU拆分类型应用预测过程获取残差块之后，可以根据类似于用于CU的编码树的其它四叉树结构将CU分割成变换单元(transform unit，TU)。在视频压缩技术最新的发展中，使用四叉树和二叉树(Quad-tree and binary tree，QTBT)分割帧来分割编码块。在QTBT块结构中，CU可以为正方形或矩形形状。
本文中，为了便于描述和理解，可将当前编码图像中待处理的图像块(简称待处理图像块)称为当前块，例如在编码中，待处理图像块指当前正在编码的块；在解码中，待处理图像块指当前正在解码的块。将参考图像中用于对当前块进行预测的已解码的图像块称为参考块，即参考块是为当前块提供参考信号的块，其中，参考信号表示图像块内的像素值。可将参考图像中为当前块提供预测信号的块为预测块，其中，预测信号表示预测块内的像素值或者采样值或者采样信号。例如，在遍历多个参考块以后，找到了最佳参考块，此最佳参考块将为当前块提供预测，此块可称为预测块。
无损视频编码情况下，可以重构原始视频图片，即经重构视频图片具有与原始视频图片相同的质量(假设存储或传输期间没有传输损耗或其它数据丢失)。在有损视频编码情况下，通过例如量化执行进一步压缩，来减少表示视频图片所需的数据量，而解码器侧无法完全重构视频图片，即经重构视频图片的质量相比原始视频图片的质量较低或较差。
H.261的几个视频编码标准属于“有损混合型视频编解码”(即，将样本域中的空间和时间预测与变换域中用于应用量化的2D变换编码结合)。视频序列的每个图片通常分割成不重叠的块集合，通常在块层级上进行编码。换句话说，编码器侧通常在块(视频块)层级处理亦即编码视频，例如，通过空间(图片内)预测和时间(图片间)预测来产生预测块，从当前块(当前处理或待处理的块)减去预测块以获取残差块，在变换域变换残差块并量化残差块，以减少待传输(压缩)的数据量，而解码器侧将相对于编码器的逆处理部分应用于经编码或经压缩块，以重构用于表示的当前块。另外，编码器复制解码器处理循环，使得编码器和解码器生成相同的预测(例如帧内预测和帧间预测)和/或重构，用于处理亦即编码后续块。
下面描述本发明实施例所应用的系统架构。参见图1A，图1A示例性地给出了本发明实施例所应用的视频编码及解码系统10的示意性框图。如图1A所示，视频编码及解码系统10可包括源设备12和目的地设备14，源设备12产生经编码视频数据，因此，源设备12可被称为视频编码装置。目的地设备14可对由源设备12所产生的经编码的视频数据进行解码，因此，目的地设备14可被称为视频解码装置。源设备12、目的地设备14或两个的各种实施方案可包含一或多个处理器以及耦合到所述一或多个处理器的存储器。所述存储器可包含但不限于RAM、ROM、EEPROM、快闪存储器或可用于以可由计算机存取的指令或数据结构的形式存储所要的程序代码的任何其它媒体，如本文所描述。源设备12和目的地设备 14可以包括各种装置，包含桌上型计算机、移动计算装置、笔记型(例如，膝上型)计算机、平板计算机、机顶盒、例如所谓的“智能”电话等电话手持机、电视机、相机、显示装置、数字媒体播放器、视频游戏控制台、车载计算机、无线通信设备或其类似者。
虽然图1A将源设备12和目的地设备14绘示为单独的设备，但设备实施例也可以同时包括源设备12和目的地设备14或同时包括两者的功能性，即源设备12或对应的功能性以及目的地设备14或对应的功能性。在此类实施例中，可以使用相同硬件和/或软件，或使用单独的硬件和/或软件，或其任何组合来实施源设备12或对应的功能性以及目的地设备14或对应的功能性。
源设备12和目的地设备14之间可通过链路13进行通信连接，目的地设备14可经由链路13从源设备12接收经编码视频数据。链路13可包括能够将经编码视频数据从源设备12移动到目的地设备14的一或多个媒体或装置。在一个实例中，链路13可包括使得源设备12能够实时将经编码视频数据直接发射到目的地设备14的一或多个通信媒体。在此实例中，源设备12可根据通信标准(例如无线通信协议)来调制经编码视频数据，且可将经调制的视频数据发射到目的地设备14。所述一或多个通信媒体可包含无线和/或有线通信媒体，例如射频(RF)频谱或一或多个物理传输线。所述一或多个通信媒体可形成基于分组的网络的一部分，基于分组的网络例如为局域网、广域网或全球网络(例如，因特网)。所述一或多个通信媒体可包含路由器、交换器、基站或促进从源设备12到目的地设备14的通信的其它设备。
源设备12包括编码器20，另外可选地，源设备12还可以包括图片源16、图片预处理器18、以及通信接口22。具体实现形态中，所述编码器20、图片源16、图片预处理器18、以及通信接口22可能是源设备12中的硬件部件，也可能是源设备12中的软件程序。分别描述如下：
图片源16，可以包括或可以为任何类别的图片捕获设备，用于例如捕获现实世界图片，和/或任何类别的图片或评论(对于屏幕内容编码，屏幕上的一些文字也认为是待编码的图片或图像的一部分)生成设备，例如，用于生成计算机动画图片的计算机图形处理器，或用于获取和/或提供现实世界图片、计算机动画图片(例如，屏幕内容、虚拟现实(virtual reality，VR)图片)的任何类别设备，和/或其任何组合(例如，实景(augmented reality，AR)图片)。图片源16可以为用于捕获图片的相机或者用于存储图片的存储器，图片源16还可以包括存储先前捕获或产生的图片和/或获取或接收图片的任何类别的(内部或外部)接口。当图片源16为相机时，图片源16可例如为本地的或集成在源设备中的集成相机；当图片源16为存储器时，图片源16可为本地的或例如集成在源设备中的集成存储器。当所述图片源16包括接口时，接口可例如为从外部视频源接收图片的外部接口，外部视频源例如为外部图片捕获设备，比如相机、外部存储器或外部图片生成设备，外部图片生成设备例如为外部计算机图形处理器、计算机或服务器。接口可以为根据任何专有或标准化接口协议的任何类别的接口，例如有线或无线接口、光接口。
其中，图片可以视为像素点(picture element)的二维阵列或矩阵。阵列中的像素点也可以称为采样点。阵列或图片在水平和垂直方向(或轴线)上的采样点数目定义图片的尺寸和/或分辨率。为了表示颜色，通常采用三个颜色分量，即图片可以表示为或包含三个采样阵列。例如在RBG格式或颜色空间中，图片包括对应的红色、绿色及蓝色采样阵列。但是，在视频编码中，每个像素通常以亮度/色度格式或颜色空间表示，例如对于YUV格式的图片，包括Y指示的亮度分量(有时也可以用L指示)以及U和V指示的两个色度分量。亮度(luma)分量Y表示亮度或灰度水平强度(例如，在灰度等级图片中两者相同)，而两个色度(chroma)分量U和V表示色度或颜色信息分量。相应地，YUV格式的图片包括亮度采样值(Y)的亮度采样阵列，和色度值(U和V)的两个色度采样阵列。RGB格式的图片可以转换或变换为YUV格式，反之亦然，该过程也称为色彩变换或转换。如果图片是黑白的，该图片可以只包括亮度采样阵列。本发明实施例中，由图片源16传输至图片处理器的图片也可称为原始图片数据17。
图片预处理器18，用于接收原始图片数据17并对原始图片数据17执行预处理，以获取经预处理的图片19或经预处理的图片数据19。例如，图片预处理器18执行的预处理可以包括整修、色彩格式转换(例如，从RGB格式转换为YUV格式)、调色或去噪。
编码器20(或称编码器20)，用于接收经预处理的图片数据19，采用相关预测模式对经预处理的图片数据19进行处理，从而提供经编码图片数据21(下文将进一步基于图2或图4或图5描述编码器20的结构细节)。在一些实施例中，编码器20可以用于执行后文所描述的各个实施例，以实现本发明所描 述的视频编码方法。
通信接口22，可用于接收经编码图片数据21，并可通过链路13将经编码图片数据21传输至目的地设备14或任何其它设备(如存储器)，以用于存储或直接重构，所述其它设备可为任何用于解码或存储的设备。通信接口22可例如用于将经编码图片数据21封装成合适的格式，例如数据包，以在链路13上传输。
目的地设备14包括解码器30，另外可选地，目的地设备14还可以包括通信接口28、图片后处理器32和显示设备34。分别描述如下：
通信接口28，可用于从源设备12或任何其它源接收经编码图片数据21，所述任何其它源例如为存储设备，存储设备例如为经编码图片数据存储设备。通信接口28可以用于藉由源设备12和目的地设备14之间的链路13或藉由任何类别的网络传输或接收经编码图片数据21，链路13例如为直接有线或无线连接，任何类别的网络例如为有线或无线网络或其任何组合，或任何类别的私网和公网，或其任何组合。通信接口28可以例如用于解封装通信接口22所传输的数据包以获取经编码图片数据21。
通信接口28和通信接口22都可以配置为单向通信接口或者双向通信接口，以及可以用于例如发送和接收消息来建立连接、确认和交换任何其它与通信链路和/或例如经编码图片数据传输的数据传输有关的信息。
解码器30(或称为解码器30)，用于接收经编码图片数据21并提供经解码图片数据31或经解码图片31(下文将进一步基于图3或图4或图5描述解码器30的结构细节)。在一些实施例中，解码器30可以用于执行后文所描述的各个实施例，以实现本发明所描述的视频解码方法。
图片后处理器32，用于对经解码图片数据31(也称为经重构图片数据)执行后处理，以获得经后处理图片数据33。图片后处理器32执行的后处理可以包括：色彩格式转换(例如，从YUV格式转换为RGB格式)、调色、整修或重采样，或任何其它处理，还可用于将将经后处理图片数据33传输至显示设备34。
显示设备34，用于接收经后处理图片数据33以向例如用户或观看者显示图片。显示设备34可以为或可以包括任何类别的用于呈现经重构图片的显示器，例如，集成的或外部的显示器或监视器。例如，显示器可以包括液晶显示器(liquid crystal display，LCD)、有机发光二极管(organic light emitting diode，OLED)显示器、等离子显示器、投影仪、微LED显示器、硅基液晶(liquid crystal on silicon，LCoS)、数字光处理器(digital light processor，DLP)或任何类别的其它显示器。
虽然，图1A将源设备12和目的地设备14绘示为单独的设备，但设备实施例也可以同时包括源设备12和目的地设备14或同时包括两者的功能性，即源设备12或对应的功能性以及目的地设备14或对应的功能性。在此类实施例中，可以使用相同硬件和/或软件，或使用单独的硬件和/或软件，或其任何组合来实施源设备12或对应的功能性以及目的地设备14或对应的功能性。
本领域技术人员基于描述明显可知，不同单元的功能性或图1A所示的源设备12和/或目的地设备14的功能性的存在和(准确)划分可能根据实际设备和应用有所不同。源设备12和目的地设备14可以包括各种设备中的任一个，包含任何类别的手持或静止设备，例如，笔记本或膝上型计算机、移动电话、智能手机、平板或平板计算机、摄像机、台式计算机、机顶盒、电视机、相机、车载设备、显示设备、数字媒体播放器、视频游戏控制台、视频流式传输设备(例如内容服务服务器或内容分发服务器)、广播接收器设备、广播发射器设备等，并可以不使用或使用任何类别的操作系统。
编码器20和解码器30都可以实施为各种合适电路中的任一个，例如，一个或多个微处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application-specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)、离散逻辑、硬件或其任何组合。如果部分地以软件实施所述技术，则设备可将软件的指令存储于合适的非暂时性计算机可读存储介质中，且可使用一或多个处理器以硬件执行指令从而执行本公开的技术。前述内容(包含硬件、软件、硬件与软件的组合等)中的任一者可视为一或多个处理器。
在一些情况下，图1A中所示视频编码及解码系统10仅为示例，本发明的技术可以适用于不必包含编码和解码设备之间的任何数据通信的视频编码设置(例如，视频编码或视频解码)。在其它实例中，数据可从本地存储器检索、在网络上流式传输等。视频编码设备可以对数据进行编码并且将数据存储到存储器，和/或视频解码设备可以从存储器检索数据并且对数据进行解码。在一些实例中，由并不彼此通 信而是仅编码数据到存储器和/或从存储器检索数据且解码数据的设备执行编码和解码。
应理解，编码器20可以部署在终端设备或者云侧的服务器上，解码器30可以部署在终端设备或者云侧的服务器上，编码器20和解码器30也可以共同部署在终端设备或者云侧的服务器上。
在一种场景中，编码器20和解码器30可以部署在终端设备上，编码器20可以对终端设备上的视频进行编码压缩，并基于本申请实施例提供的视频编码方法进行二次压缩(或者称之为增量存储压缩)，并存储压缩后的数据，在需要播放视频时，可以对存储的压缩后的数据进行解码。
在一种场景中，编码器20和解码器30可以部署在多个终端设备上，编码器20可以对终端设备上的视频进行编码压缩，并基于本申请实施例提供的视频编码方法进行二次压缩(或者称之为增量存储压缩)，并将压缩后的数据传输至其他终端设备，其他设备在需要播放视频时，可以对存储的压缩后的数据进行解码。
在一种场景中，编码器20和解码器30可以部署在终端设备和云侧的服务器上，编码器20可以对终端设备上的视频进行编码压缩，并基于本申请实施例提供的视频编码方法进行二次压缩(或者称之为增量存储压缩)，并将压缩后的数据传输至服务器。
参见图1B，图1B是根据一示例性实施例的包含图2的编码器20和/或图3的解码器30的视频译码系统40的实例的说明图。视频译码系统40可以实现本发明实施例的各种技术的组合。在所说明的实施方式中，视频译码系统40可以包含成像设备41、编码器20、解码器30(和/或藉由处理单元46的逻辑电路实施的视频编/解码器)、天线42、一个或多个处理器43、一个或多个存储器44和/或显示设备45。
如图1B所示，成像设备41、天线42、处理单元46、逻辑电路、编码器20、解码器30、处理器43、存储器44和/或显示设备45能够互相通信。如所论述，虽然用编码器20和解码器30绘示视频译码系统40，但在不同实例中，视频译码系统40可以只包含编码器20或只包含解码器30。
在一些实例中，天线42可以用于传输或接收视频数据的经编码编码数据。另外，在一些实例中，显示设备45可以用于呈现视频数据。在一些实例中，逻辑电路可以通过处理单元46实施。处理单元46可以包含专用集成电路(application-specific integrated circuit，ASIC)逻辑、图形处理器、通用处理器等。视频译码系统40也可以包含可选的处理器43，该可选处理器43类似地可以包含专用集成电路(application-specific integrated circuit，ASIC)逻辑、图形处理器、通用处理器等。在一些实例中，逻辑电路可以通过硬件实施，如视频编码专用硬件等，处理器43可以通过通用软件、操作系统等实施。另外，存储器44可以是任何类型的存储器，例如易失性存储器(例如，静态随机存取存储器(Static Random Access Memory，SRAM)、动态随机存储器(Dynamic Random Access Memory，DRAM)等)或非易失性存储器(例如，闪存等)等。在非限制性实例中，存储器44可以由超速缓存内存实施。在一些实例中，逻辑电路可以访问存储器44(例如用于实施图像缓冲器)。在其它实例中，逻辑电路和/或处理单元46可以包含存储器(例如，缓存等)用于实施图像缓冲器等。
在一些实例中，通过逻辑电路实施的编码器20可以包含(例如，通过处理单元46或存储器44实施的)图像缓冲器和(例如，通过处理单元46实施的)图形处理单元。图形处理单元可以通信耦合至图像缓冲器。图形处理单元可以包含通过逻辑电路实施的编码器20，以实施参照图2和/或本文中所描述的任何其它编码器系统或子系统所论述的各种模块。逻辑电路可以用于执行本文所论述的各种操作。
在一些实例中，解码器30可以以类似方式通过逻辑电路实施，以实施参照图3的解码器30和/或本文中所描述的任何其它解码器系统或子系统所论述的各种模块。在一些实例中，逻辑电路实施的解码器30可以包含(通过处理单元2820或存储器44实施的)图像缓冲器和(例如，通过处理单元46实施的)图形处理单元。图形处理单元可以通信耦合至图像缓冲器。图形处理单元可以包含通过逻辑电路实施的解码器30，以实施参照图3和/或本文中所描述的任何其它解码器系统或子系统所论述的各种模块。
在一些实例中，天线42可以用于接收视频数据的经编码编码数据。如所论述，经编码编码数据可以包含本文所论述的与编码视频帧相关的数据、指示符、索引值、模式选择数据等，例如与编码分割相关的数据(例如，变换系数或经量化变换系数，(如所论述的)可选指示符，和/或定义编码分割的数据)。视频译码系统40还可包含耦合至天线42并用于解码经编码编码数据的解码器30。显示设备45用于呈现视频帧。
应理解，本发明实施例中对于参考编码器20所描述的实例，解码器30可以用于执行相反过程。关 于信令语法元素，解码器30可以用于接收并解析这种语法元素，相应地解码相关视频数据。在一些例子中，编码器20可以将语法元素熵编码成经编码视频编码数据。在此类实例中，解码器30可以解析这种语法元素，并相应地解码相关视频数据。
参见图2，图2示出用于实现本发明实施例的编码器20的实例的示意性/概念性框图。在图2的实例中，编码器20包括残差计算单元204、变换处理单元206、量化单元208、逆量化单元210、逆变换处理单元212、重构单元214、缓冲器216、环路滤波器单元220、经解码图片缓冲器(decoded picture buffer，DPB)230、预测处理单元260和熵编码单元270。预测处理单元260可以包含帧间预测单元244、帧内预测单元254和模式选择单元262。帧间预测单元244可以包含运动估计单元和运动补偿单元(未图示)。图2所示的编码器20也可以称为混合型视频编码器或根据混合型视频编解码器的视频编码器。
例如，残差计算单元204、变换处理单元206、量化单元208、预测处理单元260和熵编码单元270形成编码器20的前向信号路径，而例如逆量化单元210、逆变换处理单元212、重构单元214、缓冲器216、环路滤波器220、经解码图片缓冲器(decoded picture buffer，DPB)230、预测处理单元260形成编码器的后向信号路径，其中编码器的后向信号路径对应于解码器的信号路径(参见图3中的解码器30)。
编码器20通过例如输入202，接收图片201或图片201的图像块203，例如，形成视频或视频序列的图片序列中的图片。图像块203也可以称为当前编码块或待处理图像块，图片201可以称为当前图片或待编码图片(尤其是在视频编码中将当前图片与其它图片区分开时，其它图片例如同一视频序列亦即也包括当前图片的视频序列中的先前经编码和/或经解码图片)。
编码器20的实施例可以包括分割单元(图2中未绘示)，用于将图片201分割成多个例如图像块203的块，通常分割成多个不重叠的块。分割单元可以用于对视频序列中所有图片使用相同的块大小以及定义块大小的对应栅格，或用于在图片或子集或图片群组之间更改块大小，并将每个图片分割成对应的块。
在一个实例中，编码器20的预测处理单元260可以用于执行上述分割技术的任何组合。
如图片201，图像块203也是或可以视为具有采样值的采样点的二维阵列或矩阵，虽然其尺寸比图片201小。换句话说，图像块203可以包括，例如，一个采样阵列(例如黑白图片201情况下的亮度阵列)或三个采样阵列(例如，彩色图片情况下的一个亮度阵列和两个色度阵列)或依据所应用的色彩格式的任何其它数目和/或类别的阵列。图像块203的水平和垂直方向(或轴线)上采样点的数目定义图像块203的尺寸。
如图2所示的编码器20用于逐块编码图片201，例如，对每个图像块203执行编码和预测。
残差计算单元204用于基于图片图像块203和预测块265(下文提供预测块265的其它细节)计算残差块205，例如，通过逐样本(逐像素)将图片图像块203的样本值减去预测块265的样本值，以在样本域中获取残差块205。
变换处理单元206用于在残差块205的样本值上应用例如离散余弦变换(discrete cosine transform，DCT)或离散正弦变换(discrete sine transform，DST)的变换，以在变换域中获取变换系数207。变换系数207也可以称为变换残差系数，并在变换域中表示残差块205。
变换处理单元206可以用于应用DCT/DST的整数近似值，例如为HEVC/H.265指定的变换。与正交DCT变换相比，这种整数近似值通常由某一因子按比例缩放。为了维持经正变换和逆变换处理的残差块的范数，应用额外比例缩放因子作为变换过程的一部分。比例缩放因子通常是基于某些约束条件选择的，例如，比例缩放因子是用于移位运算的2的幂、变换系数的位深度、准确性和实施成本之间的平衡等。例如，在解码器30侧通过例如逆变换处理单元212为逆变换(以及在编码器20侧通过例如逆变换处理单元212为对应逆变换)指定具体比例缩放因子，以及相应地，可以在编码器20侧通过变换处理单元206为正变换指定对应比例缩放因子。
量化单元208用于例如通过应用标量量化或向量量化来量化变换系数207，以获取经量化变换系数209。经量化变换系数209也可以称为经量化残差系数209。量化过程可以减少与部分或全部变换系数207有关的位深度。例如，可在量化期间将n位变换系数向下舍入到m位变换系数，其中n大于m。可通过调整量化参数(quantization parameter，QP)修改量化程度。例如，对于标量量化，可以应用不同的标度来实现较细或较粗的量化。较小量化步长对应较细量化，而较大量化步长对应较粗量化。可以通过量化参数(quantization parameter，QP)指示合适的量化步长。例如，量化参数可以为合适的量化步 长的预定义集合的索引。例如，较小的量化参数可以对应精细量化(较小量化步长)，较大量化参数可以对应粗糙量化(较大量化步长)，反之亦然。量化可以包含除以量化步长以及例如通过逆量化210执行的对应的量化或逆量化，或者可以包含乘以量化步长。根据例如HEVC的一些标准的实施例可以使用量化参数来确定量化步长。一般而言，可以基于量化参数使用包含除法的等式的定点近似来计算量化步长。可以引入额外比例缩放因子来进行量化和反量化，以恢复可能由于在用于量化步长和量化参数的等式的定点近似中使用的标度而修改的残差块的范数。在一个实例实施方式中，可以合并逆变换和反量化的标度。或者，可以使用自定义量化表并在例如编码数据中将其从编码器通过信号发送到解码器。量化是有损操作，其中量化步长越大，损耗越大。
逆量化单元210用于在经量化系数上应用量化单元208的逆量化，以获取经反量化系数211，例如，基于或使用与量化单元208相同的量化步长，应用量化单元208应用的量化方案的逆量化方案。经反量化系数211也可以称为经反量化残差系数211，对应于变换系数207，虽然由于量化造成的损耗通常与变换系数不相同。
逆变换处理单元212用于应用变换处理单元206应用的变换的逆变换，例如，逆离散余弦变换(discrete cosine transform，DCT)或逆离散正弦变换(discrete sine transform，DST)，以在样本域中获取逆变换块213。逆变换块213也可以称为逆变换经反量化块213或逆变换残差块213。
重构单元214(例如，求和器214)用于将逆变换块213(即经重构残差块213)添加至预测块265，以在样本域中获取经重构块215，例如，将经重构残差块213的样本值与预测块265的样本值相加。
可选地，例如线缓冲器216的缓冲器单元216(或简称“缓冲器”216)用于缓冲或存储经重构块215和对应的样本值，用于例如帧内预测。在其它的实施例中，编码器可以用于使用存储在缓冲器单元216中的未经滤波的经重构块和/或对应的样本值来进行任何类别的估计和/或预测，例如帧内预测。
例如，编码器20的实施例可以经配置以使得缓冲器单元216不只用于存储用于帧内预测254的经重构块215，也用于环路滤波器单元220(在图2中未示出)，和/或，例如使得缓冲器单元216和经解码图片缓冲器单元230形成一个缓冲器。其它实施例可以用于将经滤波块221和/或来自经解码图片缓冲器230的块或样本(图2中均未示出)用作帧内预测254的输入或基础。
环路滤波器单元220(或简称“环路滤波器”220)用于对经重构块215进行滤波以获取经滤波块221，从而顺利进行像素转变或提高视频质量。环路滤波器单元220旨在表示一个或多个环路滤波器，例如去块滤波器、样本自适应偏移(sample-adaptive offset，SAO)滤波器或其它滤波器，例如双边滤波器、自适应环路滤波器(adaptive loop filter，ALF)，或锐化或平滑滤波器，或协同滤波器。尽管环路滤波器单元220在图2中示出为环内滤波器，但在其它配置中，环路滤波器单元220可实施为环后滤波器。经滤波块221也可以称为经滤波的经重构块221。经解码图片缓冲器230可以在环路滤波器单元220对经重构编码块执行滤波操作之后存储经重构编码块。
编码器20(对应地，环路滤波器单元220)的实施例可以用于输出环路滤波器参数(例如，样本自适应偏移信息)，例如，直接输出或由熵编码单元270或任何其它熵编码单元熵编码后输出，例如使得解码器30可以接收并应用相同的环路滤波器参数用于解码。
熵编码单元270被配置为根据来自量化单元208的输出(例如，量化的变换系数)以及边信息进行熵编码。熵编码单元270可以被配置为确定表示量化的变换系数、边信息等的参数。熵编码单元270可以被配置为基于上下文信息来预测参数的值，然后对实际值和预测值之间的差进行编码。对于表示要被编码的值的目标符号，熵编码单元270可以被配置为以各种方式执行熵编码。典型的熵编码技术包括指数哥伦布(Exponential-Golomb)编码、哥伦布赖斯(Golomb-Rice)编码、上下文自适应二进制算术编码(“CABAC”)、差分编码、霍夫曼编码、游程长度编码、Lempel-Ziv(“LZ”)编码、字典编码、RANS编码、ANS编码、TANS编码或者ANS编码的其它变型、以及上述的组合。本申请实施例中，熵编码单元270可以执行ANS编码的一种或多种变型。
经解码图片缓冲器(decoded picture buffer，DPB)230可以为存储参考图片数据供编码器20编码视频数据之用的参考图片存储器。DPB230可由多种存储器设备中的任一个形成，例如动态随机存储器(dynamic random access memory，DRAM)(包含同步DRAM(synchronous DRAM，SDRAM)、磁阻式RAM(magnetoresistive RAM，MRAM)、电阻式RAM(resistive RAM，RRAM))或其它类型的存储器设备。可 以由同一存储器设备或单独的存储器设备提供DPB230和缓冲器216。在某一实例中，经解码图片缓冲器(decoded picture buffer，DPB)230用于存储经滤波块221。经解码图片缓冲器230可以进一步用于存储同一当前图片或例如先前经重构图片的不同图片的其它先前的经滤波块，例如先前经重构和经滤波块221，以及可以提供完整的先前经重构亦即经解码图片(和对应参考块和样本)和/或部分经重构当前图片(和对应参考块和样本)，例如用于帧间预测。在某一实例中，如果经重构块215无需环内滤波而得以重构，则经解码图片缓冲器(decoded picture buffer，DPB)230用于存储经重构块215。
预测处理单元260，也称为块预测处理单元260，用于接收或获取图像块203(当前图片201的当前图像块203)和经重构图片数据，例如来自缓冲器216的同一(当前)图片的参考样本和/或来自经解码图片缓冲器230的一个或多个先前经解码图片的参考图片数据231，以及用于处理这类数据进行预测，即提供可以为经帧间预测块245或经帧内预测块255的预测块265。
模式选择单元262可以用于选择预测模式(例如帧内或帧间预测模式)和/或对应的用作预测块265的预测块245或255，以计算残差块205和重构经重构块215。
模式选择单元262的实施例可以用于选择预测模式(例如，从预测处理单元260所支持的那些预测模式中选择)，所述预测模式提供最佳匹配或者说最小残差(最小残差意味着传输或存储中更好的压缩)，或提供最小信令开销(最小信令开销意味着传输或存储中更好的压缩)，或同时考虑或平衡以上两者。模式选择单元262可以用于基于码率失真优化(rate distortion optimization，RDO)确定预测模式，即选择提供最小码率失真优化的预测模式，或选择相关码率失真至少满足预测模式选择标准的预测模式。
下文将详细解释编码器20的实例(例如，通过预测处理单元260)执行的预测处理和(例如，通过模式选择单元262)执行的模式选择。
如上文所述，编码器20用于从(预先确定的)预测模式集合中确定或选择最好或最优的预测模式。预测模式集合可以包括例如帧内预测模式和/或帧间预测模式。
在可能的实现中，帧内预测模式集合可以包括多种不同的帧内预测模式，例如，如DC(或均值)模式和平面模式的非方向性模式，或如H.265中定义的方向性模式，或者可以包括67种不同的帧内预测模式，例如，如DC(或均值)模式和平面模式的非方向性模式，或如正在发展中的H.266中定义的方向性模式。
在可能的实现中，帧间预测模式集合取决于可用参考图片(即，例如前述存储在DBP230中的至少部分经解码图片)和其它帧间预测参数，例如取决于是否使用整个参考图片或只使用参考图片的一部分，例如围绕当前块的区域的搜索窗区域，来搜索最佳匹配参考块，和/或例如取决于是否应用如半像素和/或四分之一像素内插的像素内插，帧间预测模式集合例如可包括先进运动矢量(Advanced Motion Vector Prediction，AMVP)模式和融合(merge)模式。具体实施中，帧间预测模式集合可包括本发明实施例所描述的基于仿射运动模型的预测模式，例如基于仿射运动模型的先进运动矢量预测模式(Affine AMVP mode)或者基于仿射运动模型的融合模式(Affine Merge mode)，具体的，基于控制点的AMVP模式(继承的控制点运动矢量预测方法或者构造的控制点运动矢量预测方法)，基于控制点的merge模式(继承的控制点运动矢量预测方法或者构造的控制点运动矢量预测方法)；以及，高级时域运动矢量预测(advanced temporal motion vector prediction，ATMVP)方法，PLANAER方法等等；或者，通过上述仿基于仿射运动模型的融合模式、ATMVP和/或PLANAR方法的综合形成的子块融合模式(Sub-block based merging mode)，等等。本发明实施例中，对待处理推图像块的帧间预测可应用于单向预测(前向或后向)、双向预测(前向和后向)或多帧预测中，当应用于双向预测时，可采用双向预测块级的广义双向预测(Generalized Bi-prediction，GBi)，或称加权预测方法，在一个实例中，帧内预测单元254可以用于执行下文描述的帧间预测技术的任意组合。
除了以上预测模式，本发明实施例也可以应用跳过模式和/或直接模式。
预测处理单元260可以进一步用于将图像块203分割成较小的块分区或子块，例如，通过迭代使用四叉树(quad-tree，QT)分割、二进制树(binary-tree，BT)分割或三叉树(triple-tree，TT)分割，或其任何组合，以及用于例如为块分区或子块中的每一个执行预测，其中模式选择包括选择分割的图像块203的树结构和选择应用于块分区或子块中的每一个的预测模式。
帧间预测单元244可以包含运动估计(motion estimation，ME)单元(图2中未示出)和运动补偿 (motion compensation，MC)单元(图2中未示出)。运动估计单元用于接收或获取图片图像块203(当前图片201的当前图片图像块203)和经解码图片231，或至少一个或多个先前经重构块，例如，一个或多个其它/不同先前经解码图片231的经重构块，基于所确定的帧间预测模式来进行运动估计。例如，视频序列可以包括当前图片和先前经解码图片31，或换句话说，当前图片和先前经解码图片31可以是形成视频序列的图片序列的一部分，或者形成该图片序列。
例如，编码器20可以用于从多个其它图片(参考图像)中的同一或不同图片的多个参考块中选择参考块，并向运动估计单元(图2中未示出)提供参考图片和/或提供参考块的位置(X、Y坐标)与当前块的位置之间的偏移(空间偏移)作为帧间预测参数。该偏移也称为运动向量(motion vector，MV)。
运动补偿单元用于获取帧间预测参数，并基于或使用帧间预测参数执行帧间预测来获取帧间预测块245。由运动补偿单元(图2中未示出)执行的运动补偿可以包含基于通过运动估计(可能执行对子像素精确度的内插)确定的运动/块向量取出或生成预测块(预测值)。内插滤波可从已知像素样本产生额外像素样本，从而潜在地增加可用于编码图片块的候选预测块的数目。一旦接收到用于当前图片块的PU的运动向量，运动补偿单元246可以在一个参考图片列表中定位运动向量指向的预测块。运动补偿单元246还可以生成与块和视频条带相关联的语法元素，以供解码器30在解码视频条带的图片块时使用。
具体的，上述帧间预测单元244可向熵编码单元270传输语法元素，所述语法元素例如包括帧间预测参数(比如遍历多个帧间预测模式后选择用于当前块预测的帧间预测模式的指示信息)、候选运动矢量列表的索引号，可选地还包括GBi索引号、参考帧索引等等。可能应用场景中，如果帧间预测模式只有一种，那么也可以不在语法元素中携带帧间预测参数，此时解码端30可直接使用默认的预测模式进行解码。可以理解的，帧间预测单元244可以用于执行帧间预测技术的任意组合。
帧内预测单元254用于获取，例如接收同一图片的图片块203(当前图片块)和一个或多个先前经重构块，例如经重构相相邻块，以进行帧内估计。例如，编码器20可以用于从多个(预定)帧内预测模式中选择帧内预测模式。
编码器20的实施例可以用于基于优化标准选择帧内预测模式，例如基于最小残差(例如，提供最类似于当前图片块203的预测块255的帧内预测模式)或最小码率失真。
帧内预测单元254进一步用于基于如所选择的帧内预测模式的帧内预测参数确定帧内预测块255。在任何情况下，在选择用于块的帧内预测模式之后，帧内预测单元254还用于向熵编码单元270提供帧内预测参数，即提供指示所选择的用于块的帧内预测模式的信息。在一个实例中，帧内预测单元254可以用于执行帧内预测技术的任意组合。
具体的，上述帧内预测单元254可向熵编码单元270传输语法元素，所述语法元素包括帧内预测参数(比如遍历多个帧内预测模式后选择用于当前块预测的帧内预测模式的指示信息)。可能应用场景中，如果帧内预测模式只有一种，那么也可以不在语法元素中携带帧内预测参数，此时解码端30可直接使用默认的预测模式进行解码。
熵编码单元270用于将熵编码算法或方案(例如，可变长度编码(variable length coding，VLC)方案、上下文自适应VLC(context adaptive VLC，CAVLC)方案、算术编码方案、上下文自适应二进制算术编码(context adaptive binary arithmetic coding，CABAC)、基于语法的上下文自适应二进制算术编码(syntax-based context-adaptive binary arithmetic coding，SBAC)、概率区间分割熵(probability interval partitioning entropy，PIPE)编码或其它熵编码方法或技术)应用于经量化残差系数209、帧间预测参数、帧内预测参数和/或环路滤波器参数中的单个或所有上(或不应用)，以获取可以通过输出272以例如经编码编码数据21的形式输出的经编码图片数据21。可以将经编码编码数据传输到解码器30，或将其存档稍后由解码器30传输或检索。熵编码单元270还可用于熵编码正被编码的当前视频条带的其它语法元素。
编码器20的其它结构变型可用于编码视频流。例如，基于非变换的编码器20可以在没有针对某些块或帧的变换处理单元206的情况下直接量化残差信号。在另一实施方式中，编码器20可具有组合成单个单元的量化单元208和逆量化单元210。
应当理解的是，编码器20的其它的结构变化可用于编码视频流。例如，对于某些图像块或者图像帧，编码器20可以直接地量化残差信号而不需要经变换处理单元206处理，相应地也不需要经逆变换 处理单元212处理；或者，对于某些图像块或者图像帧，编码器20没有产生残差数据，相应地不需要经变换处理单元206、量化单元208、逆量化单元210和逆变换处理单元212处理；或者，编码器20可以将经重构图像块作为参考块直接地进行存储而不需要经滤波器220处理；或者，编码器20中量化单元208和逆量化单元210可以合并在一起。环路滤波器220是可选的，以及针对无损压缩编码的情况下，变换处理单元206、量化单元208、逆量化单元210和逆变换处理单元212是可选的。应当理解的是，根据不同的应用场景，帧间预测单元244和帧内预测单元254可以是被选择性的启用。
参见图3，图3示出用于实现本发明实施例的解码器30的实例的示意性/概念性框图。解码器30用于接收例如由编码器20编码的经编码图片数据(例如，经编码编码数据)21，以获取经解码图片231。在解码过程期间，解码器30从编码器20接收视频数据，例如表示经编码视频条带的图片块的经编码视频编码数据及相关联的语法元素。
在图3的实例中，解码器30包括熵解码单元304、逆量化单元310、逆变换处理单元312、重构单元314(例如求和器314)、缓冲器316、环路滤波器320、经解码图片缓冲器330以及预测处理单元360。预测处理单元360可以包含帧间预测单元344、帧内预测单元354和模式选择单元362。在一些实例中，解码器30可执行大体上与参照图2的编码器20描述的编码遍次互逆的解码遍次。
熵解码单元304用于对经编码图片数据21执行熵解码，以获取例如经量化系数309和/或经解码的编码参数(图3中未示出)，例如，帧间预测、帧内预测参数、环路滤波器参数和/或其它语法元素中(经解码)的任意一个或全部。熵解码单元304进一步用于将帧间预测参数、帧内预测参数和/或其它语法元素转发至预测处理单元360。解码器30可接收视频条带层级和/或视频块层级的语法元素。
熵解码单元304被配置为对编码数据进行熵解码，从而产生针对参数的输出符号。熵解码单元304可以被配置为重建表示量化的变换系数和边信息的参数。熵解码单元304可以被配置为以各种方式来执行熵解码。典型的熵解码技术包括指数哥伦布解码、哥伦布赖斯解码、上下文自适应二进制算术解码、霍夫曼解码、游程长度解码、Lempel-Ziv(“LZ”)解码、字典解码、RANS解码和ANS解码、TANS解码或者ANS解码的其它变型、以及上述的组合。本申请实施例中，熵解码单元304可以执行ANS解码的一种或多种变型。
逆量化单元310功能上可与逆量化单元110相同，逆变换处理单元312功能上可与逆变换处理单元212相同，重构单元314功能上可与重构单元214相同，缓冲器316功能上可与缓冲器216相同，环路滤波器320功能上可与环路滤波器220相同，经解码图片缓冲器330功能上可与经解码图片缓冲器230相同。
预测处理单元360可以包括帧间预测单元344和帧内预测单元354，其中帧间预测单元344功能上可以类似于帧间预测单元244，帧内预测单元354功能上可以类似于帧内预测单元254。预测处理单元360通常用于执行块预测和/或从经编码数据21获取预测块365，以及从例如熵解码单元304(显式地或隐式地)接收或获取预测相关参数和/或关于所选择的预测模式的信息。
当视频条带经编码为经帧内编码(I)条带时，预测处理单元360的帧内预测单元354用于基于信号表示的帧内预测模式及来自当前帧或图片的先前经解码块的数据来产生用于当前视频条带的图片块的预测块365。当视频帧经编码为经帧间编码(即B或P)条带时，预测处理单元360的帧间预测单元344(例如，运动补偿单元)用于基于运动向量及从熵解码单元304接收的其它语法元素生成用于当前视频条带的视频块的预测块365。对于帧间预测，可从一个参考图片列表内的一个参考图片中产生预测块。解码器30可基于存储于DPB330中的参考图片，使用默认建构技术来建构参考帧列表：列表0和列表1。
预测处理单元360用于通过解析运动向量和其它语法元素，确定用于当前视频条带的视频块的预测信息，并使用预测信息产生用于正经解码的当前视频块的预测块。在本发明的一实例中，预测处理单元360使用接收到的一些语法元素确定用于编码视频条带的视频块的预测模式(例如，帧内或帧间预测)、帧间预测条带类型(例如，B条带、P条带或GPB条带)、用于条带的参考图片列表中的一个或多个的建构信息、用于条带的每个经帧间编码视频块的运动向量、条带的每个经帧间编码视频块的帧间预测状态以及其它信息，以解码当前视频条带的视频块。在本公开的另一实例中，解码器30从编码数据接收的语法元素包含接收自适应参数集(adaptive parameter set，APS)、序列参数集(sequence parameter set，SPS)、图片参数集(picture parameter set，PPS)或条带标头中的一个或多个中的语法元素。
逆量化单元310可用于逆量化(即，反量化)在编码数据中提供且由熵解码单元304解码的经量化变换系数。逆量化过程可包含使用由编码器20针对视频条带中的每一视频块所计算的量化参数来确定应该应用的量化程度并同样确定应该应用的逆量化程度。
逆变换处理单元312用于将逆变换(例如，逆DCT、逆整数变换或概念上类似的逆变换过程)应用于变换系数，以便在像素域中产生残差块。
重构单元314(例如，求和器314)用于将逆变换块313(即经重构残差块313)添加到预测块365，以在样本域中获取经重构块315，例如通过将经重构残差块313的样本值与预测块365的样本值相加。
环路滤波器单元320(在编码循环期间或在编码循环之后)用于对经重构块315进行滤波以获取经滤波块321，从而顺利进行像素转变或提高视频质量。在一个实例中，环路滤波器单元320可以用于执行下文描述的滤波技术的任意组合。环路滤波器单元320旨在表示一个或多个环路滤波器，例如去块滤波器、样本自适应偏移(sample-adaptiveoffset，SAO)滤波器或其它滤波器，例如双边滤波器、自适应环路滤波器(adaptiveloopfilter，ALF)，或锐化或平滑滤波器，或协同滤波器。尽管环路滤波器单元320在图3中示出为环内滤波器，但在其它配置中，环路滤波器单元320可实施为环后滤波器。
随后将给定帧或图片中的经解码视频块321存储在存储用于后续运动补偿的参考图片的经解码图片缓冲器330中。
解码器30用于例如，藉由输出332输出经解码图片31，以向用户呈现或供用户查看。
解码器30的其它变型可用于对压缩的编码数据进行解码。例如，解码器30可以在没有环路滤波器单元320的情况下生成输出视频流。例如，基于非变换的解码器30可以在没有针对某些块或帧的逆变换处理单元312的情况下直接逆量化残差信号。在另一实施方式中，解码器30可以具有组合成单个单元的逆量化单元310和逆变换处理单元312。
在具体实施例中，解码器30可用于实现后文图9对应实施例中描述的数据解码方法。
应当理解的是，本发明的编码器20和解码器30中，针对某个环节的处理结果可以经过进一步处理后，输出到下一个环节，例如，在插值滤波、运动矢量推导或环路滤波等环节之后，对相应环节的处理结果可以进一步进行Clip或移位shift等操作。
参见图4，图4是本发明实施例提供的视频译码设备400(例如视频编码设备400或视频解码设备400)的结构示意图。视频译码设备400适于实施本文所描述的实施例。在一个实施例中，视频译码设备400可以是视频解码器(例如图1A的解码器30)或视频编码器(例如图1A的编码器20)。在另一个实施例中，视频译码设备400可以是上述图1A的解码器30或图1A的编码器20中的一个或多个组件。
视频译码设备400包括：用于接收数据的入口端口410和接收单元(Rx)420，用于处理数据的处理器、逻辑单元或中央处理器(CPU)430，用于传输数据的发射器单元(Tx)440和出口端口450，以及，用于存储数据的存储器460。视频译码设备400还可以包括与入口端口410、接收器单元420、发射器单元440和出口端口450耦合的光电转换组件和电光(EO)组件，用于光信号或电信号的出口或入口。
处理器430通过硬件和软件实现。处理器430可以实现为一个或多个CPU芯片、核(例如，多核处理器)、FPGA、ASIC和DSP。处理器430与入口端口410、接收器单元420、发射器单元440、出口端口450和存储器460通信。处理器430包括译码模块470(例如编码模块470或解码模块470)。编码/解码模块470实现本文中所公开的实施例，以实现本发明实施例所提供的色度块预测方法。例如，编码/解码模块470实现、处理或提供各种编码操作。因此，通过编码/解码模块470为视频译码设备400的功能提供了实质性的改进，并影响了视频译码设备400到不同状态的转换。或者，以存储在存储器460中并由处理器430执行的指令来实现编码/解码模块470。
存储器460包括一个或多个磁盘、磁带机和固态硬盘，可以用作溢出数据存储设备，用于在选择性地执行这些程序时存储程序，并存储在程序执行过程中读取的指令和数据。存储器460可以是易失性和/或非易失性的，可以是只读存储器(ROM)、随机存取存储器(RAM)、随机存取存储器(ternary content-addressable memory，TCAM)和/或静态随机存取存储器(SRAM)。
参见图5，图5是根据一示例性实施例的可用作图1A中的源设备12和目的地设备14中的任一个或两个的装置的简化框图。装置可以实现本发明的技术。换言之，图5为本发明实施例的编码设备或解码设备(简称为译码设备)的一种实现方式的示意性框图。其中，译码设备可以包括处理器510、存储器530 和总线系统550。其中，处理器和存储器通过总线系统相连，该存储器用于存储指令，该处理器用于执行该存储器存储的指令。译码设备的存储器存储程序代码，且处理器可以调用存储器中存储的程序代码执行本发明描述的各种视频编码或解码方法。为避免重复，这里不再详细描述。
在本发明实施例中，该处理器510可以是中央处理单元(Central Processing Unit，简称为“CPU”)，该处理器510还可以是其他通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
该存储器530可以包括只读存储器(ROM)设备或者随机存取存储器(RAM)设备。任何其他适宜类型的存储设备也可以用作存储器530。存储器530可以包括由处理器510使用总线550访问的代码和数据531。存储器530可以进一步包括操作系统533和应用程序535，该应用程序535包括允许处理器510执行本发明描述的视频编码或解码方法的至少一个程序。例如，应用程序535可以包括应用1至N，其进一步包括执行在本发明描述的视频编码或解码方法的视频编码或解码应用(简称视频译码应用)。
该总线系统550除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都标为总线系统550。
可选的，译码设备还可以包括一个或多个输出设备，诸如显示器570。在一个示例中，显示器570可以是触感显示器，其将显示器与可操作地感测触摸输入的触感单元合并。显示器570可以经由总线550连接到处理器510。
虽然图5中将装置的处理器510和存储器530绘示为集成在单个单元中，但是还可以使用其它配置。处理器510的运行可以分布在多个可直接耦合的机器中(每个机器具有一个或多个处理器)，或分布在本地区域或其它网络中。存储器530可以分布在多个机器中，例如基于网络的存储器或多个运行装置的机器中的存储器。虽然此处只绘示单个总线，但装置的总线550可以由多个总线形成。进一步地，从存储器530可以直接耦合至装置的其它组件或可以通过网络访问，并且可包括单个集成单元，例如一个存储卡，或多个单元，例如多个存储卡。因此，可以以多种配置实施装置。
参照图6，图6为本申请实施例提供的一种数据编码方法的实施例示意，如图6示出的那样，本申请实施例提供的一种数据编码方法，包括：
601、获取目标符号；
其中，图6对应的数据编码方法可以应用于基于非对称数字系统ANS的编码器，具体的，基于ANS的编码器可以作为数据编码过程中的熵编码单元，为了方便描述，以下将基于非对称数字系统ANS的编码器简称为ANS编码器。
在一种可能的实现中，ANS编码器可以接收输入的符号流(包括目标符号)，对输入符号流进行编码，并且输出编码数据(或者可以称之为编码结果)作为比特流的部分。通常，输出的比特的总数小于输入的比特的总数，从而提供压缩效果。
在一种可能的实现中，ANS编码器可以包括输入符号缓冲器，用于存储待编码的输入符号。以目标符号为例，目标符号可以为来自媒体(例如，视频、图像、音频、图形纹理)的针对量化的变换系数的参数、来自媒体的针对其它残差数据的参数或其它数据。
在一种可能的实现中，对输入符号流编码得到的比特(或者可以称之为码字)可以包括状态信息和存储比特，其中，状态信息s为整数，支持加减乘除、移位、与或非等运算，存储(memory)比特为一个先进后出的比特流，支持写入指定的比特数(write)和读出指定的比特数(read)操作。需保证在将任何合法的数字写入一个特定的比特数后，读出相同的比特数能够恢复此数字。通过情况下，编码顺序与解码顺序相反，例如反向编码，正向解码。
在ANS中，需要计算概率信息，概率信息可以包括多个输入符号中每个输入符号对应的量化概率、概率质量函数(probability mass function，PMF)和累积分布函数(cumulative distribution function，CDF)，具体的，可以基于量化概率计算PMF和CDF。
在一种可能的实现中，可以将每种符号的概率量化成分数，例如，所有量化概率的分母(记为数值M)均相等，且为2的整数次幂(记为M＝2m)。根据量化后的概率计算每种符号x的概率质量函数PMF (记为P(x))及累积分布函数CDF(记为C(x))。其中P(x)为量化概率的分子，在一种可能的实现中，C(x)为小于x的符号的P(x)的加和。
在一种可能的实现中，所述多个分布特征包括第一分布特征和第二分布特征，所述第一分布特征的熵大于所述第二分布特征的熵；所述第二分布特征对应的映射关系中的量化概率的分母的数值大于所述第一分布特征对应的映射关系中的量化概率的分母。
在多分布场景下，可以采用不同的量化概率分母，来减小编码长度，在进行数据编码时，可以包括预测模型和熵编码，预测模型可以输入原数据，输出分布索引以及待编码数据(例如本申请中的目标符号)。根据分布索引，可计算出熵。对于越小熵的分布，可以用越大的量化概率分母。
在编码或者解码时，不同的分布可以采用不同的量化概率分母。具体为，更集中的分布采用更大的量化概率分母。例如：
1.在高斯分布类型下，方差较小的分布利用更大的量化概率分母，方差较大的用的更小的量化概率分母；
2.在逻辑斯谛分布类型下，散布程度较小的分布利用较大的量化概率分母，散布程度较大的分布利用较小的量化概率分母；
3.在拉普拉斯分布类型下，尺度参数较小的分布利用较大的量化概率分母，尺度参数较大的分布利用较小的量化概率分母。
在一种可能的实现中，所述概率信息包括概率质量函数PMF的数值；所述PMF的数值为通过如下方式构建的：依次确定多个符号中每个符号的PMF的数值，所述多个符号包括所述目标符号；其中，在确定所述目标符号的PMF的数值时，将除去已确定的符号的PMF之外的剩余PMF的总数值与所述目标符号的概率进行乘积，并计算所述乘积的乘积结果与除去已确定的符号的剩余概率之间的比值，根据所述比值与预设的第五数值之间的关系，确定所述目标符号的PMF。
在一种可能的实现中，所述第五数值为1，所述关系为取较大值。
示例性的，可以初始化剩余总PMF值为M，剩余总概率为1；将取值范围内的所有符号按概率从小到大排序；对于排序后的每个符号：其PMF值为：剩余总PMF值，乘以此符号的概率，除以剩余总概率，取整后与1取较大者；将剩余总PMF值减去此符号PMF，剩余总概率减去此符号概率。
在一种可能的实现中，所述概率信息包括累积分布函数CDF的数值；所述CDF的数值为通过如下方式构建的：
基于预设顺序，依次确定每个符号的CDF的数值，其中所述预设顺序为根据多个符号对应的PMF的数值之间的关系确定，所述多个符号包括所述目标符号；其中，在所述目标符号的概率信息对应的概率分布为对称分布时，所述预设顺序为沿着所述对称分布中峰值点的两侧相交错的顺序；或者，在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从大到小的顺序；或者，在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从小到大的顺序。
例如，针对于单峰对称分布(例如，高斯分布、拉普拉斯分布、逻辑斯谛分布等)，可以将峰值点x的C(x)＝0，从峰值点向两侧，即x，x-1，x+1，x-2，x+2，...的顺序，对PMF的值做累加，得到每个符号对应的CDF值。
例如，针对于离散分布，可以将取值范围内的所有符号按PMF值从大到小排序，记为x(0)，x(1)，x(2)，…，其中，x(0)的C(x(0))＝0，按x(1)，x(2)，…的顺序，对PMF的值做累加，得到每个符号对应的CDF值。
可选的，在进行CDF的计算时，中间到两边的顺序也可以为x,x+1,x-1,x+2,x-2,...；当PMF值相等时，可选多种可能的方式打破平局，如索引由小到大(由大到小)，随机种子等。
参照表1，表1为一种概率信息的示意。
表1

本申请实施例中PMF和CDF的计算方法可以保证在内存、时延不变的前提下，减小码字长度。
在一种可能的实现中，还需要获取到编码表(也就是本申请实施例中的映射关系，例如，第一映射关系)，接下来以第一映射关系为例介绍如何构建编码表。
在一种可能的实现中，所述第一映射关系可以包括符号以及对应的比特加数(可以称之为第一信息)和状态加数(可以称之为第二信息)。
以符号为目标符号为例，在一种可能的实现中，所述第一映射关系中的所述第一信息为通过如下方式构建的：将所述目标符号的PMF的数值中最高位连续为0的比特数量与预设的第六数值的加和运算；将所述加和运算的加和结果进行比特移位操作，并将所述比特移位操作的移位结果与对所述目标符号的PMF的数值进行比特移位操作的移位结果进行减法操作，得到所述第一信息。
在一种可能的实现中，第六数值可以为m-31，其中，m为量化概率的分母上2的整数次幂。
在一种可能的实现中，将所述加和运算的加和结果进行比特移位操作具体可以为将所述加和运算的加和结果进行向左m位的比特移位操作，对所述目标符号的PMF的数值进行比特移位操作具体可以为对所述目标符号的PMF的数值进行向左b(x)位的比特移位操作，b(x)可以为上述将所述目标符号的PMF的数值中最高位连续为0的比特数量与预设的第六数值的加和运算的加和结果。
示例性的，在构建编码表时，对于每个符号x，构建方法如下(方式1)：
计算出每次编码x，写入存储中的基础比特数b(x)＝clz(P(x))+m-31。其中clz函数计算一个32位整数的最高位的连续为0的比特的数量。
计算比特加数的结果：(b(x)＜＜m)-(P(x)＜＜b(x))+M，范围[0,m×M]，用比特的无符号整数表示。
以符号为目标符号为例，在一种可能的实现中，所述第一映射关系中的所述第一信息为通过如下方式构建的：将所述加和运算的加和结果进行比特移位操作，并将所述比特移位操作的移位结果与对所述目标符号的PMF的数值进行比特移位操作的移位结果进行减法操作，将所述减法操作的操作结果与数值M进行加和操作，得到所述第一信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
示例性的，在构建编码表时，对于每个符号x，第一信息的构建方法如下(方式2)：
“比特加数”的结果相比方式1由(b(x)＜＜m)-(P(x)＜＜b(x))+M变为(b(x)＜＜m)-(P(x)＜＜b(x))，范围改变为[-M,(m-1)×M]，用比特的有符号整数表示；由于减少了必特或运算，降低了运算的开销和复杂度。可在增加少量内存的前提下，进一步提升编码效率。适用于对编码效率要求更高的场景。
在一种可能的实现中，所述第一映射关系中的所述第二信息为通过如下方式构建的(方式1)：将所述目标符号的CDF的数值和所述目标符号的PMF的数值进行减法运算，得到所述第二信息。
示例性的，在构建编码表时，对于每个符号x，第二信息的构建方法如下：
“状态加数”的结果由C(x)-P(x)变为C(x)-P(x)+M，范围改变为[1,M×2-2]，用m+1比特的无符号整数表示。
在一种可能的实现中，所述第一映射关系中的所述第二信息为通过如下方式构建的(方式2)：将所述目标符号的CDF的数值和所述目标符号的PMF的数值进行减法运算，将所述减法操作的操作结果与数值M进行加和操作，得到所述第二信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
示例性的，在构建编码表时，对于每个符号x，第一信息的构建方法如下(方式2)：
“状态加数”的计算结果相比方式1由C(x)-P(x)变为“若C(x)-P(x)≥0，则“状态加数”为C(x)-P(x)，否则为C(x)-P(x)+M”。此时“状态加数”的取值范围为[0,M-1]，可用m比特的无符号整数表示，多一个比特或的运算，提高了计算开销，可在增加少量内存的前提下，进一步提升编码效率。适用于对编码效率要求更高的场景。
在一种可能的实现中，所述第一映射关系中的所述第二信息为通过如下方式构建的(方式3)：在所述目标符号的CDF的数值和所述目标符号的PMF的数值的减法运算的结果大于或等于0时，将所述减法运算的结果作为所述第二信息。通过上述方式，可在编码效率有少量下降的前提下，进一步减小内存消耗。适用于极限省内存场景。
在一种可能的实现中，所述第一映射关系中的所述第二信息为通过如下方式构建的：在所述目标符号的CDF的数值和所述目标符号的PMF的数值的减法运算的结果小于0时，将所述减法操作的操作结果与数值M进行加和操作，得到所述第二信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
示例性的，在构建编码表时，对于每个符号x，第一信息的构建方法如下(方式2)：
“状态加数”的计算结果相比方式1由C(x)-P(x)变为“若C(x)-P(x)≥0，则“状态加数”为C(x)-P(x)，否则为C(x)-P(x)+M”。此时“状态加数”的取值范围为[0,M-1]，可用m比特的无符号整数表示。
参照表2，表2为基于上述方式1构建的第一映射关系的示意：
表2
参照表3，表3为基于上述方式2构建的第一映射关系的示意：
表3
参照表4，表4为基于上述方式3构建的第一映射关系的示意：
表4
在一种可能的实现中，所述第一信息或者所述第二信息可以表示一个整数数值，也就是单一的一个整数，例如，所述第一信息可以表示一个整数数值，第二信息可以表示一个整数数值。本申请实施例中，编码表中的索引信息仅包括符号，且映射的对象仅包括第一信息和第二信息，降低了编码表中内存占用。
应理解，还可以针对于不同的概率分布配置不同的映射关系(包括第一映射关系)。
在一种可能的实现中，所述目标符号为对图像的像素数据进行变换得到，所述对图像的像素数据进行变换得到的数据满足预设分布，所述变换还用于得到所述像素数据的分布特征，所述分布特征包括均值或方差，可以根据所述分布特征，从多个映射关系中确定与所述分布特征对应的所述第一映射关系。也就是说，可以将分布特征作为索引，从多个映射关系中确定与所述分布特征对应的所述第一映射关系。
参照图8，图8为一种编码过程的示意。
模型可以包括两个部分，一是图像数据处理模块，模型对图像数据进行变换，变换数据的分布更为简单，有利于熵编码过程。模型可以为神经网络，对图像数据处理成变换数据，并得到每个维度变换数据的分布索引。模型也可以为图像色彩变换的预处理及量化过程，如对RGB图像进行YUV，离散傅里叶变换等，得到变换数据，并针对这些变换数据建立特定的分布索引。
二是预先定义若干概率分布(如不同方差的高斯分布、逻辑斯谛分布等)，并建立对应的分布索引和编码表，其中编码表根据计算的离散PMF、CDF进行建立。
在编码过程中，对于每个维度的变换数据，可以找到对应的分布索引，由此找到对应的编码表格，使用熵编码，形成编码后的码字并存储。码字还可以存储基本的头文件，如图像的长、宽，一些必要的参数等。
在一种可能的实现中，为了进一步降低内存的占用，可以将第一信息和第二信息合并后存储，编码器可以在获取到合并的数据后，基于一定的运算规则还原得到第一信息和第二信息。
在一种可能的实现中，可以通过第一映射关系，得到所述目标符号对应的一个整数数值；基于第三运算，将所述整数数值还原为所述第一信息和所述第二信息，所述第一信息和所述第二信息分别为一个整数数值。通过上述方式，可减小内存消耗；减小内存读取时间，在部分硬件设备(如服务器)上可进一步提升吞吐率。
示例性的，可以将多整数参数(其中至多一个为有符号整数)合并成单个参数。方法为：将有符号整数放在最左边，之后通过移位、及比特或操作，按各自参数的比特数依次按比特存储；读取符号时，再通过移位、比特与操作，还原出各自参数。
参照表7，表7为进行信息合并前的编码表的一个示意，表8为进行信息合并后的编码表的一个示意，表9为编码表格参数长度汇总。
表7
表8
表9
603、根据所述第一信息以及所述编码器的状态信息，通过第一运算，得到第一编码数据。
604、根据所述第二信息，通过第二运算，更新所述状态信息，得到第二编码数据；其中，所述第一编码数据和所述第二编码数据用于得到所述目标符号的编码结果，且所述第一运算和所述第二运算不包括除法运算。
其中，第一编码数据可以为存储比特，第二编码数据可以为状态s。
在一种可能的实现中，所述第一运算和第二运算中的至少一个可以不包括除法运算，从而降低了计 算时延。
在一种可能的实现中，所述第一运算和第二运算中的至少一个可以不包括判断运算，从而降低了计算时延。
在一种可能的实现中，所述第一运算和第二运算中的至少一个可以不包括二分查找运算，从而降低了计算时延。
在一种可能的实现中，所述第一运算包括：对所述第一信息与所述状态信息进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；从所述状态信息中选择部分比特作为第一编码数据，所述部分比特在所述状态信息中的位置为根据所述比特移位操作的移位结果确定。
在一种可能的实现中，所述第二运算包括：对所述状态信息与数值M进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；其中，所述概率信息包括量化概率，所述M为所述量化概率的分母；对所述比特移位操作的移位结果与所述第二信息进行的加和操作。
示例性的，在编码期间，0≤s＜M。s初始化为0。
对于编码符号x来说：由x查表得到“比特加数”和“状态加数”；计算写入存储中的比特数b：当前状态s与“比特加数”的和，右移m位；将当前状态s最低的b位写入存储；将状态s更新为：当前状态s加上M，再右移b位后，与“状态加数”的和。
可以将s用m比特无符号整数的二进制表示，与存储的比特合并在一起，得到编码结果，也就是码字。
参照表5，表5为利用上述方式将AAABA编码为00101110(其中，前三位001表示状态为1，01110为存储比特)。
表5
参照图7，图7为通过上述方式1进行编码表构建以及通过上述介绍的第一运算和第二运算进行的编码过程的流程示意。
在一种可能的实现中，在通过上述方式2进行编码表构建时，所述第二运算可以包括：在所述状态信息初始化为所述M的情况下，对所述状态信息进行的比特移位操作；对所述比特移位操作的移位结果与所述第二信息进行的加和操作；对所述加和操作的加和结果与所述M进行减法运算。
示例性的，在整个编码期间，M≤s＜M×2；编码时，s初始化为M；
可以将“当前状态s加上M，再右移b位后，与状态加数的和”变为“当前状态s右移b位后，与状态加数的和”；将s-M用m比特无符号整数的二进制表示，与存储的比特合并在一起。
参照表6，表6为利用上述方式将AAABA编码为00101110(其中，前三位001表示状态为1，01110为存储比特)。
表6

本申请实施例提供了一种数据编码方法，应用于基于非对称数字系统ANS的编码器，所述方法包括：获取目标符号；通过第一映射关系，得到所述目标符号对应的第一信息和第二信息；所述第一信息和所述第二信息为根据所述目标符号对应的概率信息得到；根据所述第一信息以及所述编码器的状态信息，通过第一运算，得到第一编码数据；根据所述第二信息，通过第二运算，更新所述状态信息，得到第二编码数据；其中，所述第一编码数据和所述第二编码数据用于得到所述目标符号的编码结果，且所述第一运算和所述第二运算不包括除法运算。本申请中，编码表中的索引信息仅包括符号，且映射的对象仅包括第一信息和第二信息，相当于降低了编码表中内存占用，且避免了消耗较大的操作，实现内存与时延的平衡。
在一种可能的实现中，所述第二信息包括第一子信息(也可以称之为状态加数1)、第二子信息(也可以称之为状态阈值)和第三子信息(也可以称之为状态加数2)；
所述第一映射关系中的所述第一子信息为通过如下方式构建的：将所述目标符号的第三数值和所述目标符号的PMF的数值进行减法运算，得到所述第一子信息；
所述第一映射关系中的所述第二子信息为通过如下方式构建的：将所述目标符号的第三数值和所述目标符号的第一数值进行加法运算，将所述加法运算的操作结果与1进行减法操作，得到所述第二子信息；
所述第一映射关系中的所述第三子信息为通过如下方式构建的：将所述目标符号的第四数值和所述目标符号的第三数值进行减法运算，将所述减法运算的操作结果与所述目标符号的第一数值进行减法操作，得到所述第三子信息。
在一种可能的实现中，所述第二运算包括：
对所述状态信息与数值M进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；其中，所述概率信息包括量化概率，所述M为所述量化概率的分母；对所述比特移位操作的移位结果与所述第一子信息进行的加和操作；
在所述加和操作的操作结果大于所述第二子信息时，将所述加和操作的操作结果与所述第三子信息的加和结果作为所述第二编码数据；
在所述加和操作的操作结果小于所述第二子信息时，将所述加和操作的操作结果作为所述第二编码数据。
上述方式可以但不限于适用于单峰对称分布(如高斯分布，逻辑斯谛分布，拉普拉斯分布等)，用于减小编码长度，但编码计算量会提升。
1.将每个符号的PMF值分成两部分P(x)＝P1(x)+P2(x)
2.计算C1(x)为小于x的符号的P1(x)的加和；C2(x)为小于x的符号的P2(x)的加和，加上所有P1(x)的值。
如下表格示出了一个具体的示意：
在构建编码表时，对于每个符号x，构建方法的一个示意如下：
1)计算出每次编码x，写入存储中的基础比特数b(x)＝clz(P(x))+m-31。其中clz函数计算一个32位整数的最高位的连续为0的比特的数量。
2)计算比特加数的结果：(b(x)＜＜m)-(P(x)＜＜b(x))+M，范围[2,m×M]，用 比特的无符号整数表示；z
3)计算状态加数1的结果：C1(x)-P(x)
4)计算状态阀值的结果：C1(x)+P1(x)-1
5)计算状态加数2的结果：C2(x)-C1(x)-P1(x)
如下表格示出了一个编码表格的示意：
在编码时，码字可以由状态s及存储memory组成。
示例性的，在整个编码期间，0≤s＜M。s初始化为0。
编码符号x：
1)由x查表得到“比特加数”，“状态加数1”，“状态阀值”和“状态加数2”；
2)计算写入存储中的比特数b：当前状态s与“比特加数”的和，右移m位；
3)将当前状态s最低的b位写入存储；
4)将状态s更新为：当前状态s加上M，再右移b位后，与“状态加数1”的和；
5)若状态s大于“状态阀值”，则将s更新为s与“状态加数2”的和。
码字：将s用m比特无符号整数的二进制表示，与存储的比特合并在一起。
在一种可能的实现中，在所述数值M为256时，所述第一信息通过10比特存储，所述第一子信息通过8比特存储，所述第二子信息通过7比特存储，所述第三子信息通过7比特存储，多个符号的第一数值的加和为128，所述第三子信息小于128。
当M＝256(m＝8)时，满足如下条件：
每个符号的“比特加数”，“状态加数1”，“状态阀值”，“状态加数2”分别需要10比特，8比特，7比特，7比特，共32比特。所有P1(x)的和恰为128，“状态加数2”的值恒小于128。
当M＝256(m＝8)时，“比特加数”，“状态加数1”，“状态阀值”，“状态加数2”分别需要12比特，8比特，8比特，8比特，8比特。共36比特，无法用4字节表示。用如下方法可将4部分用共32比特表示：
1.比特加数B原为[2,2048]间的偶数，需12比特，可用10比特表示B/2-1；
2.调整P1(x)与P2(x)的值，使得所有P1(x)的和恰为128，且“状态加数2”的值恒小于128。则“状态阀值”、“状态加数2”的范围均为[0,127]，可用7比特表示；
应用此方案，每个符号的“比特加数”，“状态加数1”，“状态阀值”，“状态加数2”分别需要10比特，8比特，7比特，7比特，共32比特。
本申请还提供了一种数据编码方法，应用于基于非对称数字系统ANS的编码器，所述方法包括：获取第一符号，所述第一符号对应的量化概率和第二符号对应的量化概率的和为1，且所述第一符号对应的量化概率和1的差异小于阈值，所述第二符号对应的量化概率和0的差异小于阈值；根据所述编码器的状态信息和数值M之间的数值大小关系满足第一条件，将所述状态信息和所述数值M之间进行第一运算，得到第一编码数据，并将所述状态信息更新为0；根据所述编码器的状态信息和数值M之间的数值大小关系不满足所述第一条件，将所述状态信息加1。
在一种可能的实现中，所述方法还包括：获取所述第二符号；将所述编码器的状态信息作为第一编码数据，并将所述状态信息更新为所述数值M与1的差值。
上述实施例可以针对于共两种符号，且单一符号概率接近1时的编、解码方案。此实施例无需构建编码、解码表，因此无需额外内存存储表格。假设共两种符号a和b，且符号a的概率接近1，则编码算法如下：
压缩符号a：若状态s≥M-2，则将s-M+2(0或1)写入1比特到存储，然后将s更新为0；否则将s更新为s+1；
压缩符号b：将s的全部m位写入存储，并更新s为M-1。
参照图9，图9为本申请实施例提供的一种数据解码方法的实施例示意，如图9示出的那样，本申请实施例提供的一种数据解码方法，包括：
901、获取所述解码器的状态信息以及存储比特，所述状态信息与第一比特相对应，所述第一比特为当前待解码的比特；
示例性的，参照图10A，图10A为本申请实施例提供的一种数据解码方法的具体示意。
其中，状态信息(解码状态)可以为从编码侧获取到的，也可以是解码过程中对于状态信息进行更新得到的一个状态信息。其中，存储比特可以为从编码侧获取到的，也可以是解码过程中对于存储比特进行更新得到的一个存储比特。
902、根据第一映射关系，确定所述状态信息对应的第一信息、第二信息以及第三信息；所述第一信息为所述第一比特对应的目标符号，所述目标符号为所述第一比特的解码结果，所述第二信息表示从所述存储比特中选择的比特位数，所述第三信息用于和根据所述第三信息从所述存储比特中选择的比特进行加和运算，所述加和运算结果用于更新所述状态信息，更新后的状态信息与第二比特相对应，所述第二比特为所述第一比特之后的待解码比特。
应理解，图6中描述的第一映射关系和图9描述的第一映射关系为不同的映射关系。图9中描述的第一映射关系为解码表。
其中，第一信息可以称之为解码符号、第二信息可以称之为读取比特数、第三信息可以称之为状态基数。
在一种可能的实现中，所述第一信息、所述第二信息或所述第三信息为根据概率信息得到；所述概率信息包括概率质量函数PMF的数值；所述PMF的数值为通过如下方式构建的：依次确定多个符号中每个符号的PMF的数值，所述多个符号包括所述目标符号；其中，在确定所述目标符号的PMF的数值时，将除去已确定的符号的PMF之外的剩余PMF的总数值与所述目标符号的概率进行乘积，并计算所述乘积的乘积结果与除去已确定的符号的剩余概率之间的比值，根据所述比值与预设数值之间的关系，确定所述目标符号的PMF。
在一种可能的实现中，所述第一信息、所述第二信息或所述第三信息为根据概率信息得到；所述概率信息包括累积分布函数CDF的数值；所述CDF的数值为通过如下方式构建的：基于预设顺序，依次确定每个符号的CDF的数值，其中所述预设顺序为根据多个符号对应的PMF的数值之间的关系确定，所述多个符号包括所述目标符号；其中，在所述目标符号的概率信息对应的概率分布为对称分布时，所述预设顺序为沿着所述对称分布中峰值点的两侧相交错的顺序；或者，在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从大到小的顺序；或者，在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从小到大的顺序。
在一种可能的实现中，所述第一映射关系中的所述第一信息为通过如下方式构建的：将满足 C(x)≤s＜(C(x)+P(x))的x作为所述第一信息；其中，所述C表示CDF的数值，所述P表示PMF的数值，所述s表示所述状态信息。
在一种可能的实现中，所述第一映射关系中的所述第二信息为通过如下方式构建的：将clz(s-C(x)+P(x))+X的数值作为所述第二信息；其中，所述clz表示取数值中最高位连续为0的比特数量，所述X为预设的第五数值。
在一种可能的实现中，所述第一映射关系中的所述第三信息为通过如下方式构建的：将s-C(x)+P(x)的数值进行比特移位操作，得到所述第三信息，所述比特移位操作的移位数量为根据所述第二信息得到；或者，将s-C(x)+P(x)的数值进行比特移位操作，并将所述比特移位操作的操作结果减去数值M，得到所述第三信息，所述M为所述量化概率的分母，所述比特移位操作的移位数量为根据所述第二信息得到。
示例性的，在构建解码表时，对于每一种状态s，构建方法如下：
“解码符号”为满足C(x)≤s＜C(x)+P(x)的x值；“读取比特数”的值为clz(s-C(x)+P(x))+m-31；“状态基数”的值为s-C(x)+P(x)左移“读取比特数”位数的结果，与M的差。
参照表10，表10为利用上述方式得到的一个解码表的示意：
表10
在一种可能的实现中，所述第一信息、所述第二信息或所述第三信息表示一个整数数值，也就是单一的一个整数，例如，所述第一信息可以表示一个整数数值，第二信息可以表示一个整数数值，第三信息可以表示一个整数数值。本申请实施例中，解码表中的索引信息仅包括符号，且映射的对象仅包括第一信息、第二信息和第三信息，降低了编码表中内存占用。
应理解，还可以针对于不同的概率分布配置不同的映射关系(包括第一映射关系)。
在一种可能的实现中，可以获取编码结果；所述编码结果为对图像的像素数据进行编码得到的，所述状态信息以及所述存储比特为根据所述编码结果得到；对所述编码结果进行处理，所述像素数据的分布特征，所述分布特征包括均值或方差；根据所述分布特征，从多个映射关系中确定与所述分布特征对应的所述第一映射关系。
参照图10B，图10B为一种解码过程的示意。
其中，模型包括三个部分。
一是对码字中的头文件进行解码，如图像的长、宽，一些必要的参数等。这些参数可以对码字内的信息，建立解码数据(变换数据)对应的分布索引。
二是预先定义若干概率分布(如不同方差的高斯分布、逻辑斯谛分布等)，并建立对应的分布索引和解码表，其中编码表根据计算的离散PMF、CDF进行建立。
三是图像解码器，对变换数据进行解码，恢复图像。其中，解码器可以为神经网络，也可以为图像色彩变换的后处理过程，如反傅里叶变换，YUV转RGB等。
在解码过程中，对于待解码的码字，首先用模型读取头文件中基本配置，并根据码字建立必要的解码数据的分布索引。对每个维度的解码数据(变换数据)，通过分布索引找到对应解码表，利用熵解码得到解码后的变换数据。最后使用模型，将变换数据恢复成原始图像。
在一种可能的实现中，可以通过第一映射关系，得到所述状态信息对应的一个整数数值；将所述整数数值还原为所述第一信息、所述第二信息和所述第三信息，所述第一信息、所述第二信息和所述第三信息分别为一个整数数值。
示例性的，可以将“解码符号”、“读取比特数”、“状态基数”按上述规则合并。单个参数的长度和由状态数M＝2m决定，为方便计算机读取，一般设为24bits或32bits。
参照表11，表11为码表格参数长度汇总的示意：
表11
在一种可能的实现中，所述第一信息为所述第一比特对应的目标符号，所述目标符号为所述第一比特的解码结果，所述第二信息表示从所述存储比特中选择的比特位数，所述第三信息用于和根据所述第三信息从所述存储比特中选择的比特进行加和运算，所述加和运算结果用于更新所述状态信息，更新后的状态信息与第二比特相对应，所述第二比特为所述第一比特之后的待解码比特。此外，还可以从所述存储比特中剔除根据所述选择的比特，得到更新后的存储比特。
示例性的，可以根据当前状态值，查表得到“解码符号”、“读取比特数”、“状态基数”；将s更新为：从存储中读取“读取比特数”比特得到的数字，与“状态基数”的和。
参照表12，表12为一个解码示意：解码00101110(状态001表示1，01110为存储比特)，解码结果为AAABA。
表12
应理解，图6对应的实施例和图9实施例中的技术方案之间可以相互组合。示例性的，可以构建三个子表：
子表1：对于每个状态s，求出“解码符号”，方法、结果与上述解码过程相同；
子表2：对于每个符号x，求出“状态加数”，方法、结果与上述编码过程中描述的方式1的“状态加数”相同；
子表3(所有分布共用一张表)：对于每个整数i∈[1,M×2-1]，求出“状态比特数”为clz(i)+m-31。
解码单个符号过程：
将当前状态s代入子表1，得到解码出的x“解码符号”；
将解码出的x代入子表2，得到“状态加数”；
计算需从存储读取的比特数：将s减“状态加数”的值代入子表3，得到“状态比特数”；
更新状态s为：当前s的值减去“状态加数”后，左移“状态比特数”的位数，加上存储是读取“状态比特数”位数的值，对M取模。
用上述方法，每步解码的中间结果均与图9介绍的解码过程相同。
参照表13，表13为利用上述方式得到的一个解码表的示意：
表13
本申请实施例能够取得更短的压缩时间。相对于rANS，编解码时间较rANS提升3-4倍。
参照表14，表14为一个有益效果的示意：
表14
本申请实施例的表格内存更小，对于总符号数X，状态数M，如果表格每个元素用32bits存储，则编码表格大小4X，解码表格大小3M；如果压缩至24bits存储，则编码表格大小3X，解码表格大小3M。
对于特定分布构建表格，表格内存占用小于100KB(MASS＝8,M＝256)。对应tANS的10MB～20MB的表格大小，表格内存占用大大缩减。
参照表15，表15为一个有益效果的示意：
表15
在一种可能的实现中，所述第一映射关系中的所述第一信息为通过如下方式构建的：
将满足C1(x)≤s＜C1(x)+P1(x)或C2(x)≤s＜C2(x)+P2(x)的x作为所述第一信息；其中，所述C1表示CDF对应的第三数值，所述P1表示PMF对应的第一数值，所述C2表示CDF对应的第四数值，所述P2表示PMF对应的第二数值，所述s表示所述状态信息；所述第一数值和所述第二数值的加和为所述PMF的数值。
在一种可能的实现中，所述第一映射关系中的所述第二信息为通过如下方式构建的：
将clz(s′-C(x)+P(x))+X的数值作为所述第二信息；其中，所述clz表示取数值中最高位连续为0的比特数量，所述X为预设的第五数值，所述s′为通过如下得到：
若C2(x)≤s，则s’＝P1(x)+s-C2(x)+P(x)，否则s’＝s-C1(x)+P(x)。
在一种可能的实现中，所述第一映射关系中的所述第三信息为通过如下方式构建的：将s′-C(x)+P(x)的数值进行比特移位操作，得到所述第三信息，所述比特移位操作的移位数量为根据所述第二信息得到。
对于每一种状态s，构建方法如下：
1.“解码符号”为满足C1(x)≤s＜C1(x)+P1(x)或C2(x)≤s＜C2(x)+P2(x)的x值；
2.求出s对应的s’:
a)若C2(x)≤s，则s’＝P1(x)+s-C2(x)+P(x)；
b)否则s’＝s-C1(x)+P(x)
3.利用s’，用与实施例二相同的方法构建解码表；
1)“读取比特数”的值为clz(s′-C(x)+P(x))+m-31；
2)“状态基数”的值为s′-C(x)+P(x)左移“读取比特数”位数的结果，与M的差。
此外，每个解码符号可以对应1～2段连续的状态s。如以上表格中，A对应的是0～2，以及4～5。
解码单个符号时，可以根据当前状态值s，查表得到“解码符号”、“读取比特数”、“状态基数”；将s更新为：从存储中读取“读取比特数”比特得到的数字，与“状态基数”的和；
本申请还提供了一种数据解码方法，应用于基于非对称数字系统ANS的解码器，所述方法包括：
获取所述解码器的状态信息，所述状态信息与第一比特相对应，所述第一比特为当前待解码的比特；
若所述状态信息为数值M与1的差值，则确定所述第一比特的解码结果为第二符号，并将所述状态信息更新为从存储中读取所述数值M位的结果；
若所述状态信息不为数值M与1的差值，则确定所述第一比特的解码结果为第一符号，若所述状态信息为0，则将所述状态信息更新为所述数值M与2的差值与从存储中读出1个比特的值的加和结果；若所述状态信息不为0，则将所述状态信息更新为所述状态信息与1的差值；更新后的状态信息与第二比特相对应，所述第二比特为所述第一比特之后的待解码比特。
上述实施例为针对于共两种符号，且单一符号概率接近1时的编、解码方案。
两种符号a,b，此实施例无需构建编码、解码表，因此无需额外内存存储表格。假设共两种符号a和b，且符号a的概率接近1，则编码算法如下：
压缩符号a：若状态s≥M-2，则将s-M+2(0或1)写入1比特到存储，然后将s更新为0；否则将s更新为s+1；
压缩符号b：将s的全部m位写入存储，并更新s为M-1。
解码算法为：若当前状态s为M-1，则解码出符号b，并将s更新为从存储中读取m位的结果；否 则则解码出a，然后更新s：1)若s＝0，则将s更新为M-2与从存储中读出一比特的值和；2)否则，将s更新为s-1。
接下来从装置的角度介绍本申请实施例提供的一种数据编码装置，参照图11，图11为本申请实施例提供的一种数据编码装置的结构示意，如图11所示，本申请实施例提供的一种数据编码装置1100包括：
获取模块1101，用于获取目标符号；
关于获取模块1101的具体描述可以参照上述实施例中步骤601的描述，这里不再赘述。
编码模块1102，用于通过第一映射关系，得到所述目标符号对应的第一信息和第二信息；所述第一信息和所述第二信息为根据所述目标符号对应的概率信息得到；
根据所述第一信息以及所述编码器的状态信息，通过第一运算，得到第一编码数据；
根据所述第二信息，通过第二运算，更新所述状态信息，得到第二编码数据；其中，
所述第一编码数据和所述第二编码数据用于得到所述目标符号的编码结果，且所述第一运算和所述第二运算不包括除法运算。
关于编码模块1102的具体描述可以参照上述实施例中步骤602的描述，这里不再赘述。
在一种可能的实现中，所述第一信息或所述第二信息表示一个整数数值。
在一种可能的实现中，所述第一运算和所述第二运算不包括判断运算。
在一种可能的实现中，所述第一运算包括：
对所述第一信息与所述状态信息进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；
从所述状态信息中选择部分比特作为第一编码数据，所述部分比特在所述状态信息中的位置为根据所述比特移位操作的移位结果确定。
在一种可能的实现中，所述第二运算包括：
对所述状态信息与数值M进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；其中，所述概率信息包括量化概率，所述M为所述量化概率的分母；
对所述比特移位操作的移位结果与所述第二信息进行的加和操作。
在一种可能的实现中，所述概率信息包括概率质量函数PMF的数值；所述PMF的数值为通过如下方式构建的：
依次确定多个符号中每个符号的PMF的数值，所述多个符号包括所述目标符号；其中，
在确定所述目标符号的PMF的数值时，将除去已确定的符号的PMF之外的剩余PMF的总数值与所述目标符号的概率进行乘积，并计算所述乘积的乘积结果与除去已确定的符号的剩余概率之间的比值，根据所述比值与预设的第五数值之间的关系，确定所述目标符号的PMF。
在一种可能的实现中，所述第五数值为1，所述关系为取较大值。
在一种可能的实现中，所述概率信息包括累积分布函数CDF的数值；所述CDF的数值为通过如下方式构建的：
基于预设顺序，依次确定每个符号的CDF的数值，其中所述预设顺序为根据多个符号对应的PMF的数值之间的关系确定，所述多个符号包括所述目标符号；其中，
在所述目标符号的概率信息对应的概率分布为对称分布时，所述预设顺序为沿着所述对称分布中峰值点的两侧相交错的顺序；或者，
在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从大到小的顺序；或者，
在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从小到大的顺序。
在一种可能的实现中，所述目标符号为对图像的像素数据进行变换得到，所述对图像的像素数据进行变换得到的数据满足预设分布，所述变换还用于得到所述像素数据的分布特征，所述分布特征包括均值或方差，所述获取模块，还用于：
根据所述分布特征，从多个映射关系中确定与所述分布特征对应的所述第一映射关系。
在一种可能的实现中，所述多个分布特征包括第一分布特征和第二分布特征，所述第一分布特征的熵大于所述第二分布特征的熵；
所述第二分布特征对应的映射关系中的量化概率的分母的数值大于所述第一分布特征对应的映射关系中的量化概率的分母。
在一种可能的实现中，所述第一映射关系中的所述第一信息为通过如下方式构建的：
将所述目标符号的PMF的数值中最高位连续为0的比特数量与预设的第六数值的加和运算；
将所述加和运算的加和结果进行比特移位操作，并将所述比特移位操作的移位结果与对所述目标符号的PMF的数值进行比特移位操作的移位结果进行减法操作，得到所述第一信息；或者，
将所述加和运算的加和结果进行比特移位操作，并将所述比特移位操作的移位结果与对所述目标符号的PMF的数值进行比特移位操作的移位结果进行减法操作，将所述减法操作的操作结果与数值M进行加和操作，得到所述第一信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
在一种可能的实现中，所述第一映射关系中的所述第二信息为通过如下方式构建的：
将所述目标符号的CDF的数值和所述目标符号的PMF的数值进行减法运算，得到所述第二信息；或者，
将所述目标符号的CDF的数值和所述目标符号的PMF的数值进行减法运算，将所述减法操作的操作结果与数值M进行加和操作，得到所述第二信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
在一种可能的实现中，所述第一映射关系中的所述第二信息为通过如下方式构建的：
在所述目标符号的CDF的数值和所述目标符号的PMF的数值的减法运算的结果大于或等于0时，将所述减法运算的结果作为所述第二信息；或者，
在所述目标符号的CDF的数值和所述目标符号的PMF的数值的减法运算的结果小于0时，将所述减法操作的操作结果与数值M进行加和操作，得到所述第二信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
在一种可能的实现中，所述编码模块，具体用于：
通过第一映射关系，得到所述目标符号对应的一个整数数值；
基于第三运算，将所述整数数值还原为所述第一信息和所述第二信息，所述第一信息和所述第二信息分别为一个整数数值。
在一种可能的实现中，所述概率信息包括每个符号对应的PMF信息，所述PMF信息包括第一数值和第二数值；所述第一数值和所述第二数值的加和为所述PMF的数值；所述概率信息还包括每个符号对应的CDF信息，所述CDF信息包括第三数值和第四数值；所述第三数值和第四数值为通过如下方式构建的：
基于预设顺序，根据多个符号的第一数值，通过累加依次确定每个符号的对应的第三数值；
基于所述预设顺序，根据多个符号的第二数值和第三数值，通过累加依次确定每个符号对应的第四数值。
在一种可能的实现中，所述第二信息包括第一子信息、第二子信息和第三子信息；
所述第一映射关系中的所述第一子信息为通过如下方式构建的：将所述目标符号的第三数值和所述目标符号的PMF的数值进行减法运算，得到所述第一子信息；
所述第一映射关系中的所述第二子信息为通过如下方式构建的：将所述目标符号的第三数值和所述目标符号的第一数值进行加法运算，将所述加法运算的操作结果与1进行减法操作，得到所述第二子信息；
所述第一映射关系中的所述第三子信息为通过如下方式构建的：将所述目标符号的第四数值和所述目标符号的第三数值进行减法运算，将所述减法运算的操作结果与所述目标符号的第一数值进行减法操作，得到所述第三子信息。
在一种可能的实现中，所述第二运算包括：
对所述状态信息与数值M进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；其中，所述概率信息包括量化概率，所述M为所述量化概率的分母；对所述比特移位操作的移位结果与 所述第一子信息进行的加和操作；
在所述加和操作的操作结果大于所述第二子信息时，将所述加和操作的操作结果与所述第三子信息的加和结果作为所述第二编码数据；
在所述加和操作的操作结果小于所述第二子信息时，将所述加和操作的操作结果作为所述第二编码数据。
在一种可能的实现中，在所述数值M为256时，所述第一信息通过10比特存储，所述第一子信息通过8比特存储，所述第二子信息通过7比特存储，所述第三子信息通过7比特存储，多个符号的第一数值的加和为128，所述第三子信息小于128。
本申请还提供了一种数据编码装置，应用于基于非对称数字系统ANS的编码器，所述装置包括：
获取模块，用于获取第一符号，所述第一符号对应的量化概率和第二符号对应的量化概率的和为1，且所述第一符号对应的量化概率和1的差异小于阈值，所述第二符号对应的量化概率和0的差异小于阈值；
编码模块，用于根据所述编码器的状态信息和数值M之间的数值大小关系满足第一条件，将所述状态信息和所述数值M之间进行第一运算，得到第一编码数据，并将所述状态信息更新为0；
根据所述编码器的状态信息和数值M之间的数值大小关系不满足所述第一条件，将所述状态信息加1；
在一种可能的实现中，所述获取模块，还用于：
获取所述第二符号；
所述编码模块，还用于将所述编码器的状态信息作为第一编码数据，并将所述状态信息更新为所述数值M与1的差值。
接下来从装置的角度介绍本申请实施例提供的一种数据解码装置，参照图12，图12为本申请实施例提供的一种数据解码装置的结构示意，如图12所示，本申请实施例提供的一种数据解码装置1200包括：
获取模块1201，用于获取所述解码器的状态信息以及存储比特，所述状态信息与第一比特相对应，所述第一比特为当前待解码的比特；
关于获取模块1201的具体描述可以参照上述实施例中步骤901的描述，这里不再赘述。
解码模块1202，用于根据第一映射关系，确定所述状态信息对应的第一信息、第二信息以及第三信息；所述第一信息为所述第一比特对应的目标符号，所述目标符号为所述第一比特的解码结果，所述第二信息表示从所述存储比特中选择的比特位数，所述第三信息用于和根据所述第三信息从所述存储比特中选择的比特进行加和运算，所述加和运算结果用于更新所述状态信息，更新后的状态信息与第二比特相对应，所述第二比特为所述第一比特之后的待解码比特。
关于解码模块1202的具体描述可以参照上述实施例中步骤902的描述，这里不再赘述。
在一种可能的实现中，所述解码模块，还用于：
从所述存储比特中剔除根据所述选择的比特，得到更新后的存储比特。
在一种可能的实现中，所述第一信息、所述第二信息或所述第三信息表示一个整数数值。
在一种可能的实现中，所述第一映射关系中的所述第一信息为通过如下方式构建的：
将满足C(x)≤s＜(C(x)+P(x))的x作为所述第一信息；其中，所述C表示CDF的数值，所述P表示PMF的数值，所述s表示所述状态信息；或者，
将满足C1(x)≤s＜C1(x)+P1(x)或C2(x)≤s＜C2(x)+P2(x)的x作为所述第一信息；其中，所述C1表示CDF对应的第三数值，所述P1表示PMF对应的第一数值，所述C2表示CDF对应的第四数值，所述P2表示PMF对应的第二数值，所述s表示所述状态信息；所述第一数值和所述第二数值的加和为所述PMF的数值。
在一种可能的实现中，所述第一映射关系中的所述第二信息为通过如下方式构建的：
将clz(s-C(x)+P(x))+X的数值作为所述第二信息；其中，所述clz表示取数值中最高位连续为0的比特数量，所述X为预设的第五数值；或者，
将s-C(x)+P(x)的数值进行比特移位操作，得到所述第三信息，所述比特移位操作的移位数量为根据所述第二信息得到；或者，
将s-C(x)+P(x)的数值进行比特移位操作，并将所述比特移位操作的操作结果减去数值M，得到所述第三信息，所述M为所述量化概率的分母，所述比特移位操作的移位数量为根据所述第二信息得到；或者，
将clz(s′-C(x)+P(x))+X的数值作为所述第二信息；其中，所述clz表示取数值中最高位连续为0的比特数量，所述X为预设的第五数值，所述s′为通过如下得到：
若C2(x)≤s，则s’＝P1(x)+s-C2(x)+P(x)，否则s’＝s-C1(x)+P(x)。
在一种可能的实现中，所述第一映射关系中的所述第三信息为通过如下方式构建的：
将s-C(x)+P(x)的数值进行比特移位操作，得到所述第三信息，所述比特移位操作的移位数量为根据所述第二信息得到；或者，
将s-C(x)+P(x)的数值进行比特移位操作，并将所述比特移位操作的操作结果减去数值M，得到所述第三信息，所述M为所述量化概率的分母，所述比特移位操作的移位数量为根据所述第二信息得到；或者，
将s′-C(x)+P(x)的数值进行比特移位操作，得到所述第三信息，所述比特移位操作的移位数量为根据所述第二信息得到。
在一种可能的实现中，所述第一信息、所述第二信息或所述第三信息为根据概率信息得到；所述概率信息包括概率质量函数PMF的数值；所述PMF的数值为通过如下方式构建的：
依次确定多个符号中每个符号的PMF的数值，所述多个符号包括所述目标符号；其中，
在确定所述目标符号的PMF的数值时，将除去已确定的符号的PMF之外的剩余PMF的总数值与所述目标符号的概率进行乘积，并计算所述乘积的乘积结果与除去已确定的符号的剩余概率之间的比值，根据所述比值与预设数值之间的关系，确定所述目标符号的PMF。
在一种可能的实现中，所述预设数值为1，所述关系为取较大值。
在一种可能的实现中，所述第一信息、所述第二信息或所述第三信息为根据概率信息得到；所述概率信息包括累积分布函数CDF的数值；所述CDF的数值为通过如下方式构建的：
基于预设顺序，依次确定每个符号的CDF的数值，其中所述预设顺序为根据多个符号对应的PMF的数值之间的关系确定，所述多个符号包括所述目标符号；其中，
在所述目标符号的概率信息对应的概率分布为对称分布时，所述预设顺序为沿着所述对称分布中峰值点的两侧相交错的顺序；或者，
在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从大到小的顺序；或者，
在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从小到大的顺序。
在一种可能的实现中，所述获取模块，还用于：
获取编码结果；所述编码结果为对图像的像素数据进行编码得到的，所述状态信息以及所述存储比特为根据所述编码结果得到；
对所述编码结果进行处理，所述像素数据的分布特征，所述分布特征包括均值或方差；
根据所述分布特征，从多个映射关系中确定与所述分布特征对应的所述第一映射关系。
本申请还提供了一种数据解码装置，应用于基于非对称数字系统ANS的解码器，所述装置包括：
获取模块，用于获取所述解码器的状态信息，所述状态信息与第一比特相对应，所述第一比特为当前待解码的比特；
解码模块，用于若所述状态信息为数值M与1的差值，则确定所述第一比特的解码结果为第二符号，并将所述状态信息更新为从存储中读取所述数值M位的结果；
若所述状态信息不为数值M与1的差值，则确定所述第一比特的解码结果为第一符号，若所述状态信息为0，则将所述状态信息更新为所述数值M与2的差值与从存储中读出1个比特的值的加和结果；若所述状态信息不为0，则将所述状态信息更新为所述状态信息与1的差值；更新后的状态信息与第二比特相对应，所述第二比特为所述第一比特之后的待解码比特。
接下来介绍本申请实施例提供的一种执行设备，请参阅图13，图13为本申请实施例提供的执行设备的一种结构示意图，执行设备1300具体可以表现为手机、平板、笔记本电脑、智能穿戴设备、服务器等，此处不做限定。其中，执行设备1300实现图6以及图9对应实施例中数据编解码方法的功能。具体的，执行设备1300包括：接收器1301、发射器1302、处理器1303和存储器1304(其中执行设备1300中的处理器1303的数量可以一个或多个)，其中，处理器1303可以包括应用处理器13031和通信处理器13032。在本申请的一些实施例中，接收器1301、发射器1302、处理器1303和存储器1304可通过总线或其它方式连接。
存储器1304可以包括只读存储器和随机存取存储器，并向处理器1303提供指令和数据。存储器1304的一部分还可以包括非易失性随机存取存储器(non-volatile random access memory，NVRAM)。存储器1304存储有处理器和操作指令、可执行模块或者数据结构，或者它们的子集，或者它们的扩展集，其中，操作指令可包括各种操作指令，用于实现各种操作。
处理器1303控制执行设备的操作。具体的应用中，执行设备的各个组件通过总线系统耦合在一起，其中总线系统除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都称为总线系统。
上述本申请实施例揭示的方法可以应用于处理器1303中，或者由处理器1303实现。处理器1303可以是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器1303中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器1303可以是通用处理器、数字信号处理器(digital signal processing，DSP)、微处理器或微控制器、以及视觉处理器(vision processing unit，VPU)、张量处理器(tensor processing unit，TPU)等适用于AI运算的处理器，还可进一步包括专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。该处理器1303可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器1304，处理器1303读取存储器1304中的信息，结合其硬件完成上述实施例中图6以及图9对应实施例中数据编解码方法。
接收器1301可用于接收输入的数字或字符信息，以及产生与执行设备的相关设置以及功能控制有关的信号输入。发射器1302可用于通过第一接口输出数字或字符信息；发射器1302还可用于通过第一接口向磁盘组发送指令，以修改磁盘组中的数据；发射器1302还可以包括显示屏等显示设备。
本申请实施例还提供了一种训练设备，请参阅图14，图14是本申请实施例提供的服务器一种结构示意图，具体的，服务器1400由一个或多个服务器实现，服务器1400可因配置或性能不同而产生比较大的差异，可以包括一个或一个以上中央处理器(central processing units，CPU)1414(例如，一个或一个以上处理器)和存储器1432，一个或一个以上存储应用程序1442或数据1444的存储介质1430(例如一个或一个以上海量存储设备)。其中，存储器1432和存储介质1430可以是短暂存储或持久存储。存储在存储介质1430的程序可以包括一个或一个以上模块(图示没标出)，每个模块可以包括对服务器中的一系列指令操作。更进一步地，中央处理器1414可以设置为与存储介质1430通信，在服务器1400上执行存储介质1430中的一系列指令操作。
服务器1400还可以包括一个或一个以上电源1426，一个或一个以上有线或无线网络接口1450，一个或一个以上输入输出接口1458；或，一个或一个以上操作系统1441，例如Windows ServerTM，Mac OS XTM，UnixTM,LinuxTM，FreeBSDTM等等。
具体的，服务器可以进行上述实施例中和模型训练相关的步骤。
本申请实施例中还提供一种包括计算机程序产品，当其在计算机上运行时，使得计算机执行图6以 及图9对应实施例中数据编解码方法。
本申请实施例中还提供一种计算机可读存储介质，该计算机可读存储介质中存储有用于进行信号处理的程序，当其在计算机上运行时，使得计算机执行图6以及图9对应实施例中数据编解码方法。
本申请实施例提供的执行设备、训练设备或终端设备具体可以为芯片，芯片包括：处理单元和通信单元，所述处理单元例如可以是处理器，所述通信单元例如可以是输入/输出接口、管脚或电路等。该处理单元可执行存储单元存储的计算机执行指令，以使执行设备内的芯片执行上述实施例描述的数据处理方法，或者，以使训练设备内的芯片执行上述实施例描述的数据处理方法。可选地，所述存储单元为所述芯片内的存储单元，如寄存器、缓存等，所述存储单元还可以是所述无线接入设备端内的位于所述芯片外部的存储单元，如只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)等。
具体的，请参阅图15，图15为本申请实施例提供的芯片的一种结构示意图，所述芯片可以表现为神经网络处理器NPU1500，NPU 1500作为协处理器挂载到主CPU(Host CPU)上，由Host CPU分配任务。NPU的核心部分为运算电路1503，通过控制器1504控制运算电路1503提取存储器中的矩阵数据并进行乘法运算。
NPU 1500可以通过内部的各个器件之间的相互配合，来实现图6以及图9对应实施例中数据编解码方法。
更具体的，在一些实现中，NPU 1500中的运算电路1503内部包括多个处理单元(Process Engine,PE)。在一些实现中，运算电路1503是二维脉动阵列。运算电路1503还可以是一维脉动阵列或者能够执行例如乘法和加法这样的数学运算的其它电子线路。在一些实现中，运算电路1503是通用的矩阵处理器。
举例来说，假设有输入矩阵A，权重矩阵B，输出矩阵C。运算电路从权重存储器1502中取矩阵B相应的数据，并缓存在运算电路中每一个PE上。运算电路从输入存储器1501中取矩阵A数据与矩阵B进行矩阵运算，得到的矩阵的部分结果或最终结果，保存在累加器(accumulator)1508中。
统一存储器1506用于存放输入数据以及输出数据。权重数据直接通过存储单元访问控制器(Direct Memory Access Controller，DMAC)1505，DMAC被搬运到权重存储器1502中。输入数据也通过DMAC被搬运到统一存储器1506中。
BIU为Bus Interface Unit即，总线接口单元1510，用于AXI总线与DMAC和取指存储器(Instruction Fetch Buffer，IFB)1509的交互。
总线接口单元1510(Bus Interface Unit，简称BIU)，用于取指存储器1509从外部存储器获取指令，还用于存储单元访问控制器1505从外部存储器获取输入矩阵A或者权重矩阵B的原数据。
DMAC主要用于将外部存储器DDR中的输入数据搬运到统一存储器1506或将权重数据搬运到权重存储器1502中或将输入数据数据搬运到输入存储器1501中。
向量计算单元1507包括多个运算处理单元，在需要的情况下，对运算电路1503的输出做进一步处理，如向量乘，向量加，指数运算，对数运算，大小比较等等。主要用于神经网络中非卷积/全连接层网络计算，如Batch Normalization(批归一化)，像素级求和，对特征平面进行上采样等。
在一些实现中，向量计算单元1507能将经处理的输出的向量存储到统一存储器1506。例如，向量计算单元1507可以将线性函数；或，非线性函数应用到运算电路1503的输出，例如对卷积层提取的特征平面进行线性插值，再例如累加值的向量，用以生成激活值。在一些实现中，向量计算单元1507生成归一化的值、像素级求和的值，或二者均有。在一些实现中，处理过的输出的向量能够用作到运算电路1503的激活输入，例如用于在神经网络中的后续层中的使用。
控制器1504连接的取指存储器(instruction fetch buffer)1509，用于存储控制器1504使用的指令；
统一存储器1506，输入存储器1501，权重存储器1502以及取指存储器1509均为On-Chip存储器。外部存储器私有于该NPU硬件架构。
其中，上述任一处提到的处理器，可以是一个通用中央处理器，微处理器，ASIC，或一个或多个用 于控制上述程序执行的集成电路。
另外需说明的是，以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。另外，本申请提供的装置实施例附图中，模块之间的连接关系表示它们之间具有通信连接，具体可以实现为一条或多条通信总线或信号线。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本申请可借助软件加必需的通用硬件的方式来实现，当然也可以通过专用硬件包括专用集成电路、专用CPU、专用存储器、专用元器件等来实现。一般情况下，凡由计算机程序完成的功能都可以很容易地用相应的硬件来实现，而且，用来实现同一功能的具体硬件结构也可以是多种多样的，例如模拟电路、数字电路或专用电路等。但是，对本申请而言更多情况下软件程序实现是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在可读取的存储介质中，如计算机的软盘、U盘、移动硬盘、ROM、RAM、磁碟或者光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，训练设备，或者网络设备等)执行本申请各个实施例所述的方法。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。
所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、训练设备或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、训练设备或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存储的任何可用介质或者是包含一个或多个可用介质集成的训练设备、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘(Solid State Disk，SSD))等。

Claims (68)

  1. 一种数据编码方法，其特征在于，应用于基于非对称数字系统ANS的编码器，所述方法包括：
    获取目标符号；
    通过第一映射关系，得到所述目标符号对应的第一信息和第二信息；所述第一信息和所述第二信息为根据所述目标符号对应的概率信息得到；
    根据所述第一信息以及所述编码器的状态信息，通过第一运算，得到第一编码数据；
    根据所述第二信息，通过第二运算，更新所述状态信息，得到第二编码数据；其中，
    所述第一编码数据和所述第二编码数据用于得到所述目标符号的编码结果，且所述第一运算和所述第二运算不包括除法运算。
  2. 根据权利要求1所述的方法，其特征在于，所述第一信息或所述第二信息表示一个整数数值。
  3. 根据权利要求1或2所述的方法，其特征在于，所述第一运算和所述第二运算不包括判断运算。
  4. 根据权利要求1至3任一所述的方法，其特征在于，所述第一运算包括：
    对所述第一信息与所述状态信息进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；从所述状态信息中选择部分比特作为第一编码数据，所述部分比特在所述状态信息中的位置为根据所述比特移位操作的移位结果确定。
  5. 根据权利要求1至4任一所述的方法，其特征在于，所述第二运算包括：
    对所述状态信息与数值M进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；其中，所述概率信息包括量化概率，所述M为所述量化概率的分母；对所述比特移位操作的移位结果与所述第二信息进行的加和操作；或者，
    在所述状态信息初始化为所述M的情况下，对所述状态信息进行的比特移位操作；对所述比特移位操作的移位结果与所述第二信息进行的加和操作；对所述加和操作的加和结果与所述M进行减法运算。
  6. 根据权利要求1至5任一所述的方法，其特征在于，所述概率信息包括概率质量函数PMF的数值；所述PMF的数值为通过如下方式构建的：
    依次确定多个符号中每个符号的PMF的数值，所述多个符号包括所述目标符号；其中，
    在确定所述目标符号的PMF的数值时，将除去已确定的符号的PMF之外的剩余PMF的总数值与所述目标符号的概率进行乘积，并计算所述乘积的乘积结果与除去已确定的符号的剩余概率之间的比值，根据所述比值与预设的第五数值之间的关系，确定所述目标符号的PMF。
  7. 根据权利要求6所述的方法，其特征在于，所述第一数值为1，所述关系为取较大值。
  8. 根据权利要求1至7任一所述的方法，其特征在于，所述概率信息包括累积分布函数CDF的数值；所述CDF的数值为通过如下方式构建的：
    基于预设顺序，依次确定每个符号的CDF的数值，其中所述预设顺序为根据多个符号对应的PMF的数值之间的关系确定，所述多个符号包括所述目标符号；其中，
    在所述目标符号的概率信息对应的概率分布为对称分布时，所述预设顺序为沿着所述对称分布中峰值点的两侧相交错的顺序；或者，
    在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从大到小的顺序；或者，
    在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从小到大的顺序。
  9. 根据权利要求1至8任一所述的方法，其特征在于，所述目标符号为对图像的像素数据进行变换得到，所述对图像的像素数据进行变换得到的数据满足预设分布，所述变换还用于得到所述像素数据的分布特征，所述分布特征包括均值或方差，所述方法还包括：
    根据所述分布特征，从多个映射关系中确定与所述分布特征对应的所述第一映射关系。
  10. 根据权利要求9所述的方法，其特征在于，所述多个分布特征包括第一分布特征和第二分布特征，所述第一分布特征的熵大于所述第二分布特征的熵；
    所述第二分布特征对应的映射关系中的量化概率的分母的数值大于所述第一分布特征对应的映射关系中的量化概率的分母。
  11. 根据权利要求1至10任一所述的方法，其特征在于，所述第一映射关系中的所述第一信息为通过如下方式构建的：
    将所述目标符号的PMF的数值中最高位连续为0的比特数量与预设的第六数值的加和运算；
    将所述加和运算的加和结果进行比特移位操作，并将所述比特移位操作的移位结果与对所述目标符号的PMF的数值进行比特移位操作的移位结果进行减法操作，得到所述第一信息；或者，
    将所述加和运算的加和结果进行比特移位操作，并将所述比特移位操作的移位结果与对所述目标符号的PMF的数值进行比特移位操作的移位结果进行减法操作，将所述减法操作的操作结果与数值M进行加和操作，得到所述第一信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
  12. 根据权利要求1至11任一所述的方法，其特征在于，所述第一映射关系中的所述第二信息为通过如下方式构建的：
    将所述目标符号的CDF的数值和所述目标符号的PMF的数值进行减法运算，得到所述第二信息；或者，
    将所述目标符号的CDF的数值和所述目标符号的PMF的数值进行减法运算，将所述减法操作的操作结果与数值M进行加和操作，得到所述第二信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
  13. 根据权利要求1至11任一所述的方法，其特征在于，所述第一映射关系中的所述第二信息为通过如下方式构建的：
    在所述目标符号的CDF的数值和所述目标符号的PMF的数值的减法运算的结果大于或等于0时，将所述减法运算的结果作为所述第二信息；或者，
    在所述目标符号的CDF的数值和所述目标符号的PMF的数值的减法运算的结果小于0时，将所述减法操作的操作结果与数值M进行加和操作，得到所述第二信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
  14. 根据权利要求1至13任一所述的方法，其特征在于，所述通过第一映射关系，得到所述目标符号对应的第一信息和第二信息，包括：
    通过第一映射关系，得到所述目标符号对应的一个整数数值；
    基于第三运算，将所述整数数值还原为所述第一信息和所述第二信息，所述第一信息和所述第二信息分别为一个整数数值。
  15. 根据权利要求1至14任一所述的方法，其特征在于，所述概率信息包括每个符号对应的PMF信息，所述PMF信息包括第一数值和第二数值；所述第一数值和所述第二数值的加和为所述PMF的数值；所述概率信息还包括每个符号对应的CDF信息，所述CDF信息包括第三数值和第四数值；所述第三数值和第四数值为通过如下方式构建的：
    基于预设顺序，根据多个符号的第一数值，通过累加依次确定每个符号的对应的第三数值；
    基于所述预设顺序，根据多个符号的第二数值和第三数值，通过累加依次确定每个符号对应的第四数值。
  16. 根据权利要求15所述的方法，其特征在于，所述第二信息包括第一子信息、第二子信息和第三子信息；
    所述第一映射关系中的所述第一子信息为通过如下方式构建的：将所述目标符号的第三数值和所述目标符号的PMF的数值进行减法运算，得到所述第一子信息；
    所述第一映射关系中的所述第二子信息为通过如下方式构建的：将所述目标符号的第三数值和所述目标符号的第一数值进行加法运算，将所述加法运算的操作结果与1进行减法操作，得到所述第二子信息；
    所述第一映射关系中的所述第三子信息为通过如下方式构建的：将所述目标符号的第四数值和所述目标符号的第三数值进行减法运算，将所述减法运算的操作结果与所述目标符号的第一数值进行减法操作，得到所述第三子信息。
  17. 根据权利要求16所述的方法，其特征在于，所述第二运算包括：
    对所述状态信息与数值M进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；其中，所述概率信息包括量化概率，所述M为所述量化概率的分母；对所述比特移位操作的移位结果与所述第一子信息进行的加和操作；
    在所述加和操作的操作结果大于所述第二子信息时，将所述加和操作的操作结果与所述第三子信息的加和结果作为所述第二编码数据；
    在所述加和操作的操作结果小于所述第二子信息时，将所述加和操作的操作结果作为所述第二编码数据。
  18. 根据权利要求16或17所述的方法，其特征在于，在所述数值M为256时，所述第一信息通过10比特存储，所述第一子信息通过8比特存储，所述第二子信息通过7比特存储，所述第三子信息通过7比特存储，多个符号的第一数值的加和为128，所述第三子信息小于128。
  19. 一种数据编码方法，其特征在于，应用于基于非对称数字系统ANS的编码器，所述方法包括：
    获取第一符号，所述第一符号对应的量化概率和第二符号对应的量化概率的和为1，且所述第一符号对应的量化概率和1的差异小于阈值，所述第二符号对应的量化概率和0的差异小于阈值；
    根据所述编码器的状态信息和数值M之间的数值大小关系满足第一条件，将所述状态信息和所述数值M之间进行第一运算，得到第一编码数据，并将所述状态信息更新为0；
    根据所述编码器的状态信息和数值M之间的数值大小关系不满足所述第一条件，将所述状态信息加1。
  20. 根据权利要求19所述的方法，其特征在于，所述方法还包括：
    获取所述第二符号；
    将所述编码器的状态信息作为第一编码数据，并将所述状态信息更新为所述数值M与1的差值。
  21. 一种数据解码方法，其特征在于，应用于基于非对称数字系统ANS的解码器，所述方法包括：
    获取所述解码器的状态信息以及存储比特，所述状态信息与第一比特相对应，所述第一比特为当前待解码的比特；
    根据第一映射关系，确定所述状态信息对应的第一信息、第二信息以及第三信息；所述第一信息为所述第一比特对应的目标符号，所述目标符号为所述第一比特的解码结果，所述第二信息表示从所述存储比特中选择的比特位数，所述第三信息用于和根据所述第三信息从所述存储比特中选择的比特进行加和运算，所述加和运算结果用于更新所述状态信息，更新后的状态信息与第二比特相对应，所述第二比 特为所述第一比特之后的待解码比特。
  22. 根据权利要求21所述的方法，其特征在于，所述方法还包括：
    从所述存储比特中剔除根据所述选择的比特，得到更新后的存储比特。
  23. 根据权利要求21或22所述的方法，其特征在于，所述第一信息、所述第二信息或所述第三信息表示一个整数数值。
  24. 根据权利要求21至23任一所述的方法，其特征在于，所述第一映射关系中的所述第一信息为通过如下方式构建的：
    将满足C(x)≤s<(C(x)+P(x))的x作为所述第一信息；其中，所述C表示CDF的数值，所述P表示PMF的数值，所述s表示所述状态信息。
  25. 根据权利要求21至23任一所述的方法，其特征在于，所述第一映射关系中的所述第一信息为通过如下方式构建的：
    将满足C1(x)≤s<C1(x)+P1(x)或C2(x)≤s<C2(x)+P2(x)的x作为所述第一信息；其中，所述C1表示CDF对应的第三数值，所述P1表示PMF对应的第一数值，所述C2表示CDF对应的第四数值，所述P2表示PMF对应的第二数值，所述s表示所述状态信息；所述第一数值和所述第二数值的加和为所述PMF的数值。
  26. 根据权利要求21至25任一所述的方法，其特征在于，所述第一映射关系中的所述第二信息为通过如下方式构建的：
    将clz(s-C(x)+P(x))+X的数值作为所述第二信息；其中，所述clz表示取数值中最高位连续为0的比特数量，所述X为预设的第五数值。
  27. 根据权利要求21至25任一所述的方法，其特征在于，所述第一映射关系中的所述第二信息为通过如下方式构建的：
    将clz(s′-C(x)+P(x))+X的数值作为所述第二信息；其中，所述clz表示取数值中最高位连续为0的比特数量，所述X为预设的第五数值，所述s′为通过如下得到：
    若C2(x)≤s，则s’＝P1(x)+s-C2(x)+P(x)，否则s’＝s-C1(x)+P(x)。
  28. 根据权利要求21至27任一所述的方法，其特征在于，所述第一映射关系中的所述第三信息为通过如下方式构建的：
    将s-C(x)+P(x)的数值进行比特移位操作，得到所述第三信息，所述比特移位操作的移位数量为根据所述第二信息得到；或者，
    将s-C(x)+P(x)的数值进行比特移位操作，并将所述比特移位操作的操作结果减去数值M，得到所述第三信息，所述M为所述量化概率的分母，所述比特移位操作的移位数量为根据所述第二信息得到；或者，
    将s′-C(x)+P(x)的数值进行比特移位操作，得到所述第三信息，所述比特移位操作的移位数量为根据所述第二信息得到。
  29. 根据权利要求21至28任一所述的方法，其特征在于，所述第一信息、所述第二信息或所述第三信息为根据概率信息得到；所述概率信息包括概率质量函数PMF的数值；所述PMF的数值为通过如下方式构建的：
    依次确定多个符号中每个符号的PMF的数值，所述多个符号包括所述目标符号；其中，
    在确定所述目标符号的PMF的数值时，将除去已确定的符号的PMF之外的剩余PMF的总数值与所述 目标符号的概率进行乘积，并计算所述乘积的乘积结果与除去已确定的符号的剩余概率之间的比值，根据所述比值与预设数值之间的关系，确定所述目标符号的PMF。
  30. 根据权利要求21至29任一所述的方法，其特征在于，所述第一信息、所述第二信息或所述第三信息为根据概率信息得到；所述概率信息包括累积分布函数CDF的数值；所述CDF的数值为通过如下方式构建的：
    基于预设顺序，依次确定每个符号的CDF的数值，其中所述预设顺序为根据多个符号对应的PMF的数值之间的关系确定，所述多个符号包括所述目标符号；其中，
    在所述目标符号的概率信息对应的概率分布为对称分布时，所述预设顺序为沿着所述对称分布中峰值点的两侧相交错的顺序；或者，
    在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从大到小的顺序；或者，
    在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从小到大的顺序。
  31. 根据权利要求21至30任一所述的方法，其特征在于，所述方法还包括：
    获取编码结果；所述编码结果为对图像的像素数据进行编码得到的，所述状态信息以及所述存储比特为根据所述编码结果得到；
    对所述编码结果进行处理，所述像素数据的分布特征，所述分布特征包括均值或方差；
    根据所述分布特征，从多个映射关系中确定与所述分布特征对应的所述第一映射关系。
  32. 根据权利要求21至31任一所述的方法，其特征在于，所述根据第一映射关系，确定所述状态信息对应的第一信息、第二信息以及第三信息，包括：
    通过第一映射关系，得到所述状态信息对应的一个整数数值；
    将所述整数数值还原为所述第一信息、所述第二信息和所述第三信息，所述第一信息、所述第二信息和所述第三信息分别为一个整数数值。
  33. 一种数据解码方法，其特征在于，应用于基于非对称数字系统ANS的解码器，所述方法包括：
    获取所述解码器的状态信息，所述状态信息与第一比特相对应，所述第一比特为当前待解码的比特；
    若所述状态信息为数值M与1的差值，则确定所述第一比特的解码结果为第二符号，并将所述状态信息更新为从存储中读取所述数值M位的结果；
    若所述状态信息不为数值M与1的差值，则确定所述第一比特的解码结果为第一符号，若所述状态信息为0，则将所述状态信息更新为所述数值M与2的差值与从存储中读出1个比特的值的加和结果；若所述状态信息不为0，则将所述状态信息更新为所述状态信息与1的差值；更新后的状态信息与第二比特相对应，所述第二比特为所述第一比特之后的待解码比特。
  34. 一种数据编码装置，其特征在于，应用于基于非对称数字系统ANS的编码器，所述装置包括：
    获取模块，用于获取目标符号；
    编码模块，用于通过第一映射关系，得到所述目标符号对应的第一信息和第二信息；所述第一信息和所述第二信息为根据所述目标符号对应的概率信息得到；
    根据所述第一信息以及所述编码器的状态信息，通过第一运算，得到第一编码数据；
    根据所述第二信息，通过第二运算，更新所述状态信息，得到第二编码数据；其中，
    所述第一编码数据和所述第二编码数据用于得到所述目标符号的编码结果，且所述第一运算和所述第二运算不包括除法运算。
  35. 根据权利要求34所述的装置，其特征在于，所述第一信息或所述第二信息表示一个整数数值。
  36. 根据权利要求34或35所述的装置，其特征在于，所述第一运算和所述第二运算不包括判断运算。
  37. 根据权利要求34至36任一所述的装置，其特征在于，所述第一运算包括：
    对所述第一信息与所述状态信息进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；
    从所述状态信息中选择部分比特作为第一编码数据，所述部分比特在所述状态信息中的位置为根据所述比特移位操作的移位结果确定。
  38. 根据权利要求34至37任一所述的装置，其特征在于，所述第二运算包括：
    对所述状态信息与数值M进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；其中，所述概率信息包括量化概率，所述M为所述量化概率的分母；
    对所述比特移位操作的移位结果与所述第二信息进行的加和操作。
  39. 根据权利要求34至38任一所述的装置，其特征在于，所述概率信息包括概率质量函数PMF的数值；所述PMF的数值为通过如下方式构建的：
    依次确定多个符号中每个符号的PMF的数值，所述多个符号包括所述目标符号；其中，
    在确定所述目标符号的PMF的数值时，将除去已确定的符号的PMF之外的剩余PMF的总数值与所述目标符号的概率进行乘积，并计算所述乘积的乘积结果与除去已确定的符号的剩余概率之间的比值，根据所述比值与预设的第五数值之间的关系，确定所述目标符号的PMF。
  40. 根据权利要求39所述的装置，其特征在于，所述第五数值为1，所述关系为取较大值。
  41. 根据权利要求34至40任一所述的装置，其特征在于，所述概率信息包括累积分布函数CDF的数值；所述CDF的数值为通过如下方式构建的：
    基于预设顺序，依次确定每个符号的CDF的数值，其中所述预设顺序为根据多个符号对应的PMF的数值之间的关系确定，所述多个符号包括所述目标符号；其中，
    在所述目标符号的概率信息对应的概率分布为对称分布时，所述预设顺序为沿着所述对称分布中峰值点的两侧相交错的顺序；或者，
    在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从大到小的顺序；或者，
    在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从小到大的顺序。
  42. 根据权利要求34至41任一所述的装置，其特征在于，所述目标符号为对图像的像素数据进行变换得到，所述对图像的像素数据进行变换得到的数据满足预设分布，所述变换还用于得到所述像素数据的分布特征，所述分布特征包括均值或方差，所述获取模块，还用于：
    根据所述分布特征，从多个映射关系中确定与所述分布特征对应的所述第一映射关系。
  43. 根据权利要求42所述的装置，其特征在于，所述多个分布特征包括第一分布特征和第二分布特征，所述第一分布特征的熵大于所述第二分布特征的熵；
    所述第二分布特征对应的映射关系中的量化概率的分母的数值大于所述第一分布特征对应的映射关系中的量化概率的分母。
  44. 根据权利要求34至43任一所述的装置，其特征在于，所述第一映射关系中的所述第一信息为通过如下方式构建的：
    将所述目标符号的PMF的数值中最高位连续为0的比特数量与预设的第六数值的加和运算；
    将所述加和运算的加和结果进行比特移位操作，并将所述比特移位操作的移位结果与对所述目标符号的PMF的数值进行比特移位操作的移位结果进行减法操作，得到所述第一信息；或者，
    将所述加和运算的加和结果进行比特移位操作，并将所述比特移位操作的移位结果与对所述目标符号的PMF的数值进行比特移位操作的移位结果进行减法操作，将所述减法操作的操作结果与数值M进行加和操作，得到所述第一信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
  45. 根据权利要求34至44任一所述的装置，其特征在于，所述第一映射关系中的所述第二信息为通过如下方式构建的：
    将所述目标符号的CDF的数值和所述目标符号的PMF的数值进行减法运算，得到所述第二信息；或者，
    将所述目标符号的CDF的数值和所述目标符号的PMF的数值进行减法运算，将所述减法操作的操作结果与数值M进行加和操作，得到所述第二信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
  46. 根据权利要求34至44任一所述的装置，其特征在于，所述第一映射关系中的所述第二信息为通过如下方式构建的：
    在所述目标符号的CDF的数值和所述目标符号的PMF的数值的减法运算的结果大于或等于0时，将所述减法运算的结果作为所述第二信息；或者，
    在所述目标符号的CDF的数值和所述目标符号的PMF的数值的减法运算的结果小于0时，将所述减法操作的操作结果与数值M进行加和操作，得到所述第二信息，所述概率信息包括量化概率，所述M为所述量化概率的分母。
  47. 根据权利要求34至46任一所述的装置，其特征在于，所述编码模块，具体用于：
    通过第一映射关系，得到所述目标符号对应的一个整数数值；
    基于第三运算，将所述整数数值还原为所述第一信息和所述第二信息，所述第一信息和所述第二信息分别为一个整数数值。
  48. 根据权利要求34至47任一所述的装置，其特征在于，所述概率信息包括每个符号对应的PMF信息，所述PMF信息包括第一数值和第二数值；所述第一数值和所述第二数值的加和为所述PMF的数值；所述概率信息还包括每个符号对应的CDF信息，所述CDF信息包括第三数值和第四数值；所述第三数值和第四数值为通过如下方式构建的：
    基于预设顺序，根据多个符号的第一数值，通过累加依次确定每个符号的对应的第三数值；
    基于所述预设顺序，根据多个符号的第二数值和第三数值，通过累加依次确定每个符号对应的第四数值。
  49. 根据权利要求48所述的装置，其特征在于，所述第二信息包括第一子信息、第二子信息和第三子信息；
    所述第一映射关系中的所述第一子信息为通过如下方式构建的：将所述目标符号的第三数值和所述目标符号的PMF的数值进行减法运算，得到所述第一子信息；
    所述第一映射关系中的所述第二子信息为通过如下方式构建的：将所述目标符号的第三数值和所述目标符号的第一数值进行加法运算，将所述加法运算的操作结果与1进行减法操作，得到所述第二子信息；
    所述第一映射关系中的所述第三子信息为通过如下方式构建的：将所述目标符号的第四数值和所述目标符号的第三数值进行减法运算，将所述减法运算的操作结果与所述目标符号的第一数值进行减法操作，得到所述第三子信息。
  50. 根据权利要求49所述的装置，其特征在于，所述第二运算包括：
    对所述状态信息与数值M进行的加和操作，以及对所述加和操作的加和结果进行的比特移位操作；其中，所述概率信息包括量化概率，所述M为所述量化概率的分母；对所述比特移位操作的移位结果与所述第一子信息进行的加和操作；
    在所述加和操作的操作结果大于所述第二子信息时，将所述加和操作的操作结果与所述第三子信息的加和结果作为所述第二编码数据；
    在所述加和操作的操作结果小于所述第二子信息时，将所述加和操作的操作结果作为所述第二编码数据。
  51. 根据权利要求49或50所述的装置，其特征在于，在所述数值M为256时，所述第一信息通过10比特存储，所述第一子信息通过8比特存储，所述第二子信息通过7比特存储，所述第三子信息通过7比特存储，多个符号的第一数值的加和为128，所述第三子信息小于128。
  52. 一种数据编码装置，其特征在于，应用于基于非对称数字系统ANS的编码器，所述装置包括：
    获取模块，用于获取第一符号，所述第一符号对应的量化概率和第二符号对应的量化概率的和为1，且所述第一符号对应的量化概率和1的差异小于阈值，所述第二符号对应的量化概率和0的差异小于阈值；
    编码模块，用于根据所述编码器的状态信息和数值M之间的数值大小关系满足第一条件，将所述状态信息和所述数值M之间进行第一运算，得到第一编码数据，并将所述状态信息更新为0；
    根据所述编码器的状态信息和数值M之间的数值大小关系不满足所述第一条件，将所述状态信息加1。
  53. 根据权利要求52所述的装置，其特征在于，所述获取模块，还用于：
    获取所述第二符号；
    所述编码模块，还用于将所述编码器的状态信息作为第一编码数据，并将所述状态信息更新为所述数值M与1的差值。
  54. 一种数据解码装置，其特征在于，应用于基于非对称数字系统ANS的解码器，所述装置包括：
    获取模块，用于获取所述解码器的状态信息以及存储比特，所述状态信息与第一比特相对应，所述第一比特为当前待解码的比特；
    解码模块，用于根据第一映射关系，确定所述状态信息对应的第一信息、第二信息以及第三信息；所述第一信息为所述第一比特对应的目标符号，所述目标符号为所述第一比特的解码结果，所述第二信息表示从所述存储比特中选择的比特位数，所述第三信息用于和根据所述第三信息从所述存储比特中选择的比特进行加和运算，所述加和运算结果用于更新所述状态信息，更新后的状态信息与第二比特相对应，所述第二比特为所述第一比特之后的待解码比特。
  55. 根据权利要求54所述的装置，其特征在于，所述解码模块，还用于：
    从所述存储比特中剔除根据所述选择的比特，得到更新后的存储比特。
  56. 根据权利要求54或55所述的装置，其特征在于，所述第一信息、所述第二信息或所述第三信息表示一个整数数值。
  57. 根据权利要求54至56任一所述的装置，其特征在于，所述第一映射关系中的所述第一信息为通过如下方式构建的：
    将满足C(x)≤s<(C(x)+P(x))的x作为所述第一信息；其中，所述C表示CDF的数值，所述P表示PMF的数值，所述s表示所述状态信息；或者，
    将满足C1(x)≤s<C1(x)+P1(x)或C2(x)≤s<C2(x)+P2(x)的x作为所述第一信息；其中，所述C1表示CDF对应的第三数值，所述P1表示PMF对应的第一数值，所述C2表示CDF对应的第四数值，所述P2表示PMF对应的第二数值，所述s表示所述状态信息；所述第一数值和所述第二数值的加和为所述PMF的数值。
  58. 根据权利要求54至57任一所述的装置，其特征在于，所述第一映射关系中的所述第二信息为通过如下方式构建的：
    将clz(s-C(x)+P(x))+X的数值作为所述第二信息；其中，所述clz表示取数值中最高位连续为0的比特数量，所述X为预设的第五数值；或者，
    将s-C(x)+P(x)的数值进行比特移位操作，得到所述第三信息，所述比特移位操作的移位数量为根据所述第二信息得到；或者，
    将s-C(x)+P(x)的数值进行比特移位操作，并将所述比特移位操作的操作结果减去数值M，得到所述第三信息，所述M为所述量化概率的分母，所述比特移位操作的移位数量为根据所述第二信息得到；或者，
    将clz(s′-C(x)+P(x))+X的数值作为所述第二信息；其中，所述clz表示取数值中最高位连续为0的比特数量，所述X为预设的第五数值，所述s′为通过如下得到：
    若C2(x)≤s，则s’＝P1(x)+s-C2(x)+P(x)，否则s’＝s-C1(x)+P(x)。
  59. 根据权利要求54至58任一所述的装置，其特征在于，所述第一映射关系中的所述第三信息为通过如下方式构建的：
    将s-C(x)+P(x)的数值进行比特移位操作，得到所述第三信息，所述比特移位操作的移位数量为根据所述第二信息得到；或者，
    将s-C(x)+P(x)的数值进行比特移位操作，并将所述比特移位操作的操作结果减去数值M，得到所述第三信息，所述M为所述量化概率的分母，所述比特移位操作的移位数量为根据所述第二信息得到；或者，
    将s′-C(x)+P(x)的数值进行比特移位操作，得到所述第三信息，所述比特移位操作的移位数量为根据所述第二信息得到。
  60. 根据权利要求54至59任一所述的装置，其特征在于，所述第一信息、所述第二信息或所述第三信息为根据概率信息得到；所述概率信息包括概率质量函数PMF的数值；所述PMF的数值为通过如下方式构建的：
    依次确定多个符号中每个符号的PMF的数值，所述多个符号包括所述目标符号；其中，
    在确定所述目标符号的PMF的数值时，将除去已确定的符号的PMF之外的剩余PMF的总数值与所述目标符号的概率进行乘积，并计算所述乘积的乘积结果与除去已确定的符号的剩余概率之间的比值，根据所述比值与预设数值之间的关系，确定所述目标符号的PMF。
  61. 根据权利要求60所述的装置，其特征在于，所述预设数值为1，所述关系为取较大值。
  62. 根据权利要求54至61任一所述的装置，其特征在于，所述第一信息、所述第二信息或所述第三信息为根据概率信息得到；所述概率信息包括累积分布函数CDF的数值；所述CDF的数值为通过如下方式构建的：
    基于预设顺序，依次确定每个符号的CDF的数值，其中所述预设顺序为根据多个符号对应的PMF的数值之间的关系确定，所述多个符号包括所述目标符号；其中，
    在所述目标符号的概率信息对应的概率分布为对称分布时，所述预设顺序为沿着所述对称分布中峰值点的两侧相交错的顺序；或者，
    在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从大到小的顺序； 或者，
    在所述目标符号的概率信息对应的概率分布为离散分布时，所述预设顺序具体为从小到大的顺序。
  63. 根据权利要求54至62任一所述的装置，其特征在于，所述获取模块，还用于：
    获取编码结果；所述编码结果为对图像的像素数据进行编码得到的，所述状态信息以及所述存储比特为根据所述编码结果得到；
    对所述编码结果进行处理，所述像素数据的分布特征，所述分布特征包括均值或方差；
    根据所述分布特征，从多个映射关系中确定与所述分布特征对应的所述第一映射关系。
  64. 根据权利要求54至63任一所述的装置，其特征在于，所述解码模块，具体用于：
    通过第一映射关系，得到所述状态信息对应的一个整数数值；
    将所述整数数值还原为所述第一信息、所述第二信息和所述第三信息，所述第一信息、所述第二信息和所述第三信息分别为一个整数数值。
  65. 一种数据解码装置，其特征在于，应用于基于非对称数字系统ANS的解码器，所述装置包括：
    获取模块，用于获取所述解码器的状态信息，所述状态信息与第一比特相对应，所述第一比特为当前待解码的比特；
    解码模块，用于若所述状态信息为数值M与1的差值，则确定所述第一比特的解码结果为第二符号，并将所述状态信息更新为从存储中读取所述数值M位的结果；
    若所述状态信息不为数值M与1的差值，则确定所述第一比特的解码结果为第一符号，若所述状态信息为0，则将所述状态信息更新为所述数值M与2的差值与从存储中读出1个比特的值的加和结果；若所述状态信息不为0，则将所述状态信息更新为所述状态信息与1的差值；更新后的状态信息与第二比特相对应，所述第二比特为所述第一比特之后的待解码比特。
  66. 一种计算设备，其特征在于，所述计算设备包括存储器和处理器；所述存储器存储有代码，所述处理器被配置为获取所述代码，并执行如权利要求1至33任一所述的方法。
  67. 一种计算机存储介质，其特征在于，所述计算机存储介质存储有一个或多个指令，所述指令在由一个或多个计算机执行时使得所述一个或多个计算机实施权利要求1至33任一所述的方法。
  68. 一种计算机程序产品，包括代码，其特征在于，在所述代码被执行时用于实现如权利要求1至33任一所述的方法。
PCT/CN2024/071323 2023-01-09 2024-01-09 一种数据编解码方法及相关装置 Ceased WO2024149238A1 (zh)

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CN114598873A (zh) * 2020-12-03 2022-06-07 华为技术有限公司 量化参数的解码方法和装置

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US20190387232A1 (en) * 2018-06-19 2019-12-19 Qualcomm Incorporated Efficient weighted probability estimation for binary arithmetic coding
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