WO2024169252A1 - 逆导型绝缘栅双极晶体管及其制备方法 - Google Patents

逆导型绝缘栅双极晶体管及其制备方法 Download PDF

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Publication number
WO2024169252A1
WO2024169252A1 PCT/CN2023/129176 CN2023129176W WO2024169252A1 WO 2024169252 A1 WO2024169252 A1 WO 2024169252A1 CN 2023129176 W CN2023129176 W CN 2023129176W WO 2024169252 A1 WO2024169252 A1 WO 2024169252A1
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Prior art keywords
region
conductivity type
drift
emitter
doped
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English (en)
French (fr)
Inventor
张福胜
谢梓翔
李春艳
廖勇波
马颖江
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Gree Electric Appliances Inc of Zhuhai
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Gree Electric Appliances Inc of Zhuhai
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/491—Vertical IGBTs having both emitter contacts and collector contacts in the same substrate side
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/161—IGBT having built-in components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/417—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the collector side relative to other parts of the drift region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/418—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the emitter side relative to other parts of the drift region
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular to a reverse conducting insulated gate bipolar transistor and a method for preparing the same.
  • Insulated gate bipolar transistor is a key semiconductor component in electronic systems and is widely used in various medium and high voltage power control systems, such as motor drive and power conversion.
  • IGBT devices contain three electrodes: collector, emitter and gate for controlling the switching of the device.
  • the gate When the gate is turned off, the IGBT of the related technology is equivalent to a PNP type triode with an open base, so it does not have the reverse freewheeling capability, resulting in the IGBT of the related technology being only a unidirectional conduction device, that is, the current can only flow from the collector to the emitter.
  • RC-IGBT reverse-conducting insulated gate bipolar transistor
  • RC-IGBT integrates the reverse parallel diode and the IGBT of related technology on the same chip, so that the current of RC-IGBT can flow from the collector to the emitter or from the emitter to the collector, replacing the reverse parallel separated freewheeling diode device of the IGBT of related technology, saving about 1/3 of the total chip area, and significantly reducing the chip production and manufacturing costs and packaging and testing costs.
  • this integrated diode structure can reduce the thermal resistance of the diode and significantly improve its surge current resistance, while significantly reducing the disadvantage of large fluctuations in chip junction temperature and improving the power cycle capability of the device.
  • the RC-IGBT has the problem of poor reverse recovery performance of the diode. If the carrier lifetime control technology is used to increase the reverse recovery speed of the diode and reduce the reverse recovery loss, it will have an adverse effect on the performance and reliability of the IGBT in the working mode.
  • the purpose of the present disclosure is to provide a reverse-conducting insulated gate bipolar transistor and a preparation method thereof, which can optimize the reverse recovery performance of the RC-IGBT and reduce the turn-off loss of the diode without significantly increasing the process and cost.
  • an embodiment of the present disclosure provides a reverse-conducting insulated gate bipolar transistor, comprising: a drift region doped with a first conductive type; a base region doped with a second conductive type formed on the surface of the drift region, the base region comprising an active region and a virtual cell region that are staggered; a plurality of trenches extending from the surface of the drift region into the drift region and arranged in parallel, the trenches passing through the base region and contacting the drift region at the bottom, an insulating dielectric layer and a conductive material surrounded by the insulating dielectric layer being arranged in the trenches, the conductive material being led out from the first metal layer at the top to form a gate electrode; an emitter region heavily doped with the first conductive type and a contact region heavily doped with the second conductive type are formed on the surface of the active region of the base region, the first side surface of the emitter region is adjacent to the side surface of the corresponding trench, and the second side surface of the
  • the side surface is adjacent to the contact area, and the emitter area and the contact area are jointly led out from the first metal layer to form an emitter;
  • a buffer layer doped with the first conductive type is formed on the back side of the drift area;
  • a collector area heavily doped with the second conductive type and a cathode area heavily doped with the first conductive type are formed on the surface of the buffer layer with staggered distribution, and the collector area and the cathode area are jointly led out from the second metal layer to form a collector;
  • the IGBT unit is composed of the emitter area corresponding to the active area, the contact area and the adjacent base area, the drift area and the collector area;
  • the virtual cell area serves as the transistor anode area, and the reverse recovery transistor unit is composed of the base area corresponding to the transistor anode area and the adjacent contact area, the drift area and the cathode area; wherein the insulating dielectric layer of the trench located in the virtual cell area is provided with a groove.
  • the depth of the groove is 0.8 ⁇ m ⁇ 0.1 ⁇ m.
  • an oxide layer is further formed between the first metal layer and tops of the plurality of trenches.
  • the reverse conducting insulated gate bipolar transistor further includes a carrier storage layer between the drift region and the base region, the carrier storage layer being adjacent to side surfaces of adjacent trenches.
  • the insulating dielectric layer is made of silicon dioxide, and the conductive material is made of polysilicon.
  • any one of the first conductivity type and the second conductivity type is an n-type, and the other of the first conductivity type and the second conductivity type is a p-type.
  • an embodiment of the present disclosure provides a method for preparing a reverse-conducting insulated gate bipolar transistor as described above, comprising: forming a drift region doped with a first conductive type; forming a base region doped with a second conductive type on the upper surface of the drift region by ion implantation and/or diffusion, the base region comprising an active region and a virtual cell region that are staggered; etching a plurality of parallel grooves on the upper surface of the drift region, the grooves passing through the base region and the bottoms of the grooves being in contact with the drift region; forming an insulating dielectric layer on the inner walls of the grooves, and filling the grooves with conductive material; forming a groove in the insulating dielectric layer of the grooves located in the virtual cell region by dry etching; etching a groove on the upper surface of the active region of the base region by ion implantation and/or diffusion.
  • a first metal layer is deposited on the surface of the emitter region and the contact region, and a conductive material is led out from the top of the first metal layer to form a gate electrode, and the emitter region and the contact region are jointly led out from the first metal layer to form an emitter; thinning is performed on the back side of the drift region, and a buffer layer doped with the first conductivity type is formed by deep ion injection and/or diffusion; shallow injection of first conductivity type ions is performed on the surface of the buffer layer to form a cathode region heavily doped with the first conductivity type; shallow injection of second conductivity type ions is performed on the surface of the buffer layer to form a collector region heavily doped with the second conductivity type, and the collector region and the cathode region are staggered; a second metal layer is deposited on the surface of the collector region and the cathode region, and the collector region
  • the preparation method before depositing the first metal layer, the preparation method further includes forming an oxide layer on top of the plurality of trenches.
  • the preparation method before forming the base region, further includes forming a carrier storage layer doped with the first conductivity type on the surface of the drift region by deep ion implantation and/or diffusion, and the trench penetrates the carrier storage layer.
  • the dry etching gas is any one of octafluorocyclopentene, carbon tetrafluoride and trifluoromethane.
  • a base region doped with a second conductive type is formed on the surface of a drift region doped with a first conductive type, the base region including an active region and a virtual cell region that are staggered; a plurality of trenches extending from the surface of the drift region into the drift region and arranged in parallel, the trenches passing through the base region and contacting the drift region at the bottom, an insulating dielectric layer and a conductive material surrounded by the insulating dielectric layer are arranged in the trenches, the conductive material is led out from the first metal layer at the top to form a gate electrode; an emitter region heavily doped with the first conductive type and a contact region heavily doped with the second conductive type are formed on the surface of the active region of the base region, the first side surface of the emitter region is adjacent to the side surface of the corresponding trench, and the second side surface of the emitter region is adjacent to the side surface
  • the emitter area and the contact area are jointly led out from the first metal layer to form an emitter;
  • a buffer layer doped with the first conductive type is formed on the back of the drift area;
  • a collector area heavily doped with the second conductive type and a cathode area heavily doped with the first conductive type are formed on the surface of the buffer layer with staggered distribution, and the collector area and the cathode area are jointly led out from the second metal layer to form a collector;
  • the IGBT unit is composed of the contact area, the emitter area and the adjacent trench, the base area, the drift area and the collector area corresponding to the active area;
  • the virtual cell area serves as the transistor anode area, and the reverse recovery transistor unit is composed of the trench, the base area, the drift area and the cathode area corresponding to the transistor anode area; wherein the insulating dielectric layer of the trench located in the virtual cell area is provided with a groove.
  • the concentration of electron holes in the vicinity can be reduced, thereby reducing the carrier injection efficiency, optimizing the reverse recovery performance of the RC-IGBT, and reducing the turn-off loss of the diode.
  • FIG1 is a schematic diagram showing the structure of a reverse-conducting insulated gate bipolar transistor provided by an embodiment of the present disclosure
  • FIG2 is a schematic diagram showing a partial enlarged structure of a virtual cell region of the reverse conducting insulated gate bipolar transistor shown in FIG1 ;
  • FIG3 is a schematic diagram showing a reverse recovery waveform simulation of the reverse conducting insulated gate bipolar transistor shown in FIG1 ;
  • FIG. 4 is a scatter diagram showing a trade-off relationship between the reverse breakdown voltage and the reverse recovery loss of the reverse conducting insulated gate bipolar transistor shown in FIG. 1 .
  • Drift region 1. Drift region; 2. Base region; 21. Active region; 22. Virtual cell region; 3. Groove; 30. Carrier storage layer; 31. Insulating dielectric layer; 32. Conductive material; 33. Recess; 41. Emitter region; 42. Contact region; 5. First metal layer; 50. Oxide layer; 6. Buffer layer; 71. Collector region; 72. Cathode region; 8. Second metal layer; G. Gate electrode; E. Emitter; C. Collector.
  • FIG1 is a schematic diagram showing the structure of a reverse conducting insulated gate bipolar transistor provided in an embodiment of the present disclosure
  • FIG2 is a schematic diagram showing a local enlarged structure of a virtual cell region of the reverse conducting insulated gate bipolar transistor shown in FIG1 .
  • the reverse conducting insulated gate bipolar transistor (hereinafter referred to as RC-IGBT) provided in the embodiment of the present disclosure includes:
  • a base region 2 doped with a second conductive type is formed on the surface of the drift region 1, and the base region 2 includes an active region 21 and a dummy cell region (Dummy) 22 that are staggered;
  • An emitter region 41 heavily doped with a first conductivity type and a contact region 42 heavily doped with a second conductivity type are formed on the surface of the active region 21 of the base region 2.
  • a first side surface of the emitter region 41 is adjacent to a side surface of the corresponding trench 3, and a second side surface of the emitter region 41 is adjacent to the contact region 42.
  • the emitter region 41 and the contact region 42 are jointly led out from the first metal layer 5 to form an emitter E.
  • a buffer layer 6 doped with a first conductivity type is formed on the back side of the drift region 1;
  • a collector region 71 heavily doped with the second conductivity type and a cathode region 72 heavily doped with the first conductivity type are formed in a staggered manner.
  • the collector region 71 and the cathode region 72 are jointly led out from the second metal layer 8 to form a collector electrode C.
  • the IGBT unit is composed of the emitter region 41 corresponding to the active region 21, the contact region 42 and the adjacent base region 2, the drift region 1 and the collector region 71;
  • the virtual cell region 22 serves as the anode region of the transistor, and the base region 2 corresponding to the anode region of the transistor and its adjacent contact region 42, the drift region 1 and the cathode region 72 form a reverse recovery transistor unit;
  • the insulating dielectric layer 31 of the trench 3 in the dummy cell region 22 is provided with a groove 33 .
  • any one of the first conductivity type and the second conductivity type is n-type, and the other of the first conductivity type and the second conductivity type is p-type.
  • the semiconductor substrate of the device is considered to be composed of silicon (Si) material.
  • the substrate can also be composed of any other material suitable for manufacturing RC-IGBT, such as germanium (Ge), silicon carbide (SiC), etc.
  • the material of the insulating dielectric layer of the device can be composed of silicon oxide ( SiOx ), but other dielectric materials can also be used, such as silicon nitride ( SixNy ) , aluminum oxide ( AlxOy ) and silicon oxynitride ( SixNyOz ).
  • a p-type conductive semiconductor region can be formed by doping one or more impurities into the original semiconductor region. These impurities can be but are not limited to: boron (B), aluminum (Al), gallium (Ga), etc.
  • An n-type conductive semiconductor region can also be formed by doping the original semiconductor region with one or more impurities, which can be but are not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (H+), etc.
  • impurities can be but are not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (H+), etc.
  • the heavily doped p-type conductive semiconductor region is marked as p+ region
  • the heavily doped p-type conductive semiconductor region is marked as p+ region
  • the doped n-type conductive semiconductor region is marked as an n+ region.
  • the impurity concentration of a heavily doped region is generally between 1 ⁇ 1019cm -3 and 1 ⁇ 1021cm -3 .
  • the lightly doped p-type conductive semiconductor region is marked as a p-region
  • the lightly doped n-type conductive semiconductor region is marked as an n-region.
  • the impurity concentration of a lightly doped region is generally between 1 ⁇ 1012cm -3 and 1 ⁇ 1015cm -3 .
  • n-type MOS channel RC-IGBT device wherein the first conductivity type is n-type and the second conductivity type is p-type.
  • present disclosure is also applicable to a p-type MOS channel RC-IGBT device.
  • the drift region 1 is lightly doped with n-, and the base region 2 is p-doped on the basis of the drift region 1.
  • the emitter region 41 is heavily doped with n+, and the contact region 42 is heavily doped with p+.
  • the buffer layer 6 is lightly doped with n-.
  • the collector region 71 is heavily doped with p+, and the cathode region 72 is heavily doped with n+.
  • the insulating dielectric layer 31 is made of silicon dioxide SiO 2
  • the conductive material 32 is made of polycrystalline silicon Si.
  • the active region 21 and the dummy cell region 22 are alternately distributed along the lateral direction of the device, some of the trenches 3 are located in the active region 21, such as the two trenches 3 shown in FIG. 1 are located in the active region 21; some of the trenches 3 are located in the dummy cell region 22, such as the two trenches 3 shown in FIG. 1 are located in the dummy cell region 22.
  • the process parameters of the virtual cell region 22 are consistent with those of the active region 21, except that the virtual cell region 22 does not contain an n+ heavily doped region and has no emitter region lead-out, so it can be used as the anode of the reverse diode path.
  • the main function of the virtual cell region 22 is to reduce the current gain of the trench gate IGBT, reduce the short-circuit current amplitude of the IGBT, shield the peak electric field of the diode, and improve the short-circuit reliability.
  • a groove 33 is etched in the insulating dielectric layer 31 of the groove 3 in the virtual cell region 22, while a groove 33 is not etched in the insulating dielectric layer 31 of the groove 3 in the active region 21.
  • the RC-IGBT device has three electrodes: an emitter E at the top, a collector C at the bottom, and a gate electrode G.
  • the gate electrode G, the insulating dielectric layer 31, the p-base region 2, the n+ type emitter region 41, the p+ contact region 42 and the n-drift region 1 together constitute a metal-oxide-semiconductor (hereinafter referred to as "MOS") structure.
  • MOS metal-oxide-semiconductor
  • the p-base region 2, the n-drift region 1 and the p+ collector region 71 on the back together constitute a PNP bipolar transistor.
  • the MOS structure and the PNP tube together constitute an IGBT structure, so that the MOS structure can be used to control the current of the PNP tube to flow from the collector C to the emitter E, which is called the forward conduction of the RC-IGBT current.
  • the p+ contact region 42, the p-base region 2, the n-drift region 1 and the n+ cathode region 72 on the back together form a PIN diode (i.e., a reverse recovery transistor unit), wherein the p+ contact region 42 and the p-base region 2 serve as the anode of the PIN diode, and the n+ cathode region 72 serves as the cathode of the PIN diode.
  • the PIN diode When the voltage of the emitter E of the RC-IGBT device is higher than the preset voltage value of the collector C, the PIN diode The electrode tube can be turned on, and then the current flows from the emitter E to the collector C, which is called reverse conduction of the RC-IGBT current.
  • the first conduction path is from the front p-base region 2 to the n-drift region 1, then passes through the n-buffer layer 6, and finally flows out from the back n+ cathode region 72.
  • the device is equivalent to a PIN diode structure. The holes injected from the front and the electrons injected from the back are used to modulate the conductivity in the n-drift region 1. At this time, the reverse conduction voltage drop (VF) is low.
  • the second conduction path is through the front MOS source region, the n-type channel region, the n-drift region 1 and the n-buffer layer 6, and finally flows out from the back n+ cathode region 72.
  • the device is equivalent to an n-channel MOSFET structure. At this time, the device is in both PIN and MOSFET working modes. Since the injection of the front n-channel electron carriers suppresses the hole injection in the p-base region of the front diode, the conductivity modulation of the n-drift region is weakened, and the reverse conduction voltage drop (VF) of the device will increase.
  • the groove 33 can be used to reduce the electron hole concentration near it, thereby reducing the carrier injection efficiency, optimizing the reverse recovery performance of the RC-IGBT, and reducing the turn-off loss of the diode.
  • a base region 2 doped with a second conductive type is formed on the surface of a drift region 1 doped with a first conductive type, and the base region 2 includes an active region 21 and a virtual cell region 22 that are staggered; a plurality of trenches 3 are extended from the surface of the drift region 1 into the drift region 1 and are arranged in parallel, the trenches 3 penetrate the base region 2 and the bottom of the trenches is in contact with the drift region 1, an insulating dielectric layer 31 and a conductive material 32 surrounded by the insulating dielectric layer 31 are arranged in the trenches 3, and the conductive material 32 is led out from the first metal layer 5 on the top to form a gate electrode G; an emitter region 41 heavily doped with a first conductive type and a contact region 42 heavily doped with a second conductive type are formed on the surface of the active region 21 of the base region 2, a first side surface of the emitter region 41 is adjacent
  • the electron hole concentration nearby can be reduced, thereby reducing the carrier injection efficiency, optimizing the reverse recovery performance of the RC-IGBT, and reducing the turn-off loss of the diode.
  • the depth of the groove 33 is 0.8 ⁇ m ⁇ 0.1 ⁇ m.
  • a groove 33 is etched in the insulating dielectric layer 31 of the trench 3 in the virtual cell area 22.
  • the depth d of the groove 33 needs to be optimized and tested. If the depth d is too large, the stability and reliability of the device may be reduced. If d is too small, the regulating effect on carriers is not obvious.
  • the present disclosure simulates the design and analysis of the RC-IGBT under the conditions of a reverse breakdown voltage of 600V and a current of 5A, and finds that when the depth of the groove 33 is 0.8 ⁇ m ⁇ 0.1 ⁇ m, the carrier injection efficiency meets the design requirements, which can optimize the reverse recovery performance of the RC-IGBT and reduce the turn-off loss of the diode.
  • FIG 3 is a schematic diagram showing a reverse recovery waveform simulation of the reverse conducting insulated gate bipolar transistor shown in FIG1 ; and FIG4 is a scatter plot showing a balance relationship between the reverse breakdown voltage and the reverse recovery loss of the reverse conducting insulated gate bipolar transistor shown in FIG1 .
  • the solid line curve represents the RC-IGBT structure provided by the embodiment of the present disclosure
  • the dashed line curve represents the RC-IGBT structure of the related art. It can be seen that under the same conditions, the turn-off charge of the RC-IGBT structure of the embodiment of the present disclosure is lower than that of the RC-IGBT structure of the related art.
  • the circular points represent the RC-IGBT structure of the embodiment of the present disclosure
  • the square points represent the RC-IGBT structure of the related art.
  • the groove 33 is made by dry etching, and the etching gas can be any one of octafluorocyclopentene (C5F8), carbon tetrafluoride (CF4) and trifluoromethane (CHF3).
  • the high selectivity of the etching gas to SiO2 /Si helps to form the groove 33.
  • the etching performance such as etching rate, SiO2 /Si selectivity and etching profile control, it should be ensured that the high selectivity gas to SiO2 /Si does not affect the IGBT area; when the diode undergoes reverse recovery, the groove 33 is used to improve the overall diode reverse recovery performance of the device and reduce the reverse recovery loss.
  • an oxide layer 50 is further formed between the first metal layer 5 and the tops of the plurality of trenches 3.
  • the oxide layer 50 may be provided with contact vias, so that the conductive material 32 of the trench 3 is connected to the first metal layer 5 through the contact vias to form a gate electrode G.
  • the oxide layer 50 also covers the emitter region 41 and the contact region 42, and the emitter region 41 and the contact region 42 are connected to the first metal layer 5 through the contact vias to form an emitter E.
  • the RC-IGBT further includes a carrier storage layer (CS) 30 between the drift region 1 and the base region 2, and the carrier storage layer 30 is adjacent to the side of the adjacent trench 3.
  • the function of the carrier storage layer 30 is to reduce the hole injection efficiency in the diode working state, and increase the emitter carrier concentration in the IGBT working state, thereby reducing the conduction voltage drop.
  • the embodiment of the present disclosure also provides a method for preparing the reverse conducting insulated gate bipolar transistor as described above, comprising the following steps S1 to S11:
  • Step S1 forming a drift region 1 doped with a first conductivity type
  • Step S2 forming a second conductive type doped layer on the upper surface of the drift region 1 by ion implantation and/or diffusion.
  • a mixed base region 2 the base region 2 includes an active region 21 and a virtual cell region 22 that are staggered;
  • Step S3 etching a plurality of trenches 3 arranged in parallel on the upper surface of the drift region 1, wherein the trenches 3 penetrate the base region 2 and the bottoms of the trenches 3 are in contact with the drift region 1;
  • Step S4 forming an insulating dielectric layer 31 on the inner wall of the trench 3, and filling the trench 3 with a conductive material 32;
  • Step S5 forming a groove 33 in the insulating dielectric layer 31 of the trench 3 located in the dummy cell area 22 by dry etching;
  • Step S6 forming an emitter region 41 heavily doped with the first conductivity type and a contact region 42 heavily doped with the second conductivity type on the upper surface of the active region 21 of the base region 2 by ion implantation and/or diffusion;
  • Step S7 depositing a first metal layer 5 on the surface of the emitter region 41 and the contact region 42, and leading the conductive material 32 from the top of the first metal layer 5 to form a gate electrode G, and the emitter region 41 and the contact region 42 are jointly led from the first metal layer 5 to form an emitter E;
  • Step S8 thinning the back side of the drift region 1 and forming a first conductive type doped buffer layer 6 by deep ion implantation and/or diffusion;
  • Step S9 shallowly implanting first conductive type ions on the surface of the buffer layer 6 to form a cathode region 72 heavily doped with the first conductive type;
  • Step S10 shallowly implanting the second conductive type ions on the surface of the buffer layer 6 to form a collector region 71 heavily doped with the second conductive type, wherein the collector region 71 and the cathode region 72 are alternately distributed;
  • Step S11 depositing a second metal layer 8 on the surfaces of the collector region 71 and the cathode region 72 , and the collector region 71 and the cathode region 72 are jointly led out from the second metal layer 8 to form a collector electrode C.
  • an oxide layer 50 is further formed on the top of the plurality of trenches 3.
  • the oxide layer 50 may be provided with contact vias, so that the conductive material 32 of the trench 3 is connected to the first metal layer 5 through the contact vias to form a gate electrode G.
  • the oxide layer 50 also covers the emitter region 41 and the contact region 42, and the emitter region 41 and the contact region 42 are connected to the first metal layer 5 through the contact vias to form an emitter E.
  • a carrier storage layer 30 doped with the first conductivity type is formed on the surface of the drift region 1 by deep ion implantation and/or diffusion, and the trench 3 penetrates the carrier storage layer 30.
  • the function of the carrier storage layer 30 is to reduce the hole injection efficiency in the diode working state, and increase the emitter carrier concentration in the IGBT working state, thereby reducing the conduction voltage drop.
  • the dry etching gas is any one of octafluorocyclopentene, carbon tetrafluoride and trifluoromethane.
  • the high selectivity of the etching gas to SiO 2 /Si helps to form the groove 33.
  • the etching performance such as etching rate, SiO 2 /Si selectivity and etching profile control, it should be ensured that the high selectivity of SiO 2 /Si gas does not affect the IGBT.
  • the groove 33 is used to enhance the overall diode reverse recovery performance of the device and reduce reverse recovery losses.
  • the RC-IGBT device of the embodiment of the present disclosure does not require an additional photolithography plate compared to the RC-IGBT device of the related art, that is, the manufacturing cost is not increased.
  • the groove 33 can be formed by etching the insulating dielectric layer 31 of the groove 3 in the virtual cell area 22 without significantly increasing the process and cost, thereby reducing the concentration of electron holes in the vicinity, thereby reducing the carrier injection efficiency, optimizing the reverse recovery performance of the RC-IGBT, and reducing the turn-off loss of the diode.

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Abstract

一种逆导型绝缘栅双极晶体管及其制备方法，该逆导型绝缘栅双极晶体管包括：第一导电类型掺杂的漂移区（1）、第二导电类型掺杂的基区（2）、从漂移区（1）的表面延伸入漂移区（1）且平行排列的多个沟槽（3），沟槽（3）贯穿基区（2）且底部与漂移区（1）接触，沟槽（3）内设置有绝缘介质层（31）和由绝缘介质层（31）包围的导电材料（32）；基区（2）包括交错分布的有源区（21）和虚拟元胞区（22）；由有源区（21）对应的发射区（41）、接触区（42）及其毗连的基区（2）、漂移区（1）和集电区（71）组成IGBT单元；虚拟元胞区（22）对应的基区（2）及其毗连的接触区（42）、漂移区（1）和阴极区（72）组成反向恢复晶体管单元；其中，位于虚拟元胞区（22）内的沟槽（3）的绝缘介质层（31）设置有凹槽（33）。在不显著增加工艺和成本的基础上，优化RC-IGBT的反向恢复性能，降低二极管的关断损耗。

Description

逆导型绝缘栅双极晶体管及其制备方法
交叉引用
本公开引用于2023年2月13日提交的专利名称为“逆导型绝缘栅双极晶体管及其制备方法”的第202310116479.4号中国专利申请，其通过引用被全部并入本公开。
技术领域
本公开涉及半导体技术领域，尤其涉及一种逆导型绝缘栅双极晶体管及其制备方法。
背景技术
绝缘栅双极晶体管(Insulated gate bipolar transistor，简称IGBT)是电子系统中的关键半导体元件，被广泛应用于各种中高压功率控制系统中，如马达驱动、电能转换等。IGBT器件包含三个电极：集电极、发射极以及用于控制器件开关的栅极。相关技术的IGBT在栅极关断时等效为一个基区开路的PNP型三极管，因此不具备反向续流能力，导致相关技术的IGBT只能作为一个单向导通器件，即电流只能从集电极流向发射极。但是多数功率电路系统都有电流双向导通的需求，因此，近年来一种新型的逆导型绝缘栅双极晶体管(Reverse-Conducting IGBT，简称RC-IGBT)结构被提出。
与相关技术的IGBT相比，RC-IGBT将反向并联二极管与相关技术的IGBT集成于同一块芯片上，使得RC-IGBT的电流既可以由集电极流向发射极，亦可由发射极流向集电极，以取代相关技术IGBT反并联分离式的续流二极管器件，节省总芯片面积约1/3，可大幅降低芯片生产制造成本及封装测试成本。同时这种集成二极管结构可以降低二极管的热阻，并较大幅度提高其抗浪涌电流，同时可显著降低芯片结温波动大的缺点，提高器件的功率循环能力。
但是，由于二极管与IGBT集成在同一颗芯片之中，RC-IGBT存在二极管的反向恢复性能较差的问题。如果采用载流子寿命控制技术提高二极管的反向恢复速度、降低反向恢复损耗，会对IGBT工作模式下的性能和可靠性产生不利影响。
发明内容
本公开的目的在于提供一种逆导型绝缘栅双极晶体管及其制备方法，其可以在不显著增加工艺和成本的基础上，优化RC-IGBT的反向恢复性能，降低二极管的关断损耗。
第一方面，本公开实施例提供了一种逆导型绝缘栅双极晶体管，包括：第一导电类型掺杂的漂移区；在漂移区的表面形成有第二导电类型掺杂的基区，基区包括交错分布的有源区和虚拟元胞区；从漂移区的表面延伸入漂移区且平行排列的多个沟槽，沟槽贯穿基区且底部与漂移区接触，沟槽内设置有绝缘介质层和由绝缘介质层包围的导电材料，导电材料从顶部的第一金属层引出形成栅电极；在基区的有源区的表面形成有第一导电类型重度掺杂的发射区和第二导电类型重度掺杂的接触区，发射区的第一侧面与对应的沟槽的侧面毗连，发射区的第二侧面与接触区毗连，发射区和接触区共同从第一金属层引出形成发射极；在漂移区的背面形成有第一导电类型掺杂的缓冲层；在缓冲层的表面形成有交错分布的第二导电类型重度掺杂的集电区和第一导电类型重度掺杂的阴极区，集电区和阴极区共同从第二金属层引出形成集电极；由有源区对应的发射区、接触区及其毗连的基区、漂移区和集电区组成IGBT单元；虚拟元胞区作为晶体管阳极区，由晶体管阳极区对应的基区及其毗连的接触区、漂移区和阴极区组成反向恢复晶体管单元；其中，位于虚拟元胞区内的沟槽的绝缘介质层设置有凹槽。
在一个示例性实施例中，凹槽的深度为0.8μm±0.1μm。
在一个示例性实施例中，第一金属层与多个沟槽的顶部之间还形成有氧化层。
在一个示例性实施例中，逆导型绝缘栅双极晶体管还包括位于漂移区与基区之间的载流子储存层，载流子储存层与相邻的沟槽的侧面毗连。
在一个示例性实施例中，绝缘介质层的材质为二氧化硅，导电材料的材质为多晶硅。
在一个示例性实施例中，第一导电类型和第二导电类型中的任一者为n型，第一导电类型和第二导电类型中的另一者为p型。
第二方面，本公开实施例提供了一种如前所述的逆导型绝缘栅双极晶体管的制备方法，包括：形成第一导电类型掺杂的漂移区；在漂移区的上表面通过离子注入和/或扩散的方式形成第二导电类型掺杂的基区，基区包括交错分布的有源区和虚拟元胞区；在漂移区的上表面刻蚀平行排列的多个沟槽，沟槽贯穿基区且底部与漂移区接触；在沟槽的内壁形成绝缘介质层，并在沟槽内填充导电材料；在位于虚拟元胞区内的沟槽的绝缘介质层通过干法刻蚀形成凹槽；在基区的有源区的上表面通过离子注入和/ 或扩散的方式形成第一导电类型重度掺杂的发射区和第二导电类型重度掺杂的接触区；在发射区和接触区的表面沉积第一金属层，导电材料从顶部的第一金属层引出形成栅电极，发射区和接触区共同从第一金属层引出形成发射极；在漂移区的背面进行减薄，并通过离子深层注入和/或扩散的方式形成第一导电类型掺杂的缓冲层；在缓冲层的表面进行第一导电类型离子浅层注入，形成第一导电类型重度掺杂的阴极区；在缓冲层的表面进行第二导电类型离子浅层注入，形成第二导电类型重度掺杂的集电区，且集电区与阴极区交错分布；在集电区与阴极区的表面沉积第二金属层，集电区和阴极区共同从第二金属层引出形成集电极。
在一个示例性实施例中，在沉积第一金属层之前，制备方法还包括在多个沟槽的顶部形成的氧化层。
在一个示例性实施例中，在形成基区之前，制备方法还包括在漂移区的表面通过离子深层注入和/或扩散的方式形成第一导电类型掺杂的载流子储存层，且沟槽贯穿载流子储存层。
在一个示例性实施例中，干法刻蚀的气体为八氟环戊烯、四氟化碳和三氟甲烷中的任一者。
根据本公开实施例提供的逆导型绝缘栅双极晶体管及其制备方法，在第一导电类型掺杂的漂移区的表面形成有第二导电类型掺杂的基区，基区包括交错分布的有源区和虚拟元胞区；从漂移区的表面延伸入漂移区且平行排列的多个沟槽，沟槽贯穿基区且底部与漂移区接触，沟槽内设置有绝缘介质层和由绝缘介质层包围的导电材料，导电材料从顶部的第一金属层引出形成栅电极；在基区的有源区的表面形成有第一导电类型重度掺杂的发射区和第二导电类型重度掺杂的接触区，发射区的第一侧面与对应的沟槽的侧面毗连，发射区的第二侧面与接触区毗连，发射区和接触区共同从第一金属层引出形成发射极；在漂移区的背面形成有第一导电类型掺杂的缓冲层；在缓冲层的表面形成有交错分布的第二导电类型重度掺杂的集电区和第一导电类型重度掺杂的阴极区，集电区和阴极区共同从第二金属层引出形成集电极；由有源区对应的接触区、发射区及其毗连的沟槽、基区、漂移区和集电区组成IGBT单元；虚拟元胞区作为晶体管阳极区，由晶体管阳极区对应的沟槽、基区、漂移区和阴极区组成反向恢复晶体管单元；其中，位于虚拟元胞区内的沟槽的绝缘介质层设置有凹槽。由此，在不显著 增加工艺和成本的基础上，通过在虚拟元胞区内的沟槽的绝缘介质层刻蚀形成凹槽，可以减小附近的电子空穴浓度，从而降低载流子注入效率，优化RC-IGBT的反向恢复性能，降低二极管的关断损耗。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。另外，在附图中，相同的部件使用相同的附图标记，且附图并未按照实际的比例绘制。
图1示出本公开实施例提供的逆导型绝缘栅双极晶体管的结构示意图；
图2示出图1所示的逆导型绝缘栅双极晶体管的虚拟元胞区的局部放大结构示意图；
图3示出图1所示的逆导型绝缘栅双极晶体管的反向恢复波形仿真示意图；
图4示出图1所示的逆导型绝缘栅双极晶体管的反向击穿电压与反向恢复损耗之间的平衡关系散点图。
附图标记说明：
1、漂移区；2、基区；21、有源区；22、虚拟元胞区；3、沟槽；30、载流子储存
层；31、绝缘介质层；32、导电材料；33、凹槽；41、发射区；42、接触区；5、第一金属层；50、氧化层；6、缓冲层；71、集电区；72、阴极区；8、第二金属层；G、栅电极；E、发射极；C、集电极。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
图1示出本公开实施例提供的逆导型绝缘栅双极晶体管的结构示意图，图2示出图1所示的逆导型绝缘栅双极晶体管的虚拟元胞区的局部放大结构示意图。
如图1和图2所示，本公开实施例提供的逆导型绝缘栅双极晶体管(以下简称RC-IGBT)包括：
第一导电类型掺杂的漂移区1；
在漂移区1的表面形成有第二导电类型掺杂的基区2，基区2包括交错分布的有源区21和虚拟元胞区(Dummy)22；
从漂移区1的表面延伸入漂移区1且平行排列的多个沟槽3，沟槽3贯穿基区2且底部与漂移区1接触，沟槽3内设置有绝缘介质层31和由绝缘介质层31包围的导电材料32，导电材料32从顶部的第一金属层5引出形成栅电极G；
在基区2的有源区21的表面形成有第一导电类型重度掺杂的发射区41和第二导电类型重度掺杂的接触区42，发射区41的第一侧面与对应的沟槽3的侧面毗连，发射区41的第二侧面与接触区42毗连，发射区41和接触区42共同从第一金属层5引出形成发射极E；
在漂移区1的背面形成有第一导电类型掺杂的缓冲层6；
在缓冲层6的表面形成有交错分布的第二导电类型重度掺杂的集电区71和第一导电类型重度掺杂的阴极区72，集电区71和阴极区72共同从第二金属层8引出形成集电极C；
由有源区21对应的发射区41、接触区42及其毗连的基区2、漂移区1和集电区71组成IGBT单元；
虚拟元胞区22作为晶体管阳极区，由晶体管阳极区对应的基区2及其毗连的接触区42、漂移区1和阴极区72组成反向恢复晶体管单元；
其中，位于虚拟元胞区22内的沟槽3的绝缘介质层31设置有凹槽33。
需要指出的是，本公开实施例中，第一导电类型和第二导电类型中的任一者为n型，第一导电类型和第二导电类型中的另一者为p型。器件的半导体衬底被认为由硅(Si)材料构成。但是，该衬底亦可由其他任何适合制造RC-IGBT的材料构成，如锗(Ge)，碳化硅(SiC)等。在以下说明中，器件的绝缘介质层的材料可以由氧化硅(SiOx)构成，但其他电介质材料亦可被采用，如氮化硅(SixNy)、氧化铝(AlxOy)及氮氧化硅(SixNyOz)等。在以下说明中，一个p型导电的半导体区可以通过向原始半导体区掺入一种或几种杂质构成，这些杂质可以是但并不局限于：硼(B)、铝(Al)、镓(Ga)等。一个n型导电的半导体区亦可通过向原始半导体区掺入一种或几种杂质构成，这些杂质可以是但并不局限于：磷(P)、砷(As)、碲(Sb)、硒(Se)、质子(H+)等。在以下说明中，重度掺杂的p型导电的半导体区被标记为p+区，重度 掺杂的n型导电的半导体区被标记为n+区。例如，在硅材料衬底中，若无特别指出，一个重度掺杂的区域的杂质浓度一般在1×1019cm-3至1×1021cm-3之间。在以下说明中，轻度掺杂的p型导电的半导体区被标记为p-区，轻度掺杂的n型导电的半导体区被标记为n-区。例如，在硅材料衬底中，若无特别指出，一个轻度掺杂的区域的杂质浓度一般在1×1012cm-3至1×1015cm-3之间。
此外，以下实施例将采用n型MOS沟道的RC-IGBT器件予以说明，其中，第一导电类型为n型，第二导电类型为p型。但需要指出的是，本公开同样适用于p型MOS沟道的RC-IGBT器件。
如图1所示，漂移区1由n-轻度掺杂而得，基区2是在漂移区1的基础上进行p型掺杂而得。发射区41由n+重度掺杂而得，接触区42由p+重度掺杂而得。缓冲层6由n-轻度掺杂而得。集电区71由p+重度掺杂而得，阴极区72由n+重度掺杂而得。可选地，绝缘介质层31的材质为二氧化硅SiO2，导电材料32的材质为多晶硅Si。
从漂移区1的表面延伸入漂移区1且平行排列的多个沟槽3，例如图1所示的4个沟槽3，沟槽3贯穿基区2且底部与漂移区1接触，沟槽3内设置有绝缘介质层31和由绝缘介质层31包围的导电材料32，导电材料32从顶部的第一金属层5引出形成栅电极G。另外，有源区21与虚拟元胞区22沿器件的横向方向交替分布，部分沟槽3位于有源区21，例如图1所示的2个沟槽3位于有源区21；部分沟槽3位于虚拟元胞区22，例如图1所示的2个沟槽3位于虚拟元胞区22。
如图2所示，虚拟元胞区22与有源区21的工艺参数一致，只是内部不含n+重度掺杂区域，也无发射区引出，其可以作为反向二极管通路的阳极。虚拟元胞区22的作用主要是减小沟槽栅IGBT的电流增益，降低IGBT短路电流幅值，屏蔽二极管的尖峰电场，提高短路可靠性。进一步地，在虚拟元胞区22内的沟槽3的绝缘介质层31中刻蚀有凹槽33，而有源区21内的沟槽3的绝缘介质层31中并未刻蚀凹槽33。
本公开实施例中的RC-IGBT器件的工作原理如下：RC-IGBT器件有三个电极：位于顶部的发射极E，位于底部的集电极C以及栅电极G。其中，栅电极G、绝缘介质层31、p基区2、n+型发射区41、p+接触区42及n-漂移区1共同构成了一个金属-氧化物-半导体(下文中称为“MOS”)结构。此外，p基区2、n-漂移区1及背面的p+集电区71共同构成了一个PNP型双极性晶体管。MOS结构与PNP管共同构成了一个IGBT结构，从而可以利用MOS结构控制PNP管的电流从集电极C流向发射极E，称为RC-IGBT电流的正向导通。另一方面，p+接触区42、p基区2、n-漂移区1及背面的n+阴极区72共同构成了一个P-I-N二极管(即反向恢复晶体管单元)，其中p+接触区42和p基区2作为P-I-N二极管的阳极，n+阴极区72作为P-I-N二极管的阴极。当RC-IGBT器件的发射极E的电压高过集电极C的电压预设值时，P-I-N二 极管可以导通，继而实现电流由发射极E流向集电极C，称为RC-IGBT电流的逆向导通。
当RC-IGBT器件处于反向导通状态时，存在两条导电路径：第一条导电路径为从正面p基区2到n-漂移区1，然后经过n-缓冲层6，最后从背面n+阴极区72流出，器件等效为PIN二极管结构，n-漂移区1内由正面注入的空穴和背面注入的电子进行电导调制，此时反向导通压降(VF)较低；第二条导电路径为经过正面MOS源区、n型沟道区、n-漂移区1及n-缓冲层6，最后从背面n+阴极区72流出，器件等效为n沟道MOSFET结构，此时器件同时处于PIN和MOSFET工作模式，由于正面n沟道电子载流子的注入抑制了正面二极管p基区的空穴注入，n-漂移区的电导调制被削弱，器件的反向导通压降(VF)会升高。
由此，在虚拟元胞区22内的沟槽3的绝缘介质层31刻蚀形成凹槽33后，当二极管经历反向恢复时，利用该凹槽33可以减小其附近的电子空穴浓度，从而降低载流子注入效率，优化RC-IGBT的反向恢复性能，降低二极管的关断损耗。
根据本公开实施例提供的逆导型绝缘栅双极晶体管，在第一导电类型掺杂的漂移区1的表面形成有第二导电类型掺杂的基区2，基区2包括交错分布的有源区21和虚拟元胞区22；从漂移区1的表面延伸入漂移区1且平行排列的多个沟槽3，沟槽3贯穿基区2且底部与漂移区1接触，沟槽3内设置有绝缘介质层31和由绝缘介质层31包围的导电材料32，导电材料32从顶部的第一金属层5引出形成栅电极G；在基区2的有源区21的表面形成有第一导电类型重度掺杂的发射区41和第二导电类型重度掺杂的接触区42，发射区41的第一侧面与对应的沟槽3的侧面毗连，发射区41的第二侧面与接触区42毗连，发射区41和接触区42共同从第一金属层5引出形成发射极E；在漂移区1的背面形成有第一导电类型掺杂的缓冲层6；在缓冲层6的表面形成有交错分布的第二导电类型重度掺杂的集电区71和第一导电类型重度掺杂的阴极区72，集电区71和阴极区72共同从第二金属层8引出形成集电极C；由有源区21对应的接触区42、发射区41及其毗连的沟槽3、基区2、漂移区1和集电区71组成IGBT单元；虚拟元胞区22作为晶体管阳极区，由晶体管阳极区对应的沟槽3、基区2、漂移区1和阴极区72组成反向恢复晶体管单元；其中，位于虚拟元胞区22内的沟槽3的绝缘介质层31设置有凹槽33。由此，在不显著增加工艺和成本的基础上，通过在虚拟元胞区22内的沟槽3的绝缘介质层31刻蚀形成凹槽33，可以减小附近的电子空穴浓度，从而降低载流子注入效率，优化RC-IGBT的反向恢复性能，降低二极管的关断损耗。
在一些实施例中，凹槽33的深度为0.8μm±0.1μm。
如图2所示，虚拟元胞区22内的沟槽3的绝缘介质层31中刻蚀有凹槽33，凹槽33的深度d需要进行优化测试，深度d太大容易造成器件稳定性和可靠性下降，深度 d太小对载流子的调节效果不明显。
本公开在反向击穿电压为600V、电流为5A的条件下对RC-IGBT进行仿真设计分析，得出凹槽33的深度为0.8μm±0.1μm时，载流子的注入效率满足设计要求，可以优化RC-IGBT的反向恢复性能，降低二极管的关断损耗。
图3示出图1所示的逆导型绝缘栅双极晶体管的反向恢复波形仿真示意图；图4示出图1所示的逆导型绝缘栅双极晶体管的反向击穿电压与反向恢复损耗之间的平衡关系散点图。
如图3所示，实线曲线代表本公开实施例提供的RC-IGBT结构，虚线曲线代表相关技术的RC-IGBT结构，可以看出，在相同条件下，本公开实施例的RC-IGBT结构的关断电荷比相关技术的RC-IGBT结构低。如图4所示，圆形点代表本公开实施例的RC-IGBT结构，方形点代表相关技术的RC-IGBT结构，可以看出，尽管本公开实施例的RC-IGBT结构与相关技术的RC-IGBT相比，其反向击穿电压VF会略微升高0.2V，但是本公开实施例的RC-IGBT结构的反向恢复损耗Err比相关技术的RC-IGBT结构降低了32％。
另外，凹槽33通过干法刻蚀制作而成，刻蚀气体可以为八氟环戊烯(C5F8)、四氟化碳(CF4)和三氟甲烷(CHF3)中的任一者。刻蚀气体对SiO2/Si的高选择性有助于形成凹槽33，为了优化刻蚀性能，如蚀刻速率、SiO2/Si选择性和刻蚀轮廓控制，应保证SiO2/Si的高选择性气体不会影响IGBT区域；在二极管经历反向恢复时，利用该凹槽33提升器件整体的二极管反向恢复性能，降低反向恢复损耗。
在一些实施例中，第一金属层5与多个沟槽3的顶部之间还形成有氧化层50。氧化层50可以设置有接触过孔，以使沟槽3的导电材料32通过接触过孔与第一金属层5连接形成栅电极G。另外，氧化层50还覆盖发射区41和接触区42，发射区41和接触区42通过接触过孔与第一金属层5连接形成发射极E。
在一些实施例中，RC-IGBT还包括位于漂移区1与基区2之间的载流子储存层(CS)30，载流子储存层30与相邻的沟槽3的侧面毗连。载流子储存层30的作用是为了减小在二极管工作状态下的空穴注入效率，同时增加在IGBT工作状态下的发射极载流子浓度，从而减小导通压降。
另外，本公开实施例还提供一种如前所述的逆导型绝缘栅双极晶体管的制备方法，包括如下步骤S1～S11：
步骤S1：形成第一导电类型掺杂的漂移区1；
步骤S2：在漂移区1的上表面通过离子注入和/或扩散的方式形成第二导电类型掺 杂的基区2，基区2包括交错分布的有源区21和虚拟元胞区22；
步骤S3：在漂移区1的上表面刻蚀平行排列的多个沟槽3，沟槽3贯穿基区2且底部与漂移区1接触；
步骤S4：在沟槽3的内壁形成绝缘介质层31，并在沟槽3内填充导电材料32；
步骤S5：在位于虚拟元胞区22内的沟槽3的绝缘介质层31通过干法刻蚀形成凹槽33；
步骤S6：在基区2的有源区21的上表面通过离子注入和/或扩散的方式形成第一导电类型重度掺杂的发射区41和第二导电类型重度掺杂的接触区42；
步骤S7：在发射区41和接触区42的表面沉积第一金属层5，导电材料32从顶部的第一金属层5引出形成栅电极G，发射区41和接触区42共同从第一金属层5引出形成发射极E；
步骤S8：在漂移区1的背面进行减薄，并通过离子深层注入和/或扩散的方式形成第一导电类型掺杂的缓冲层6；
步骤S9：在缓冲层6的表面进行第一导电类型离子浅层注入，形成第一导电类型重度掺杂的阴极区72；
步骤S10：在缓冲层6的表面进行第二导电类型离子浅层注入，形成第二导电类型重度掺杂的集电区71，且集电区71与阴极区72交错分布；
步骤S11：在集电区71与阴极区72的表面沉积第二金属层8，集电区71和阴极区72共同从第二金属层8引出形成集电极C。
在一些实施例中，在沉积第一金属层5之前，还包括在多个沟槽3的顶部形成的氧化层50。氧化层50可以设置有接触过孔，以使沟槽3的导电材料32通过接触过孔与第一金属层5连接形成栅电极G。另外，氧化层50还覆盖发射区41和接触区42，发射区41和接触区42通过接触过孔与第一金属层5连接形成发射极E。
在一些实施例中，在形成基区2之前，还包括在漂移区1的表面通过离子深层注入和/或扩散的方式形成第一导电类型掺杂的载流子储存层30，且沟槽3贯穿载流子储存层30。载流子储存层30的作用是为了减小在二极管工作状态下的空穴注入效率，同时增加在IGBT工作状态下的发射极载流子浓度，从而减小导通压降。
在一些实施例中，干法刻蚀的气体为八氟环戊烯、四氟化碳和三氟甲烷中的任一者。刻蚀气体对SiO2/Si的高选择性有助于形成凹槽33，为了优化刻蚀性能，如蚀刻速率、SiO2/Si选择性和刻蚀轮廓控制，应保证SiO2/Si的高选择性气体不会影响IGBT 区域；在二极管经历反向恢复时，利用该凹槽33提升器件整体的二极管反向恢复性能，降低反向恢复损耗。
需要指出的是，根据以上制备方法，本公开实施例的RC-IGBT器件相对于相关技术的RC-IGBT器件而言，并不需要额外的光刻版，即并不会增加制造成本。
根据本公开实施例提供的逆导型绝缘栅双极晶体管的制备方法，通过在位于虚拟元胞区22内的沟槽3的绝缘介质层31设置有凹槽33，可以在不显著增加工艺和成本的基础上，在虚拟元胞区22内的沟槽3的绝缘介质层31刻蚀形成凹槽33，减小了附近的电子空穴浓度，从而降低载流子注入效率，优化RC-IGBT的反向恢复性能，降低二极管的关断损耗。
应当指出，在说明书中提到的“一个实施例”、“实施例”、“示例性实施例”、“一些实施例”等表示所述的实施例可以包括特定特征、结构或特性，但未必每个实施例都包括该特定特征、结构或特性。此外，这样的短语未必是指同一实施例。此外，在结合实施例描述特定特征、结构或特性时，结合明确或未明确描述的其他实施例实现这样的特征、结构或特性处于本领域技术人员的知识范围之内。
应当容易地理解，应当按照最宽的方式解释本公开中的“在……上”、“在……以上”和“在……之上”，以使得“在……上”不仅意味着“直接处于某物上”，还包括“在某物上”且其间具有中间特征或层的含义，并且“在……以上”或者“在……之上”不仅包括“在某物以上”或“之上”的含义，还可以包括“在某物以上”或“之上”且其间没有中间特征或层(即，直接处于某物上)的含义。
需要说明的是，在本文中，诸如“第一”和“第二”等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (10)

  1. 一种逆导型绝缘栅双极晶体管，包括：
    第一导电类型掺杂的漂移区；
    在所述漂移区的表面形成有第二导电类型掺杂的基区，所述基区包括交错分布的有源区和虚拟元胞区；
    从所述漂移区的表面延伸入所述漂移区且平行排列的多个沟槽，所述沟槽贯穿所述基区且底部与所述漂移区接触，所述沟槽内设置有绝缘介质层和由所述绝缘介质层包围的导电材料，所述导电材料从顶部的第一金属层引出形成栅电极；
    在所述基区的所述有源区的表面形成有第一导电类型重度掺杂的发射区和第二导电类型重度掺杂的接触区，所述发射区的第一侧面与对应的所述沟槽的侧面毗连，所述发射区的第二侧面与所述接触区毗连，所述发射区和所述接触区共同从所述第一金属层引出发射极；
    在所述漂移区的背面形成有第一导电类型掺杂的缓冲层；
    在所述缓冲层的表面形成有交错分布的第二导电类型重度掺杂的集电区和第一导电类型重度掺杂的阴极区，所述集电区和所述阴极区共同从第二金属层引出形成集电极；
    由所述有源区对应的所述发射区、所述接触区及其毗连的所述基区、所述漂移区和所述集电区组成IGBT单元；
    所述虚拟元胞区作为晶体管阳极区，由所述晶体管阳极区对应的所述基区及其毗连的所述接触区、所述漂移区和所述阴极区组成反向恢复晶体管单元；
    其中，位于所述虚拟元胞区内的所述沟槽的所述绝缘介质层设置有凹槽。
  2. 根据权利要求1所述的逆导型绝缘栅双极晶体管，其中，所述凹槽的深度为0.8μm±0.1μm。
  3. 根据权利要求1所述的逆导型绝缘栅双极晶体管，其中，所述第一金属层与所述多个沟槽的顶部之间还形成有氧化层。
  4. 根据权利要求1所述的逆导型绝缘栅双极晶体管，其中，还包括位于所述漂移区与所述基区之间的载流子储存层，所述载流子储存层与相邻的所述沟槽的侧面毗连。
  5. 根据权利要求1所述的逆导型绝缘栅双极晶体管，其中，所述绝缘介质层的材质为二氧化硅，所述导电材料的材质为多晶硅。
  6. 根据权利要求1所述的逆导型绝缘栅双极晶体管，其中，所述第一导电类型和所述第二导电类型中的任一者为n型，所述第一导电类型和所述第二导电类型中的另一者为p型。
  7. 一种如权利要求1至6任一项所述的逆导型绝缘栅双极晶体管的制备方法，其中，包括：
    形成第一导电类型掺杂的漂移区；
    在所述漂移区的上表面通过离子注入和/或扩散的方式形成第二导电类型掺杂的基区，所述基区包括交错分布的有源区和虚拟元胞区；
    在所述漂移区的上表面刻蚀平行排列的多个沟槽，所述沟槽贯穿所述基区且底部与所述漂移区接触；
    在所述沟槽的内壁形成绝缘介质层，并在所述沟槽内填充导电材料；
    在位于所述虚拟元胞区内的所述沟槽的所述绝缘介质层通过干法刻蚀形成凹槽；
    在所述基区的所述有源区的上表面通过离子注入和/或扩散的方式形成第一导电类型重度掺杂的发射区和第二导电类型重度掺杂的接触区；
    在所述发射区和所述接触区的表面沉积第一金属层，所述导电材料的顶部从所述第一金属层引出形成栅电极，所述发射区和所述接触区共同从所述第一金属层引出形成发射极；
    在所述漂移区的背面进行减薄，并通过离子深层注入和/或扩散的方式形成第一导电类型掺杂的缓冲层；
    在所述缓冲层的表面进行第一导电类型离子浅层注入，形成第一导电类型重度掺杂的阴极区；
    在所述缓冲层的表面进行第二导电类型离子浅层注入，形成第二导电类型重度掺杂的集电区，且所述集电区与所述阴极区交错分布；
    在所述集电区与所述阴极区的表面沉积第二金属层，所述集电区和所述阴极区共同从所述第二金属层引出形成集电极。
  8. 根据权利要求7所述的制备方法，其中，在沉积所述第一金属层之前，还包括在所述多个沟槽的顶部形成的氧化层。
  9. 根据权利要求7所述的制备方法，其中，在形成所述基区之前，还包括在所述 漂移区的表面通过离子深层注入和/或扩散的方式形成第一导电类型掺杂的载流子储存层，且所述沟槽贯穿所述载流子储存层。
  10. 根据权利要求7所述的制备方法，其中，所述干法刻蚀的气体为八氟环戊烯、四氟化碳和三氟甲烷中的任一者。
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