WO2024183494A1 - 数据读取方法、装置、设备及可读存储介质 - Google Patents

数据读取方法、装置、设备及可读存储介质 Download PDF

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Publication number
WO2024183494A1
WO2024183494A1 PCT/CN2024/073958 CN2024073958W WO2024183494A1 WO 2024183494 A1 WO2024183494 A1 WO 2024183494A1 CN 2024073958 W CN2024073958 W CN 2024073958W WO 2024183494 A1 WO2024183494 A1 WO 2024183494A1
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Prior art keywords
weight
request
attribute data
sub
read
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English (en)
French (fr)
Inventor
任子木
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Tencent Technology (Shenzhen) Co Ltd
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Tencent Technology (Shenzhen) Co Ltd
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Priority to EP24766217.4A priority Critical patent/EP4586256A4/en
Publication of WO2024183494A1 publication Critical patent/WO2024183494A1/zh
Priority to US19/169,081 priority patent/US20250259687A1/en
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8046—Systolic arrays
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Definitions

  • the embodiments of the present application relate to the field of computer technology, and in particular to a data reading method, device, equipment and readable storage medium.
  • Peak computing power is an indicator in the field of computer technology to measure computer performance. Peak computing power refers to the maximum number of calculations that a processor can achieve per unit time, and the ability to read data from storage units is closely related to peak computing power.
  • a systolic array there is an array structure including multiple rows and columns of processing engines, which is called a systolic array.
  • Data in a storage unit can be read into the systolic array, and the data can be efficiently calculated by the systolic array.
  • the target data in the storage unit will be stored in a queue. If the condition that the data in the storage unit is read into the systolic array is met, the target data will be taken out of the queue and sent to the systolic array.
  • a chip can be used as a carrier for objects with data storage functions such as storage units and queues.
  • data storage functions such as storage units and queues.
  • queues require a certain amount of storage resources, which easily leads to a large chip area.
  • a data reading method, device, equipment and readable storage medium are provided.
  • a processor of an electronic device comprising a systolic array and a storage unit respectively connected to the processor, the systolic array comprising a weight attribute register, the method comprising:
  • first weight read request is used to request to read weight attribute data from a storage unit
  • first feature map read request is used to request to read feature map attribute data from the storage unit
  • the reference state identifier being used to represent a state of a weight attribute register in a systolic array after a preset running time from a current time, the weight attribute register being used to store the weight attribute data;
  • the feature map attribute data stored in the storage unit is read to the systolic array based on the first feature map read request, and the systolic array is used to perform calculations based on the weight attribute data and the feature map attribute data.
  • a storage system comprising a processing unit and a storage unit;
  • the storage unit is used to store weight attribute data and feature mapping attribute data
  • the processing unit is used to obtain a first weight read request and a first feature map read request, wherein the first weight read request is used to read weight attribute data from the storage unit, and the first feature map read request is used to request to read feature map attribute data from the storage unit;
  • the processing unit is further used to obtain a reference state identifier, the reference state identifier is used to represent the state of a weight attribute register in the systolic array after a preset running time from a current time, the weight attribute register is used to store the weight attribute data;
  • the processing unit is further configured to read the weight attribute data stored in the storage unit to the systolic array in response to the first weight read request when the reference state identifier satisfies a first preset condition;
  • the processing unit is further configured to read the feature mapping attribute data stored in the storage unit to the systolic array based on the first feature mapping read request when the reference state identifier satisfies a second preset condition, and the systolic array is configured to perform calculations based on the weight attribute data and the feature mapping attribute data.
  • a data reading device comprising:
  • An acquisition module used to acquire a first weight read request and a first feature map read request, wherein the first weight read request is used to request to read weight attribute data from a storage unit, and the first feature map read request is used to request to read feature map attribute data from the storage unit;
  • the acquisition module is further used to acquire a reference state identifier, wherein the reference state identifier is used to represent a state of a weight attribute register in the systolic array after a preset running time from a current time, wherein the weight attribute register is used to store the weight attribute data;
  • a reading module configured to read the weight attribute data stored in the storage unit into the systolic array in response to the first weight read request when the reference state identifier satisfies a first preset condition
  • the reading module is further used to read the feature mapping attribute data stored in the storage unit to the systolic array based on the first feature mapping read request when the reference state identifier meets the second preset condition, and the systolic array is used to perform calculations based on the weight attribute data and the feature mapping attribute data.
  • an electronic device comprising a processor and a memory, wherein the memory stores at least one computer-readable instruction, and the at least one computer-readable instruction is loaded and executed by the processor so that the electronic device implements any of the above-mentioned data reading methods.
  • a computer-readable storage medium in which at least one computer-readable instruction is stored.
  • the at least one computer-readable instruction is loaded and executed by a processor to enable an electronic device to implement any of the above-mentioned data reading methods.
  • a computer program product is also provided, wherein at least one computer-readable instruction is stored in the computer program product, and the at least one computer-readable instruction is loaded and executed by a processor to enable an electronic device to implement any of the above-mentioned data reading methods.
  • FIG1 is a schematic diagram of an implementation environment of a data reading method provided in an embodiment of the present application.
  • FIG2 is a schematic diagram of data loading of a systolic array provided in an embodiment of the present application.
  • FIG3 is a flow chart of a data reading method provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of updating a status indicator provided in an embodiment of the present application.
  • FIG5 is a schematic diagram of determining whether a sub-request is valid provided in an embodiment of the present application.
  • FIG6 is a schematic diagram of a data collection process provided in an embodiment of the present application.
  • FIG8 is a schematic diagram of the structure of an arbitration unit provided in an embodiment of the present application.
  • FIG9 is a schematic diagram of the structure of a data reading device provided in an embodiment of the present application.
  • FIG10 is a schematic diagram of the structure of a terminal device provided in an embodiment of the present application.
  • FIG11 is a schematic diagram of the structure of a server provided in an embodiment of the present application.
  • FIG. 12 is an architecture diagram of another storage system provided in an embodiment of the present application.
  • FIG1 is a schematic diagram of an implementation environment of a data reading method provided in an embodiment of the present application.
  • the implementation environment includes a terminal device 101 and a server 102.
  • the data reading method in the embodiment of the present application can be executed by the terminal device 101, or by the server 102, or by the terminal device 101 and the server 102 together.
  • the terminal device 101 can be a smart phone, a game console, a desktop computer, a tablet computer, a laptop computer, a smart TV, a smart car device, an intelligent voice interaction device, a smart home appliance, etc.
  • the server 102 can be a single server, or a server cluster consisting of multiple servers, or any one of a cloud computing platform and a virtualization center, which is not limited in the embodiments of the present application.
  • the server 102 can be connected to the terminal device 101 through a wired network or a wireless network.
  • the server 102 can have functions such as data processing, data storage, and data transmission and reception, which are not limited in the embodiments of the present application.
  • the number of terminal devices 101 and servers 102 is not limited and can be one or more.
  • Figure 2 is a schematic diagram of data loading of a systolic array provided in an embodiment of the present application.
  • a systolic array is an array structure whose working mode and process can be compared to the working mode and process of the human blood circulation system.
  • data flows rhythmically between the process engines (PE) of the systolic array in a set pipeline manner.
  • PE process engines
  • all the processing engines process the data flowing through them in parallel, so the systolic array can achieve a very high parallel processing speed.
  • the systolic array includes M rows and N columns of processing engines, where M and N are both positive integers greater than 1.
  • a beat register can be inserted between any two columns of processing engines in the systolic array, and/or a beat register can be inserted between any two rows of processing engines in the systolic array.
  • layout and wiring can be facilitated, which is conducive to physical implementation.
  • the beat register is a first-level beat register.
  • the systolic array shown in Figure 2 includes 8 rows and 8 columns of processing engines, and a beat register is inserted between every two columns of processing engines in the systolic array.
  • the electronic device may include a processor, a storage unit and a systolic array, and the electronic device includes a systolic array and a storage unit respectively connected to the processor, and the systolic array includes a weight attribute register.
  • the electronic device can read data from the storage unit and load the data into the systolic array.
  • the embodiment of the present application does not limit the storage unit.
  • the storage unit is any one of L1 storage (L1Memory), L2 storage, internal disk, etc.
  • the embodiments of the present application are applicable to the field of artificial intelligence technology.
  • the features of media information such as images, texts, and audio can be processed by neural network models for feature extraction, classification, and the like.
  • the essence of the neural network model processing the features of media information is to calculate the model parameters of the neural network model and the features of the media information.
  • the features of the media information belong to feature map (FM) attribute data
  • the model parameters of the neural network model belong to weight (WT) attribute data.
  • the data in the storage unit includes weight attribute data and feature map attribute data.
  • weight attribute data and feature map attribute data When the weight attribute data and feature map attribute data are loaded into the systolic array, the loading of the weight attribute data and the loading of the feature map attribute data have a certain timing relationship.
  • the electronic device can read the weight attribute data from the storage unit.
  • the read weight attribute data needs to be tapped by the triangularization array, and the horizontal data is converted into oblique triangular data and then input into the pulsating array. Since the tap register is inserted into the pulsating array, the weight attribute data needs to be tapped by the triangularization array.
  • the systolic array includes 8 rows and 8 columns of processing engines.
  • the electronic device can load the weight attribute data from the storage unit based on a read request for the weight attribute data.
  • the weight attribute data is input into the systolic array after passing through the triangulated array.
  • the weight attribute data is located in the processing engine of the first row of the first column of the systolic array.
  • the electronic device can load the weight attribute data from the storage unit based on a read request for the weight attribute data.
  • the weight attribute data is input into the systolic array after passing through the triangulated array.
  • the weight attribute data is located in the processing engines of the first row of the first column, the second row of the first column, and the first row of the second column of the systolic array.
  • the first The weight attribute data loaded in the clock cycle is located in the processing engine of the second row of the first column
  • the weight attribute data loaded in the second clock cycle is located in the processing engine of the first row of the first column and the first row of the second column.
  • the electronic device can load the weight attribute data from the storage unit based on the read request for the weight attribute data, and the weight attribute data is input into the systolic array after the triangulation array.
  • the weight attribute data is located in the processing engines of the first row of the first column to the third row, the first row of the second column to the second row, and the first row of the third column of the systolic array.
  • the weight attribute data loaded in the first clock cycle is located in the processing engine of the third row of the first column
  • the weight attribute data loaded in the second clock cycle is located in the processing engine of the second row of the first column and the second row of the second column
  • the weight attribute data loaded in the third clock cycle is located in the processing engine of the first row of the first column, the first row of the second column, and the first row of the third column. And so on.
  • the flow mode of the weight attribute data loaded in the first clock cycle is: from the processing engine of the first column and the first row to the processing engine of the first column and the second row, and then to the processing engine of the first column and the third row;
  • the flow mode of the weight attribute data loaded in the second clock cycle is: from the processing engine of the first column and the first row of the second column to the processing engine of the first column and the second row of the second column.
  • the weight attribute data is loaded into the processing engine of the first column and the first row in the first clock cycle
  • the weight attribute data is loaded into the processing engine of the first column and the first row in the second clock cycle
  • the weight attribute data is loaded into the processing engine of the first column and the first row in the second column
  • the weight attribute data is loaded into the processing engine of the first column and the first row in the third clock cycle.
  • each clock cycle loads a new row of weight attribute data to the systolic array, and the weight attribute data of this row has one more column than the weight attribute data of the previous clock cycle.
  • the weight attribute data loaded into the systolic array sinks one row, and at the same time, a new row of weight attribute data is loaded into the systolic array, and the weight attribute data in this row has one more column than the weight attribute data in the previous clock cycle. Therefore, after eight clock cycles, the weight attribute data is located in the processing engines of the first to eighth rows of the first column, the first to seventh rows of the second column, the first to sixth rows of the third column, the first to fifth rows of the fourth column, the first to fourth rows of the fifth column, the first to third rows of the sixth column, the first to second rows of the seventh column, and the first row of the eighth column, as shown in the gray processing engine in FIG2.
  • the systolic array includes M rows and N columns of processing engines, and a new row of weight attribute data is loaded into the systolic array in one clock cycle, and the row of weight attribute data has one more column than the weight attribute data in the previous clock cycle. Therefore, if a row of N weight attribute data is newly loaded into the systolic array in one clock cycle, a row of N weight attribute data is newly loaded into the systolic array in each clock cycle after the clock cycle. In other words, the weight attribute data newly loaded in one clock cycle is not greater than the number of processing engines in one row.
  • the electronic device can read the feature mapping attribute data from the storage unit.
  • the electronic device can load the feature mapping attribute data from the storage unit based on the read request for the feature mapping attribute data, and the feature mapping attribute data flows from the input side (such as the left side) of the systolic array into the processing engine in the first column of the systolic array, and the weight attribute data residing in the processing engine and the feature mapping attribute data flowing into the processing engine are calculated by each processing engine in the first column.
  • at least one of multiplication calculation and addition calculation is performed on the weight attribute data and the feature mapping attribute data by the processing engine.
  • a clock cycle ends and enters the next clock cycle of the clock cycle.
  • the next clock cycle of the clock cycle is the current clock cycle at the current time.
  • the electronic device can load the weight attribute data from the storage unit based on the read request for the weight attribute data.
  • the weight attribute data is input into the systolic array after the triangulation array.
  • the weight attribute data loaded into the systolic array sinks one row, and a new row of weight attribute data is loaded into the systolic array, so that all the processing engines in the first column of the systolic array and all the processing engines in the second column are loaded with weight attribute data.
  • the feature mapping attribute data loaded in the previous clock cycle flows into the processing engine in the second column of the systolic array, and the weight attribute data residing in the processing engine and the feature mapping attribute data flowing into the processing engine are calculated through each processing engine in the second column.
  • the electronic device can load the feature mapping attribute data from the storage unit based on the read request for the feature mapping attribute data, and the feature mapping attribute data flows from the input side (such as the left side) of the systolic array to the first column processing engine of the systolic array, and the weight attribute data residing in the processing engine and the feature mapping attribute data flowing into the processing engine are processed by each processing engine of the first column. And so on.
  • the weight attribute data loaded into the systolic array sinks one row, and the feature mapping attribute data loaded into the systolic array shifts one column to the right.
  • a new row of weight attribute data is loaded into the systolic array, and a new column of feature mapping attribute data is loaded into the systolic array.
  • the feature mapping attribute data flowing through each processing engine will participate in the calculation together with the weight attribute data flowing through the processing engine.
  • the weight attribute data flows out from the first output side of the systolic array (such as the side adjacent to the input side, specifically the lower side), and the feature mapping attribute data flows out from the second output side of the systolic array (such as the side opposite to the input side, specifically the right side).
  • the electronic device needs to load the weight attribute data in the storage unit into the first column processing engine of the systolic array before it can load the feature mapping attribute data in the storage unit into the first column processing engine of the systolic array, and the electronic device needs to go through at least one clock cycle to load the weight attribute data in the storage unit into the first column processing engine of the systolic array.
  • the electronic device can load the weight attribute data in the storage unit into the systolic array again.
  • the loading of weight attribute data and the loading of feature mapping attribute data have a certain timing relationship.
  • the feature mapping attribute data in the storage unit can be loaded into the systolic array, and only after the weight attribute data in the first column processing engine of the systolic array and the feature mapping attribute data flowing into the first column processing engine are calculated, the feature mapping attribute data in the storage unit can be loaded into the systolic array again, so the related art instantiates a queue in the storage unit.
  • the read data end (a port in the storage unit for inputting feature mapping attribute data or weight attribute data into the systolic array) does not have the condition of receiving data, that is, when the feature mapping attribute data or weight attribute data in the storage unit cannot be loaded into the systolic array
  • the data is read from the storage unit and stored in the queue.
  • the read data end has the condition of receiving data, that is, when the feature mapping attribute data or weight attribute data in the storage unit can be loaded into the systolic array
  • the data is taken out from the queue and sent to the systolic array through the read data end.
  • the depth of the queue needs to be greater than or equal to the read delay. For example, if the read delay is 10 clock cycles, the depth of the queue is at least 10, which can avoid data loss. As the amount of processed data increases, the read delay will also increase, so that the two queues need to occupy a large amount of storage resources, resulting in a large chip area.
  • the embodiment of the present application provides a data reading method, which can be applied in the above-mentioned implementation environment and can reduce the chip area.
  • the terminal device 101 or server 102 that executes the data reading method in the embodiment of the present application is referred to as an electronic device.
  • the method can be executed by an electronic device, specifically, it can be executed by a processor of the electronic device, and the electronic device also includes a systolic array and a storage unit respectively connected to the processor, and the systolic array includes a weight attribute register.
  • the method includes the following steps.
  • Step 301 obtaining a first weight read request and a first feature map read request, wherein the first weight read request is used to request to read weight attribute data from a storage unit, and the first feature map read request is used to request to read feature map attribute data from a storage unit.
  • the data reading method of the embodiment of the present application is applicable to the field of artificial intelligence technology, and in the field of artificial intelligence technology, the features of media information are often processed through neural network models.
  • the weight attribute data belongs to the model parameters of the neural network model, and specifically can be in the layer of the neural network model, characterizing the contribution of the variable corresponding to the weight attribute data to the calculation result of the layer.
  • the neural network model can be a feature extraction model for extracting features from media information, or the neural network model can also be a classification model for classifying media information.
  • the feature mapping attribute data belongs to the features of the media information.
  • the media information includes at least one of images, text, audio, etc., that is, the feature mapping attribute data belongs to at least one of image features, text features, or audio features.
  • the electronic device may obtain a first weight read (Weight Read, wt_rd) request in any clock cycle, and the first weight read request is used to read weight (Weight, wt) attribute data.
  • the electronic device may obtain a first feature map read (Feature Map Read, fm_rd) request in any clock cycle, and the first feature map read request is used to read feature map (Feature Map, fm) attribute data.
  • the embodiment of the present application does not limit the order of the first weighted read request and the first feature mapping read request. That is, the first weighted read request and the first feature mapping read request can be obtained at the same time, the first weighted read request can be obtained first, and then the first feature mapping read request can be obtained, or the first feature mapping read request can be obtained first and then the first weighted read request can be obtained.
  • Step 302 obtaining a reference state identifier, wherein the reference state identifier is used to represent the state of a weight attribute register in the systolic array after a preset running time from the current time, and the weight attribute register is used to store weight attribute data.
  • the electronic device has an arbiter unit, which coordinates the timing relationship between the weight attribute data and the feature mapping attribute data by maintaining a reference state register.
  • the reference state register can be recorded as a weight occupation (wt_occupy) register, and the reference state register is used to store the reference state identifier.
  • the reference state identifier can be recorded as wt_occupy.
  • the reference state identifier is used to characterize the state of the weight attribute register in the systolic array after a preset running time from the current time, and the weight attribute register is used to store the weight attribute data.
  • the preset running time in English, is pre-defined elapsed time, which can be a preset time calculated from a certain time point.
  • the preset running time is the time from the moment when the reference state identifier is judged to meet the first preset condition to the moment when the corresponding data enters the systolic array.
  • the time from the moment when the reference state identifier is judged to meet the first preset condition to the moment when the corresponding data enters the systolic array can be the same as the time from the moment when the reference state identifier is judged to meet the second preset condition to the moment when the corresponding data enters the systolic array. Since the clock frequency is regular, the preset running time can be pre-set.
  • Step 303 When the reference state flag satisfies a first preset condition, in response to a first weight read request, read the weight attribute data stored in the storage unit into the systolic array.
  • the state of the weight attribute register is: the weight attribute register is in a state of waiting to store weight attribute data, or the weight attribute register is in a state of storing weight attribute data.
  • the pulsating array operates regularly at a certain frequency, so it can be determined at the current time whether the weight attribute register in the pulsating array is in a state of waiting to store weight attribute data or a state of storing weight attribute data after the preset running time from the current time.
  • the weight attribute register if all the processing engines in the first column of the systolic array have weight attribute data, the weight attribute register is in a state where the weight attribute data has been stored; if all or some of the processing engines in the first column of the systolic array do not have weight attribute data, the weight attribute register is in a state where weight attribute data is waiting to be stored.
  • the weight attribute register is in a state where the weight attribute data has been stored; if the processing engine in the first column of the systolic array does not have unused weight attribute data, the weight attribute register is in a state where weight attribute data is to be stored. If the weight attribute data residing in any processing engine is calculated with the feature mapping attribute data flowing through the processing engine, the weight attribute data has been used; if the weight attribute data residing in any processing engine is not calculated with the feature mapping attribute data flowing through the processing engine, the weight attribute data has not been used.
  • the weight attribute register is in a state of waiting to store weight attribute data.
  • the weight attribute register is in a state of storing the weight attribute data; if all processing engines have used weight attribute data, the weight attribute register is in a state of waiting to store weight attribute data.
  • the reference state flag satisfies the first preset condition: the reference state flag indicates that the weight attribute register is in a state of waiting to store weight attribute data after a preset running time from the current time. state.
  • weight attribute register may cause the weight attribute register to be in a state where weight attribute data is to be stored.
  • the first possibility is that all or some of the processing engines in the first column of the systolic array have never received weight attribute data.
  • the second possibility is that all of the processing engines in the first column of the systolic array have received weight attribute data, but the weight attribute data in all or some of the processing engines have been calculated with the feature mapping attribute data flowing through the processing engines, so that the weight attribute data in the processing engines have been used.
  • the electronic device can load the weight attribute data in the storage unit to the systolic array.
  • the electronic device determines that the reference state identifier satisfies the first preset condition, so as to read the weight attribute data stored in the storage unit to the systolic array, so that all the processing engines in the first column of the systolic array have weight attribute data, and all or part of the processing engines have unused weight attribute data.
  • the reference state identifier represents that after the preset running time from the current time, the weight attribute register is in a state where the weight attribute data is stored, it means that all processing engines in the first column of the systolic array have weight attribute data, and all or part of the processing engines have unused weight attribute data. In this case, the electronic device cannot load the weight attribute data in the storage unit into the systolic array. Based on this principle, the electronic device determines that the reference state identifier does not meet the first preset condition. At this time, the electronic device will block the first weight read request.
  • Step 304 when the reference state identifier satisfies the second preset condition, in response to the first feature map read request, the feature map attribute data stored in the storage unit is read into the systolic array, and the systolic array is used to perform calculations based on the weight attribute data and the feature map attribute data.
  • step 304 may be performed after step 302. Based on the state of the weight attribute register after the preset running time, it can be determined whether the reference state flag meets the second preset condition, thereby determining whether the feature map attribute data can be loaded into the systolic array.
  • the calculation based on the weight attribute data and the feature mapping attribute data specifically includes: determining the relationship between the weight attribute data and the feature mapping attribute data according to the structure of the neural network model, and then organizing the weight attribute data and the feature mapping attribute data to participate in the calculation of the neural network model according to the relationship between the weight attribute data and the feature mapping attribute data, and obtaining a calculation result.
  • the calculation result can be an intermediate calculation result or a result finally output by the neural network model.
  • the relationship between the weight attribute data and the feature map attribute data can be that the weight attribute data and the feature map attribute data are respectively used as input data of a specific function in the neural network model, and the output data of the function is a calculation result obtained by calculating the weight attribute data and the feature map attribute data.
  • the relationship between the weight attribute data and the feature map attribute data can be a dot product multiplication relationship.
  • the reference state flag satisfies the second preset condition: the reference state flag indicates that the weight attribute register is in a state where all weight attribute data are stored after a preset running time from the current time.
  • the weight attribute register is in a state where the weight attribute data has been stored, indicating that all processing engines in the first column of the systolic array have weight attribute data, and all or part of the processing engines have unused weight attribute data, and the electronic device can load the feature mapping attribute data in the storage unit to the systolic array.
  • the electronic device determines that the reference state identifier satisfies the second preset condition, so as to read the feature mapping attribute data stored in the storage unit to the systolic array, so that all processing engines in the first column of the systolic array can calculate the weight attribute data residing in the processing engine and the feature mapping attribute data flowing through the processing engine.
  • the reference state identifier indicates that when the weight attribute register is in a state of waiting to store weight attribute data after a preset running time from the current time, it indicates that all or part of the processing engines in the first column of the systolic array are not There is weight attribute data, and/or the weight attribute data of all processing engines in the first column of the systolic array have been used. In this case, the electronic device cannot load the feature mapping attribute data in the storage unit into the systolic array. Based on this principle, the electronic device determines that the reference state identifier does not meet the second preset condition, and at this time, the electronic device will block the first feature mapping read request.
  • the weight attribute data can be directly read based on the first weight read request, and the first feature map read request can also be shielded.
  • the feature map attribute data can be directly read based on the first feature map read request, and the first weight read request can also be shielded.
  • steps 306 to 307 as shown below are also included (not shown in FIG. 3 ).
  • Step 306 obtaining a first state flag, the first state flag indicating whether the weight attribute register has stored the weight attribute data of a set number of clock cycles after a preset running time from the current time.
  • the reference state identifier can be arbitrated by an arbitration unit, and when the reference state identifier meets the first preset condition, the weight attribute data is read based on the first weight read request, or, when the reference state identifier does not meet the first preset condition, the first weight read request is shielded.
  • the arbitration unit can maintain a first state register, and store the first state identifier through the first state register.
  • the first state identifier is set to a third value
  • the first state identifier is set to a fourth value. It can be understood that the value of the first state identifier is the third value only within the set number of clock cycles, and the value in other clock cycles is the fourth value.
  • the first state identifier can be recorded as wt_last_beat.
  • the weight attribute register When the first state flag is set from the third value to the fourth value, it indicates that after the preset running time from the current time, the weight attribute register has stored the weight attribute data of the set number of clock cycles.
  • the first state flag When the first state flag is set from the fourth value to the third value, it indicates that after the preset running time from the current time, the weight attribute register starts to store the weight attribute data of the set number of clock cycles.
  • the embodiment of the present application does not limit the magnitude of the third value and the fourth value.
  • the third value is 1 and the fourth value is 0.
  • Step 307 in response to the first state identification representing that the weight attribute register has stored the weight attribute data of a set number of clock cycles after the preset running time from the current time, it is determined that the reference state identification represents that the weight attribute register is in a state of storing the weight attribute data after the preset running time from the current time.
  • the electronic device sets the reference state identifier from the first value to the second value.
  • the reference state identifier when the reference state identifier is the first value, it indicates that the weight attribute register is in a state of waiting to store the weight attribute data after the preset running time; when the reference state identifier is the second value, it indicates that the weight attribute register is in a state of storing the weight attribute data after the preset running time.
  • the embodiment of the present application does not limit the size of the first value and the second value. Exemplarily, the first value is 0 and the second value is 1.
  • Figure 4 is a schematic diagram of updating a state identifier provided in an embodiment of the present application.
  • the first state identifier is set from 1 (i.e., the third value) to 0 (i.e., the fourth value)
  • the reference state identifier is set from 0 (i.e., the first value) to 1 (i.e., the second value).
  • the method further includes steps 308 and 309 (not shown in FIG. 3 ).
  • steps 308 and 309 may be performed after step 307 .
  • Step 308 obtaining a second state flag, the second state flag indicating whether the weight attribute data in the weight attribute register is calculated with the feature mapping attribute data of the first clock cycle after a preset running time from the current time.
  • the arbitration unit After a feature map read request of any clock cycle passes through the arbitration unit, if the second preset condition is met, the feature map attribute data corresponding to the feature map read request is transmitted through the systolic array and the register in the buffer after a preset running time. The weight attribute data in the weight attribute register is used for calculation. Based on this, the arbitration unit can maintain a second state register, and the second state identifier is stored in the second state register.
  • the second state identifier is set to the fifth value
  • the second state identifier is set to the sixth value. It can be understood that the value of the second state identifier is the fifth value only in the first clock cycle, and the value in other clock cycles is the sixth value.
  • the second state identifier can be recorded as fm_update_first_beat.
  • the second state flag When the second state flag is set from the fifth value to the sixth value, it indicates that after the preset running time from the current time, the weight attribute data in the weight attribute register and the feature mapping attribute data of the first clock cycle have completed the calculation.
  • the second state flag When the second state flag is set from the sixth value to the fifth value, it indicates that the weight attribute data in the weight attribute register and the feature mapping attribute data of the first clock cycle have started to be calculated.
  • the embodiment of the present application does not limit the magnitude of the fifth value and the sixth value.
  • the fifth value is 1 and the sixth value is 0.
  • Step 309 when the second state identification represents that the weight attribute data in the weight attribute register and the feature mapping attribute data of the first clock cycle are calculated after the preset running time from the current time, it is determined that the reference state identification represents that the weight attribute register is in a state of waiting to store weight attribute data after the preset running time from the current time.
  • the electronic device sets the reference state flag from the second value to the first value.
  • the reference state flag is set from 1 (i.e., the second value) to 0 (i.e., the first value).
  • the initial value of the reference state identifier is the first value, indicating that after the preset running time from the current time, the weight attribute register is in a state of waiting to store weight attribute data.
  • the reference state identifier satisfies the first preset condition, so the weight attribute data stored in the storage unit can be read to the systolic array in response to the first weight read request. If the first feature mapping read request is obtained, the first feature mapping read request is shielded. This process will continue for several clock cycles until the reference state identifier is set from the first value to the second value.
  • the reference state identifier is the second value, it can be characterized that the weight attribute register is in a state where the weight attribute data is stored. In this case, the reference state identifier satisfies the second preset condition. Therefore, within one clock cycle, the feature mapping attribute data stored in the storage unit can be read to the pulsation array in response to the first feature mapping read request. If the first weight read request is obtained, the first weight read request is shielded. After the clock cycle, the reference state identifier is set from the second value to the first value. Next, implementation method A or implementation method B is executed.
  • the reference state identifier is a first value.
  • the weight attribute data stored in the storage unit can be read to the systolic array in response to the first weight read request, and the first feature map read request is shielded.
  • the reference state identifier is set from the first value to the second value.
  • the feature map attribute data stored in the storage unit can be read to the systolic array in response to the first feature map read request, and the first weight read request is shielded.
  • the reference state identifier is set from the second value to the first value. Repeat this process until the reading stops.
  • the reference state identifier is the first value.
  • step 310 to step 311 are executed (not shown in FIG3 ).
  • Step 310 to step 311 may be executed after step 304 or after “the reference state identifier is set from the second value to the first value”.
  • Step 310 obtaining a second weight read request and a second feature map read request, wherein the second weight read request is used to request to read weight attribute data from a storage unit, and the second feature map read request is used to request to read feature map attribute data from a storage unit.
  • the electronic device may also obtain a second weight read request in any clock cycle, and the second weight read request is used to read the wt attribute data.
  • the electronic device may also obtain a second feature map read request in any clock cycle, and the second feature map read request is used to read the fm attribute data.
  • the second feature mapping read request may be obtained first, and the second weighted read request may be obtained later.
  • the second feature mapping read request may also be obtained first, and the second weighted read request may be obtained later.
  • Step 311 based on the second weight read request, the weight attribute data stored in the storage unit is read into the systolic array, and based on the second feature map read request, the feature map attribute data stored in the storage unit is read into the systolic array, and the read delay of the weight attribute data and the read delay of the feature map attribute data are preset running times.
  • the read delay of the weight attribute data and the read delay of the feature mapping attribute data are both preset running times, that is to say, the read delay of the weight attribute data and the read delay of the feature mapping attribute data are equal. Therefore, every time a clock cycle of weight attribute data is loaded into the systolic array, correspondingly, a clock cycle of feature mapping attribute data will flow into the systolic array and be calculated with the weight attribute data residing in the systolic array, so that the timing relationship between the weight attribute data and the feature mapping attribute data is maintained.
  • the timing relationship between the weight attribute data and the feature mapping attribute data can be maintained when the read delay of the weight attribute data and the feature mapping attribute data are equal, there is no need to introduce a queue to store data, which reduces the storage resources required for the queue and helps reduce the chip area.
  • the first weighted read request includes at least one first weighted sub-request
  • the storage unit includes at least one first storage block.
  • the first weighted read request includes four first weighted sub-requests, which are respectively recorded as req0 to req3, and the storage unit includes four first storage blocks, which are respectively recorded as bg0 to bg3.
  • step 303 "reading the weight attribute data stored in the storage unit to the systolic array in response to the first weight read request” includes steps 3031 to 3032 as shown below (not shown in FIG. 3).
  • Step 3031 for any first weight sub-request, if any first weight sub-request is a valid request, determine the first storage block corresponding to any first weight sub-request, and read the weight attribute data corresponding to any first weight sub-request from the first storage block corresponding to any first weight sub-request.
  • the electronic device may directly determine any first weighted sub-request as a valid request, or may compare any first weighted sub-request with a reference first weighted sub-request to determine whether any first weighted sub-request is a valid request based on the comparison result.
  • "determining any first weight sub-request as a valid request” in step 3031 includes: extracting the address of the first storage block corresponding to any first weight sub-request from any first weight sub-request; in response to the address of the first storage block corresponding to any first weight sub-request being different from the address of the first storage block corresponding to the reference first weight sub-request, determining that any first weight sub-request is a valid request, and the reference first weight sub-request is at least one first weight sub-request among multiple first weight sub-requests other than any first weight sub-request.
  • Any first weighted sub-request includes an identification bit and an address (Address, Addr), wherein the identification bit is used to indicate that the first weighted sub-request is a valid request, and the address is a storage address where data corresponding to the first weighted sub-request is located.
  • any first weight sub-request includes the address of the first storage block to realize reading the weight attribute data corresponding to the first weight sub-request from the first storage block.
  • any first weight sub-request corresponds to an address of a first storage block
  • any two first weight sub-requests may correspond to the address of the same first storage block, or may correspond to addresses of different first storage blocks. Based on this, it is necessary to determine whether two first weight sub-requests correspond to the address of the same first storage block.
  • any first weight sub-request includes the address of the first storage block
  • the address of the corresponding first storage block can be extracted from the first weight sub-request.
  • the address of the first storage block corresponding to any first weight sub-request is compared with the address of the first storage block corresponding to the reference first weight sub-request. If the comparison result is that the two addresses are different, then any first weight sub-request is determined to be a valid request; if the comparison result is that the two addresses are the same, then any first weight sub-request is determined to be a valid request.
  • the first weighted sub-request is an invalid request.
  • the number of reference first weight sub-requests is at least one. In the case where there are at least two reference first weight sub-requests, if the address of the first storage block corresponding to any first weight sub-request is different from the address of the first storage block corresponding to each reference first weight sub-request, then any first weight sub-request is determined to be an invalid request; if the address of the first storage block corresponding to the reference first weight sub-request is the same as the address of the first storage block corresponding to any first weight sub-request, then any first weight sub-request is determined to be an invalid request.
  • each first weight sub-request other than any first weight sub-request among multiple first weight sub-requests may be used as a reference first weight sub-request, or each first weight sub-request before (or after) any first weight sub-request among multiple first weight sub-requests may be used as a reference first weight sub-request.
  • the first weighted read request includes four first weighted sub-requests, which are respectively denoted as sub-request 0 to sub-request 3.
  • the first weighted sub-request includes an identification bit used to characterize that the first weighted sub-request is valid and an address for storing data corresponding to the first weighted sub-request. All or part of the address included in any first weighted sub-request is the address of the first storage block.
  • Figure 5 shows that sub-requests 0 to 3 all include an identification bit and an address representing "valid", and part of the address is the address of the corresponding first storage block.
  • the electronic device may directly determine whether sub-request 0 is valid. For example, the electronic device directly determines that sub-request 0 is a valid request.
  • the electronic device may compare the address of the first storage block corresponding to sub-request 0 with the address of the first storage block corresponding to sub-request 1.
  • the flag bit of sub-request 1 indicates "valid”
  • the operation result is determined to be true when both operands are true.
  • the comparison result is different
  • the operand corresponding to the comparison result indicates that sub-request 1 is "valid”, which is equivalent to true.
  • the flag bit of sub-request 1 indicates that sub-request 1 is "valid”, which is equivalent to true. Therefore, the operation result is true, that is, the operation result is that sub-request 1 is "valid".
  • sub-request 2 For sub-request 2, based on a principle similar to that of sub-request 1, the address of the first storage block corresponding to sub-request 2 can be compared with the address of the first storage block corresponding to sub-requests 0 and 1.
  • the comparison result is different and the flag bit of sub-request 2 indicates "valid”
  • a logical AND operation is performed on the comparison result and the flag bit to obtain that sub-request 2 is valid.
  • the comparison result is the same and the flag bit of sub-request 2 indicates that sub-request 2 is "valid”
  • a logical AND operation is performed on the comparison result and the flag bit to obtain that sub-request 2 is invalid.
  • sub-request 3 For sub-request 3, based on a principle similar to that of sub-request 1, the address of the first storage block corresponding to sub-request 3 can be compared with the address of the first storage block corresponding to sub-requests 0, 1, and 2.
  • the comparison result is different and the flag bit of sub-request 3 indicates "valid”
  • a logical AND operation is performed between the comparison result and the flag bit to obtain that sub-request 3 is valid.
  • the comparison result is the same and the flag bit of sub-request 3 indicates that sub-request 3 is "valid”
  • a logical AND operation is performed between the comparison result and the flag bit to obtain that sub-request 3 is invalid.
  • the identification bit of the first weight sub-request when the identification bit of the first weight sub-request is the seventh value, the identification bit of the first weight sub-request is determined to represent "valid", and when the identification bit of the first weight sub-request is the eighth value, the identification bit of the first weight sub-request is determined to represent "invalid".
  • the embodiment of the present application does not limit the seventh value and the eighth value. In an exemplary embodiment, the seventh value is 1 and the eighth value is 0.
  • any first weight sub-request includes the address of the first storage block, based on the address of the first storage block included in any first weight sub-request, the first storage block corresponding to the first weight sub-request can be determined, and the data corresponding to the first weight sub-request can be read from the first storage block.
  • any first storage block includes at least one second storage block.
  • 0 includes the second storage block 0 and 1
  • the first storage block 1 includes the second storage block 0 and 1
  • the first storage block 2 includes the second storage block 0 and 1
  • the first storage block 3 includes the second storage block 0 and 1. Since the first storage block includes at least one second storage block, the second storage block can be recorded as a storage module (Bank), and the first storage block can be recorded as a storage module group (Bank Group).
  • step 3031 "reading weight attribute data corresponding to any first weight sub-request from the first storage block corresponding to any first weight sub-request” includes: determining the second storage block corresponding to any first weight sub-request based on any first weight sub-request; reading the weight attribute data corresponding to any first weight sub-request from the second storage block corresponding to any first weight sub-request.
  • any first weight sub-request includes the address of the first storage block, and the first storage block includes at least one second storage block, any first weight sub-request may include the address of the second storage block. Based on the address of the second storage block included in any first weight sub-request, the second storage block corresponding to the first weight sub-request may be determined, and the weight attribute data corresponding to the first weight sub-request may be read from the second storage block.
  • Step 3032 Send the weight attribute data corresponding to each first weight sub-request to the systolic array.
  • the electronic device needs to determine whether each first weight sub-request in the first weight read request is a valid request, and can only read the data corresponding to the first weight sub-request if the first weight sub-request is a valid request, there are differences in the reading completion time of the data corresponding to each first weight sub-request.
  • the data corresponding to each first weight sub-request can be collected by a collection unit. After the collection unit collects the data corresponding to each first weight sub-request, according to the export command (for example, the reg command), the data corresponding to each first weight sub-request is exported to the storage unit as the weight attribute data corresponding to the first weight read request, thereby sending the weight attribute data to the systolic array.
  • the first weighted read request includes four first weighted sub-requests, which are sub-requests 0 to 3.
  • the collection unit has not collected the data corresponding to any of the first weighted sub-requests, at time T1, the collection unit collects the data corresponding to sub-requests 0 and 1, at time T2, the collection unit collects the data corresponding to sub-requests 0 to 2, and at time T3, the collection unit collects the data corresponding to sub-requests 0 to 3.
  • the export command the data corresponding to sub-requests 0 to 3 are exported to the storage unit as the weight attribute data corresponding to the first weighted read request.
  • the first feature mapping read request includes at least one first feature mapping sub-request
  • the second weight read request includes at least one second weight sub-request
  • the second feature mapping read request includes at least one second feature mapping sub-request.
  • the method further includes steps 312 to 313 (not shown in FIG. 3 ).
  • Step 312 Get a write request.
  • the electronic device can obtain a write request at any clock cycle, and the write request is used to write weight attribute data or feature mapping attribute data into the storage unit.
  • the write request can be a data move write (Write, wr) request based on direct memory access (Direct Memory Access, DMA), which is used to move data in other storage to the storage unit. Therefore, the write request can be recorded as a dma_wr request.
  • Step 313 Write the corresponding weight attribute data or feature mapping attribute data into the storage unit based on the write request.
  • the write request includes at least one third sub-request, and the storage unit includes at least one first storage block.
  • the write request includes four third sub-requests, and the storage unit includes four first storage blocks.
  • step 313 includes: for any third sub-request, determining the first storage block corresponding to any third sub-request; and writing the data corresponding to any third sub-request into the first storage block corresponding to any third sub-request based on any third sub-request.
  • any third sub-request includes the address of the first storage block. Therefore, based on the address of the first storage block included in any third sub-request, the first storage block corresponding to the third sub-request can be determined, and the weight attribute data or feature mapping attribute data corresponding to the third sub-request can be written into the first storage block corresponding to the third sub-request.
  • any first storage block includes at least one second storage block.
  • "writing data corresponding to any third sub-request into the first storage block corresponding to any third sub-request based on any third sub-request” includes: determining the second storage block corresponding to any third sub-request based on any third sub-request; and writing the data corresponding to any third sub-request into the second storage block corresponding to any third sub-request.
  • any third sub-request may include the address of the second storage block. Based on the address of the second storage block included in any third sub-request, the second storage block corresponding to the third sub-request may be determined, and the data corresponding to the third sub-request may be written into the second storage block corresponding to the third sub-request.
  • the scheduler is a strict priority (SP) scheduler.
  • the feature mapping attribute data needs to be loaded into the systolic array first, so as to calculate the feature mapping attribute data flowing through the systolic array and the weight attribute data residing in the systolic array, and then the weight attribute data can be loaded into the systolic array again.
  • the priority of the (first or second) weight read request is lower than the priority of the (first or second) feature mapping read request, wherein the priority of the write request can be higher than the priority of the weight read request, or lower than the priority of the weight read request, and can be higher than the priority of the feature mapping read request, or lower than the priority of the feature mapping read request.
  • the priority of the feature mapping read request is higher than the priority of the weight read request
  • the priority of the weight read request is higher than the priority of the write request.
  • the scheduler coordinates the priorities of various requests so that data can be read and written in an orderly manner, achieving efficient switching between multiple requests and improving data processing efficiency.
  • the information including but not limited to user device information, user personal information, etc.
  • data including but not limited to data used for analysis, stored data, displayed data, etc.
  • signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards in the relevant regions.
  • the first data, second data, third data, etc. involved in this application are all obtained with full authorization.
  • the above method characterizes the state of the weight attribute register in the pulsation array through a reference state identifier.
  • the weight attribute data stored in the storage unit is read to the pulsation array in response to the first weight read request;
  • the reference state identifier satisfies the second preset condition
  • the feature mapping attribute data stored in the storage unit is read to the pulsation array in response to the first feature mapping read request.
  • the storage resources required for the reference state identifier are fewer. This method can be applied to chips. Since the fewer the storage resources, the smaller the chip area, the chip has the conditions to reduce the chip area.
  • Figure 7 is an architecture diagram of a storage system provided by an embodiment of the present application.
  • the storage system includes a conflict detection unit, a hash unit, at least one processing block and a collection unit, and any processing block includes an arbitration unit, at least one second storage block and a selection unit.
  • FIG7 does not show the storage unit and the first storage block.
  • a first storage block includes each second storage block in a processing block, that is, one processing block corresponds to a first storage block, and the storage unit includes each first storage block.
  • the storage unit includes the first storage block corresponding to processing block 0, the first storage block corresponding to processing block 1, the first storage block corresponding to processing block 2, and the first storage block corresponding to processing block 3.
  • the first storage block corresponding to processing block 0 includes the second storage blocks 0 and 1 in processing block 0; the first storage block corresponding to processing block 1 includes the second storage blocks 0 and 1 in processing block 1; the first storage block corresponding to processing block 2 includes the second storage blocks 0 and 1 in processing block 2; the first storage block corresponding to processing block 3 includes the second storage blocks 0 and 1 in processing block 3.
  • the electronic device can read the feature mapping attribute data from the storage unit based on the feature mapping read request, and can also read the weight attribute data from the storage unit based on the weight read request.
  • the processing method for the feature mapping read request in the embodiment of the present application is similar to the processing method for the weight read request. Therefore, the following is a processing method for the feature mapping read request. Request as an example to illustrate the processing method of the embodiment of the present application for the feature mapping read request.
  • the feature mapping read request (corresponding to the first feature mapping read request and the second feature mapping read request)
  • the feature mapping read request is subjected to conflict detection through the conflict detection unit, wherein the principle of conflict detection is shown in FIG5 .
  • the feature mapping read request includes sub-requests 0 to 3.
  • sub-request 0 is directly determined to be valid; for sub-request 1, when the address of the first storage block corresponding to sub-request 0 is different from the address of the first storage block corresponding to sub-request 1, sub-request 1 is determined to be valid, otherwise, sub-request 1 is determined to be invalid; for sub-request 2, when the address of the first storage block corresponding to sub-requests 0 and 1 is different from the address of the first storage block corresponding to sub-request 2, sub-request 2 is determined to be valid, otherwise, sub-request 2 is determined to be invalid; for sub-request 3, when the address of the first storage block corresponding to sub-requests 0 to 2 is different from the address of the first storage block corresponding to sub-request 3, sub-request 3 is determined to be valid, otherwise, sub-request 3 is determined to be invalid.
  • each sub-request included in the feature mapping read request is valid. For any sub-request, if the sub-request is valid, the hash unit is used to determine the first storage block corresponding to the sub-request based on the address of the first storage block corresponding to the sub-request, and the request path of the processing block where the first storage block corresponding to the sub-request is located is set to be valid, so that the sub-request can reach the corresponding first storage block; if the sub-request is invalid, the hash unit is used to set the request path of the processing block where the first storage block corresponding to the sub-request is located to be invalid, so as to prevent the sub-request from reaching the corresponding first storage block.
  • sub-request 0 corresponds to the first storage block 0, and processing block 0 includes the first storage block 0. If sub-request 0 is valid, the request path of processing block 0 is set to valid through the hash unit, so that sub-request 0 can reach the first storage block 0; if sub-request 0 is invalid, the request path of processing block 0 is set to invalid through the hash unit, so as to prevent sub-request 0 from reaching the first storage block 0.
  • the storage system includes at least one processing block, one processing block includes an arbitration unit, a first storage block (not shown in the figure) and a selection unit, and the first storage block includes at least one second storage block.
  • the structural diagram of the arbitration unit can be seen in Figure 8.
  • the sub-request is first arbitrated by the arbitration unit.
  • the arbitration unit is configured with an update logic of the reference state identifier, and the update logic is shown in FIG4 .
  • the initial values of the reference state identifier, the first state identifier, and the second state identifier are all 0.
  • the electronic device can read the weight attribute data from the storage unit, and load it into the weight attribute register of the systolic array after the preset running time. If the weight attribute register is in a state to be stored with the weight attribute data after the preset running time, then in the second clock cycle, the electronic device can also read the weight attribute data from the storage unit, and load it into the weight attribute register of the systolic array after the preset running time. This loading method will continue for several clock cycles until the weight attribute register is in a state where the weight attribute data has been stored after the preset running time.
  • the clock cycle at this time can be recorded as the set number of clock cycles. That is to say, in the set number of clock cycles, the electronic device reads the weight attribute data from the storage unit, and loads it into the weight attribute register of the systolic array after the preset running time. At this time, the weight attribute register is in a state where the weight attribute data has been stored.
  • the first state flag When a sub-request of a weight read request corresponding to a set number of clock cycles flows into the arbitration unit, the first state flag may be set from 0 to 1, and when the sub-request flows out of the arbitration unit, the first state flag may be set from 1 to 0.
  • the first state flag When the first state flag is set from 1 to 0, it may indicate that after a preset running time, the weight attribute register has stored the weight attribute data of the set number of clock cycles, and at this time, the reference state flag is set from 0 to 1.
  • the electronic device can read the feature mapping attribute data from the storage unit in any clock cycle, and after a preset running time, the feature mapping attribute data flows into the systolic array and is calculated with the weight attribute data in the weight attribute register.
  • this clock cycle is the first clock cycle for reading the feature mapping attribute data.
  • the second state flag can be set from 0 to 1, and when the sub-request flows out of the arbitration unit, the second state flag can be set from 1 to 0.
  • the state flag is set from 1 to 0, it can indicate that the weight attribute data of the weight attribute register and the feature mapping attribute data of the first clock cycle are calculated after the preset running time. At this time, the reference state flag is set from 1 to 0.
  • the reference state flag is first set from 0 to 1, and then from 1 to 0.
  • the reference state flag can be obtained when any sub-request of the feature mapping read request is arbitrated by the arbitration unit. If the reference state flag is equal to 1, it is determined that the sub-request meets the second preset condition, and the second storage block to which the sub-request belongs is determined based on the address carried by the sub-request, and the sub-request is sent to the corresponding second storage block through the scheduler; if the reference state flag is equal to 0, it is determined that the sub-request does not meet the second preset condition, and the sub-request is blocked.
  • the sub-request meets the second preset condition and the sub-request belongs to the second storage block 0
  • the sub-request is sent to the second storage block 0 through the scheduler
  • the sub-request meets the second preset condition and the sub-request belongs to the second storage block 1
  • the sub-request is sent to the second storage block 1 through the scheduler.
  • the selection unit reads the data corresponding to the sub-request from the second storage block corresponding to the sub-request based on any sub-request of the feature map read request.
  • the data corresponding to each sub-request is collected by the collection unit.
  • the collection process can be seen in the description of FIG6 and will not be repeated here.
  • the collection unit collects the data corresponding to each sub-request of the feature map read request, it is equivalent to collecting the feature map attribute data corresponding to the feature map read request.
  • the feature map attribute data is input into the systolic array through the export command.
  • the arbitration unit arbitrates the sub-requests of the feature mapping read request of one clock cycle, the arbitration results of the sub-requests are the same. Based on this, after the feature mapping read request of one clock cycle is arbitrated by the arbitration unit, the feature mapping read request can be input into the conflict detection unit for the above-mentioned processing. In this case, the sub-requests of the feature mapping read request can be arbitrated by the arbitration unit in the processing block, or the processing block may not include the arbitration unit.
  • the sub-requests of the feature mapping read request can be directly sent to the corresponding second storage block through the hash unit, or the sub-requests of the feature mapping read request can be directly sent to the corresponding scheduler through the hash unit, and then sent to the corresponding second storage block after being scheduled by the scheduler.
  • the weight read request can be processed similarly.
  • the arbitration unit when any sub-request of the weight read request is arbitrated by the arbitration unit, if the reference state identifier is equal to 0, it is determined that the sub-request meets the first preset condition, the second storage block to which the sub-request belongs is determined based on the address carried by the sub-request, and the sub-request is sent to the corresponding second storage block through the scheduler; if the reference state identifier is equal to 1, it is determined that the sub-request does not meet the first preset condition, and the sub-request is blocked.
  • the arbitration unit determines that the sub-request of the weighted read request (corresponding to the first weighted read request) satisfies the first preset condition in each clock cycle of several clock cycles. As time passes, when the arbitration unit determines that the sub-request of the weighted read request does not satisfy the first preset condition, the arbitration unit can determine that the sub-request of the feature mapping read request (corresponding to the first feature mapping read request) satisfies the second preset condition.
  • the arbitration unit determines that the sub-request of the feature mapping read request satisfies the second preset condition, when the read delay of the weight attribute data and the read delay of the feature mapping attribute data are the same, the subsequent reading of the weight attribute data and the reading of the feature mapping attribute data can be performed without the arbitration of the arbitration unit, that is, the subsequent sub-request of the weighted read request (corresponding to the second weighted read request) and the sub-request of the feature mapping read request (corresponding to the second feature mapping read request) can be performed without the arbitration of the arbitration unit. This is because the read delay of the weight attribute data and the read delay of the feature mapping attribute data are both reference time cycles.
  • the electronic device can write feature mapping attribute data and weight attribute data into a storage unit based on a write request.
  • the following describes how to process the write request.
  • the write request includes at least one sub-request (corresponding to the third sub-request).
  • the hash unit determines the first storage block corresponding to the sub-request based on the address of the first storage block corresponding to the sub-request, and sets the request path of the processing block where the first storage block corresponding to the sub-request is located to be valid, so that the sub-request can reach the corresponding first storage block; if the sub-request is invalid, the hash unit sets the request path of the processing block where the first storage block corresponding to the sub-request is located to be invalid, so as to prevent the sub-request from reaching the corresponding first storage block.
  • the second storage block to which the sub-request belongs can be determined based on the address carried by the sub-request, and the sub-request is sent to the corresponding second storage block through the scheduler to The corresponding data is written into the second storage block.
  • the scheduler can receive sub-requests of feature mapping read requests, sub-requests of weighted read requests, and sub-requests of write requests.
  • the priorities of various sub-requests can be configured.
  • the priority of the sub-request of feature mapping read request is higher than the priority of the sub-request of weighted read request
  • the priority of the sub-request of weighted read request is higher than the priority of the sub-request of write request.
  • the scheduler Based on the priorities of various sub-requests, the scheduler sends various sub-requests to the second storage block in order.
  • the arbitration unit determines whether the sub-request of the feature mapping read request meets the second preset condition or whether the sub-request of the weighted read request meets the first preset condition based on the reference state identifier.
  • the condition is met, the data corresponding to the sub-request is read from the second storage block.
  • the storage resources required for the reference state identifier are less, which is conducive to reducing the chip area.
  • the arbitration unit performs arbitration on the sub-request, which is beneficial to construct the timing between the weight attribute data and the feature mapping attribute data.
  • the embodiment of the present application can achieve efficient switching between multiple requests, which is beneficial to improving the efficiency of data reading.
  • FIG. 12 is an architecture diagram of another storage system provided in an embodiment of the present application.
  • the storage system includes a processing unit 1201, and also includes a storage unit 1202 and a systolic array 1203 respectively connected to the processing unit 1201.
  • the storage unit 1202 is used to store weight attribute data and feature mapping attribute data.
  • the processing unit 1201 is used to obtain a first weight read request and a first feature map read request, wherein the first weight read request is used to request to read weight attribute data from a storage unit, and the first feature map read request is used to request to read feature map attribute data from a storage unit.
  • the processing unit 1201 is further used to obtain a reference state identifier, which is used to represent the state of a weight attribute register in the systolic array 1203 after a preset running time from the current time, and the weight attribute register is used to store weight attribute data.
  • the processing unit 1201 is further configured to read the weight attribute data stored in the storage unit to the systolic array 1203 in response to a first weight read request when the reference state identifier satisfies a first preset condition.
  • the processing unit 1201 is further configured to read the feature mapping attribute data stored in the storage unit to the systolic array 1203 in response to the first feature mapping read request when the reference state identifier satisfies the second preset condition;
  • the systolic array 1203 is used to perform calculations based on the weight attribute data and the feature map attribute data.
  • the processing unit 1201 includes a first state register, a reference state register, and a determination unit;
  • a first state register used to store a first state flag, the first state flag indicating whether the weight attribute register has stored the weight attribute data of a set number of clock cycles after a preset running time from the current time;
  • a reference status register used to store a reference status identifier
  • a determination unit is used to obtain a first state identifier; when the first state identifier represents that after a preset running time from the current time, the weight attribute register has stored the weight attribute data of a set number of clock cycles, it is determined that the reference state identifier represents that after the preset running time from the current time, the weight attribute register is in a state where the weight attribute data has been stored, and the reference state identifier satisfies a second preset condition: the reference state identifier represents that after the preset running time from the current time, the weight attribute register is in a state where the weight attribute data has been stored.
  • the processing unit 1201 includes a second state register, a reference state register, and a determination unit;
  • a second state register used to store a second state flag, the second state flag indicating whether the weight attribute data in the weight attribute register is calculated with the feature mapping attribute data of the first clock cycle after a preset running time from the current time;
  • a reference status register used to store a reference status identifier
  • a determination unit is used to obtain a second state identifier; when the second state identifier represents that after a preset running time from the current time, the weight attribute data in the weight attribute register and the feature mapping attribute data of the first clock cycle are calculated, it is determined that the reference state identifier represents that after the preset running time from the current time, the weight attribute register is in a state of waiting to store the weight attribute data, and the reference state identifier satisfies the first preset condition: the reference state identifier represents that after the preset running time from the current time, the weight attribute register is in a state of waiting to store the weight attribute data.
  • the processing unit 1201 is further configured to obtain a second weight read request and a second feature map read request, the second weight read request being used to request reading weight attribute data from the storage unit, and the second feature map read request being used to request reading feature map attribute data from the storage unit;
  • the processing unit 1201 is further configured to read the weight attribute data stored in the storage unit to the systolic array 1203 based on the second weight read request;
  • the processing unit 1201 is further configured to read the feature mapping attribute data stored in the storage unit to the systolic array 1203 based on the second feature mapping read request, and the read delay of the weight attribute data and the read delay of the feature mapping attribute data are preset running times.
  • the processing unit 1201 includes a hash unit, a reading unit, and a collecting unit
  • the storage unit 1202 includes at least one first storage block
  • Any first storage block used to store weight attribute data and feature map attribute data
  • a hash unit configured to determine, for any first weighted sub-request, a first storage block corresponding to any first weighted sub-request when any first weighted sub-request is a valid request, the first weighted read request including at least one first weighted sub-request;
  • a reading unit configured to read weight attribute data corresponding to any first weight sub-request from a first storage block corresponding to any first weight sub-request
  • the collecting unit is used to collect the weight attribute data corresponding to each first weight sub-request, and send the weight attribute data corresponding to each first weight sub-request to the systolic array 1203.
  • system further includes a conflict detection unit
  • a conflict detection unit used for extracting an address of a first storage block corresponding to any first weight sub-request from any first weight sub-request
  • the conflict detection unit is also used to determine that any first weight sub-request is a valid request in response to the address of the first storage block corresponding to any first weight sub-request being different from the address of the first storage block corresponding to the reference first weight sub-request, and the reference first weight sub-request is at least one first weight sub-request among multiple first weight sub-requests except any first weight sub-request.
  • any first storage block includes at least one second storage block
  • Any second storage block used to store weight attribute data and feature map attribute data
  • the reading unit is used to determine the second storage block corresponding to any first weight sub-request; and read the weight attribute data corresponding to any first weight sub-request from the second storage block corresponding to any first weight sub-request.
  • the processing unit 1201 is further used to obtain a write request, which is used to write weight attribute data or feature mapping attribute data into a storage unit; and write the weight attribute data or feature mapping attribute data corresponding to the write request into the storage unit.
  • the processing unit 1201 includes a hash unit and a write unit, and the storage unit 1202 includes at least one first storage block;
  • a hash unit configured to determine, for any third sub-request, a first storage block corresponding to any third sub-request, The write request includes at least one third sub-request;
  • a writing unit is used to write the weight attribute data or feature mapping attribute data corresponding to any third sub-request into the first storage block corresponding to any third sub-request.
  • the function of the first state register, the function of the second state register, the function of the reference state register and the function of the determination unit can be implemented by the arbitration unit shown in FIG7.
  • the function of the hash unit can be implemented by the hash unit shown in FIG7.
  • the function of the reading unit can be implemented by the scheduler and the selection unit shown in FIG8.
  • the function of the collection unit can be implemented by the collection unit shown in FIG7.
  • the function of the conflict detection unit can be implemented by the conflict detection unit shown in FIG7.
  • the function of the second storage block can be implemented by the second storage block shown in FIG7.
  • the function of the writing unit can be implemented by the scheduler shown in FIG8.
  • FIG. 12 belongs to the same concept, and the specific implementation process is detailed in the method embodiment.
  • the contents in the system provided in FIG. 12 corresponding to FIG. 7 and FIG. 8 can be found in the description of FIG. 7 and FIG. 8, and will not be repeated here.
  • the above system characterizes the state of the weight attribute register in the systolic array through a reference state identifier.
  • the weight attribute data stored in the storage unit is read to the systolic array in response to the first weight read request;
  • the reference state identifier satisfies the second preset condition
  • the feature mapping attribute data stored in the storage unit is read to the systolic array in response to the first feature mapping read request.
  • the storage resources required for the reference state identifier are fewer.
  • the system can be applied to chips. Since the fewer the storage resources, the smaller the chip area, the chip has the conditions to reduce the chip area.
  • FIG9 is a schematic diagram of the structure of a data reading device provided in an embodiment of the present application. As shown in FIG9 , the device includes:
  • An acquisition module 901 is used to acquire a first weight read request and a first feature map read request, wherein the first weight read request is used to request to read weight attribute data from a storage unit, and the first feature map read request is used to request to read feature map attribute data from a storage unit;
  • the acquisition module 901 is further used to acquire a reference state identifier, which is used to represent the state of a weight attribute register in the systolic array after a preset running time from the current time, and the weight attribute register is used to store weight attribute data;
  • a reading module 902 configured to read the weight attribute data stored in the storage unit into the systolic array in response to a first weight read request when the reference state identifier satisfies a first preset condition
  • the reading module 902 is also used to read the feature mapping attribute data stored in the storage unit to the systolic array in response to the first feature mapping read request when the reference state identifier meets the second preset condition.
  • the systolic array is used to perform calculations based on the weight attribute data and the feature mapping attribute data.
  • the reference state flag satisfies the first preset condition: the reference state flag indicates that the weight attribute register is in a state of waiting to store weight attribute data after a preset running time from the current time;
  • the reference state flag satisfies the second preset condition that: the reference state flag indicates that after a preset running time from the current time, the weight attribute register is in a state where all weight attribute data are stored.
  • the acquisition module 901 is further used to acquire a first state flag, which indicates whether the weight attribute register has stored the weight attribute data of a set number of clock cycles after a preset running time from the current time;
  • the device also includes:
  • a determination module is used to determine that the reference state identification represents that the weight attribute register is in a state where the weight attribute register has stored the weight attribute data for a set number of clock cycles after the preset running time from the current time, when the first state identification represents that the weight attribute register has stored the weight attribute data for a set number of clock cycles after the preset running time from the current time.
  • the acquisition module 901 is further used to acquire a second state identifier, which indicates whether the weight attribute data in the weight attribute register is calculated with the feature mapping attribute data of the first clock cycle after a preset running time from the current time;
  • the device also includes:
  • a determination module is used to determine that the reference state identification represents that the weight attribute register is in a state of waiting to store weight attribute data after the preset running time from the current time, when the weight attribute data in the weight attribute register and the feature mapping attribute data of the first clock cycle are calculated after the second state identification represents that the weight attribute data in the weight attribute register and the feature mapping attribute data of the first clock cycle are calculated.
  • the acquisition module 901 is further used to acquire a second weight read request and a second feature map read request, the second weight read request is used to request to read weight attribute data from the storage unit, and the second feature map read request is used to request to read feature map attribute data from the storage unit;
  • the reading module 902 is also used to read the weight attribute data stored in the storage unit to the pulsation array based on the second weight read request; and read the feature mapping attribute data stored in the storage unit to the pulsation array based on the second feature mapping read request, and the read delay of the weight attribute data and the read delay of the feature mapping attribute data are preset running times.
  • the first weight read request includes at least one first weight sub-request
  • the storage unit includes at least one first storage block
  • the reading module 902 is used to determine the first storage block corresponding to any first weight sub-request for any first weight sub-request, when any first weight sub-request is a valid request, read the weight attribute data corresponding to any first weight sub-request from the first storage block corresponding to any first weight sub-request; and send the weight attribute data corresponding to each first weight sub-request to the pulsating array.
  • the device further includes:
  • An extraction module used to extract the address of the first storage block corresponding to any first weight sub-request from any first weight sub-request
  • a determination module is used to determine that any first weight sub-request is a valid request in response to the address of the first storage block corresponding to any first weight sub-request being different from the address of the first storage block corresponding to the reference first weight sub-request, and the reference first weight sub-request is the first weight sub-request among multiple first weight sub-requests other than any first weight sub-request.
  • any first storage block includes at least one second storage block
  • the reading module 902 is used to determine the second storage block corresponding to any first weight sub-request; and read the weight attribute data corresponding to any first weight sub-request from the second storage block corresponding to any first weight sub-request.
  • the acquisition module 901 is further used to acquire a write request, where the write request is used to write the third data into the storage unit, where the third data is weight attribute data or feature mapping attribute data;
  • the device also includes:
  • the writing module is used to write the weight attribute data or feature mapping attribute data corresponding to the write request into the storage unit.
  • the write request includes at least one third sub-request
  • the storage unit includes at least one first storage block
  • a writing module is used to determine, for any third sub-request, a first storage block corresponding to any third sub-request; and write the weight attribute data or feature mapping attribute data corresponding to any third sub-request into the first storage block corresponding to any third sub-request.
  • the above-mentioned device characterizes the state of the weight attribute register in the pulsation array through a reference state identifier.
  • the weight attribute data stored in the storage unit is read to the pulsation array in response to the first weight read request;
  • the reference state identifier satisfies the second preset condition
  • the feature mapping attribute data stored in the storage unit is read to the pulsation array in response to the first feature mapping read request.
  • the storage resources required for the reference state identifier are fewer.
  • the device can be applied to chips. Since the fewer the storage resources, the smaller the chip area, the chip has the conditions to reduce the chip area.
  • the device provided in FIG. 9 above only uses the division of the above functional modules as an example to illustrate when implementing its functions.
  • the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.
  • the device and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiment, which will not be repeated here.
  • FIG10 shows a block diagram of a terminal device 1000 provided by an exemplary embodiment of the present application. 1000 includes: a processor 1001 and a memory 1002 .
  • the processor 1001 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc.
  • the processor 1001 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array).
  • the processor 1001 may also include a main processor and a coprocessor.
  • the main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state.
  • the processor 1001 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen.
  • the processor 1001 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.
  • AI Artificial Intelligence
  • the memory 1002 may include one or more computer-readable storage media, which may be non-transitory.
  • the memory 1002 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices.
  • the non-transitory computer-readable storage medium in the memory 1002 is used to store at least one computer-readable instruction, which is used to be executed by the processor 1001 to implement the data reading method provided in the method embodiment of the present application.
  • the terminal device 1000 may further optionally include: a peripheral device interface 1003 and at least one peripheral device.
  • the processor 1001, the memory 1002 and the peripheral device interface 1003 may be connected via a bus or a signal line.
  • Each peripheral device may be connected to the peripheral device interface 1003 via a bus, a signal line or a circuit board.
  • the peripheral device includes: at least one of a radio frequency circuit 1004, a display screen 1005, a camera assembly 1006, an audio circuit 1007 and a power supply 1008.
  • the peripheral device interface 1003 may be used to connect at least one peripheral device related to I/O (Input/Output) to the processor 1001 and the memory 1002.
  • the processor 1001, the memory 1002, and the peripheral device interface 1003 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 1001, the memory 1002, and the peripheral device interface 1003 may be implemented on a separate chip or circuit board, which is not limited in this embodiment.
  • the radio frequency circuit 1004 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals.
  • the radio frequency circuit 1004 communicates with the communication network and other communication devices through electromagnetic signals.
  • the radio frequency circuit 1004 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals into electrical signals.
  • the radio frequency circuit 1004 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, and the like.
  • the radio frequency circuit 1004 can communicate with other terminals through at least one wireless communication protocol.
  • the display screen 1005 can be one, which is set on the front panel of the terminal device 1000; in other embodiments, the display screen 1005 can be at least two, which are respectively set on different surfaces of the terminal device 1000 or are folded; in other embodiments, the display screen 1005 can be a flexible display screen, which is set on the curved surface or folded surface of the terminal device 1000. Even, the display screen 1005 can also be set to a non-rectangular irregular shape, that is, a special-shaped screen.
  • the display screen 1005 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).
  • the camera assembly 1006 is used to collect images or videos.
  • the camera assembly 1006 includes a front camera and Rear camera.
  • the front camera is set on the front panel of the terminal, and the rear camera is set on the back of the terminal.
  • there are at least two rear cameras which are any one of a main camera, a depth of field camera, a wide-angle camera, and a telephoto camera, so as to realize the fusion of the main camera and the depth of field camera to realize the background blur function, the fusion of the main camera and the wide-angle camera to realize panoramic shooting and VR (Virtual Reality) shooting function or other fusion shooting functions.
  • the camera assembly 1006 may also include a flash.
  • the flash can be a single-color temperature flash or a dual-color temperature flash.
  • a dual-color temperature flash refers to a combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.
  • the audio circuit 1007 may include a microphone and a speaker.
  • the microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals and input them into the processor 1001 for processing, or input them into the radio frequency circuit 1004 to achieve voice communication.
  • the microphone may also be an array microphone or an omnidirectional acquisition microphone.
  • the speaker is used to convert the electrical signal from the processor 1001 or the radio frequency circuit 1004 into sound waves.
  • the speaker may be a traditional film speaker or a piezoelectric ceramic speaker.
  • the speaker When the speaker is a piezoelectric ceramic speaker, it can not only convert the electrical signal into sound waves audible to humans, but also convert the electrical signal into sound waves inaudible to humans for purposes such as ranging.
  • the audio circuit 1007 may also include a headphone jack.
  • the power supply 1008 is used to power various components in the terminal device 1000.
  • the power supply 1008 can be an alternating current, a direct current, a disposable battery, or a rechargeable battery.
  • the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery.
  • a wired rechargeable battery is a battery charged through a wired line
  • a wireless rechargeable battery is a battery charged through a wireless coil.
  • the rechargeable battery can also be used to support fast charging technology.
  • the terminal device 1000 further includes one or more sensors 1009 .
  • the one or more sensors 1009 include, but are not limited to: an acceleration sensor 1011 , a gyroscope sensor 1012 , a pressure sensor 1013 , an optical sensor 1014 , and a proximity sensor 1015 .
  • the acceleration sensor 1011 can detect the magnitude of acceleration on the three coordinate axes of the coordinate system established by the terminal device 1000.
  • the acceleration sensor 1011 can be used to detect the components of gravity acceleration on the three coordinate axes.
  • the processor 1001 can control the display screen 1005 to display the user interface in a horizontal view or a vertical view according to the gravity acceleration signal collected by the acceleration sensor 1011.
  • the acceleration sensor 1011 can also be used for collecting game or user motion data.
  • the gyro sensor 1012 can detect the body direction and rotation angle of the terminal device 1000, and the gyro sensor 1012 can cooperate with the acceleration sensor 1011 to collect the user's 3D actions on the terminal device 1000.
  • the processor 1001 can implement the following functions based on the data collected by the gyro sensor 1012: motion sensing (such as changing the UI according to the user's tilt operation), image stabilization during shooting, game control, and inertial navigation.
  • the pressure sensor 1013 can be set on the side frame of the terminal device 1000 and/or the lower layer of the display screen 1005.
  • the processor 1001 performs left and right hand recognition or shortcut operations according to the holding signal collected by the pressure sensor 1013.
  • the processor 1001 controls the operability controls on the UI interface according to the user's pressure operation on the display screen 1005.
  • the operability controls include at least one of a button control, a scroll bar control, an icon control, and a menu control.
  • the optical sensor 1014 is used to collect the ambient light intensity.
  • the processor 1001 can control the display brightness of the display screen 1005 according to the ambient light intensity collected by the optical sensor 1014. Specifically, when the ambient light intensity is high, the display brightness of the display screen 1005 is increased; when the ambient light intensity is low, the display brightness of the display screen 1005 is reduced.
  • the processor 1001 can also dynamically adjust the shooting parameters of the camera assembly 1006 according to the ambient light intensity collected by the optical sensor 1014.
  • the proximity sensor 1015 also known as a distance sensor, is usually disposed on the front panel of the terminal device 1000.
  • the proximity sensor 1015 is used to collect the distance between the user and the front of the terminal device 1000.
  • the processor 1001 controls the display screen 1005 to switch from the on screen state to the off screen state; when the proximity sensor 1015 detects that the distance between the user and the front of the terminal device 1000 is gradually decreasing, the processor 1001 controls the display screen 1005 to switch from the on screen state to the off screen state;
  • the processor 1001 controls the display screen 1005 to switch from the screen-off state to the screen-on state.
  • FIG. 10 does not limit the terminal device 1000 and may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.
  • FIG11 is a schematic diagram of the structure of the server provided in the embodiment of the present application.
  • the server 1100 may have relatively large differences due to different configurations or performances, and may include one or more processors 1101 and one or more memories 1102, wherein the one or more memories 1102 store at least one computer-readable instruction, and the at least one computer-readable instruction is loaded and executed by the one or more processors 1101 to implement the data reading method provided in the above-mentioned various method embodiments.
  • the processor 1101 is a CPU.
  • the server 1100 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output.
  • the server 1100 may also include other components for implementing device functions, which will not be described in detail here.
  • the above-mentioned computer readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.
  • ROM read-only memory
  • RAM random access memory
  • CD-ROM compact disc
  • magnetic tape a magnetic tape
  • floppy disk a magnetic tape
  • optical data storage device etc.
  • a computer program product is further provided.
  • the computer program product stores at least one computer-readable instruction.
  • the at least one computer-readable instruction is loaded and executed by a processor to enable an electronic device to implement any of the above data reading methods.

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Abstract

一种数据读取方法，由电子设备的处理器执行，电子设备包括分别与处理器连接的脉动阵列和存储单元，脉动阵列包含权重属性寄存器，方法包括：获取第一权重读请求和第一特征映射读请求，第一权重读请求用于请求从存储单元中读取权重属性数据，第一特征映射读请求用于请求从存储单元中读取特征映射属性数据(301)；获取参考状态标识，参考状态标识用于表征在从当前时间起的预设运行时间后，脉动阵列中权重属性寄存器的状态，权重属性寄存器用于寄存权重属性数据(302)；在参考状态标识满足第一预设条件的情况下，响应于第一权重读请求将存储单元存储的权重属性数据读取至脉动阵列(303)；及在参考状态标识满足第二预设条件的情况下，响应于第一特征映射读请求将存储单元存储的特征映射属性数据读取至脉动阵列，脉动阵列用于基于权重属性数据和特征映射属性数据进行计算(304)。

Description

数据读取方法、装置、设备及可读存储介质
相关申请
本申请要求2023年3月9日申请的，申请号为2023102548749，名称为“数据读取方法、装置、设备及可读存储介质”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请实施例涉及计算机技术领域，特别涉及一种数据读取方法、装置、设备及可读存储介质。
背景技术
峰值算力是计算机技术领域衡量计算机性能的一个指标，峰值算力是指处理器单位时间内能达到的最大计算次数，而从存储单元中读取数据的能力与峰值算力息息相关。
相关技术中，存在一种包括多行多列处理引擎的阵列结构，该阵列结构称为脉动阵列。可以将存储单元中的数据读取至脉动阵列，通过脉动阵列对数据进行高效计算。通常情况下，在不满足将存储单元中的数据读取至脉动阵列的条件下，响应于针对目标数据的读请求，会将存储单元中的目标数据寄存在队列中。在满足将存储单元中的数据读取至脉动阵列的条件下，会从队列中取出目标数据，将目标数据送入脉动阵列。
一般来说，芯片可以作为存储单元、队列等具有数据存储功能的物体的载体。然而，队列需要占用一定的寄存资源，容易致使芯片面积大。
发明内容
根据本申请的各种实施例，提供一种数据读取方法、装置、设备及可读存储介质。
一方面，提供了由电子设备的处理器执行，所述电子设备包括分别与所述处理器连接的脉动阵列和存储单元，所述脉动阵列包含权重属性寄存器，所述方法包括：
获取第一权重读请求和第一特征映射读请求，所述第一权重读请求用于请求从存储单元中读取权重属性数据，所述第一特征映射读请求用于请求从所述存储单元中读取特征映射属性数据；
获取参考状态标识，所述参考状态标识用于表征在从当前时间起的预设运行时间后，脉动阵列中权重属性寄存器的状态，所述权重属性寄存器用于寄存所述权重属性数据；
在所述参考状态标识满足第一预设条件的情况下，响应于所述第一权重读请求将所述存储单元存储的所述权重属性数据读取至所述脉动阵列；及
在所述参考状态标识满足第二预设条件的情况下，基于所述第一特征映射读请求将所述存储单元存储的所述特征映射属性数据读取至所述脉动阵列，所述脉动阵列用于基于所述权重属性数据和特征映射属性数据进行计算。
另一方面，提供了一种存储系统，所述存储系统包括处理单元和存储单元；
所述存储单元，用于存储权重属性数据和特征映射属性数据；
所述处理单元，用于获取第一权重读请求和第一特征映射读请求，所述第一权重读请求用于从所述存储单元中读取权重属性数据，所述第一特征映射读请求用于请求从所述存储单元中读取特征映射属性数据；
所述处理单元，还用于获取参考状态标识，所述参考状态标识用于表征在从当前时间起的预设运行时间后，脉动阵列中权重属性寄存器的状态，所述权重属性寄存器用于寄存所述权重属性数据；
所述处理单元，还用于在所述参考状态标识满足第一预设条件的情况下，响应于所述第一权重读请求将所述存储单元存储的所述权重属性数据读取至所述脉动阵列；及
所述处理单元，还用于在所述参考状态标识满足第二预设条件的情况下，基于所述第一特征映射读请求将所述存储单元存储的所述特征映射属性数据读取至所述脉动阵列，所述脉动阵列用于基于所述权重属性数据和特征映射属性数据进行计算。
另一方面，提供了一种数据读取装置，所述装置包括：
获取模块，用于获取第一权重读请求和第一特征映射读请求，所述第一权重读请求用于请求从存储单元中读取权重属性数据，所述第一特征映射读请求用于请求从所述存储单元中读取特征映射属性数据；
所述获取模块，还用于获取参考状态标识，所述参考状态标识用于表征在从当前时间起的预设运行时间后，脉动阵列中权重属性寄存器的状态，所述权重属性寄存器用于寄存所述权重属性数据；
读取模块，用于在所述参考状态标识满足第一预设条件的情况下，响应于所述第一权重读请求将所述存储单元存储的所述权重属性数据读取至所述脉动阵列；及
所述读取模块，还用于在所述参考状态标识满足第二预设条件的情况下，基于所述第一特征映射读请求将所述存储单元存储的所述特征映射属性数据读取至所述脉动阵列，所述脉动阵列用于基于所述权重属性数据和特征映射属性数据进行计算。
另一方面，提供了一种电子设备，所述电子设备包括处理器和存储器，所述存储器中存储有至少一条计算机可读指令，所述至少一条计算机可读指令由所述处理器加载并执行，以使所述电子设备实现上述任一所述的数据读取方法。
另一方面，还提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有至少一条计算机可读指令，所述至少一条计算机可读指令由处理器加载并执行，以使电子设备实现上述任一所述的数据读取方法。
另一方面，还提供了一种计算机程序产品，所述计算机程序产品中存储有至少一条计算机可读指令，所述至少一条计算机可读指令由处理器加载并执行，以使电子设备实现上述任一种数据读取方法。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据公开的附图获得其他的附图。
图1是本申请实施例提供的一种数据读取方法的实施环境示意图；
图2是本申请实施例提供的一种脉动阵列的数据加载示意图；
图3是本申请实施例提供的一种数据读取方法的流程图；
图4是本申请实施例提供的一种状态标识的更新示意图；
图5是本申请实施例提供的一种子请求是否有效的判断示意图；
图6是本申请实施例提供的一种数据收集过程的示意图；
图7是本申请实施例提供的一种存储系统的架构图；
图8是本申请实施例提供的一种仲裁单元的结构示意图；
图9是本申请实施例提供的一种数据读取装置的结构示意图；
图10是本申请实施例提供的一种终端设备的结构示意图；
图11是本申请实施例提供的一种服务器的结构示意图；
图12是本申请实施例提供的另一种存储系统的架构图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
图1是本申请实施例提供的一种数据读取方法的实施环境示意图，如图1所示，该实施环境包括终端设备101和服务器102。其中，本申请实施例中的数据读取方法可以由终端设备101执行，也可以由服务器102执行，或者由终端设备101和服务器102共同执行。
终端设备101可以是智能手机、游戏主机、台式计算机、平板电脑、膝上型便携计算机、智能电视、智能车载设备、智能语音交互设备、智能家电等。服务器102可以为一台服务器，或者为多台服务器组成的服务器集群，或者为云计算平台和虚拟化中心中的任意一种，本申请实施例对此不加以限定。服务器102可以与终端设备101通过有线网络或无线网络进行通信连接。服务器102可以具有数据处理、数据存储以及数据收发等功能，在本申请实施例中不加以限定。终端设备101和服务器102的数量不受限制，可以是一个或多个。
为便于理解下述各可选实施例，下面结合图2对脉动阵列进行描述。请参见图2，图2是本申请实施例提供的一种脉动阵列的数据加载示意图。
脉动阵列(Systolic Array)是一种阵列结构，其工作方式和过程可以类比于人体血液循环系统的工作方式和过程。在脉动阵列中，数据按设定的流水方式在脉动阵列的处理引擎(Process Engine，PE)间有节奏地流动。在数据流动的过程中，所有的处理引擎并行地对流经它的数据进行处理，因此，脉动阵列可以达到很高的并行处理速度。
脉动阵列包括M行N列的处理引擎，M和N均为大于1的正整数。可选地，脉动阵列的任两列处理引擎之间可以插入打拍寄存器，和/或，脉动阵列的任两行处理引擎之间可以插入打拍寄存器。一方面，由于脉动阵列的尺寸较大，通过插入打拍寄存器，可以便于布局布线，有利于物理实现。另一方面，由于处理引擎进行数据处理需要一定的时间，而数据流经一列处理引擎所需的时间小于数据流经整个脉动阵列所需的时间，因此，通过插入打拍寄存器，可以提高时钟频率，降低时钟周期，减小延迟。在示例性实施例中，打拍寄存器为一级打拍寄存器。例如，图2示出的脉动阵列包括8行8列的处理引擎，且脉动阵列的每两列处理引擎之间插入了打拍寄存器。
电子设备可以包括处理器、存储单元和脉动阵列，电子设备包括分别与所述处理器连接的脉动阵列和存储单元，所述脉动阵列包含权重属性寄存器。电子设备可以从存储单元中读取数据，并将数据加载至脉动阵列中。本申请实施例不对存储单元做限定，示例性地，存储单元为L1存储(L1Memory)、L2存储、内盘等中的任一项。
本申请实施例适用于人工智能技术领域。在人工智能技术领域中，可以通过神经网络模型对图像、文本、音频等媒体信息的特征进行特征提取、分类等处理。神经网络模型对媒体信息的特征进行处理的本质为：神经网络模型的模型参数和媒体信息的特征进行计算。在本申请实施例中，媒体信息的特征属于特征映射(Feature Map，FM)属性数据，而神经网络模型的模型参数属于权重(Weight，WT)属性数据。
存储单元中的数据包括权重属性数据和特征映射属性数据。其中，将权重属性数据和特征映射属性数据加载至脉动阵列时，权重属性数据的加载和特征映射属性数据的加载具有一定的时序关系。
以图2为例，电子设备可以从存储单元中读取权重属性数据。其中，读取的权重属性数据需要经过三角化阵列(Triangularization Array)打拍，将水平的数据转换为斜三角的数据后输入至脉动阵列。其中，由于脉动阵列中插入了打拍寄存器，因此，需要通过三角化阵列对权重属性数据打拍。
具体来说，脉动阵列包括8行8列的处理引擎。在第一个时钟周期，电子设备可以基于针对权重属性数据的读请求，从存储单元中加载权重属性数据，权重属性数据经过三角化阵列之后输入脉动阵列，此时，权重属性数据位于脉动阵列第一列第一行的处理引擎中。在第二个时钟周期，电子设备可以基于针对权重属性数据的读请求，从存储单元中加载权重属性数据，权重属性数据经过三角化阵列之后输入脉动阵列，此时，权重属性数据位于脉动阵列第一列第一行、第一列第二行、以及第二列第一行的处理引擎中。其中，第一个 时钟周期加载的权重属性数据位于第一列第二行的处理引擎中，第二个时钟周期加载的权重属性数据位于第一列第一行和第二列第一行的处理引擎中。在第三个时钟周期，电子设备可以基于针对权重属性数据的读请求，从存储单元中加载权重属性数据，权重属性数据经过三角化阵列之后输入脉动阵列，此时，权重属性数据位于脉动阵列第一列第一行至第三行、第二列第一行至第二行、以及第三列第一行的处理引擎中。其中，第一个时钟周期加载的权重属性数据位于第一列第三行的处理引擎中，第二个时钟周期加载的权重属性数据位于第一列第二行和第二列第二行的处理引擎中，第三个时钟周期加载的权重属性数据位于第一列第一行、第二列第一行和第三列第一行的处理引擎中。以此类推。
由上述第一至三个时钟周期的描述可知，第一个时钟周期加载的权重属性数据的流动方式为：从第一列第一行的处理引擎流至第一列第二行的处理引擎，再流至第一列第三行的处理引擎；第二个时钟周期加载的权重属性数据的流动方式为：从第一列第一行和第二列第一行的处理引擎流至第一列第二行和第二列第二行的处理引擎。也就是说，每经过一个时钟周期，已加载至脉动阵列中的权重属性数据下沉一行。此外，在第一个时钟周期将权重属性数据加载至第一列第一行的处理引擎，在第二个时钟周期将权重属性数据加载至第一列第一行和第二列第一行的处理引擎，在第三个时钟周期将权重属性数据加载至第一列第一行、第二列第一行和第三列第一行的处理引擎。也就是说，每一个时钟周期新加载一行权重属性数据至脉动阵列，且该行权重属性数据比上一个时钟周期的权重属性数据多一列。
由于每经过一个时钟周期，已加载至脉动阵列中的权重属性数据下沉一行，同时，新加载一行权重属性数据至脉动阵列，且该行权重属性数据比上一个时钟周期的权重属性数据多一列。因此，经过八个时钟周期后，权重属性数据位于脉动阵列第一列第一至八行、第二列第一至七行、第三列第一至六行、第四列第一至五行、第五列第一至四行、第六列第一至三行、第七列第一至二行、以及第八列第一行的处理引擎中，如图2中的灰色处理引擎。
需要说明的是，由于脉动阵列包括M行N列的处理引擎，而一个时钟周期新加载一行权重属性数据至脉动阵列，且该行权重属性数据比上一个时钟周期的权重属性数据多一列。因此，若某一个时钟周期新加载一行N个权重属性数据至脉动阵列，则该时钟周期之后的每一个时钟周期新加载一行N个权重属性数据至脉动阵列。也就是说，一个时钟周期新加载的权重属性数据不大于一行处理引擎的数量。
在脉动阵列第一列所有的处理引擎加载有权重属性数据的情况下，电子设备可以从存储单元中读取特征映射属性数据。在任一个时钟周期，电子设备可以基于针对特征映射属性数据的读请求，从存储单元中加载特征映射属性数据，特征映射属性数据从脉动阵列的输入侧(如左侧)流入脉动阵列第一列处理引擎，通过第一列的各个处理引擎，对驻留在处理引擎中的权重属性数据和流入处理引擎的特征映射属性数据进行计算。可选地，通过处理引擎，对权重属性数据和特征映射属性数据进行相乘计算和相加计算中的至少一项。
接下来，一个时钟周期结束，进入该一个时钟周期的下一个时钟周期，该一个时钟周期的下一个时钟周期即为当前时间下的当前时钟周期。在当前时钟周期，电子设备可以基于针对权重属性数据的读请求，从存储单元中加载权重属性数据，权重属性数据经过三角化阵列之后输入脉动阵列，此时，已加载至脉动阵列中的权重属性数据下沉一行，且新加载一行权重属性数据至脉动阵列，使得脉动阵列第一列所有的处理引擎和第二列所有的处理引擎加载有权重属性数据。这种情况下，上一个时钟周期加载的特征映射属性数据流入脉动阵列第二列处理引擎，通过第二列的各个处理引擎，对驻留在处理引擎中的权重属性数据和流入处理引擎的特征映射属性数据进行计算。此外，在当前时钟周期，电子设备可以基于针对特征映射属性数据的读请求，从存储单元中加载特征映射属性数据，特征映射属性数据从脉动阵列的输入侧(如左侧)流入脉动阵列第一列处理引擎，通过第一列的各个处理引擎，对驻留在处理引擎中的权重属性数据和流入处理引擎的特征映射属性数据进 行计算。以此类推。
也就是说，在脉动阵列第一列所有的处理引擎加载有权重属性数据的情况下，在每一个时钟周期，已加载至脉动阵列中的权重属性数据下沉一行，已加载至脉动阵列中的特征映射属性数据右移一列，同时，新加载一行权重属性数据至脉动阵列，新加载一列特征映射属性数据至脉动阵列。此外，流经每一个处理引擎的特征映射属性数据会与流经该处理引擎中的权重属性数据一起参与计算。最终，权重属性数据从脉动阵列第一输出侧(如与输入侧相邻的一侧，具体比如是下侧)流出，而特征映射属性数据从脉动阵列的第二输出侧(如与输入侧相对的一侧，具体比如是右侧)流出。
综合上述内容可知，电子设备需要将存储单元中的权重属性数据加载至脉动阵列第一列处理引擎之后，才可以将存储单元中的特征映射属性数据加载至脉动阵列第一列处理引擎，而电子设备将存储单元中的权重属性数据加载至脉动阵列第一列处理引擎中需要经过至少一个时钟周期。此外，只有驻留在脉动阵列第一列处理引擎中的权重属性数据和流入第一列处理引擎中的特征映射属性数据进行计算的情况下，电子设备才可以再次将存储单元中的权重属性数据加载至脉动阵列。基于上述内容得知，权重属性数据的加载和特征映射属性数据的加载具有一定的时序关系。
由于需要经过至少一个时钟周期将存储单元中的权重属性数据加载至脉动阵列第一列处理引擎之后，才可以将存储单元中的特征映射属性数据加载至脉动阵列，且，只有在将脉动阵列第一列处理引擎中的权重属性数据和流入第一列处理引擎中的特征映射属性数据进行计算之后，才可以再次将存储单元中的特征映射属性数据加载至脉动阵列，因此，相关技术在存储单元中例化了队列。在读数据端(是存储单元中用于将特征映射属性数据或者权重属性数据输入至脉动阵列的端口)不具备接收数据的条件下，也就是说，在存储单元中的特征映射属性数据或者权重属性数据无法加载至脉动阵列的情况下，响应于读请求，从存储单元中读取数据并寄存在队列中。在读数据端具备接收数据的条件下，也就是说，在存储单元中的特征映射属性数据或者权重属性数据可以加载至脉动阵列的情况下，从队列中取出数据，通过读数据端将数据送入脉动阵列。
由于存储单元中的数据包括权重属性数据和特征映射属性数据，因此，需要例化权重属性数据对应的队列和特征映射属性数据对应的队列。又由于存在读延迟，因此，需要队列的深度大于或者等于读延迟，比如读延迟为10个时钟周期，则队列的深度至少为10，这样可以避免数据的丢失。随着处理数据量的增大，读延迟也会增加，使得两个队列需要占用大量的寄存资源，导致芯片面积大。
本申请实施例提供了一种数据读取方法，该方法可应用于上述实施环境中，可以降低芯片面积。以图3所示的本申请实施例提供的一种数据读取方法的流程图为例，为便于描述，将执行本申请实施例中的数据读取方法的终端设备101或者服务器102称为电子设备，该方法可以由电子设备来执行，具体可由电子设备的处理器执行，电子设备还包括分别与所述处理器连接的脉动阵列和存储单元，所述脉动阵列包含权重属性寄存器。如图3所示，该方法包括如下步骤。
步骤301，获取第一权重读请求和第一特征映射读请求。其中，第一权重读请求用于请求从存储单元中读取权重属性数据，第一特征映射读请求用于请求从存储单元中读取特征映射属性数据。
本申请实施例的数据读取方法适用于人工智能技术领域，而在人工智能技术领域中，常通过神经网络模型对媒体信息的特征进行处理。其中，权重属性数据属于神经网络模型的模型参数，具体可以是在神经网络模型的层中，表征该权重属性数据所对应变量对于该层计算结果贡献的大小。神经网络模型可以为用于对媒体信息进行特征提取的特征提取模型，或者，神经网络模型也可以为用于对媒体信息进行分类的分类模型等。特征映射属性数据属于媒体信息的特征，在示例性实施例中，媒体信息包括图像、文本、音频等至少一项，即特征映射属性数据属于图像特征、文本特征或音频特征等中的至少一项。
电子设备可以在任一个时钟周期获取第一权重读(Weight Read，wt_rd)请求，第一权重读请求用于读取权重(Weight，wt)属性数据。此外，电子设备可以在任一个时钟周期获取第一特征映射读(Feature Map Read，fm_rd)请求，第一特征映射读请求用于读取特征映射(Feature Map，fm)属性数据。
本申请实施例不对第一权重读请求和第一特征映射读请求的先后顺序做限定。即，可以同时获取第一权重读请求和第一特征映射读请求，也可以先获取第一权重读请求，再获取第一特征映射读请求，还可以先获取第一特征映射读请求再获取第一权重读请求。
步骤302，获取参考状态标识。其中，参考状态标识用于表征在从当前时间起的预设运行时间后，脉动阵列中权重属性寄存器的状态，权重属性寄存器用于寄存权重属性数据。
可选地，电子设备存在一个仲裁(Arbiter)单元，通过维护一个参考状态寄存器来协调权重属性数据和特征映射属性数据之间的时序关系。参考状态寄存器可以记为权重占领(Weight Occupy，wt_occupy)寄存器，参考状态寄存器用于寄存参考状态标识，可选地，参考状态标识可以记为wt_occupy。其中，参考状态标识用于表征在从当前时间起的预设运行时间后，脉动阵列中权重属性寄存器的状态，而权重属性寄存器用于寄存权重属性数据。预设运行时间，英文为pre-defined elapsed time，可以是从某个时间点起计算的预设时长的时间。可选地，预设运行时间为判断参考状态标识是否满足第一预设条件的时刻至对应数据进入脉动阵列的时刻相隔的时间。判断参考状态标识是否满足第一预设条件的时刻至对应数据进入脉动阵列的时刻相隔的时间，可以与判断参考状态标识是否满足第二预设条件的时刻至对应数据进入脉动阵列的时刻相隔的时间相同。由于时钟频率是规律的，因此预设运行时间可以是预先设定的。
步骤303，在参考状态标识满足第一预设条件的情况下，响应于第一权重读请求将存储单元存储的权重属性数据读取至脉动阵列。
电子设备从参考状态寄存器中获取到参考状态标识之时，相当于得到了预设运行时间后权重属性寄存器的状态。其中，权重属性寄存器的状态是：权重属性寄存器处于待寄存权重属性数据的状态，或者，权重属性寄存器处于寄存完权重属性数据的状态。脉动阵列是按照一定频率有规律地运行的，因此能够在当前时间确定从当前时间起到预设运行时间后，脉动阵列中权重属性寄存器，是处于待寄存权重属性数据的状态，还是寄存完权重属性数据的状态。
在一种可能的实现方式中，若脉动阵列第一列全部的处理引擎存在权重属性数据，则权重属性寄存器处于寄存完权重属性数据的状态；若脉动阵列第一列的全部处理引擎或者部分处理引擎不存在权重属性数据，则权重属性寄存器处于待寄存权重属性数据的状态。
在另一种可能的实现方式中，若脉动阵列第一列的处理引擎存在未被使用过的权重属性数据，则权重属性寄存器处于寄存完权重属性数据的状态；若脉动阵列第一列的处理引擎不存在未被使用过的权重属性数据，则权重属性寄存器处于待寄存权重属性数据的状态。其中，若驻留在任一个处理引擎的权重属性数据与流经该处理引擎的特征映射属性数据进行了计算，则该权重属性数据被使用过；若驻留在任一个处理引擎的权重属性数据未与流经该处理引擎的特征映射属性数据进行计算，则该权重属性数据未被使用过。
例如，若脉动阵列第一列的全部处理引擎或者部分处理引擎不存在权重属性数据，则权重属性寄存器处于待寄存权重属性数据的状态。在脉动阵列第一列全部处理引擎均存在权重属性数据的情况下，若全部处理引擎或者部分处理引擎存在未被使用过的权重属性数据，则权重属性寄存器处于寄存完权重属性数据的状态；若全部处理引擎均存在被使用过的权重属性数据，则权重属性寄存器处于待寄存权重属性数据的状态。
基于预设运行时间后权重属性寄存器的状态可以确定参考状态标识是否满足第一预设条件，从而确定是否可以将权重属性数据加载至脉动阵列。
在示例性实施例中，在步骤303中，参考状态标识满足第一预设条件为：参考状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器处于待寄存权重属性数据的状 态。
存在如下两种可能性会导致权重属性寄存器处于待寄存权重属性数据的状态。第一种情况是：脉动阵列第一列存在全部或者部分处理引擎从未接收过权重属性数据。第二种情况是：脉动阵列第一列全部处理引擎接收过权重属性数据，但全部处理引擎或者部分处理引擎中的权重属性数据与流经处理引擎的特征映射属性数据进行了计算，使得处理引擎中的权重属性数据被使用过。
在脉动阵列第一列存在全部或者部分处理引擎没有权重属性数据，和/或，脉动阵列第一列全部处理引擎的权重属性数据均被使用过的情况下，电子设备可以将存储单元中的权重属性数据加载至脉动阵列。基于这个原理，在参考状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器处于待寄存权重属性数据的状态时，电子设备确定参考状态标识满足第一预设条件，以便于将存储单元存储的权重属性数据读取至脉动阵列，使脉动阵列第一列的所有处理引擎均存在权重属性数据，且全部处理引擎或者部分处理引擎存在未被使用过的权重属性数据。
可以理解的是，在参考状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器处于寄存完权重属性数据的状态时，说明脉动阵列第一列的所有处理引擎均存在权重属性数据，且全部处理引擎或者部分处理引擎存在未被使用过的权重属性数据。这种情况下，电子设备无法将存储单元中的权重属性数据加载至脉动阵列。基于这个原理，电子设备确定参考状态标识不满足第一预设条件，此时，电子设备会屏蔽第一权重读请求。
步骤304，在参考状态标识满足第二预设条件的情况下，响应于第一特征映射读请求将存储单元存储的特征映射属性数据读取至脉动阵列，脉动阵列用于基于权重属性数据和特征映射属性数据进行计算。
其中，步骤304可以在步骤302之后执行。基于预设运行时间后权重属性寄存器的状态可以确定参考状态标识是否满足第二预设条件，从而确定是否可以将特征映射属性数据加载至脉动阵列。
在一些实施例中，基于权重属性数据和特征映射属性数据进行计算，具体包括：按照神经网络模型的结构，确定权重属性数据和特征映射属性数据的关系，从而依据权重属性数据和特征映射属性数据的关系，组织权重属性数据和特征映射属性数据参与神经网络模型的计算，获得计算结果。该计算结果可以是中间计算结果，也可以是神经网络模型最终输出的结果。
在一些实施例中，权重属性数据和特征映射属性数据的关系，可以是将权重属性数据和特征映射属性数据分别作为神经网络模型中特定的函数的输入数据，该函数的输出数据则是基于权重属性数据和特征映射属性数据进行计算获得的计算结果。权重属性数据和特征映射属性数据的关系可以是点积相乘的关系。
在示例性实施例中，在步骤304中，参考状态标识满足第二预设条件为：参考状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器处于寄存完权重属性数据的状态。
若参考状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器处于寄存完权重属性数据的状态，说明脉动阵列第一列的所有处理引擎均有权重属性数据，且全部处理引擎或者部分处理引擎存在未被使用过的权重属性数据，电子设备可以将存储单元中的特征映射属性数据加载至脉动阵列。基于这个原理，在参考状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器处于寄存完权重属性数据的状态时，电子设备确定参考状态标识满足第二预设条件，以便于将存储单元存储的特征映射属性数据读取至脉动阵列，使得脉动阵列第一列的所有处理引擎可以对驻留在处理引擎中的权重属性数据和流经处理引擎的特征映射属性数据进行计算。
可以理解的是，参考状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器处于待寄存权重属性数据的状态时，说明脉动阵列第一列存在全部或者部分处理引擎不 存在权重属性数据，和/或，脉动阵列第一列全部处理引擎的权重属性数据均被使用过。这种情况下，电子设备无法将存储单元中的特征映射属性数据加载至脉动阵列。基于这个原理，电子设备确定参考状态标识不满足第二预设条件，此时，电子设备会屏蔽第一特征映射读请求。
在参考状态标识满足第一预设条件时，可以直接基于第一权重读请求读取权重属性数据，此外，还可以屏蔽第一特征映射读请求。在参考状态标识满足第二预设条件时，可以直接基于第一特征映射读请求读取特征映射属性数据，此外，还可以屏蔽第一权重读请求。通过对参考状态标识进行仲裁处理，有利于构建权重属性数据和特征映射属性数据之间的时序，便于通过脉动阵列基于权重属性数据和特征映射属性数据进行计算。
可选地，在步骤304之前，还包括如下所示的步骤306至步骤307(图3未示出)。
步骤306，获取第一状态标识，第一状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器是否寄存完第设定数量个时钟周期的权重属性数据。
本申请实施例中，可以通过仲裁单元对参考状态标识进行仲裁，在参考状态标识满足第一预设条件的情况下，基于第一权重读请求读取权重属性数据，或者，在参考状态标识不满足第一预设条件的情况下，屏蔽第一权重读请求。
基于此，仲裁单元可以维护一个第一状态寄存器，通过第一状态寄存器来寄存第一状态标识。在任一个时钟周期的第一权重读请求到达仲裁单元时，若该时钟周期为第设定数量个时钟周期，则将第一状态标识置为第三数值，若该时钟周期不为第设定数量个时钟周期，则将第一状态标识置为第四数值。可以理解的是，第一状态标识仅在第设定数量个时钟周期内的数值为第三数值，在其他时钟周期内的数值为第四数值。可选地，第一状态标识可以记为wt_last_beat。
当第一状态标识由第三数值置为第四数值时，表征在从当前时间起的预设运行时间后，权重属性寄存器寄存完第设定数量个时钟周期的权重属性数据。在第一状态标识由第四数值置为第三数值的情况下，表征在从当前时间起的预设运行时间后，权重属性寄存器开始寄存第设定数量个时钟周期的权重属性数据。
本申请实施例不对第三数值和第四数值的大小做限定。示例性地，第三数值为1，第四数值为0。
步骤307，响应于第一状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器寄存完第设定数量个时钟周期的权重属性数据，确定参考状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器处于寄存完权重属性数据的状态。
在第一状态标识由第三数值置为第四数值的情况下，表明预设运行时间后权重属性寄存器寄存完第设定数量个时钟周期的权重属性数据，也就是说，预设运行时间后权重属性寄存器处于寄存完权重属性数据的状态。这种情况下，电子设备将参考状态标识由第一数值置为第二数值。其中，参考状态标识为第一数值时，表明预设运行时间后权重属性寄存器处于待寄存权重属性数据的状态；参考状态标识为第二数值时，表明预设运行时间后权重属性寄存器处于寄存完权重属性数据的状态。本申请实施例不对第一数值和第二数值的大小做限定。示例性地，第一数值为0，第二数值为1。
请参见图4，图4是本申请实施例提供的一种状态标识的更新示意图。由图4可以看出，在第一状态标识由1(即第三数值)置为0(即第四数值)的情况下，参考状态标识由0(即第一数值)置为1(即第二数值)。
在示例性实施例中，该方法还包括步骤308至步骤309(图3未示出)，可选地，步骤308至步骤309可以在步骤307之后执行。
步骤308，获取第二状态标识，第二状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器中的权重属性数据是否和第一个时钟周期的特征映射属性数据进行计算。
任一个时钟周期的特征映射读请求经过仲裁单元之后，在满足第二预设条件的情况下，该特征映射读请求对应的特征映射属性数据经过预设运行时间后，通过脉动阵列与寄存在 权重属性寄存器中的权重属性数据进行计算。基于此，仲裁单元可以维护一个第二状态寄存器，通过第二状态寄存器来寄存第二状态标识。在任一个时钟周期的特征映射读请求到达仲裁单元时，若该时钟周期为第一个时钟周期，则将第二状态标识置为第五数值，若该时钟周期不为第一个时钟周期，则将第二状态标识置为第六数值。可以理解的是，第二状态标识仅在第一个时钟周期内的数值为第五数值，在其他时钟周期内的数值为第六数值。可选地，第二状态标识可以记为fm_update_first_beat。
当第二状态标识由第五数值置为第六数值时，表征在从当前时间起的预设运行时间后，权重属性寄存器中的权重属性数据和第一个时钟周期的特征映射属性数据完成了计算。在第二状态标识由第六数值置为第五数值的情况下，表征权重属性寄存器中的权重属性数据和第一个时钟周期的特征映射属性数据开始进行计算。
本申请实施例不对第五数值和第六数值的大小做限定。示例性地，第五数值为1，第六数值为0。
步骤309，在第二状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器中的权重属性数据和第一个时钟周期的特征映射属性数据进行计算的情况下，确定参考状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器处于待寄存权重属性数据的状态。
在第二状态标识由第五数值置为第六数值的情况下，表明预设运行时间后权重属性寄存器中的权重属性数据和第一个时钟周期的特征映射属性数据完成计算。这种情况下，电子设备将参考状态标识由第二数值置为第一数值。由图4可以看出，在第二状态标识由1(即第五数值)置为0(即第六数值)的情况下，参考状态标识由1(即第二数值)置为0(即第一数值)。
综合上述，参考状态标识的初始值为第一数值，表征在从当前时间起的预设运行时间后，权重属性寄存器处于待寄存权重属性数据的状态。这种情况下，参考状态标识满足第一预设条件，因此，可以响应于第一权重读请求将存储单元存储的权重属性数据读取至脉动阵列，若获取到第一特征映射读请求，则屏蔽第一特征映射读请求，这个过程会持续若干个时钟周期，直至参考状态标识由第一数值置为第二数值。
由于参考状态标识为第二数值时可以表征权重属性寄存器处于寄存完权重属性数据的状态。这种情况下，参考状态标识满足第二预设条件，因此，在一个时钟周期内，可以响应于第一特征映射读请求将存储单元存储的特征映射属性数据读取至脉动阵列，若获取到第一权重读请求，则屏蔽第一权重读请求。该时钟周期后，参考状态标识由第二数值置为第一数值。接下来，执行实现方式A或者实现方式B。
在实现方式A中，参考状态标识为第一数值，在下一个时钟周期内，可以响应于第一权重读请求将存储单元存储的权重属性数据读取至脉动阵列，并屏蔽第一特征映射读请求，该时钟周期后，参考状态标识由第一数值置为第二数值。在接下来的一个时钟周期内，可以响应于第一特征映射读请求将存储单元存储的特征映射属性数据读取至脉动阵列，并屏蔽第一权重读请求，该时钟周期后，参考状态标识由第二数值置为第一数值。重复该过程，直至停止读取。
在实现方式B中，参考状态标识为第一数值。接下来，执行步骤310至步骤311(图3未示出)。其中，步骤310至步骤311可以步骤304之后或者在“参考状态标识由第二数值置为第一数值”之后执行。
步骤310，获取第二权重读请求和第二特征映射读请求，第二权重读请求用于请求从存储单元中读取权重属性数据，第二特征映射读请求用于请求从存储单元中读取特征映射属性数据。
电子设备还可以在任一个时钟周期获取第二权重读请求，第二权重读请求用于读取wt属性数据。电子设备还可以在任一个时钟周期获取第二特征映射读请求，第二特征映射读请求用于读取fm属性数据。其中，电子设备可以同时获取第二权重读请求和第二特征映 射读请求，也可以先获取第二权重读请求再获取第二特征映射读请求，还可以先获取第二特征映射读请求再获取第二权重读请求。
步骤311，基于第二权重读请求将存储单元存储的权重属性数据读取至脉动阵列，基于第二特征映射读请求将存储单元存储的特征映射属性数据读取至脉动阵列，权重属性数据的读延迟和特征映射属性数据的读延迟为预设运行时间。
由于权重属性数据的读延迟和特征映射属性数据的读延迟均为预设运行时间，也就是说，权重属性数据的读延迟和特征映射属性数据的读延迟相等。因此，每将一个时钟周期的权重属性数据加载至脉动阵列，对应的，会有一个时钟周期的特征映射属性数据流入脉动阵列，并与驻留在脉动阵列的权重属性数据进行计算，使得权重属性数据和特征映射属性数据的时序关系得以维持。基于此，可以无需判断参考状态标识满足第一预设条件或者第二预设条件，直接基于第二权重读请求将存储单元存储的权重属性数据读取至脉动阵列，并基于第二特征映射读请求将存储单元存储的特征映射属性数据读取至脉动阵列。
由于在权重属性数据的读延迟和特征映射属性数据的读延迟相等的情况下，可以维持权重属性数据和特征映射属性数据的时序关系，因此，不需要引入队列来寄存数据，减少了队列所需的寄存资源，有利于降低芯片面积。此外，无需判断参考状态标识满足第一预设条件或者第二预设条件，直接基于第二权重读请求或者第二特征映射读请求读取对应数据，可以实现权重读请求、特征映射读请求之间的高效切换，加快数据读取效率，降低运算时间。
本申请实施例中，第一权重读请求包括至少一个第一权重子请求，存储单元包括至少一个第一存储块。例如，第一权重读请求包括4个第一权重子请求，分别为记为req0至req3，存储单元包括4个第一存储块，分别记为bg0至bg3。
在步骤303中，“响应于第一权重读请求将存储单元存储的权重属性数据读取至脉动阵列”包括如下所示的步骤3031至步骤3032(图3未示出)。
步骤3031，对于任一个第一权重子请求，在任一个第一权重子请求为有效请求的情况下，确定任一个第一权重子请求对应的第一存储块，从任一个第一权重子请求对应的第一存储块中读取任一个第一权重子请求对应的权重属性数据。
电子设备可以直接将任一个第一权重子请求确定为有效(Valid)请求，也可以将任一个第一权重子请求与参考第一权重子请求进行对比，通过对比结果来确定任一个第一权重子请求是否为有效请求。
在示例性实施例中，步骤3031中“确定任一个第一权重子请求为有效请求”包括：从任一个第一权重子请求中提取任一个第一权重子请求对应的第一存储块的地址；响应于任一个第一权重子请求对应的第一存储块的地址与参考第一权重子请求对应的第一存储块的地址不同，确定任一个第一权重子请求为有效请求，参考第一权重子请求为多个第一权重子请求中除任一个第一权重子请求之外的至少一个第一权重子请求。
任一个第一权重子请求包括标识位和地址(Address，Addr)，其中，标识位用于表征第一权重子请求为有效请求，地址是第一权重子请求对应的数据所在的存储地址。
本申请实施例中，需要从存储单元中读取任一个第一权重子请求对应的数据，由于存储单元包括至少一个第一存储块，因此，任一个第一权重子请求包括第一存储块的地址，以实现从该第一存储块中读取该第一权重子请求对应的权重属性数据。
可以理解的是，任一个第一权重子请求对应一个第一存储块的地址，任两个第一权重子请求可能对应同一个第一存储块的地址，也可能对应不同的第一存储块的地址。基于此，需要判断两个第一权重子请求是否对应同一个第一存储块的地址。
可选地，由于任一个第一权重子请求包括第一存储块的地址，因此，可以从该第一权重子请求中提取出对应第一存储块的地址。将任一个第一权重子请求对应的第一存储块的地址与参考第一权重子请求对应的第一存储块的地址进行比较。若比较结果为两个地址不同，则确定任一个第一权重子请求为有效请求；若比较结果为两个地址相同，则确定任一 个第一权重子请求为无效请求。
参考第一权重子请求的数量为至少一个。在存在至少两个参考第一权重子请求的情况下，若任一个第一权重子请求对应的第一存储块的地址与各个参考第一权重子请求对应的第一存储块的地址不同，则确定任一个第一权重子请求为无效请求；若存在参考第一权重子请求对应的第一存储块的地址与任一个第一权重子请求对应的第一存储块的地址相同，则确定任一个第一权重子请求为无效请求。
本申请实施例不对参考第一权重子请求的确定方式做限定。在示例性实施例中，可以将多个第一权重子请求中除任一个第一权重子请求之外的各个第一权重子请求作为参考第一权重子请求，或者，可以将多个第一权重子请求中位于任一个第一权重子请求之前(或者之后)的各个第一权重子请求作为参考第一权重子请求。
请参见图5，图5是本申请实施例提供的一种子请求是否有效的判断示意图。本申请实施例中，第一权重读请求包括4个第一权重子请求，分别为记为子请求0至子请求3。对于任一个第一权重子请求，该第一权重子请求包括用于表征该第一权重子请求有效的标识位和用于存储该第一权重子请求对应的数据的地址。任一个第一权重子请求包括的地址中的全部或者部分为第一存储块的地址。例如，图5示出了子请求0至子请求3均包括表征“有效”的标识位和地址，且地址的部分为对应第一存储块的地址。
对于子请求0，电子设备可以直接判断子请求0是否有效。例如，电子设备直接确定子请求0为有效请求。
对于子请求1，电子设备可以将子请求0对应的第一存储块的地址和子请求1对应的第一存储块的地址进行比较，在比较结果为不同(其中，“！＝”为计算机中的运算符号，表征两个变量不相等)，且子请求1的标识位表征“有效”的情况下，通过将比较结果和标识位进行逻辑与运算，得到子请求1有效。其中，对于逻辑与运算，在两个操作数均为真的情况下确定运算结果为真。在本申请实施例中，当比较结果为不同时，比较结果对应的操作数表征子请求1“有效”，相当于真，此外，子请求1的标识位表征子请求1“有效”，相当于真，因此，运算结果为真，即运算结果为子请求1“有效”。
可以理解的是，在比较结果为相同，且子请求1的标识位表征子请求1“有效”的情况下，通过将比较结果和标识位进行逻辑与运算，得到子请求1无效。其中，比较结果为相同时，比较结果对应的操作数表征子请求1“无效”。
对于子请求2，基于与子请求1相类似的原理，可以将子请求2对应的第一存储块的地址和子请求0、1对应的第一存储块的地址进行比较，在比较结果为不同，且子请求2的标识位表征“有效”的情况下，通过将比较结果和标识位进行逻辑与运算，得到子请求2有效。在比较结果为存在相同，且子请求2的标识位表征子请求2“有效”的情况下，通过将比较结果和标识位进行逻辑与运算，得到子请求2无效。
对于子请求3，基于与子请求1相类似的原理，可以将子请求3对应的第一存储块的地址和子请求0、1、2对应的第一存储块的地址进行比较，在比较结果为不同，且子请求3的标识位表征“有效”的情况下，通过将比较结果和标识位进行逻辑与运算，得到子请求3有效。在比较结果为存在相同，且子请求3的标识位表征子请求3“有效”的情况下，通过将比较结果和标识位进行逻辑与运算，得到子请求3无效。
可选地，对于任一个第一权重子请求，在该第一权重子请求的标识位为第七数值的情况下，确定第一权重子请求的标识位表征“有效”，在该第一权重子请求的标识位为第八数值的情况下，确定第一权重子请求的标识位表征“无效”。本申请实施例不对第七数值、第八数值做限定，在示例性实施例中，第七数值为1，第八数值为0。
由于任一个第一权重子请求包括第一存储块的地址，因此，基于任一个第一权重子请求包括的第一存储块的地址，可以确定该第一权重子请求对应的第一存储块，并从该第一存储块中读取该第一权重子请求对应的数据。
在示例性实施例中，任一个第一存储块包括至少一个第二存储块。例如，第一存储块 0包括第二存储块0和1，第一存储块1包括第二存储块0和1，第一存储块2包括第二存储块0和1，第一存储块3包括第二存储块0和1。由于第一存储块包括至少一个第二存储块，因此，可以将第二存储块记为存储模块(Bank)，将第一存储块记为存储模块组(Bank Group)。
步骤3031中“从任一个第一权重子请求对应的第一存储块中读取任一个第一权重子请求对应的权重属性数据”，包括：基于任一个第一权重子请求确定任一个第一权重子请求对应的第二存储块；从任一个第一权重子请求对应的第二存储块中读取任一个第一权重子请求对应的权重属性数据。
由于任一个第一权重子请求包括第一存储块的地址，而第一存储块包括至少一个第二存储块，因此，任一个第一权重子请求可以包括第二存储块的地址。可以基于任一个第一权重子请求包括的第二存储块的地址，确定该第一权重子请求对应的第二存储块，并从该第二存储块中读取该第一权重子请求对应的权重属性数据。
步骤3032，将各个第一权重子请求对应的权重属性数据送入脉动阵列。
由于电子设备需要判断第一权重读请求中的各个第一权重子请求是否为有效请求，并在第一权重子请求为有效请求的情况下，才可以读取第一权重子请求对应的数据，因此，各个第一权重子请求对应的数据的读取完成时间存在差异。可以通过收集单元收集各个第一权重子请求对应的数据。当收集单元收集到各个第一权重子请求对应的数据之后，根据导出命令(例如，reg命令)，将各个第一权重子请求对应的数据作为第一权重读请求对应的权重属性数据导出存储单元，从而将权重属性数据送入脉动阵列。
请参见图6，图6是本申请实施例提供的一种数据收集过程的示意图。本申请实施例中，第一权重读请求包括四个第一权重子请求，分别为子请求0至3。在T0时刻，收集单元未收集到任一个第一权重子请求对应的数据，在T1时刻，收集单元收集到子请求0和1对应的数据，在T2时刻，收集单元收集到子请求0至2对应的数据，在T3时刻，收集单元收集到子请求0至3对应的数据。这种情况下，根据导出命令，将子请求0至3对应的数据作为第一权重读请求对应的权重属性数据导出存储单元。
需要说明的是，第一特征映射读请求包括至少一个第一特征映射子请求，第二权重读请求包括至少一个第二权重子请求，第二特征映射读请求包括至少一个第二特征映射子请求。有关“响应于第一特征映射读请求将存储单元存储的特征映射属性数据读取至脉动阵列”、“基于第二权重读请求将存储单元存储的权重属性数据读取至脉动阵列”、“基于第二特征映射读请求将存储单元存储的特征映射属性数据读取至脉动阵列”的实现方式，可以见上文有关步骤3031至步骤3032的描述，二者实现方式相类似，在此不再赘述。
在示例性实施例中，该方法还包括步骤312至步骤313(图3未示出)。
步骤312，获取写请求。
电子设备可以在任一个时钟周期获取写请求，写请求用于将权重属性数据或者特征映射属性数据写入存储单元中。可以理解的是，写请求可以是一种基于直接存储器访问(Direct Memory Access，DMA)的数据搬移写(Write，wr)请求，用于将其他存储中的数据搬移至存储单元中，因此，写请求可以记为dma_wr请求。
步骤313，基于写请求将对应的权重属性数据或者特征映射属性数据写入存储单元中。
可选地，写请求包括至少一个第三子请求，存储单元包括至少一个第一存储块。例如，写请求包括四个第三子请求，存储单元包括四个第一存储块。
这种情况下，步骤313包括：对于任一个第三子请求，确定任一个第三子请求对应的第一存储块；基于任一个第三子请求将任一个第三子请求对应的数据写入任一个第三子请求对应的第一存储块。
本申请实施例中，任一个第三子请求包括第一存储块的地址，因此，基于任一个第三子请求包括的第一存储块的地址，可以确定该第三子请求对应的第一存储块，并将该第三子请求对应的权重属性数据或者特征映射属性数据写入该第三子请求对应的第一存储块。
在示例性实施例中，任一个第一存储块包括至少一个第二存储块。这种情况下，“基于任一个第三子请求将任一个第三子请求对应的数据写入任一个第三子请求对应的第一存储块”，包括：基于任一个第三子请求确定任一个第三子请求对应的第二存储块；将任一个第三子请求对应的数据写入任一个第三子请求对应的第二存储块。
由于任一个第三子请求包括第一存储块的地址，而第一存储块包括至少一个第二存储块，因此，任一个第三子请求可以包括第二存储块的地址。可以基于任一个第三子请求包括的第二存储块的地址，确定该第三子请求对应的第二存储块，并将该第三子请求对应的数据写入该第三子请求对应的第二存储块。
由于电子设备既可以接收写请求，也可以接收特征映射读请求，还可以接收权重读请求，因此，可以通过调度器协调各种请求的优先级。可选地，调度器为严格优先级(Strict Priority，SP)调度器。
由于权重属性数据和特征映射属性数据具有一定的时序关系，一般情况下，在权重属性数据加载至脉动阵列第一列处理引擎之后，需要先将特征映射属性数据加载至脉动阵列，以便于对流经脉动阵列的特征映射属性数据和驻留在脉动阵列的权重属性数据进行计算之后，才可以再次将权重属性数据加载至脉动阵列。基于上述内容，(第一或者第二)权重读请求的优先级低于(第一或者第二)特征映射读请求的优先级，其中，写请求的优先级可以高于权重读请求的优先级，也可以低于权重读请求的优先级，可以高于特征映射读请求的优先级，也可以低于特征映射读请求的优先级。示例性地，特征映射读请求的优先级高于权重读请求的优先级，权重读请求的优先级高于写请求的优先级。
通过调度器协调各种请求的优先级，使得数据能够有序的读取和写入，实现多请求之间的高效切换，提高数据处理效率。
需要说明的是，本申请所涉及的信息(包括但不限于用户设备信息、用户个人信息等)、数据(包括但不限于用于分析的数据、存储的数据、展示的数据等)以及信号，均为经用户授权或者经过各方充分授权的，且相关数据的收集、使用和处理需要遵守相关地区的相关法律法规和标准。例如，本申请中涉及到的第一数据、第二数据、第三数据等都是在充分授权的情况下获取的。
上述方法通过参考状态标识表征脉动阵列中权重属性寄存器的状态。在参考状态标识满足第一预设条件的情况下，响应于第一权重读请求将存储单元存储的权重属性数据读取至脉动阵列；在参考状态标识满足第二预设条件的情况下，响应于第一特征映射读请求将存储单元存储的特征映射属性数据读取至脉动阵列。相对于队列所需的寄存资源来说，参考状态标识所需的寄存资源更少。该方法可应用于芯片中，由于寄存资源越少芯片面积越小，因此使芯片具备了降低芯片面积的条件。
上述从方法步骤的角度阐述了本申请实施例的数据读取方法，下面来系统全面的阐述。请参见图7，图7是本申请实施例提供的一种存储系统的架构图。其中，该存储系统包括冲突检测单元、散列单元、至少一个处理块和收集单元，任一个处理块包括仲裁单元、至少一个第二存储块和选择单元。
需要说明的是，图7未示出存储单元和第一存储块。本申请实施例中，一个第一存储块包括一个处理块中的各个第二存储块，即一个处理块对应一个第一存储块，存储单元包括各个第一存储块。如图7中，存储单元包括处理块0对应的第一存储块、处理块1对应的第一存储块、处理块2对应的第一存储块和处理块3对应的第一存储块。处理块0对应的第一存储块包括处理块0中的第二存储块0和1；处理块1对应的第一存储块包括处理块1中的第二存储块0和1；处理块2对应的第一存储块包括处理块2中的第二存储块0和1；处理块3对应的第一存储块包括处理块3中的第二存储块0和1。
本申请实施例中，电子设备可以基于特征映射读请求，从存储单元中读取特征映射属性数据，也可以基于权重读请求，从存储单元中读取权重属性数据。本申请实施例针对特征映射读请求的处理方式和针对权重读请求的处理方式相类似，因此，下面以特征映射读 请求为例，阐述本申请实施例针对特征映射读请求的处理方式。
电子设备获取到特征映射读请求(对应第一特征映射读请求和第二特征映射读请求)之后，通过冲突检测单元对特征映射读请求进行冲突检测，其中，冲突检测的原理如图5所示。本申请实施例中，特征映射读请求包括子请求0至子请求3。对于子请求0，直接确定子请求0有效；对于子请求1，当子请求0对应的第一存储块的地址和子请求1对应的第一存储块的地址不同时，确定子请求1有效，否则，确定子请求1无效；对于子请求2，当子请求0、1对应的第一存储块的地址和子请求2对应的第一存储块的地址均不同时，确定子请求2有效，否则，确定子请求2无效；对于子请求3，当子请求0至2对应的第一存储块的地址和子请求3对应的第一存储块的地址均不同时，确定子请求3有效，否则，确定子请求3无效。
在对特征映射读请求进行冲突检测之后，可以确定特征映射读请求包括的各个子请求是否有效。对于任一个子请求，若该子请求有效，则通过散列单元基于该子请求对应的第一存储块的地址，确定该子请求对应的第一存储块，并将该子请求对应的第一存储块所在的处理块的请求通路置为有效，以便于该子请求能够到达对应的第一存储块；若该子请求无效，则通过散列单元将该子请求对应的第一存储块所在的处理块的请求通路置为无效，防止该子请求到达对应的第一存储块。
例如，子请求0对应第一存储块0，而处理块0包括第一存储块0。若子请求0有效，则通过散列单元将处理块0的请求通路置为有效，以便于子请求0到达第一存储块0；若子请求0无效，则通过散列单元将处理块0的请求通路置为无效，防止子请求0到达第一存储块0。
本申请实施例中，该存储系统包括至少一个处理块，一个处理块包括仲裁单元、第一存储块(图中未示出)和选择单元，第一存储块包括至少一个第二存储块。其中，仲裁单元的结构示意图可以参见图8。
对于特征映射读请求的任一个子请求，将该子请求输入对应的处理块之后，该子请求先通过仲裁单元进行仲裁。如图8所示，仲裁单元配置了参考状态标识的更新逻辑，该更新逻辑如图4所示。
具体来说，参考状态标识、第一状态标识和第二状态标识的初始值均为0。在第一个时钟周期，电子设备可以从存储单元中读取权重属性数据，经过预设运行时间后加载至脉动阵列的权重属性寄存器中。若预设运行时间后权重属性寄存器处于待寄存权重属性数据的状态，则在第二个时钟周期，电子设备还可以从存储单元中读取权重属性数据，经过预设运行时间后加载至脉动阵列的权重属性寄存器中。这种加载方式会持续若干个时钟周期，直至预设运行时间后权重属性寄存器处于寄存完权重属性数据的状态，这时的时钟周期可以记为第设定数量个时钟周期。也就是说，在第设定数量个时钟周期，电子设备从存储单元中读取权重属性数据，经过预设运行时间后加载至脉动阵列的权重属性寄存器中，此时，权重属性寄存器处于寄存完权重属性数据的状态。
在第设定数量个时钟周期对应的权重读请求的子请求流入仲裁单元时，可以将第一状态标识由0置为1，在该子请求流出仲裁单元时，可以将第一状态标识由1置为0。当第一状态标识由1置为0时，可以表明预设运行时间后权重属性寄存器寄存完第设定数量个时钟周期的权重属性数据，此时，将参考状态标识由0置为1。
当权重属性寄存器寄存完第设定数量个时钟周期的权重属性数据时，相当于权重属性寄存器处于寄存完权重属性数据的状态。这种情况下，电子设备可以在任一个时钟周期，从存储单元中读取特征映射属性数据，经过预设运行时间后，特征映射属性数据流入脉动阵列并与权重属性寄存器中的权重属性数据进行计算。其中，这个时钟周期是读取特征映射属性数据的第一个时钟周期。
在第一个时钟周期对应的特征映射读请求的子请求流入仲裁单元时，可以将第二状态标识由0置为1，在该子请求流出仲裁单元时，可以将第二状态标识由1置为0。当第二 状态标识由1置为0时，可以表明预设运行时间后权重属性寄存器的权重属性数据和第一个时钟周期的特征映射属性数据进行计算，此时，将参考状态标识由1置为0。
综上可知，参考状态标识是先由0置为1，再由1置为0。通过仲裁单元对特征映射读请求的任一个子请求进行仲裁时，可以获取参考状态标识。若参考状态标识等于1，则确定该子请求满足第二预设条件，基于子请求携带的地址确定子请求所属的第二存储块，并通过调度器将该子请求送入对应的第二存储块；若参考状态标识等于0，则确定该子请求不满足第二预设条件，屏蔽该子请求。例如，若该子请求满足第二预设条件且子请求属于第二存储块0，则通过调度器将子请求送入第二存储块0；若该子请求满足第二预设条件且子请求属于第二存储块1，则通过调度器将子请求送入第二存储块1。
接着，通过选择单元，基于特征映射读请求的任一个子请求，从该子请求对应的第二存储块中读取该子请求对应的数据。通过收集单元收集各个子请求对应的数据，该收集过程可以见图6的描述，在此不再赘述。当收集单元收集到特征映射读请求的各个子请求对应的数据之后，相当于收集到特征映射读请求对应的特征映射属性数据。之后，通过导出命令将特征映射属性数据输入脉动阵列。
可以理解的是，通过仲裁单元对一个时钟周期的特征映射读请求的各个子请求进行仲裁时，各个子请求的仲裁结果相同。基于此，可以通过仲裁单元对一个时钟周期的特征映射读请求进行仲裁之后，再将该特征映射读请求输入冲突检测单元进行上述处理。这种情况下，可以在处理块通过仲裁单元对该特征映射读请求的各个子请求进行仲裁，也可以处理块不包括仲裁单元。也就是说，可以通过散列单元直接将特征映射读请求的各个子请求送入对应的第二存储块，或者，通过散列单元直接将特征映射读请求的各个子请求送入对应的调度器，通过调度器的调度之后送入对应的第二存储块。
按照上述特征映射读请求的处理方式，可以对权重读请求进行类似的处理。其中，通过仲裁单元对权重读请求的任一个子请求进行仲裁时，若参考状态标识等于0，则确定该子请求满足第一预设条件，基于子请求携带的地址确定子请求所属的第二存储块，并通过调度器将该子请求送入对应的第二存储块；若参考状态标识等于1，则确定该子请求不满足第一预设条件，屏蔽该子请求。
通常情况下，通过仲裁单元会在若干个时钟周期的每一个时钟周期内均确定权重读请求(对应第一权重读请求)的子请求满足第一预设条件。随着时间的流逝，当通过仲裁单元确定权重读请求的子请求不满足第一预设条件时，可以通过仲裁单元确定特征映射读请求(对应第一特征映射读请求)的子请求满足第二预设条件。一旦通过仲裁单元确定特征映射读请求的子请求满足第二预设条件，在权重属性数据的读延迟和特征映射属性数据的读延迟相同的情况下，后续权重属性数据的读取、特征映射属性数据的读取均可以不经过仲裁单元的仲裁，也即是后续权重读请求(对应第二权重读请求)的子请求、特征映射读请求(对应第二特征映射读请求)的子请求均可以不经过仲裁单元的仲裁。这是由于权重属性数据的读延迟和特征映射属性数据的读延迟均为参考时间周期，因此，每将一个时钟周期的权重属性数据加载至脉动阵列，对应的，会有一个时钟周期的特征映射属性数据流入脉动阵列，并与驻留在脉动阵列的权重属性数据进行计算，使得权重属性数据和特征映射属性数据的时序关系得以维持，因此，无需经过仲裁单元的仲裁。
本申请实施例中，电子设备可以基于写请求，将特征映射属性数据、权重属性数据写入存储单元，下面介绍写请求的处理方式。
写请求包括至少一个子请求(对应第三子请求)。对于任一个子请求，通过散列单元基于该子请求对应的第一存储块的地址，确定该子请求对应的第一存储块，并将该子请求对应的第一存储块所在处理块的请求通路置为有效，以便于该子请求能够到达对应的第一存储块；若该子请求无效，则通过散列单元将该子请求对应的第一存储块所在处理块的请求通路置为无效，防止该子请求到达对应的第一存储块。可以基于子请求携带的地址确定子请求所属的第二存储块，并通过调度器将该子请求送入对应的第二存储块，以将该子请 求对应的数据写入第二存储块。
由于调度器可以接收特征映射读请求的子请求、权重读请求的子请求以及写请求的子请求，因此，可以配置各种子请求的优先级。可选地，特征映射读请求的子请求的优先级高于权重读请求的子请求的优先级，权重读请求的子请求的优先级高于写请求的子请求的优先级。调度器基于各种子请求的优先级，有序的将各种子请求送入第二存储块。
本申请实施例中，通过仲裁单元基于参考状态标识确定特征映射读请求的子请求是否满足第二预设条件或者权重读请求的子请求是否满足第一预设条件，当满足条件时，从第二存储块读取子请求对应的数据。相对于队列所需的寄存资源来说，参考状态标识所需的寄存资源更少，有利于降低芯片面积。
例如，针对读延迟为6，读数据宽度为2千比特(Kilo-Bit，kb)的访存系统。相关技术中，需要设置两个深度为6、宽度为2kb的队列，其中一个队列用于寄存权重属性数据，另一个队列用于寄存特征映射属性数据，且这两个队列需要消耗24kb的寄存器。相对于相关技术需要的芯片面积来说，本申请实施例所需的芯片面积可减少29491.2平方微米(Square Micron，um2)。
此外，在权重读请求的子请求满足第一预设条件或者特征映射读请求的子请求满足第二预设条件时可以直接读取对应的数据，在子请求不满足条件时屏蔽该子请求。通过仲裁单元对子请求进行仲裁处理，有利于构建权重属性数据和特征映射属性数据之间的时序。一旦通过仲裁单元确定特征映射读请求的子请求满足第二预设条件，在权重属性数据的读延迟和特征映射属性数据的读延迟相同的情况下，后续权重属性数据的读取、特征映射属性数据的读取均可以不经过仲裁单元的仲裁，直接读取对应的数据，且权重属性数据和特征映射属性数据之间的时序也能够得以维持。基于上述内容，本申请实施例能够实现多请求间高效切换，有利于提高数据的读取效率。
请参见图12，图12是本申请实施例提供的另一种存储系统的架构图。该存储系统包括处理单元1201，还包括分别与处理单元1201连接的存储单元1202和脉动阵列1203。
存储单元1202，用于存储权重属性数据和特征映射属性数据。
处理单元1201，用于获取第一权重读请求和第一特征映射读请求，第一权重读请求用于请求从存储单元中读取权重属性数据，第一特征映射读请求用于请求从存储单元中读取特征映射属性数据。
处理单元1201，还用于获取参考状态标识，参考状态标识用于表征在从当前时间起的预设运行时间后，脉动阵列1203中权重属性寄存器的状态，权重属性寄存器用于寄存权重属性数据。
处理单元1201，还用于在参考状态标识满足第一预设条件的情况下，响应于第一权重读请求将存储单元存储的权重属性数据读取至脉动阵列1203。
处理单元1201，还用于在参考状态标识满足第二预设条件的情况下，响应于第一特征映射读请求将存储单元存储的特征映射属性数据读取至脉动阵列1203；
脉动阵列1203用于基于权重属性数据和特征映射属性数据进行计算。
在一种可能的实现方式中，处理单元1201包括第一状态寄存器、参考状态寄存器和确定单元；
第一状态寄存器，用于寄存第一状态标识，第一状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器是否寄存完第设定数量个时钟周期的权重属性数据；
参考状态寄存器，用于寄存参考状态标识；
确定单元，用于获取第一状态标识；在第一状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器寄存完第设定数量个时钟周期的权重属性数据的情况下，确定参考状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器处于寄存完权重属性数据的状态，参考状态标识满足第二预设条件为：参考状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器处于寄存完权重属性数据的状态。
在一种可能的实现方式中，处理单元1201包括第二状态寄存器、参考状态寄存器和确定单元；
第二状态寄存器，用于寄存第二状态标识，第二状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器中的权重属性数据是否和第一个时钟周期的特征映射属性数据进行计算；
参考状态寄存器，用于寄存参考状态标识；
确定单元，用于获取第二状态标识；在第二状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器中的权重属性数据和第一个时钟周期的特征映射属性数据进行计算的情况下，确定参考状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器处于待寄存权重属性数据的状态，参考状态标识满足第一预设条件为：参考状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器处于待寄存权重属性数据的状态。
在一种可能的实现方式中，处理单元1201，还用于获取第二权重读请求和第二特征映射读请求，第二权重读请求用于请求从存储单元中读取权重属性数据，第二特征映射读请求用于请求从存储单元中读取特征映射属性数据；
处理单元1201，还用于基于第二权重读请求将存储单元存储的权重属性数据读取至脉动阵列1203；
处理单元1201，还用于基于第二特征映射读请求将存储单元存储的特征映射属性数据读取至脉动阵列1203，权重属性数据的读延迟和特征映射属性数据的读延迟为预设运行时间。
在一种可能的实现方式中，处理单元1201包括散列单元、读取单元和收集单元，存储单元1202包括至少一个第一存储块；
任一个第一存储块，用于存储权重属性数据和特征映射属性数据；
散列单元，用于对于任一个第一权重子请求，在任一个第一权重子请求为有效请求的情况下，确定任一个第一权重子请求对应的第一存储块，第一权重读请求包括至少一个第一权重子请求；
读取单元，用于从任一个第一权重子请求对应的第一存储块中读取任一个第一权重子请求对应的权重属性数据；
收集单元，用于收集各个第一权重子请求对应的权重属性数据，并将各个第一权重子请求对应的权重属性数据送入脉动阵列1203。
在一种可能的实现方式中，系统还包括冲突检测单元；
冲突检测单元，用于从任一个第一权重子请求中提取任一个第一权重子请求对应的第一存储块的地址；
冲突检测单元，还用于响应于任一个第一权重子请求对应的第一存储块的地址与参考第一权重子请求对应的第一存储块的地址不同，确定任一个第一权重子请求为有效请求，参考第一权重子请求为多个第一权重子请求中除任一个第一权重子请求之外的至少一个第一权重子请求。
在一种可能的实现方式中，任一个第一存储块包括至少一个第二存储块；
任一个第二存储块，用于存储权重属性数据和特征映射属性数据；
读取单元，用于确定任一个第一权重子请求对应的第二存储块；从任一个第一权重子请求对应的第二存储块中读取任一个第一权重子请求对应的权重属性数据。
在一种可能的实现方式中，处理单元1201，还用于获取写请求，写请求用于将权重属性数据或者特征映射属性数据写入存储单元中；将写请求对应的权重属性数据或者特征映射属性数据写入存储单元中。
在一种可能的实现方式中，处理单元1201包括散列单元和写入单元，存储单元1202包括至少一个第一存储块；
散列单元，用于对于任一个第三子请求，确定任一个第三子请求对应的第一存储块， 写请求包括至少一个第三子请求；
写入单元，用于将任一个第三子请求对应的权重属性数据或者特征映射属性数据写入任一个第三子请求对应的第一存储块。
上述第一状态寄存器的功能、第二状态寄存器的功能、参考状态寄存器的功能和确定单元的功能可通过图7所示的仲裁单元实现。上述散列单元的功能可通过图7所示的散列单元实现。上述读取单元的功能可通过图8所示的调度器和选择单元实现。上述收集单元的功能可通过图7所示的收集单元实现。上述冲突检测单元的功能可通过图7所示的冲突检测单元实现。上述第二存储块的功能可通过图7所示的第二存储块实现。上述写入单元的功能可通过图8所示的调度器实现。
应理解的是，上述图12提供的系统与方法实施例属于同一构思，其具体实现过程详见方法实施例，此外，图12提供的系统中与图7、图8相对应的内容可以参见图7、图8的描述，这里不再赘述。
上述系统通过参考状态标识表征脉动阵列中权重属性寄存器的状态。在参考状态标识满足第一预设条件的情况下，响应于第一权重读请求将存储单元存储的权重属性数据读取至脉动阵列；在参考状态标识满足第二预设条件的情况下，响应于第一特征映射读请求将存储单元存储的特征映射属性数据读取至脉动阵列。相对于队列所需的寄存资源来说，参考状态标识所需的寄存资源更少。该系统可应用于芯片中，由于寄存资源越少芯片面积越小，因此使芯片具备了降低芯片面积的条件。
图9所示为本申请实施例提供的一种数据读取装置的结构示意图，如图9所示，该装置包括：
获取模块901，用于获取第一权重读请求和第一特征映射读请求，第一权重读请求用于请求从存储单元中读取权重属性数据，第一特征映射读请求用于请求从存储单元中读取特征映射属性数据；
获取模块901，还用于获取参考状态标识，参考状态标识用于表征在从当前时间起的预设运行时间后，脉动阵列中权重属性寄存器的状态，权重属性寄存器用于寄存权重属性数据；
读取模块902，用于在参考状态标识满足第一预设条件的情况下，响应于第一权重读请求将存储单元存储的权重属性数据读取至脉动阵列；
读取模块902，还用于在参考状态标识满足第二预设条件的情况下，响应于第一特征映射读请求将存储单元存储的特征映射属性数据读取至脉动阵列，脉动阵列用于基于权重属性数据和特征映射属性数据进行计算。
在一种可能的实现方式中，参考状态标识满足第一预设条件为：参考状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器处于待寄存权重属性数据的状态；
参考状态标识满足第二预设条件为：参考状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器处于寄存完权重属性数据的状态。
在一种可能的实现方式中，获取模块901，还用于获取第一状态标识，第一状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器是否寄存完第设定数量个时钟周期的权重属性数据；
装置还包括：
确定模块，用于在第一状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器寄存完第设定数量个时钟周期的权重属性数据的情况下，确定参考状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器处于寄存完权重属性数据的状态。
在一种可能的实现方式中，获取模块901，还用于获取第二状态标识，第二状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器中的权重属性数据是否和第一个时钟周期的特征映射属性数据进行计算；
装置还包括：
确定模块，用于在第二状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器中的权重属性数据和第一个时钟周期的特征映射属性数据进行计算的情况下，确定参考状态标识表征在从当前时间起的预设运行时间后，权重属性寄存器处于待寄存权重属性数据的状态。
在一种可能的实现方式中，获取模块901，还用于获取第二权重读请求和第二特征映射读请求，第二权重读请求用于请求从存储单元中读取权重属性数据，第二特征映射读请求用于请求从存储单元中读取特征映射属性数据；
读取模块902，还用于基于第二权重读请求将存储单元存储的权重属性数据读取至脉动阵列；基于第二特征映射读请求将存储单元存储的特征映射属性数据读取至脉动阵列，权重属性数据的读延迟和特征映射属性数据的读延迟为预设运行时间。
在一种可能的实现方式中，第一权重读请求包括至少一个第一权重子请求，存储单元包括至少一个第一存储块；
读取模块902，用于对于任一个第一权重子请求，在任一个第一权重子请求为有效请求的情况下，确定任一个第一权重子请求对应的第一存储块，从任一个第一权重子请求对应的第一存储块中读取任一个第一权重子请求对应的权重属性数据；将各个第一权重子请求对应的权重属性数据送入脉动阵列。
在一种可能的实现方式中，装置还包括：
提取模块，用于从任一个第一权重子请求中提取任一个第一权重子请求对应的第一存储块的地址；
确定模块，用于响应于任一个第一权重子请求对应的第一存储块的地址与参考第一权重子请求对应的第一存储块的地址不同，确定任一个第一权重子请求为有效请求，参考第一权重子请求为多个第一权重子请求中除任一个第一权重子请求之外的第一权重子请求。
在一种可能的实现方式中，任一个第一存储块包括至少一个第二存储块；
读取模块902，用于确定任一个第一权重子请求对应的第二存储块；从任一个第一权重子请求对应的第二存储块中读取任一个第一权重子请求对应的权重属性数据。
在一种可能的实现方式中，获取模块901，还用于获取写请求，写请求用于将第三数据写入存储单元中，第三数据为权重属性数据或者特征映射属性数据；
装置还包括：
写入模块，用于将写请求对应的权重属性数据或者特征映射属性数据写入存储单元中。
在一种可能的实现方式中，写请求包括至少一个第三子请求，存储单元包括至少一个第一存储块；
写入模块，用于对于任一个第三子请求，确定任一个第三子请求对应的第一存储块；将任一个第三子请求对应的权重属性数据或者特征映射属性数据写入任一个第三子请求对应的第一存储块。
上述装置通过参考状态标识表征脉动阵列中权重属性寄存器的状态。在参考状态标识满足第一预设条件的情况下，响应于第一权重读请求将存储单元存储的权重属性数据读取至脉动阵列；在参考状态标识满足第二预设条件的情况下，响应于第一特征映射读请求将存储单元存储的特征映射属性数据读取至脉动阵列。相对于队列所需的寄存资源来说，参考状态标识所需的寄存资源更少。该装置可应用于芯片中，由于寄存资源越少芯片面积越小，因此使芯片具备了降低芯片面积的条件。
应理解的是，上述图9提供的装置在实现其功能时，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将设备的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述实施例提供的装置与方法实施例属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。
图10示出了本申请一个示例性实施例提供的终端设备1000的结构框图。该终端设备 1000包括有：处理器1001和存储器1002。
处理器1001可以包括一个或多个处理核心，比如4核心处理器、8核心处理器等。处理器1001可以采用DSP(Digital Signal Processing，数字信号处理)、FPGA(Field-Programmable Gate Array，现场可编程门阵列)、PLA(Programmable Logic Array，可编程逻辑阵列)中的至少一种硬件形式来实现。处理器1001也可以包括主处理器和协处理器，主处理器是用于对在唤醒状态下的数据进行处理的处理器，也称CPU(Central Processing Unit，中央处理器)；协处理器是用于对在待机状态下的数据进行处理的低功耗处理器。在一些实施例中，处理器1001可以集成有GPU(Graphics Processing Unit，图像处理器)，GPU用于负责显示屏所需要显示的内容的渲染和绘制。一些实施例中，处理器1001还可以包括AI(Artificial Intelligence，人工智能)处理器，该AI处理器用于处理有关机器学习的计算操作。
存储器1002可以包括一个或多个计算机可读存储介质，该计算机可读存储介质可以是非暂态的。存储器1002还可包括高速随机存取存储器，以及非易失性存储器，比如一个或多个磁盘存储设备、闪存存储设备。在一些实施例中，存储器1002中的非暂态的计算机可读存储介质用于存储至少一个计算机可读指令，该至少一个计算机可读指令用于被处理器1001所执行以实现本申请中方法实施例提供的数据读取方法。
在一些实施例中，终端设备1000还可选包括有：外围设备接口1003和至少一个外围设备。处理器1001、存储器1002和外围设备接口1003之间可以通过总线或信号线相连。各个外围设备可以通过总线、信号线或电路板与外围设备接口1003相连。具体地，外围设备包括：射频电路1004、显示屏1005、摄像头组件1006、音频电路1007和电源1008中的至少一种。
外围设备接口1003可被用于将I/O(Input/Output，输入/输出)相关的至少一个外围设备连接到处理器1001和存储器1002。在一些实施例中，处理器1001、存储器1002和外围设备接口1003被集成在同一芯片或电路板上；在一些其他实施例中，处理器1001、存储器1002和外围设备接口1003中的任意一个或两个可以在单独的芯片或电路板上实现，本实施例对此不加以限定。
射频电路1004用于接收和发射RF(Radio Frequency，射频)信号，也称电磁信号。射频电路1004通过电磁信号与通信网络以及其他通信设备进行通信。射频电路1004将电信号转换为电磁信号进行发送，或者，将接收到的电磁信号转换为电信号。可选地，射频电路1004包括：天线系统、RF收发器、一个或多个放大器、调谐器、振荡器、数字信号处理器、编解码芯片组、用户身份模块卡等等。射频电路1004可以通过至少一种无线通信协议来与其它终端进行通信。该无线通信协议包括但不限于：万维网、城域网、内联网、各代移动通信网络(2G、3G、4G及5G)、无线局域网和/或WiFi(Wireless Fidelity，无线保真)网络。在一些实施例中，射频电路1004还可以包括NFC(Near Field Communication，近距离无线通信)有关的电路，本申请对此不加以限定。
显示屏1005用于显示UI(User Interface，用户界面)。该UI可以包括图形、文本、图标、视频及其它们的任意组合。当显示屏1005是触摸显示屏时，显示屏1005还具有采集在显示屏1005的表面或表面上方的触摸信号的能力。该触摸信号可以作为控制信号输入至处理器1001进行处理。此时，显示屏1005还可以用于提供虚拟按钮和/或虚拟键盘，也称软按钮和/或软键盘。在一些实施例中，显示屏1005可以为一个，设置在终端设备1000的前面板；在另一些实施例中，显示屏1005可以为至少两个，分别设置在终端设备1000的不同表面或呈折叠设计；在另一些实施例中，显示屏1005可以是柔性显示屏，设置在终端设备1000的弯曲表面上或折叠面上。甚至，显示屏1005还可以设置成非矩形的不规则图形，也即异形屏。显示屏1005可以采用LCD(Liquid Crystal Display，液晶显示屏)、OLED(Organic Light-Emitting Diode，有机发光二极管)等材质制备。
摄像头组件1006用于采集图像或视频。可选地，摄像头组件1006包括前置摄像头和 后置摄像头。通常，前置摄像头设置在终端的前面板，后置摄像头设置在终端的背面。在一些实施例中，后置摄像头为至少两个，分别为主摄像头、景深摄像头、广角摄像头、长焦摄像头中的任意一种，以实现主摄像头和景深摄像头融合实现背景虚化功能、主摄像头和广角摄像头融合实现全景拍摄以及VR(Virtual Reality，虚拟现实)拍摄功能或者其它融合拍摄功能。在一些实施例中，摄像头组件1006还可以包括闪光灯。闪光灯可以是单色温闪光灯，也可以是双色温闪光灯。双色温闪光灯是指暖光闪光灯和冷光闪光灯的组合，可以用于不同色温下的光线补偿。
音频电路1007可以包括麦克风和扬声器。麦克风用于采集用户及环境的声波，并将声波转换为电信号输入至处理器1001进行处理，或者输入至射频电路1004以实现语音通信。出于立体声采集或降噪的目的，麦克风可以为多个，分别设置在终端设备1000的不同部位。麦克风还可以是阵列麦克风或全向采集型麦克风。扬声器则用于将来自处理器1001或射频电路1004的电信号转换为声波。扬声器可以是传统的薄膜扬声器，也可以是压电陶瓷扬声器。当扬声器是压电陶瓷扬声器时，不仅可以将电信号转换为人类可听见的声波，也可以将电信号转换为人类听不见的声波以进行测距等用途。在一些实施例中，音频电路1007还可以包括耳机插孔。
电源1008用于为终端设备1000中的各个组件进行供电。电源1008可以是交流电、直流电、一次性电池或可充电电池。当电源1008包括可充电电池时，该可充电电池可以是有线充电电池或无线充电电池。有线充电电池是通过有线线路充电的电池，无线充电电池是通过无线线圈充电的电池。该可充电电池还可以用于支持快充技术。
在一些实施例中，终端设备1000还包括有一个或多个传感器1009。该一个或多个传感器1009包括但不限于：加速度传感器1011、陀螺仪传感器1012、压力传感器1013、光学传感器1014以及接近传感器1015。
加速度传感器1011可以检测以终端设备1000建立的坐标系的三个坐标轴上的加速度大小。比如，加速度传感器1011可以用于检测重力加速度在三个坐标轴上的分量。处理器1001可以根据加速度传感器1011采集的重力加速度信号，控制显示屏1005以横向视图或纵向视图进行用户界面的显示。加速度传感器1011还可以用于游戏或者用户的运动数据的采集。
陀螺仪传感器1012可以检测终端设备1000的机体方向及转动角度，陀螺仪传感器1012可以与加速度传感器1011协同采集用户对终端设备1000的3D动作。处理器1001根据陀螺仪传感器1012采集的数据，可以实现如下功能：动作感应(比如根据用户的倾斜操作来改变UI)、拍摄时的图像稳定、游戏控制以及惯性导航。
压力传感器1013可以设置在终端设备1000的侧边框和/或显示屏1005的下层。当压力传感器1013设置在终端设备1000的侧边框时，可以检测用户对终端设备1000的握持信号，由处理器1001根据压力传感器1013采集的握持信号进行左右手识别或快捷操作。当压力传感器1013设置在显示屏1005的下层时，由处理器1001根据用户对显示屏1005的压力操作，实现对UI界面上的可操作性控件进行控制。可操作性控件包括按钮控件、滚动条控件、图标控件、菜单控件中的至少一种。
光学传感器1014用于采集环境光强度。在一个实施例中，处理器1001可以根据光学传感器1014采集的环境光强度，控制显示屏1005的显示亮度。具体地，当环境光强度较高时，调高显示屏1005的显示亮度；当环境光强度较低时，调低显示屏1005的显示亮度。在另一个实施例中，处理器1001还可以根据光学传感器1014采集的环境光强度，动态调整摄像头组件1006的拍摄参数。
接近传感器1015，也称距离传感器，通常设置在终端设备1000的前面板。接近传感器1015用于采集用户与终端设备1000的正面之间的距离。在一个实施例中，当接近传感器1015检测到用户与终端设备1000的正面之间的距离逐渐变小时，由处理器1001控制显示屏1005从亮屏状态切换为息屏状态；当接近传感器1015检测到用户与终端设备1000 的正面之间的距离逐渐变大时，由处理器1001控制显示屏1005从息屏状态切换为亮屏状态。
本领域技术人员可以理解，图10中示出的结构并不构成对终端设备1000的限定，可以包括比图示更多或更少的组件，或者组合某些组件，或者采用不同的组件布置。
图11为本申请实施例提供的服务器的结构示意图，该服务器1100可因配置或性能不同而产生比较大的差异，可以包括一个或多个处理器1101和一个或多个的存储器1102，其中，该一个或多个存储器1102中存储有至少一条计算机可读指令，该至少一条计算机可读指令由该一个或多个处理器1101加载并执行以实现上述各个方法实施例提供的数据读取方法，示例性的，处理器1101为CPU。当然，该服务器1100还可以具有有线或无线网络接口、键盘以及输入输出接口等部件，以便进行输入输出，该服务器1100还可以包括其他用于实现设备功能的部件，在此不做赘述。
在示例性实施例中，还提供了一种计算机可读存储介质，该存储介质中存储有至少一条计算机可读指令，该至少一条计算机可读指令由处理器加载并执行，以使电子设备实现上述任一种数据读取方法。
可选地，上述计算机可读存储介质可以是只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、只读光盘(Compact Disc Read-Only Memory，CD-ROM)、磁带、软盘和光数据存储设备等。
在示例性实施例中，还提供了一种计算机程序产品，该计算机程序产品中存储有至少一条计算机可读指令，该至少一条计算机可读指令由处理器加载并执行，以使电子设备实现上述任一种数据读取方法。
应当理解的是，在本文中提及的“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
以上所述仅为本申请的示例性实施例，并不用以限制本申请，凡在本申请的原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (23)

  1. 一种数据读取方法，由电子设备的处理器执行，所述电子设备包括分别与所述处理器连接的脉动阵列和存储单元，所述脉动阵列包含权重属性寄存器，所述方法包括：
    获取第一权重读请求和第一特征映射读请求，所述第一权重读请求用于请求从所述存储单元中读取权重属性数据，所述第一特征映射读请求用于请求从所述存储单元中读取特征映射属性数据；
    获取参考状态标识，所述参考状态标识用于表征在预设运行时间后，脉动阵列中权重属性寄存器的状态，所述权重属性寄存器用于寄存所述权重属性数据；
    在所述参考状态标识满足第一预设条件的情况下，响应于所述第一权重读请求将所述存储单元存储的所述权重属性数据读取至所述脉动阵列；及
    在所述参考状态标识满足第二预设条件的情况下，响应于所述第一特征映射读请求将所述存储单元存储的所述特征映射属性数据读取至所述脉动阵列，所述脉动阵列用于基于所述权重属性数据和特征映射属性数据进行计算。
  2. 根据权利要求1所述的方法，所述参考状态标识满足第一预设条件为：所述参考状态标识表征在从当前时间起的所述预设运行时间后，所述权重属性寄存器处于待寄存权重属性数据的状态。
  3. 根据权利要求1或2所述的方法，所述参考状态标识满足第二预设条件为：所述参考状态标识表征在从当前时间起的所述预设运行时间后，所述权重属性寄存器处于寄存完权重属性数据的状态。
  4. 根据权利要求2所述的方法，所述方法还包括：
    获取第一状态标识，所述第一状态标识表征在从当前时间起的所述预设运行时间后，所述权重属性寄存器是否寄存完第设定数量个时钟周期的权重属性数据；
    当所述第一状态标识表征：在从当前时间起的所述预设运行时间后，所述权重属性寄存器寄存完第设定数量个时钟周期的权重属性数据，则确定所述参考状态标识表征在从当前时间起的所述预设运行时间后，所述权重属性寄存器处于寄存完权重属性数据的状态。
  5. 根据权利要求3所述的方法，所述方法还包括：
    获取第二状态标识，所述第二状态标识表征在从当前时间起的所述预设运行时间后所述权重属性寄存器中的权重属性数据是否和第一个时钟周期的特征映射属性数据进行计算；
    当所述第二状态标识表征：在从当前时间起的所述预设运行时间后，所述权重属性寄存器中的权重属性数据和第一个时钟周期的特征映射属性数据进行计算，则确定所述参考状态标识表征在从当前时间起的所述预设运行时间后，所述权重属性寄存器处于待寄存权重属性数据的状态。
  6. 根据权利要求1至5任一项所述的方法，在所述基于所述第一特征映射读请求将所述存储单元存储的所述特征映射属性数据读取至所述脉动阵列之后，还包括：
    获取第二权重读请求和第二特征映射读请求，所述第二权重读请求用于请求从所述存储单元中读取所述权重属性数据，所述第二特征映射读请求用于请求从所述存储单元中读取所述特征映射属性数据；
    基于所述第二权重读请求将所述存储单元存储的所述权重属性数据读取至所述脉动阵列；
    基于所述第二特征映射读请求将所述存储单元存储的所述特征映射属性数据读取至所述脉动阵列，所述权重属性数据的读延迟和所述特征映射属性数据的读延迟为所述预设运行时间。
  7. 根据权利要求1至6任一项所述的方法，所述第一权重读请求包括至少一个第一权重子请求，所述存储单元包括至少一个第一存储块；
    所述响应于所述第一权重读请求将所述存储单元存储的所述权重属性数据读取至所 述脉动阵列，包括：
    对于任一个第一权重子请求，在所述任一个第一权重子请求为有效请求的情况下，确定所述任一个第一权重子请求对应的第一存储块，从所述任一个第一权重子请求对应的第一存储块中读取所述任一个第一权重子请求对应的权重属性数据；
    将各个第一权重子请求对应的权重属性数据送入所述脉动阵列。
  8. 根据权利要求7所述的方法，所述方法还包括：
    从所述任一个第一权重子请求中提取所述任一个第一权重子请求对应的第一存储块的地址；
    当所述任一个第一权重子请求对应的第一存储块的地址与参考第一权重子请求对应的第一存储块的地址不同，确定所述任一个第一权重子请求为有效请求，所述参考第一权重子请求为所述多个第一权重子请求中除所述任一个第一权重子请求之外的至少一个第一权重子请求。
  9. 根据权利要求7所述的方法，任一个第一存储块包括至少一个第二存储块；
    所述从所述任一个第一权重子请求对应的第一存储块中读取所述任一个第一权重子请求对应的权重属性数据，包括：
    确定所述任一个第一权重子请求对应的第二存储块；
    从所述任一个第一权重子请求对应的第二存储块中读取所述任一个第一权重子请求对应的权重属性数据。
  10. 根据权利要求1至9任一项所述的方法，所述方法还包括：
    获取写请求，所述写请求用于将所述权重属性数据或者所述特征映射属性数据写入所述存储单元中；
    将所述写请求对应的权重属性数据或者特征映射属性数据写入所述存储单元中。
  11. 根据权利要求10所述的方法，所述写请求包括至少一个第三子请求，所述存储单元包括至少一个第一存储块；
    所述将所述写请求对应的权重属性数据或者特征映射属性数据写入所述存储单元中，包括：
    对于任一个第三子请求，确定所述任一个第三子请求对应的第一存储块；
    将所述任一个第三子请求对应的权重属性数据或者特征映射属性数据写入所述任一个第三子请求对应的第一存储块。
  12. 一种存储系统，所述存储系统包括处理单元，还包括分别与所述处理器连接的存储单元和脉动阵列，所述脉动阵列包含权重属性寄存器；
    所述存储单元，用于存储权重属性数据和特征映射属性数据；
    所述处理单元，用于获取第一权重读请求和第一特征映射读请求，所述第一权重读请求用于从所述存储单元中读取权重属性数据，所述第一特征映射读请求用于请求从所述存储单元中读取特征映射属性数据；
    所述处理单元，还用于获取参考状态标识，所述参考状态标识用于表征在从当前时间起的预设运行时间后，脉动阵列中权重属性寄存器的状态，所述权重属性寄存器用于寄存所述权重属性数据；
    所述处理单元，还用于在所述参考状态标识满足第一预设条件的情况下，响应于所述第一权重读请求将所述存储单元存储的所述权重属性数据读取至所述脉动阵列；及
    所述处理单元，还用于在所述参考状态标识满足第二预设条件的情况下，基于所述第一特征映射读请求将所述存储单元存储的所述特征映射属性数据读取至所述脉动阵列；
    所述脉动阵列，用于基于所述权重属性数据和特征映射属性数据进行计算。
  13. 根据权利要求12所述的系统，所述处理单元包括第一状态寄存器、参考状态寄存器和确定单元；
    所述第一状态寄存器，用于寄存第一状态标识，所述第一状态标识表征在从当前时间 起的所述预设运行时间后所述权重属性寄存器是否寄存完第设定数量个时钟周期的权重属性数据；
    所述参考状态寄存器，用于寄存所述参考状态标识；
    所述确定单元，用于获取所述第一状态标识；当所述第一状态标识表征：在从当前时间起的所述预设运行时间后，所述权重属性寄存器寄存完第设定数量个时钟周期的权重属性数据，则确定所述参考状态标识表征在从当前时间起的所述预设运行时间后，所述权重属性寄存器处于寄存完权重属性数据的状态，所述参考状态标识满足第二预设条件为：所述参考状态标识表征在从当前时间起的所述预设运行时间后，所述权重属性寄存器处于寄存完权重属性数据的状态。
  14. 根据权利要求12或13所述的系统，所述处理单元包括第二状态寄存器、参考状态寄存器和确定单元；
    所述第二状态寄存器，用于寄存第二状态标识，所述第二状态标识表征在从当前时间起的所述预设运行时间后所述权重属性寄存器中的权重属性数据是否和第一个时钟周期的特征映射属性数据进行计算；
    所述参考状态寄存器，用于寄存所述参考状态标识；
    所述确定单元，用于获取第二状态标识；在所述第二状态标识表征在从当前时间起的所述预设运行时间后所述权重属性寄存器中的权重属性数据和第一个时钟周期的特征映射属性数据进行计算的情况下，确定所述参考状态标识表征在从当前时间起的所述预设运行时间后，所述权重属性寄存器处于待寄存权重属性数据的状态，所述参考状态标识满足第一预设条件为：所述参考状态标识表征在从当前时间起的所述预设运行时间后，所述权重属性寄存器处于待寄存权重属性数据的状态。
  15. 根据权利要求12至14任一项所述的系统，所述处理单元，还用于获取第二权重读请求和第二特征映射读请求，所述第二权重读请求用于请求从所述存储单元中读取所述权重属性数据，所述第二特征映射读请求用于请求从所述存储单元中读取所述特征映射属性数据；
    所述处理单元，还用于基于所述第二权重读请求将所述存储单元存储的所述权重属性数据读取至所述脉动阵列；
    所述处理单元，还用于基于所述第二特征映射读请求将所述存储单元存储的所述特征映射属性数据读取至所述脉动阵列，所述权重属性数据的读延迟和所述特征映射属性数据的读延迟为所述预设运行时间。
  16. 根据权利要求12至15任一项所述的系统，所述处理单元包括散列单元、读取单元和收集单元，所述存储单元包括至少一个第一存储块；
    任一个第一存储块，用于存储所述权重属性数据和所述特征映射属性数据；
    所述散列单元，用于对于任一个第一权重子请求，在所述任一个第一权重子请求为有效请求的情况下，确定所述任一个第一权重子请求对应的第一存储块，所述第一权重读请求包括至少一个第一权重子请求；
    所述读取单元，用于从所述任一个第一权重子请求对应的第一存储块中读取所述任一个第一权重子请求对应的权重属性数据；
    所述收集单元，用于收集各个第一权重子请求对应的权重属性数据，并将各个第一权重子请求对应的权重属性数据送入所述脉动阵列。
  17. 根据权利要求16所述的系统，所述系统还包括冲突检测单元；
    所述冲突检测单元，用于从所述任一个第一权重子请求中提取所述任一个第一权重子请求对应的第一存储块的地址；
    所述冲突检测单元，还用于当所述任一个第一权重子请求对应的第一存储块的地址与参考第一权重子请求对应的第一存储块的地址不同，确定所述任一个第一权重子请求为有效请求，所述参考第一权重子请求为所述多个第一权重子请求中除所述任一个第一权重子 请求之外的至少一个第一权重子请求。
  18. 根据权利要求16所述的系统，任一个第一存储块包括至少一个第二存储块；
    任一个第二存储块，用于存储所述权重属性数据和所述特征映射属性数据；
    所述读取单元，用于确定所述任一个第一权重子请求对应的第二存储块；从所述任一个第一权重子请求对应的第二存储块中读取所述任一个第一权重子请求对应的权重属性数据。
  19. 根据权利要求12至18任一项所述的系统，所述处理单元，还用于获取写请求，所述写请求用于将所述权重属性数据或者所述特征映射属性数据写入所述存储单元中；将所述写请求对应的权重属性数据或者特征映射属性数据写入所述存储单元中。
  20. 根据权利要求19所述的系统，所述处理单元包括散列单元和写入单元，所述存储单元包括至少一个第一存储块；
    所述散列单元，用于对于任一个第三子请求，确定所述任一个第三子请求对应的第一存储块，所述写请求包括至少一个第三子请求；
    所述写入单元，用于将所述任一个第三子请求对应的权重属性数据或者特征映射属性数据写入所述任一个第三子请求对应的第一存储块。
  21. 一种数据读取装置，所述装置包括：
    获取模块，用于获取第一权重读请求和第一特征映射读请求，所述第一权重读请求用于请求从存储单元中读取权重属性数据，所述第一特征映射读请求用于请求从所述存储单元中读取特征映射属性数据；
    所述获取模块，还用于获取参考状态标识，所述参考状态标识用于表征在从当前时间起的预设运行时间后，脉动阵列中权重属性寄存器的状态，所述权重属性寄存器用于寄存所述权重属性数据；
    读取模块，用于在所述参考状态标识满足第一预设条件的情况下，响应于所述第一权重读请求将所述存储单元存储的所述权重属性数据读取至所述脉动阵列；及
    所述读取模块，还用于在所述参考状态标识满足第二预设条件的情况下，基于所述第一特征映射读请求将所述存储单元存储的所述特征映射属性数据读取至所述脉动阵列，所述脉动阵列用于基于所述权重属性数据和特征映射属性数据进行计算。
  22. 一种电子设备，所述电子设备包括处理器和存储器，所述存储器中存储有至少一条计算机可读指令，所述至少一条计算机可读指令由所述处理器加载并执行，以使所述电子设备实现如权利要求1至11任一所述的数据读取方法。
  23. 一种计算机可读存储介质，所述计算机可读存储介质中存储有至少一条计算机可读指令，所述至少一条计算机可读指令由处理器加载并执行，以使电子设备实现如权利要求1至11任一所述的数据读取方法。
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