WO2024198857A1 - 晶体管结构、半导体结构及其制备方法 - Google Patents

晶体管结构、半导体结构及其制备方法 Download PDF

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Publication number
WO2024198857A1
WO2024198857A1 PCT/CN2024/080124 CN2024080124W WO2024198857A1 WO 2024198857 A1 WO2024198857 A1 WO 2024198857A1 CN 2024080124 W CN2024080124 W CN 2024080124W WO 2024198857 A1 WO2024198857 A1 WO 2024198857A1
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WIPO (PCT)
Prior art keywords
word line
semiconductor
gate
air gap
separation groove
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PCT/CN2024/080124
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English (en)
French (fr)
Inventor
刘翔
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CXMT Corp
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CXMT Corp
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Priority to EP24777647.9A priority Critical patent/EP4518605A4/en
Publication of WO2024198857A1 publication Critical patent/WO2024198857A1/zh
Priority to US18/940,705 priority patent/US20250393262A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/023—Manufacture or treatment of FETs having insulated gates [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/021—Manufacture or treatment of air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/20—Air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular to a transistor structure, a semiconductor structure and a preparation method thereof.
  • VCAT vertical channel array transistor
  • parasitic capacitance is formed between two adjacent word lines, which causes the voltage of one word line to rise rapidly at the same time as the voltage of the other word line rises, thereby generating a large leakage current. Therefore, how to avoid interference between two adjacent word lines to reduce static leakage of the device during use is an urgent problem to be solved.
  • the present disclosure provides a transistor structure, a semiconductor structure and a method for manufacturing the same, which can avoid interference between two adjacent word lines to reduce static leakage of the device during use.
  • the present disclosure provides a semiconductor structure, including:
  • a substrate having a plurality of active groups distributed at intervals and arranged in an array along a first direction and a second direction; the active groups include two semiconductor pillars facing each other in the second direction and separated by a separation groove; the second direction intersects the first direction;
  • a word line structure comprises a first word line and two second word lines arranged corresponding to any column of the active group arranged along the first direction; the first word line is located in the separation groove, and the two second word lines are respectively located on the side walls of the corresponding semiconductor column away from the separation groove;
  • the second word line and the first word line both extend along the first direction, and the second word line and the first word line are staggered in a direction perpendicular to the substrate.
  • the semiconductor structure further comprises:
  • the air gap structure is located in the separation groove, above the first word line, and opposite to the second word line in the second direction.
  • a top surface of the first word line is flush with a bottom surface of the second word line or is lower than a bottom surface of the second word line.
  • the bottom surface of the second word line is flush with or higher than the bottom surface of the air gap structure; the top surface of the second word line is flush with or lower than the top surface of the air gap structure.
  • the semiconductor structure further comprises:
  • the interlayer dielectric layer covers the sidewall of the semiconductor column perpendicular to the second direction and is located between the semiconductor column and the first word line and between the semiconductor column and the second word line.
  • the semiconductor structure further comprises:
  • a first isolation structure is located in the separation groove and closes the air gap structure; the first isolation structure is used to define the top surface of the air gap structure;
  • the second isolation structure is located in the interval between the adjacent active groups and covers the second word line and the interlayer dielectric layer located in the interval.
  • the semiconductor structure further comprises:
  • a plurality of capacitor units are respectively arranged above the corresponding semiconductor columns.
  • the present disclosure further provides a method for preparing a semiconductor structure, comprising:
  • the intermediate structure Graphically forming the intermediate structure to obtain a plurality of active groups arranged in an array along the first direction and the second direction;
  • the active group includes two semiconductor pillars facing each other in the second direction and separated by the separation groove;
  • the second direction intersects the first direction;
  • the second word line and the first word line both extend along the first direction, and the second word line and the first word line are staggered in a direction perpendicular to the substrate.
  • the preparation method before patterning the intermediate structure, the preparation method further comprises:
  • first isolation structure in the separation groove, wherein the first isolation structure is used to define a top surface of an air gap structure, and the air gap structure is located above the first word line in the separation groove;
  • the second word line is also opposite to the air gap structure in the second direction.
  • the preparation method before forming the first word line in the separation groove, further includes: forming a first interlayer dielectric layer covering the inner wall of the separation groove; wherein the first word line is formed on the first interlayer dielectric layer and fills a portion of the separation groove;
  • the preparation method further includes: forming a second interlayer dielectric layer at least covering the top surface of the first word line; wherein the air gap structure is formed on the second interlayer dielectric layer.
  • the forming of a plurality of separation grooves in the substrate that are arranged in parallel and spaced apart and extend along a first direction to obtain a plurality of intermediate structures includes:
  • a plurality of separation grooves along the first direction are formed in the plurality of the initial structures and the first sub-isolation structures to obtain the intermediate structure.
  • the preparation method further includes:
  • the forming of a second word line on a sidewall of the semiconductor column away from the separation groove comprises:
  • the second word lines are respectively formed on the side walls of the third interlayer dielectric layer away from the semiconductor pillars on both sides; there is a gap between the two second word lines in the same word line trench;
  • a third sub-isolation structure is formed in the word line groove to cover the exposed surfaces of the second sub-isolation structure, the second word line and the third interlayer dielectric layer; wherein the third sub-isolation structure, the second sub-isolation structure and the first sub-isolation structure together constitute a second isolation structure.
  • a bottom surface of the word line trench is flush with a top surface of the first word line
  • a bottom surface of the word line trench is lower than a top surface of the first word line.
  • the bottom surface of the second word line is flush with or higher than the bottom surface of the air gap structure; the top surface of the second word line is flush with or lower than the top surface of the air gap structure.
  • the preparation method further comprises:
  • a capacitor unit is formed above the semiconductor column.
  • the separation groove can separate the same active group into two semiconductor pillars, and form two second word lines on the outer side walls of the two semiconductor pillars, and form a first word line in the separation groove.
  • the second word line and the first word line are staggered in a direction perpendicular to the substrate, so that the second word line and the first word line together constitute the control word line of the corresponding semiconductor pillar.
  • the present disclosure further provides a transistor structure, comprising: a semiconductor column and a first gate and a second gate respectively located on opposite sides of the semiconductor column;
  • the first gate and the second gate are staggered in the extension direction of the semiconductor column; the first gate and the second gate together constitute a control gate of the semiconductor column.
  • a top surface of the first gate is flush with a bottom surface of the second gate or is lower than a bottom surface of the second gate.
  • the transistor structure further includes: an air gap structure located between two adjacent semiconductor pillars and above the first gate, and bottoms of the two adjacent semiconductor pillars are interconnected.
  • the first gate and the second gate are staggered in a direction perpendicular to the substrate to jointly control the semiconductor column, thereby reducing interference between adjacent transistors and reducing static leakage of the device during use.
  • FIG. 1 (a) is a schematic diagram of a cross-sectional structure of a semiconductor structure provided in some embodiments of the present disclosure
  • FIG. 1 (b) is a schematic diagram of a part of the structure shown in FIG. 1 (a);
  • FIG. 2 (a) is a partial schematic diagram of a semiconductor structure provided by some embodiments of the present disclosure when 0 is written;
  • FIG. 2 (b) is a voltage-current diagram of the structure shown in FIG. 2 (a) when 0 is written;
  • FIG. 3 (a) is a partial schematic diagram of a semiconductor structure provided by some embodiments of the present disclosure when 1 is written;
  • FIG. 3 (b) is a voltage-current diagram of the structure shown in FIG. 3 (a) when 1 is written;
  • FIG4 is a schematic flow chart of a method for preparing a semiconductor structure provided in some embodiments of the present disclosure.
  • FIG5 is a schematic flow chart of step S200 in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure
  • FIG6 is a schematic flow chart of step S500 in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure
  • FIG. 7 is a schematic diagram of a cross-sectional structure of a structure obtained in step S100 in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure
  • FIG. 8 (a) is a schematic diagram of a cross-sectional structure of a structure obtained in step S210 in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure
  • FIG. 8 (b) is a schematic diagram of a top view of FIG. 8 (a);
  • FIG. 9 (a) is a schematic diagram of a cross-sectional structure of a structure obtained in step S220 in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure
  • FIG. 9 (b) is a schematic diagram of a top view of FIG. 9 (a);
  • FIG. 10 is a schematic diagram of the process structure in step S220 in the method for preparing a semiconductor structure provided in some embodiments of the present disclosure
  • FIG. 11 is a schematic diagram of a cross-sectional structure of a structure obtained after forming a first interlayer dielectric layer in a method for preparing a semiconductor structure provided by some embodiments of the present disclosure
  • FIG. 12 is a schematic diagram of a cross-sectional structure of a structure obtained in step S300 in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure
  • FIG. 13 is a schematic diagram of a cross-sectional structure of a structure obtained in step S400 in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure
  • FIG. 14 is a schematic cross-sectional view of a structure obtained after an initial second sub-isolation structure is formed in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure
  • FIG. 15 is a schematic diagram of a cross-sectional structure of a structure obtained after obtaining a second sub-isolation structure in a method for preparing a semiconductor structure provided by some embodiments of the present disclosure
  • FIG. 16 is a schematic cross-sectional view of a structure obtained in step S510 in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure
  • FIG. 17 is a schematic diagram of a cross-sectional structure of a structure obtained in step S520 in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure
  • FIG. 18 is a schematic diagram of a cross-sectional structure of a structure obtained in step S530 in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure
  • FIG. 19 is a partial enlarged schematic diagram of a structure obtained in step S530 in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure.
  • FIG20 is a schematic diagram of a cross-sectional structure of a transistor structure provided by some embodiments of the present disclosure.
  • FIG. 21 is a schematic diagram of a cross-sectional structure of a transistor structure provided in some other embodiments of the present disclosure.
  • substrate 100. semiconductor pillar; 10a. intermediate structure; 10b. initial structure; 10c. first sub-isolation structure; 11 a, patterned mask layer; 111a, mask pattern; 112a, mask sidewall; 2, word line structure; 21, first word line; 22, second word line; 3, air gap structure; 4, interlayer dielectric layer; 41, first interlayer dielectric layer; 42, second interlayer dielectric layer; 43, third interlayer dielectric layer; 5, first isolation structure; 6, second isolation structure; 61a, initial second sub-isolation structure; 61, second sub-isolation structure; 62, third sub-isolation structure; 7, capacitor contact structure; S, separation groove; W, word line groove; G1, first gate; G2, second gate; G21, second gate on the right; G22, the second gate on the left.
  • first element, component, region, layer, word line, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, a first word line may be referred to as a second word line, and similarly, a second word line may be referred to as a first word line; the first word line and the second word line are different word lines.
  • Spatial relationship terms such as “on", “above", etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as “above” or “on it” will be oriented as “below” the other elements or features. Therefore, the exemplary terms “on", “above" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
  • additional orientations e.g., rotated 90 degrees or other orientations
  • Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and/or tolerances are anticipated.
  • Embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present disclosure.
  • the present disclosure provides a transistor structure, a semiconductor structure and a method for manufacturing the same. Interference between two adjacent word lines can be avoided to reduce static leakage of the device during use.
  • the present disclosure provides a semiconductor structure.
  • the semiconductor structure may include a substrate 1 and a word line structure 2 .
  • the substrate 1 has a plurality of active groups which are distributed at intervals and arranged in an array along the first direction and the second direction; the active group includes two semiconductor pillars 100 which are opposite to each other in the second direction and separated by a separation groove S.
  • the word line structure 2 includes a first word line 21 and two second word lines 22 arranged corresponding to any column of active groups arranged along the first direction.
  • the first word line 21 is located in the separation groove S, and the two second word lines 22 are respectively located on the side walls of the corresponding semiconductor column 100 away from the separation groove S.
  • the second word line 22 and the first word line 21 both extend along the first direction, and the second word line 22 and the first word line 21 are staggered in a direction perpendicular to the substrate 1, for example, the bottom surface of the second word line 22 is flush with or higher than the top surface of the first word line 21, and the distance between the bottom surface of the second word line 22 and the top surface of the first word line 21 is less than 30nm.
  • the bottom surface of the second word line 22 is higher than the top surface of the first word line 21 but the distance is less than 30nm, which will not affect the opening of the transistor.
  • the separation groove S can be separated into two semiconductor pillars 100 in the same active group, and two second word lines 22 are formed on the outer side walls of the two semiconductor pillars 100, and the first word line 21 is formed in the separation groove S.
  • the second word line 22 and the first word line 21 are staggered in the direction perpendicular to the substrate 1, so that the second word line 22 and the first word line 21 can jointly constitute the control word line of the corresponding semiconductor pillar 100, that is, only turning on the first word line 21 or the second word line 22 is not enough to turn on the corresponding transistor device.
  • the interference between the two second word lines 22 between adjacent active groups can be reduced to reduce the static leakage of the device during use.
  • the semiconductor structure provided in the above embodiment reduces the interference between two second word lines 22 between adjacent active groups, and can also reduce the parasitic capacitance between adjacent second word lines 22, thereby reducing the impact of the parasitic capacitance on the charging and discharging speed of the device and improving the storage speed of the semiconductor structure.
  • two second word lines 22 respectively arranged on the outer side walls of two semiconductor pillars 100 share the same first word line 21, which can reduce the size of the semiconductor structure to the greatest extent on the one hand, and make the layout of the semiconductor structure more reasonable on the other hand, thereby effectively improving the storage density of the semiconductor structure.
  • the second direction intersects with the first direction.
  • Figure (a) in Figure 1 Please refer to Figure (a) in Figure 1 to understand the role of the working process of the first word line 21 and the second word line 22 in improving the coupling of adjacent transistors: for two adjacent active groups, when the first word line 21 in the left active group and the second word line 22 on the right are turned on, the surrounding electrons will gather in the channel on the right in the left active group. Since the second word line 22 on the right in the left active group is adjacent to the second word line 22 on the left in the right active group, the voltage of the second word line 22 on the left in the right active group may rise, and the electrons will gather in the channel corresponding to the second word line 22 in the right active group.
  • the parasitic capacitance between adjacent second word lines 22 in adjacent active groups can be reduced by setting a shorter second word line 22 without changing the channel length in the semiconductor structure.
  • FIG. 1 (b) please refer to understand the role of the first word line 21 located at the bottom of the separation groove S in improving the static leakage of the device during use:
  • the bottom and top of the active group are of the first doping type, and the middle of the active group is of the second doping type.
  • the bottom and top of the active group are N+ doped, used as source and drain, and the middle of the active group is P doped, used as a P-type channel (P channel).
  • the first word line 21 at the bottom is turned on, since its voltage is higher (for example, 2V-3V), which is greater than the operating voltage (for example, 1V) of the bit line or storage structure (for example, a capacitor unit electrically contacting the top surface of the semiconductor column, not shown in the figure), the surrounding electrons will gather around the first word line 21 at the bottom, and will not continuously leak between the storage structure and the bit line.
  • its voltage for example, 2V-3V
  • 1V the operating voltage of the bit line or storage structure
  • the substrate 1 may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrates 100 or II/VI semiconductor substrates 100; or, the substrate 1 may also include Si/SiGe, Si/SiC, silicon on insulator (SOI) or silicon germanium on insulator substrates.
  • Si silicon
  • SiGe silicon germanium
  • SiGeC silicon germanium carbon
  • SiC silicon carbide
  • GaAs gallium arsenide
  • InAs indium arsenide
  • InP indium phosphide
  • the substrate 1 may also include Si/SiGe, Si/SiC, silicon on insulator (SOI) or silicon germanium on
  • the present disclosure does not specifically limit the material of the word line structure 2.
  • the material of the word line structure 2 may include but is not limited to metal materials, such as tungsten, cobalt, titanium nitride, etc.
  • the semiconductor structure may further include an air gap structure 3.
  • the air gap structure 3 is located in the separation trench S, above the first word line 21, and opposite to the second word line 22 in the second direction.
  • the air gap structure 3 in the separation groove S can reduce the floating body effect between adjacent active groups, thereby further reducing the static leakage of the device during use.
  • the present disclosure does not specifically limit the positional relationship between the first word line 21 and the second word line 22.
  • the top surface of the first word line 21 may be flush with the bottom surface of the second word line 22; or, the top surface of the first word line 21 may be lower than the bottom surface of the second word line 22.
  • the present disclosure does not specifically limit the positional relationship between the second word line 22 and the air gap structure 3.
  • the bottom surface of the second word line 22 may be flush with the bottom surface of the air gap structure 3; or, the bottom surface of the second word line 22 may be higher than the bottom surface of the air gap structure 3.
  • the top surface of the second word line 22 may be flush with the top surface of the air gap structure 3; or, the top surface of the second word line 22 may be lower than the top surface of the air gap structure 3.
  • the semiconductor structure may further include an interlayer dielectric layer 4.
  • the interlayer dielectric layer 4 covers the sidewalls of the semiconductor pillar 100 perpendicular to the second direction and is located between the semiconductor pillar 100 and the first word line 21 and between the semiconductor pillar 100 and the second word line 22.
  • the interlayer dielectric layer 4 may not be disposed between the air gap structure 3 and the semiconductor column 100, which is also permitted.
  • the orthographic projection of the interlayer dielectric layer 4 on the semiconductor column 100 may overlap or substantially overlap with the orthographic projection of the first word line 21 on the semiconductor column 100, and overlap or substantially overlap with the orthographic projection of the second word line 22 on the semiconductor column 100.
  • the semiconductor structure may further include a first isolation structure 5 and a second isolation structure 6 .
  • the first isolation structure 5 is located in the separation groove S and closes the air gap structure 3.
  • the first isolation structure 5 can be used to define the top surface of the air gap structure 3.
  • the second isolation structure 6 is located in the interval between adjacent active groups and covers the second word line 22 and the interlayer dielectric layer 4 located in the interval.
  • the present disclosure does not specifically limit the material of the first isolation structure 5.
  • the material of the first isolation structure 5 may include but is not limited to silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), or a combination thereof.
  • the semiconductor structure may further include a plurality of capacitor units.
  • a plurality of capacitor units may be respectively disposed above corresponding semiconductor pillars 100 .
  • FIG2 (a) and FIG2 (b) show the current IDS from the drain to the source corresponding to the two capacitor units when 0 (for example, 0V) is written
  • FIG3 (a) and FIG3 (b) show the current IDS from the drain to the source of the storage nodes NC and NC0 corresponding to the two capacitor units when 1 (for example, 1V) is written.
  • Vg refers to the voltage applied to the storage node
  • IDS refers to the current flowing through the storage node.
  • a capacitor contact structure 7 may be aligned and arranged on the semiconductor column 100, and the material of the capacitor contact structure 7 may be polysilicon, metal or metal silicide, etc. This is beneficial to improve the contact between the capacitor unit and the corresponding semiconductor column 100.
  • the present disclosure also provides a method for preparing a semiconductor structure.
  • the method for preparing the semiconductor structure may include the following steps:
  • S200 forming a plurality of separation grooves arranged in parallel and spaced apart and extending along a first direction in a substrate to obtain a plurality of intermediate structures.
  • S400 Patterning the intermediate structure to obtain a plurality of active groups arranged in an array along a first direction and a second direction; the active group includes two semiconductor pillars facing each other in the second direction and separated by a separation groove; the second direction intersects with the first direction.
  • S500 forming a second word line on a sidewall of the semiconductor column away from the separation trench.
  • the second word line and the first word line both extend along the first direction, and the second word line and the first word line are staggered in a direction perpendicular to the substrate.
  • the bottom surface of the second word line is flush with or higher than the top surface of the first word line, and the distance between the bottom surface of the second word line and the top surface of the first word line is less than 30nm.
  • the separation groove S can be used to separate the same active group into two semiconductor pillars 100, and two second word lines 22 are formed on the outer side walls of the two semiconductor pillars 100, respectively, and a first word line 21 is formed in the separation groove S.
  • the second word line 22 and the first word line 21 are staggered in a direction perpendicular to the substrate 1, so that the second word line 22 and the first word line 21 can jointly constitute the control word line of the corresponding semiconductor pillar 100, that is, only turning on the first word line 21 or the second word line 22 is not enough to turn on the corresponding device.
  • the interference between the two second word lines 22 between adjacent active groups can be reduced to reduce the static leakage of the device during use.
  • the method for preparing the semiconductor structure reduces the interference between two second word lines 22 between adjacent active groups, and can also reduce the parasitic capacitance between adjacent second word lines 22, thereby reducing the impact of the parasitic capacitance on the charging and discharging speed of the device and improving the storage speed of the semiconductor structure.
  • two second word lines 22 respectively formed on the outer side walls of two semiconductor pillars 100 share the same first word line 21, which can minimize the size of the semiconductor structure and make the layout of the semiconductor structure more reasonable, thereby effectively improving the storage density of the semiconductor structure.
  • the preparation method may further include the following step: forming a first isolation structure in the separation trench.
  • the first isolation structure is used to define the top surface of the air gap structure, and the air gap structure is located above the first word line in the separation groove. It should be noted that the second word line is opposite to the air gap structure in the second direction.
  • the air gap structure 3 in the separation groove S can reduce the floating body effect between adjacent active groups, thereby further reducing the static leakage of the device during use.
  • the preparation method may further include the following step: forming a first interlayer dielectric layer covering the inner wall of the separation trench.
  • the first word line is formed on the first interlayer dielectric layer and fills a portion of the separation trench.
  • the preparation method may further include the following steps: Step: forming a second interlayer dielectric layer at least covering a top surface of the first word line.
  • the air gap structure is formed on the second interlayer dielectric layer.
  • forming a plurality of separation grooves arranged in parallel and spaced apart and extending along a first direction in a substrate to obtain a plurality of intermediate structures may include the following steps:
  • S210 patterning the substrate to form a plurality of initial structures that are arranged in parallel and spaced apart and extend along a second direction.
  • S220 forming a first sub-isolation structure in a space between adjacent initial structures.
  • S230 forming a plurality of separation grooves along a first direction in the plurality of initial structures and the first sub-isolation structure to obtain an intermediate structure.
  • the preparation method can also include the following steps: forming an initial second sub-isolation structure in the interval between adjacent active groups in the second direction; etching back the initial second sub-isolation structure to form a word line groove, and obtaining a second sub-isolation structure.
  • step S500 of forming a second word line on the sidewall of the semiconductor pillar away from the separation trench may include the following steps:
  • S510 conformally forming a third interlayer dielectric layer on the inner wall of the word line trench.
  • S520 forming second word lines on side walls of the third interlayer dielectric layer away from the semiconductor pillars on both sides; a gap is formed between two second word lines in the same word line trench.
  • S530 forming a third sub-isolation structure in the word line trench to cover the exposed surfaces of the second sub-isolation structure, the second word line and the third interlayer dielectric layer; wherein the third sub-isolation structure, the second sub-isolation structure and the first sub-isolation structure together constitute the second isolation structure.
  • the manufacturing method may further include the following step: forming a capacitor unit above the semiconductor column.
  • step S100 a substrate 1 is provided.
  • step S200 parallel and spaced apart and extending along a first direction X are formed in the substrate 1.
  • a plurality of extending separation grooves S are formed to obtain a plurality of intermediate structures 10a.
  • step S200 forms a plurality of separation grooves S arranged in parallel and spaced apart and extending along a first direction in the substrate 1 to obtain a plurality of intermediate structures 10a, which can be specifically represented by the following steps S210-S230:
  • step S210 as shown in FIG. 8( a ) and FIG. 8( b ), the substrate 1 is patterned to form a plurality of initial structures 10 b arranged in parallel and spaced apart and extending along the second direction Y.
  • step S210 as shown in FIG. 8( a ) and FIG. 8( b ) , the substrate 1 is patterned to form a plurality of initial structures 10 b arranged in parallel and spaced apart and extending along the second direction Y.
  • step S220 as shown in FIGS. 8( a ) and 8 ( b ), a first sub-isolation structure 10 c is formed in a space between adjacent initial structures 10 b .
  • step S230 as shown in FIGS. 9 and 10 , a plurality of separation grooves S are formed along a first direction in the plurality of initial structures 10 b and the first sub-isolation structures, and an intermediate structure 10 a is obtained.
  • FIG10 shows a process structure diagram of forming a plurality of separation grooves S in some embodiments.
  • the separation grooves S may be formed in the initial structure 10b and the first sub-isolation structure in the following manner:
  • a patterned mask layer 11 a is formed on the substrate 1 ; and a plurality of separation grooves S are formed along a first direction based on the patterned mask layer 11 a.
  • the patterned mask layer 11a may be a single film layer, or may include multiple film layers; when the patterned mask layer 11a includes multiple film layers, the multiple film layers may be stacked in the vertical direction, or may be arranged in the horizontal direction.
  • the patterned mask layer 11a may include a mask pattern 111a and a mask sidewall 112b located on the sidewall of the mask pattern 111a.
  • the material of the mask sidewall 112b may be the same as or different from the material of the mask pattern 111a.
  • the preparation method may further include the following steps:
  • a first interlayer dielectric layer 41 covering the inner wall of the separation groove S is formed.
  • step S300 a first word line 21 is formed in the separation trench S.
  • step S300 is performed after forming the first interlayer dielectric layer 41 covering the inner wall of the separation trench S. Also, as shown in FIG.
  • the preparation method may further include the following steps:
  • a second interlayer dielectric layer 42 is formed to at least cover the top surface of the first word line 21.
  • the air gap structure 3 is formed on the second interlayer dielectric layer 42.
  • the first interlayer dielectric layer 41 may not be disposed between the air gap structure 3 and the inner wall of the separation groove S; that is, the first interlayer dielectric layer 41 may cover the entire inner wall of the separation groove S, or cover part of the inner wall of the separation groove S.
  • the orthographic projection of the first interlayer dielectric layer 41 on the semiconductor pillar 100 along the second direction Y may be The first word line 21 is overlapped or substantially overlapped with the orthographic projection of the first word line 21 on the semiconductor pillar 100 .
  • the preparation method may further include the following steps:
  • a first isolation structure 5 is formed in the separation trench S. Specifically, the first isolation structure 5 can be used to define a top surface of the air gap structure 3 , and the air gap structure 3 is located above the first word line 21 in the separation trench S.
  • the step of forming the first isolation structure 5 is performed after forming the second interlayer dielectric layer 42 .
  • the intermediate structure 10a is patterned to obtain a plurality of active groups arranged in an array along the first direction and the second direction.
  • the active group includes two semiconductor pillars 100 that are opposite to each other in the second direction and separated by a separation groove S.
  • the mask pattern 111a can be removed, and then the intermediate structure 10a is etched using the mask sidewall 112b and a portion of the first isolation structure 5 located above the intermediate structure 10a as a mask to form a plurality of active groups separated by a plurality of grooves arranged in the second direction Y.
  • the preparation method may further include the following step: removing the patterned mask layer 11 a and a portion of the first isolation structure 5 located above the intermediate structure 10 a .
  • the present disclosure does not specifically limit the method for removing the patterned mask layer 11a and part of the first isolation structure 5.
  • the patterned mask layer 11a and the first isolation structure 5 located above the intermediate structure 10a may be removed by, but is not limited to, a chemical-mechanical polishing process.
  • the preparation method may further include the following steps:
  • an initial second sub-isolation structure 61 a is formed in the interval between adjacent active groups in the second direction; as shown in FIG. 15 , the initial second sub-isolation structure 61 a is etched back to form a word line trench W, and a second sub-isolation structure 61 is obtained.
  • the present disclosure does not specifically limit the position of the word line trench W.
  • the bottom surface of the word line trench W may be flush with the top surface of the first word line 21; or, the bottom surface of the word line trench W may be lower than the top surface of the first word line 21; or, the bottom surface of the word line trench W may be higher than the top surface of the first word line 21.
  • step S500 a second word line 22 is formed on the sidewall of the semiconductor pillar 100 away from the separation trench S. As shown in FIG. 16 to FIG. 19 .
  • the second word line 22 and the first word line 21 both extend along the first direction, and the second word line 22 and the first word line 21 are staggered in a direction perpendicular to the substrate 1.
  • the second word line 22 may also be opposite to the air gap structure 3 in the second direction.
  • step S500 is performed after the second sub-isolation structure is obtained.
  • the present disclosure does not specifically limit the position of the second word line 22.
  • the bottom surface of the second word line 22 may be Alternatively, the bottom surface of the second word line 22 may be higher than the bottom surface of the air gap structure 3.
  • the top surface of the second word line 22 may be flush with the top surface of the air gap structure 3; alternatively, the top surface of the second word line 22 may be lower than the top surface of the air gap structure 3.
  • step S500 forms the second word line 22 on the sidewall of the semiconductor pillar 100 away from the separation trench S, which can be specifically performed as follows: steps S510-S530:
  • step S510 as shown in FIG. 16 , a third interlayer dielectric layer 43 is conformally formed on the inner wall of the word line trench W.
  • step S520 as shown in FIG17, second word lines 22 are formed on the sidewalls of the third interlayer dielectric layer 43 away from the semiconductor pillars 100. There is a gap between the two second word lines 22 in the same word line trench W.
  • a third sub-isolation structure 62 is formed in the word line trench W to cover the exposed surfaces of the second sub-isolation structure 61, the second word line 22 and the third interlayer dielectric layer 43.
  • the third sub-isolation structure 62, the second sub-isolation structure 61 and the first sub-isolation structure together constitute the second isolation structure 6.
  • the present disclosure does not specifically limit the method for forming the third interlayer dielectric layer 43 in step S510.
  • the third interlayer dielectric layer 43 may be formed by, but not limited to, an in-situ steam growth (ISSG) process and/or an atomic layer deposition (ALD) process.
  • ISSG in-situ steam growth
  • ALD atomic layer deposition
  • the present disclosure does not specifically limit the material of the third interlayer dielectric layer 43 formed in step S510.
  • the material of the third interlayer dielectric layer 43 may include, but not limited to, oxide.
  • a metal material may be formed on the sidewalls of the third interlayer dielectric layer 43 away from the semiconductor pillars 100 on both sides by a physical vapor deposition (PVD) process or an evaporation process, but is not limited thereto, and then anisotropic etching is performed in the vertical direction to remove the horizontal portion of the metal material and part of the vertical portion of the metal material, and the remaining metal material serves as the second word line 22.
  • PVD physical vapor deposition
  • the manufacturing method may further include the following step: forming a capacitor unit above the semiconductor pillar 100 .
  • the semiconductor structure preparation methods provided in the present disclosure can be used to prepare corresponding semiconductor structures. Therefore, the technical features between the semiconductor structure preparation method embodiments and the semiconductor structure embodiments can be replaced and supplemented with each other without causing conflicts, so that those skilled in the art can understand the technical content of the present disclosure.
  • the present disclosure also provides a transistor structure.
  • the transistor structure may include a semiconductor pillar 100 and a first gate G1 and a second gate G2 located at opposite sides of the semiconductor pillar 100 .
  • the first gate G1 and the second gate G2 are staggered in the extension direction of the semiconductor column 100, and the first gate G1 and the second gate G2 can together constitute the control gate of the semiconductor column 100.
  • the bottom surface of the second gate G2 is flush with or higher than
  • the top surface of the first gate G1 and the distance between the bottom surface of the second gate G2 and the top surface of the first gate G1 are less than 30 nm.
  • the first gate G1 and the second gate G2 are staggered in a direction perpendicular to the substrate 1, so that the first gate G1 and the second gate G2 together constitute the control gate of the corresponding semiconductor column 100, that is, applying voltage only to the first gate G1 or the second gate G2 is not enough to turn on the corresponding transistor structure. In this way, interference with adjacent transistors can be avoided to reduce static leakage of the device during use.
  • the transistor structure provided in the above embodiment avoids interference with adjacent transistors and can also reduce the parasitic capacitance between adjacent first gates G1 or adjacent second gates G2, thereby reducing the impact of the parasitic capacitance on the charging and discharging speed of the device and improving the storage speed of the transistor structure.
  • first gate G1 and the second gate G2 are staggered in the extension direction of the semiconductor pillar 100, which can reduce the size of the transistor structure to the greatest extent on the one hand, and make the layout of the transistor structure more reasonable on the other hand, thereby effectively improving the storage density of the transistor structure.
  • the first gate G1 and the second gate G1 have a shorter gate length than the overall gate, which can reduce the difficulty of the gate manufacturing process.
  • the first gate G1 may be shared by transistor structures located on two opposite sides thereof.
  • the dotted box in FIG21 illustrates two transistor structures; when a voltage is applied to the second gate G22 and the first gate G1 on the left, the transistor structure on the left side of the dotted box in FIG21 is turned on, and at this time, the transistor structure on the right side of the dotted box in FIG21 remains in a closed state; when a voltage is applied to the second gate G21 and the first gate G1 on the right, the transistor structure on the right side of the dotted box in FIG21 is turned on, and at this time, the transistor structure on the left side of the dotted box in FIG21 remains in a closed state.
  • the present disclosure does not specifically limit the positional relationship between the first gate G1 and the second gate G2.
  • the top surface of the first gate G1 may be flush with the bottom surface of the second gate G2; or the top surface of the first gate G1 may be lower than the bottom surface of the second gate G2.
  • the transistor structure may further include an air gap structure 3 located between two adjacent semiconductor pillars 100 and above the first gate G1 .
  • the bottoms of two adjacent semiconductor pillars 100 may be interconnected.

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Abstract

公开了一种晶体管结构、半导体结构及其制备方法。该半导体结构包括衬底和字线结构。衬底具有间隔分布且沿第一方向及第二方向阵列排布的多个有源组。有源组包括在第二方向上相对且通过分隔槽隔开的两个半导体柱。字线结构包括与沿第一方向排列的任一列有源组对应设置的一个第一字线和两个第二字线。第一字线位于分隔槽内，两个第二字线分别位于对应半导体柱背离分隔槽的侧壁上。其中，第二字线和第一字线均沿第一方向延伸，且第二字线和第一字线在垂直于衬底的方向上错位设置。

Description

晶体管结构、半导体结构及其制备方法
交叉引用
本公开要求于2023年3月29日提交的申请号为202310318809.8名称为“晶体管结构、半导体结构及其制备方法”的中国发明专利申请的优先权，该中国发明专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，特别是涉及一种晶体管结构、半导体结构及其制备方法。
背景技术
随着动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)技术的发展，存储单元的尺寸越来越小，其阵列架构由8F2到6F2再到4F2(F：在给定工艺条件下可获得的最小图案尺寸)；另外，为了尽可能地缩小单个阵列区晶体管面积，追求更高的芯片面积利用率，出现了垂直沟道阵列晶体管(Vertical channel array transistor，简称VCAT)技术。
然而，在4F2设计的结构中，相邻的两个字线之间会形成寄生电容，这使得其中一个字线电压上升的瞬间，另一字线的电压也会快速上升，从而产生较大的漏电流。因此，如何避免相邻两个字线之间的干扰，以减少器件在使用过程中的静态漏电，是当前亟需解决的问题。
发明内容
基于此，本公开提供一种晶体管结构、半导体结构及其制备方法，可以避免相邻两个字线之间的干扰，以减少器件在使用过程中的静态漏电。
为了实现上述目的，一方面，本公开提供一种半导体结构，包括：
衬底，具有间隔分布且沿第一方向及第二方向阵列排布的多个有源组；所述有源组包括在所述第二方向上相对且通过分隔槽隔开的两个半导体柱；所述第二方向与所述第一方向相交；
字线结构；所述字线结构包括与沿所述第一方向排列的任一列所述有源组对应设置的一个第一字线和两个第二字线；所述第一字线位于所述分隔槽内，两个所述第二字线分别位于对应所述半导体柱背离所述分隔槽的侧壁上；
其中，所述第二字线和所述第一字线均沿所述第一方向延伸，且所述第二字线和所述第一字线在垂直于所述衬底的方向上错位设置。
在一些实施例中，所述半导体结构还包括：
气隙结构，位于所述分隔槽内，并位于所述第一字线的上方，且与所述第二字线在所述第二方向上相对。
在一些实施例中，所述第一字线的顶面平齐于所述第二字线的底面或低于所述第二字线的底面。
在一些实施例中，所述第二字线的底面平齐于所述气隙结构的底面或高于所述气隙结构的底面；所述第二字线的顶面平齐于所述气隙结构的顶面或低于所述气隙结构的顶面。
在一些实施例中，所述半导体结构还包括：
层间介质层，覆盖所述半导体柱垂直于所述第二方向的侧壁，且位于所述半导体柱和所述第一字线之间及所述半导体柱和所述第二字线之间。
在一些实施例中，所述半导体结构还包括：
第一隔离结构，位于所述分隔槽内且封闭所述气隙结构；所述第一隔离结构用于定义所述气隙结构的顶面；
第二隔离结构，位于相邻所述有源组之间的间隔内且覆盖位于所述间隔内的所述第二字线及所述层间介质层。
在一些实施例中，所述半导体结构还包括：
多个电容单元，分别设置于对应所述半导体柱的上方。
另一方面，本公开还提供一种半导体结构的制备方法，包括：
提供衬底；
于所述衬底内形成平行间隔排列且沿第一方向延伸的多个分隔槽，以得到多个中间结构；
于所述分隔槽内形成第一字线；
图形化所述中间结构，获得沿所述第一方向及第二方向阵列排布的多个有源组；所述有源组包括在第二方向上相对且通过所述分隔槽隔开的两个半导体柱；所述第二方向与所述第一方向相交；
于所述半导体柱背离所述分隔槽的侧壁上形成第二字线；
其中，所述第二字线和所述第一字线均沿所述第一方向延伸，且所述第二字线和所述第一字线在垂直于所述衬底的方向上错位设置。
在一些实施例中，所述图形化所述中间结构之前，所述制备方法还包括：
于所述分隔槽中形成第一隔离结构，所述第一隔离结构用于定义气隙结构的顶面，所述气隙结构位于所述分隔槽内所述第一字线的上方；
其中，所述第二字线还与所述气隙结构在所述第二方向上相对。
在一些实施例中，所述于所述分隔槽内形成第一字线之前，所述制备方法还包括：形成覆盖所述分隔槽内壁的第一层间介质层；其中，所述第一字线形成于所述第一层间介质层上并填充部分所述分隔槽；
于所述分隔槽中形成第一隔离结构之前，所述制备方法还包括：形成至少覆盖所述第一字线顶面的第二层间介质层；其中，所述气隙结构形成于所述第二层间介质层上。
在一些实施例中，所述于所述衬底内形成平行间隔排列且沿第一方向延伸的多个分隔槽，以得到多个中间结构，包括：
图形化所述衬底，形成平行间隔排列且沿所述第二方向延伸的多个初始结构；
于相邻所述初始结构之间的间隔形成第一子隔离结构；
于多个所述初始结构及所述第一子隔离结构中形成沿所述第一方向的多个分隔槽，并得到所述中间结构。
在一些实施例中，所述图形化所述中间结构之后，且于所述半导体柱背离所述分隔槽的侧壁上形成第二字线之前，所述制备方法还包括：
于在所述第二方向上相邻的所述有源组的间隔内形成初始第二子隔离结构；
回刻蚀所述初始第二子隔离结构，形成字线沟槽，并得到第二子隔离结构；
所述于所述半导体柱背离所述分隔槽的侧壁上形成第二字线，包括：
于所述字线沟槽的内壁上保形形成第三层间介质层；
于所述第三层间介质层背离两侧所述半导体柱的侧壁上分别形成所述第二字线；同一所述字线沟槽内的两个所述第二字线之间具有间隔；
于所述字线沟槽内形成覆盖所述第二子隔离结构、所述第二字线及所述第三层间介质层三者裸露表面的第三子隔离结构；其中，所述第三子隔离结构和所述第二子隔离结构、所述第一子隔离结构共同构成第二隔离结构。
在一些实施例中，所述字线沟槽的底面与所述第一字线的顶面平齐；
或，所述字线沟槽的底面低于所述第一字线的顶面。
在一些实施例中，所述第二字线的底面平齐于所述气隙结构的底面或高于所述气隙结构的底面；所述第二字线的顶面平齐于所述气隙结构的顶面或低于所述气隙结构的顶面。
在一些实施例中，所述制备方法还包括：
于所述半导体柱的上方形成电容单元。
本公开提供的半导体结构及其制备方法，至少可以具有如下有益效果：
在本公开实施例中，分隔槽可以在同一有源组分隔为两个半导体柱，并分别在两个半导体柱的外侧壁形成两个第二字线，以及在分隔槽内形成第一字线。基于此，第二字线和第一字线在垂直于衬底的方向上错位设置，可以使得第二字线和第一字线共同构成对应半导体柱的控制字线。从而能够减少相邻有源组之间两个第二字线间的干扰，以减少器件在使用过程中的静态漏电。
再一方面，本公开还提供一种晶体管结构，包括：半导体柱以及分别位于所述半导体柱相对两侧的第一栅极和第二栅极；
其中，所述第一栅极和所述第二栅极在所述半导体柱的延伸方向上错位设置；所述第一栅极和所述第二栅极共同构成所述半导体柱的控制栅极。
在一些实施例中，所述第一栅极的顶面平齐于所述第二栅极的底面或低于所述第二栅极的底面。
在一些实施例中，所述晶体管结构还包括：位于相邻两个所述半导体柱之间且位于所述第一栅极上方的气隙结构，相邻两个所述半导体柱的底部互连。
本公开提供的晶体管结构，至少可以具有如下有益效果：
在本公开实施例中，通过在垂直于衬底的方向上错位设置第一栅极和第二栅极共同对半导体柱进行控制，从而能够减少相邻晶体管间的干扰，以减少器件在使用过程中的静态漏电。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1中的(a)图为本公开一些实施例提供的半导体结构的截面结构示意图；图1中的(b)图为图1中的(a)图所示结构的局部示意图；
图2中的(a)图为本公开一些实施例提供的半导体结构写入0时的局部示意图；图2中的(b)图为图2中的(a)图所示结构写入0时的电压-电流图；
图3中的(a)图为本公开一些实施例提供的半导体结构写入1时的局部示意图；图3中的(b)图为图3中的(a)图所示结构写入1时的电压-电流图；
图4为本公开一些实施例提供的半导体结构的制备方法的流程示意图；
图5为本公开一些实施例提供的半导体结构的制备方法中步骤S200的流程示意图；
图6为本公开一些实施例提供的半导体结构的制备方法中步骤S500的流程示意图；
图7为本公开一些实施例提供的半导体结构的制备方法中步骤S100所得结构的截面结构示意图；
图8中的(a)图为本公开一些实施例提供的半导体结构的制备方法中步骤S210所得结构的截面结构示意图；图8中的(b)图为图8中的(a)图的俯视示意图；
图9中的(a)图为本公开一些实施例提供的半导体结构的制备方法中步骤S220所得结构的截面结构示意图；图9中的(b)图为图9中的(a)图的俯视示意图；
图10为本公开一些实施例提供的半导体结构的制备方法中步骤S220中的过程结构示意图；
图11为本公开一些实施例提供的半导体结构的制备方法中形成第一层间介质层后所得结构的截面结构示意图；
图12为本公开一些实施例提供的半导体结构的制备方法中步骤S300所得结构的截面结构示意图；
图13为本公开一些实施例提供的半导体结构的制备方法中步骤S400所得结构的截面结构示意图；
图14为本公开一些实施例提供的半导体结构的制备方法中形成初始第二子隔离结构后所得结构的截面结构示意图；
图15为本公开一些实施例提供的半导体结构的制备方法中得到第二子隔离结构后所得结构的截面结构示意图；
图16为本公开一些实施例提供的半导体结构的制备方法中步骤S510所得结构的截面结构示意图；
图17为本公开一些实施例提供的半导体结构的制备方法中步骤S520所得结构的截面结构示意图；
图18为本公开一些实施例提供的半导体结构的制备方法中步骤S530所得结构的截面结构示意图；
图19为本公开一些实施例提供的半导体结构的制备方法中步骤S530所得结构的局部放大示意图；
图20为本公开一些实施例提供的晶体管结构的截面结构示意图；
图21为本公开另一些实施例提供的晶体管结构的截面结构示意图。
附图标记说明：
1、衬底；100、半导体柱；10a、中间结构；10b、初始结构；10c、第一子隔离结构；11
a、图形化掩膜层；111a、掩膜图形；112a、掩膜侧墙；2、字线结构；21、第一字线；22、第二字线；3、气隙结构；4、层间介质层；41、第一层间介质层；42、第二层间介质层；43、第三层间介质层；5、第一隔离结构；6、第二隔离结构；61a、初始第二子隔离结构；61、第二子隔离结构；62、第三子隔离结构；7、电容接触结构；
S、分隔槽；W、字线沟槽；G1、第一栅极；G2、第二栅极；G21、位于右侧的第二栅极；
G22、位于左侧的第二栅极。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的首选实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。
应当明白，当元件或层被称为“在...上”或“相邻...”时，其可以直接地在其它元件或层上或与之相邻，或者可以存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、字线和/或部分，这些元件、部件、区、层、字线和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、字线或部分与另一个元件、部件、区、层、字线或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层、字线或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一字线称为第二字线，且类似地，可以将第二字线称为第一字线；第一字线与第二字线为不同的字线。
空间关系术语例如“在...上”、“在...上方”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件的上方”或“在其上”元件或特征将取向为在其它元件或特征“下”。因此，示例性术语“在...上”、“在...上方”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应明白，当术语“组成”和/或“包括”在该说明书中使用时，可以确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时，在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本公开的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。本公开的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。因此，图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本公开的范围。
鉴于现有技术中的不足之处，本公开提供一种晶体管结构、半导体结构及其制备方法， 可以避免相邻两个字线之间的干扰，以减少器件在使用过程中的静态漏电。
本公开根据一些实施例，提供一种半导体结构。
请参阅图1中的(a)图和图1中的(b)图，在一些实施例中，该半导体结构可以包括衬底1以及字线结构2。
衬底1具有间隔分布且沿第一方向及第二方向阵列排布的多个有源组；有源组包括在第二方向上相对且通过分隔槽S隔开的两个半导体柱100。
字线结构2包括与沿第一方向排列的任一列有源组对应设置的一个第一字线21和两个第二字线22。其中，第一字线21位于分隔槽S内，两个第二字线22分别位于对应半导体柱100背离分隔槽S的侧壁上。第二字线22和第一字线21均沿第一方向延伸，且第二字线22和第一字线21在垂直于衬底1的方向上错位设置，例如，第二字线22的底面平齐于或高于第一字线21的顶面，且第二字线22底面与第一字线21的顶面的间距小于30nm。由于第一字线21和第二字线22形成的电场有发散范围，第二字线22的底面高于第一字线21的顶面但间距小于30nm不会影响晶体管的开启。
在上述实施例提供的半导体结构中，分隔槽S可以在同一有源组分隔为两个半导体柱100，并分别在两个半导体柱100的外侧壁形成两个第二字线22，以及在分隔槽S内形成第一字线21。基于此，第二字线22和第一字线21在垂直于衬底1的方向上错位设置，可以使得第二字线22和第一字线21共同构成对应半导体柱100的控制字线，也即：仅打开第一字线21或第二字线22并不足以打开对应的晶体管器件。从而能够减少相邻有源组之间两个第二字线22间的干扰，以减少器件在使用过程中的静态漏电。
此外，上述实施例提供的半导体结构，减少相邻有源组之间两个第二字线22间的干扰，还可以降低相邻第二字线22之间的寄生电容，从而能够降低寄生电容对器件的充放电速度产生影响，提升半导体结构的存储速度。
并且，在同一有源组内，分别设置于两个半导体柱100外侧壁的两个第二字线22共用同一第一字线21，一方面可以最大程度地降低半导体结构的尺寸，另一方面也可以使半导体结构的布局更合理，从而有效提升半导体结构的存储密度。
需要说明的是，在本公开实施例中，第二方向与第一方向相交。
请结合图1中的(a)图理解第一字线21和第二字线22工作过程对于改善相邻晶体管耦合的作用：对于相邻两个有源组来说，当位于左侧有源组中的第一字线21和右边的第二字线22打开时，周围电子则会聚集在位于左侧有源组中右边的沟道中，而由于左侧有源组中右边的第二字线22与位于右侧有源组中左边的第二字线22相邻，可能会导致位于右侧有源组中左边的第二字线22的电压上升，电子会聚集在位于右侧有源组中第二字线22对应的沟道中， 但由于右侧有源组中的第一字线21未开启，所以可以避免右侧有源组中沟道聚集的电子泄露。且在不改变半导体结构内的沟道长度的情况下，通过设置较短的第二字线22以减少相邻有源组中相邻第二字线22之间的寄生电容。
此外，请结合图1中的(b)图理解位于分隔槽S底部的第一字线21对于改善器件在使用过程中的静态漏电方面的作用：
以右侧的器件为例，有源组底部和顶部为第一掺杂类型，有源组中部为第二掺杂类型，例如有源组底部和顶部为N+型掺杂，用于作为源漏极，有源组中部为P型掺杂，用于作为P型沟道(P channel)。当位于底部的第一字线21打开时，由于其电压较高(例如为2V-3V)，大于位线或存储结构(例如与半导体柱顶面电接触的电容单元，图中未示出)的工作电压(例如为1V)，周围电子则会聚集在位于底部的第一字线21周围，而不会持续不断地在存储结构与位线之间泄露。
本公开对于衬底1的材质并不做具体限定。作为示例，衬底1可以包括硅(Si)衬底、硅锗(SiGe)衬底、硅锗碳(SiGeC)衬底、碳化硅(SiC)衬底、砷化镓(GaAs)衬底、砷化铟(InAs)衬底、磷化铟(InP)衬底或其它的III/V半导体衬底100或II/VI半导体衬底100；或者，衬底1也可以包括Si/SiGe、Si/SiC、绝缘体上硅(SOI)或绝缘体上硅锗等衬底。
本公开对于字线结构2的材质并不做具体限定。作为示例，字线结构2的材质可以包括但不仅限于金属材料，例如钨、钴、氮化钛等。
请继续参阅图1中的(a)图，在一些实施例中，该半导体结构还可以包括气隙结构3。气隙结构3位于分隔槽S内，并位于第一字线21的上方，且与第二字线22在第二方向上相对。
在上述实施例提供的半导体结构中，分隔槽S内的气隙结构3可以降低相邻有源组之间的浮体效应，从而进一步减少器件在使用过程中的静态漏电。
本公开对于第一字线21与第二字线22的位置关系并不做具体限定。作为示例，第一字线21的顶面可以与第二字线22的底面相平齐；或者，第一字线21的顶面也可以低于第二字线22的底面。
本公开对于第二字线22与气隙结构3的位置关系亦不做具体限定。作为示例，第二字线22的底面可以与气隙结构3的底面相平齐；或者，第二字线22的底面也可以高于气隙结构3的底面。作为示例，第二字线22的顶面可以与气隙结构3的顶面相平齐；或者，第二字线22的顶面也可以低于气隙结构3的顶面。
请继续参阅图1中的(a)图，在一些实施例中，该半导体结构还可以包括层间介质层4。层间介质层4覆盖半导体柱100垂直于第二方向的侧壁，且位于半导体柱100和第一字线21之间以及半导体柱100和第二字线22之间。
需要说明的是，在另一些实施例中，气隙结构3与半导体柱100之间可以不设置层间介质层4，这也是允许的。譬如，层间介质层4在半导体柱100上的正投影可以与第一字线21在半导体柱100上的正投影重叠或大致重叠，并与第二字线22在半导体柱100上的正投影重叠或大致重叠。
请继续参阅图1中的(a)图，在一些实施例中，该半导体结构还可以包括第一隔离结构5以及第二隔离结构6。
第一隔离结构5位于分隔槽S内且封闭气隙结构3，第一隔离结构5可以用于定义气隙结构3的顶面。第二隔离结构6位于相邻有源组之间的间隔内且覆盖位于间隔内的第二字线22及层间介质层4。
本公开对于第一隔离结构5的材质并不做具体限定。作为示例，第一隔离结构5的材质可以包括但不仅限于氮化硅(SiN)、氮氧化硅(SiON)以及氧化硅(SiO2)等或其组合。
在一些实施例中，该半导体结构还可以包括多个电容单元。
示例的，多个电容单元(图中未示出)可以分别设置于对应半导体柱100的上方。
图2中的(a)图和图2中的(b)图示出了写入0(例如为0V)时，流经两个电容单元所对应的漏极至源极的电流IDS，以及图3中的(a)图和图3中的(b)图示出了写入1(例如为1V)时，流经两个电容单元所对应的存储节点NC、NC0的漏极至源极电流IDS。其中，Vg指的是施加于存储节点的电压；IDS指的是流经存储节点的电流。
如图2中的(a)图及图2中的(b)图所示，当写入0时，若打开(On)左侧的第二字线22以及位于底部的第一字线21，右侧的第二字线22保持关闭(Off)，则左侧的器件被打开，电流流经对应的存储节点NC，而几乎无电流流经另一侧的存储节点NC0，即右侧的器件能够保持关断状态。
如图3中的(a)图及图3中的(b)图所示，当写入1时，若打开左侧的第二字线22以及位于底部的第一字线21，右侧的第二字线22保持关闭，则左侧的器件被打开，电流流经对应的存储节点NC，而几乎无电流流经另一侧的存储节点NC0，即右侧的器件能够保持关断状态。
作为示例，如图1中的(a)图所示，可以在半导体柱100上对准设置电容接触结构7，电容接触结构7的材料可以是多晶硅、金属或金属硅化物等。有利于改善电容单元与对应半导体柱100的接触情况。
本公开还根据一些实施例，提供一种半导体结构的制备方法。
请参阅图4，在一些实施例中，该半导体结构的制备方法可以包括如下的步骤：
S100：提供衬底。
S200：于衬底内形成平行间隔排列且沿第一方向延伸的多个分隔槽，以得到多个中间结构。
S300：于分隔槽内形成第一字线。
S400：图形化中间结构，获得沿第一方向及第二方向阵列排布的多个有源组；有源组包括在第二方向上相对且通过分隔槽隔开的两个半导体柱；第二方向与第一方向相交。
S500：于半导体柱背离分隔槽的侧壁上形成第二字线。
需要说明的是，第二字线和第一字线均沿第一方向延伸，且第二字线和第一字线在垂直于衬底的方向上错位设置，例如，第二字线的底面平齐于或高于第一字线的顶面，且第二字线底面与第一字线的顶面的间距小于30nm。
在上述实施例提供的半导体结构的制备方法中，分隔槽S可以在同一有源组分隔为两个半导体柱100，并分别在两个半导体柱100的外侧壁形成两个第二字线22，以及在分隔槽S内形成第一字线21。基于此，第二字线22和第一字线21在垂直于衬底1的方向上错位设置，可以使得第二字线22和第一字线21共同构成对应半导体柱100的控制字线，也即：仅打开第一字线21或第二字线22并不足以打开对应的器件。从而能够减少相邻有源组之间两个第二字线22间的干扰，以减少器件在使用过程中的静态漏电。
此外，上述实施例提供的半导体结构的制备方法，减少相邻有源组之间两个第二字线22间的干扰，还可以降低相邻第二字线22之间的寄生电容，从而能够降低寄生电容对器件的充放电速度产生影响，提升半导体结构的存储速度。
并且，在同一有源组内，分别形成于两个半导体柱100外侧壁的两个第二字线22共用同一第一字线21，一方面可以最大程度地降低半导体结构的尺寸，另一方面也可以使半导体结构的布局更合理，从而有效提升半导体结构的存储密度。
在一些实施例中，图形化中间结构之前，该制备方法还可以包括如下的步骤：于分隔槽中形成第一隔离结构。
第一隔离结构用于定义气隙结构的顶面，气隙结构位于分隔槽内第一字线的上方。需要说明的是，第二字线与气隙结构在第二方向上相对。
在上述实施例提供的半导体结构的制备方法中，分隔槽S内的气隙结构3可以降低相邻有源组之间的浮体效应，从而进一步减少器件在使用过程中的静态漏电。
在一些实施例中，于分隔槽内形成第一字线之前，该制备方法还可以包括如下的步骤：形成覆盖分隔槽内壁的第一层间介质层。
需要说明的是，第一字线形成于第一层间介质层上并填充部分分隔槽。
在一些实施例中，于分隔槽中形成第一隔离结构之前，该制备方法还可以包括如下的步 骤：形成至少覆盖第一字线顶面的第二层间介质层。
需要说明的是，气隙结构形成于第二层间介质层上。
请参阅图5，在一些实施例中，于衬底内形成平行间隔排列且沿第一方向延伸的多个分隔槽，以得到多个中间结构，可以包括如下的步骤：
S210：图形化衬底，形成平行间隔排列且沿第二方向延伸的多个初始结构。
S220：于相邻初始结构之间的间隔形成第一子隔离结构。
S230：于多个初始结构及第一子隔离结构中形成沿第一方向的多个分隔槽，并得到中间结构。
在一些实施例中，其特征在于，图形化中间结构之后，且于半导体柱背离分隔槽的侧壁上形成第二字线之前，该制备方法还可以包括如下的步骤：于在第二方向上相邻的有源组的间隔内形成初始第二子隔离结构；回刻蚀初始第二子隔离结构，形成字线沟槽，并得到第二子隔离结构。
请参阅图6，在一些实施例中，步骤S500于半导体柱背离分隔槽的侧壁上形成第二字线，可以包括如下的步骤：
S510：于字线沟槽的内壁上保形形成第三层间介质层。
S520：于第三层间介质层背离两侧半导体柱的侧壁上分别形成第二字线；同一字线沟槽内的两个第二字线之间具有间隔。
S530：于字线沟槽内形成覆盖第二子隔离结构、第二字线及第三层间介质层三者裸露表面的第三子隔离结构；其中，第三子隔离结构和第二子隔离结构、第一子隔离结构共同构成第二隔离结构。
在一些实施例中，该制备方法还可以包括如下的步骤：于半导体柱的上方形成电容单元。
应该理解的是，虽然图4至图6的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图4至图6中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
为了更清楚的说明上述一些实施例中的制备方法，以下请结合图7至图19理解本公开的一些实施例。
请参阅图7，在步骤S100中，提供衬底1。
请参阅图8至图10，在步骤S200中，于衬底1内形成平行间隔排列且沿第一方向X延 伸的多个分隔槽S，以得到多个中间结构10a。
在一些实施例中，步骤S200于衬底1内形成平行间隔排列且沿第一方向延伸的多个分隔槽S，以得到多个中间结构10a，具体可以表现为如下的步骤S210-S230：
在步骤S210中，如图8中的(a)图和图8中的(b)图所示，图形化衬底1，形成平行间隔排列且沿第二方向Y延伸的多个初始结构10b。
在步骤S220中，如图8中的(a)图和图8中的(b)图所示，于相邻初始结构10b之间的间隔形成第一子隔离结构10c。
在步骤S230中，如图9至图10所示，于多个初始结构10b及第一子隔离结构中形成沿第一方向的多个分隔槽S，并得到中间结构10a。
本公开对于步骤S230中形成多个分隔槽S的方式并不做具体限定。作为示例，图10示出了一些实施例中形成多个分隔槽S的过程结构图，可以采用如下的方式在初始结构10b和第一子隔离结构中形成分隔槽S：
于衬底1上形成图形化掩膜层11a；基于图形化掩膜层11a形成沿第一方向的多个分隔槽S。
本公开对于前述步骤中图形化掩膜层11a的形式并不做具体限定。例如，图形化掩膜层11a可以是单一膜层，也可以包括多个膜层；当图形化掩膜层11a包括多个膜层时，多个膜层可以在纵向堆叠设置，也可以在横向排列设置。作为示例，如图10所示，图形化掩膜层11a可以包括掩膜图形111a以及位于掩膜图形111a侧壁的掩膜侧墙112b。其中，掩膜侧墙112b的材质与掩膜图形111a的材质相同或不同均是允许的。
请参阅图11，在一些实施例中，该制备方法还可以包括如下的步骤：
形成覆盖分隔槽S内壁的第一层间介质层41。
请参阅图12，在步骤S300中，于分隔槽S内形成第一字线21。
需要说明的是，在一些实施例中，步骤S300在形成覆盖分隔槽S内壁的第一层间介质层41之后执行。并且，如图12所示，第一字线21应当形成于第一层间介质层41上，并填充部分分隔槽S。
请继续参阅图12，在一些实施例中，该制备方法还可以包括如下的步骤：
形成至少覆盖第一字线21顶面的第二层间介质层42。气隙结构3形成于第二层间介质层42上。
需要说明的是，在一些实施例中，气隙结构3与分隔槽S内壁之间可以不设置第一层间介质层41；也即，第一层间介质层41覆盖全部的分隔槽S内壁，或者覆盖部分的分隔槽S内壁，均是允许的。譬如，第一层间介质层41在半导体柱100上沿第二方向Y的正投影可 以与第一字线21在半导体柱100上的正投影重叠或大致重叠。
请继续参阅图12，在一些实施例中，该制备方法还可以包括如下的步骤：
于分隔槽S中形成第一隔离结构5。具体的，第一隔离结构5可以用于定义气隙结构3的顶面，气隙结构3位于分隔槽S内第一字线21的上方。
需要说明的是，在一些实施例中，上述形成第一隔离结构5的步骤在形成第二层间介质层42之后执行。
请参阅图12-图13，在步骤S400中，图形化中间结构10a，获得沿第一方向及第二方向阵列排布的多个有源组。具体的，有源组包括在第二方向上相对且通过分隔槽S隔开的两个半导体柱100。例如，可以去除掩膜图形111a，然后以掩膜侧墙112b和位于中间结构10a上方的部分第一隔离结构5作为掩膜对中间结构10a进行刻蚀，以形成由第二方向Y排布的多个沟槽分隔开的多个有源组。
请继续参阅图13，在一些实施例中，在步骤S400图形化中间结构10a之前，该制备方法还可以包括如下的步骤：去除图形化掩膜层11a以及位于中间结构10a上方的部分第一隔离结构5。
本公开对于去除图形化掩膜层11a以及部分第一隔离结构5的方式并不做具体限定。作为示例，可以采用但不仅限于化学机械研磨(Chemical-Mechanical Polishing)工艺去除图形化掩膜层11a以及位于中间结构10a上方的第一隔离结构5。
请参阅图14至图15，在一些实施例中，在步骤S400图形化中间结构10a之后，该制备方法还可以包括如下的步骤：
如图14所示，于在第二方向上相邻的有源组的间隔内形成初始第二子隔离结构61a；如图15所示，回刻蚀初始第二子隔离结构61a，形成字线沟槽W，并得到第二子隔离结构61。
本公开对于字线沟槽W的位置并不做具体限定。作为示例，字线沟槽W的底面可以与第一字线21的顶面平齐；或者，字线沟槽W的底面也可以低于第一字线21的顶面；或者，字线沟槽W的底面也可以高于第一字线21的顶面。
请参阅图16至图19，在步骤S500中，于半导体柱100背离分隔槽S的侧壁上形成第二字线22。
其中，第二字线22和第一字线21均沿第一方向延伸，且第二字线22和第一字线21在垂直于衬底1的方向上错位设置。作为示例，第二字线22还可以与气隙结构3在第二方向上相对。
需要说明的是，在一些实施例中，上述步骤S500在得到第二子隔离结构之后执行。
本公开对于第二字线22的位置并不做具体限定。作为示例，第二字线22的底面可以与 气隙结构3的底面相平齐；或者，第二字线22的底面也可以高于气隙结构3的底面。作为示例，第二字线22的顶面可以平齐于气隙结构3的顶面；或者，第二字线22的顶面也可以低于气隙结构3的顶面。
在一些实施例中，步骤S500于半导体柱100背离分隔槽S的侧壁上形成第二字线22，具体可以表现为如下的步骤S510-S530：
在步骤S510中，如图16所示，于字线沟槽W的内壁上保形形成第三层间介质层43。
在步骤S520中，如图17所示，于第三层间介质层43背离两侧半导体柱100的侧壁上分别形成第二字线22。其中，同一字线沟槽W内的两个第二字线22之间具有间隔。
在步骤S530中，如图18和图19所示，于字线沟槽W内形成覆盖第二子隔离结构61、第二字线22及第三层间介质层43三者裸露表面的第三子隔离结构62。其中，第三子隔离结构62和第二子隔离结构61、第一子隔离结构共同构成第二隔离结构6。
本公开对于步骤S510中形成第三层间介质层43的方式并不做具体限定。作为示例，可以采用但不限于原位水汽生长(in-situ steam generation，简称ISSG)工艺和/或原子层沉积(Atomic layer deposition，简称ALD)工艺等方式形成第三层间介质层43。本公开对于步骤S510中形成的第三层间介质层43的材质亦不做具体限定。作为示例，第三层间介质层43的材质可以包括但不仅限于氧化物。
本公开对于步骤S520中形成第二字线22的方式亦不做具体限定。作为示例，可以采用但不限于物理气相沉积(Physical Vapor Deposition，简称PVD)工艺或者蒸镀工艺等方式在第三层间介质层43背离两侧半导体柱100的侧壁上形成金属材料，然后执行竖直方向的各向异性刻蚀以去除金属材料的水平部分及金属材料的部分竖直部分，剩余的金属材料作为第二字线22。
在一些实施例中，该制备方法还可以包括如下的步骤：于半导体柱100的上方形成电容单元。
需要注意的是，本公开提供的半导体结构的制备方法均可用于制备对应的半导体结构，故而半导体结构的制备方法实施例与半导体结构实施例之间的技术特征，在不产生冲突的前提下可以相互替换及补充，以使得本领域技术人员能够获悉本公开的技术内容。
本公开还根据一些实施例，提供一种晶体管结构。
请参阅图20，在一些实施例中，该晶体管结构可以包括半导体柱100以及分别位于半导体柱100相对两侧的第一栅极G1和第二栅极G2。
第一栅极G1和第二栅极G2在半导体柱100的延伸方向上错位设置，第一栅极G1和第二栅极G2可以共同构成半导体柱100的控制栅极。例如，第二栅极G2的底面平齐于或高于 第一栅极G1的顶面，且第二栅极G2底面与第一栅极G1的顶面的间距小于30nm。
在上述实施例提供的晶体管结构中，第一栅极G1和第二栅极G2在垂直于衬底1的方向上错位设置，可以使得第一栅极G1和第二栅极G2共同构成对应半导体柱100的控制栅极，也即：仅对第一栅极G1或第二栅极G2施加电压并不足以打开对应的晶体管结构。如此，能够避免对相邻晶体管产生干扰，以减少器件在使用过程中的静态漏电。
此外，上述实施例提供的晶体管结构，避免对相邻晶体管产生干扰，还可以降低相邻第一栅极G1或相邻第二栅极G2之间的寄生电容，从而能够降低寄生电容对器件的充放电速度产生影响，提升晶体管结构的存储速度。
并且，第一栅极G1和第二栅极G2在半导体柱100的延伸方向上错位设置的方式，一方面可以最大程度地降低晶体管结构的尺寸，另一方面也可以使晶体管结构的布局更合理，从而有效提升晶体管结构的存储密度。针对相同沟道长度的晶体管来说，第一栅极G1和第二栅极G1相对于整体的栅极具有较低的栅极长度，能够降低栅极制作工艺难度。
在上述实施例提供的晶体管结构中，第一栅极G1可以为位于其相对的两侧的晶体管结构所共用。
例如，图21中的虚线框示意出了两个晶体管结构；当对位于左侧的第二栅极G22以及第一栅极G1施加电压时，图21虚线框中左侧的晶体管结构被打开，此时，图21虚线框中右侧的晶体管结构保持关闭状态；当对位于右侧的第二栅极G21以及第一栅极G1施加电压时，图21虚线框中右侧的晶体管结构被打开，此时，图21虚线框中左侧的晶体管结构保持关闭状态。此外，当位于左侧的第二栅极G22以及位于右侧的第二栅极G21均未被施加电压时，即使附近其他晶体管结构被打开，导致位于左侧的第二栅极G22或位于右侧的第二栅极G21电压被拉高，由于第一栅极G1不会受到干扰，仍能通过第一栅极G1端的电压对相应的晶体管结构进行精准控制。
本公开对于第一栅极G1和第二栅极G2的位置关系并不做具体限定。作为示例，第一栅极G1的顶面可以与第二栅极G2的底面相平齐；或者，第一栅极G1的顶面可以低于第二栅极G2的底面。
请继续参阅图20，在一些实施例中，该晶体管结构还可以包括位于相邻两个半导体柱100之间且位于第一栅极G1上方的气隙结构3。
需要说明的是，在一些实施例中，相邻两个半导体柱100的底部可以互连。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。

Claims (20)

  1. 一种半导体结构，包括：
    衬底(1)，具有间隔分布且沿第一方向(X)及第二方向(Y)阵列排布的多个有源组；所述有源组包括在所述第二方向(Y)上相对且通过分隔槽(S)隔开的两个半导体柱(100)；所述第二方向(Y)与所述第一方向(X)相交；
    字线结构(2)；所述字线结构(2)包括与沿所述第一方向(X)排列的任一列所述有源组对应设置的一个第一字线(21)和两个第二字线(22)；所述第一字线(21)位于所述分隔槽(S)内，两个所述第二字线(22)分别位于对应所述半导体柱(100)背离所述分隔槽(S)的侧壁上；
    其中，所述第二字线(22)和所述第一字线(21)均沿所述第一方向(X)延伸，且所述第二字线(22)和所述第一字线(21)在垂直于所述衬底(1)的方向上错位设置。
  2. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括：
    气隙结构(3)，位于所述分隔槽(S)内，并位于所述第一字线(21)的上方，且与所述第二字线(22)在所述第二方向(Y)上相对。
  3. 根据权利要求1-2任一项所述的半导体结构，其中，所述第一字线(21)的顶面平齐于所述第二字线(22)的底面或低于所述第二字线(22)的底面。
  4. 根据权利要求2所述的半导体结构，其中，所述第二字线(22)的底面平齐于所述气隙结构(3)的底面或高于所述气隙结构(3)的底面；所述第二字线(22)的顶面平齐于所述气隙结构(3)的顶面或低于所述气隙结构(3)的顶面。
  5. 根据权利要求2所述的半导体结构，其中，所述半导体结构还包括：
    层间介质层(4)，覆盖所述半导体柱(100)垂直于所述第二方向(Y)的侧壁，且位于所述半导体柱(100)和所述第一字线(21)之间及所述半导体柱(100)和所述第二字线(22)之间。
  6. 根据权利要求5所述的半导体结构，其中，所述半导体结构还包括：
    第一隔离结构(5)，位于所述分隔槽(S)内且封闭所述气隙结构(3)；所述第一隔离结构(5)用于定义所述气隙结构(3)的顶面；
    第二隔离结构(6)，位于相邻所述有源组之间的间隔内且覆盖位于所述间隔内的所述第二字线(22)及所述层间介质层(4)。
  7. 根据权利要求1-6中任一项所述的半导体结构，其中，所述半导体结构还包括：
    多个电容接触结构(7)，分别设置于对应所述半导体柱(100)的上方。
  8. 根据权利要求3所述的半导体结构，其中，所述第二字线(22)底面与所述第一字线(21)的顶面的间距小于30nm。
  9. 一种半导体结构的制备方法，包括：
    提供衬底(1)；
    于所述衬底(1)内形成平行间隔排列且沿第一方向(X)延伸的多个分隔槽(S)，以得到多个中间结构(10a)；
    于所述分隔槽(S)内形成第一字线(21)；
    图形化所述中间结构(10a)，获得沿所述第一方向(X)及第二方向(Y)阵列排布的多个有源组；所述有源组包括在第二方向(Y)上相对且通过所述分隔槽(S)隔开的两个半导体柱(100)；所述第二方向(Y)与所述第一方向(X)相交；
    于所述半导体柱(100)背离所述分隔槽(S)的侧壁上形成第二字线(22)；
    其中，所述第二字线(22)和所述第一字线(21)均沿所述第一方向(X)延伸，且所述第二字线(22)和所述第一字线(21)在垂直于所述衬底(1)的方向上错位设置。
  10. 根据权利要求9所述的半导体结构的制备方法，其中，所述图形化所述中间结构(10a)之前，所述制备方法还包括：
    于所述分隔槽(S)中形成第一隔离结构(5)，所述第一隔离结构(5)用于定义气隙结构(3)的顶面，所述气隙结构(3)位于所述分隔槽(S)内所述第一字线(21)的上方；
    其中，所述第二字线(22)还与所述气隙结构(3)在所述第二方向(Y)上相对。
  11. 根据权利要求10所述的半导体结构的制备方法，其中，
    所述于所述分隔槽(S)内形成第一字线(21)之前，所述制备方法还包括：形成覆盖所述分隔槽(S)内壁的第一层间介质层(41)；其中，所述第一字线(21)形成于所述第一层间介质层(41)上并填充部分所述分隔槽(S)；
    于所述分隔槽(S)中形成第一隔离结构(5)之前，所述制备方法还包括：形成至少覆盖所述第一字线(21)顶面的第二层间介质层(42)；其中，所述气隙结构(3)形成于所述第二层间介质层(42)上。
  12. 根据权利要求10所述的半导体结构的制备方法，其中，所述于所述衬底(1)内形成平行间隔排列且沿第一方向(X)延伸的多个分隔槽(S)，以得到多个中间结构(10a)，包括：
    图形化所述衬底(1)，形成平行间隔排列且沿所述第二方向(Y)延伸的多个初始结构(10b)；
    于相邻所述初始结构(10b)之间的间隔形成第一子隔离结构(10c)；
    于多个所述初始结构(10b)及所述第一子隔离结构(10c)中形成沿所述第一方向(X)的多个分隔槽(S)，并得到所述中间结构(10a)。
  13. 根据权利要求12所述的半导体结构的制备方法，其中，
    所述图形化所述中间结构(10a)之后，且于所述半导体柱(100)背离所述分隔槽(S)的侧壁上形成第二字线(22)之前，所述制备方法还包括：
    于在所述第二方向(Y)上相邻的所述有源组的间隔内形成初始第二子隔离结构(61a)；
    回刻蚀所述初始第二子隔离结构(61a)，形成字线沟槽(W)，并得到第二子隔离结构(61)；
    所述于所述半导体柱(100)背离所述分隔槽(S)的侧壁上形成第二字线(22)，包括：
    于所述字线沟槽(W)的内壁上保形形成第三层间介质层(43)；
    于所述第三层间介质层(43)背离两侧所述半导体柱(100)的侧壁上分别形成所述第二字线(22)；同一所述字线沟槽(W)内的两个所述第二字线(22)之间具有间隔；
    于所述字线沟槽(W)内形成覆盖所述第二子隔离结构(61)、所述第二字线(22)及所述第三层间介质层(43)三者裸露表面的第三子隔离结构(62)；其中，所述第三子隔离结构(62)和所述第二子隔离结构(61)、所述第一子隔离结构(10c)共同构成第二隔离结构(6)。
  14. 根据权利要求13所述的半导体结构的制备方法，其中，
    所述字线沟槽(W)的底面与所述第一字线(21)的顶面平齐；
    或，所述字线沟槽(W)的底面低于所述第一字线(21)的顶面。
  15. 根据权利要求13所述的半导体结构的制备方法，其中，所述第二字线(22)的底面平齐于所述气隙结构(3)的底面或高于所述气隙结构(3)的底面；所述第二字线(22)的顶面平齐于所述气隙结构(3)的顶面或低于所述气隙结构(3)的顶面。
  16. 根据权利要求9-15中任一项所述的半导体结构的制备方法，其中，所述制备方法还包括：
    于所述半导体柱(100)的上方形成电容接触结构(7)。
  17. 一种晶体管结构，包括：半导体柱(100)以及分别位于所述半导体柱(100)相对两侧的第一栅极(G1)和第二栅极(G2)；
    其中，所述第一栅极(G1)和所述第二栅极(G2)在所述半导体柱(100)的延伸方向上错位设置；所述第一栅极(G1)和所述第二栅极(G2)共同构成所述半导体柱(100)的控制栅极。
  18. 根据权利要求17所述的晶体管结构，其中，所述第一栅极(G1)的顶面平齐于所述第二栅极(G2)的底面或低于所述第二栅极(G2)的底面。
  19. 根据权利要求17所述的晶体管结构，其中，所述晶体管结构还包括：位于相邻两个所述半导体柱(100)之间且位于所述第一栅极(G1)上方的气隙结构(3)，相邻两个所述半导体柱(100)的底部互连。
  20. 根据权利要求17-19任一项所述的晶体管结构，其中，所述第二栅极(G2)底面与所述第一栅极(G1)的顶面的间距小于30nm。
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