WO2024222316A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024222316A1
WO2024222316A1 PCT/CN2024/082370 CN2024082370W WO2024222316A1 WO 2024222316 A1 WO2024222316 A1 WO 2024222316A1 CN 2024082370 W CN2024082370 W CN 2024082370W WO 2024222316 A1 WO2024222316 A1 WO 2024222316A1
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WO
WIPO (PCT)
Prior art keywords
multiplexing
group
lines
line
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2024/082370
Other languages
English (en)
French (fr)
Inventor
刘聪
赵二瑾
宋江
蒋志亮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to EP24795699.8A priority Critical patent/EP4651692A4/en
Publication of WO2024222316A1 publication Critical patent/WO2024222316A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • This article relates to but is not limited to the field of display technology, and in particular to a display panel and a display device.
  • OLED Organic light emitting diode
  • TFT thin film transistor
  • Embodiments of the present disclosure provide a display panel and a display device.
  • this embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing data lines, and N multiplexing control lines.
  • the substrate comprises a display area and a first frame area located on at least one side of the display area.
  • a plurality of sub-pixels and a plurality of data lines are located in the display area, and the plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels.
  • a plurality of multiplexing circuits, a plurality of multiplexing data lines, and N multiplexing control lines are located in the first frame area, wherein N is equal to 2n+1, and n is an integer greater than 0.
  • At least one of the plurality of multiplexing circuits is electrically connected to the N multiplexing control lines, a multiplexing data line, and a plurality of data lines, and is configured to provide the data signals transmitted by the multiplexing data lines to the plurality of data lines under the control of the N multiplexing control lines.
  • Each of the multiplexed data lines overlaps with at least n multiplexed control lines in their orthographic projections on the substrate, or the multiplexed data lines do not overlap with the orthographic projections of the N multiplexed control lines on the substrate.
  • the N multiplexing control lines include a first group of multiplexing control lines and a second group of multiplexing control lines, the first group of multiplexing control lines includes n multiplexing control lines, and the second group of multiplexing control lines includes n+1 multiplexing control lines.
  • the plurality of multiplexing data lines include a first group of multiplexing data lines and a second group of multiplexing data lines, each multiplexing data line in the first group of multiplexing data lines overlaps with n multiplexing control lines in the first group of multiplexing control lines in an orthographic projection of the substrate, and each multiplexing data line in the second group of multiplexing data lines overlaps with n+1 multiplexing control lines in the second group of multiplexing control lines.
  • the plurality of sub-pixels include: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light; at least one of the N multiplexing control lines is configured to control the multiplexing circuit to provide data signals to the plurality of first sub-pixels through the data lines, at least one of the N multiplexing control lines is configured to control the multiplexing circuit to provide data signals to the plurality of second sub-pixels through the data lines, and at least one of the N multiplexing control lines is configured to control the multiplexing circuit to provide data signals to the plurality of third sub-pixels through the data lines.
  • n 4.
  • the N multiplexing control lines include: a first multiplexing control line, a second multiplexing control line, a third multiplexing control line, a fourth multiplexing control line, a fifth multiplexing control line, a sixth multiplexing control line, a seventh multiplexing control line, an eighth multiplexing control line, and a ninth multiplexing control line.
  • the plurality of sub-pixels include a first group of sub-pixels, a second group of sub-pixels, and a third group of sub-pixels
  • the first group of sub-pixels includes a first group of first sub-pixels, a first group of second sub-pixels, and a first group of third sub-pixels
  • the second group of sub-pixels includes a second group of first sub-pixels, a second group of second sub-pixels, and a second group of third sub-pixels
  • the third group of sub-pixels includes a third group of first sub-pixels, a third group of second sub-pixels, and a third group of third sub-pixels.
  • the first multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the first group of first sub-pixels;
  • the second multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the first group of second sub-pixels;
  • the third multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the first group of third sub-pixels;
  • the fourth multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the second group of first sub-pixels;
  • the fifth multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the second group of second sub-pixels;
  • the sixth multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the second group of third sub-pixels;
  • the seventh multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the third group of first sub-pixels;
  • the eighth multiplexing control line is configured
  • the first group of multiplexing control lines includes: a fourth multiplexing control line, a seventh multiplexing control line, an eighth multiplexing control line and a ninth multiplexing control line;
  • the second group of multiplexing control lines includes: a first multiplexing control line, a second multiplexing control line, a third multiplexing control line, a sixth multiplexing control line and a fifth multiplexing control line.
  • the fourth multiplexing control line, the seventh multiplexing control line, the eighth multiplexing control line, and the ninth multiplexing control line are sequentially arranged in a direction away from the second group of multiplexing data lines.
  • the first multiplexing control line, the second multiplexing control line, the third multiplexing control line, the sixth multiplexing control line, and the fifth multiplexing control line are sequentially arranged in a direction away from the first group of multiplexing data lines.
  • the multiplexing control line that controls the multiplexing circuit to provide a data signal to the first sub-pixel is a first-type multiplexing control line
  • the multiplexing control line that controls the multiplexing circuit to provide a data signal to the second sub-pixel is a second-type multiplexing control line
  • the multiplexing control line that controls the multiplexing circuit to provide a data signal to the third sub-pixel is a third-type multiplexing control line.
  • the first group of multiplexing control lines includes: the first-type multiplexing control line and at least one third-type multiplexing control line; the second group of multiplexing control lines includes: the third-type multiplexing control line and the remaining third-type multiplexing control lines.
  • the N multiplexing control lines include: a first multiplexing control line, a second multiplexing control line, a third multiplexing control line, a fourth multiplexing control line, a fifth multiplexing control line, a sixth multiplexing control line, a seventh multiplexing control line, an eighth multiplexing control line, and a ninth multiplexing control line.
  • the plurality of sub-pixels include a first group of sub-pixels, a second group of sub-pixels, and a third group of sub-pixels
  • the first group of sub-pixels includes a first group of first sub-pixels, a first group of second sub-pixels, and a first group of third sub-pixels
  • the second group of sub-pixels includes a second group of first sub-pixels, a second group of second sub-pixels, and a second group of third sub-pixels
  • the third group of sub-pixels includes a third group of first sub-pixels, a third group of second sub-pixels, and a third group of third sub-pixels.
  • the first multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the first group of first sub-pixels;
  • the second multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the first group of second sub-pixels;
  • the third multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the first group of third sub-pixels;
  • the fourth multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the second group of first sub-pixels;
  • the fifth multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the second group of second sub-pixels;
  • the sixth multiplexing control line is configured to control the multiplexing circuit
  • the data signal is provided to the second group of third sub-pixels;
  • the seventh multiplexing control line is configured to control the multiplexing circuit to provide data signals to the third group of first sub-pixels;
  • the eighth multiplexing control line is configured to
  • the first group of multiplexing control lines includes: a first multiplexing control line, a fourth multiplexing control line, a seventh multiplexing control line, and a third multiplexing control line;
  • the second group of multiplexing control lines includes: a second multiplexing control line, a fifth multiplexing control line, an eighth multiplexing control line, a sixth multiplexing control line, and a ninth multiplexing control line.
  • the plurality of multiplexed data lines include a first group of multiplexed data lines and a second group of multiplexed data lines, and the number of multiplexed control lines overlapped by each multiplexed data line of the first group of multiplexed data lines is the same as the number of multiplexed control lines overlapped by each multiplexed data line of the second group of multiplexed data lines.
  • the N multiplexing control lines include a first group of multiplexing control lines and a second group of multiplexing control lines, the first group of multiplexing control lines includes n multiplexing control lines, and the second group of multiplexing control lines includes n+1 multiplexing control lines.
  • Each multiplexing data line in the first group of multiplexing data lines overlaps with an extension of n multiplexing control lines in the first group of multiplexing control lines and one multiplexing control line in the second group of multiplexing control lines in an orthographic projection of the substrate, and each multiplexing data line in the second group of multiplexing data lines overlaps with n+1 multiplexing control lines in the second group of multiplexing control lines in an orthographic projection of the substrate.
  • the plurality of sub-pixels include: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light.
  • the multiplexing control line having an extension line in the second group of multiplexing control lines is configured to control the multiplexing circuit to provide a data signal to the third sub-pixel.
  • the N multiplexing control lines include: a first multiplexing control line, a second multiplexing control line, a third multiplexing control line, a fourth multiplexing control line, a fifth multiplexing control line, a sixth multiplexing control line, a seventh multiplexing control line, an eighth multiplexing control line, and a ninth multiplexing control line.
  • the plurality of sub-pixels include a first group of sub-pixels, a second group of sub-pixels, and a third group of sub-pixels
  • the first group of sub-pixels includes a first group of first sub-pixels, a first group of second sub-pixels, and a first group of third sub-pixels
  • the second group of sub-pixels includes a second group of first sub-pixels, a second group of second sub-pixels, and a second group of third sub-pixels
  • the third group of sub-pixels includes a third group of first sub-pixels, a third group of second sub-pixels, and a third group of third sub-pixels.
  • the first multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the first group of first sub-pixels;
  • the second multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the first group of second sub-pixels;
  • the third multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the first group of third sub-pixels;
  • the fourth multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the second group of first sub-pixels;
  • the fifth multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the second group of second sub-pixels;
  • the sixth multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the second group of third sub-pixels;
  • the seventh multiplexing control line is configured to control the multiplexing circuit to provide a data signal to the third group of first sub-pixels;
  • the eighth multiplexing control line is configured
  • the first group of multiplexing control lines includes: a sixth multiplexing control line, a seventh multiplexing control line, an eighth multiplexing control line and a ninth multiplexing control line;
  • the second group of multiplexing control lines includes: a first multiplexing control line, a second multiplexing control line, a third multiplexing control line, a fourth multiplexing control line and a fifth multiplexing control line; wherein the third multiplexing control line has an extension line.
  • each multiplexed data line of the first group of multiplexed data lines and the second group of multiplexed data lines overlaps with an orthographic projection of the N multiplexed control lines on the substrate.
  • the N multiplexing control lines each have an extension line; the N multiplexing control lines include a first group of multiplexing control lines and a second group of multiplexing control lines, the first group of multiplexing control lines includes n multiplexing control lines, and the second group of multiplexing control lines includes n+1 multiplexing control lines.
  • the data line overlaps with the extension lines of n multiplexed control lines in the first group of multiplexed control lines and n+1 multiplexed control lines in the second group of multiplexed control lines on the orthographic projection of the substrate, and each multiplexed data line in the second group of multiplexed data lines overlaps with the extension lines of n+1 multiplexed control lines in the second group of multiplexed control lines and n multiplexed control lines in the first group of multiplexed control lines on the orthographic projection of the substrate.
  • the first color light is red light
  • the second color light is green light
  • the third color light is blue light
  • the first border area includes at least: a first signal access area and a second signal access area, the second signal access area is located on a side of the first signal access area away from the display area; the first signal access area is provided with a first group of first contact pads; the second signal access area is provided with a plurality of multiplexing control contact pads; the plurality of multiplexing data lines are connected to the first group of first contact pads of the first signal access area, and the N multiplexing control lines are connected to the plurality of multiplexing control contact pads of the second signal access area.
  • the first signal access area is further provided with a second group of first contact pads, and the second group of first contact pads is located on a side of the first group of first contact pads away from the display area; the second signal access area is further provided with a group of intermediate contact pads; the second group of first contact pads of the first signal access area is connected to the group of intermediate contact pads of the second signal access area through a plurality of pin connection lines.
  • the plurality of multiplexing control contact pads of the second signal access area include a first group of multiplexing control contact pads and a second group of multiplexing control contact pads, and the first group of multiplexing control contact pads and the second group of multiplexing control contact pads are located on opposite sides of the group of intermediate contact pads along the first direction.
  • the first group of multiplexing control lines is connected to the first group of multiplexing control contact pads
  • the second group of multiplexing control lines is connected to the second group of multiplexing control contact pads.
  • a first end of each of the N multiplexing control lines is connected to the first group of multiplexing control contact pads, and a second end of each of the multiplexing control lines is connected to the second group of multiplexing control contact pads.
  • the plurality of multiplexed data lines do not overlap with the N multiplexed control lines in their orthographic projection on the substrate
  • the N multiplexed control lines include a first group of multiplexed control lines and a second group of multiplexed control lines, the first group of multiplexed control lines includes n multiplexed control lines, and the second group of multiplexed control lines includes n+1 multiplexed control lines; the first group of multiplexed control lines and the second group of multiplexed control lines are arranged on opposite sides of the plurality of multiplexed data lines.
  • an embodiment of the present disclosure provides a display device, including the display panel as described above.
  • the present embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing data lines, and N multiplexing control lines.
  • the substrate comprises a display area and a first frame area located on at least one side of the display area.
  • a plurality of sub-pixels and a plurality of data lines are located in the display area, and the plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels.
  • a plurality of multiplexing circuits, a plurality of multiplexing data lines, and N multiplexing control lines are located in the first frame area; wherein N is equal to 2n+1, and n is an integer greater than 0. At least one of the plurality of multiplexing circuits is electrically connected to the N multiplexing control lines, a multiplexing data line, and a plurality of data lines, and is configured to provide the data signals transmitted by the multiplexing data lines to the plurality of data lines under the control of the N multiplexing control lines.
  • At least part of each of the multiple multiplexed data lines extends along the first direction, and at least part of each of the N multiplexed control lines extends along the second direction; at least part of the multiplexed data lines and at least part of the multiplexed control lines intersect.
  • At least some segments of the multiplexing control line and at least some segments of the multiplexing data lines have the same crossing angle.
  • a crossing angle between at least a portion of the multiplexing control line segments and at least a portion of the multiplexing data line segments is less than or equal to 90 degrees.
  • the value of N is 9.
  • FIG1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG2 is a partial cross-sectional schematic diagram of a display area of a display panel according to at least one embodiment of the present disclosure
  • FIG3 is a partial plan view of a first frame region according to at least one embodiment of the present disclosure.
  • FIG4 is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure.
  • FIG5 is a diagram showing an example of the arrangement of multiplexed control lines and multiplexed data lines according to at least one embodiment of the present disclosure
  • FIG6 is a partial enlarged schematic diagram of area S1 in FIG3 ;
  • FIG7 is a partial enlarged schematic diagram of area S2 in FIG3 ;
  • FIG8A is a schematic diagram of the display panel after the first gate metal layer is formed in FIG7 ;
  • FIG8B is a schematic diagram of the display panel after the second gate metal layer is formed in FIG7 ;
  • FIG8C is a schematic diagram of the display panel after the first source-drain metal layer is formed in FIG7 ;
  • FIG9 is a partial enlarged schematic diagram of area S3 in FIG3 ;
  • FIG10 is a partial enlarged schematic diagram of area S4 in FIG3 ;
  • FIG. 11 is another exemplary diagram of the arrangement of multiplexed control lines and multiplexed data lines according to at least one embodiment of the present disclosure
  • FIG. 12 is another exemplary diagram of the arrangement of multiplexed control lines and multiplexed data lines according to at least one embodiment of the present disclosure
  • FIG13 is another exemplary diagram of the arrangement of multiplexed control lines and multiplexed data lines according to at least one embodiment of the present disclosure
  • FIG. 14 is another exemplary diagram of the arrangement of multiplexed control lines and multiplexed data lines according to at least one embodiment of the present disclosure
  • FIG. 15 is another exemplary diagram of the arrangement of multiplexed control lines and multiplexed data lines according to at least one embodiment of the present disclosure
  • FIG. 16 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • a channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” may be interchanged.
  • connection includes the case where the components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • a extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, line segment or strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.
  • a extends along direction B means "the main part of A extends along direction B".
  • a and B are of the same layer structure
  • a and B are formed simultaneously by the same patterning process.
  • the same layer does not always mean that the thickness of the layer or the height of the layer is the same in the cross-sectional view.
  • the orthographic projection of A includes the orthographic projection of B means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.
  • the multiplexing circuit is very important to the picture quality of wearable products such as watches, especially when performing low grayscale display. Due to the signal load difference caused by the overlapping of the wiring connected to the multiplexing circuit, poor display such as bright and dark stripes or split screen will occur.
  • This embodiment provides a display panel and a display device, which can improve the overlap of the wiring connected to the multiplexing circuit. Poor display caused by the difference in signal load.
  • the present embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing data lines, and N multiplexing control lines.
  • the substrate comprises a display area and a first frame area located on at least one side of the display area.
  • a plurality of sub-pixels and a plurality of data lines are located in the display area, and a plurality of data lines are connected to a plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels.
  • a plurality of multiplexing circuits, a plurality of multiplexing data lines, and N multiplexing control lines are located in the first frame area.
  • N is equal to 2n+1, and n is an integer greater than 0.
  • At least one of the plurality of multiplexing circuits is electrically connected to N multiplexing control lines, a multiplexing data line, and a plurality of data lines, and is configured to provide data signals transmitted by the multiplexing data lines to the plurality of data lines under the control of the N multiplexing control lines.
  • Each of the multiplexed data lines overlaps with at least n multiplexed control lines in their orthographic projections on the substrate, or the multiplexed data lines do not overlap with the orthographic projections of the N multiplexed control lines on the substrate.
  • the number of multiplexed control lines may be an odd number.
  • the value of n may be 4, and the value of N may be 9.
  • the display panel provided in this embodiment can avoid or greatly reduce the signal load difference caused by the overlapping of the routing of the multiplexed data lines and the multiplexed control lines connected to the multiplexing circuit, thereby improving the poor display condition of the display panel.
  • FIG1 is a schematic diagram of a display panel of at least one embodiment of the present disclosure.
  • the display panel may include: a display area AA, a first frame area B1 located on one side of the display area AA, and a second frame area B2 located on the remaining sides of the display area AA.
  • the first frame area B1 may be connected to the second frame area B2.
  • the first frame area B1 may be the lower frame of the display panel, and the second frame area B2 may include the remaining frame area of the display panel except the lower frame.
  • the display area AA may be a flat area including a plurality of sub-pixels PX constituting a pixel array, and the plurality of sub-pixels PX may be configured to display a dynamic picture or a still image.
  • the display area AA may be referred to as an active area (Active Area).
  • the display area AA may be circular or elliptical. However, this embodiment is not limited thereto.
  • the display area may be other shapes such as a rectangle.
  • the display panel may be a flexible panel, and thus the display panel may be deformable, such as curled, bent, folded, or rolled up.
  • the display area AA may include: a display structure layer disposed on a substrate, or may include a display structure layer and a touch structure layer disposed on a substrate in sequence.
  • the display panel may integrate a touch structure to form a structure in which the touch structure is on a thin film encapsulation (Touch on Thin Film Encapsulation, referred to as Touch on TFE).
  • the Touch on TFE structure mainly includes a Flexible Multi-Layer On Cell (FMLOC) structure and a Flexible Single-Layer On Cell (FSLOC) structure.
  • FMLOC Flexible Multi-Layer On Cell
  • FLOC Flexible Single-Layer On Cell
  • the FMLOC structure is based on the working principle of mutual capacitance detection, and generally uses two layers of metal to form a driving (Tx) electrode and a sensing (Rx) electrode.
  • the driving chip (IC) realizes the touch action by detecting the mutual capacitance between the driving electrode and the sensing electrode.
  • the FSLOC structure is based on the working principle of self-capacitance (or voltage) detection, and generally uses a single layer of metal to form a touch electrode.
  • the integrated circuit realizes the touch action by detecting the self-capacitance (or voltage) of the touch electrode.
  • the display structure layer may include a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL.
  • the plurality of gate lines GL may extend along a first direction X
  • the plurality of data lines DL may extend along a second direction Y.
  • the orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate may intersect to form a plurality of sub-pixel regions.
  • a sub-pixel PX may be disposed in a sub-pixel region.
  • the plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX.
  • the plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide gate drive signals to the plurality of sub-pixels PX.
  • the gate drive signal may include a scan signal, or may include a scan signal and a light emitting control signal, or may include a scan signal. signal, reset control signal and light-emitting control signal.
  • the first direction X may be an extension direction (e.g., a row direction) of the gate lines GL in the display area AA
  • the second direction Y may be an extension direction (e.g., a column direction) of the data lines DL in the display area AA.
  • the first direction X and the second direction Y may intersect each other, for example, may be perpendicular to each other.
  • a pixel unit of display area AA may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., green light), and a third sub-pixel emitting a third color light (e.g., blue light).
  • a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light.
  • a pixel unit may include four sub-pixels, and the four sub-pixels may include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.
  • the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the three sub-pixels may be arranged in parallel horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged in parallel horizontally, vertically, or in a square pattern.
  • this embodiment is not limited to this.
  • a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit.
  • the pixel circuit may include multiple transistors and at least one capacitor.
  • the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • T in the above circuit structure refers to a thin film transistor
  • C refers to a capacitor
  • the number before T represents the number of thin film transistors in the circuit
  • the number before C represents the number of capacitors in the circuit.
  • the multiple transistors in the pixel circuit may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product.
  • the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors.
  • multiple transistors in a pixel circuit may use low-temperature polysilicon thin-film transistors, or may use oxide thin-film transistors, or may use low-temperature polysilicon thin-film transistors and oxide thin-film transistors.
  • the active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • oxide thin-film transistor uses oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current.
  • Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display panel namely the LTPS+Oxide (LTPO for short) display panel, can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.
  • LTPS+Oxide LTPO for short
  • the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc.
  • the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as required.
  • the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.
  • the anode of the light-emitting element may be electrically connected to the corresponding pixel circuit.
  • this embodiment is not limited to this.
  • FIG2 is a partial cross-sectional schematic diagram of a display area of a display panel of at least one embodiment of the present disclosure.
  • FIG2 is a diagram showing a structure of a sub-pixel in the display area as an example.
  • the same type of multiple transistors in a pixel circuit is used as an example for illustration.
  • multiple transistors in a pixel circuit can all be low-temperature polysilicon thin-film transistors or oxide thin-film transistors.
  • the display area of the display panel may be
  • the display structure layer includes: a substrate 10, and a circuit structure layer 12, a light emitting structure layer 13, a packaging structure layer 14, and a touch structure layer 15 sequentially arranged on the substrate 10.
  • the display structure layer may include at least the circuit structure layer 12 and the light emitting structure layer 13.
  • the circuit structure layer 12 may include at least: a pixel circuit of a plurality of sub-pixels, and the pixel circuit of each sub-pixel may include a plurality of transistors and at least one capacitor.
  • the light emitting structure layer 13 may include at least: a light emitting element of a plurality of sub-pixels.
  • FIG. 2 illustrates a thin film transistor 21 and a capacitor 22 included in each sub-pixel as an example.
  • the circuit structure layer 12 of the display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, and a first source-drain metal layer disposed on the substrate 10.
  • a first gate insulating layer 101 may be disposed between the semiconductor layer and the first gate metal layer
  • a second gate insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer
  • an interlayer insulating layer 103 may be disposed between the second gate metal layer and the first source-drain metal layer
  • a passivation layer 104 and a first flat layer 105 may be disposed on the side of the first source-drain metal layer away from the substrate 10.
  • the first gate insulating layer 101, the second gate insulating layer 102, the interlayer insulating layer 103, and the passivation layer 104 may be an inorganic insulating layer
  • the first flat layer 105 may be an organic insulating layer.
  • a buffer layer may be provided on the side of the semiconductor layer close to the substrate, and the buffer layer may prevent harmful substances in the substrate from invading the interior of the display panel and may also increase the adhesion of the film layer in the display panel on the substrate.
  • the passivation layer may be omitted on the side of the first source and drain metal layer away from the substrate, and only the first planarization layer may be provided.
  • the semiconductor layer of the display area may include at least: an active layer 210 of a thin film transistor 21.
  • the active layer 210 of the thin film transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102.
  • the first gate metal layer may include at least: a gate electrode 213 of the thin film transistor 21, and a first electrode plate 221 of the capacitor 22.
  • the orthographic projection of the gate electrode 213 of the thin film transistor 21 on the substrate 10 may cover the orthographic projection of the channel region 2100 of the active layer 210 on the substrate 10.
  • the second gate metal layer may include at least: a second electrode plate 222 of the capacitor 22.
  • the orthographic projections of the second electrode plate 222 and the first electrode plate 221 of the capacitor 22 on the substrate 10 may at least partially overlap, for example, the two may overlap.
  • the first source-drain metal layer may include at least: a source electrode 211 and a drain electrode 212 of the thin film transistor 21.
  • the interlayer insulating layer 103 may be provided with a plurality of vias (for example, including a first pixel via and a second pixel via) in the display area.
  • the interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101 in the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the active layer 210; the interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101 in the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the active layer 210.
  • the source electrode 211 of the thin film transistor 21 may be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain electrode 212 may be electrically connected to the second region 2102 of the active layer 210 through the second pixel via.
  • the gate line of the display area may be located, for example, in the first gate metal layer, and the data line and the high potential power line of the display area may be located, for example, in the first source-drain metal layer.
  • the light emitting structure layer 13 may include: a pixel definition layer 134 and a plurality of light emitting elements.
  • each light emitting element may include: a stacked first electrode 131, an organic light emitting layer 132, and a second electrode 133.
  • the first electrode 131 of the light emitting element may be an anode, and the first electrode 131 may be disposed on the first flat layer 105, and electrically connected to the second electrode 212 of the thin film transistor through a pixel via provided in the first flat layer 105 and the passivation layer 104.
  • the pixel definition layer 134 is disposed on the first electrode 131 and the first flat layer 105, and the pixel definition layer 134 may be provided with a plurality of pixel openings, and one pixel opening may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light emitting layer 132 may be disposed in a pixel opening and connected to the corresponding first electrode 131.
  • the second electrode 133 may be disposed on the organic light emitting layer 132 and connected to the organic light emitting layer 132. The organic light emitting layer 132 may emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.
  • the organic light-emitting layer 132 of the light-emitting element may include a light-emitting layer (EML, Emitting Layer), and a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole blocking layer (HBL, Hole Block Layer), an electron blocking layer (EBL, Electron Block Layer), an electron injection layer (EIL, Electron Injection Layer), and an electron transport layer (ETL, Electron Transport Layer)
  • EML Electron Transport Layer
  • the light emitting characteristics of the organic material can be used to emit light according to the required grayscale.
  • the light-emitting layers of the light-emitting elements emitting different colors of light may be different.
  • the red light-emitting element includes a red light-emitting layer
  • the green light-emitting element includes a green light-emitting layer
  • the blue light-emitting element includes a blue light-emitting layer.
  • the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer
  • the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer.
  • any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment.
  • any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels can be isolated.
  • the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.
  • FMM fine metal mask
  • Open Mask open mask
  • the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked.
  • the first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials
  • the second encapsulation layer 142 may be made of organic materials
  • the second encapsulation layer 142 may be arranged between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external water vapor cannot enter the light-emitting element.
  • this embodiment is not limited to this.
  • the encapsulation structure layer may adopt a five-layer stacked structure of inorganic/organic/inorganic/organic/inorganic.
  • the touch structure layer 15 may include multiple touch units. At least one touch unit may include at least one touch electrode.
  • the orthographic projection of at least one touch electrode on the substrate may include the orthographic projections of multiple sub-pixels on the substrate.
  • the touch unit includes multiple touch electrodes, the multiple touch electrodes may be arranged at intervals, and adjacent touch electrodes may be connected to each other through a connecting portion.
  • the touch electrodes and the connecting portion may be in the same layer structure.
  • the touch electrode may have a rhombus shape, for example, a regular rhombus, a horizontally long rhombus, or a vertically long rhombus. However, this embodiment is not limited to this.
  • the touch electrode may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons.
  • the first frame area B1 may include: a first fan-out area B11, a bending area B12, a second fan-out area B13, a first signal access area B14, and a second signal access area B15, which are sequentially arranged in a direction away from the display area AA.
  • the first fan-out area B11 may be connected to the second frame area B2 and located on one side of the display area AA.
  • the bending area B12 may be connected to the first fan-out area B11 and the second fan-out area B13 and located on the side of the first fan-out area B11 away from the display area AA.
  • the second fan-out area B13 may be located on the side of the bending area B12 away from the display area AA.
  • the first signal access area B14 may be located on the side of the second fan-out area B13 away from the display area AA.
  • the second signal access area B15 may be located on the side of the first signal access area B14 away from the display area AA.
  • FIG3 is a partial plan view of the first frame area of at least one embodiment of the present disclosure.
  • FIG3 shows an overall diagram of the panel detection line, multiplexed data lead-out line, data bending connection line, touch bending connection line, detection bending connection line, control bending connection line, multiplexed data line and panel detection lead-out line in the first frame area, and the data fan-out line, control lead-out line, control connection line and control signal line are only shown as a few lines, and this example does not limit the number of multiple lines in the first frame area.
  • the first fan-out area B11 can be connected to the display area AA and the second frame area.
  • the first fan-out area B11 can be provided with a first power line 311, a second power line 321a and 321b, a plurality of display lead lines, a plurality of panel detection lines, a plurality of multiplexing circuits 40, a plurality of electrostatic discharge (ESD) circuits 41, and a plurality of shift register units 42 of a gate driving circuit.
  • the first power line 311 may have a first main
  • the first main body of the first power line 311 may be substantially located at the midline of the first fan-out area B11 in the first direction X, and the midline of the first fan-out area B11 in the first direction X may be parallel to the second direction Y.
  • the first main body of the first power line 311 may extend toward one side of the bending area B12.
  • the first extension of the first power line 311 may be electrically connected to a plurality of high potential power lines electrically connected to the pixel circuits of a plurality of sub-pixels of the display area AA.
  • the second power lines 321a and 321b may be located on opposite sides of the first power line 311 in the first direction X.
  • the second power line 321a may extend from the left side along the edge of the display panel to the second frame area, and the second power line 321b may extend from the right side along the edge of the display panel to the second frame area.
  • the second power lines 321a and 321b may be connected in the second frame area to provide a low potential power signal to a plurality of sub-pixels of the display area AA.
  • the first power line 311, the second power lines 321a and 321b may be in the same layer structure, for example, may be located in the first source and drain metal layer.
  • the gate drive circuit may include a plurality of cascaded shift register units 42, each shift register unit 42 may be connected to at least one gate line of the display area AA, and configured to provide a gate drive signal to at least one gate line of the display area AA.
  • the multiplexing circuit 40 may be configured so that a signal source provides a data signal to a plurality of data lines. A portion of the multiplexing circuit 40 may be arranged on opposite sides of the first main body of the first power line 311 in the first direction X and arranged in an array along the first direction X, and another portion of the multiplexing circuit 40 may be arranged at intervals with the shift register unit 42 of the gate drive circuit.
  • the shift register unit 42 of the gate drive circuit may be arranged along the edge of the display area AA from the first fan-out area B11.
  • the electrostatic discharge circuit 41 may be configured to eliminate static electricity on the connected signal line.
  • a plurality of electrostatic discharge circuits 41 may be arranged on opposite sides of the first main body of the first power line 311 in the first direction X, and located on one side of the first main body of the multiplexing circuit 40 close to the first power line 311.
  • the plurality of display lead lines of the first fan-out area B11 may include at least: a plurality of data fan-out lines 63, a plurality of control lead lines (e.g., including a first group of control lead lines 64a and a second group of control lead lines 64b), and a plurality of multiplexed data lead lines (e.g., including a first group of multiplexed data lead lines 62a and a second group of multiplexed data lead lines 62b).
  • the plurality of data fan-out lines 63 may be electrically connected to a plurality of multiplexing circuits 40 and a plurality of data lines of the display area AA.
  • One end of a data fan-out line 63 may be electrically connected to at least one data line of the display area AA, and the other end may be electrically connected to a multiplexing circuit 40.
  • the plurality of data fan-out lines 63 and the plurality of data lines may be electrically connected in a one-to-one correspondence.
  • a multiplexing circuit 40 may be connected to the plurality of data lines via the plurality of data fan-out lines 63 so as to provide data signals to the plurality of data lines.
  • one multiplexing circuit 40 may provide data signals to nine data lines through multiple data fan-out lines 63.
  • adjacent data fan-out lines 63 may be located at different metal layers, for example, multiple data fan-out lines 63 may be alternately arranged at a first gate metal layer and a second gate metal layer.
  • a plurality of multiplexed data lead-out lines can be electrically connected to a plurality of multiplexed circuits 40.
  • a multiplexed data lead-out line can be configured to transmit data signals to a multiplexed circuit 40, so that the multiplexed circuit 40 provides data signals to the plurality of data lines connected thereto.
  • a plurality of multiplexed data lead-out lines can for example include a first group of multiplexed data lead-out lines 62a and a second group of multiplexed data lead-out lines 62b.
  • Each group of multiplexed data lead-out lines can include a plurality of multiplexed data lead-out lines, and the number of two groups of multiplexed data lead-out lines can be the same or different.
  • the first group of multiplexed data lead-out lines 62a and the second group of multiplexed data lead-out lines 62b can be located at the opposite sides of the first main body of the first power line 311.
  • the first group of multiplexed data lead lines 62a can extend to the left and be connected to the multiple multiplexed circuits 40 located on the left side of the first main body of the first power line 311; the second group of multiplexed data lead lines 62b can extend to the right and be connected to the multiple multiplexed circuits 40 located on the right side of the first main body of the first power line 311.
  • the multiple multiplexed data lead lines can be located on the side of the second power lines 331a and 331b close to the substrate.
  • the multiple multiplexed data lead lines can be of the same layer structure, for example, they can all be located in the second gate metal layer.
  • the plurality of control leads may include, for example, a first group of control leads 64 a and a second group of control leads 64 b.
  • Each group of control leads may include a plurality of control leads. The number may be the same or different.
  • the first group of control lead wires 64a and the second group of control lead wires 64b may be located at opposite sides of the first main body of the first power line 311.
  • the first group of control lead wires 64a may be located at a side of the first group of multiplexed data lead wires 62a close to the first power line 311, and the second group of control lead wires 64b may be located at a side of the second group of multiplexed data lead wires 62b close to the first power line 311.
  • Multiple control lead wires may be connected to the electrostatic discharge circuit 41 to avoid static electricity accumulation.
  • the plurality of control leads may include: a plurality of multiplexed control leads (e.g., including the first group of multiplexed control leads 53a and the second group of multiplexed control leads 53b shown in FIG6 ), and a plurality of drive control leads (e.g., including the first group of drive control leads 83a and the second group of drive control leads 83b shown in FIG6 ).
  • the plurality of multiplexed control leads may be connected to a plurality of multiplexed circuits 40, and may be configured to provide multiplexed control signals to the plurality of multiplexed circuits 40.
  • the plurality of drive control leads may be connected to a gate drive circuit 42, and may, for example, provide a drive control signal (e.g., including a start signal, a clock signal, a power supply signal, etc.) to the gate drive circuit 42.
  • the plurality of panel inspection lines may be configured to perform crack detection in the display area AA.
  • the plurality of panel inspection lines may include a first group of panel inspection lines 331a and a second group of panel inspection lines 331b.
  • the first group of panel inspection lines 331a may overlap with the second power supply line 321a in the orthographic projection portion of the substrate, and the second group of panel inspection lines 331b may overlap with the second power supply line 321b in the orthographic projection portion of the substrate.
  • the plurality of panel inspection lines may be in the same layer structure, such as being located in the first gate metal layer.
  • the bending area B12 can be configured to bend the second fan-out area B13, the first signal access area B14, and the second signal access area B15 to the back of the display area AA.
  • the bending area B12 can be provided with a plurality of bending connection lines to connect the routing lines transmitting the same signal in the first fan-out area B11 and the second fan-out area B13.
  • the plurality of bending connection lines in the bending area B12 can be of the same layer structure, for example, they can all be located in the first source and drain metal layer.
  • the multiple bending connection lines may include: a first power bending connection line 31, a second power bending connection line 32a and 32b, a first group of detection bending connection lines 33a and a second group of detection bending connection lines 33b, a first group of touch bending connection lines 34a and a second group of touch bending connection lines 34b, a first group of data bending connection lines 36a and a second group of data bending connection lines 36b, a first group of control bending connection lines 35a and a second group of control bending connection lines 35b.
  • the second power bending connection line 32a, the first group of detection bending connection lines 33a, the first group of touch bending connection lines 34a, the first group of data bending connection lines 36a, the first group of control bending connection lines 35a, the first power bending connection lines 31, the second group of control bending connection lines 35b, the second group of data bending connection lines 36b, the second group of touch bending connection lines 34b, the second group of detection bending connection lines 33b and the second power bending connection lines 32b can be arranged in sequence along the first direction X.
  • the second fan-out area B13 may be provided with at least a first power lead 312, second power lead lines 322a and 322b, a plurality of panel detection lead lines (including a first group of panel detection lead lines 332a and a second group of panel detection lead lines 332b as shown in FIG. 3), a plurality of multiplexed data lines (including a first group of multiplexed data lines 61a and a second group of multiplexed data lines 61b as shown in FIG. 3), a plurality of control connection lines (including a first group of control connection lines 65a and a second group of control connection lines 65b as shown in FIG. 3), and a plurality of control signal lines (including a first group of control signal lines 66a and a second group of control signal lines 66b as shown in FIG. 3).
  • the first power lead 312 can be connected to the first power line 311 of the first fan-out area B11 through the first power connection line 31 of the bending area B12.
  • the first power lead 312, the first power connection line 31 and the first power line 311 can be an integral structure connected to each other, for example, all located in the first source and drain metal layer.
  • the first power lead 312 may include a second main body extending along the second direction Y, and a second extension and a third extension connected to the second main body.
  • the second extension and the third extension may extend along opposite sides of the first direction X to bypass the first signal access area B14 and extend to the second signal access area B15.
  • the second extension of the first power lead 312 can bypass the first signal access area B14 from the left, and the second extension of the first power lead 312 can bypass the first signal access area B14 from the right.
  • the second power lead 322a can be connected to the second power line 321a through the second power connection line 32a of the bending area B12.
  • the second power lead 322b can be located on the side of the second extension of the first power lead 312 close to the edge of the display panel.
  • the second power lead 322a, the second power connection line 32a and the second power line 321a can be an integrated structure connected to each other, for example, both are located in the first source and drain metal layer.
  • the second power lead 322b can be connected to the second power line 321b through the second power connection line 32b of the bending area B12.
  • the second power lead 322b can be located on the side of the third extension of the first power lead 312 close to the edge of the display panel.
  • the second power lead 322b, the second power connection line 32b and the second power line 321b can be an integrated structure connected to each other, for example, both are located in the first source and drain metal layer.
  • the plurality of panel detection lead-out lines of the second fan-out area B13 may include a first group of panel detection lead-out lines 332a and a second group of panel detection lead-out lines 332b.
  • the plurality of panel detection lead-out lines of the first group of panel detection lead-out lines 332a may be connected to the plurality of panel detection lines of the first group of panel detection lines 331a in the first fan-out area B11 through the plurality of detection bend connection lines of the first group of detection bend connection lines 33a of the bending area B12.
  • the plurality of panel detection lead-out lines in the second group of panel detection lead-out lines 332b may be connected to the plurality of panel detection lines of the first group of panel detection lines 331b in the first fan-out area B11 through the plurality of detection bend connection lines of the second group of detection bend connection lines 33b of the bending area B12.
  • the first group of panel detection lead-out lines 332a may be located on the side of the second power lead-out line 322a away from the edge of the display panel.
  • the second group of panel detection lead-out lines 332b may be located on the side of the second power lead-out line 322b away from the edge of the display panel.
  • the plurality of panel detection lead lines may be in a same-layer structure, for example, may all be located in the second gate metal layer.
  • the plurality of multiplexed data lines of the second fan-out area B13 may extend substantially along the second direction Y toward the first signal access area B14.
  • the plurality of multiplexed data lines may include a first group of multiplexed data lines 61a and a second group of multiplexed data lines 61b.
  • the plurality of multiplexed data lines of the first group of multiplexed data lines 61a may be connected to the plurality of multiplexed data lead-out lines of the first group of multiplexed data lead-out lines 62a in the first fan-out area B11 through the plurality of data bend connection lines of the first group of data bend connection lines 36a in the bend area B12.
  • the plurality of multiplexed data lines of the second group of multiplexed data lines 61b may be connected to the plurality of multiplexed data lead-out lines of the second group of multiplexed data lead-out lines 62b in the first fan-out area B11 through the plurality of data bend connection lines of the second group of data bend connection lines 36b in the bend area B12.
  • the first group of multiplexed data lines 61a can be configured to provide data signals to sub-pixels in the left half area of display area AA
  • the second group of multiplexed data lines 61b can be configured to provide data signals to sub-pixels in the right half area of display area AA.
  • the plurality of control connection lines of the second fan-out area B13 may extend along the second direction Y toward the first signal access area and the side of B14.
  • the plurality of control connection lines may include a first group of control connection lines 65a (for example, including the first group of multiplexing control connection lines 52a and the first group of driving control connection lines 82a shown in FIG9 ) and a second group of control connection lines 65b (for example, including the second group of multiplexing control connection lines 52b and the second group of driving control connection lines 82b shown in FIG10 ).
  • the plurality of control connection lines of the first group of control connection lines 65a may be connected to the plurality of control lead-out lines of the first group of control lead-out lines 64a in the first fan-out area B11 through the plurality of control bend connection lines of the first group of control bend connection lines 35a of the bend area B12.
  • the plurality of control connection lines of the second group of control connection lines 65b may be connected to the plurality of control lead-out lines of the second group of control lead-out lines 64b in the first fan-out area B11 through the plurality of control bend connection lines of the second group of control bend connection lines 35b of the bend area B12.
  • the first group of control connection lines 65a can be located on one side of the second main body of the first group of multiplexed data lines 61a close to the first power lead line 312, and the second group of control connection lines 65b can be located on one side of the second group of multiplexed data lines 61b close to the second main body of the first power lead line 312.
  • the plurality of control signal lines of the second fan-out region B13 may include a first group of control signal lines 66a and a second group of control signal lines 66b.
  • the first group of control signal lines 66a may be connected to the first group of control connection lines 65a
  • the second group of control signal lines 66b may be connected to the second group of control connection lines 65b.
  • the first group of control signal lines 66a may bypass the first signal access region B14 from one side (e.g., the left side) along the first direction X and extend toward the second signal access region B15.
  • the second group of control signal lines 66b may extend from the other side (e.g., the right side) along the first direction X. It bypasses the first signal access area B14 and extends toward the second signal access area B15.
  • the plurality of control signal lines of the second fan-out area B13 may include a plurality of multiplexed control lines (e.g., including the first group of multiplexed control lines 51a shown in FIG. 9 and the second group of multiplexed control lines 51b shown in FIG. 10), and a plurality of drive control lines (e.g., including the first group of drive control lines 81a shown in FIG. 9 and the second group of drive control lines 81b shown in FIG. 10).
  • a plurality of multiplexed control lines e.g., including the first group of multiplexed control lines 51a shown in FIG. 9 and the second group of multiplexed control lines 51b shown in FIG. 10
  • drive control lines e.g., including the first group of drive control lines 81a shown in FIG. 9 and the second group of drive control lines 81b shown in FIG. 10
  • the plurality of multiplexed control lines may be connected to the plurality of multiplexed control lead-out lines of the first fan-out area B11 (e.g., including the first group of multiplexed control lead-out lines 53a and the second group of multiplexed control lead-out lines 53b shown in FIG. 6), and are configured to provide multiplexed control signals to the multiplexing circuit.
  • the plurality of drive control lines may be connected to the plurality of drive control lead-out lines of the first fan-out area B11 (e.g., including the first group of drive control lead-out lines 83a and the second group of drive control lead-out lines 83b shown in FIG. 6), and are configured to provide drive control signals (e.g., including start signals, clock signals, voltage signals, etc.) to the gate drive circuit.
  • the first signal access area B14 may be configured to set a driver chip (IC, Integrated Circuit).
  • the driver chip set in the first signal access area B14 may be a display driver chip or a touch and display driver integrated chip (TDDI, Touch and Display Driver Integration).
  • TDDI Touch and Display Driver Integration
  • the first signal access area B14 may also be referred to as a driver chip setting area.
  • the driver chip may be configured to generate a data signal required for driving a sub-pixel and provide the data signal to a data line of the display area.
  • the first signal access area B14 may be provided with a plurality of first contact pads.
  • the plurality of first contact pads may include a first group of first contact pads 71a and a second group of first contact pads 71b.
  • the second group of first contact pads 71b may be located on the side of the first group of first contact pads 71a away from the display area AA.
  • the plurality of first contact pads in the first group of first contact pads 71a may be arranged in at least one row along the first direction X array.
  • the plurality of multiplexed data lines (for example, including the first group of multiplexed data lines 61a and the second group of multiplexed data lines 61b) in the second fan-out area B13 may be electrically connected to the plurality of first contact pads in the first group of first contact pads 71a in the first signal access area B14 to be configured to receive data signals from the driver chip.
  • the plurality of first contact pads in the second group of first contact pads 71b may be arranged in a row along the first direction X.
  • the second signal access area B15 may be provided with a plurality of second contact pads 72, and the plurality of second contact pads 72 may be configured to bind a flexible printed circuit (FPC) so that a plurality of signal lines (e.g., control signal lines, power lines, etc.) are connected to an external control device through the plurality of second contact pads 72.
  • the second signal access area B15 may also be referred to as a circuit binding area.
  • the second group of first contact pads 71b in the first signal access area B14 may be electrically connected to the plurality of second contact pads 72 in the second signal access area B15 through a plurality of pin connection lines 73.
  • the plurality of second contact pads 72 may include a plurality of multiplexing control contact pads (e.g., the multiplexing control contact pad 721 shown in FIG. 5 ).
  • the plurality of multiplexing control lines may extend to be electrically connected to the plurality of multiplexing control contact pads in the second signal access area B15, and the plurality of multiplexing control lines may be configured to receive multiplexing control signals through the multiplexing control contact pads of the second signal access area B15.
  • FIG4 is an equivalent circuit diagram of a multiplexing circuit of at least one embodiment of the present disclosure.
  • FIG4 is a multiplexing circuit 40 as an example for illustration.
  • a multiplexing circuit 40 may be electrically connected to nine multiplexing control lines, one multiplexing data line 61, and multiple data lines (e.g., first data line DL1 to ninth data line DL9).
  • the multiplexing circuit 40 may include nine multiplexing transistors (i.e., first multiplexing transistor M1 to ninth multiplexing transistor M9).
  • the gates of the nine multiplexing transistors can be connected to different multiplexing control lines respectively, that is, the gate of the first multiplexing transistor M1 is connected to the first multiplexing control line 511, the gate of the second multiplexing transistor M2 is connected to the second multiplexing control line 512, the gate of the third multiplexing transistor M3 is connected to the third multiplexing control line 513, the gate of the fourth multiplexing transistor M4 is connected to the fourth multiplexing control line 514, the gate of the fifth multiplexing transistor M5 is connected to the fifth multiplexing control line 515, the gate of the sixth multiplexing transistor M6 is connected to the sixth multiplexing control line 516, the gate of the seventh multiplexing transistor M7 is connected to the seventh multiplexing control line 517, the gate of the eighth multiplexing transistor M8 is connected to the eighth multiplexing control line 518, and the gate of the ninth multiplexing transistor M9 is connected to the eighth multiplexing control line 519.
  • the gate of is connected to the ninth multiplex
  • the first electrodes of the nine multiplexing transistors can all be connected to the same multiplexing data line 61.
  • the second electrodes of the nine multiplexing transistors are respectively connected to different data lines of the display area.
  • the second electrode of the first multiplexing transistor M1 is connected to the first data line DL1
  • the second electrode of the second multiplexing transistor M2 is connected to the second data line DL2
  • the second electrode of the third multiplexing transistor M3 is connected to the third data line DL3
  • the second electrode of the fourth multiplexing transistor M4 is connected to the fourth data line DL4
  • the second electrode of the fifth multiplexing transistor M5 is connected to the fifth data line DL5
  • the second electrode of the sixth multiplexing transistor M6 is connected to the sixth data line DL6
  • the second electrode of the seventh multiplexing transistor M7 is connected to the seventh data line DL7
  • the second electrode of the eighth multiplexing transistor M8 is connected to the eighth data line DL8
  • the plurality of sub-pixels of the display area may include a first group of sub-pixels, a second group of sub-pixels, and a third group of sub-pixels.
  • the first group of sub-pixels may include a first group of first sub-pixels, a first group of second sub-pixels, and a first group of third sub-pixels
  • the second group of sub-pixels may include a second group of first sub-pixels, a second group of second sub-pixels, and a second group of third sub-pixels
  • the third group of sub-pixels may include a third group of first sub-pixels, a third group of second sub-pixels, and a third group of third sub-pixels.
  • the first data line DL1 may be connected to the first group of first sub-pixels R1 emitting the first color light, and configured to provide a data signal to the first group of first sub-pixels R1.
  • the second data line DL2 may be connected to the first group of second sub-pixels G1 emitting the second color light, and configured to provide a data signal to the first group of second sub-pixels G1.
  • the third data line DL3 may be connected to the first group of third sub-pixels B1, and configured to provide a data signal to the first group of third sub-pixels B1.
  • the fourth data line DL4 may be connected to the second group of first sub-pixels R2, and configured to provide a data signal to the second group of first sub-pixels R2.
  • the fifth data line DL5 may be connected to the second group of second sub-pixels G2, and configured to provide a data signal to the second group of second sub-pixels G2.
  • the sixth data line DL6 may be connected to the second group of third sub-pixels B2, and configured to provide a data signal to the second group of third sub-pixels B2.
  • the seventh data line DL7 may be connected to the third group of first sub-pixels R3, and configured to provide a data signal to the third group of first sub-pixels R3.
  • the eighth data line DL8 may be connected to the third group of second sub-pixels G3, and configured to provide a data signal to the third group of second sub-pixels G3.
  • the ninth data line GL9 may be connected to the third group of third sub-pixels B3, and configured to provide a data signal to the third group of third sub-pixels B3.
  • a group of sub-pixels may include at least one column of sub-pixels in the display area, and a column of sub-pixels may include, for example, a plurality of sub-pixels arranged along the second direction Y.
  • the first color light may be red light
  • the second color light may be green light
  • the third color light may be blue light.
  • nine multiplexing control lines can control multiple multiplexing circuits 40 to provide data signals to sub-pixels of the display area.
  • the first multiplexing control line 511 can be configured to provide a first multiplexing control signal to control the multiplexing circuit 40 to provide a data signal to the first group of first sub-pixels R1.
  • the second multiplexing control line 512 can be configured to provide a second multiplexing control signal to control the multiplexing circuit 40 to provide a data signal to the first group of second sub-pixels G1.
  • the third multiplexing control line 513 can be configured to provide a third multiplexing control signal to control the multiplexing circuit 40 to provide a data signal to the first group of third sub-pixels B1.
  • the fourth multiplexing control line 514 can be configured to provide a fourth multiplexing control signal to control the multiplexing circuit 40 to provide a data signal to the second group of first sub-pixels R2.
  • the fifth multiplexing control line 515 can be configured to provide a fifth multiplexing control signal to control the multiplexing circuit 40 to provide a data signal to the second group of second sub-pixels G2.
  • the sixth multiplexing control line 516 can be configured to provide a sixth multiplexing control signal to control the multiplexing circuit 40 to provide a data signal to the second group of third sub-pixels B2.
  • the seventh multiplexing control line 517 can be configured to provide a seventh multiplexing control signal to control the multiplexing circuit 40 to provide a data signal to the third group of first sub-pixels R3.
  • the eighth multiplexing control line 518 can be configured to provide an eighth multiplexing control signal to control the multiplexing circuit 40 to provide a data signal to the third group of second sub-pixels G3.
  • the ninth multiplexing control line 519 can be configured to provide a ninth multiplexing control signal to control the multiplexing circuit 40 to provide a data signal to the third group of third sub-pixels B3.
  • a plurality of multiplexing circuits 40 may be disposed in the first fan-out region B11, and a plurality of multiplexing control lines (for example, included in the first group of control signal lines 66 a and the second group of control signal lines 66 b) may be disposed in the first fan-out region B11.
  • a plurality of multiplexed control lines can be electrically connected to a plurality of multiplexing circuits 40 through a plurality of control bending connection lines (e.g., including a first group of control bending connection lines 35a and a second group of control bending connection lines 35b) in the bending region B12 and a plurality of multiplexed control lead lines (e.g., included in a first group of control lead lines 64a and a second group of control lead lines 64b) in the first fan-out region B11.
  • a plurality of control bending connection lines e.g., including a first group of control bending connection lines 35a and a second group of control bending connection lines 35b
  • a plurality of multiplexed control lead lines e.g., included in a first group of control lead lines 64a and a second group of control lead lines 64b
  • a plurality of multiplexed data lines (e.g., including a first group of multiplexed data lines 61a and a second group of multiplexed data lines 61b) are located in the second fan-out region B13, and a plurality of multiplexed data lines can be connected through a plurality of data bending connection lines (e.g., including a first group of data bending connection lines 36a and a second group of data bending connection lines 36b) in the bending region B12 and a plurality of multiplexed data lead lines (e.g., including a first group of multiplexed data lead lines 62a and a second group of multiplexed data lead lines 62b) in the first fan-out region B11.
  • a plurality of data bending connection lines e.g., including a first group of data bending connection lines 36a and a second group of data bending connection lines 36b
  • a plurality of multiplexed data lead lines e.g., including a first
  • the multiplexing circuit 40 can be connected to the multiple data lines of the display area AA through the multiple data fan-out lines 63.
  • the multiplexed control lines are connected to the multiplexed control contact pad (e.g., the multiplexed control contact pad 721 shown in FIG. 5) of the second signal access area B15, they extend and gather toward the middle area of the first frame area of the display panel by bypassing the first signal access area B14, and then extend toward the direction close to the display area AA.
  • Multiple multiplexed data lines (e.g., including a first group of multiplexed data lines 61a and a second group of multiplexed data lines 61b) are concentrated on one side of the first signal access area B14 close to the display area AA, and the multiple multiplexed data lines extend toward the side of the display area AA approximately along the second direction Y.
  • the second fan-out area B13 shown in FIG. 3 multiple multiplexed data lines and multiple multiplexed control lines will overlap, thereby forming overlapping capacitance.
  • the multiplexing circuit 40 when the multiplexing circuit 40 adopts a 1:9 design as shown in Figure 4 (i.e., the multiplexing circuit 40 provides a data signal of a multiplexed data line 61 to at least nine data lines under the control of nine multiplexed control lines), the nine multiplexed control lines cannot be evenly divided into two groups to be wound on both sides of the first signal access area B14, and there will be a difference between the number of multiplexed control lines overlapped by each multiplexed data line in the first group of multiplexed data lines 61a and the number of multiplexed control lines overlapped by each multiplexed data line in the second group of multiplexed data lines 61b.
  • FIG5 is an example diagram of the arrangement of multiplexed control lines and multiplexed data lines of at least one embodiment of the present disclosure.
  • FIG5 only takes a number of multiplexed data lines as an example for illustration.
  • FIG5 is a schematic diagram showing the approximate direction of multiplexed control lines and multiplexed data lines in the second fan-out area of the display panel.
  • the present embodiment does not limit the number of multiplexed data lines.
  • the present example is illustrated by taking the 1:9 design shown in FIG4 as an example of a multiplexing circuit.
  • the present example can improve the local display difference of the display area (for example, there is a difference in the display on the left and right sides of the display area) caused by the inconsistent overlapping capacitance of multiple multiplexed data lines and multiple multiplexed control lines by setting the arrangement of nine multiplexed control lines, thereby improving the display effect.
  • the plurality of second contact pads within the second signal access region B15 may include: a plurality of multiplexing control contact pads 721 and a group of intermediate contact pads 722.
  • the plurality of second contact pads may be arranged in a row along the first direction X.
  • a group of intermediate contact pads 722 may include a plurality of contact pads, and the group of intermediate contact pads 722 may be connected to a second group of first contact pads 71b within the first signal access region B14 through a plurality of pin connection lines 73.
  • the plurality of multiplexing control contact pads 721 may include a first group of multiplexing control contact pads 721a and a second group of multiplexing control contact pads 721b.
  • the first group of multiplexing control contact pads 721a and the second group of multiplexing control contact pads 721b may be located on opposite sides of a group of intermediate contact pads 722 along the first direction X.
  • the nine multiplexing control lines may include a first group of multiplexing control lines 51a and a second group of multiplexing control lines 51b.
  • the first group of control signal lines 66a in FIG3 may include the first group of multiplexing control lines 51a
  • the second group of control signal lines 66b may include the second group of multiplexing control lines 51b.
  • the first group of multiplexing control lines 51a may include the following four multiplexing control lines: a fourth multiplexing control line 514, a seventh multiplexing control line 517, an eighth multiplexing control line 518, and a ninth multiplexing control line 519.
  • the second group of multiplexing control lines 51b may include the following five multiplexing control lines: a first multiplexing control line 511, a second multiplexing control line 512, a third multiplexing control line 513, a sixth multiplexing control line 516, and a fifth multiplexing control line 515.
  • the first group of multiplexing control lines 51a may bypass one side (eg, the left side) of the first signal access area B14 along the first direction X
  • the second group of multiplexing control lines 51b may bypass the other side (eg, the right side) of the second signal access area B14 along the first direction X.
  • the first group of multiplexing control lines 51 a may be connected via the first group of multiplexing control lines
  • the first group of multiplexed control connection lines 52a may include a ninth multiplexed control connection line 529, an eighth multiplexed control connection line 528, a seventh multiplexed control connection line 527, and a fourth multiplexed control connection line 524
  • the second group of multiplexed control connection lines 52b may include a first multiplexed control connection line 521, a second multiplexed control connection line 522, a third multiplexed control connection line 523, a fifth multiplexed control connection line 525, and a sixth multiplexed control connection line 526.
  • the first multiplexing control connection line 521 is connected to the first multiplexing control line 511
  • the second multiplexing control connection line 522 is connected to the second multiplexing control line 512
  • the third multiplexing control connection line 523 is connected to the third multiplexing control line 513
  • the fourth multiplexing control connection line 524 is connected to the fourth multiplexing control line 514
  • the fifth multiplexing control connection line 525 is connected to the fifth multiplexing control line 515
  • the sixth multiplexing control connection line 526 is connected to the sixth multiplexing control line 516
  • the seventh multiplexing control connection line 527 is connected to the seventh multiplexing control line 517
  • the eighth multiplexing control connection line 528 is connected to the eighth multiplexing control line 518
  • the ninth multiplexing control connection line 529 is connected to the ninth multiplexing control line 519.
  • the first group of multiplexing control lines 51a may be connected to the first group of multiplexing control contact pads 721a.
  • each multiplexing control line in the first group of multiplexing control lines 51a may be connected to at least one multiplexing control contact pad 721 in the first group of multiplexing control contact pads 721a.
  • Each multiplexing control line of the first group of multiplexing control lines 51a may include at least a first multiplexing extension segment and a second multiplexing extension segment connected to each other.
  • the ninth multiplexing control line 519 may include: a first multiplexing extension segment 5191 and a second multiplexing extension segment 5192 connected to each other, the first multiplexing extension segment 5191 extending at least along the second direction Y, and the second multiplexing extension segment 5192 extending at least along the first direction X.
  • One end of the first multiplexing extension 5191 is connected to some multiplexing control contact pads 721 in the first group of multiplexing control contact pads 721a, and the other end is connected to one end of the second multiplexing extension 5192, and the other end of the second multiplexing extension 5192 is connected to the ninth multiplexing control connection line 529 in the first group of multiplexing control connection lines 52a in the first group of control connection lines (for example, the first group of control connection lines 65a shown in FIG. 3).
  • the first multiplexing extension of each multiplexing control line in the first group of multiplexing control lines 51a can be located on the side of the first group of multiplexing data lines 61a away from the second group of multiplexing data lines 61b, and the second multiplexing extension of each multiplexing control line can cross the first group of multiplexing data lines 61a.
  • the orthographic projection of each multiplexing data line 61 in the first group of multiplexing data lines 61a and the second multiplexing extension of each multiplexing control line of the first group of multiplexing control lines 51a on the substrate may overlap.
  • Each multiplexed data line 61 in the first group of multiplexed data lines 61a may cross the second multiplexed extension of each multiplexed control line of the first group of multiplexed control lines 51a.
  • the intersection angles of each multiplexed data line 61 in the first group of multiplexed data lines 61a and the second multiplexed extension of each multiplexed control line of the first group of multiplexed control lines 51a may be substantially the same, for example, they may all be 90 degrees.
  • intersection angles of the second multiplexed extension of at least one multiplexed control line of the first group of multiplexed control lines 51a and the multiple multiplexed data lines 61 in the first group of multiplexed data lines 61a may be different.
  • the intersection angle may be less than or equal to 90 degrees.
  • the fourth multiplexing control line 514, the seventh multiplexing control line 517, the eighth multiplexing control line 518, and the ninth multiplexing control line 519 in the first group of multiplexing control lines 51a can be arranged in sequence in a direction away from the first signal access area B14.
  • the present embodiment does not limit the arrangement order of the four multiplexing control lines in the first group of multiplexing control lines 51a.
  • the fourth multiplexing control line 514, the seventh multiplexing control line 517, the eighth multiplexing control line 518, and the ninth multiplexing control line 519 can be arranged in sequence in a direction close to the first signal access area B14.
  • the ninth multiplexing control line 519, the seventh multiplexing control line 517, the eighth multiplexing control line 518, and the fourth multiplexing control line 514 can be arranged in sequence in a direction close to or away from the first signal access area B14.
  • the second group of multiplexing control lines 51 b may be connected to the second group of multiplexing control contact pads 721 b.
  • each multiplexing control line in the second group of multiplexing control lines 51 b may be connected to at least one multiplexing control contact pad 721 in the second group of multiplexing control contact pads 721 b.
  • Each multiplexing control line in the second group of multiplexing control lines 51 b may include at least: a third multiplexing extension segment and a fourth multiplexing extension segment connected to each other.
  • the first multiplexing control line 511 may include: a third multiplexing extension segment 5111 and a fourth multiplexing extension segment 5112 connected to each other, the third multiplexing extension segment 5111 may extend at least along the second direction Y, and the fourth multiplexing extension segment 5112 may extend along the second direction Y. It may extend at least along the first direction X.
  • One end of the third multiplexing extension 5111 is connected to at least one multiplexing control contact pad 721 in the second group of multiplexing control contact pads 721b, and the other end is connected to one end of the fourth multiplexing extension 5112, and the other end of the fourth multiplexing extension 5112 is connected to the first multiplexing control connection line 521 in the second group of multiplexing control connection lines 52b in the second group of control connection lines (for example, the second group of control connection lines 65b shown in FIG. 3).
  • the third multiplexing extension of each multiplexing control line in the second group of multiplexing control lines 51b may be located on the side of the second group of multiplexing data lines 61b away from the first group of multiplexing data lines 61a, and the fourth multiplexing extension of each multiplexing control line may cross the second group of multiplexing data lines 61b.
  • the orthographic projection of each multiplexing data line 61 in the second group of multiplexing data lines 61b and the fourth multiplexing extension of each multiplexing control line of the second group of multiplexing control lines 51b on the substrate may overlap.
  • Each multiplexed data line 61 in the second group of multiplexed data lines 61b may cross the fourth multiplexed extension of each multiplexed control line of the second group of multiplexed control lines 51b.
  • the intersection angles of each multiplexed data line 61 in the second group of multiplexed data lines 61b and the fourth multiplexed extension of each multiplexed control line of the second group of multiplexed control lines 51b may be substantially the same, for example, they may all be 90 degrees.
  • intersection angles of the fourth multiplexed extension of at least one multiplexed control line of the second group of multiplexed control lines 51b and the multiple multiplexed data lines 61 in the second group of multiplexed data lines 61b may be different.
  • the intersection angle may be less than or equal to 90 degrees.
  • the first multiplexing control line 511, the second multiplexing control line 512, the third multiplexing control line 513, the sixth multiplexing control line 516 and the fifth multiplexing control line 515 in the second group of multiplexing control lines 51b can be arranged in sequence in a direction away from the first signal access area B14.
  • the present embodiment does not limit the arrangement order of the five multiplexing control lines in the second group of multiplexing control lines 51b.
  • first multiplexing control line 511, the second multiplexing control line 512, the third multiplexing control line 513, the sixth multiplexing control line 516 and the fifth multiplexing control line 515 can be arranged in sequence in a direction close to the first signal access area B14.
  • first multiplexing control line 511, the third multiplexing control line 513, the second multiplexing control line 512, the sixth multiplexing control line 516 and the fifth multiplexing control line 515 can be arranged in sequence in a direction close to or away from the first signal access area B14.
  • the first group of multiplexing control lines 51a and the second group of multiplexing control lines 51b converge in the middle area of the first group of multiplexing data lines 61a and the second group of multiplexing data lines 61a after bypassing the first signal access area B14.
  • the four multiplexing control lines of the first group of multiplexing control lines 51a overlap with the orthographic projection of each multiplexing data line 61 in the first group of multiplexing data lines 61a on the substrate, and do not overlap with the orthographic projection of the second group of multiplexing data lines 61b on the substrate;
  • the five multiplexing control lines of the second group of multiplexing control lines 51b overlap with the orthographic projection of each multiplexing data line 61 in the second group of multiplexing data lines 61b on the substrate, and do not overlap with the orthographic projection of the first group of multiplexing data lines 61a on the substrate.
  • each multiplexed data line 61 in the first group of multiplexed data lines 61a overlaps with four multiplexed control lines in their orthographic projections on the substrate
  • each multiplexed data line 61 in the second group of multiplexed data lines 61b overlaps with five multiplexed control lines in their orthographic projections on the substrate.
  • Figure 5 is a partially enlarged schematic diagram of area S1 in Figure 3.
  • Figure 7 is a partially enlarged schematic diagram of area S2 in Figure 3.
  • Figure 8A is a schematic diagram of the display panel after the first gate metal layer is formed in Figure 7.
  • Figure 8B is a schematic diagram of the display panel after the second gate metal layer is formed in Figure 7.
  • Figure 8C is a schematic diagram of the display panel after the first source and drain metal layer is formed in Figure 7.
  • Figure 9 is a partially enlarged schematic diagram of area S3 in Figure 3.
  • Figure 10 is a partially enlarged schematic diagram of area S4 in Figure 3.
  • Figures 7 to 8C are illustrated by taking a multiplexing circuit as an example.
  • the first group of control signal lines 66a may include at least: a first group of multiplexing control lines 51a (i.e., including the ninth multiplexing control line 519, the eighth multiplexing control line 518, the seventh multiplexing control line 517, and the fourth multiplexing control line 514), a first group of driving control lines 81a (for example, including: a scan start signal line 811, a first scan clock signal line 821, a second scan clock signal line 831, a first scan output line 841, a first initial signal line 561, a first low voltage line 571, and a first high voltage line 581).
  • a first group of multiplexing control lines 51a i.e., including the ninth multiplexing control line 519, the eighth multiplexing control line 518, the seventh multiplexing control line 517, and the fourth multiplexing control line 514
  • a first group of driving control lines 81a for example, including: a scan start signal line 811, a first scan clock signal line 821
  • the first group of driving control lines 81a may be located on the side of the first group of multiplexing control lines 51a close to the display area.
  • the first high voltage line 581 , the ninth multiplexing control line 519 , the eighth multiplexing control line 518 , the seventh multiplexing control line 517 and the fourth multiplexing control line 514 may be sequentially arranged in the second direction Y along a direction away from the display area.
  • the first group of control connection lines 65a of the second fan-out area B13 can include at least: a first group of multiplexing control connection lines 52a (for example, including: a ninth multiplexing control connection line 529, an eighth multiplexing control connection line 528, a seventh multiplexing control connection line 527 and a fourth multiplexing control connection line 524), a first group of drive control connection lines 82a (for example, including: a scan start connection line 812, a first scan clock connection line 822, a second scan clock connection line 832, a first scan output connection line 842, a first initial connection line 563, a first low voltage connection line 573 and a first high voltage connection line 583).
  • a first group of multiplexing control connection lines 52a for example, including: a ninth multiplexing control connection line 529, an eighth multiplexing control connection line 528, a seventh multiplexing control connection line 527 and a fourth multiplexing control connection line 524
  • the ninth multiplexing control connection line 529 is connected to the ninth multiplexing control line 519
  • the eighth multiplexing control connection line 528 is connected to the eighth multiplexing control line 518
  • the seventh multiplexing control connection line 527 is connected to the seventh multiplexing control line 517
  • the fourth multiplexing control connection line 524 is connected to the fourth multiplexing control line 514.
  • the scan start connection line 812 is connected to the scan start signal line 811
  • the first scan clock connection line 822 is connected to the first scan clock signal line 821
  • the second scan clock connection line 832 is connected to the second scan clock signal line 831
  • the first scan output connection line 842 is connected to the first scan output line 841
  • the first initial connection line 563 is connected to the initial signal line 561
  • the first low voltage connection line 573 is connected to the first voltage line 571
  • the first high voltage connection line 583 is connected to the first high voltage line 581.
  • the first group of multiplexing control connection lines 52a and the first group of driving control connection lines 82a of the first group of control connection lines 65a can extend to the bending area B12 along the second direction Y, and be connected to the first group of control bending connection lines 35a of the bending area B12.
  • the first group of driving control connection lines 82a in the first group of control connection lines 65a can be located on the side of the first group of multiplexing control connection lines 52a close to the first group of multiplexing data lines 61a in the first direction X.
  • the first high-voltage connection line 583, the first initial connection line 563, the first low-voltage connection line 573, the first scan output connection line 842, the scan start connection line 812, the first scan clock connection line 822, the second scan clock connection line 832, the ninth multiplexing control connection line 529, the eighth multiplexing control connection line 528, the seventh multiplexing control connection line 527 and the fourth multiplexing control connection line 524 can be arranged in sequence along the direction away from the first group of multiplexing data lines 61a in the first direction X.
  • the first high-voltage connection line 583, the first initial connection line 563, and the first low-voltage connection line 573 for transmitting constant voltage signals are arranged on one side of the four multiplexed control connection lines close to the first group of multiplexed data lines 61a, so as to avoid interference of the first group of multiplexed control connection lines 52a with the first group of multiplexed data lines 61a.
  • the first group of control signal lines 66a can be a same-layer structure, for example, all located in the first source and drain metal layer.
  • the routing lines in the first group of control connection lines 65a can be, for example, all double-layer routing lines, for example, can be located in the first gate metal layer and the second gate metal layer.
  • the ninth multiplexing control connection line 529 may include: a first routing line 5291 located in the first gate metal layer and a second routing line 5292 located in the second gate metal layer, and the ninth multiplexing control line 519 can be located in the first source and drain metal layer.
  • the ninth multiplexing control line 519 can be connected to the first routing line 5291 and the second routing line 5292 of the ninth multiplexing control connection line 529 through a via opened in the insulating layer.
  • the first routing line 5291 of the ninth multiplexing control connection line 529 can extend along the second direction Y to the first signal access area B14, for example, it can be connected to the first invalid contact pad (not shown) in the first signal access area B14.
  • the ninth multiplexing control line 519 can also be connected to the second invalid contact pad (not shown) in the first signal access area B14 through a connecting line at a position bypassing the first signal access area B14, and the second invalid contact pad can be located on the side of the first contact pad connected to the first group of multiplexing data lines 61a away from the first invalid contact pad in the first direction X; the first invalid contact pad and the second invalid contact pad can be electrically connected through the contact pad connecting line, and by setting a parallel line of the ninth multiplexing control line in the first signal access area B14, it is helpful to reduce the resistance of the ninth multiplexing control line.
  • the film layer structures of the remaining control signal lines and control connecting lines are roughly the same, so they are not repeated here.
  • the second group of control signal lines 66 b may include at least: a second group of multiplexing control lines 51 b (i.e., including a first multiplexing control line 511, a second multiplexing control line 512, a third multiplexing control line 513, a sixth multiplexing control line 516, and a fifth multiplexing control line 515), a second group of driving control lines 81 b (e.g., including: a light emitting
  • the second group of drive control lines 81b can be located on the side of the second group of multiplexing control lines 51b close to the display area.
  • the light-emitting start signal line 851, the first light-emitting clock signal line 861, the second light-emitting clock signal line 871, the second light-emitting output line 881, the second initial signal line 562, the second low-voltage line 572, and the second high-voltage line 582, the first multiplexing control line 511, the second multiplexing control line 512, the third multiplexing control line 513, the sixth multiplexing control line 516, and the fifth multiplexing control line 515 can be arranged in sequence along the direction away from the display area.
  • the second group of control connection lines 65b of the second fan-out area B13 can include at least: a second group of multiplexed control connection lines 52b (for example, including: a first multiplexed control connection line 521, a second multiplexed control connection line 522, a third multiplexed control connection line 523, a sixth multiplexed control connection line 526 and a fifth multiplexed control connection line 525), a second group of drive control connection lines 82b (for example, including: a light-emitting start connection line 852, a first light-emitting clock connection line 862, a second light-emitting clock connection line 872, a first light-emitting output connection line 882, a second initial connection line 564, a second low voltage connection line 574 and a second high voltage connection line 584).
  • a second group of multiplexed control connection lines 52b for example, including: a first multiplexed control connection line 521, a second multiplexed control connection line 5
  • the first multiplexed control connection line 521 is connected to the first multiplexed control line 511
  • the second multiplexed control connection line 522 is connected to the second multiplexed control line 512
  • the third multiplexed control connection line 523 is connected to the third multiplexed control line 513
  • the sixth multiplexed control connection line 526 is connected to the sixth multiplexed control line 516
  • the fifth multiplexed control connection line 525 is connected to the fifth multiplexed control line 515.
  • the light-emitting start connection line 852 is connected to the light-emitting start signal line 851
  • the first light-emitting clock connection line 862 is connected to the first light-emitting clock signal line 861
  • the second light-emitting clock connection line 872 is connected to the second light-emitting clock signal line 871
  • the first light-emitting output connection line 882 is connected to the first light-emitting output line 881
  • the second initial connection line 564 is connected to the second initial signal line 562
  • the second low voltage connection line 574 is connected to the second voltage line 572
  • the second high voltage connection line 584 is connected to the second high voltage line 582.
  • the first initial signal line 561 and the second initial signal line 562 may be an integrated structure connected to each other, and the first initial signal line 561 and the second initial signal line 562 may be configured to transmit an initial signal.
  • the first low voltage line 571 and the second low voltage line 572 may be an integrated structure connected to each other.
  • the first low voltage line 571 and the second low voltage line 572 may be configured to transmit a first voltage signal.
  • the first high voltage line 581 and the second high voltage line 572 may be an integrated structure connected to each other.
  • the first high voltage line 581 and the second high voltage line 582 may be configured to transmit a second voltage signal.
  • the second voltage signal may be greater than the first voltage signal.
  • the second group of multiplexing control connection lines 52b and the second group of driving control connection lines 82b of the second group of control connection lines 65b may extend to the bending region B12 along the second direction Y and be connected to the second group of control bending connection lines 35b of the bending region B12.
  • the second group of driving control connection lines 82b of the second group of control connection lines 65b may be located on a side of the second group of multiplexing control connection lines 52b close to the second group of multiplexing data lines 61b in the first direction X.
  • the second high-voltage connection line 584, the second initial connection line 564, the second low-voltage connection line 574, the first light-emitting output connection line 882, the light-emitting start connection line 852, the first light-emitting clock connection line 862, the second light-emitting clock connection line 872, the first multiplexing control connection line 521, the second multiplexing control connection line 522, the third multiplexing control connection line 523, the sixth multiplexing control connection line 526 and the fifth multiplexing control connection line 525 can be sequentially arranged in the first direction X along the direction away from the second group of multiplexing data lines 61b.
  • the second high-voltage connection line 584, the second initial connection line 564 and the second low-voltage connection line 574 transmitting the constant voltage signal are arranged on the side of the five multiplexing control connection lines close to the second group of multiplexing data lines 61b, which can avoid the interference of the second group of multiplexing control connection lines 52b on the second group of multiplexing data lines 61b.
  • the second group of control signal lines 66 b may be of the same layer structure, for example, all located in the first source and drain metal layer.
  • the routing lines in the second group of control connection lines 65 b may be, for example, all double-layer routing lines, for example, located in the first gate metal layer and the second gate metal layer.
  • the film layer structure of the second group of control signal lines 66 b and the second group of control connection lines 65 b may refer to the film layer structure of the first group of control signal lines 66 a and the first group of control connection lines 65 a, so it will not be described in detail here.
  • the first main body of the first power line 311 of the first fan-out area B11 may be located at the midline position of the first fan-out area B11 along the first direction X, for example.
  • the first main body of the first power line 311 may be electrically connected to the first power connection line 31 of the bending area B12, for example, it may be an integrated structure connected to each other.
  • the first power connection line 31 may have a plurality of hollow portions arranged along the second direction Y, and the shapes and sizes of the plurality of hollow portions may be substantially the same.
  • the stress accumulated on the line during the bending process can be relieved, which is conducive to releasing the stress when the line is bent, thereby improving the bending effect.
  • the edges of the first power connection line 31 on both sides in the first direction X may be wavy.
  • the edge of the bending connection line may be formed into a wavy shape by connecting a plurality of arc segments.
  • the first group of control lead-out lines 64 a on the left side of the first main body of the first power line 311 of the first fan-out area B11 may include: a first group of multiplexed control first lead-out lines 53 a (for example, including: a ninth multiplexed control first lead-out line 539, an eighth multiplexed control first lead-out line 538, a seventh multiplexed control first lead-out line 537, and a fourth multiplexed control first lead-out line 534), a group of multiplexed control second lead-out lines 54 (for example, including: a ninth multiplexed control second lead-out line 549, an eighth multiplexed control second lead-out line 548, a seventh multiplexed control second lead-out line 549, and a Line 547, the sixth multiplexing control second lead line 546, the fifth multiplexing control second lead line 545, the fourth multiplexing control second lead line 544, the
  • the ninth multiplexed control first lead 539, the eighth multiplexed control first lead 538, the seventh multiplexed control first lead 537, and the fourth multiplexed control first lead 534 may extend along the second direction Y.
  • the ninth multiplexed control first lead 539, the eighth multiplexed control first lead 538, the seventh multiplexed control first lead 537, and the fourth multiplexed control first lead 534 may be located on one side of the first group of drive control lead 83a close to the first main body of the first power line 311 in the first direction X.
  • the ninth multiplexed control first lead 539, the eighth multiplexed control first lead 538, the seventh multiplexed control first lead 537, and the fourth multiplexed control first lead 534 may be arranged in sequence along the direction close to the first main body of the first power line 311 in the first direction X.
  • the first scan clock lead line 823, the second scan clock lead line 833, the scan start lead line 813, the scan output lead line 843, the first low voltage lead line 575, the first initial lead line 565 and the first high voltage lead line can be arranged in sequence along the first direction X in the direction of the first main body of the ninth multiplexing control first lead line 539 away from the first power line 311.
  • the second group of control lead lines 64 b on the right side of the first main body of the first power line 311 of the first fan-out area B11 may include: a second group of multiplexing control first lead lines 53 b (for example, including: a first multiplexing control first lead line 531, a second multiplexing control first lead line 532, a third multiplexing control first lead line 533, a sixth multiplexing control first lead line 536, and a fifth multiplexing control first lead line 535), a group of multiplexing control third lead lines 55 (for example, including: a ninth multiplexing control third lead line 559, an eighth multiplexing control third lead line 558, a seventh multiplexing control third lead line 559, a seventh multiplexing control third lead line 551, a seventh multiplexing control third lead line 552, a seventh multiplexing control third lead line 553, a seventh multiplexing control third lead line 554, a seventh multiplexing control third lead line
  • Use control third lead line 557, sixth multiplexing control third lead line 556, fifth multiplexing control third lead line 555, fourth multiplexing control third lead line 554, third multiplexing control third lead line 553, second multiplexing control third lead line 552, first multiplexing control third lead line 551), second group of drive control lead lines 83b for example, including: light start lead line 853, first light-emitting clock lead line 863, second light-emitting clock lead line 873, first light-emitting output lead line 883, second initial lead line 566, second low voltage lead line 576, second high voltage lead line (not shown)).
  • the first multiplexing control first lead line 531, the second multiplexing control first lead line 532, the third multiplexing control first lead line 533, the sixth multiplexing control first lead line 536, and the fifth multiplexing control first lead line 535 may extend substantially along the second direction Y.
  • the first multiplexing control first lead line 531, the second multiplexing control first lead line 532, the third multiplexing control first lead line 533, the sixth multiplexing control first lead line 536, and the fifth multiplexing control first lead line 535 may extend substantially along the second direction Y.
  • the multiplexed control first lead 535 may be located on the side of the first main body of the second group of driving control lead 83b close to the first power line 311 in the first direction X.
  • the first multiplexed control first lead 531, the second multiplexed control first lead 532, the third multiplexed control first lead 533, the sixth multiplexed control first lead 536 and the fifth multiplexed control first lead 535 may be arranged in sequence along the direction close to the first main body of the first power line 311 in the first direction X.
  • the second light-emitting clock lead 873, the first light-emitting clock lead 863, the light-emitting start lead 853, the light-emitting output lead 883, the second low-voltage lead 576, the second initial lead 566 and the second high-voltage lead may be arranged in sequence along the first direction X in the direction of the first multiplexed control lead 531 away from the first main body of the first power line 311.
  • a group of multiplexing control second lead lines 54 and a group of multiplexing control third lead lines 55 may extend at least along the first direction X.
  • a group of multiplexing control second lead lines 54 and a group of multiplexing control third lead lines 55 may be of the same layer structure, for example, may be located in the first source and drain metal layer.
  • a group of multiplexing control second lead lines 54 and a group of multiplexing control third lead lines 55 may be electrically connected via a connection line located in the first gate metal layer.
  • the ninth multiplexed control second lead line 549, the eighth multiplexed control second lead line 548, the seventh multiplexed control second lead line 547, the sixth multiplexed control second lead line 546, the fifth multiplexed control second lead line 545, the fourth multiplexed control second lead line 544, the third multiplexed control second lead line 543, the second multiplexed control second lead line 542, and the first multiplexed control second lead line 541 can be arranged in sequence in the second direction Y along the direction close to the display area AA.
  • the ninth multiplexing control third lead line 559, the eighth multiplexing control third lead line 558, the seventh multiplexing control third lead line 557, the sixth multiplexing control third lead line 556, the fifth multiplexing control third lead line 555, the fourth multiplexing control third lead line 554, the third multiplexing control third lead line 553, the second multiplexing control third lead line 552, and the first multiplexing control third lead line 551 can be arranged in sequence in the second direction Y along the direction close to the display area AA.
  • the ninth multiplexing control second lead line 549 is connected to the ninth multiplexing control first lead line 539 through a via provided in the insulating layer, so that the ninth multiplexing control second lead line 549 provides a ninth multiplexing control signal to the multiple multiplexing circuits 40 in the left area of the first power line 311; the ninth multiplexing control second lead line 549 is connected to the ninth multiplexing control third lead line 559, so that the ninth multiplexing control third lead line 559 provides a ninth multiplexing control signal to the multiple multiplexing circuits 40 in the right area of the first power line 311.
  • the eighth multiplexing control second lead line 548 is connected to the eighth multiplexing control first lead line 538 through a via set in the insulating layer, so that the eighth multiplexing control second lead line 548 provides the eighth multiplexing control signal to the multiple multiplexing circuits 40 in the left area of the first power line 311; the eighth multiplexing control second lead line 548 is connected to the eighth multiplexing control third lead line 558, so that the eighth multiplexing control third lead line 558 provides the eighth multiplexing control signal to the multiple multiplexing circuits 40 in the right area of the first power line 311.
  • the seventh multiplexing control second lead line 547 is connected to the seventh multiplexing control first lead line 537 through a via set in the insulating layer, so that the seventh multiplexing control second lead line 547 provides the seventh multiplexing control signal to the multiple multiplexing circuits 40 in the left area of the first power line 311; the seventh multiplexing control second lead line 547 is connected to the seventh multiplexing control third lead line 557, so that the seventh multiplexing control third lead line 557 provides the seventh multiplexing control signal to the multiple multiplexing circuits 40 in the right area of the first power line 311.
  • the fourth multiplexing control second lead line 544 is connected to the fourth multiplexing control first lead line 534 through a via set in the insulating layer, so that the fourth multiplexing control second lead line 544 provides a fourth multiplexing control signal to the multiple multiplexing circuits 40 in the left area of the first power line 311; the fourth multiplexing control second lead line 544 is connected to the fourth multiplexing control third lead line 554, so that the fourth multiplexing control third lead line 554 provides a fourth multiplexing control signal to the multiple multiplexing circuits 40 in the right area of the first power line 311.
  • the fifth multiplexing control third lead line 555 is connected to the fifth multiplexing control first lead line 535 through a via hole provided in the insulating layer, so that the fifth multiplexing control third lead line 555 is provided to the right area of the first power line 311.
  • the fifth multiplexing control third lead line 555 is connected to the fifth multiplexing control second lead line 545, so that the fifth multiplexing control second lead line 545 provides a fifth multiplexing control signal to multiple multiplexing circuits 40 in the area on the left side of the first power line 311.
  • the sixth multiplexing control third lead line 556 is connected to the sixth multiplexing control first lead line 536 through a via set in the insulating layer, so that the sixth multiplexing control third lead line 556 provides the sixth multiplexing control signal to the multiple multiplexing circuits 40 in the right area of the first power line 311; the sixth multiplexing control third lead line 556 is connected to the sixth multiplexing control second lead line 546, so that the sixth multiplexing control second lead line 546 provides the sixth multiplexing control signal to the multiple multiplexing circuits 40 in the left area of the first power line 311.
  • the third multiplexing control third lead line 553 is connected to the third multiplexing control first lead line 533 through a via set in the insulating layer, so that the third multiplexing control third lead line 553 provides a third multiplexing control signal to multiple multiplexing circuits 40 in the right area of the first power line 311; the third multiplexing control third lead line 553 is connected to the third multiplexing control second lead line 543, so that the third multiplexing control second lead line 543 provides a third multiplexing control signal to multiple multiplexing circuits 40 in the left area of the first power line 311.
  • the second multiplexing control third lead line 552 is connected to the second multiplexing control first lead line 532 through a via set in the insulating layer, so that the second multiplexing control third lead line 552 provides a second multiplexing control signal to the multiple multiplexing circuits 40 in the right area of the first power line 311; the second multiplexing control third lead line 552 is connected to the second multiplexing control second lead line 542, so that the second multiplexing control second lead line 542 provides a second multiplexing control signal to the multiple multiplexing circuits 40 in the left area of the first power line 311.
  • the first multiplexing control third lead line 551 is connected to the first multiplexing control first lead line 531 through a via set in the insulating layer, so that the first multiplexing control third lead line 551 provides a first multiplexing control signal to multiple multiplexing circuits 40 in the area to the right of the first power line 311; the first multiplexing control third lead line 551 is connected to the first multiplexing control second lead line 541, so that the first multiplexing control second lead line 541 provides a first multiplexing control signal to multiple multiplexing circuits 40 in the area to the left of the first power line 311.
  • the wiring method of the first group of control lead lines 64a and the second group of control lead lines 64b in the first fan-out area of this example helps to transmit the first multiplexed control signal to the ninth multiplexed control signal to the multiplexing circuits in the left and right areas of the first power line 311, and can save wiring space, which is conducive to narrowing the border.
  • the ninth multiplexing control first lead 539 can be electrically connected to the electrostatic discharge circuit 41.
  • the ninth multiplexing control first lead 539 may include a wiring located in the first gate metal layer and a wiring located in the second gate metal layer, and the wiring located in the first gate metal layer and the wiring located in the second gate metal layer may be electrically connected through a connecting electrode located in the first source-drain metal layer.
  • the structures of the remaining multiplexing control first lead wires are similar, so they are not described here.
  • the active layers of the nine multiplexing transistors of the multiplexing circuit are located in the semiconductor layer.
  • the active layer of each multiplexing transistor may include: a first region, a second region, and a channel region located between the first region and the second region.
  • the first active layer M10 of the first multiplexing transistor M1, the second active layer M20 of the second multiplexing transistor M2, the third active layer M30 of the third multiplexing transistor M3, the fourth active layer M40 of the fourth multiplexing transistor M4, the fifth active layer M50 of the fifth multiplexing transistor M5, the sixth active layer M60 of the sixth multiplexing transistor M6, the seventh active layer M70 of the seventh multiplexing transistor M7, the eighth active layer M80 of the eighth multiplexing transistor M8, and the ninth active layer M90 of the ninth multiplexing transistor M9 may be arranged in sequence along the first direction X.
  • the second active layer M20 and the third active layer M30 can be an integrated structure connected to each other
  • the fifth active layer M50 and the sixth active layer M60 can be an integrated structure connected to each other
  • the eighth active layer M80 and the ninth active layer M90 can be an integrated structure connected to each other, thereby reducing the occupied space of the multiplexing circuit.
  • this embodiment is not limited to this.
  • the active layers of the nine multiplexing transistors can be independently set.
  • the gates of the nine multiplexing transistors of the multiplexing circuit may be located at the first gate metal layer.
  • the positive projection of the gate of each multiplexing transistor on the substrate may cover the positive projection of the channel region of the corresponding active layer on the substrate.
  • the gate M13 of the first multiplexing transistor M1, the gate M23 of the second multiplexing transistor M2, the gate M33 of the third multiplexing transistor M3, the gate M43 of the fourth multiplexing transistor M4, the gate M53 of the fifth multiplexing transistor M5, the gate M63 of the sixth multiplexing transistor M6, the gate M73 of the seventh multiplexing transistor M7, the gate M83 of the eighth multiplexing transistor M8, and the gate M93 of the ninth multiplexing transistor M9 may all extend along the second direction Y and be arranged in sequence along the first direction X.
  • the first and second electrodes of the nine multiplexing transistors of the multiplexing circuit can be located at the first source-drain metal layer.
  • the first electrode M11 of the first multiplexing transistor M1 can simultaneously serve as the first electrode of the second multiplexing transistor M2 and the first electrode of the third multiplexing transistor M3.
  • the first electrode M11 of the first multiplexing transistor M1 can be connected to the first region of the first active layer M10 of the first multiplexing transistor M1, the first region of the second active layer M20 of the second multiplexing transistor M2, and the first region of the third active layer M30 of the third multiplexing transistor M3 through multiple vias opened in the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer, and can also be electrically connected to the multiplexing data lead-out line 62 located at the first gate metal layer through the vias opened in the interlayer insulating layer and the second gate insulating layer.
  • the second electrode M12 of the first multiplexing transistor M1 can be connected to the second region of the first active layer M10 of the first multiplexing transistor M1 through multiple vias opened in the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer, and can also be electrically connected to the data fan-out line 63 located in the first gate metal layer through the vias opened in the interlayer insulating layer and the second gate insulating layer.
  • the second electrode M22 of the second multiplexing transistor M2 can be connected to the second region of the second active layer M20 of the second multiplexing transistor M2 through multiple vias opened in the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer, and can also be electrically connected to the data fan-out line 63 located in the second gate metal layer through the vias opened in the interlayer insulating layer.
  • the second electrode M32 of the third multiplexing transistor M3 can be connected to the second region of the third active layer M30 through multiple vias opened in the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer, and can also be electrically connected to the data fan-out line 63 located in the first gate metal layer through the vias opened in the interlayer insulating layer and the second gate insulating layer.
  • the first electrode M41 of the fourth multiplexing transistor M4 can simultaneously serve as the first electrode of the fifth multiplexing transistor M5 and the first electrode of the sixth multiplexing transistor M6.
  • the first electrode M41 of the fourth multiplexing transistor M4 can be connected to the first area of the fourth active layer M40 of the fourth multiplexing transistor M4, the first area of the fifth active layer M50 of the fifth multiplexing transistor M5, and the first area of the sixth active layer M60 of the sixth multiplexing transistor M6 through multiple vias opened in the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer, and can also be electrically connected to the multiplexing data lead-out line 62 located in the first gate metal layer through vias opened in the interlayer insulating layer and the second gate insulating layer.
  • the second electrode M42 of the fourth multiplexing transistor M4 can be connected to the second region of the fourth active layer M40 of the fourth multiplexing transistor M4 through multiple vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer, and can also be electrically connected to the data fan-out line 63 located at the second gate metal layer through the vias opened in the interlayer insulating layer.
  • the second electrode M52 of the fifth multiplexing transistor M5 can be connected to the second region of the fifth active layer M50 of the fifth multiplexing transistor M5 through multiple vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer, and can also be electrically connected to the data fan-out line 63 located at the first gate metal layer through the vias opened in the interlayer insulating layer and the second gate insulating layer.
  • the second electrode M62 of the sixth multiplexing transistor M6 can be connected to the second region of the sixth active layer M60 through multiple vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer, and can also be electrically connected to the data fan-out line 63 located at the second gate metal layer through the vias opened in the interlayer insulating layer.
  • the first electrode M71 of the seventh multiplexing transistor M7 can simultaneously serve as the first electrode of the eighth multiplexing transistor M8 and the first electrode of the ninth multiplexing transistor M9.
  • the first electrode M71 of the seventh multiplexing transistor M7 can be connected to the first area of the seventh active layer M70 of the seventh multiplexing transistor M7, the first area of the eighth active layer M80 of the eighth multiplexing transistor M8, and the first area of the ninth active layer M90 of the ninth multiplexing transistor M9 through multiple vias opened in the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer, and can also be connected to the first area of the ninth active layer M90 of the ninth multiplexing transistor M9 through multiple vias opened in the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.
  • the via hole is electrically connected to the multiplexed data lead line 62 located on the first gate metal layer.
  • the second electrode M72 of the seventh multiplexing transistor M7 can be connected to the second region of the first active layer M70 of the seventh multiplexing transistor M7 through multiple vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer, and can also be electrically connected to the data fan-out line 63 located in the first gate metal layer through the vias opened in the interlayer insulating layer and the second gate insulating layer.
  • the second electrode M82 of the eighth multiplexing transistor M8 can be connected to the second region of the eighth active layer M80 of the eighth multiplexing transistor M8 through multiple vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer, and can also be electrically connected to the data fan-out line 63 located in the second gate metal layer through the vias opened in the interlayer insulating layer.
  • the second electrode M92 of the ninth multiplexing transistor M9 can be connected to the second region of the ninth active layer M90 through multiple vias opened in the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer, and can also be electrically connected to the data fan-out line 63 located in the first gate metal layer through the vias opened in the interlayer insulating layer and the second gate insulating layer.
  • a plurality of data fan-out lines 63 may be alternately arranged in the first gate metal layer and the second gate metal layer.
  • a plurality of multiplexed data lead-out lines 62 may be alternately arranged in the first gate metal layer and the second gate metal layer. This embodiment is not limited to this.
  • the gate M13 of the first multiplexing transistor M1 may be electrically connected to the first multiplexing control second lead 541 through a via hole opened in the interlayer insulating layer and the second gate insulating layer.
  • the gate M23 of the second multiplexing transistor M2 may be electrically connected to the second multiplexing control second lead 542.
  • the gate M33 of the third multiplexing transistor M3 may be electrically connected to the third multiplexing control second lead 543.
  • the gate M43 of the fourth multiplexing transistor M4 may be electrically connected to the fourth multiplexing control second lead 544.
  • the gate M53 of the fifth multiplexing transistor M5 may be electrically connected to the fifth multiplexing control second lead 545.
  • the gate M63 of the sixth multiplexing transistor M6 may be electrically connected to the sixth multiplexing control second lead 546.
  • the gate M73 of the seventh multiplexing transistor M7 may be electrically connected to the seventh multiplexing control second lead 547.
  • the gate M83 of the eighth multiplexing transistor M8 may be electrically connected to the eighth multiplexing control second lead 548.
  • the gate M93 of the ninth multiplexing transistor M9 may be electrically connected to the ninth multiplexing control second lead-out line 549 .
  • the ninth multiplexing control second lead line 549, the eighth multiplexing control second lead line 548, the seventh multiplexing control second lead line 547, the sixth multiplexing control second lead line 546, the fifth multiplexing control second lead line 545, the fourth multiplexing control second lead line 544, the third multiplexing control second lead line 543, the second multiplexing control second lead line 542, and the first multiplexing control second lead line 541 can be located at the first source-drain metal layer.
  • a third low-voltage lead line 577, a second scan clock second lead line 834, a first scan clock second lead line 824, and a third high-voltage lead line 587 can be arranged on one side of a group of multiplexing control second lead lines 54 close to the multiplexing circuit; the third low-voltage lead line 577, the second scan clock second lead line 834, the first scan clock second lead line 824, and the third high-voltage lead line 587 can be arranged in sequence along the direction away from the multiplexing circuit.
  • a first scan output second lead line 844 may be provided on a side of a group of multiplexing control second lead lines 54 away from the multiplexing circuit.
  • the third low voltage lead 577 can be electrically connected to the first low voltage lead 575, and the third low voltage lead 577 can provide a first voltage signal to the gate drive circuit in the left frame area.
  • the third high voltage lead 587 can be electrically connected to the first high voltage lead, and the third high voltage lead 587 can provide a second voltage signal to the gate drive circuit in the left frame area.
  • the first scan clock second lead 824 can be electrically connected to the first scan clock lead 823, and the second scan clock second lead 834 can be electrically connected to the second scan clock lead 833.
  • the first scan clock second lead 824 and the second scan clock second lead 834 can provide a scan clock signal to the gate drive circuit.
  • the first scan output second lead 844 can be electrically connected to the first scan output lead 843.
  • the structure of the multiplexing circuit in the right area of the first power line 311 is similar to that in the left area, so it is not repeated here.
  • the multiplexing circuit in the right area can be electrically connected to a set of multiplexing control third lead lines 55.
  • the wiring for signal transmission in the first border region of this example may be as shown in Table 1.
  • the data signal can be provided by the first contact pad in the first signal access area B14, and the drive control signal, the first power signal, the second power signal and the multiplexing control signal (for example, including the first multiplexing control signal to the ninth multiplexing control signal) can be provided by the second contact pad in the second signal access area B15.
  • the ninth multiplexing control line 519, the ninth multiplexing control connection line 529, the control bend connection line, the ninth multiplexing control first lead line 539, the ninth multiplexing control second lead line 549 and the ninth multiplexing control third lead line 559 can be connected in sequence to provide the ninth multiplexing control signal to multiple multiplexing circuits 40.
  • the eighth multiplexing control line 518, the eighth multiplexing control connection line 528, the control bending connection line, the eighth multiplexing control first lead line 538, the eighth multiplexing control second lead line 548 and the eighth multiplexing control third lead line 558 can be connected in sequence to provide the eighth multiplexing control signal to multiple multiplexing circuits 40.
  • the seventh multiplexing control line 517, the seventh multiplexing control connection line 529, the control bend connection line, the seventh multiplexing control first lead line 537, the seventh multiplexing control second lead line 547 and the seventh multiplexing control third lead line 557 can be connected in sequence to provide the seventh multiplexing control signal to multiple multiplexing circuits 40.
  • the fourth multiplexing control line 514, the fourth multiplexing control connection line 524, the control bending connection line, the fourth multiplexing control first lead line 534, the fourth multiplexing control second lead line 544 and the fourth multiplexing control third lead line 554 can be connected in sequence to provide the fourth multiplexing control signal to multiple multiplexing circuits 40.
  • the sixth multiplexing control line 516, the sixth multiplexing control connection line 526, the control bend connection line, the sixth multiplexing control first lead line 536, the sixth multiplexing control third lead line 556 and the sixth multiplexing control second lead line 546 can be connected in sequence to provide the sixth multiplexing control signal to multiple multiplexing circuits 40.
  • the fifth multiplexing control line 515, the fifth multiplexing control connection line 525, the control bending connection line, the fifth multiplexing control first lead line 535, the fifth multiplexing control third lead line 555 and the fifth multiplexing control second lead line 545 can be connected in sequence to provide the fifth multiplexing control signal to multiple multiplexing circuits 40.
  • the third multiplexing control line 513, the third multiplexing control connection line 523, the control bending connection line, the third multiplexing control first lead line 533, the third multiplexing control third lead line 553 and the third multiplexing control second lead line 543 can be connected in sequence to provide the third multiplexing control signal to multiple multiplexing circuits 40.
  • the second multiplexing control line 512, the second multiplexing control connection line 522, the control bend connection line, the second multiplexing control first lead line 532, the second multiplexing control third lead line 552 and the second multiplexing control second lead line 542 can be connected in sequence to provide the second multiplexing control signal to multiple multiplexing circuits 40.
  • the first multiplexing control line 515, the first multiplexing control connection line 521, the control bending connection line, the first multiplexing control first lead line 531, the first multiplexing control third lead line 551 and the first multiplexing control second lead line 541 can be connected in sequence to provide the first multiplexing control signal to multiple multiplexing circuits 40.
  • the first group of multiplexed data lines 61a can be configured to provide data signals to sub-pixels in the left area of the display area
  • the second group of multiplexed data lines 61b can be configured to provide data signals to sub-pixels in the right area of the display area.
  • the first group of multiplexed data lines 61a overlaps with four multiplexed control lines
  • the second group of multiplexed data lines 61b overlaps with five multiplexed control lines.
  • the brightness data of the display area of this example is shown in Table 2.
  • the brightness difference rate in Table 2 may refer to the ratio of the absolute value of the brightness difference between the left area and the right area to the brightness of the left area.
  • the brightness difference of the same color sub-pixels in the left and right areas of the display area that are controlled by the same reset control signal to provide data signals is less than 0.06%, and the brightness difference is invisible to the naked eye.
  • the grouping method of the multiplexed control lines of this example can improve the display defects such as split screen caused by the signal load difference generated by the overlap of the multiplexed data lines and the multiplexed control lines.
  • FIG11 is another exemplary diagram of the arrangement of multiplexed control lines and multiplexed data lines according to at least one embodiment of the present disclosure.
  • only a number of multiplexed data lines are used as an example for illustration. This embodiment does not limit the number of multiplexed data lines.
  • This example uses the 1:9 design shown in FIG. 4 as an example for illustration.
  • the plurality of second contact pads within the second signal access area B15 may include: a plurality of multiplexing control contact pads 721 and a group of intermediate contact pads 722.
  • the plurality of multiplexing control contact pads 721 may include a first group of multiplexing control contact pads 721a and a second group of multiplexing control contact pads 721b.
  • the first group of multiplexing control contact pads 721a and the second group of multiplexing control contact pads 721b may be located on opposite sides of a group of intermediate contact pads 722 along the first direction X.
  • the multiplexed control line that controls the multiplexing circuit to provide a data signal to the first sub-pixel emitting the first color light may be a first type multiplexed control line
  • the multiplexed control line that controls the multiplexing circuit to provide a data signal to the second sub-pixel emitting the second color light e.g., green light
  • the multiplexed control line that controls the multiplexing circuit to provide a data signal to the third sub-pixel emitting the third color light e.g., blue light
  • the multiplexed control line that controls the multiplexing circuit to provide a data signal to the third sub-pixel emitting the third color light may be a third type multiplexed control line.
  • the first type multiplexed control line may include: a first multiplexed control line 511, a fourth multiplexed control line 514, and a seventh multiplexed control line 517;
  • the second type multiplexed control line may include: a second multiplexed control line 512, a fifth multiplexed control line 515, and an eighth multiplexed control line 518;
  • the third type multiplexed control line may include: a third multiplexed control line 513, a sixth multiplexed control line 516, and a ninth multiplexed control line 519.
  • the nine multiplexing control lines may include a first group of multiplexing control lines 51a and a second group of multiplexing control lines 51b.
  • the first group of multiplexing control lines 51a may include: a first type of multiplexing control line (i.e., including the seventh multiplexing control line 517, the fourth multiplexing control line 514, the first multiplexing control line 511) and a third type of multiplexing control line (e.g., the third multiplexing control line 513).
  • the second group of multiplexing control lines 51b may include: a second type of multiplexing control line (i.e., including the second multiplexing control line 512, the fifth multiplexing control line 515, the eighth multiplexing control line 518) and the remaining third type of multiplexing control lines (e.g., the sixth multiplexing control line 516 and the ninth multiplexing control line 519).
  • the first group of multiplexing control lines may include: a first type of multiplexing control line and two third type of multiplexing control lines;
  • the second group of multiplexing control lines may include: a second type of multiplexing control line and a third type of multiplexing control line.
  • the seventh multiplexing control line 517, the fourth multiplexing control line 514, the first multiplexing control line 511 and the third multiplexing control line 513 can be arranged in sequence along the direction close to the first signal access area B14.
  • the second multiplexing control line 512, the fifth multiplexing control line 515, the eighth multiplexing control line 518, the sixth multiplexing control line 516 and the ninth multiplexing control line 519 can be arranged in sequence along the direction away from the first signal access area B14.
  • this embodiment does not limit the arrangement order of multiple multiplexing control lines in each group of multiplexing control lines.
  • the third multiplexing control line 513, the seventh multiplexing control line 517, the fourth multiplexing control line 514 and the first multiplexing control line 511 can be arranged in sequence along the direction away from or close to the first signal access area.
  • the sixth multiplexing control line 516 and the ninth multiplexing control line 519 , the second multiplexing control line 512 , the fifth multiplexing control line 515 and the eighth multiplexing control line 518 may be sequentially arranged in a direction away from or close to the first signal access area B14 .
  • the first group of multiplexed control lines 51a may overlap with the first group of multiplexed data lines 61a in their orthographic projections on the substrate, and may not overlap with the second group of multiplexed data lines 61b in their orthographic projections on the substrate.
  • the second group of multiplexed control lines 51b may overlap with the second group of multiplexed data lines 61b in their orthographic projections on the substrate, and may not overlap with the first group of multiplexed data lines 61a in their orthographic projections on the substrate.
  • Each multiplexed data line of the first group of multiplexed data lines 61a overlaps with the orthographic projections of four multiplexed control lines on the substrate, and each multiplexed data line of the second group of multiplexed data lines 61b overlaps with the orthographic projections of five multiplexed control lines on the substrate.
  • the first type of multiplexing control line that controls the provision of data signals to the first sub-pixel and the second type of multiplexing control line that controls the provision of data signals to the second sub-pixel (for example, the first type of multiplexing control line and the second type of multiplexing control line can be respectively routed from opposite sides of the first signal access region, so that the number of multiplexing control lines routed from opposite sides of the first signal access region is the same), it can be ensured that The uniformity of the red light emitted by the first sub-pixel and the green light emitted by the second sub-pixel; since the human eye is least sensitive to the blue light emitted by the third sub-pixel, by adopting an asymmetric wiring design for the third type of multiplexing control line that controls the data signal provided to the third sub-pixel (for example, there is a difference in the number of third type multiplexing control lines that are wound from the opposite sides of the first signal access area, one third
  • the asymmetric wiring of the multiplexing control line in this example refers to the inconsistency of the number of multiplexing control lines arranged on the opposite sides of the first signal access area, and the symmetric wiring refers to the consistency of the number of multiplexing control lines arranged on the opposite sides of the first signal access area.
  • the arrangement of the nine multiplexed control lines used in this example can improve the local display differences in the display area caused by the signal load differences caused by the overlap of the multiplexed control lines and the multiplexed data lines caused by the asymmetric design of the odd number of multiplexed control lines, thereby improving the display effect.
  • FIG12 is another example diagram of the arrangement of multiplexed control lines and multiplexed data lines of at least one embodiment of the present disclosure.
  • FIG12 only takes a number of multiplexed data lines as an example for illustration.
  • the present embodiment does not limit the number of multiplexed data lines.
  • the present example takes the multiplexing circuit using the 1:9 design shown in FIG4 as an example for illustration.
  • the nine multiplexing control lines may include a first group of multiplexing control lines 51a and a second group of multiplexing control lines 51b.
  • the first group of multiplexing control lines 51a may include the following four multiplexing control lines: a ninth multiplexing control line 519, an eighth multiplexing control line 518, a seventh multiplexing control line 517, and a sixth multiplexing control line 516.
  • the second group of multiplexing control lines 51b may include the following five multiplexing control lines: a first multiplexing control line 511, a second multiplexing control line 512, a third multiplexing control line 513, a fourth multiplexing control line 514, and a fifth multiplexing control line 515.
  • the third multiplexing control line 513 that controls the multiplexing circuit to emit a third sub-pixel of a third color light may have an extension line 5130.
  • the extension line 5130 of the third multiplexing control line 513 may extend along the first direction X toward the direction of the first group of multiplexing data lines 61a.
  • the ninth multiplexing control line 519, the eighth multiplexing control line 518, the seventh multiplexing control line 517 and the sixth multiplexing control line 516 can be arranged in sequence along the direction close to the first signal access area B14.
  • the present embodiment does not limit the arrangement order of the four multiplexing control lines in the first group of multiplexing control lines 51a.
  • the ninth multiplexing control line 519, the eighth multiplexing control line 518, the seventh multiplexing control line 517 and the sixth multiplexing control line 516 can be arranged in sequence along the direction away from the first signal access area B14.
  • the sixth multiplexing control line 516, the ninth multiplexing control line 519, the eighth multiplexing control line 518 and the seventh multiplexing control line 517 can be arranged in sequence along the direction away from or close to the first signal access area B14.
  • the first multiplexing control line 511, the second multiplexing control line 512, the third multiplexing control line 513, the fourth multiplexing control line 514 and the fifth multiplexing control line 515 can be arranged in sequence along the direction away from the first signal access area B14.
  • the present embodiment does not limit the arrangement order of the five multiplexing control lines in the second group of multiplexing control lines 51b.
  • the first multiplexing control line 511, the second multiplexing control line 512, the third multiplexing control line 513, the fourth multiplexing control line 514 and the fifth multiplexing control line 515 can be arranged in sequence along the direction away from the first signal access area B14.
  • the fourth multiplexing control line 514, the fifth multiplexing control line 515, the first multiplexing control line 511, the second multiplexing control line 512 and the third multiplexing control line 513 can be arranged in sequence along the direction away from or close to the first signal access area B14.
  • the first group of multiplexing control lines 51a may overlap with the orthographic projection of the first group of multiplexing data lines 61a on the substrate, and may not overlap with the orthographic projection of the second group of multiplexing data lines 61b on the substrate.
  • the second group of multiplexing control lines 51b may overlap with the orthographic projection of the second group of multiplexing data lines 61b on the substrate, and may not overlap with the orthographic projection of the first group of multiplexing data lines 61a on the substrate.
  • the orthographic projection of the extended line 5130 of the third multiplexing control line 513 in the second group of multiplexing control lines 51b on the substrate overlaps with the orthographic projection of the first group of multiplexing data lines 61a on the substrate.
  • each multiplexed data line in the first group of multiplexed data lines 61a may overlap with the four multiplexed control lines in the first group of multiplexed control lines 51a and the extended line 5130 of the third multiplexed control line 513 in the orthographic projection on the substrate, that is, each multiplexed data line in the first group of multiplexed data lines 61a overlaps with the orthographic projection of the five multiplexed control lines in the substrate.
  • Each multiplexed data line in the second group of multiplexed data lines 61b overlaps with the orthographic projection of the five multiplexed control lines in the second group of multiplexed control lines 51b in the substrate.
  • each multiplexed data line overlaps with the orthographic projection of the same number (e.g., five) of multiplexed control lines in the substrate.
  • the extension line of the multiplexing control line to overlap with the multiplexing data line, it is possible to ensure that multiple multiplexing data lines overlap with the same number of multiplexing control lines, thereby improving the local display difference of the display area caused by the signal load difference caused by the inconsistent overlapping capacitance of multiple multiplexing data lines and multiple multiplexing control lines due to the inability to evenly divide the odd number of multiplexing control lines (for example, there is a difference in the display on the left and right sides of the display area), thereby improving the display effect.
  • the human eye Since the human eye is least sensitive to the blue light emitted by the third sub-pixel, by extending the third multiplexing control line that controls the data signal to the third sub-pixel, the local display difference of the blue light emitted by the third sub-pixel can be made indistinguishable to the naked eye, thereby improving the poor display caused by the data signal load difference.
  • FIG. 13 is another example diagram of the arrangement of multiplexed control lines and multiplexed data lines of at least one embodiment of the present disclosure.
  • FIG. 13 only takes a number of multiplexed data lines as an example for illustration. This embodiment does not limit the number of multiplexed data lines.
  • This example takes the multiplexing circuit using the 1:9 design shown in FIG. 4 as an example for illustration. This example does not limit the number of multiplexed control lines, for example, the number of multiplexed control lines can be other odd numbers.
  • the nine multiplexing control lines may include a first group of multiplexing control lines 51a and a second group of multiplexing control lines 51b.
  • the first group of multiplexing control lines 51a may include the following four multiplexing control lines: a ninth multiplexing control line 519, an eighth multiplexing control line 518, a seventh multiplexing control line 517, and a sixth multiplexing control line 516.
  • the second group of multiplexing control lines 51b may include the following five multiplexing control lines: a first multiplexing control line 511, a second multiplexing control line 512, a third multiplexing control line 513, a fourth multiplexing control line 514, and a fifth multiplexing control line 515.
  • Each of the multiplexing control lines has an extension line.
  • the extension line 5110 of the first multiplexing control line 511 can extend along the first direction X toward the first group of multiplexing data lines 61a;
  • the extension line 5120 of the second multiplexing control line 512 can extend along the first direction X toward the first group of multiplexing data lines 61a;
  • the extension line 5130 of the third multiplexing control line 513 can extend along the first direction X toward the first group of multiplexing data lines 61a;
  • the extension line 5140 of the fourth multiplexing control line 514 can extend along the first direction X toward the first group of multiplexing data lines 61a;
  • the extension line 5150 of the fifth multiplexing control line 515 can extend along the first direction X toward the first group of multiplexing data lines 61a;
  • the extension line 5160 of the sixth multiplexing control line 516 may extend in the direction of the second multiplexing data line 61b along the first direction X;
  • the extension line of the first group of multiplexing control lines 51a may be located on the side of the second group of multiplexing control lines close to the display area, and the extension line of the second group of multiplexing control lines 51b may be located on the side of the first group of multiplexing control lines away from the display area.
  • the ninth multiplexing control line 519, the eighth multiplexing control line 518, the seventh multiplexing control line 517, and the sixth multiplexing control line 516 can be arranged in sequence along the direction close to the first signal access area B14.
  • the first group of multiplexing control lines 51a can overlap with the orthographic projection of the first group of multiplexing data lines 61a on the substrate, and the extension line of each multiplexing control line in the first group of multiplexing control lines 51a can overlap with the orthographic projection of the second group of multiplexing data lines 61b on the substrate.
  • This embodiment does not limit the arrangement order of multiple multiplexing control lines in the first group of multiplexing control lines 51a.
  • the ninth multiplexing control line 519, the eighth multiplexing control line 518, the seventh multiplexing control line 517, and the sixth multiplexing control line 516 can be arranged in sequence along the direction away from the first signal access area B14.
  • the first multiplexing control line 511, the second multiplexing control line 512, the third multiplexing control line 513, the fourth multiplexing control line 514 and the fifth multiplexing control line 515 can be arranged in sequence along the direction away from the first signal access area B14.
  • the second group of multiplexing control lines 51b can overlap with the orthographic projection of the second group of multiplexing data lines 61b on the substrate, and the extension line of each multiplexing control line in the second group of multiplexing control lines 51b overlaps with the orthographic projection of the first group of multiplexing data lines 61a on the substrate.
  • This embodiment does not limit the arrangement order of multiple multiplexing control lines in the second group of multiplexing control lines 51b.
  • the first multiplexing control line 511, the second multiplexing control line 512, the third multiplexing control line 513, the fourth multiplexing control line 514 and the fifth multiplexing control line 515 can be arranged in sequence along the direction close to the first signal access area B14.
  • the first group of multiplexing control lines 51a may include five multiplexing control lines
  • the second group of multiplexing control lines 51b may include four multiplexing control lines. This embodiment does not limit the arrangement order of the multiple multiplexing control lines in each group of multiplexing control lines.
  • the lengths of the nine multiplexed control lines may be substantially the same to ensure the consistency of the routing capacitance of the multiplexed control lines.
  • Each multiplexed control line overlaps with the first group of multiplexed data lines 61a and the second group of multiplexed data lines 61b, which can ensure the consistency of the overlapping capacitance between different multiplexed control lines and multiplexed data lines, thereby improving the poor display caused by the inconsistent overlapping capacitance between the multiplexed control lines and the multiplexed data lines, and improving the display effect.
  • FIG. 14 is another example diagram of the arrangement of multiplexed control lines and multiplexed data lines of at least one embodiment of the present disclosure.
  • FIG. 14 only takes a number of multiplexed data lines as an example for illustration. This embodiment does not limit the number of multiplexed data lines.
  • This example takes the multiplexing circuit using the 1:9 design shown in FIG. 4 as an example for illustration. This example does not limit the number of multiplexed control lines, for example, the number of multiplexed control lines can be other odd numbers.
  • each of the nine multiplexing control lines can be connected to at least one multiplexing control contact pad 721 in the first group of multiplexing control contact pads 721a, and the second end can be connected to at least one multiplexing control contact pad 721 in the second group of multiplexing control contact pads 721b.
  • Each multiplexing control line can bypass the first signal access area B14 from the side of the first signal access area B14 close to the display area.
  • the first multiplexing control line 511, the second multiplexing control line 512, the third multiplexing control line 513, the fourth multiplexing control line 514, the fifth multiplexing control line 515, the sixth multiplexing control line 516, the seventh multiplexing control line 517, the eighth multiplexing control line 518 and the ninth multiplexing control line 519 can be arranged in sequence along the direction close to the first signal access area B14.
  • the present embodiment does not limit the arrangement order of the nine multiplexing control lines.
  • the first multiplexing control line 511, the second multiplexing control line 512, the third multiplexing control line 513, the fourth multiplexing control line 514, the fifth multiplexing control line 515, the sixth multiplexing control line 516, the seventh multiplexing control line 517, the eighth multiplexing control line 518 and the ninth multiplexing control line 519 can be arranged in sequence along the direction away from the first signal access area B14.
  • the first group of multiplexed data lines 61a may overlap with the nine multiplexed control lines
  • the second group of multiplexed data lines 61b may overlap with the nine multiplexed control lines.
  • the nine multiplexed control lines may be connected to the first group of multiplexed control connection lines (the first group of multiplexed control connection lines 52a shown in FIG5 ) and the second group of multiplexed control connection lines (the second group of multiplexed control connection lines 52b shown in FIG5 ) in the interval area between the first group of multiplexed data lines 61a and the second group of multiplexed data lines 61b, and connected to part of the control bending connection lines in the first group of control bending connection lines 35a and the second group of control bending connection lines 35b in the bending area B12 through the first group of multiplexed control connection lines and the second group of multiplexed control connection lines.
  • each multiplexed control line by setting each multiplexed control line to overlap with the first group of multiplexed data lines 61a and the second group of multiplexed data lines 61b, the consistency of the overlapping capacitance between different multiplexed control lines and multiplexed data lines can be ensured, thereby improving the poor display caused by the inconsistent overlapping capacitance between the multiplexed control lines and the multiplexed data lines, and improving the display effect.
  • FIG. 15 is another example diagram of the arrangement of multiplexed control lines and multiplexed data lines of at least one embodiment of the present disclosure.
  • FIG. 15 only takes a number of multiplexed data lines as an example for illustration. This embodiment does not limit the number of multiplexed data lines.
  • This example takes the multiplexing circuit using the 1:9 design shown in FIG. 4 as an example for illustration. This example does not limit the number of multiplexed control lines, for example, the number of multiplexed control lines can be other odd numbers.
  • the nine multiplexing control lines may not overlap with the orthographic projection of the multiple multiplexing data lines on the substrate.
  • the nine multiplexing control lines may include a first group of multiplexing control lines 51a and a second group of multiplexing control lines 51b.
  • the first group of multiplexing control lines 51a may include the following four multiplexing control lines: a ninth multiplexing control line 519, an eighth multiplexing control line 518, a seventh multiplexing control line 517, and a sixth multiplexing control line 516.
  • the second group of multiplexing control lines 51b may include the following five multiplexing control lines: a first multiplexing control line 511, a second multiplexing control line 512, a third multiplexing control line 513, a fourth multiplexing control line 514, and a fifth multiplexing control line 515.
  • the first group of multiplexing control lines may be located on a side of the first group of multiplexing data lines 61a away from the second group of multiplexing data lines 61b, and the second group of multiplexing control lines may be located on a side of the second group of multiplexing data lines 61b away from the first group of multiplexing data lines 61a.
  • the ninth multiplexing control line 519, the eighth multiplexing control line 518, the seventh multiplexing control line 517, and the sixth multiplexing control line 516 can be arranged in sequence along the direction close to the first signal access area B14.
  • This embodiment does not limit the arrangement order of the multiple multiplexing control lines in the first group of multiplexing control lines 51a.
  • the ninth multiplexing control line 519, the eighth multiplexing control line 518, the seventh multiplexing control line 517, and the sixth multiplexing control line 516 can be arranged in sequence along the direction away from the first signal access area B14.
  • the first multiplexing control line 511, the second multiplexing control line 512, the third multiplexing control line 513, the fourth multiplexing control line 514 and the fifth multiplexing control line 515 can be arranged in sequence along the direction away from the first signal access area B14.
  • This embodiment does not limit the arrangement order of the multiple multiplexing control lines in the second group of multiplexing control lines 51b.
  • the first multiplexing control line 511, the second multiplexing control line 512, the third multiplexing control line 513, the fourth multiplexing control line 514 and the fifth multiplexing control line 515 can be arranged in sequence along the direction close to the first signal access area B14.
  • the first group of multiplexing control lines 51a may include five multiplexing control lines
  • the second group of multiplexing control lines 51b may include four multiplexing control lines.
  • the first group of control bending connection lines 35a connected to the first group of multiplexing control lines 51a may be located on a side of the first group of data bending connection lines 36a close to the edge of the display panel.
  • the second group of control bending connection lines 35b connected to the second group of multiplexing control lines 51b may be located on a side of the second group of data bending connection lines 36b close to the edge of the display panel.
  • multiple multiplexed control lines are arranged not to overlap with multiple multiplexed data lines, thereby avoiding capacitance generated by overlapping multiple multiplexed control lines with multiple multiplexed data lines. This can avoid signal load differences caused by inconsistent overlapping capacitance and improve display effects.
  • This embodiment also provides a display panel, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing data lines, and N multiplexing control lines.
  • the substrate comprises a display area and a first frame area located on at least one side of the display area.
  • a plurality of sub-pixels and a plurality of data lines are located in the display area, and the plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels.
  • a plurality of multiplexing circuits, a plurality of multiplexing data lines, and N multiplexing control lines are located in the first frame area; wherein N is equal to 2n+1, and n is an integer greater than 0.
  • At least one of the plurality of multiplexing circuits is electrically connected to the N multiplexing control lines, a multiplexing data line, and a plurality of data lines, and is configured to provide the data signals transmitted by the multiplexing data lines to the plurality of data lines under the control of the N multiplexing control lines.
  • At least a portion of each of the multiplexed data lines extends along a first direction, and at least a portion of each of the N multiplexed control lines extends along a second direction.
  • Some line segments cross.
  • the second multiplexing extension segment or the fourth multiplexing extension segment of the multiplexing control line in the above embodiment may cross the multiplexing data line.
  • At least some segments of the multiplexing control line and at least some segments of the multiplexing data lines have the same crossing angle.
  • intersection angle of at least part of the multiplexing control line segments and at least part of the multiplexing data line segments is less than or equal to 90 degrees.
  • the clockwise intersection angle of at least part of the multiplexing control line segments and at least part of the multiplexing data line segments may be less than or equal to 90 degrees.
  • the value of N is 9.
  • FIG16 is a schematic diagram of a display device of at least one embodiment of the present disclosure.
  • the present embodiment provides a display device 91, including a display panel 910 of the aforementioned embodiment.
  • the display panel 910 may be an OLED display panel, such as an OLED display panel with an integrated touch structure.
  • the display device 91 may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator, or may be a product or component with touch and display functions.
  • the display device 91 may be a wearable display device, for example, it may be worn on a human body in some manner.
  • the display device 91 may be a smart watch, a smart bracelet, etc.
  • this embodiment is not limited to this.

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Abstract

一种显示面板包括：衬底、多个子像素、多条数据线、多个多路复用电路、多条复用数据线以及N条复用控制线。多个多路复用电路、多条复用数据线以及N条复用控制线位于显示区域至少一侧的第一边框区域。N等于2n+1，n为大于0的整数。至少一个多路复用电路与N条复用控制线、一条复用数据线和多条数据线电连接，被配置为在N条复用控制线的控制下，向多条数据线提供所述复用数据线传输的数据信号。每条复用数据线与至少n条复用控制线在衬底的正投影存在交叠，或者，多条复用数据线与N条复用控制线在衬底的正投影没有交叠。

Description

显示面板及显示装置
本申请要求于2023年4月25日提交中国专利局、申请号为202310456499.6、发明名称为“显示面板及显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及但不限于显示技术领域，尤指一种显示面板及显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(TFT，Thin Film Transistor)进行信号控制的显示装置已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示面板及显示装置。
一方面，本实施例提供一种显示面板，包括：衬底、多个子像素、多条数据线、多个多路复用电路、多条复用数据线以及N条复用控制线。衬底包括显示区域和位于所述显示区域至少一侧的第一边框区域。多个子像素和多条数据线位于所述显示区域，所述多条数据线与所述多个子像素连接，且被配置为给所述多个子像素提供数据信号。多个多路复用电路、多条复用数据线以及N条复用控制线位于所述第一边框区域，其中，N等于2n+1，n为大于0的整数。所述多个多路复用电路中的至少一个多路复用电路与所述N条复用控制线、一条复用数据线和多条数据线电连接，被配置为在所述N条复用控制线的控制下，向所述多条数据线提供所述复用数据线传输的数据信号。所述多条复用数据线中的每条复用数据线与至少n条复用控制线在所述衬底的正投影存在交叠，或者，所述多条复用数据线与所述N条复用控制线在所述衬底的正投影没有交叠。
在一些示例性实施方式中，所述N条复用控制线包括第一组复用控制线和第二组复用控制线，所述第一组复用控制线包括n条复用控制线，所述第二组复用控制线包括n+1条复用控制线。所述多条复用数据线包括第一组复用数据线和第二组复用数据线，所述第一组复用数据线中的每条复用数据线与所述第一组复用控制线中的n条复用控制线在所述衬底的正投影存在交叠，所述第二组复用数据线中的每条复用数据线与所述第二组复用控制线中的n+1条复用控制线存在交叠。
在一些示例性实施方式中，所述多个子像素包括：出射第一颜色光的第一子像素、出射第二颜色光的第二子像素和出射第三颜色光的第三子像素；所述N条复用控制线中的至少一条被配置为控制所述多路复用电路通过所述数据线向多个第一子像素提供数据信号，所述N条复用控制线中的至少一条被配置为控制所述多路复用电路通过所述数据线向多个第二子像素提供数据信号，所述N条复用控制线中的至少一条被配置为控制所述多路复用电路通过所述数据线向多个第三子像素提供数据信号。
在一些示例性实施方式中，n的取值为4。
在一些示例性实施方式中，所述N条复用控制线包括：第一复用控制线、第二复用控制线、第三复用控制线、第四复用控制线、第五复用控制线、第六复用控制线、第七复用控制线、第八复用控制线和第九复用控制线。所述多个子像素包括第一组子像素、第二组子像素和第三组子像素，所述第一组子像素包括第一组第一子像素、第一组第二子像素和第一组第三子像素，所述第二组子像素包括第二组第一子像素、第二组第二子像素和第二组第三子像素，所述第三组子像素包括第三组第一子像素、第三组第二子像素和第三组第三子像素。所述第一复用控制线被配置为控制所述多路复用电路给所述第一组第一子像素提供数据信号；所述第二复用控制线被配置为控制所述多路复用电路给所述第一组第二子像素提供数据信号；所述第三复用控制线被配置为控制所述多路复用电路给所述第一组第三子像素提供数据信号；所述第四复用控制线被配置为控制所述多路复用电路给所述第二组第一子像素提供数据信号；所述第五复用控制线被配置为控制所述多路复用电路给所述第二组第二子像素提供数据信号；所述第六复用控制线被配置为控制所述多路复用电路给所述第二组第三子像素提供数据信号；所述第七复用控制线被配置为控制所述多路复用电路给所述第三组第一子像素提供数据信号；所述第八复用控制线被配置为控制所述多路复用电路给所述第三组第二子像素提供数据信号；所述第九复用控制线被配置为控制所述多路复用电路给所述第三组第三子像素提供数据信号。所述第一组复用控制线包括：第四复用控制线、第七复用控制线、第八复用控制线和第九复用控制线；所述第二组复用控制线包括：第一复用控制线、第二复用控制线、第三复用控制线、第六复用控制线和第五复用控制线。
在一些示例性实施方式中，所述第一组复用控制线中，所述第四复用控制线、所述第七复用控制线、所述第八复用控制线和所述第九复用控制线沿着远离所述第二组复用数据线的方向依次排布。所述第二组复用控制线中，所述第一复用控制线、所述第二复用控制线、所述第三复用控制线、所述第六复用控制线和所述第五复用控制线沿着远离所述第一组复用数据线的方向依次排布。
在一些示例性实施方式中，所述N条复用控制线中，控制所述多路复用电路给所述第一子像素提供数据信号的复用控制线为第一类型复用控制线，控制所述多路复用电路给所述第二子像素提供数据信号的复用控制线为第二类型复用控制线，控制所述多路复用电路给所述第三子像素提供数据信号的复用控制线为第三类型复用控制线。所述第一组复用控制线包括：所述第一类型复用控制线以及至少一条第三类型复用控制线；所述第二组复用控制线包括：所述第三类型复用控制线以及其余的第三类型复用控制线。
在一些示例性实施方式中，所述N条复用控制线包括：第一复用控制线、第二复用控制线、第三复用控制线、第四复用控制线、第五复用控制线、第六复用控制线、第七复用控制线、第八复用控制线和第九复用控制线。所述多个子像素包括第一组子像素、第二组子像素和第三组子像素，所述第一组子像素包括第一组第一子像素、第一组第二子像素和第一组第三子像素，所述第二组子像素包括第二组第一子像素、第二组第二子像素和第二组第三子像素，所述第三组子像素包括第三组第一子像素、第三组第二子像素和第三组第三子像素。所述第一复用控制线被配置为控制所述多路复用电路给所述第一组第一子像素提供数据信号；所述第二复用控制线被配置为控制所述多路复用电路给所述第一组第二子像素提供数据信号；所述第三复用控制线被配置为控制所述多路复用电路给所述第一组第三子像素提供数据信号；所述第四复用控制线被配置为控制所述多路复用电路给所述第二组第一子像素提供数据信号；所述第五复用控制线被配置为控制所述多路复用电路给所述第二组第二子像素提供数据信号；所述第六复用控制线被配置为控制所述多路复用电路 给所述第二组第三子像素提供数据信号；所述第七复用控制线被配置为控制所述多路复用电路给所述第三组第一子像素提供数据信号；所述第八复用控制线被配置为控制所述多路复用电路给所述第三组第二子像素提供数据信号；所述第九复用控制线被配置为控制所述多路复用电路给所述第三组第三子像素提供数据信号。所述第一组复用控制线包括：第一复用控制线、第四复用控制线、第七复用控制线、以及第三复用控制线；所述第二组复用控制线包括：第二复用控制线、第五复用控制线、第八复用控制线、第六复用控制线和第九复用控制线。
在一些示例性实施方式中，所述多条复用数据线包括第一组复用数据线和第二组复用数据线，所述第一组复用数据线的每条复用数据线所交叠的复用控制线的数目与所述第二组复用数据线的每条复用数据线所交叠的复用控制线的数目相同。
在一些示例性实施方式中，所述N条复用控制线包括第一组复用控制线和第二组复用控制线，所述第一组复用控制线包括n条复用控制线，所述第二组复用控制线包括n+1条复用控制线。所述第一组复用数据线中的每条复用数据线与所述第一组复用控制线中的n条复用控制线和所述第二组复用控制线中的一条复用控制线的延长线在所述衬底的正投影存在交叠，所述第二组复用数据线中的每条复用数据线与所述第二组复用控制线中的n+1条复用控制线在所述衬底的正投影存在交叠。
在一些示例性实施方式中，所述多个子像素包括：出射第一颜色光的第一子像素、出射第二颜色光的第二子像素和出射第三颜色光的第三子像素。所述第二组复用控制线中具有延长线的复用控制线被配置为控制所述多路复用电路给所述第三子像素提供数据信号。
在一些示例性实施方式中，所述N条复用控制线包括：第一复用控制线、第二复用控制线、第三复用控制线、第四复用控制线、第五复用控制线、第六复用控制线、第七复用控制线、第八复用控制线和第九复用控制线。所述多个子像素包括第一组子像素、第二组子像素和第三组子像素，所述第一组子像素包括第一组第一子像素、第一组第二子像素和第一组第三子像素，所述第二组子像素包括第二组第一子像素、第二组第二子像素和第二组第三子像素，所述第三组子像素包括第三组第一子像素、第三组第二子像素和第三组第三子像素。所述第一复用控制线被配置为控制所述多路复用电路给所述第一组第一子像素提供数据信号；所述第二复用控制线被配置为控制所述多路复用电路给所述第一组第二子像素提供数据信号；所述第三复用控制线被配置为控制所述多路复用电路给所述第一组第三子像素提供数据信号；所述第四复用控制线被配置为控制所述多路复用电路给所述第二组第一子像素提供数据信号；所述第五复用控制线被配置为控制所述多路复用电路给所述第二组第二子像素提供数据信号；所述第六复用控制线被配置为控制所述多路复用电路给所述第二组第三子像素提供数据信号；所述第七复用控制线被配置为控制所述多路复用电路给所述第三组第一子像素提供数据信号；所述第八复用控制线被配置为控制所述多路复用电路给所述第三组第二子像素提供数据信号；所述第九复用控制线被配置为控制所述多路复用电路给所述第三组第三子像素提供数据信号。所述第一组复用控制线包括：第六复用控制线、第七复用控制线、第八复用控制线和第九复用控制线；所述第二组复用控制线包括：第一复用控制线、第二复用控制线、第三复用控制线、第四复用控制线和第五复用控制线；其中，所述第三复用控制线具有延长线。
在一些示例性实施方式中，所述第一组复用数据线和所述第二组复用数据线的每条复用数据线与所述N条复用控制线在所述衬底的正投影存在交叠。
在一些示例性实施方式中，所述N条复用控制线均具有延长线；所述N条复用控制线包括第一组复用控制线和第二组复用控制线，所述第一组复用控制线包括n条复用控制线，所述第二组复用控制线包括n+1条复用控制线。所述第一组复用数据线中的每条复 用数据线与所述第一组复用控制线中的n条复用控制线和所述第二组复用控制线中的n+1条复用控制线的延长线在所述衬底的正投影存在交叠，所述第二组复用数据线中的每条复用数据线与所述第二组复用控制线中的n+1条复用控制线和所述第一组复用控制线中的n条复用控制线的延长线在所述衬底的正投影存在交叠。
在一些示例性实施方式中，所述第一颜色光为红光，所述第二颜色光为绿光，所述第三颜色光为蓝光。
在一些示例性实施方式中，所述第一边框区域至少包括：第一信号接入区域和第二信号接入区域，所述第二信号接入区域位于所述第一信号接入区域远离所述显示区域的一侧；所述第一信号接入区域设置有第一组第一接触垫；所述第二信号接入区域设置有多个复用控制接触垫；所述多条复用数据线与所述第一信号接入区域的第一组第一接触垫连接，所述N条复用控制线与所述第二信号接入区域的多个复用控制接触垫连接。
在一些示例性实施方式中，所述第一信号接入区域还设置有第二组第一接触垫，所述第二组第一接触垫位于所述第一组第一接触垫远离所述显示区域的一侧；所述第二信号接入区域还设置有一组中间接触垫；所述第一信号接入区域的第二组第一接触垫通过多条引脚连接线与所述第二信号接入区域的该组中间接触垫连接。所述第二信号接入区域的多个复用控制接触垫包括第一组复用控制接触垫和第二组复用控制接触垫，所述第一组复用控制接触垫和所述第二组复用控制接触垫沿第一方向位于该组中间接触垫的相对两侧。
在一些示例性实施方式中，所述第一组复用控制线与所述第一组复用控制接触垫连接，所述第二组复用控制线与所述第二组复用控制接触垫连接。
在一些示例性实施方式中，所述N条复用控制线中每条复用控制线的第一端与所述第一组复用控制接触垫连接，每条复用控制线的第二端与所述第二组复用控制接触垫连接。
在一些示例性实施方式中，所述多条复用数据线与所述N条复用控制线在所述衬底的正投影没有交叠，所述N条复用控制线包括第一组复用控制线和第二组复用控制线，所述第一组复用控制线包括n条复用控制线，所述第二组复用控制线包括n+1条复用控制线；所述第一组复用控制线和所述第二组复用控制线设置在所述多条复用数据线的相对两侧。另一方面，本公开实施例提供一种显示装置，包括如上所述的显示面板。
另一方面，本实施例提供一种显示面板，包括：衬底、多个子像素、多条数据线、多个多路复用电路、多条复用数据线以及N条复用控制线。衬底包括显示区域和位于所述显示区域至少一侧的第一边框区域。多个子像素和多条数据线位于所述显示区域，所述多条数据线与所述多个子像素连接，且被配置为给所述多个子像素提供数据信号。多个多路复用电路、多条复用数据线以及N条复用控制线位于所述第一边框区域；其中，N等于2n+1，n为大于0的整数。所述多个多路复用电路中的至少一个多路复用电路与所述N条复用控制线、一条复用数据线和多条数据线电连接，被配置为在所述N条复用控制线的控制下，向所述多条数据线提供所述复用数据线传输的数据信号。所述多条复用数据线中的每条复用数据线的至少部分线段沿第一方向延伸，所述N条复用控制线中的每条复用控制线的至少部分线段沿第二方向延伸；所述复用数据线的至少部分线段和所述复用控制线的至少部分线段交叉。
在一些示例性实施方式中，所述复用控制线的至少部分线段与多条复用数据线的至少部分线段的交叉角度相同。
在一些示例性实施方式中，所述复用控制线的至少部分线段与所述复用数据线的至少部分线段的交叉角度小于或等于90度。
在一些示例性实施方式中，N的取值为9。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示面板的示意图；
图2为本公开至少一实施例的显示面板的显示区域的局部剖面示意图；
图3为本公开至少一实施例的第一边框区域的局部平面示意图；
图4为本公开至少一实施例的多路复用电路的等效电路图；
图5为本公开至少一实施例的复用控制线和复用数据线的排布示例图；
图6为图3中区域S1的局部放大示意图；
图7为图3中区域S2的局部放大示意图；
图8A为图7中形成第一栅金属层后的显示面板的示意图；
图8B为图7中形成第二栅金属层后的显示面板的示意图；
图8C为图7中形成第一源漏金属层后的显示面板的示意图；
图9为图3中区域S3的局部放大示意图；
图10为图3中区域S4的局部放大示意图；
图11为本公开至少一实施例的复用控制线和复用数据线的另一排布示例图；
图12为本公开至少一实施例的复用控制线和复用数据线的另一排布示例图；
图13为本公开至少一实施例的复用控制线和复用数据线的另一排布示例图；
图14为本公开至少一实施例的复用控制线和复用数据线的另一排布示例图；
图15为本公开至少一实施例的复用控制线和复用数据线的另一排布示例图；
图16为本公开至少一实施例的显示装置的示意图。
详述
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。
在本说明书中，A沿着B方向延伸是指，A可以包括主体部分和与主体部分连接的次要部分，主体部分是线、线段或条形状体，主体部分沿着B方向伸展，且主体部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。本说明书中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
本说明书中所说的“A和B为同层结构”是指，A和B通过同一次构图工艺同时形成。“相同层”不总是意味着层的厚度或层的高度在截面图中是相同的。“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
随着显示技术的发展，提高屏占比减少边框尺寸是一个重要的改进方向。目前的显示面板通常设置多路复用电路(MUX)来减少数据线的数量，从而减少边框区域的数据扇出线所在的空间，以减少边框尺寸。然而，多路复用电路所连接的走线在边框区域的排布存在交叠的情况，走线交叠所产生的电容会影响走线传输的信号产生负载差异(例如，数据信号的负载差异、复用控制信号的负载差异)，从而造成显示面板的显示不良。以显示面板应用于手表等可穿戴产品为例，多路复用电路对手表等可穿戴产品的画质非常重要，特别是在进行低灰阶显示时，由于多路复用电路所连接的走线交叠造成信号负载差异，会导致亮暗条纹或分屏等显示不良。
本实施例提供一种显示面板及显示装置，可以改善多路复用电路所连接的走线交叠造 成的信号负载差异而导致的显示不良情况。
本实施例提供一种显示面板，包括：衬底、多个子像素、多条数据线、多个多路复用电路、多条复用数据线以及N条复用控制线。衬底包括显示区域和位于显示区域至少一侧的第一边框区域。多个子像素和多条数据线位于显示区域，多条数据线与多个子像素连接，被配置为给多个子像素提供数据信号。多个多路复用电路、多条复用数据线以及N条复用控制线位于第一边框区域。N等于2n+1，n为大于0的整数。多个多路复用电路中的至少一个多路复用电路与N条复用控制线、一条复用数据线和多条数据线电连接，被配置为在N条复用控制线的控制下，向多条数据线提供所述复用数据线传输的数据信号。多条复用数据线中的每条复用数据线与至少n条复用控制线在衬底的正投影存在交叠，或者，多条复用数据线与N条复用控制线在衬底的正投影没有交叠。在本示例中，复用控制线的数目可以为奇数。例如，n的取值可以为4，N的取值可以为9。
本实施例提供的显示面板，通过设置多条复用数据线中的每条复用数据线与至少n条复用控制线在衬底的正投影交叠，或者，多条复用数据线与N条复用控制线在衬底的正投影没有交叠，可以避免或大大减轻多路复用电路所连接的复用数据线和复用控制线由于走线交叠产生的信号负载差异，从而可以改善显示面板的显示不良情况。
下面通过多个示例对本实施例的方案进行举例说明。
图1为本公开至少一实施例的显示面板的示意图。在一些示例中，如图1所示，显示面板可以包括：显示区域AA、位于显示区域AA一侧的第一边框区域B1、以及位于显示区域AA其余侧的第二边框区域B2。第一边框区域B1可以与第二边框区域B2连通。例如，第一边框区域B1可以为显示面板的下边框，第二边框区域B2可以包括显示面板除下边框以外的其余边框区域。
在一些示例中，如图1所示，显示区域AA可以是平坦的区域，包括组成像素阵列的多个子像素PX，多个子像素PX可以被配置为显示动态图片或静止图像。显示区域AA可以称为有效区域(Active Area)。在一些示例中，显示区域AA可以为圆形或椭圆形。然而，本实施例对此并不限定。例如，显示区域可以为矩形等其它形状。在一些示例中，显示面板可以为柔性面板，因而显示面板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在一些示例中，如图1所示，显示区域AA可以包括：设置在衬底上的显示结构层，或者可以包括依次设置在衬底上的显示结构层和触控结构层。例如，显示面板可以集成触控结构形成触控结构在薄膜封装(Touch on Thin Film Encapsulation，简称Touch on TFE)上的结构。Touch on TFE结构主要包括柔性多层覆盖表面式(FMLOC，Flexible Multi-Layer On Cell)结构和柔性单层覆盖表面式(FSLOC，Flexible Single-Layer On Cell)结构。FMLOC结构是基于互容检测的工作原理，一般采用两层金属形成驱动(Tx)电极和感应(Rx)电极，驱动芯片(IC)通过检测驱动电极和感应电极间的互容来实现触控动作。FSLOC结构是基于自容(或电压)检测的工作原理，一般采用单层金属形成触控电极，集成电路通过检测触控电极自容(或电压)来实现触控动作。
在一些示例中，显示结构层可以包括多个子像素PX、多条栅线GL和多条数据线DL。多条栅线GL可以沿第一方向X延伸，多条数据线DL可以沿第二方向Y延伸。多条栅线GL和多条数据线DL在衬底上的正投影可以交叉形成多个子像素区域。一个子像素PX可以设置在一个子像素区域内。多条数据线DL可以与多个子像素PX电连接，多条数据线DL可以被配置为向多个子像素PX提供数据信号。多条栅线GL可以与多个子像素PX电连接，多条栅线GL可以被配置为向多个子像素PX提供栅极驱动信号。例如，栅极驱动信号可以包括扫描信号，或者可以包括扫描信号和发光控制信号，或者可以包括扫描信 号、复位控制信号和发光控制信号。
在一些示例中，如图1所示，第一方向X可以是显示区域AA中栅线GL的延伸方向(例如，行方向)，第二方向Y可以是显示区域AA中数据线DL的延伸方向(例如，列方向)。第一方向X和第二方向Y可以相互交叉，例如可以相互垂直。
在一些示例中，显示区域AA的一个像素单元可以包括三个子像素，三个子像素可以分别为出射第一颜色光(例如，红光)的第一子像素、出射第二颜色光(例如，绿光)的第二子像素和出射第三颜色光(例如，蓝光)的第三子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素可以分别为出射红光的子像素、出射绿光的子像素、出射蓝光的子像素和出射白光的子像素。又如，一个像素单元可以包括四个子像素，四个子像素可以包括一个出射红光的子像素、一个出射蓝光的子像素、以及两个出射绿光的子像素。
在一些示例中，子像素的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
在一些示例中，一个子像素可以包括：像素电路以及与像素电路电连接的发光元件。像素电路可以包括多个晶体管和至少一个电容。例如，像素电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。其中，上述电路结构中的T指的是薄膜晶体管，C指的是电容，T前面的数字代表电路中薄膜晶体管的数量，C前面的数字代表电路中电容的数量。在一些示例中，像素电路中的多个晶体管可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在另一些示例中，像素电路中的多个晶体管可以包括P型晶体管和N型晶体管。
在一些示例中，像素电路中的多个晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示面板上，即LTPS+Oxide(简称LTPO)显示面板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例中，发光元件可以是发光二极管(LED，Light Emitting Diode)、有机发光二极管(OLED，Organic Light Emitting Diode)、量子点发光二极管(QLED，Quantum Dot Light Emitting Diode)、微LED(包括：mini-LED或micro-LED)等中的任一者。例如，发光元件可以为OLED，发光元件在其对应的像素电路的驱动下可以发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。在一些示例中，发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
图2为本公开至少一实施例的显示面板的显示区域的局部剖面示意图。图2中以显示区域的一个子像素的结构为例进行示意。在本示例中，以像素电路中的多个晶体管的类型相同为例进行说明，例如，像素电路中的多个晶体管均可以采用低温多晶硅薄膜晶体管或均采用氧化物薄膜晶体管。
在一些示例中，如图2所示，在垂直于显示面板的方向上，显示面板的显示区域可以 包括：衬底10、以及依次设置在衬底10上的电路结构层12、发光结构层13、封装结构层14以及触控结构层15。其中，显示结构层可以至少包括电路结构层12和发光结构层13。电路结构层12可以至少包括：多个子像素的像素电路，每个子像素的像素电路可以包括多个晶体管和至少一个电容。发光结构层13可以至少包括：多个子像素的发光元件。
在一些示例中，图2中以每个子像素包括的一个薄膜晶体管21和一个电容22为例进行示意。在一些示例中，显示区域的电路结构层12可以包括：设置在衬底10上的半导体层、第一栅金属层、第二栅金属层以及第一源漏金属层。半导体层和第一栅金属层之间可以设置有第一栅绝缘层101，第一栅金属层和第二栅金属层之间可以设置有第二栅绝缘层102，第二栅金属层和第一源漏金属层之间可以设置有层间绝缘层103，第一源漏金属层远离衬底10一侧可以设置有钝化层104和第一平坦层105。其中，第一栅绝缘层101、第二栅绝缘层102、层间绝缘层103和钝化层104可以为无机绝缘层，第一平坦层105可以为有机绝缘层。然而，本实施例对此并不限定。在另一些示例中，半导体层靠近衬底一侧还可以设置缓冲层，缓冲层可以防止衬底中的有害物质侵入显示面板的内部，还可以增加显示面板中的膜层在衬底上的附着力。另一些示例中，第一源漏金属层远离衬底一侧可以省略钝化层，仅设置第一平坦层。
在一些示例中，如图2所示，显示区域的半导体层可以至少包括：薄膜晶体管21的有源层210。薄膜晶体管21的有源层210可以包括：第一区2101、第二区2102以及位于第一区2101和第二区2102之间的沟道区2100。第一栅金属层可以至少包括：薄膜晶体管21的栅极213、以及电容22的第一极板221。薄膜晶体管21的栅极213在衬底10的正投影可以覆盖有源层210的沟道区2100在衬底10的正投影。第二栅金属层可以至少包括：电容22的第二极板222。电容22的第二极板222和第一极板221在衬底10的正投影可以至少部分交叠，例如，两者可以重合。第一源漏金属层可以至少包括：薄膜晶体管21的源极211和漏极212。层间绝缘层103在显示区域可以开设有多个过孔(例如，包括第一像素过孔和第二像素过孔)，第一像素过孔内的层间绝缘层103、第二栅绝缘层102和第一栅绝缘层101可以被去掉，暴露出有源层210的第一区2101的至少部分表面；第二像素过孔内的层间绝缘层103、第二栅绝缘层102和第一栅绝缘层101可以被去掉，暴露出有源层210的第二区2102的至少部分表面。薄膜晶体管21的源极211可以通过第一像素过孔与有源层210的第一区2101电连接，漏极212可以通过第二像素过孔与有源层210的第二区2102电连接。在一些示例中，显示区域的栅线例如可以位于第一栅金属层，显示区域的数据线和高电位电源线例如可以位于第一源漏金属层。
在一些示例中，如图2所示，发光结构层13可以包括：像素定义层134和多个发光元件。例如，每个发光元件可以包括：叠设的第一电极131、有机发光层132和第二电极133。发光元件的第一电极131可以为阳极，第一电极131可以设置在第一平坦层105上，并通过第一平坦层105和钝化层104开设的像素过孔，与薄膜晶体管的第二极212电连接。像素定义层134设置在第一电极131和第一平坦层105上，像素定义层134可以开设有多个像素开口，一个像素开口可以暴露出对应的一个第一电极131的至少部分表面。有机发光层132的至少部分可以设置在一个像素开口内，并与对应的第一电极131连接。第二电极133可以设置在有机发光层132上，并与有机发光层132连接。有机发光层132在第一电极131和第二电极133的驱动下可以出射相应颜色的光线。
在一些示例中，发光元件的有机发光层132可以包括发光层(EML，Emitting Layer)，以及包括空穴注入层(HIL，Hole Injection Layer)、空穴传输层(HTL，Hole Transport Layer)、空穴阻挡层(HBL，Hole Block Layer)、电子阻挡层(EBL，Electron Block Layer)、电子注入层(EIL，Electron Injection Layer)、电子传输层(ETL，Electron Transport Layer) 中的一个或多个膜层。在第一电极131和第二电极133的电压驱动下，可以利用有机材料的发光特性根据需要的灰度发光。
在一些示例中，出射不同颜色光的发光元件的发光层可以不同。例如，红色发光元件包括红色发光层，绿色发光元件包括绿色发光层，蓝色发光元件包括蓝色发光层。为了降低工艺难度和提升良率，位于发光层一侧的空穴注入层和空穴传输层可以采用共通层，位于发光层另一侧的电子注入层和电子传输层可以采用共通层。在一些示例中，空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以通过一次工艺(一次蒸镀工艺或一次喷墨打印工艺)制作，并通过形成的膜层表面段差或者通过表面处理等手段实现隔离。例如，相邻子像素对应的空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以是隔离的。在一些示例中，有机发光层可以通过采用精细金属掩模版(FMM，Fine Metal Mask)或者开放式掩膜版(Open Mask)蒸镀制备形成，或者采用喷墨工艺制备形成。
在一些示例中，如图2所示，封装结构层14可以包括叠设的第一封装层141、第二封装层142和第三封装层143。其中，第一封装层141和第三封装层143可以采用无机材料，第二封装层142可以采用有机材料，第二封装层142可以设置在第一封装层141和第三封装层143之间，以保证外界水汽无法进入发光元件。然而，本实施例对此并不限定。例如，封装结构层可以采用无机/有机/无机/有机/无机的五层叠设结构。
在一些示例中，触控结构层15可以包括多个触控单元。至少一个触控单元可以包括至少一个触控电极。至少一个触控电极在衬底的正投影可以包含多个子像素在衬底的正投影。当触控单元包括多个触控电极，多个触控电极可以间隔设置，且相邻的触控电极之间可以通过连接部彼此连接。触控电极和连接部可以为同层结构。在一些示例中，触控电极可以具有菱形状，例如可以是正菱形，或者是横长的菱形，或者是纵长的菱形。然而，本实施例对此并不限定。在一些示例中，触控电极可以具有三角形、正方形、梯形、平行四边形、五边形、六边形和其它多边形中的任意一种或多种。
在一些示例中，如图1所示，第一边框区域B1可以包括：沿着远离显示区域AA的方向依次设置的第一扇出区域B11、弯折区域B12、第二扇出区域B13、第一信号接入区域B14以及第二信号接入区域B15。第一扇出区域B11可以与第二边框区域B2连通，并位于显示区域AA的一侧。弯折区域B12可以与第一扇出区域B11和第二扇出区域B13连通，并位于第一扇出区域B11远离显示区域AA的一侧。第二扇出区域B13可以位于弯折区域B12远离显示区域AA的一侧。第一信号接入区域B14可以位于第二扇出区域B13远离显示区域AA的一侧。第二信号接入区域B15可以位于第一信号接入区域B14远离显示区域AA的一侧。
图3为本公开至少一实施例的第一边框区域的局部平面示意图。图3中对第一边框区域的面板检测线、复用数据引出线、数据弯折连接线、触控弯折连接线、检测弯折连接线、控制弯折连接线、复用数据线以及面板检测引出线进行了整体示意，数据扇出线、控制引出线、控制连接线以及控制信号线仅以若干条走线为例进行示意，本示例对于第一边框区域的多种走线的数目并不限定。
在一些示例中，如图3所示，第一扇出区域B11可以连接到显示区域AA和第二边框区域。第一扇出区域B11可以设置有第一电源线311、第二电源线321a和321b、多条显示引出线、多条面板检测线、多个多路复用电路40、多个静电释放(ESD)电路41、以及栅极驱动电路的多个移位寄存器单元42。
在一些示例中，如图3所示，第一电源线311可以具有沿第二方向Y延伸的第一主 体部和沿着显示区域AA边缘延伸的第一延伸部，第一电源线311的第一主体部可以大致位于第一扇出区域B11在第一方向X的中线位置，第一扇出区域B11在第一方向X的中线可以平行于第二方向Y。第一电源线311的第一主体部可以向弯折区域B12一侧延伸。第一电源线311的第一延伸部可以与显示区域AA的多个子像素的像素电路电连接的多条高电位电源线电连接。
在一些示例中，如图3所示，第二电源线321a和321b可以在第一方向X上可以位于第一电源线311的相对两侧。第二电源线321a可以从左侧沿着显示面板的边缘向第二边框区域延伸，第二电源线321b可以从右侧沿着显示面板的边缘向第二边框区域延伸。第二电源线321a和321b可以在第二边框区域连接，以便给显示区域AA的多个子像素提供低电位电源信号。在一些示例中，第一电源线311、第二电源线321a和321b可以为同层结构，例如可以位于第一源漏金属层。
在一些示例中，栅极驱动电路可以包括多个级联的移位寄存器单元42，每个移位寄存器单元42可以连接显示区域AA的至少一条栅线，配置为显示区域AA的至少一条栅线提供栅极驱动信号。多路复用电路40可以配置为使得一个信号源给多个数据线提供数据信号。一部分多路复用电路40可以设置在第一电源线311的第一主体部在第一方向X的相对两侧并沿第一方向X阵列排布，另一部分多路复用电路40可以与栅极驱动电路的移位寄存器单元42间隔设置。栅极驱动电路的移位寄存器单元42可以从第一扇出区域B11沿着显示区域AA的边缘排布。静电释放电路41可以被配置为消除所连接的信号线上的静电。多个静电释放电路41可以排布在第一电源线311的第一主体部在第一方向X的相对两侧，并位于多路复用电路40靠近第一电源线311的第一主体部的一侧。
在一些示例中，如图3所示，第一扇出区域B11的多条显示引出线可以至少包括：多条数据扇出线63、多条控制引出线(例如包括第一组控制引出线64a和第二组控制引出线64b)、以及多条复用数据引出线(例如包括第一组复用数据引出线62a和第二组复用数据引出线62b)。多条数据扇出线63可以与多个多路复用电路40和显示区域AA的多条数据线电连接。一条数据扇出线63的一端可以与显示区域AA的至少一条数据线电连接，另一端可以与一个多路复用电路40电连接。例如，多条数据扇出线63和多条数据线可以一一对应电连接。一个多路复用电路40可以通过多条数据扇出线63与多条数据线连接，以便给多条数据线提供数据信号。例如，一个多路复用电路40可以通过多条数据扇出线63给九条数据线提供数据信号。在一些示例中，相邻数据扇出线63可以位于不同金属层，例如多条数据扇出线63可以间隔设置在第一栅金属层和第二栅金属层。
在一些示例中，如图3所示，多条复用数据引出线可以与多个多路复用电路40电连接。一条复用数据引出线可以被配置为给一个多路复用电路40传输数据信号，以便多路复用电路40将数据信号提供给与其连接的多条数据线。多条复用数据引出线可以例如可以包括第一组复用数据引出线62a和第二组复用数据引出线62b。每组复用数据引出线可以包括多条复用数据引出线，两组复用数据引出线的数目可以相同或不同。第一组复用数据引出线62a和第二组复用数据引出线62b可以位于第一电源线311的第一主体部的相对两侧。例如，第一组复用数据引出线62a可以向左侧延伸，并与位于第一电源线311的第一主体部左侧的多个多路复用电路40连接；第二组复用数据引出线62b可以向右侧延伸，并与位于第一电源线311的第一主体部右侧的多个多路复用电路40连接。多条复用数据引出线可以位于第二电源线331a和331b靠近衬底的一侧。多条复用数据引出线可以为同层结构，例如，可以均位于第二栅金属层。
在一些示例中，如图3所示，多条控制引出线例如可以包括第一组控制引出线64a和第二组控制引出线64b。每组控制引出线可以包括多条控制引出线。两组控制引出线的 数目可以相同或不同。第一组控制引出线64a和第二组控制引出线64b可以位于第一电源线311的第一主体部的相对两侧。第一组控制引出线64a可以位于第一组复用数据引出线62a靠近第一电源线311的一侧，第二组控制引出线64b可以位于第二组复用数据引出线62b靠近第一电源线311的一侧。多条控制引出线可以与静电释放电路41连接，以避免静电累积。
在一些示例中，多条控制引出线可以包括：多条复用控制引出线(例如包括图6所示的第一组复用控制引出线53a和第二组复用控制引出线53b)、以及多条驱动控制引出线(例如包括图6所示的第一组驱动控制引出线83a和第二组驱动控制引出线83b)。多条复用控制引出线可以与多个多路复用电路40连接，可以配置为给多个多路复用电路40提供复用控制信号。多条驱动控制引出线可以与栅极驱动电路42连接，例如可以给栅极驱动电路42提供驱动控制信号(比如包括起始信号、时钟信号、电源信号等)。
在一些示例中，多条面板检测线可以被配置为进行显示区域AA的裂纹检测。多条面板检测线可以包括第一组面板检测线331a和第二组面板检测线331b。第一组面板检测线331a可以与第二电源线321a在衬底的正投影部分交叠，第二组面板检测线331b可以与第二电源线321b在衬底的正投影部分交叠。例如，多条面板检测线可以为同层结构，比如均位于第一栅金属层。
在一些示例中，如图3所示，弯折区域B12可以被配置为使第二扇出区域B13、第一信号接入区域B14和第二信号接入区域B15弯折到显示区域AA的背面。弯折区域B12可以设置有多条弯折连接线，以便连接第一扇出区域B11和第二扇出区域B13内传输相同信号的走线。弯折区域B12的多条弯折连接线可以为同层结构，例如可以均位于第一源漏金属层。
在一些示例中，如图3所示，多条弯折连接线可以包括：第一电源弯折连接线31、第二电源弯折连接线32a和32b、第一组检测弯折连接线33a和第二组检测弯折连接线33b、第一组触控弯折连接线34a和第二组触控弯折连接线34b、第一组数据弯折连接线36a和第二组数据弯折连接线36b、第一组控制弯折连接线35a和第二组控制弯折连接线35b。第二电源弯折连接线32a、第一组检测弯折连接线33a、第一组触控弯折连接线34a、第一组数据弯折连接线36a、第一组控制弯折连接线35a、第一电源弯折连接线31、第二组控制弯折连接线35b、第二组数据弯折连接线36b、第二组触控弯折连接线34b、第二组检测弯折连接线33b和第二电源弯折连接线32b可以沿第一方向X依次排布。
在一些示例中，如图3所示，第二扇出区域B13可以至少设置有第一电源引出线312、第二电源引出线322a和322b、多条面板检测引出线(包括如图3所示的第一组面板检测引出线332a和第二组面板检测引出线332b)、多条复用数据线(包括如图3所示的第一组复用数据线61a和第二组复用数据线61b)、多条控制连接线(包括如图3所示的第一组控制连接线65a和第二组控制连接线65b)以及多条控制信号线(包括如图3所示的第一组控制信号线66a和第二组控制信号线66b)。
在一些示例中，如图3所示，第一电源引出线312可以通过弯折区域B12的第一电源连接线31与第一扇出区域B11的第一电源线311连接。例如，第一电源引出线312、第一电源连接线31和第一电源线311可以为相互连接的一体结构，例如均位于第一源漏金属层。第一电源引出线312可以包括沿第二方向Y延伸的第二主体部、以及与第二主体部连接的第二延伸部和第三延伸部。第二延伸部和第三延伸部可以沿第一方向X的相对两侧延伸，以绕过第一信号接入区B14，向第二信号接入区B15延伸。例如，第一电源引出线312的第二延伸部可以从左侧绕过第一信号接入区B14，第一电源引出线312的第二延伸部可以从右侧绕过第一信号接入区B14。
在一些示例中，如图3所示，第二电源引出线322a可以通过弯折区域B12的第二电源连接线32a与第二电源线321a连接。第二电源引出线322b可以位于第一电源引出线312的第二延伸部靠近显示面板的边缘的一侧。例如，第二电源引出线322a、第二电源连接线32a和第二电源线321a可以为相互连接的一体结构，例如均位于第一源漏金属层。第二电源引出线322b可以通过弯折区域B12的第二电源连接线32b与第二电源线321b连接。第二电源引出线322b可以位于第一电源引出线312的第三延伸部靠近显示面板的边缘的一侧。例如，第二电源引出线322b、第二电源连接线32b和第二电源线321b可以为相互连接的一体结构，例如均位于第一源漏金属层。
在一些示例中，如图3所示，第二扇出区域B13的多条面板检测引出线可以包括第一组面板检测引出线332a和第二组面板检测引出线332b。第一组面板检测引出线332a的多条面板检测引出线可以通过弯折区域B12的第一组检测弯折连接线33a的多条检测弯折连接线与第一扇出区域B11内的第一组面板检测线331a的多条面板检测线连接。第二组面板检测引出线332b内的多条面板检测引出线可以通过弯折区域B12的第二组检测弯折连接线33b的多条检测弯折连接线与第一扇出区域B11内的第一组面板检测线331b的多条面板检测线连接。第一组面板检测引出线332a可以位于第二电源引出线322a远离显示面板边缘的一侧。第二组面板检测引出线332b可以位于第二电源引出线322b远离显示面板边缘的一侧。在一些示例中，多条面板检测引出线可以为同层结构，例如可以均位于第二栅金属层。
在一些示例中，如图3所示，第二扇出区域B13的多条复用数据线可以大致沿第二方向Y向第一信号接入区B14延伸。多条复用数据线可以包括第一组复用数据线61a和第二组复用数据线61b。第一组复用数据线61a的多条复用数据线可以通过弯折区域B12的第一组数据弯折连接线36a的多条数据弯折连接线与第一扇出区域B11内的第一组复用数据引出线62a的多条复用数据引出线连接。第二组复用数据线61b的多条复用数据线可以通过弯折区域B12的第二组数据弯折连接线36b的多条数据弯折连接线与第一扇出区域B11内的第二组复用数据引出线62b的多条复用数据引出线连接。例如，第一组复用数据线61a可以配置为给显示区域AA的左半侧区域内的子像素提供数据信号，第二组复用数据线61b可以配置为给显示区域AA的右半侧区域内的子像素提供数据信号。
在一些示例中，如图3所示，第二扇出区域B13的多条控制连接线可以沿第二方向Y向第一信号接入区与B14一侧延伸。多条控制连接线可以包括第一组控制连接线65a(例如包括图9所示的第一组复用控制连接线52a和第一组驱动控制连接线82a)和第二组控制连接线65b(例如包括图10所示的第二组复用控制连接线52b和第二组驱动控制连接线82b)。第一组控制连接线65a的多条控制连接线可以通过弯折区域B12的第一组控制弯折连接线35a的多条控制弯折连接线与第一扇出区域B11内的第一组控制引出线64a的多条控制引出线连接。第二组控制连接线65b的多条控制连接线可以通过弯折区域B12的第二组控制弯折连接线35b的多条控制弯折连接线与第一扇出区域B11内的第二组控制引出线64b的多条控制引出线连接。第一组控制连接线65a可以位于第一组复用数据线61a靠近第一电源引出线312的第二主体部的一侧，第二组控制连接线65b可以位于第二组复用数据线61b靠近第一电源引出线312的第二主体部的一侧。
在一些示例中，如图3所示，第二扇出区域B13的多条控制信号线可以包括第一组控制信号线66a和第二组控制信号线66b。第一组控制信号线66a可以与第一组控制连接线65a连接，第二组控制信号线66b可以与第二组控制连接线65b连接。第一组控制信号线66a可以沿第一方向X从一侧(例如左侧)绕过第一信号接入区域B14，并向第二信号接入区域B15延伸。第二组控制信号线66b可以沿第一方向X从另一侧(例如右侧) 绕过第一信号接入区域B14，并向第二信号接入区域B15延伸。
在一些示例中，第二扇出区域B13的多条控制信号线可以包括多条复用控制线(例如包括图9所示的第一组复用控制线51a和图10所示的第二组复用控制线51b)、以及多条驱动控制线(例如包括图9所示的第一组驱动控制线81a和图10所示的第二组驱动控制线81b)。多条复用控制线可以与第一扇出区域B11的多条复用控制引出线(例如包括图6所示的第一组复用控制引出线53a和第二组复用控制引出线53b)连接，被配置为给多路复用电路提供复用控制信号。多条驱动控制线可以与第一扇出区域B11的多条驱动控制引出线(例如包括图6所示的第一组驱动控制引出线83a和第二组驱动控制引出线83b)连接，被配置为给栅极驱动电路提供驱动控制信号(例如包括起始信号、时钟信号、电压信号等)。
在一些示例中，如图3所示，第一信号接入区域B14可以被配置为设置驱动芯片(IC，Integrated Circuit)，例如，第一信号接入区域B14设置的驱动芯片可以是显示驱动芯片或者可以是触控与显示驱动集成芯片(TDDI，Touch and Display Driver Integration)。第一信号接入区域B14还可以称为驱动芯片设置区。驱动芯片可以被配置为产生用于驱动子像素所需的数据信号，并将数据信号提供给显示区域的数据线。
在一些示例中，如图3所示，第一信号接入区域B14可以设置有多个第一接触垫。多个第一接触垫可以包括第一组第一接触垫71a和第二组第一接触垫71b。第二组第一接触垫71b可以位于第一组第一接触垫71a远离显示区域AA的一侧。第一组第一接触垫71a内的多个第一接触垫可以沿第一方向X阵列排布为至少一行。第二扇出区域B13内的多条复用数据线(例如包括第一组复用数据线61a和第二组复用数据线61b)可以与第一信号接入区域B14内的第一组第一接触垫71a内的多个第一接触垫电连接，以配置为从驱动芯片接收数据信号。第二组第一接触垫71b内的多个第一接触垫可以沿第一方向X排布为一行。
在一些示例中，如图3所示，第二信号接入区域B15可以设置有多个第二接触垫72，多个第二接触垫72可以被配置为绑定柔性电路板(FPC，Flexible Printed Circuit)，使得多条信号线(例如，控制信号线、电源线等)通过多个第二接触垫72与外部控制装置连接。第二信号接入区域B15还可以被称为电路绑定区域。第一信号接入区域B14内的第二组第一接触垫71b可以通过多条引脚连接线73与第二信号接入区域B15内的多个第二接触垫72电连接。
在一些示例中，多个第二接触垫72可以包括多个复用控制接触垫(例如图5所示的复用控制接触垫721)。多条复用控制线可以延伸至与第二信号接入区域B15内的多个复用控制接触垫电连接，多条复用控制线可以被配置为通过第二信号接入区域B15的复用控制接触垫接收复用控制信号。
图4为本公开至少一实施例的多路复用电路的等效电路图。图4中以一个多路复用电路40为例进行示意。在一些示例中，如图4所示，一个多路复用电路40可以与九条复用控制线、一条复用数据线61以及多条数据线(例如，第一数据线DL1至第九数据线DL9)电连接。多路复用电路40可以包括九个复用晶体管(即第一复用晶体管M1至第九复用晶体管M9)。九个复用晶体管的栅极可以分别连接不同的复用控制线，即第一复用晶体管M1的栅极连接第一复用控制线511，第二复用晶体管M2的栅极连接第二复用控制线512，第三复用晶体管M3的栅极连接第三复用控制线513，第四复用晶体管M4的栅极连接第四复用控制线514，第五复用晶体管M5的栅极连接第五复用控制线515，第六复用晶体管M6的栅极连接第六复用控制线516，第七复用晶体管M7的栅极连接第七复用控制线517，第八复用晶体管M8的栅极连接第八复用控制线518，第九复用晶体管M9 的栅极连接第九复用控制线519。
在一些示例中，九个复用晶体管的第一极可以均连接同一条复用数据线61。九个复用晶体管的第二极分别连接显示区域的不同数据线。例如，第一复用晶体管M1的第二极连接第一数据线DL1，第二复用晶体管M2的第二极连接第二数据线DL2，第三复用晶体管M3的第二极连接第三数据线DL3，第四复用晶体管M4的第二极连接第四数据线DL4，第五复用晶体管M5的第二极连接第五数据线DL5，第六复用晶体管M6的第二极连接第六数据线DL6，第七复用晶体管M7的第二极连接第七数据线DL7，第八复用晶体管M8的第二极连接第八数据线DL8，第九复用晶体管M9的第二极连接第九数据线DL9。
在一些示例中，显示区域的多个子像素可以包括第一组子像素、第二组子像素和第三组子像素。第一组子像素可以包括第一组第一子像素、第一组第二子像素和第一组第三子像素，第二组子像素可以包括第二组第一子像素、第二组第二子像素和第二组第三子像素，第三组子像素可以包括第三组第一子像素、第三组第二子像素和第三组第三子像素。
在一些示例中，第一数据线DL1可以与出射第一颜色光的第一组第一子像素R1连接，配置为给第一组第一子像素R1提供数据信号。第二数据线DL2可以与出射第二颜色光的第一组第二子像素G1连接，配置为给第一组第二子像素G1提供数据信号。第三数据线DL3可以与第一组第三子像素B1连接，配置为给第一组第三子像素B1提供数据信号。第四数据线DL4可以与第二组第一子像素R2连接，配置为给第二组第一子像素R2提供数据信号。第五数据线DL5可以与第二组第二子像素G2连接，配置为给第二组第二子像素G2提供数据信号。第六数据线DL6可以与第二组第三子像素B2连接，配置为给第二组第三子像素B2提供数据信号。第七数据线DL7可以与第三组第一子像素R3连接，配置为给第三组第一子像素R3提供数据信号。第八数据线DL8可以与第三组第二子像素G3连接，配置为给第三组第二子像素G3提供数据信号。第九数据线GL9可以与第三组第三子像素B3连接，配置为给第三组第三子像素B3提供数据信号。本实施例中，一组子像素可以包括显示区域的至少一列子像素，一列子像素例如可以包括沿第二方向Y排布的多个子像素。例如，第一颜色光可以为红光，第二颜色光可以为绿光，第三颜色光可以为蓝光。
在一些示例中，九条复用控制线可以控制多个多路复用电路40给显示区域的子像素提供数据信号。如图4所示，第一复用控制线511可以配置为提供第一复用控制信号，控制多路复用电路40向第一组第一子像素R1提供数据信号。第二复用控制线512可以配置为提供第二复用控制信号，控制多路复用电路40向第一组第二子像素G1提供数据信号。第三复用控制线513可以配置为提供第三复用控制信号，控制多路复用电路40向第一组第三子像素B1提供数据信号。第四复用控制线514可以配置为提供第四复用控制信号，控制多路复用电路40向第二组第一子像素R2提供数据信号。第五复用控制线515可以配置为提供第五复用控制信号，控制多路复用电路40向第二组第二子像素G2提供数据信号。第六复用控制线516可以配置为提供第六复用控制信号，控制多路复用电路40向第二组第三子像素B2提供数据信号。第七复用控制线517可以配置为提供第七复用控制信号，控制多路复用电路40向第三组第一子像素R3提供数据信号。第八复用控制线518可以配置为提供第八复用控制信号，控制多路复用电路40向第三组第二子像素G3提供数据信号。第九复用控制线519可以配置为提供第九复用控制信号，控制多路复用电路40向第三组第三子像素B3提供数据信号。
在一些示例中，如图3所示，多个多路复用电路40可以设置在第一扇出区域B11内，多条复用控制线(例如包括在第一组控制信号线66a和第二组控制信号线66b内)可以位 于第二扇出区域B13，多条复用控制线可以通过弯折区域B12内的多条控制弯折连接线(例如包括第一组控制弯折连接线35a和第二组控制弯折连接线35b)和第一扇出区域B11内的多条复用控制引出线(例如包括在第一组控制引出线64a和第二组控制引出线64b内)与多个多路复用电路40电连接。多条复用数据线(例如包括第一组复用数据线61a和第二组复用数据线61b)位于第二扇出区域B13，多条复用数据线可以通过弯折区域B12内的多条数据弯折连接线(例如包括第一组数据弯折连接线36a和第二组数据弯折连接线36b)和第一扇出区域B11内的多条复用数据引出线(例如包括第一组复用数据引出线62a和第二组复用数据引出线62b)连接。多路复用电路40可以通过多条数据扇出线63与显示区域AA的多条数据线连接。在第二扇出区域B13内，多条复用控制线在与第二信号接入区域B15的复用控制接触垫(例如图5所示的复用控制接触垫721)连接之后，绕过第一信号接入区域B14向显示面板的第一边框区域的中间区域延伸和聚集，随后向靠近显示区域AA的方向延伸。多条复用数据线(例如包括第一组复用数据线61a和第二组复用数据线61b)集中在第一信号接入区域B14靠近显示区域AA的一侧，且多条复用数据线大致沿第二方向Y向显示区域AA一侧延伸。在图3所示的第二扇出区域B13，多条复用数据线和多条复用控制线会存在交叠，从而形成交叠电容。
在一些示例中，在多路复用电路40采用如图4所示的1:9的设计时(即，多路复用电路40在九条复用控制线的控制下，将一条复用数据线61的数据信号提供给至少九条数据线)，九条复用控制线无法平均分为两组在第一信号接入区域B14的两侧绕线，第一组复用数据线61a中每条复用数据线所交叠的复用控制线的数目和第二组复用数据线61b中每条复用数据线所交叠的复用控制线的数目会存在差异。
图5为本公开至少一实施例的复用控制线和复用数据线的排布示例图。图5中仅以若干条复用数据线为例进行示意。图5所示为显示面板的第二扇出区域的复用控制线和复用数据线的大致走向示意图。本实施例对于复用数据线的数目并不限定。本示例以多路复用电路采用图4所示的1:9的设计为例进行示意。本示例通过设置九条复用控制线的排布方式，可以改善由于多条复用数据线和多条复用控制线的交叠电容不一致而造成的显示区域的局部显示差异性(例如，显示区域左右两侧的显示存在差异)，进而改善显示效果。
在一些示例中，如图3和图5所示，第二信号接入区域B15内的多个第二接触垫可以包括：多个复用控制接触垫721和一组中间接触垫722。例如，多个第二接触垫可以沿第一方向X排布为一行。一组中间接触垫722可以包括多个接触垫，该组中间接触垫722可以通过多条引脚连接线73与第一信号接入区域B14内的第二组第一接触垫71b连接。多个复用控制接触垫721可以包括第一组复用控制接触垫721a和第二组复用控制接触垫721b。第一组复用控制接触垫721a和第二组复用控制接触垫721b可以位于一组中间接触垫722沿第一方向X的相对两侧。
在一些示例中，如图5所示，九条复用控制线可以包括第一组复用控制线51a和第二组复用控制线51b。图3中的第一组控制信号线66a可以包括第一组复用控制线51a，第二组控制信号线66b可以包括第二组复用控制线51b。第一组复用控制线51a可以包括以下四条复用控制线：第四复用控制线514、第七复用控制线517、第八复用控制线518和第九复用控制线519。第二组复用控制线51b可以包括以下五条复用控制线：第一复用控制线511、第二复用控制线512、第三复用控制线513、第六复用控制线516和第五复用控制线515。第一组复用控制线51a可以从第一信号接入区域B14沿第一方向X的一侧(例如左侧)绕过，第二组复用控制线51b可以从第二信号接入区域B14沿第一方向X的另一侧(例如右侧)绕过。
在一些示例中，如图5所示，第一组复用控制线51a可以通过第一组复用控制连接线 52a与弯折区域B12内的第一组控制弯折连接线35a内的部分控制弯折连接线连接；第二组复用控制线51b可以通过第二组复用控制连接线52b与弯折区域B12内的第二组控制弯折连接线35b内的部分控制弯折连接线连接。第一组复用控制连接线52a可以包括第九复用控制连接线529、第八复用控制连接线528、第七复用控制连接线527和第四复用控制连接线524；第二组复用控制连接线52b可以包括第一复用控制连接线521、第二复用控制连接线522、第三复用控制连接线523、第五复用控制连接线525和第六复用控制连接线526。第一复用控制连接线521与第一复用控制线511连接，第二复用控制连接线522与第二复用控制线512连接，第三复用控制连接线523与第三复用控制线513连接，第四复用控制连接线524与第四复用控制线514连接，第五复用控制连接线525与第五复用控制线515连接，第六复用控制连接线526与第六复用控制线516连接，第七复用控制连接线527与第七复用控制线517连接，第八复用控制连接线528与第八复用控制线518连接，第九复用控制连接线529与第九复用控制线519连接。
在一些示例中，如图5所示，第一组复用控制线51a可以与第一组复用控制接触垫721a连接。例如，第一组复用控制线51a中的每条复用控制线可以与第一组复用控制接触垫721a内的至少一个复用控制接触垫721连接。第一组复用控制线51a的每条复用控制线可以至少包括相互连接的第一复用延伸段和第二复用延伸段。以第九复用控制线519为例，第九复用控制线519可以包括：相互连接的第一复用延伸段5191和第二复用延伸段5192，第一复用延伸段5191至少沿第二方向Y延伸，第二复用延伸段5192至少沿第一方向X延伸。第一复用延伸段5191的一端与第一组复用控制接触垫721a内的部分复用控制接触垫721连接，另一端与第二复用延伸段5192的一端连接，第二复用延伸段5192的另一端与第一组控制连接线(例如图3所示的第一组控制连接线65a)内的第一组复用控制连接线52a内的第九复用控制连接线529连接。第一组复用控制线51a内的每条复用控制线的第一复用延伸段可以位于第一组复用数据线61a远离第二组复用数据线61b的一侧，每条复用控制线的第二复用延伸段可以横跨第一组复用数据线61a。第一组复用数据线61a内的每条复用数据线61与第一组复用控制线51a的每条复用控制线的第二复用延伸段在衬底的正投影可以存在交叠。第一组复用数据线61a内的每条复用数据线61与第一组复用控制线51a的每条复用控制线的第二复用延伸段可以交叉。第一组复用数据线61a内的每条复用数据线61与第一组复用控制线51a的每条复用控制线的第二复用延伸段的交叉角度可以大致相同，例如可以均为90度。在另一些示例中，第一组复用控制线51a的至少一条复用控制线的第二复用延伸段与第一组复用数据线61a内的多条复用数据线61的交叉角度可以不同。例如，交叉角度可以小于或等于90度。
在一些示例中，如图5所示，第一组复用控制线51a内的第四复用控制线514、第七复用控制线517、第八复用控制线518和第九复用控制线519可以按照远离第一信号接入区域B14的方向依次排布。然而，本实施例对于第一组复用控制线51a内的四条复用控制线的排布顺序并不限定。例如，第四复用控制线514、第七复用控制线517、第八复用控制线518和第九复用控制线519可以按照靠近第一信号接入区域B14的方向依次排布。又如，第九复用控制线519、第七复用控制线517、第八复用控制线518和第四复用控制线514可以按照靠近或者远离第一信号接入区域B14的方向依次排布。
在一些示例中，如图5所示，第二组复用控制线51b可以与第二组复用控制接触垫721b连接。例如，第二组复用控制线51b中的每条复用控制线可以与第二组复用控制接触垫721b内的至少一个复用控制接触垫721连接。第二组复用控制线51b的每条复用控制线可以至少包括：相互连接的第三复用延伸段和第四复用延伸段。以第一复用控制线511为例，第一复用控制线511可以包括：相互连接的第三复用延伸段5111和第四复用延伸段5112，第三复用延伸段5111可以至少沿第二方向Y延伸，第四复用延伸段5112 可以至少沿第一方向X延伸。第三复用延伸段5111的一端与第二组复用控制接触垫721b内的至少一个复用控制接触垫721连接，另一端与第四复用延伸段5112的一端连接，第四复用延伸段5112的另一端与第二组控制连接线(例如图3所示的第二组控制连接线65b)内的第二组复用控制连接线52b内的第一复用控制连接线521连接。第二组复用控制线51b内的每条复用控制线的第三复用延伸段可以位于第二组复用数据线61b远离第一组复用数据线61a的一侧，每条复用控制线的第四复用延伸段可以横跨第二组复用数据线61b。第二组复用数据线61b内的每条复用数据线61与第二组复用控制线51b的每条复用控制线的第四复用延伸段在衬底的正投影可以存在交叠。第二组复用数据线61b内的每条复用数据线61与第二组复用控制线51b的每条复用控制线的第四复用延伸段可以交叉。第二组复用数据线61b内的每条复用数据线61与第二组复用控制线51b的每条复用控制线的第四复用延伸段的交叉角度可以大致相同，例如可以均为90度。在另一些示例中，第二组复用控制线51b的至少一条复用控制线的第四复用延伸段与第二组复用数据线61b内的多条复用数据线61的交叉角度可以不同。例如，交叉角度可以小于或等于90度。
在一些示例中，如图5所示，第二组复用控制线51b内的第一复用控制线511、第二复用控制线512、第三复用控制线513、第六复用控制线516和第五复用控制线515可以按照远离第一信号接入区域B14的方向依次排布。然而，本实施例对于第二组复用控制线51b内的五条复用控制线的排布顺序并不限定。例如，第一复用控制线511、第二复用控制线512、第三复用控制线513、第六复用控制线516和第五复用控制线515可以按照靠近第一信号接入区域B14的方向依次排布。又如，第一复用控制线511、第三复用控制线513、第二复用控制线512、第六复用控制线516和第五复用控制线515可以按照靠近或者远离第一信号接入区域B14的方向依次排布。
在一些示例中，如图5所示，第一组复用控制线51a和第二组复用控制线51b在绕过第一信号接入区域B14后，在第一组复用数据线61a和第二组复用数据线61a的中间区域汇聚。第一组复用控制线51a的四条复用控制线与第一组复用数据线61a内的每条复用数据线61在衬底的正投影均存在交叠，且与第二组复用数据线61b在衬底的正投影不交叠；第二组复用控制线51b的五条复用控制线与第二组复用数据线61b内的每条复用数据线61在衬底的正投影均存在交叠，且与第一组复用数据线61a在衬底的正投影不交叠。换言之，第一组复用数据线61a中的每条复用数据线61与四条复用控制线在衬底的正投影存在交叠，第二组复用数据线61b中的每条复用数据线61与五条复用控制线在衬底的正投影存在交叠。
下面以图5所示的走线排布方式为例对图3所示的第一边框区域的局部进行示例说明。图6为图3中区域S1的局部放大示意图。图7为图3中区域S2的局部放大示意图。图8A为图7中形成第一栅金属层后的显示面板的示意图。图8B为图7中形成第二栅金属层后的显示面板的示意图。图8C为图7中形成第一源漏金属层后的显示面板的示意图。图9为图3中区域S3的局部放大示意图。图10为图3中区域S4的局部放大示意图。图7至图8C中以一个多路复用电路为例进行示意。
在一些示例中，如图3和图9所示，第一组控制信号线66a可以至少包括：第一组复用控制线51a(即包括第九复用控制线519、第八复用控制线518、第七复用控制线517和第四复用控制线514)、第一组驱动控制线81a(例如包括：扫描起始信号线811、第一扫描时钟信号线821、第二扫描时钟信号线831、第一扫描输出线841、第一初始信号线561、第一低压线571和第一高压线581)。第一组驱动控制线81a可以位于第一组复用控制线51a靠近显示区域的一侧。例如，扫描起始信号线811、第一扫描时钟信号线821、第二扫描时钟信号线831、第一扫描输出线841、第一初始信号线561、第一低压线571、 第一高压线581、第九复用控制线519、第八复用控制线518、第七复用控制线517和第四复用控制线514在第二方向Y上可以沿着远离显示区域的方向依次设置。
在一些示例中，如图3和图9所示，第二扇出区域B13的第一组控制连接线65a可以至少包括：第一组复用控制连接线52a(例如包括：第九复用控制连接线529、第八复用控制连接线528、第七复用控制连接线527及第四复用控制连接线524)、第一组驱动控制连接线82a(例如包括：扫描起始连接线812、第一扫描时钟连接线822、第二扫描时钟连接线832、第一扫描输出连接线842、第一初始连接线563、第一低压连接线573和第一高压连接线583)。
在一些示例中，如图9所示，第九复用控制连接线529与第九复用控制线519连接，第八复用控制连接线528与第八复用控制线518连接，第七复用控制连接线527与第七复用控制线517连接，第四复用控制连接线524与第四复用控制线514连接。扫描起始连接线812与扫描起始信号线811连接，第一扫描时钟连接线822与第一扫描时钟信号线821连接，第二扫描时钟连接线832与第二扫描时钟信号线831连接，第一扫描输出连接线842与第一扫描输出线841连接，第一初始连接线563与初始信号线561连接，第一低压连接线573与第一电压线571连接，第一高压连接线583与第一高压线581连接。
在一些示例中，如图3和图9所示，第一组控制连接线65a的第一组复用控制连接线52a和第一组驱动控制连接线82a可以沿第二方向Y延伸至弯折区域B12，并与弯折区域B12的第一组控制弯折连接线35a连接。第一组控制连接线65a内的第一组驱动控制连接线82a在第一方向X上可以位于第一组复用控制连接线52a靠近第一组复用数据线61a的一侧。例如，第一高压连接线583、第一初始连接线563、第一低压连接线573、第一扫描输出连接线842、扫描起始连接线812、第一扫描时钟连接线822、第二扫描时钟连接线832、第九复用控制连接线529、第八复用控制连接线528、第七复用控制连接线527及第四复用控制连接线524可以在第一方向X上沿着远离第一组复用数据线61a的方向依次设置。本示例将传输恒压信号的第一高压连接线583、第一初始连接线563、第一低压连接线573设置在四条复用控制连接线靠近第一组复用数据线61a的一侧，可以避免第一组复用控制连接线52a对第一组复用数据线61a的干扰。
在一些示例中，如图3和图9所示，第一组控制信号线66a可以为同层结构，例如均位于第一源漏金属层。第一组控制连接线65a内的走线例如可以均为双层走线，例如可以位于第一栅金属层和第二栅金属层。例如，第九复用控制连接线529可以包括：位于第一栅金属层的第一走线5291和位于第二栅金属层的第二走线5292，第九复用控制线519可以位于第一源漏金属层。第九复用控制线519可以通过绝缘层开设的过孔与第九复用控制连接线529的第一走线5291和第二走线5292连接。第九复用控制连接线529的第一走线5291可以沿第二方向Y延伸至第一信号接入区域B14，例如可以与第一信号接入区域B14内的第一无效接触垫(图未示)连接。在另一些示例中，第九复用控制线519在绕过第一信号接入区域B14的位置还可以通过连接线与第一信号接入区域B14内的第二无效接触垫(图未示)连接，第二无效接触垫可以在第一方向X上位于第一组复用数据线61a所连接的第一接触垫远离第一无效接触垫的一侧；第一无效接触垫和第二无效接触垫可以通过接触垫连接线电连接，通过在第一信号接入区域B14设置第九复用控制线的并联线路，有利于降低第九复用控制线的电阻。关于其余控制信号线和控制连接线的膜层结构大致相同，故于此不再赘述。
在一些示例中，如图3和图10所示，第二组控制信号线66b可以至少包括：第二组复用控制线51b(即包括第一复用控制线511、第二复用控制线512、第三复用控制线513、第六复用控制线516和第五复用控制线515)、第二组驱动控制线81b(例如包括：发光 起始信号线851、第一发光时钟信号线861、第二发光时钟信号线871、第二发光输出线881、第二初始信号线562、第二低压线572和第二高压线582)。第二组驱动控制线81b可以位于第二组复用控制线51b靠近显示区域的一侧。例如，发光起始信号线851、第一发光时钟信号线861、第二发光时钟信号线871、第二发光输出线881、第二初始信号线562、第二低压线572、第二高压线582、第一复用控制线511、第二复用控制线512、第三复用控制线513、第六复用控制线516和第五复用控制线515可以沿着远离显示区域的方向依次设置。
在一些示例中，如图3和图10所示，第二扇出区域B13的第二组控制连接线65b可以至少包括：第二组复用控制连接线52b(例如包括：第一复用控制连接线521、第二复用控制连接线522、第三复用控制连接线523、第六复用控制连接线526和第五复用控制连接线525)、第二组驱动控制连接线82b(例如包括：发光起始连接线852、第一发光时钟连接线862、第二发光时钟连接线872、第一发光输出连接线882、第二初始连接线564、第二低压连接线574和第二高压连接线584)。
在一些示例中，如图10所示，第一复用控制连接线521与第一复用控制一线511连接，第二复用控制连接线522与第二复用控制线512连接，第三复用控制连接线523与第三复用控制线513连接，第六复用控制连接线526与第六复用控制线516连接，第五复用控制连接线525与第五复用控制线515连接。发光起始连接线852与发光起始信号线851连接，第一发光时钟连接线862与第一发光时钟信号线861连接，第二发光时钟连接线872与第二发光时钟信号线871连接，第一发光输出连接线882与第一发光输出线881连接，第二初始连接线564与第二初始信号线562连接，第二低压连接线574与第二电压线572连接，第二高压连接线584与第二高压线582连接。
在一些示例中，第一初始信号线561与第二初始信号线562可以为相互连接的一体结构，第一初始信号线561和第二初始信号线562可以被配置为传输初始信号。第一低压线571和第二低压线572可以为相互连接的一体结构。第一低压线571和第二低压线572可以被配置为传输第一电压信号。第一高压线581和第二高压线572可以为相互连接的一体结构。第一高压线581和第二高压线582可以被配置为传输第二电压信号。第二电压信号可以大于第一电压信号。
在一些示例中，如图3和图10所示，第二组控制连接线65b的第二组复用控制连接线52b和第二组驱动控制连接线82b可以沿第二方向Y延伸至弯折区域B12，并与弯折区域B12的第二组控制弯折连接线35b连接。第二组控制连接线65b的第二组驱动控制连接线82b在第一方向X上可以位于第二组复用控制连接线52b靠近第二组复用数据线61b的一侧。例如，第二高压连接线584、第二初始连接线564、第二低压连接线574、第一发光输出连接线882、发光起始连接线852、第一发光时钟连接线862、第二发光时钟连接线872、第一复用控制连接线521、第二复用控制连接线522、第三复用控制连接线523、第六复用控制连接线526和第五复用控制连接线525可以在第一方向X上沿着远离第二组复用数据线61b的方向依次设置。本示例将传输恒压信号的第二高压连接线584、第二初始连接线564、第二低压连接线574设置在五条复用控制连接线靠近第二组复用数据线61b的一侧，可以避免第二组复用控制连接线52b对第二组复用数据线61b的干扰。
在一些示例中，如图3和图10所示，第二组控制信号线66b可以为同层结构，例如均位于第一源漏金属层。第二组控制连接线65b内的走线例如可以均为双层走线，比如可以位于第一栅金属层和第二栅金属层。关于第二组控制信号线66b和第二组控制连接线65b的膜层结构可以参照第一组控制信号线66a和第一组控制连接线65a的膜层结构，故于此不再赘述。
在一些示例中，如图6所示，第一扇出区域B11的第一电源线311的第一主体部例如可以位于第一扇出区域B11沿第一方向X的中线位置。第一电源线311的第一主体部可以与弯折区域B12的第一电源连接线31电连接，例如可以为相互连接的一体结构。第一电源连接线31可以具有沿第二方向Y排布的多个镂空部，多个镂空部的形状和尺寸可以大致相同。本示例通过在弯折区域B12的弯折连接走线上设置镂空部，可以疏导弯折过程中走线上积累的应力，有利于在走线弯折时释放应力，从而改善弯折效果。第一电源连接线31在第一方向X上的两侧边缘可以为波浪形。例如，弯折连接走线的边缘可以由多条弧线段连接形成波浪形。通过设置弯折连接走线的边缘为波浪形，可以分散弯折过程中弯折连接走线受到的弯折应力，可以避免应力集中，改善弯折效果。
在一些示例中，如图3和图6所示，第一扇出区域B11的第一电源线311的第一主体部左侧的第一组控制引出线64a可以包括：第一组复用控制第一引出线53a(例如包括：第九复用控制第一引出线539、第八复用控制第一引出线538、第七复用控制第一引出线537和第四复用控制第一引出线534)、一组复用控制第二引出线54(例如包括：第九复用控制第二引出线549、第八复用控制第二引出线548、第七复用控制第二引出线547、第六复用控制第二引出线546、第五复用控制第二引出线545、第四复用控制第二引出线544、第三复用控制第二引出线543、第二复用控制第二引出线542、第一复用控制第二引出线541)、第一组驱动控制引出线83a(例如包括：扫描起始引出线813、第一扫描时钟引出线823、第二扫描时钟引出线833、第一扫描输出引出线843、第一初始引出线565、第一低压引出线575、第一高压引出线(图未示))。
在一些示例中，如图6所示，第九复用控制第一引出线539、第八复用控制第一引出线538、第七复用控制第一引出线537和第四复用控制第一引出线534可以沿第二方向Y延伸。第九复用控制第一引出线539、第八复用控制第一引出线538、第七复用控制第一引出线537和第四复用控制第一引出线534可以在第一方向X上位于第一组驱动控制引出线83a靠近第一电源线311的第一主体部的一侧。第九复用控制第一引出线539、第八复用控制第一引出线538、第七复用控制第一引出线537和第四复用控制第一引出线534可以在第一方向X上沿着靠近第一电源线311的第一主体部的方向依次设置。第一扫描时钟引出线823、第二扫描时钟引出线833、扫描起始引出线813、扫描输出引出线843、第一低压引出线575、第一初始引出线565和第一高压引出线可以沿第一方向X位于第九复用控制第一引出线539远离第一电源线311的第一主体部的方向依次设置。
在一些示例中，如图3和图6所示，第一扇出区域B11的第一电源线311的第一主体部右侧的第二组控制引出线64b可以包括：第二组复用控制第一引出线53b(例如包括：第一复用控制第一引出线531、第二复用控制第一引出线532、第三复用控制第一引出线533、第六复用控制第一引出线536和第五复用控制第一引出线535)、一组复用控制第三引出线55(例如包括：第九复用控制第三引出线559、第八复用控制第三引出线558、第七复用控制第三引出线557、第六复用控制第三引出线556、第五复用控制第三引出线555、第四复用控制第三引出线554、第三复用控制第三引出线553、第二复用控制第三引出线552、第一复用控制第三引出线551)、第二组驱动控制引出线83b(例如包括：发光起始引出线853、第一发光时钟引出线863、第二发光时钟引出线873、第一发光输出引出线883、第二初始引出线566、第二低压引出线576、第二高压引出线(图未示))。
在一些示例中，如图6所示，第一复用控制第一引出线531、第二复用控制第一引出线532、第三复用控制第一引出线533、第六复用控制第一引出线536和第五复用控制第一引出线535可以大致沿第二方向Y延伸。第一复用控制第一引出线531、第二复用控制第一引出线532、第三复用控制第一引出线533、第六复用控制第一引出线536和第五复 用控制第一引出线535可以在第一方向X上位于第二组驱动控制引出线83b靠近第一电源线311的第一主体部的一侧。第一复用控制第一引出线531、第二复用控制第一引出线532、第三复用控制第一引出线533、第六复用控制第一引出线536和第五复用控制第一引出线535可以在第一方向X上沿着靠近第一电源线311的第一主体部的方向依次设置。第二发光时钟引出线873、第一发光时钟引出线863、发光起始引出线853、发光输出引出线883、第二低压引出线576、第二初始引出线566和第二高压引出线可以沿第一方向X位于第一复用控制引出线531远离第一电源线311的第一主体部的方向依次设置。
在一些示例中，如图6所示，一组复用控制第二引出线54和一组复用控制第三引出线55可以至少沿第一方向X延伸。一组复用控制第二引出线54和一组复用控制第三引出线55可以为同层结构，例如可以位于第一源漏金属层。一组复用控制第二引出线54和一组复用控制第三引出线55可以通过位于第一栅金属层的连接线电连接。
在一些示例中，如图6所示，第九复用控制第二引出线549、第八复用控制第二引出线548、第七复用控制第二引出线547、第六复用控制第二引出线546、第五复用控制第二引出线545、第四复用控制第二引出线544、第三复用控制第二引出线543、第二复用控制第二引出线542、第一复用控制第二引出线541可以在第二方向Y上沿着靠近显示区域AA的方向依次设置。第九复用控制第三引出线559、第八复用控制第三引出线558、第七复用控制第三引出线557、第六复用控制第三引出线556、第五复用控制第三引出线555、第四复用控制第三引出线554、第三复用控制第三引出线553、第二复用控制第三引出线552、第一复用控制第三引出线551可以在第二方向Y上沿着靠近显示区域AA的方向依次设置。
在一些示例中，第九复用控制第二引出线549通过绝缘层设置的过孔与第九复用控制第一引出线539连接，以使得第九复用控制第二引出线549给第一电源线311左侧区域内的多个多路复用电路40提供第九复用控制信号；第九复用控制第二引出线549与第九复用控制第三引出线559连接，使得第九复用控制第三引出线559给第一电源线311右侧区域内的多个多路复用电路40提供第九复用控制信号。
在一些示例中，第八复用控制第二引出线548通过绝缘层设置的过孔与第八复用控制第一引出线538连接，以使得第八复用控制第二引出线548给第一电源线311左侧区域内的多个多路复用电路40提供第八复用控制信号；第八复用控制第二引出线548与第八复用控制第三引出线558连接，使得第八复用控制第三引出线558给第一电源线311右侧区域内的多个多路复用电路40提供第八复用控制信号。
在一些示例中，第七复用控制第二引出线547通过绝缘层设置的过孔与第七复用控制第一引出线537连接，以使得第七复用控制第二引出线547给第一电源线311左侧区域内的多个多路复用电路40提供第七复用控制信号；第七复用控制第二引出线547与第七复用控制第三引出线557连接，使得第七复用控制第三引出线557给第一电源线311右侧区域内的多个多路复用电路40提供第七复用控制信号。
在一些示例中，第四复用控制第二引出线544通过绝缘层设置的过孔与第四复用控制第一引出线534连接，以使得第四复用控制第二引出线544给第一电源线311左侧区域内的多个多路复用电路40提供第四复用控制信号；第四复用控制第二引出线544与第四复用控制第三引出线554连接，使得第四复用控制第三引出线554给第一电源线311右侧区域内的多个多路复用电路40提供第四复用控制信号。
在一些示例中，第五复用控制第三引出线555通过绝缘层设置的过孔与第五复用控制第一引出线535连接，以使得第五复用控制第三引出线555给第一电源线311右侧区域内 的多个多路复用电路40提供第五复用控制信号；第五复用控制第三引出线555与第五复用控制第二引出线545连接，使得第五复用控制第二引出线545给第一电源线311左侧区域内的多个多路复用电路40提供第五复用控制信号。
在一些示例中，第六复用控制第三引出线556通过绝缘层设置的过孔与第六复用控制第一引出线536连接，以使得第六复用控制第三引出线556给第一电源线311右侧区域内的多个多路复用电路40提供第六复用控制信号；第六复用控制第三引出线556与第六复用控制第二引出线546连接，使得第六复用控制第二引出线546给第一电源线311左侧区域内的多个多路复用电路40提供第六复用控制信号。
在一些示例中，第三复用控制第三引出线553通过绝缘层设置的过孔与第三复用控制第一引出线533连接，以使得第三复用控制第三引出线553给第一电源线311右侧区域内的多个多路复用电路40提供第三复用控制信号；第三复用控制第三引出线553与第三复用控制第二引出线543连接，使得第三复用控制第二引出线543给第一电源线311左侧区域内的多个多路复用电路40提供第三复用控制信号。
在一些示例中，第二复用控制第三引出线552通过绝缘层设置的过孔与第二复用控制第一引出线532连接，以使得第二复用控制第三引出线552给第一电源线311右侧区域内的多个多路复用电路40提供第二复用控制信号；第二复用控制第三引出线552与第二复用控制第二引出线542连接，使得第二复用控制第二引出线542给第一电源线311左侧区域内的多个多路复用电路40提供第二复用控制信号。
在一些示例中，第一复用控制第三引出线551通过绝缘层设置的过孔与第一复用控制第一引出线531连接，以使得第一复用控制第三引出线551给第一电源线311右侧区域内的多个多路复用电路40提供第一复用控制信号；第一复用控制第三引出线551与第一复用控制第二引出线541连接，使得第一复用控制第二引出线541给第一电源线311左侧区域内的多个多路复用电路40提供第一复用控制信号。
本示例的第一扇出区域内的第一组控制引出线64a和第二组控制引出线64b的布线方式，有助于实现第一复用控制信号至第九复用控制信号向第一电源线311左右两侧区域内的多路复用电路进行传输，而且可以节省布线空间，以有利于边框窄化。
在一些示例中，如图6所示，以第九复用控制第一引出线539为例，第九复用控制第一引线539可以与静电释放电路41电连接。第九复用控制第一引线539可以包括位于第一栅金属层的走线和位于第二栅金属层的走线，位于第一栅金属层的走线和位于第二栅金属层的走线可以通过位于第一源漏金属层的连接电极电连接。关于其余复用控制第一引出线的结构类似，故于此不再赘述。
在一些示例中，如图7至图8C所示，多路复用电路的九个复用晶体管的有源层位于半导体层。每个复用晶体管的有源层可以包括：第一区、第二区和位于第一区和第二区之间的沟道区。第一复用晶体管M1的第一有源层M10、第二复用晶体管M2的第二有源层M20、第三复用晶体管M3的第三有源层M30、第四复用晶体管M4的第四有源层M40、第五复用晶体管M5的第五有源层M50、第六复用晶体管M6的第六有源层M60、第七复用晶体管M7的第七有源层M70、第八复用晶体管M8的第八有源层M80以及第九复用晶体管M9的第九有源层M90可以沿第一方向X依次排布。其中，第二有源层M20和第三有源层M30可以为相互连接的一体结构，第五有源层M50和第六有源层M60可以为相互连接的一体结构，第八有源层M80和第九有源层M90可以为相互连接的一体结构，从而可以减少多路复用电路的占用空间。然而，本实施例对此并不限定。例如，九个复用晶体管的有源层可以独立设置。
在一些示例中，如图7至图8C所示，多路复用电路的九个复用晶体管的栅极可以位于第一栅金属层。每个复用晶体管的栅极在衬底的正投影可以覆盖对应的有源层的沟道区在衬底的正投影。第一复用晶体管M1的栅极M13、第二复用晶体管M2的栅极M23、第三复用晶体管M3的栅极M33、第四复用晶体管M4的栅极M43、第五复用晶体管M5的栅极M53、第六复用晶体管M6的栅极M63、第七复用晶体管M7的栅极M73、第八复用晶体管M8的栅极M83以及第九复用晶体管M9的栅极M93可以均沿第二方向Y延伸，并依次沿第一方向X排布。
在一些示例中，如图7至图8C所示，多路复用电路的九个复用晶体管的第一极和第二极可以位于第一源漏金属层。第一复用晶体管M1的第一极M11可以同时作为第二复用晶体管M2的第一极和第三复用晶体管M3的第一极。第一复用晶体管M1的第一极M11可以通过层间绝缘层、第二栅绝缘层和第一栅绝缘层开设的多个过孔与第一复用晶体管M1的第一有源层M10的第一区、第二复用晶体管M2的第二有源层M20的第一区、第三复用晶体管M3的第三有源层M30的第一区连接，还可以通过层间绝缘层和第二栅绝缘层开设的过孔与位于第一栅金属层的复用数据引出线62电连接。
在一些示例中，第一复用晶体管M1的第二极M12可以通过层间绝缘层、第二栅绝缘层和第一栅绝缘层开设的多个过孔与第一复用晶体管M1的第一有源层M10的第二区连接，还可以通过层间绝缘层和第二栅绝缘层开设的过孔与位于第一栅金属层的数据扇出线63电连接。第二复用晶体管M2的第二极M22可以通过层间绝缘层、第二栅绝缘层和第一栅绝缘层开设的多个过孔与第二复用晶体管M2的第二有源层M20的第二区连接，还可以通过层间绝缘层开设的过孔与位于第二栅金属层的数据扇出线63电连接。第三复用晶体管M3的第二极M32可以通过层间绝缘层、第二栅绝缘层和第一栅绝缘层开设的多个过孔与第三有源层M30的第二区连接，还可以通过层间绝缘层和第二栅绝缘层开设的过孔与位于第一栅金属层的数据扇出线63电连接。
在一些示例中，第四复用晶体管M4的第一极M41可以同时作为第五复用晶体管M5的第一极和第六复用晶体管M6的第一极。第四复用晶体管M4的第一极M41可以通过层间绝缘层、第二栅绝缘层和第一栅绝缘层开设的多个过孔与第四复用晶体管M4的第四有源层M40的第一区、第五复用晶体管M5的第五有源层M50的第一区、第六复用晶体管M6的第六有源层M60的第一区连接，还可以通过层间绝缘层和第二栅绝缘层开设的过孔与位于第一栅金属层的复用数据引出线62电连接。
在一些示例中，第四复用晶体管M4的第二极M42可以通过层间绝缘层、第二栅绝缘层和第一栅绝缘层开设的多个过孔与第四复用晶体管M4的第四有源层M40的第二区连接，还可以通过层间绝缘层开设的过孔与位于第二栅金属层的数据扇出线63电连接。第五复用晶体管M5的第二极M52可以通过层间绝缘层、第二栅绝缘层和第一栅绝缘层开设的多个过孔与第五复用晶体管M5的第五有源层M50的第二区连接，还可以通过层间绝缘层和第二栅绝缘层开设的过孔与位于第一栅金属层的数据扇出线63电连接。第六复用晶体管M6的第二极M62可以通过层间绝缘层、第二栅绝缘层和第一栅绝缘层开设的多个过孔与第六有源层M60的第二区连接，还可以通过层间绝缘层开设的过孔与位于第二栅金属层的数据扇出线63电连接。
在一些示例中，第七复用晶体管M7的第一极M71可以同时作为第八复用晶体管M8的第一极和第九复用晶体管M9的第一极。第七复用晶体管M7的第一极M71可以通过层间绝缘层、第二栅绝缘层和第一栅绝缘层开设的多个过孔与第七复用晶体管M7的第七有源层M70的第一区、第八复用晶体管M8的第八有源层M80的第一区、第九复用晶体管M9的第九有源层M90的第一区连接，还可以通过层间绝缘层和第二栅绝缘层开设的 过孔与位于第一栅金属层的复用数据引出线62电连接。
在一些示例中，第七复用晶体管M7的第二极M72可以通过层间绝缘层、第二栅绝缘层和第一栅绝缘层开设的多个过孔与第七复用晶体管M7的第一有源层M70的第二区连接，还可以通过层间绝缘层和第二栅绝缘层开设的过孔与位于第一栅金属层的数据扇出线63电连接。第八复用晶体管M8的第二极M82可以通过层间绝缘层、第二栅绝缘层和第一栅绝缘层开设的多个过孔与第八复用晶体管M8的第八有源层M80的第二区连接，还可以通过层间绝缘层开设的过孔与位于第二栅金属层的数据扇出线63电连接。第九复用晶体管M9的第二极M92可以通过层间绝缘层、第二栅绝缘层和第一栅绝缘层开设的多个过孔与第九有源层M90的第二区连接，还可以通过层间绝缘层和第二栅绝缘层开设的过孔与位于第一栅金属层的数据扇出线63电连接。
在一些示例中，如图7至图8C所示，多条数据扇出线63可以交替设置在第一栅金属层和第二栅金属层。多条复用数据引出线62可以交替设置在第一栅金属层和第二栅金属层。本实施例对此并不限定。
在一些示例中，如图7至图8C所示，第一复用晶体管M1的栅极M13可以通过层间绝缘层和第二栅绝缘层开设的过孔与第一复用控制第二引出线541电连接。第二复用晶体管M2的栅极M23可以与第二复用控制第二引出线542电连接。第三复用晶体管M3的栅极M33可以与第三复用控制第二引出线543电连接。第四复用晶体管M4的栅极M43可以与第四复用控制第二引出线544电连接。第五复用晶体管M5的栅极M53可以与第五复用控制第二引出线545电连接。第六复用晶体管M6的栅极M63可以与第六复用控制第二引出线546电连接。第七复用晶体管M7的栅极M73可以与第七复用控制第二引出线547电连接。第八复用晶体管M8的栅极M83可以与第八复用控制第二引出线548电连接。第九复用晶体管M9的栅极M93可以与第九复用控制第二引出线549电连接。
在一些示例中，第九复用控制第二引出线549、第八复用控制第二引出线548、第七复用控制第二引出线547、第六复用控制第二引出线546、第五复用控制第二引出线545、第四复用控制第二引出线544、第三复用控制第二引出线543、第二复用控制第二引出线542、第一复用控制第二引出线541可以位于第一源漏金属层。在一组复用控制第二引出线54靠近多路复用电路的一侧可以设置有第三低压引出线577、第二扫描时钟第二引出线834、第一扫描时钟第二引出线824、第三高压引出线587；第三低压引出线577、第二扫描时钟第二引出线834、第一扫描时钟第二引出线824、第三高压引出线587可以沿着远离多路复用电路的方向依次设置。在一组复用控制第二引出线54远离多路复用电路的一侧可以设置有第一扫描输出第二引出线844。
在一些示例中，第三低压引出线577可以与第一低压引出线575电连接，第三低压引出线577可以给左侧边框区域内的栅极驱动电路提供第一电压信号。第三高压引出线587可以与第一高压引出线电连接，第三高压引出线587可以给左侧边框区域内的栅极驱动电路提供第二电压信号。第一扫描时钟第二引出线824可以与第一扫描时钟引出线823电连接，第二扫描时钟第二引出线834可以与第二扫描时钟引出线833电连接。第一扫描时钟第二引出线824和第二扫描时钟第二引出线834可以给栅极驱动电路提供扫描时钟信号。第一扫描输出第二引出线844可以与第一扫描输出引出线843电连接。
关于设置在第一电源线311右侧区域内的多路复用电路的结构与左侧区域内的多路复用电路的结构类似，故于此不再赘述。其中，右侧区域的多路复用电路可以与一组复用控制第三引出线55电连接。
如图3至图10所示，本示例的第一边框区域内的信号传输的布线可以如表1所示。 其中，数据信号可以由第一信号接入区域B14内的第一接触垫提供，驱动控制信号、第一电源信号、第二电源信号和复用控制信号(例如包括第一复用控制信号至第九复用控制信号)可以由第二信号接入区域B15内的第二接触垫提供。
表1
在一些示例中，如图3至图10所示，第九复用控制线519、第九复用控制连接线529、控制弯折连接线、第九复用控制第一引出线539、第九复用控制第二引出线549和第九复用控制第三引出线559可以依次连接，以实现将第九复用控制信号提供给多个多路复用电路40。
在一些示例中，第八复用控制线518、第八复用控制连接线528、控制弯折连接线、第八复用控制第一引出线538、第八复用控制第二引出线548和第八复用控制第三引出线558可以依次连接，以实现将第八复用控制信号提供给多个多路复用电路40。
在一些示例中，第七复用控制线517、第七复用控制连接线529、控制弯折连接线、第七复用控制第一引出线537、第七复用控制第二引出线547和第七复用控制第三引出线557可以依次连接，以实现将第七复用控制信号提供给多个多路复用电路40。
在一些示例中，第四复用控制线514、第四复用控制连接线524、控制弯折连接线、第四复用控制第一引出线534、第四复用控制第二引出线544和第四复用控制第三引出线554可以依次连接，以实现将第四复用控制信号提供给多个多路复用电路40。
在一些示例中，第六复用控制线516、第六复用控制连接线526、控制弯折连接线、第六复用控制第一引出线536、第六复用控制第三引出线556和第六复用控制第二引出线546可以依次连接，以实现将第六复用控制信号提供给多个多路复用电路40。
在一些示例中，第五复用控制线515、第五复用控制连接线525、控制弯折连接线、第五复用控制第一引出线535、第五复用控制第三引出线555和第五复用控制第二引出线545可以依次连接，以实现将第五复用控制信号提供给多个多路复用电路40。
在一些示例中，第三复用控制线513、第三复用控制连接线523、控制弯折连接线、第三复用控制第一引出线533、第三复用控制第三引出线553和第三复用控制第二引出线543可以依次连接，以实现将第三复用控制信号提供给多个多路复用电路40。
在一些示例中，第二复用控制线512、第二复用控制连接线522、控制弯折连接线、第二复用控制第一引出线532、第二复用控制第三引出线552和第二复用控制第二引出线542可以依次连接，以实现将第二复用控制信号提供给多个多路复用电路40。
在一些示例中，第一复用控制线515、第一复用控制连接线521、控制弯折连接线、第一复用控制第一引出线531、第一复用控制第三引出线551和第一复用控制第二引出线541可以依次连接，以实现将第一复用控制信号提供给多个多路复用电路40。
在一些示例中，第一组复用数据线61a可以配置为给显示区域的左侧区域的子像素提供数据信号，第二组复用数据线61b可以配置为给显示区域的右侧区域的子像素提供数据信号。本示例中，第一组复用数据线61a与四条复用控制线存在交叠，第二组复用数据线61b与五条复用控制线存在交叠。本示例的显示区域的亮度数据如表2所示。表2中的亮度差异率可以指左侧区域和右侧区域的亮度差异的绝对值与左侧区域的亮度之比。
表2
由表2可知，本示例的显示面板中，显示区域的左侧区域和右侧区域的由相同复位控制信号控制提供数据信号的相同颜色子像素的亮度差异均小于0.06％，亮度差异肉眼不可见。虽然本示例的九条复用控制线无法平均分组，并从第一信号接入区域的相对两侧绕线，第一组复用数据线61a和第二组复用数据线61b所交叠的复用控制线的数目不同，但是通过本示例的复用控制线的分组方式，可以改善由于复用数据线和复用控制线的交叠产生的信号负载差异造成的分屏等显示不良。
图11为本公开至少一实施例的复用控制线和复用数据线的另一排布示例图。图11 中仅以若干条复用数据线为例进行示意。本实施例对于复用数据线的数目并不限定。本示例以多路复用电路采用图4所示的1:9的设计为例进行示意。
在一些示例中，如图11所示，第二信号接入区域B15内的多个第二接触垫可以包括：多个复用控制接触垫721和一组中间接触垫722。多个复用控制接触垫721可以包括第一组复用控制接触垫721a和第二组复用控制接触垫721b。第一组复用控制接触垫721a和第二组复用控制接触垫721b可以位于一组中间接触垫722沿第一方向X的相对两侧。
在一些示例中，九条复用控制线中，控制多路复用电路给出射第一颜色光(例如红光)的第一子像素提供数据信号的复用控制线可以为第一类型复用控制线，控制多路复用电路给出射第二颜色光(例如绿光)的第二子像素提供数据信号的复用控制线可以为第二类型复用控制线，控制多路复用电路给出射第三颜色光(例如蓝光)的第三子像素提供数据信号的复用控制线可以为第三类型复用控制线。本示例中，第一类型复用控制线可以包括：第一复用控制线511、第四复用控制线514和第七复用控制线517；第二类型复用控制线可以包括：第二复用控制线512、第五复用控制线515和第八复用控制线518；第三类型复用控制线可以包括：第三复用控制线513、第六复用控制线516和第九复用控制线519。
在一些示例中，如图11所示，九条复用控制线可以包括第一组复用控制线51a和第二组复用控制线51b。第一组复用控制线51a可以包括：第一类型复用控制线(即包括第七复用控制线517、第四复用控制线514、第一复用控制线511)以及一条第三类型复用控制线(例如第三复用控制线513)。第二组复用控制线51b可以包括：第二类型复用控制线(即包括第二复用控制线512、第五复用控制线515、第八复用控制线518)以及剩余的第三类型复用控制线(例如第六复用控制线516和第九复用控制线519)。然而，本实施例对此并不限定。在另一些示例中，第一组复用控制线可以包括：第一类型复用控制线以及两条第三类型复用控制线；第二组复用控制线可以包括：第二类型复用控制线以及一条第三类型复用控制线。对于第一组复用控制线和第二组复用控制线包括的第三类型复用控制线的划分方式并不限定。
在一些示例中，如图11所示，第七复用控制线517、第四复用控制线514、第一复用控制线511和第三复用控制线513可以沿着靠近第一信号接入区域B14的方向依次设置。第二复用控制线512、第五复用控制线515、第八复用控制线518、第六复用控制线516和第九复用控制线519可以沿着远离第一信号接入区域B14的方向依次设置。然而，本实施例对于每组复用控制线内多条复用控制线的排布顺序并不限定。在另一些示例中，第三复用控制线513、第七复用控制线517、第四复用控制线514和第一复用控制线511可以沿着远离或者靠近第一信号接入区域的方向依次设置。又如，第六复用控制线516和第九复用控制线519、第二复用控制线512、第五复用控制线515和第八复用控制线518可以沿着远离或靠近第一信号接入区域B14的方向依次设置。
在一些示例中，如图11所示，第一组复用控制线51a与第一组复用数据线61a在衬底的正投影可以存在交叠，与第二组复用数据线61b在衬底的正投影没有交叠。第二组复用控制线51b与第二组复用数据线61b在衬底的正投影可以存在交叠，与第一组复用数据线61a在衬底的正投影没有交叠。第一组复用数据线61a的每条复用数据线与四条复用控制线在衬底的正投影存在交叠，第二组复用数据线61b的每条复用数据线与五条复用控制线在衬底的正投影存在交叠。
在一些示例中，在第二扇出区域内，通过将控制给第一子像素提供数据信号的第一类型复用控制线和给第二子像素提供数据信号的第二类型复用控制线采用对称布线设计(例如，第一类型复用控制线和第二类型复用控制线可以分别从第一信号接入区域的相对两侧进行绕线，使得从第一信号接入区域相对两侧绕线的复用控制线的数目相同)，可以保证 第一子像素出射的红光和第二子像素出射的绿光的均一性；由于人眼对于第三子像素出射的蓝光最不敏感，通过将控制给第三子像素提供数据信号的第三类型复用控制线采用非对称布线设计(例如，从第一信号接入区域的相对两侧进行绕线的第三类型复用控制线的数目存在差异，一条第三类型复用控制线从第一信号接入区域的左侧绕线，两条第三类型复用控制线从第一信号接入区域的右侧绕线，使得第一信号接入区域相对两侧排布的复用控制线的数目不一致)，可以使得第三子像素出射的蓝光的局部显示差异性为肉眼不可区别，保证显示效果。本示例的复用控制线的非对称布线是指第一信号接入区域相对两侧排布的复用控制线的数目不一致，对称布线是指第一信号接入区域相对两侧排布的复用控制线的数目一致。本示例所采用的九条复用控制线的排布方式，可以改善奇数条的复用控制线的非对称设计产生的复用控制线和复用数据线交叠导致的信号负载差异而造成的显示区域的局部显示差异性，进而可以改善显示效果。
关于本示例的显示面板的其余结构可以参照前述实施例的描述，故于此不再赘述。
图12为本公开至少一实施例的复用控制线和复用数据线的另一排布示例图。图12中仅以若干条复用数据线为例进行示意。本实施例对于复用数据线的数目并不限定。本示例以多路复用电路采用图4所示的1:9的设计为例进行示意。
在一些示例中，如图12所示，九条复用控制线可以包括第一组复用控制线51a和第二组复用控制线51b。第一组复用控制线51a可以包括以下四条复用控制线：第九复用控制线519、第八复用控制线518、第七复用控制线517以及第六复用控制线516。第二组复用控制线51b可以包括以下五条复用控制线：第一复用控制线511、第二复用控制线512、第三复用控制线513、第四复用控制线514和第五复用控制线515。其中，控制多路复用电路给出射第三颜色光的第三子像素的第三复用控制线513可以具有延长线5130。第三复用控制线513的延长线5130可以沿第一方向X向第一组复用数据线61a的方向延伸。
在一些示例中，如图12所示，第一组复用控制线51a中，第九复用控制线519、第八复用控制线518、第七复用控制线517和第六复用控制线516可以沿着靠近第一信号接入区域B14的方向依次设置。然而，本实施例对于第一组复用控制线51a内的四条复用控制线的排布顺序并不限定。在另一些示例中，第九复用控制线519、第八复用控制线518、第七复用控制线517和第六复用控制线516可以沿着远离第一信号接入区域B14的方向依次设置。又如，第六复用控制线516、第九复用控制线519、第八复用控制线518和第七复用控制线517可以沿着远离或靠近第一信号接入区域B14的方向依次设置。
在一些示例中，如图12所示，第二组复用控制线51b中，第一复用控制线511、第二复用控制线512、第三复用控制线513、第四复用控制线514和第五复用控制线515可以沿着远离第一信号接入区域B14的方向依次设置。然而，本实施例对于第二组复用控制线51b内的五条复用控制线的排布顺序并不限定。在另一些示例中，第一复用控制线511、第二复用控制线512、第三复用控制线513、第四复用控制线514和第五复用控制线515可以沿着远离第一信号接入区域B14的方向依次设置。又如，第四复用控制线514、第五复用控制线515、第一复用控制线511、第二复用控制线512和第三复用控制线513可以沿着远离或靠近第一信号接入区域B14的方向依次设置。
在一些示例中，如图12所示，第一组复用控制线51a可以与第一组复用数据线61a在衬底的正投影存在交叠，并与第二组复用数据线61b在衬底的正投影没有交叠。第二组复用控制线51b可以与第二组复用数据线61b在衬底的正投影存在交叠，并与第一组复用数据线61a在衬底的正投影没有交叠。第二组复用控制线51b中的第三复用控制线513的延长线5130在衬底的正投影与第一组复用数据线61a在衬底的正投影存在交叠。
在本示例中，第一组复用数据线61a内的每条复用数据线与第一组复用控制线51a内的四条复用控制线以及第三复用控制线513的延长线5130在衬底的正投影可以存在交叠，即，第一组复用数据线61a内的每条复用数据线与五条复用控制线在衬底的正投影存在交叠。第二组复用数据线61b内的每条复用数据线与第二组复用控制线51b内的五条复用控制线在衬底的正投影存在交叠。在本示例中，每条复用数据线与相同数目(例如五条)的复用控制线在衬底的正投影存在交叠。
本示例通过设置复用控制线的延长线与复用数据线交叠，可以保证多条复用数据线与相同数目的复用控制线交叠，从而改善由于奇数条复用控制线无法均分导致多条复用数据线和多条复用控制线的交叠电容不一致产生的信号负载差异而造成的显示区域的局部显示差异性(例如，显示区域左右两侧的显示存在差异)，进而改善显示效果。由于人眼对第三子像素出射的蓝光最不敏感，通过将控制给第三子像素提供数据信号的第三复用控制线进行延长设计，可以使得第三子像素出射的蓝光的局部显示差异性为肉眼不可区别的基础上，改善数据信号负载差异造成的显示不良。
关于本示例的显示面板的其余结构可以参照前述实施例的描述，故于此不再赘述。
图13为本公开至少一实施例的复用控制线和复用数据线的另一排布示例图。图13中仅以若干条复用数据线为例进行示意。本实施例对于复用数据线的数目并不限定。本示例以多路复用电路采用图4所示的1:9的设计为例进行示意。本示例对于复用控制线的数目并不限定，例如，复用控制线的条数可以为其他奇数。
在一些示例中，如图13所示，九条复用控制线可以包括第一组复用控制线51a和第二组复用控制线51b。第一组复用控制线51a可以包括以下四条复用控制线：第九复用控制线519、第八复用控制线518、第七复用控制线517以及第六复用控制线516。第二组复用控制线51b可以包括以下五条复用控制线：第一复用控制线511、第二复用控制线512、第三复用控制线513、第四复用控制线514和第五复用控制线515。其中，每条复用控制线均具有延长线。例如，第一复用控制线511的延长线5110可以沿第一方向X向第一组复用数据线61a的方向延伸；第二复用控制线512的延长线5120可以沿第一方向X向第一组复用数据线61a的方向延伸；第三复用控制线513的延长线5130可以沿第一方向X向第一组复用数据线61a的方向延伸；第四复用控制线514的延长线5140可以沿第一方向X向第一组复用数据线61a的方向延伸；第五复用控制线515的延长线5150可以沿第一方向X向第一组复用数据线61a的方向延伸；第六复用控制线516的延长线5160可以沿第一方向X向第二组复用数据线61b的方向延伸；第七复用控制线517的延长线5170可以沿第一方向X向第二组复用数据线61b的方向延伸；第八复用控制线518的延长线5180可以沿第一方向X向第二组复用数据线61b的方向延伸；第九复用控制线519的延长线5190可以沿第一方向X向第二组复用数据线61b的方向延伸。第一组复用控制线51a的延长线可以位于第二组复用控制线靠近显示区域的一侧，第二组复用控制线51b的延长线可以位于第一组复用控制线远离显示区域的一侧。
在一些示例中，如图13所示，第一组复用控制线51a中，第九复用控制线519、第八复用控制线518、第七复用控制线517和第六复用控制线516可以沿着靠近第一信号接入区域B14的方向依次设置。第一组复用控制线51a可以与第一组复用数据线61a在衬底的正投影存在交叠，第一组复用控制线51a中每条复用控制线的延长线可以与第二组复用数据线61b在衬底的正投影存在交叠。本实施例对于第一组复用控制线51a内的多条复用控制线的排布顺序并不限定。例如，第九复用控制线519、第八复用控制线518、第七复用控制线517和第六复用控制线516可以沿着远离第一信号接入区域B14的方向依次设置。
在一些示例中，如图13所示，第二组复用控制线51b中，第一复用控制线511、第二复用控制线512、第三复用控制线513、第四复用控制线514和第五复用控制线515可以沿着远离第一信号接入区域B14的方向依次设置。第二组复用控制线51b可以与第二组复用数据线61b在衬底的正投影存在交叠，第二组复用控制线51b中每条复用控制线的延长线与第一组复用数据线61a在衬底的正投影存在交叠。本实施例对于第二组复用控制线51b内的多条复用控制线的排布顺序并不限定。例如，第一复用控制线511、第二复用控制线512、第三复用控制线513、第四复用控制线514和第五复用控制线515可以沿着靠近第一信号接入区域B14的方向依次设置。在另一些示例中，第一组复用控制线51a可以包括五条复用控制线，第二组复用控制线51b可以包括四条复用控制线。本实施例对于每组复用控制线中的多条复用控制线的排布顺序并不限定。
在一些示例中，九条复用控制线的长度(包括延长线的长度)可以大致相同，以保证复用控制线的走线电容一致性。每条复用控制线均与第一组复用数据线61a和第二组复用数据线61b存在交叠，可以保证不同复用控制线和复用数据线之间的交叠电容的一致性，从而改善由于复用控制线和复用数据线的交叠电容不一致而造成的显示不良，可以改善显示效果。
关于本示例的显示面板的其余结构可以参照前述实施例的描述，故于此不再赘述。
图14为本公开至少一实施例的复用控制线和复用数据线的另一排布示例图。图14中仅以若干条复用数据线为例进行示意。本实施例对于复用数据线的数目并不限定。本示例以多路复用电路采用图4所示的1:9的设计为例进行示意。本示例对于复用控制线的数目并不限定，例如，复用控制线的条数可以为其他奇数。
在一些示例中，如图14所示，九条复用控制线中每条复用控制线的第一端可以与第一组复用控制接触垫721a内的至少一个复用控制接触垫721连接，第二端可以与第二组复用控制接触垫721b内的至少一个复用控制接触垫721连接。每条复用控制线可以采用从第一信号接入区域B14靠近显示区域的一侧来绕过第一信号接入区域B14。九条复用控制线中，第一复用控制线511、第二复用控制线512、第三复用控制线513、第四复用控制线514、第五复用控制线515、第六复用控制线516、第七复用控制线517、第八复用控制线518和第九复用控制线519可以沿着靠近第一信号接入区域B14的方向依次设置。然而，本实施例对于九条复用控制线的排布顺序并不限定。例如，第一复用控制线511、第二复用控制线512、第三复用控制线513、第四复用控制线514、第五复用控制线515、第六复用控制线516、第七复用控制线517、第八复用控制线518和第九复用控制线519可以沿着远离第一信号接入区域B14的方向依次设置。
在一些示例中，如图14所示，第一组复用数据线61a可以与九条复用控制线存在交叠，第二组复用数据线61b可以与九条复用控制线存在交叠。九条复用控制线可以在第一组复用数据线61a和第二组复用数据线61b的间隔区域内与第一组复用控制连接线(如图5所示的第一组复用控制连接线52a)和第二组复用控制连接线(如图5所示的第二组复用控制连接线52b)连接，并通过第一组复用控制连接线和第二组复用控制连接线与弯折区域B12内的第一组控制弯折连接线35a和第二组控制弯折连接线35b内的部分控制弯折连接线连接。
本示例通过设置每条复用控制线均与第一组复用数据线61a和第二组复用数据线61b存在交叠，可以保证不同复用控制线和复用数据线之间的交叠电容的一致性，从而改善由于复用控制线和复用数据线的交叠电容不一致而造成的显示不良，可以改善显示效果。
关于本示例的显示面板的其余结构可以参照前述实施例的描述，故于此不再赘述。
图15为本公开至少一实施例的复用控制线和复用数据线的另一排布示例图。图15中仅以若干条复用数据线为例进行示意。本实施例对于复用数据线的数目并不限定。本示例以多路复用电路采用图4所示的1:9的设计为例进行示意。本示例对于复用控制线的数目并不限定，例如，复用控制线的条数可以为其他奇数。
在一些示例中，如图15所示，九条复用控制线可以与多条复用数据线在衬底的正投影没有交叠。九条复用控制线可以包括第一组复用控制线51a和第二组复用控制线51b。第一组复用控制线51a可以包括以下四条复用控制线：第九复用控制线519、第八复用控制线518、第七复用控制线517以及第六复用控制线516。第二组复用控制线51b可以包括以下五条复用控制线：第一复用控制线511、第二复用控制线512、第三复用控制线513、第四复用控制线514和第五复用控制线515。第一组复用控制线可以位于第一组复用数据线61a远离第二组复用数据线61b的一侧，第二组复用控制线可以位于第二组复用数据线61b远离第一组复用数据线61a的一侧。
在一些示例中，如图15所示，第一组复用控制线51a中，第九复用控制线519、第八复用控制线518、第七复用控制线517和第六复用控制线516可以沿着靠近第一信号接入区域B14的方向依次设置。本实施例对于第一组复用控制线51a内的多条复用控制线的排布顺序并不限定。例如，第九复用控制线519、第八复用控制线518、第七复用控制线517和第六复用控制线516可以沿着远离第一信号接入区域B14的方向依次设置。
在一些示例中，如图15所示，第二组复用控制线51b中，第一复用控制线511、第二复用控制线512、第三复用控制线513、第四复用控制线514和第五复用控制线515可以沿着远离第一信号接入区域B14的方向依次设置。本实施例对于第二组复用控制线51b内的多条复用控制线的排布顺序并不限定。例如，第一复用控制线511、第二复用控制线512、第三复用控制线513、第四复用控制线514和第五复用控制线515可以沿着靠近第一信号接入区域B14的方向依次设置。在另一些示例中，第一组复用控制线51a可以包括五条复用控制线，第二组复用控制线51b可以包括四条复用控制线。
在一些示例中，如图15所示，在弯折区域B12内，与第一组复用控制线51a连接的第一组控制弯折连接线35a可以位于第一组数据弯折连接线36a靠近显示面板边缘的一侧。与第二组复用控制线51b连接的第二组控制弯折连接线35b可以位于第二组数据弯折连接线36b靠近显示面板边缘的一侧。
本示例中，通过设置多条复用控制线与多条复用数据线没有交叠，避免多条复用控制线与多条复用数据线交叠产生电容，可以避免由于交叠电容不一致造成的信号负载差异，可以改善显示效果。
关于本示例的显示面板的其余结构可以参照前述实施例的描述，故于此不再赘述。
本实施例还提供一种显示面板，包括：衬底、多个子像素、多条数据线、多个多路复用电路、多条复用数据线以及N条复用控制线。衬底包括显示区域和位于所述显示区域至少一侧的第一边框区域。多个子像素和多条数据线位于所述显示区域，所述多条数据线与所述多个子像素连接，且被配置为给所述多个子像素提供数据信号。多个多路复用电路、多条复用数据线以及N条复用控制线位于所述第一边框区域；其中，N等于2n+1，n为大于0的整数。所述多个多路复用电路中的至少一个多路复用电路与所述N条复用控制线、一条复用数据线和多条数据线电连接，被配置为在所述N条复用控制线的控制下，向所述多条数据线提供所述复用数据线传输的数据信号。所述多条复用数据线中的每条复用数据线的至少部分线段沿第一方向延伸，所述N条复用控制线中的每条复用控制线的至少部分线段沿第二方向延伸。所述复用数据线的至少部分线段和所述复用控制线的至少 部分线段交叉。例如，前述实施例的复用控制线的第二复用延伸段或第四复用延伸段与复用数据线可以交叉。
在一些示例性实施方式中，所述复用控制线的至少部分线段与多条复用数据线的至少部分线段的交叉角度相同。
在一些示例性实施方式中，所述复用控制线的至少部分线段与所述复用数据线的至少部分线段的交叉角度小于或等于90度。例如，复用控制线的至少部分线段与复用数据线的至少部分线段的顺时针交叉角度可以小于或等于90度。
在一些示例性实施方式中，N的取值为9。
关于本示例的显示面板的其余说明可以参照前述实施例的描述，故于此不再赘述。
图16为本公开至少一实施例的显示装置的示意图。如图16所示，本实施例提供一种显示装置91，包括前述实施例的显示面板910。在一些示例中，显示面板910可以为OLED显示面板，例如集成触控结构的OLED显示面板。显示装置91可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件，或者可以为具有触控和显示功能的产品或部件。
在一些示例中，显示装置91可以为穿戴式显示装置，例如可以通过某些方式佩戴在人体上。比如，显示装置91可以为智能手表、智能手环等。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (25)

  1. 一种显示面板，包括：
    衬底，包括显示区域和位于所述显示区域至少一侧的第一边框区域；
    多个子像素和多条数据线，位于所述显示区域，所述多条数据线与所述多个子像素连接，且被配置为给所述多个子像素提供数据信号；
    多个多路复用电路、多条复用数据线以及N条复用控制线，位于所述第一边框区域；其中，N等于2n+1，n为大于0的整数；
    所述多个多路复用电路中的至少一个多路复用电路与所述N条复用控制线、一条复用数据线和多条数据线电连接，被配置为在所述N条复用控制线的控制下，向所述多条数据线提供所述复用数据线传输的数据信号；
    所述多条复用数据线中的每条复用数据线与至少n条复用控制线在所述衬底的正投影存在交叠，或者，所述多条复用数据线与所述N条复用控制线在所述衬底的正投影没有交叠。
  2. 根据权利要求1所述的显示面板，其中，所述N条复用控制线包括第一组复用控制线和第二组复用控制线，所述第一组复用控制线包括n条复用控制线，所述第二组复用控制线包括n+1条复用控制线；
    所述多条复用数据线包括第一组复用数据线和第二组复用数据线，所述第一组复用数据线中的每条复用数据线与所述第一组复用控制线中的n条复用控制线在所述衬底的正投影存在交叠，所述第二组复用数据线中的每条复用数据线与所述第二组复用控制线中的n+1条复用控制线存在交叠。
  3. 根据权利要求2所述的显示面板，其中，所述多个子像素包括：出射第一颜色光的第一子像素、出射第二颜色光的第二子像素和出射第三颜色光的第三子像素；所述N条复用控制线中的至少一条被配置为控制所述多路复用电路通过所述数据线向多个第一子像素提供数据信号，所述N条复用控制线中的至少一条被配置为控制所述多路复用电路通过所述数据线向多个第二子像素提供数据信号，所述N条复用控制线中的至少一条被配置为控制所述多路复用电路通过所述数据线向多个第三子像素提供数据信号。
  4. 根据权利要求3所述的显示面板，其中，n的取值为4。
  5. 根据权利要求4所述的显示面板，其中，所述N条复用控制线包括：第一复用控制线、第二复用控制线、第三复用控制线、第四复用控制线、第五复用控制线、第六复用控制线、第七复用控制线、第八复用控制线和第九复用控制线；
    所述多个子像素包括第一组子像素、第二组子像素和第三组子像素，所述第一组子像素包括第一组第一子像素、第一组第二子像素和第一组第三子像素，所述第二组子像素包括第二组第一子像素、第二组第二子像素和第二组第三子像素，所述第三组子像素包括第三组第一子像素、第三组第二子像素和第三组第三子像素；
    所述第一复用控制线被配置为控制所述多路复用电路给所述第一组第一子像素提供数据信号；
    所述第二复用控制线被配置为控制所述多路复用电路给所述第一组第二子像素提供数据信号；
    所述第三复用控制线被配置为控制所述多路复用电路给所述第一组第三子像素提供数据信号；
    所述第四复用控制线被配置为控制所述多路复用电路给所述第二组第一子像素提供数据信号；
    所述第五复用控制线被配置为控制所述多路复用电路给所述第二组第二子像素提供数据信号；
    所述第六复用控制线被配置为控制所述多路复用电路给所述第二组第三子像素提供数据信号；
    所述第七复用控制线被配置为控制所述多路复用电路给所述第三组第一子像素提供数据信号；
    所述第八复用控制线被配置为控制所述多路复用电路给所述第三组第二子像素提供数据信号；
    所述第九复用控制线被配置为控制所述多路复用电路给所述第三组第三子像素提供数据信号；
    所述第一组复用控制线包括：第四复用控制线、第七复用控制线、第八复用控制线和第九复用控制线；
    所述第二组复用控制线包括：第一复用控制线、第二复用控制线、第三复用控制线、第六复用控制线和第五复用控制线。
  6. 根据权利要求5所述的显示面板，其中，所述第一组复用控制线中，所述第四复用控制线、所述第七复用控制线、所述第八复用控制线和所述第九复用控制线沿着远离所述第二组复用数据线的方向依次排布；
    所述第二组复用控制线中，所述第一复用控制线、所述第二复用控制线、所述第三复用控制线、所述第六复用控制线和所述第五复用控制线沿着远离所述第一组复用数据线的方向依次排布。
  7. 根据权利要求3所述的显示面板，其中，所述N条复用控制线中，控制所述多路复用电路给所述第一子像素提供数据信号的复用控制线为第一类型复用控制线，控制所述多路复用电路给所述第二子像素提供数据信号的复用控制线为第二类型复用控制线，控制所述多路复用电路给所述第三子像素提供数据信号的复用控制线为第三类型复用控制线；
    所述第一组复用控制线包括：所述第一类型复用控制线以及至少一条第三类型复用控制线；
    所述第二组复用控制线包括：所述第三类型复用控制线以及其余的第三类型复用控制线。
  8. 根据权利要求7所述的显示面板，其中，所述N条复用控制线包括：第一复用控制线、第二复用控制线、第三复用控制线、第四复用控制线、第五复用控制线、第六复用控制线、第七复用控制线、第八复用控制线和第九复用控制线；
    所述多个子像素包括第一组子像素、第二组子像素和第三组子像素，所述第一组子像素包括第一组第一子像素、第一组第二子像素和第一组第三子像素，所述第二组子像素包括第二组第一子像素、第二组第二子像素和第二组第三子像素，所述第三组子像素包括第三组第一子像素、第三组第二子像素和第三组第三子像素；
    所述第一复用控制线被配置为控制所述多路复用电路给所述第一组第一子像素提供数据信号；
    所述第二复用控制线被配置为控制所述多路复用电路给所述第一组第二子像素提供 数据信号；
    所述第三复用控制线被配置为控制所述多路复用电路给所述第一组第三子像素提供数据信号；
    所述第四复用控制线被配置为控制所述多路复用电路给所述第二组第一子像素提供数据信号；
    所述第五复用控制线被配置为控制所述多路复用电路给所述第二组第二子像素提供数据信号；
    所述第六复用控制线被配置为控制所述多路复用电路给所述第二组第三子像素提供数据信号；
    所述第七复用控制线被配置为控制所述多路复用电路给所述第三组第一子像素提供数据信号；
    所述第八复用控制线被配置为控制所述多路复用电路给所述第三组第二子像素提供数据信号；
    所述第九复用控制线被配置为控制所述多路复用电路给所述第三组第三子像素提供数据信号；
    所述第一组复用控制线包括：第一复用控制线、第四复用控制线、第七复用控制线、以及第三复用控制线；
    所述第二组复用控制线包括：第二复用控制线、第五复用控制线、第八复用控制线、第六复用控制线和第九复用控制线。
  9. 根据权利要求1所述的显示面板，其中，所述多条复用数据线包括第一组复用数据线和第二组复用数据线，所述第一组复用数据线的每条复用数据线所交叠的复用控制线的数目与所述第二组复用数据线的每条复用数据线所交叠的复用控制线的数目相同。
  10. 根据权利要求9所述的显示面板，其中，所述N条复用控制线包括第一组复用控制线和第二组复用控制线，所述第一组复用控制线包括n条复用控制线，所述第二组复用控制线包括n+1条复用控制线；
    所述第一组复用数据线中的每条复用数据线与所述第一组复用控制线中的n条复用控制线和所述第二组复用控制线中的一条复用控制线的延长线在所述衬底的正投影存在交叠，所述第二组复用数据线中的每条复用数据线与所述第二组复用控制线中的n+1条复用控制线在所述衬底的正投影存在交叠。
  11. 根据权利要求10所述的显示面板，其中，所述多个子像素包括：出射第一颜色光的第一子像素、出射第二颜色光的第二子像素和出射第三颜色光的第三子像素；
    所述第二组复用控制线中具有延长线的复用控制线被配置为控制所述多路复用电路给所述第三子像素提供数据信号。
  12. 根据权利要求11所述的显示面板，其中，所述N条复用控制线包括：第一复用控制线、第二复用控制线、第三复用控制线、第四复用控制线、第五复用控制线、第六复用控制线、第七复用控制线、第八复用控制线和第九复用控制线；
    所述多个子像素包括第一组子像素、第二组子像素和第三组子像素，所述第一组子像素包括第一组第一子像素、第一组第二子像素和第一组第三子像素，所述第二组子像素包括第二组第一子像素、第二组第二子像素和第二组第三子像素，所述第三组子像素包括第三组第一子像素、第三组第二子像素和第三组第三子像素；
    所述第一复用控制线被配置为控制所述多路复用电路给所述第一组第一子像素提供数据信号；
    所述第二复用控制线被配置为控制所述多路复用电路给所述第一组第二子像素提供数据信号；
    所述第三复用控制线被配置为控制所述多路复用电路给所述第一组第三子像素提供数据信号；
    所述第四复用控制线被配置为控制所述多路复用电路给所述第二组第一子像素提供数据信号；
    所述第五复用控制线被配置为控制所述多路复用电路给所述第二组第二子像素提供数据信号；
    所述第六复用控制线被配置为控制所述多路复用电路给所述第二组第三子像素提供数据信号；
    所述第七复用控制线被配置为控制所述多路复用电路给所述第三组第一子像素提供数据信号；
    所述第八复用控制线被配置为控制所述多路复用电路给所述第三组第二子像素提供数据信号；
    所述第九复用控制线被配置为控制所述多路复用电路给所述第三组第三子像素提供数据信号；
    所述第一组复用控制线包括：第六复用控制线、第七复用控制线、第八复用控制线和第九复用控制线；
    所述第二组复用控制线包括：第一复用控制线、第二复用控制线、第三复用控制线、第四复用控制线和第五复用控制线；其中，所述第三复用控制线具有延长线。
  13. 根据权利要求9所述的显示面板，其中，所述第一组复用数据线和所述第二组复用数据线的每条复用数据线与所述N条复用控制线在所述衬底的正投影存在交叠。
  14. 根据权利要求13所述的显示面板，其中，所述N条复用控制线均具有延长线；所述N条复用控制线包括第一组复用控制线和第二组复用控制线，所述第一组复用控制线包括n条复用控制线，所述第二组复用控制线包括n+1条复用控制线；
    所述第一组复用数据线中的每条复用数据线与所述第一组复用控制线中的n条复用控制线和所述第二组复用控制线中的n+1条复用控制线的延长线在所述衬底的正投影存在交叠，所述第二组复用数据线中的每条复用数据线与所述第二组复用控制线中的n+1条复用控制线和所述第一组复用控制线中的n条复用控制线的延长线在所述衬底的正投影存在交叠。
  15. 根据权利要求3至8以及11至12中任一项所述的显示面板，其中，所述第一颜色光为红光，所述第二颜色光为绿光，所述第三颜色光为蓝光。
  16. 根据权利要求1至12以及14中任一项所述的显示面板，其中，所述第一边框区域至少包括：第一信号接入区域和第二信号接入区域，所述第二信号接入区域位于所述第一信号接入区域远离所述显示区域的一侧；所述第一信号接入区域设置有第一组第一接触垫；所述第二信号接入区域设置有多个复用控制接触垫；所述多条复用数据线与所述第一信号接入区域的第一组第一接触垫连接，所述N条复用控制线与所述第二信号接入区域的多个复用控制接触垫连接。
  17. 根据权利要求16所述的显示面板，其中，所述第一信号接入区域还设置有第二组第一接触垫，所述第二组第一接触垫位于所述第一组第一接触垫远离所述显示区域的一侧；所述第二信号接入区域还设置有一组中间接触垫；所述第一信号接入区域的第二组第一接触垫通过多条引脚连接线与所述第二信号接入区域的该组中间接触垫连接；
    所述第二信号接入区域的多个复用控制接触垫包括第一组复用控制接触垫和第二组复用控制接触垫，所述第一组复用控制接触垫和所述第二组复用控制接触垫沿第一方向位于该组中间接触垫的相对两侧。
  18. 根据权利要求17所述的显示面板，其中，所述第一组复用控制线与所述第一组复用控制接触垫连接，所述第二组复用控制线与所述第二组复用控制接触垫连接。
  19. 根据权利要求17所述的显示面板，其中，所述N条复用控制线中每条复用控制线的第一端与所述第一组复用控制接触垫连接，每条复用控制线的第二端与所述第二组复用控制接触垫连接。
  20. 根据权利要求1所述的显示面板，其中，所述多条复用数据线与所述N条复用控制线在所述衬底的正投影没有交叠，所述N条复用控制线包括第一组复用控制线和第二组复用控制线，所述第一组复用控制线包括n条复用控制线，所述第二组复用控制线包括n+1条复用控制线；所述第一组复用控制线和所述第二组复用控制线设置在所述多条复用数据线的相对两侧。
  21. 一种显示装置，包括如权利要求1至20中任一项所述的显示面板。
  22. 一种显示面板，包括：
    衬底，包括显示区域和位于所述显示区域至少一侧的第一边框区域；
    多个子像素和多条数据线，位于所述显示区域，所述多条数据线与所述多个子像素连接，且被配置为给所述多个子像素提供数据信号；
    多个多路复用电路、多条复用数据线以及N条复用控制线，位于所述第一边框区域；其中，N等于2n+1，n为大于0的整数；
    所述多个多路复用电路中的至少一个多路复用电路与所述N条复用控制线、一条复用数据线和多条数据线电连接，被配置为在所述N条复用控制线的控制下，向所述多条数据线提供所述复用数据线传输的数据信号；
    所述多条复用数据线中的每条复用数据线的至少部分线段沿第一方向延伸，所述N条复用控制线中的每条复用控制线的至少部分线段沿第二方向延伸；所述复用数据线的至少部分线段和所述复用控制线的至少部分线段交叉。
  23. 根据权利要求22所述的显示面板，其中，所述复用控制线的至少部分线段与多条复用数据线的至少部分线段的交叉角度相同。
  24. 根据权利要求22所述的显示面板，其中，所述复用控制线的至少部分线段与所述复用数据线的至少部分线段的交叉角度小于或等于90度。
  25. 根据权利要求22所述的显示面板，其中，N的取值为9。
PCT/CN2024/082370 2023-04-25 2024-03-19 显示面板及显示装置 Ceased WO2024222316A1 (zh)

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