WO2024255377A1 - 控制信号传输的方法及装置、系统、存储介质、电子设备 - Google Patents

控制信号传输的方法及装置、系统、存储介质、电子设备 Download PDF

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Publication number
WO2024255377A1
WO2024255377A1 PCT/CN2024/083113 CN2024083113W WO2024255377A1 WO 2024255377 A1 WO2024255377 A1 WO 2024255377A1 CN 2024083113 W CN2024083113 W CN 2024083113W WO 2024255377 A1 WO2024255377 A1 WO 2024255377A1
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Prior art keywords
signal
link
mcu
relay control
dsp
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PCT/CN2024/083113
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English (en)
French (fr)
Inventor
赵伟康
杨才坤
高显扬
姚贯杰
慈潭龙
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Suzhou Metabrain Intelligent Technology Co Ltd
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Suzhou Metabrain Intelligent Technology Co Ltd
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Priority to EP24822333.1A priority Critical patent/EP4580087A4/en
Publication of WO2024255377A1 publication Critical patent/WO2024255377A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/25—Arrangements specific to fibre transmission
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G08—SIGNALLING
    • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C23/00—Non-electrical signal transmission systems, e.g. optical systems
    • G08C23/06—Non-electrical signal transmission systems, e.g. optical systems through light guides, e.g. optical fibres
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

  • the embodiments of the present application relate to the field of computers, and more specifically, to a method and device for controlling signal transmission, a system, a non-volatile readable storage medium, and an electronic device.
  • CXL Computer Express Link
  • Intel Intel Corporation
  • CPU central processing unit
  • GPU graphics processing unit
  • hard disk hard disk
  • network card and other devices inside the server.
  • external servers or between servers and external devices such as memory resource pools and GPU resource pools.
  • the existing technology usually adopts the method of integrating the CXL interface controller with the CPU to form a single SoC (System on a Chip), which is suitable for the CXL optical interconnection of the CPU inside a single server or other host, but not for the CXL external optical interconnection. It is impossible to achieve the interconnection between the server and other hosts and the external memory resource pool or accelerated computing resource pool.
  • the existing technical solution directly skips the link training process that is incompatible with the optical fiber link and the CXL protocol, which requires the corresponding link status to be set in advance between the CPU and the device, which is not suitable for the resource pool, which is an external interconnection architecture that requires flexible expansion.
  • the embodiments of the present application provide a method and apparatus for controlling signal transmission, a system, a non-volatile readable storage medium, and an electronic device, so as to at least solve the problem in the related art that data signals defined by the CXL protocol cannot be transmitted between devices via an optical fiber link.
  • a method for controlling signal transmission is provided, which is applied to a relay control device, and includes: receiving a first signal sent by a first device through a first link, wherein the first link connects the first device and the relay control device, the relay control device is a device supporting the open interconnection standard CXL protocol, and the first signal is an electrical signal; determining a link state of the first link using the first signal; and sending a control instruction to a microcontroller processing unit MCU device based on the link state of the first link, so as to control the transmission of the first signal through the MCU device, wherein the MCU is connected to the relay control device.
  • a method for controlling signal transmission comprises: obtaining a second signal sent by a second device, wherein the second signal is obtained by converting an optical signal received by an optical receiver into an electrical signal, and the optical signal is sent by the second device; transmitting the second signal to a relay control device, wherein the relay control device is a device supporting the open interconnection standard CXL protocol, and the relay control device is configured to recover the second signal and transmit it to the first device through a first link.
  • a device for controlling signal transmission comprising: a relay control device, the relay control device being connected to a first device via a first link, wherein the relay control device is a device supporting an open interconnection standard CXL protocol, and when the first device sends a first signal, the relay control device is configured to receive the first signal via the first link, and is configured to determine a link state of the first link using the first signal; an MCU device, the MCU device being connected to the relay control device, and being configured to control a signal selection device and a DSP device to transmit the first signal according to a control instruction sent by the relay control device, wherein the control instruction includes the link state of the first link, and the signal selection device and the DSP device are both connected to the MCU device.
  • a system for controlling signal transmission includes any one of the above-mentioned devices for controlling signal transmission.
  • a computer non-volatile readable storage medium in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.
  • an electronic device including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.
  • the relay control device is a device that supports the open interconnection standard CXL protocol, it has the ability to identify the state of the first link that transmits the first signal based on the first signal sent by the received first device. It is possible to communicate with the MCU device and send a control instruction to the MCU device so that the MCU device enters the corresponding link state and controls the transmission of the first signal. Thereby, the transmission of data signals of different rates specified by the CXL protocol can be realized. Therefore, the problem that the data signals defined by the CXL protocol cannot be transmitted between devices through an optical fiber link in the related art can be solved, and the effect of transmitting the data signals defined by the CXL protocol through an optical fiber link between devices can be achieved.
  • FIG1 is a hardware structure block diagram of a mobile terminal of a method for controlling signal transmission according to an embodiment of the present application
  • FIG2 is a flowchart of a method for controlling signal transmission according to an embodiment of the present application.
  • FIG3 is a flow chart of a CXL external optical interconnection transmitter according to an embodiment of the present application.
  • FIG4 is a second flowchart of a method for controlling signal transmission according to an embodiment of the present application.
  • FIG5 is a flow chart of a CXL external optical interconnect receiving end according to an embodiment of the present application.
  • FIG6 is a structural block diagram of a device for controlling signal transmission according to an embodiment of the present application.
  • FIG. 7 is a system structure block diagram of a system for controlling signal transmission according to an embodiment of the present application.
  • CXL (Compute Express Link) is an open industrial standard for high-bandwidth and low-latency device interconnection. It can be used to connect devices such as CPU and GPU, memory and smart network card.
  • MCU Micro Controller Unit
  • Micro control unit also known as single-chip microcomputer, is a CPU with appropriately reduced frequency and specifications, and integrates memory, counters, etc. on a single chip.
  • DSP Digital Signal Processor
  • Digital signal processor is a processor composed of large-scale or ultra-large-scale integrated circuit chips to complete digital signal processing tasks.
  • FIG1 is a hardware structure block diagram of a mobile terminal of a method for controlling signal transmission in an embodiment of the present application.
  • the mobile terminal may include one or more (only one is shown in FIG1 ) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA (Field Programmable Gate Array)) and a memory 104 configured to store data, wherein the mobile terminal may also include a transmission device 106 configured as a communication function and an input and output device 108.
  • processors 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA (Field Programmable Gate Array)
  • FPGA Field Programmable Gate Array
  • FIG1 is only for illustration and does not limit the structure of the mobile terminal.
  • the mobile terminal may also include more or fewer components than those shown in FIG1 , or have a configuration different from that shown in FIG1 .
  • the memory 104 may be configured to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for controlling signal transmission in the embodiment of the present application.
  • the processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method.
  • the memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory.
  • the memory 104 may include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the mobile terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
  • the transmission device 106 is configured to receive or send data via a network.
  • the specific example of the above network may include a wireless network provided by a communication provider of the mobile terminal.
  • the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet.
  • the transmission device 106 can be a radio frequency (Radio Frequency, referred to as RF) module, which is configured to communicate with the Internet wirelessly.
  • RF Radio Frequency
  • FIG. 2 is a flow chart of the method for controlling signal transmission according to an embodiment of the present application. As shown in FIG. 2 , the flow chart includes the following steps:
  • Step S202 receiving a first signal sent by a first device through a first link, wherein the first link connects the first device and a relay control device, the relay control device is a device supporting an open interconnection standard CXL protocol, and the first signal is an electrical signal;
  • Step S204 determining a link state of the first link using the first signal
  • Step S206 sending a control instruction to a micro-control processing unit MCU device based on the link state of the first link, so as to control the transmission of the first signal through the MCU device, wherein the MCU is connected to the relay control device.
  • the execution subject of the above steps may be a relay control device, etc., but is not limited thereto.
  • the first device includes but is not limited to a CPU and a GPU, and is externally interconnected with the relay control device via a first link, and the first link is a fiber optic link.
  • the relay control device can be a chip device that supports the open interconnection standard CXL protocol, for example, including but not limited to a switch chip, a retimer chip, a field programmable gate array (FPGA) chip, etc., to realize signal relay and support the detection of the receiving end.
  • the CXL protocol is an interconnection protocol based on PCIe5.0 (Peripheral Component Interconnect Express 5.0, a computer bus high-speed data transmission standard).
  • the data signal transmission rate in normal working state is 32Gbps (Gigabits per second, gigabits per second)/lane (channel).
  • the CXL protocol is very suitable for building a resource pool platform to provide a high-speed, low-latency data transmission channel for independent resource devices. Due to the large link loss of the external copper cable high-speed interconnection solution, the existing technology can only achieve meter-level interconnection under the CXL protocol standard 32Gbps/lane rate condition, which greatly limits the space of the resource pool and the advantages of the external interconnection of the CXL protocol.
  • the optical fiber link loss is much smaller than the copper cable link loss.
  • the CXL external interconnection solution based on optical fiber technology can achieve long-distance, high-speed data transmission, effectively expand the physical boundary of the resource pool, and give full play to the external interconnection advantages of the CXL protocol.
  • This embodiment also defines three link states according to the CXL link transmission and training process, and configures DSP devices and data signal selection devices through MCU to realize the transmission of different types of data signals.
  • the relay control device when the first device sends the first signal through the first link, transmits the current link status information of the first link to the MCU device through a control instruction.
  • the MCU device can control the DSP device and the signal selection device to enter the corresponding state to transmit the first signal transmitted by the relay control device to the optical transmitter for electrical-optical conversion, and finally transmit it outward via the optical fiber.
  • the relay control device is a device that supports the open interconnection standard CXL protocol, it has the ability to identify the state of the first link that transmits the first signal based on the first signal sent by the received first device. It is possible to communicate with the MCU device and send a control instruction to the MCU device so that the MCU device enters the corresponding link state and controls the transmission of the first signal. Thereby, the transmission of data signals of different rates specified by the CXL protocol can be realized. Therefore, the problem that the data signals defined by the CXL protocol cannot be transmitted between devices through an optical fiber link in the related art can be solved, and the effect of transmitting the data signals defined by the CXL protocol between devices through an optical fiber link can be achieved.
  • determining a link state of a first link using a first signal includes: When the signal transmission rate of the first signal is less than the first preset rate, it is determined that the first link is in the link training state, and the first preset rate is set based on the standard rate of the CXL protocol.
  • the standard rate of the CXL protocol is 32Gbps/lane
  • the first preset rate can be the same as the standard rate of the CXL protocol, or it can be less than 32Gbps/lane.
  • the relay control device controls the MCU device to enter the state of the control signal selection device. Specifically as follows:
  • a control instruction is sent to the micro-control processing unit MCU device to control the transmission of the first signal through the MCU device, including: sending a first control instruction to the MCU device to control the signal gating device to receive the first signal from the relay control device through the MCU device, and controlling the signal gating device to transmit the first signal to the optical transmitter, wherein the first control instruction includes information that the first link is in a link training state.
  • the signal gating device can be a data signal gating chip, including but not limited to an ASIC (Application-Specific Integrated Circuit) chip, an ARM (Advanced RISC Machine) chip or an FPGA (Field-Programmable Gate Array) chip, etc., to realize the selection and passing of the signal, and the supported signal rate covers the signal rate specified by the CXL protocol.
  • the MCU device can control the signal gating device to transmit the data signal directly transmitted through the relay control device.
  • there are still four data signal rates namely 2.5Gbps, 5Gbps, 8Gbps and 16Gbps.
  • the DSP devices used in general optical fiber links or optical modules are mainly designed for high-bandwidth signals and are difficult to support low-rate signals during link training.
  • the time required for the DSP device to switch the rate is about 100 ms (millisecond) or s (second), which will cause a huge delay. Therefore, the DSP device is generally set to process constant-rate signals without rate switching.
  • the four rate signals of 2.5Gbps, 5Gbps, 8Gbps and 16Gbps can ensure signal transmission quality without shaping and recovery by the DSP device. Therefore, the data signal during link training is directly transmitted to the optical transmitter through the signal selection device without shaping and recovery by the DSP device.
  • the MCU device when the first link is in the link training state, the MCU device is controlled to control the signal selection device to directly transmit the first signal, so that the low-speed data signal is directly transmitted to the optical receiver without passing through the DSP device, thereby realizing the normal transmission of the low-speed data signal during the entire link training process.
  • determining the link state of the first link using the first signal includes: determining that the first link is in a signal transmission state when the signal transmission rate of the first signal is equal to a first preset rate, wherein the first preset rate is set based on the standard rate of the CXL protocol.
  • the relay control device controls the MCU to enter a state of controlling the signal normally transmitted by the DSP device.
  • a control instruction is sent to the micro-control processing unit MCU device to control the transmission of the first signal through the MCU device, including: sending a second control instruction to the MCU device to control the DSP device to receive the first signal from the relay control device through the MCU device, and control the DSP device to process the first signal to obtain a first processed signal; and controlling the signal selection device to receive the processed signal from the DSP device through the MCU device, and controlling the signal selection device to transmit the first processed signal to the optical transmitter, wherein the second control instruction includes information that the first link is in a signal transmission state.
  • the data signal rate processed by the DSP device is set to 32Gbps, corresponding to the standard rate of the CXL protocol. The DSP device needs to shape and restore the incoming first signal and then transmit it to the signal selection device.
  • the first signal is shaped and restored by the DSP device, so that the normal transmission of the entire link data signal can be achieved.
  • determining the link state of the first link using the first signal includes: determining that the first link is in an idle state when the signal amplitude of the first signal is less than a first preset amplitude, wherein the first preset amplitude is set based on the standard amplitude of the CXL protocol.
  • the first preset amplitude may be the amplitude required by the CXL protocol, for example, the first preset amplitude is 20mV (millivolt). If the signal amplitude of the first signal is lower than 20mV, the first link is in an idle state, and the relay control device controls the MCU device to enter a state of controlling the DSP device. Specifically as follows:
  • a control instruction is sent to the micro-control processing unit MCU device to control the transmission of the first signal through the MCU device, including: sending a third control instruction to the MCU device to control the DSP device to receive the first signal from the relay control device through the MCU device, and control the DSP device to perform noise suppression processing on the first signal to obtain a second processed signal; and control the signal gating device to receive the second processed signal from the DSP device through the MCU device, and control the signal gating device to transmit the second processed signal to the optical transmitter, wherein the third control instruction includes information that the first link is in an idle state.
  • the MCU device controls the DSP device to be in a noise suppression state, and the MCU device controls the signal gating device to transmit a low-noise signal suppressed by the DSP device to avoid the receiving end identifying the low-amplitude noise signal as a normal signal.
  • the entire first link will enter an idle state during the link training process and when there is no data transmission, and low-amplitude (less than 20mV) noise signals are still generated.
  • This low-amplitude noise signal is passed through the DSP device, and the noise is suppressed by the digital circuit inside the DSP device, and then transmitted through the signal selection device, which can reduce the probability that the receiving end optical interconnection device recognizes the noise signal as a normal data signal.
  • the method further includes: transmitting the first signal to the optical transmitter through the signal selection device; performing optical signal conversion on the first signal through the optical transmitter to obtain a first optical signal; and transmitting the first optical signal to the second device through the optical transmitter.
  • the optical transmitter can be connected to the optical receiver in the second device, and the electrical signal is photoelectrically converted into an optical signal and then transmitted to the optical receiver via an optical fiber, thereby realizing the transmission of the signal.
  • the method further includes: receiving a second signal sent by a signal selection device, wherein the second signal is an electrical signal; performing recovery processing on the second signal to obtain a recovery signal; and sending the recovery signal to the first device via the first link.
  • the MCU device enters a corresponding state in combination with the input signal and the register value identifying the current data link state in the relay control device, so as to transmit the electrical signal after the photoelectric conversion of the optical receiver to the relay control device via the DSP device and the signal selection device, and finally transmit it to the first device via the electrical link.
  • the reception of the signal is realized.
  • FIG. 3 it is a flow chart of the CXL external optical interconnection transmitting end in the present embodiment, which specifically includes the following steps:
  • an electrical signal (corresponding to the first signal mentioned above) is input into a CXL relay control device (corresponding to the relay control device mentioned above);
  • the CXL relay control device determines the link state (corresponding to the first link mentioned above) according to the input electrical signal
  • the CXL relay control device controls the MCU (corresponding to the MCU device mentioned above) to enter state 1;
  • MCU controls DSP (corresponding to the DSP device mentioned above) to be in a normal data transmission state, and MCU controls the data strobe chip (corresponding to the signal strobe device mentioned above) to transmit the data signal processed by the DSP chip;
  • the MCU controls the data strobe chip to transmit the data signal directly transmitted via the CXL relay control device;
  • the CXL relay control device controls the MCU to enter state 3;
  • the MCU controls the DSP chip to be in a noise suppression state, and the MCU controls the data selection chip to transmit the low-noise signal suppressed by the DSP chip, so as to prevent the receiving end from identifying the low-amplitude noise signal as a normal signal;
  • the electrical signal transmitted through the data selection chip is photoelectrically converted into an optical signal by the optical transmitter and then transmitted through the optical fiber.
  • FIG. 4 is a second flow chart of the method for controlling signal transmission according to an embodiment of the present application. As shown in FIG. 4 , the flow chart includes the following steps:
  • Step S402 obtaining a second signal sent by a second device, wherein the second signal is obtained by converting a received optical signal into an electrical signal by an optical receiver, and the optical signal is sent by the second device;
  • Step S404 transmit the second signal to a relay control device, wherein the relay control device is a device supporting the open interconnection standard CXL protocol, and the relay control device is configured to perform recovery processing on the second signal and transmit the second signal to the first device through the first link.
  • the relay control device is a device supporting the open interconnection standard CXL protocol, and the relay control device is configured to perform recovery processing on the second signal and transmit the second signal to the first device through the first link.
  • the execution subject of the above steps may be an MCU device, etc., but is not limited thereto.
  • the second device includes but is not limited to a CPU and a GPU.
  • the second device and the first device are both external devices, connected to the relay control device through a link.
  • the first device and the second device are each connected to a relay control device.
  • the relay control device can be a chip device that supports the open interconnection standard CXL protocol, for example, including but not limited to a Switch chip, a Retimer chip, an FPGA chip, etc., to realize signal relay and support the detection of the receiving end.
  • the CXL protocol is an interconnection protocol based on PCIe5.0.
  • the data signal transmission rate in normal working state is 32Gbps/lane. There are processes such as link training in the process of establishing a connection between devices through the CXL interconnection protocol.
  • the CXL protocol is very suitable for building a resource pool platform and providing a high-speed, low-latency data transmission channel for independent resource devices. Due to the large link loss of the external copper cable high-speed interconnection solution, the prior art can only achieve meter-level length interconnection under the rate condition of the CXL protocol standard 32Gbps/lane, which greatly limits the space of the resource pool and the advantages of the external interconnection of the CXL protocol. The loss of optical fiber links is much smaller than that of copper cable links.
  • the CXL external interconnection solution based on optical fiber technology can achieve long-distance, high-speed data transmission, effectively expand the physical boundaries of the resource pool, and give full play to the external interconnection advantages of the CXL protocol.
  • the fiber link transmits the data signal defined by the CXL protocol to realize the external long-distance interconnection of the CXL protocol high-speed signal.
  • This embodiment also defines three link states according to the CXL link transmission and training process, and configures the DSP device and the data signal selection device through the MCU to realize the transmission of different types of data signals.
  • the MCU device when the optical receiver receives the second signal through the optical fiber link, the MCU device combines the second signal and the register value identifying the current data link state in the relay control device to enter the corresponding state, so as to transmit the electrical signal after the photoelectric conversion of the optical receiver to the relay control device via the DSP device and the signal selection device, and finally transmit it to the first device via the first link.
  • the MCU device obtains the second signal sent by the second device, wherein the second signal is obtained by the optical receiver converting the received optical signal into an electrical signal, and the optical signal is sent by the second device; the second signal is transmitted to the relay control device, wherein the relay control device is a device that supports the open interconnection standard CXL protocol, and the relay control device is configured to recover the second signal and transmit it to the first device through the first link, the MCU can enter the corresponding link state and control the transmission of the second signal.
  • the transmission of data signals of different rates specified by the CXL protocol can be realized. Therefore, the problem that the data signals defined by the CXL protocol cannot be transmitted between devices through an optical fiber link in the related art can be solved, and the effect of transmitting the data signals defined by the CXL protocol through an optical fiber link between devices can be achieved.
  • obtaining a second signal sent by a second device includes: obtaining a second signal from a DSP device or a signal gating device, wherein the second signal is a signal transmitted from an optical receiver to the DSP device and the signal gating device.
  • the signal gating device may be a data signal gating chip, including but not limited to an ASIC chip, an ARM chip or an FPGA chip, etc., for realizing the selection and passing of signals, and the supported signal rate covers the signal rate specified by the CXL protocol, including but not limited to an ASIC chip, an ARM chip or an FPGA chip, etc.
  • the optical receiver is connected to the DSP device and the signal gating device, and the second signal will be transmitted to the DSP device and the signal gating device.
  • the DSP device and the signal gating device are also connected to the MCU device, so the MCU device can obtain the second signal from the DSP device or the signal gating device and make a judgment on the second signal.
  • the second signal is transmitted to the relay control device, including: when the signal amplitude of the second signal is less than or equal to the second preset amplitude, sending a third control instruction to the DSP device to control the DSP device to perform noise suppression processing on the second signal to obtain a signal after noise suppression processing; sending a fourth control instruction to the signal gating device to control the signal gating device to transmit the signal after noise suppression processing to the relay control device.
  • the second preset amplitude can be the amplitude of the low-noise signal, and when the signal amplitude of the second signal is less than or equal to the amplitude of the low-noise signal, the MCU device maintains the state of controlling the DSP device, and the MCU device controls the signal gating device to transmit the low-noise signal suppressed by the DSP device. Thereby, the normal transmission of the signal can be guaranteed.
  • transmitting a second signal to a relay control device includes: when the signal amplitude of the second signal is greater than a second preset amplitude, determining whether the second signal includes a character sequence and a register value, wherein the character sequence is used to identify that the second link is in a link training state, and the register value is used to identify the current link state of the second link; when the second signal includes a character sequence and a register value, and the signal amplitude of the second signal is less than or equal to the second preset amplitude, sending a fifth control instruction to a DSP device to control the DSP device to perform noise suppression processing on the second signal to obtain a noise suppression processing.
  • the MCU device controls the signal selection device to transmit the signal after the noise suppression processing to the relay control device.
  • the MCU device exits the state of controlling the DSP device, and the MCU device performs state judgment according to whether there is a character sequence representing link training in the second signal and the register value identifying the current link state in the relay control device.
  • the second signal is transmitted to the relay control device, including: when the second signal includes a character sequence and the register value is a preset register value, sending a seventh control instruction to the DSP device to control the DSP device to perform noise suppression processing on the second signal to obtain a signal after noise suppression processing, wherein the character sequence is used to identify that the second link is in a link training state, and the register value is used to identify the current link state of the second link; sending an eighth control instruction to the signal selection device to control the signal selection device to transmit the signal after noise suppression processing to the relay control device.
  • the MCU device enters the state of controlling the DSP; the MCU device controls the DSP device to be in a normal data transmission state, and the MCU device controls the signal selection device to transmit the data signal processed by the DSP device. Normal transmission of the entire link data signal can be achieved.
  • the method further includes: receiving a first control instruction sent by a relay control device through a first link, wherein the first control instruction includes information that the first link is in a link training state, and the first link connects the first device and the relay control device; responding to the first control instruction, controlling the signal gating device to receive a first signal from the relay control device, and controlling the signal gating device to transmit the first signal to the optical transmitter, wherein the first signal is an electrical signal received by the relay control device from the first device through the first link.
  • the first link is in the link training process, there are still four rates for the data signal, namely 2.5Gbps, 5Gbps, 8Gbps and 16Gbps.
  • the DSP device used in the general optical fiber link or optical module is mainly designed for high-bandwidth signals and is difficult to support low-rate signals during link training.
  • the time required for the DSP device to switch the rate is about hundreds of ms or seconds, which will cause a large delay. Therefore, the DSP device is generally set to process constant-rate signals without rate switching.
  • the four rate signals of 2.5Gbps, 5Gbps, 8Gbps and 16Gbps can ensure the signal transmission quality without shaping and recovery by the DSP device. Therefore, the data signal during link training is directly transmitted to the optical transmitter through the signal selection device without shaping and recovery by the DSP device.
  • the MCU device controls the signal selection device to directly transmit the first signal, so that the low-speed data signal is directly transmitted to the optical receiver without passing through the DSP device, thereby realizing the normal transmission of the low-speed data signal during the entire link training process.
  • the method further includes: receiving a second control instruction sent by a relay control device through a first link, wherein the second control instruction includes information that the first link is in a signal transmission state, and the first link connects the first device and the relay control device; responding to the second control instruction to control the DSP device to receive a first signal from the relay control device, and controlling the DSP device to process the first signal to obtain a first processed signal, and controlling the signal selection device to transmit the first processed signal to the optical transmitter.
  • the data signal rate processed by the DSP device is set to 32Gbps, corresponding to the standard rate of the CXL protocol.
  • the DSP device needs to shape and restore the incoming first signal and transmit it to the signal selection device.
  • the first signal is shaped and restored by the DSP device, so that the normal transmission of the entire link data signal can be achieved.
  • the method further includes: receiving a third control instruction sent by a relay control device through a first link, wherein the third control instruction includes information that the first link is in an idle state, and the first link connects the first device and the relay control device; responding to the third control instruction, controlling the DSP device to receive a first signal from the relay control device, and controlling the DSP device to perform noise suppression processing on the first signal to obtain a second processed signal, and controlling the signal gating device to transmit the second processed signal to the optical transmitter after receiving the second processed signal from the DSP device.
  • the MCU device controls the DSP device to be in a noise suppression state, and the MCU device controls the signal gating device to transmit a low-noise signal suppressed by the DSP device to avoid the receiving end from identifying the low-amplitude noise signal as a normal signal.
  • the entire first link will enter an idle state during link training and when there is no data transmission, and at this time, a low-amplitude (less than 20mV) noise signal is still generated.
  • This low-amplitude noise signal is passed through the DSP device, and the noise is suppressed by the internal digital circuit of the DSP device, and then transmitted through the signal gating device, which can reduce the probability that the receiving end optical interconnection device identifies the noise signal as a normal data signal.
  • the method further includes: converting the signal received from the signal gating device into an optical signal by an optical transmitter, and transmitting the converted optical signal to the second device, thereby transmitting the signal.
  • FIG. 5 it is a flow chart of the CXL external optical interconnect receiving end in the present embodiment, which specifically includes the following steps:
  • the optical receiver After receiving the optical signal, the optical receiver converts the optical signal into an electrical signal (corresponding to the second signal mentioned above) and then transmits it to the DSP and data selection chip;
  • state 3 includes controlling the data strobe chip to transmit the low noise signal after DSP suppression
  • the MCU controls the data strobe chip to transmit the data signal directly transmitted via the CXL relay control device;
  • the electrical signal transmitted through the data strobe chip is further transmitted after passing through the CXL relay control device;
  • the MCU controls the DSP chip to be in a noise suppression state, and the MCU controls the data strobe chip to transmit the low-noise signal suppressed by the DSP chip;
  • MCU controls DSP to be in normal data transmission state
  • MCU controls data strobe chip to transmit DSP Data signal after chip processing.
  • the MCU controls the DSP and the data signal gating chip to enter state 3, at which time the link is in an idle state with only low-amplitude noise signals.
  • State 3 is exited when link training is started or normal rate signals are transmitted, and whether to enter state 1 or state 2 is determined according to the set logic.
  • the technical solution of the present application can be embodied in the form of a software product, which is stored in a non-volatile readable storage medium (such as ROM (Read-0nly Memory)/RAM (Random Access Memory), a disk, or an optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application.
  • a non-volatile readable storage medium such as ROM (Read-0nly Memory)/RAM (Random Access Memory), a disk, or an optical disk
  • a terminal device which can be a mobile phone, a computer, a server, or a network device, etc.
  • a device for controlling signal transmission is also provided, and the device is configured to implement the above-mentioned embodiment and optional implementation mode, and the descriptions that have been made are not repeated.
  • the term "module” can implement software of predetermined functions, and/or a combination of hardware.
  • the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceived.
  • FIG6 is a structural block diagram of a device for controlling signal transmission according to an embodiment of the present application. As shown in FIG6 , the device includes:
  • a relay control device the relay control device is connected to the first device through a first link, wherein the relay control device is a device supporting an open interconnection standard CXL protocol, and when the first device sends a first signal, the relay control device is configured to receive the first signal through the first link, and is configured to determine a link state of the first link using the first signal;
  • the MCU device is connected to the relay control device and is configured to control the signal selection device and the DSP device to transmit the first signal according to the control instruction sent by the relay control device, wherein the control instruction includes the link status of the first link, and the signal selection device and the DSP device are both connected to the MCU device.
  • the apparatus further includes: an optical transmitter, which is connected to a signal selection device, configured to receive a first signal sent by the signal selection device, configured to perform optical signal conversion on the first signal to obtain a first optical signal, and configured to transmit the first optical signal to a second device.
  • an optical transmitter which is connected to a signal selection device, configured to receive a first signal sent by the signal selection device, configured to perform optical signal conversion on the first signal to obtain a first optical signal, and configured to transmit the first optical signal to a second device.
  • the apparatus further includes an optical receiver connected to a second device, configured to convert an optical signal received from the second device into an electrical signal to obtain a second signal, and configured to send the second signal to a DSP device and a signal selection device.
  • the MCU device is also configured to obtain a second signal from a DSP device or a signal gating device, and transmit the second signal to the relay control device through the DSP device and the signal gating device, wherein the DSP device is configured to process the second signal according to the control instruction sent by the MCU device, and the signal gating device is configured to send the processed second signal to the relay control device according to the control instruction sent by the MCU.
  • the relay control device, the MCU device, the DSP device, the signal selection are all arranged in a PCB (Printed Circuit Board).
  • the PCB board can be a board connected to the server mainboard or resource pool bottom board through a gold finger or a cable, or it can be the main body of the server mainboard or resource pool bottom board, which is used to install the devices and components shown in this embodiment and provide an electrical link.
  • the relay control device, MCU device, DSP device, signal gating device, optical transmitter and optical receiver can be in the form of a pluggable optical module, or in the form of an onboard optical module, or in the form of a co-packaged optical module on the same PCB board as the relay control device, so as to realize signal gating processing and photoelectric or electro-optical conversion.
  • the first device includes but is not limited to a CPU, a GPU, and is externally interconnected with the relay control device through a first link, and the first link is a fiber optic link.
  • the relay control device may be a chip device that supports the open interconnection standard CXL protocol, for example, including but not limited to a Switch chip, a Retimer chip, an FPGA chip, etc., to realize signal relay and support detection at the receiving end.
  • the signal gating device may be a data signal gating chip, including but not limited to an ASIC chip, an ARM chip or an FPGA chip, etc., to realize signal selection and pass, and the supported signal rate covers the signal rate specified by the CXL protocol.
  • the MCU device can control the signal gating device to transmit the data signal directly transmitted through the relay control device.
  • the number of DSP devices may be one or more
  • the number of signal gating devices may be one or more
  • the number of MCU devices, optical receivers, and optical transmitters are all one.
  • the relay control device transmits the current status information of the first link to the MCU device, and the MCU device controls the DSP device and the signal selection device to enter the corresponding state to transmit the signal transmitted by the relay control device to the optical transmitter for electrical-to-optical conversion, and finally transmit it outward via the optical fiber.
  • the MCU device when receiving a signal through the optical fiber link, the MCU device combines the input second signal and the register value identifying the current data link state in the relay control device to enter a corresponding state, so as to transmit the electrical signal after the photoelectric conversion of the optical receiver to the CXL relay control device via the DSP device and the signal selection device, and finally transmit it to the first device via the electrical link.
  • the relay control device is a device that supports the open interconnection standard CXL protocol, it has the ability to identify the state of the first link that transmits the first signal according to the first signal sent by the received first device. It is possible to communicate with the MCU device and send a control instruction to the MCU device so that the MCU device enters the corresponding link state and controls the transmission of the first signal. Thereby, the transmission of data signals of different rates specified by the CXL protocol can be realized. Therefore, the problem that the data signals defined by the CXL protocol cannot be transmitted between devices through an optical fiber link in the related art can be solved, and the effect of transmitting the data signals defined by the CXL protocol through an optical fiber link between devices can be achieved.
  • the embodiment of the present application also provides a system for control signal transmission, and the system for control signal transmission includes the above-mentioned control signal transmission device.
  • This embodiment describes the system for control signal transmission in the form of a specific embodiment.
  • Figure 7 it is a system structure block diagram of the system for control signal transmission in this embodiment.
  • the system includes a device for signal transmission between two control signal transmission devices.
  • the first device is a CPU
  • the second device is a CPU/GPU memory hard disk
  • the relay control device is a CXL relay control device
  • the signal gating device is a data signal gating chip
  • the MCU device is an MCU
  • the DSP device is a DSP.
  • the specific interaction process includes:
  • the CPU transmits the electrical signal to the CXL relay control device through the first link, and the CXL relay control device
  • the state of the first link is determined according to the input electrical signal. If the input electrical signal transmission rate is 32Gpbs/s, the link is in a normal data transmission state, the CXL relay control device controls the MCU to enter state 1, the MCU controls the DSP to be in a normal data transmission state, and the MCU controls the data gating chip to transmit the data signal processed by the DSP chip; if the input electrical signal is a signal with a rate lower than 32Gbps/s, the link is in a link training state; the CXL relay control device controls the MCU to enter state 2, and the MCU controls the data gating chip to transmit the data signal directly transmitted through the CXL relay control device; if the input electrical signal amplitude is lower than the protocol requirement (20mV), the link is in an idle state, and the CXL relay control device controls the MCU to enter state 3.
  • the MCU controls the DSP chip to be in a noise suppression state, and the MCU controls the data gating chip to transmit the low-noise signal suppressed by the DSP chip to prevent the receiving end from identifying the low-amplitude noise signal as a normal signal;
  • the electrical signal transmitted through the data gating chip is converted into an optical signal by the optical transmitter and then transmitted to the optical receiver corresponding to the CPU/GPU memory hard disk through the optical fiber.
  • the optical receiver converts the optical signal into an electrical signal and transmits it to the DSP and the data signal gating chip.
  • the MCU obtains the electrical signal from the DSP or the data signal selection chip, and makes a state judgment based on whether the input electrical signal amplitude exceeds the low noise signal amplitude level; if the input DSP electrical signal amplitude exceeds the low noise signal amplitude level, the MCU exits state 3; the state judgment is made based on whether there is a character sequence representing link training in the input signal and the register value indicating the current link state in the CXL relay control; if there is a character sequence representing the link training state in the signal and the register representing the current link rate in the CXL relay control device is not 16Gbps, the MCU enters state 2; the MCU controls the DSP chip to be in a noise suppression state to reduce its power consumption.
  • the MCU determines whether the input DSP electrical signal amplitude does not exceed the low noise signal amplitude level. If the input DSP electrical signal amplitude does not exceed the low noise signal amplitude level, the MCU maintains state 3; the MCU controls the DSP chip to be in a noise suppression state, and the MCU controls the data selection chip to transmit the low noise signal suppressed by the DSP chip. If there is no character sequence representing link training in the signal or there is a character sequence representing link training status but the register representing the current link rate in the CXL relay control device corresponds to 16Gbps, the MCU enters state 1, the MCU controls the DSP to be in normal data transmission state, and the MCU controls the data selection chip to transmit the data signal processed by the DSP chip.
  • this embodiment uses a data signal gating chip in combination with a DSP chip to realize the transmission of data signals of different rates specified by the CXL protocol, and can suppress low-amplitude noise signals when the circuit is in an idle state.
  • Three data link states are defined, and the DSP chip and the data signal gating chip are controlled and adapted by the MCU.
  • This method can give full play to the advantages of the DSP digital chip in high-speed signal transmission and its ability to suppress low-amplitude noise signals, and realize the transmission of low-speed data signals exceeding the bandwidth of the DSP chip through the data signal gating chip.
  • CXL external optical interconnection can be realized, effectively expanding the external transmission distance of the CXL protocol, and the integration form is relatively flexible.
  • the transmission of high-speed and low-speed signals in the CXL protocol link can be realized, and the suppression of low-amplitude noise signals can be realized to reduce the probability of misidentification at the receiving end.
  • the integration form of this solution is relatively flexible, and it is easy to expand, which is conducive to external interconnection between devices.
  • the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.
  • An embodiment of the present application further provides a computer non-volatile readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.
  • the computer non-volatile readable storage medium may include but is not limited to: Limited to: U disk, Read-Only Memory (ROM), Random Access Memory (RAM), mobile hard disk, magnetic disk or CD-ROM and other non-volatile readable storage media that can store computer programs.
  • An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.
  • the electronic device may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.
  • modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation.
  • the present application is not limited to any specific combination of hardware and software.

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Abstract

本申请实施例提供了一种控制信号传输的方法及装置、系统、非易失性可读存储介质、电子设备，该方法包括：通过第一链路接收第一设备发送的第一信号，其中，第一链路连接第一设备和中继控制设备，中继控制设备是支持开放式互连标准CXL协议的设备，第一信号是电信号；利用第一信号确定第一链路的链路状态；基于第一链路的链路状态向微控制处理单元MCU设备发送控制指令，以通过MCU设备控制第一信号的传输，其中，MCU与中继控制设备连接。通过本申请，解决了相关技术中存在的无法实现设备之间通过光纤链路传输CXL协议所定义的数据信号的问题，进而达到了设备之间通过光纤链路传输CXL协议所定义的数据信号的效果。

Description

控制信号传输的方法及装置、系统、存储介质、电子设备
相关申请的交叉引用
本申请要求于2023年06月13日提交中国专利局，申请号为202310696041.8，申请名称为“控制信号传输的方法及装置、系统、存储介质、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及计算机领域，具体而言，涉及一种控制信号传输的方法及装置、系统、非易失性可读存储介质、电子设备。
背景技术
随着高速互连技术的迅速发展，高速互连协议也在不断更迭。CXL(Computer Express Link，一种开放式互连新标准)协议是由Intel(英特尔公司)牵头制定的一项开放的互联标准协议，可用于服务器内部中央处理器(Central Processing Unit，简称为CPU)与图形处理器(Graphics Processing Unit，简称为GPU)、硬盘、网卡等设备的高速率、低延迟连接，也可用于外部服务器与服务器，或服务器与内存资源池、GPU资源池等外部设备的高速率、低延迟连接。
但是，现有技术通常采用将CXL界面控制器与CPU集成形成单一SoC(System on a Chip，芯片系统)的方法，适用于单一服务器等主机内部CPU的CXL光互连，不适用于CXL外部光互连。无法实现服务器等主机与外部内存资源池或加速计算资源池之间的互连。并且，现有技术方案直接跳过光纤链路与CXL协议中不兼容的链路训练过程，这需要提前在CPU与设备之间设定好对应链路状态，不适合资源池这种需要灵活拓展的外部互连架构。
由此可见，相关技术中存在无法实现设备之间通过光纤链路传输CXL协议所定义的数据信号的问题。
发明内容
本申请实施例提供了一种控制信号传输的方法及装置、系统、非易失性可读存储介质、电子设备，以至少解决相关技术中存在的无法实现设备之间通过光纤链路传输CXL协议所定义的数据信号的问题。
根据本申请的一个可选实施例，提供了一种控制信号传输的方法，应用于中继控制设备，包括：通过第一链路接收第一设备发送的第一信号，其中，上述第一链路连接上述第一设备和中继控制设备，上述中继控制设备是支持开放式互连标准CXL协议的设备，上述第一信号是电信号；利用上述第一信号确定上述第一链路的链路状态；基于上述第一链路的链路状态向微控制处理单元MCU设备发送控制指令，以通过上述MCU设备控制第一信号的传输，其中，上述MCU与上述中继控制设备连接。
根据本申请的另一个可选实施例，提供了一种控制信号传输的方法，应用 于MCU设备，包括：获取第二设备发送的第二信号，其中，上述第二信号是光接收器将接收到的光信号进行电信号转换得到的，上述光信号是上述第二设备发送的；将上述第二信号传输至中继控制设备，其中，上述中继控制设备是支持开放式互连标准CXL协议的设备，上述中继控制设备被配置为对上述第二信号进行恢复处理后通过第一链路传输至第一设备。
根据本申请的另一个可选实施例，提供了一种控制信号传输的装置，包括：中继控制设备，上述中继控制设备通过第一链路与第一设备连接，其中，上述中继控制设备是支持开放式互连标准CXL协议的设备，在上述第一设备发送第一信号时，上述中继控制设备被配置为通过上述第一链路接收上述第一信号，并被配置为利用上述第一信号确定上述第一链路的链路状态；MCU设备，上述MCU设备与上述中继控制设备连接，被配置为按照上述中继控制设备发送的控制指令，控制信号选通设备和DSP设备传输上述第一信号，其中，上述控制指令中包括上述第一链路的链路状态，上述信号选通设备和上述DSP设备均与上述MCU设备连接。
根据本申请的另一个可选实施例，提供了一种控制信号传输的系统，控制信号传输的系统包括上述任一项控制信号传输的装置。
根据本申请的又一个可选实施例，还提供了一种计算机非易失性可读存储介质，计算机非易失性可读存储介质中存储有计算机程序，其中，计算机程序被设置为运行时执行上述任一项方法实施例中的步骤。
根据本申请的又一个可选实施例，还提供了一种电子设备，包括存储器和处理器，存储器中存储有计算机程序，处理器被设置为运行计算机程序以执行上述任一项方法实施例中的步骤。
通过本申请，由于中继控制设备是支持开放式互连标准CXL协议的设备，具备根据接收的第一设备发送的第一信号，识别出传输第一信号的第一链路的状态的能力。可以通过与MCU设备进行通信，向MCU设备发送控制指令，使得MCU设备进入对应的链路状态，控制第一信号的传输。从而可以实现对CXL协议规定的不同速率数据信号的传输。因此，可以解决相关技术中存在的无法实现设备之间通过光纤链路传输CXL协议所定义的数据信号的问题，达到实现设备之间通过光纤链路传输CXL协议所定义的数据信号的效果。
附图说明
图1是本申请实施例的一种控制信号传输的方法的移动终端的硬件结构框图；
图2是根据本申请实施例的控制信号传输的方法的流程图一；
图3是根据本申请实施例的CXL外部光互连发送端的流程图；
图4是根据本申请实施例的控制信号传输的方法的流程图二；
图5是根据本申请实施例的CXL外部光互连接收端的流程图；
图6是根据本申请实施例的控制信号传输的装置的结构框图；
图7是根据本申请实施例的控制信号传输的系统的系统结构框图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本申请的实施例。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
下面对本实施例中的相关技术解释如下：
CXL：(Compute Express Link)，是一种开放工业标准用于高带宽低延迟的设备互联。它可以用来连接CPU和GPU，内存和智能网卡等类型的设备。
MCU：(Micro Controller Unit)微控制单元，又称单片机，是CPU的频率与规格做适当缩减，并将内存、计数器等都整合在单一芯片上。
DSP：(Digital Signal Processor)数字信号处理器，是由大规模或超大规模集成电路芯片组成的用来完成数字信号处理任务的处理器。
本申请实施例中所提供的方法实施例可以在移动终端、计算机终端或者类似的运算装置中执行。以运行在移动终端上为例，图1是本申请实施例的一种控制信号传输的方法的移动终端的硬件结构框图。如图1所示，移动终端可以包括一个或多个(图1中仅示出一个)处理器102(处理器102可以包括但不限于微处理器MCU或可编程逻辑器件FPGA(Field Programmable Gate Array)等的处理装置)和被配置为存储数据的存储器104，其中，上述移动终端还可以包括被配置为通信功能的传输设备106以及输入输出设备108。本领域普通技术人员可以理解，图1所示的结构仅为示意，其并不对上述移动终端的结构造成限定。例如，移动终端还可包括比图1中所示更多或者更少的组件，或者具有与图1所示不同的配置。
存储器104可被配置为存储计算机程序，例如，应用软件的软件程序以及模块，如本申请实施例中的控制信号传输的方法对应的计算机程序，处理器102通过运行存储在存储器104内的计算机程序，从而执行各种功能应用以及数据处理，即实现上述的方法。存储器104可包括高速随机存储器，还可包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中，存储器104可包括相对于处理器102远程设置的存储器，这些远程存储器可以通过网络连接至移动终端。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
传输设备106被配置为经由一个网络接收或者发送数据。上述的网络具体实例可包括移动终端的通信供应商提供的无线网络。在一个实例中，传输设备106包括一个网络适配器(Network Interface Controller，简称为NIC)，其可通过基站与其他网络设备相连从而可与互联网进行通讯。在一个实例中，传输设备106可以为射频(Radio Frequency，简称为RF)模块，其被配置为通过无线方式与互联网进行通讯。
在本实施例中提供了一种控制信号传输的方法，图2是根据本申请实施例的控制信号传输的方法的流程图一，如图2所示，该流程包括如下步骤：
步骤S202，通过第一链路接收第一设备发送的第一信号，其中，第一链路连接第一设备和中继控制设备，中继控制设备是支持开放式互连标准CXL协议的设备，第一信号是电信号；
步骤S204，利用第一信号确定第一链路的链路状态；
步骤S206，基于第一链路的链路状态向微控制处理单元MCU设备发送控制指令，以通过MCU设备控制第一信号的传输，其中，MCU与中继控制设备连接。
其中，上述步骤的执行主体可以为中继控制设备等，但不限于此。
本实施例中，第一设备包括但不限于是CPU、GPU，通过第一链路与中继控制设备外部互联，第一链路是光纤链路。
中继控制设备可以是支持开放式互连标准CXL协议的芯片设备，例如，包括但不限于是Switch芯片(交换芯片)、Retimer芯片(重定时芯片)、可编程阵列逻辑(Field Programmable Gate Array，简称为FPGA)芯片等，用以实现信号中继并支持接收端的检测。CXL协议是基于PCIe5.0(Peripheral Component Interconnect Express 5.0，一种计算机总线高速数据传输标准)的互连协议，正常工作状态数据信号传输速率为32Gbps(Gigabits per second，每秒传输的千兆位数)/lane(通道)，设备之间通过CXL互连协议建立连接过程中存在链路训练等过程。得益于CXL协议的特点，CXL协议非常适用于搭建资源池平台，为独立的资源设备提供高速、低延迟数据传输通道。由于外部铜缆高速互连方案链路损耗较大，现有技术在CXL协议标准32Gbps/lane的速率工况下仅能实现米级长度互连，极大地限制了资源池的空间和CXL协议外部互连的优势。而光纤链路损耗远小于铜缆链路损耗，基于光纤技术的CXL外部互连方案可实现长距离、高速率数据传输，有效拓展资源池物理边界，充分发挥CXL协议的外部互连优势，并不需要提前在CPU与设备之间设定好对应链路状态，也可以实现在服务器等主机和资源池等设备之间通过光纤链路传输CXL协议所定义的数据信号，实现CXL协议高速信号的外部长距离互连。本实施例还根据CXL链路传输和训练过程定义了三种链路状态，并通过MCU配置DSP设备和数据信号选通设备以实现不同类型数据信号的传输。
在本实施例中，在第一设备通过第一链路发送第一信号时，中继控制设备将第一链路的当前链路状态信息通过控制指令传输给MCU设备，MCU设备可以控制DSP设备和信号选通设备进入对应状态，以将中继控制设备传入的第一信号传送到光发送器进行电光转换，最后经光纤向外传输。
通过上述步骤，由于中继控制设备是支持开放式互连标准CXL协议的设备，具备根据接收的第一设备发送的第一信号，识别出传输第一信号的第一链路的状态的能力。可以通过与MCU设备进行通信，向MCU设备发送控制指令，使得MCU设备进入对应的链路状态，控制第一信号的传输。从而可以实现对CXL协议规定的不同速率数据信号的传输。因此，可以解决相关技术中存在的无法实现设备之间通过光纤链路传输CXL协议所定义的数据信号的问题，达到实现设备之间通过光纤链路传输CXL协议所定义的数据信号的效果。
在一个示例性实施例中，利用第一信号确定第一链路的链路状态，包括： 在第一信号的信号传输速率小于第一预设速率的情况下，确定第一链路处于链路训练状态，第一预设速率是基于CXL协议的标准速率设定的。在本实施例中，CXL协议的标准速率是32Gbps/lane，第一预设速率可以与CXL协议的标准速率相同，也可以小于32Gbps/lane。例如，在第一信号的传输速率小于32Gbps/lane时，则确定第一链路处于链路训练状态，中继控制设备控制MCU设备进入控制信号选通设备的状态中。具体如下：
基于第一链路的链路状态向微控制处理单元MCU设备发送控制指令，以通过MCU设备控制第一信号的传输，包括：向MCU设备发送第一控制指令，以通过MCU设备控制信号选通设备从中继控制设备处接收第一信号，并控制信号选通设备将第一信号传输至光发送器，其中，第一控制指令中包括第一链路处于链路训练状态的信息。在本实施例中，信号选通设备可以是数据信号选通芯片，包括但不限于是ASIC(Application-Specific Integrated Circuit，特定应用集成电路)芯片、ARM(Advanced RISC Machine，高级精简指令集计算机)芯片或FPGA(Field-Programmable Gate Array，现场可编程门阵列)芯片等，用以实现信号的选择通过，支持的信号速率覆盖CXL协议规定的信号速率。MCU设备可以控制信号选通设备传输经中继控制设备直接传入的数据信号。在第一链路处于链路训练过程中，数据信号还存在4种速率，分别是2.5Gbps、5Gbps、8Gbps和16Gbps，一般光纤链路或光模块中所用DSP设备主要针对高带宽信号设计，难以支持链路训练过程中的低速率信号。并且，DSP设备进行速率切换所需时间约为百ms(millisecond)或s(second)级，会产生极大延时。因此，一般将DSP设备设定为处理恒定速率的信号，不进行速率切换。而2.5Gbps、5Gbps、8Gbps和16Gbps四种速率信号可以在不经DSP设备整形恢复保证信号传输质量，因此链路训练时的数据信号直接通过信号选通设备传输到光发送器，无需经过DSP设备整形恢复。
本实施例在第一链路处于链路训练状态时，控制MCU设备控制信号选通设备直接传输第一信号，使得低速数据信号不经过DSP设备，直接传输至光接收器，从而实现了整个链路训练过程中低速数据信号的正常传输。
在一个示例性实施例中，利用第一信号确定第一链路的链路状态，包括：在第一信号的信号传输速率等于第一预设速率的情况下，确定第一链路处于信号传输状态，其中，第一预设速率是基于CXL协议的标准速率设定的。在本实施例中，例如，在第一信号的传输速率等于32Gbps/lane时，则确定第一链路处于正常的信号传输状态，中继控制设备控制MCU进入控制DSP设备正常传输的信号的状态中。具体如下：
基于第一链路的链路状态向微控制处理单元MCU设备发送控制指令，以通过MCU设备控制第一信号的传输，包括：向MCU设备发送第二控制指令，以通过MCU设备控制DSP设备从中继控制设备处接收第一信号，并控制DSP设备对第一信号进行处理，得到第一处理信号；并通过MCU设备控制信号选通设备从DSP设备处接收处理后的信号，并控制信号选通设备将第一处理信号传输至光发送器，其中，第二控制指令中包括第一链路处于信号传输状态的信息。在本实施例中， DSP设备处理的数据信号速率被设定为32Gbps，对应CXL协议标准速率。DSP设备需对传入的第一信号进行整形恢复后传输至信号选通设备。
本实施例通过DSP设备对第一信号进行整形恢复，可以实现整个链路数据信号的正常传输。
在一个示例性实施例中，利用第一信号确定第一链路的链路状态，包括：在第一信号的信号幅值小于第一预设幅值的情况下，确定第一链路处于空闲状态，其中，第一预设幅值是基于CXL协议的标准幅值设定的。在本实施例中，第一预设幅值可以是CXL协议要求的幅值，例如，第一预设幅值是20mV(millivolt)，若第一信号的信号幅值低于20mV，则第一链路处于空闲状态，中继控制设备控制MCU设备进入控制DSP设备的状态。具体如下：
基于第一链路的链路状态向微控制处理单元MCU设备发送控制指令，以通过MCU设备控制第一信号的传输，包括：向MCU设备发送第三控制指令，以通过MCU设备控制DSP设备从中继控制设备处接收第一信号，并控制DSP设备对第一信号进行噪声抑制处理，得到第二处理信号；并通过MCU设备控制信号选通设备从DSP设备处接收第二处理信号，并控制信号选通设备将第二处理信号传输至光发送器，其中，第三控制指令包括第一链路处于空闲状态的信息。在本实施例中，MCU设备控制DSP设备处于噪声抑制状态，MCU设备控制信号选通设备传输经DSP设备抑制后的低噪声信号，以避免接收端将低幅值噪声信号识别为正常信号。
本实施例在链路训练过程中和无数据传输时整个第一链路会进入空闲状态，此时仍有低幅值(小于20mV)噪声信号产生。将此低幅值噪声信号通过DSP设备，利用DSP设备内部数字电路对噪声进行抑制，之后再通过信号选通设备进行传输，可以降低接收端光互连设备将噪声信号识别为正常数据信号的概率。
在一个示例性实施例中，上述方法还包括：通过信号选通设备将第一信号传输至光发送器；通过光发送器对第一信号进行光信号转换，得到第一光信号；通过光发送器将第一光信号传输至第二设备。在本实施例中，光发送器可以与第二设备中的光接收器连接，将电信号进行光电转换为光信号后经光纤传输至光接收器，从而实现对信号的传输。
在一个示例性实施例中，上述方法还包括：接收信号选通设备发送的第二信号，其中，第二信号是电信号；对第二信号进行恢复处理，得到恢复信号；通过第一链路将恢复信号发送至第一设备。在本实施例中，当光接收器通过光纤链路接收信号时，MCU设备结合输入信号和中继控制设备中标识当前数据链路状态的寄存器值进入对应状态，以将光接收器光电转换后的电信号经DSP设备和信号选通设备传入到中继控制设备，最后经电链路传输到第一设备。从而实现对信号的接收。
下面结合图3对本实施例进行详细说明，如图3所示，是本实施例中的CXL外部光互连发送端的流程图，具体包括以下步骤：
S301，电信号(对应于上述中的第一信号)输入CXL中继控制设备(对应于上述中的中继控制设备)；
S302，CXL中继控制设备根据输入电信号判断链路(对应于上述中的第一链路)状态；
S303，若输入电信号传输速率为32Gpbs/s，则链路处于正常数据传输状态；
S304，CXL中继控制设备控制MCU(对应于上述中的MCU设备)进入状态1；
S305，MCU控制DSP(对应于上述中的DSP设备)处于正常数据传输状态，MCU控制数据选通芯片(对应于上述中的信号选通设备)传输DSP芯片处理后的数据信号；
S307，若输入电信号为低于32Gbps/s速率的信号，则链路处于链路训练状态；
S308，CXL中继控制设备控制MCU进入状态2；
S309，MCU控制数据选通芯片传输经CXL中继控制设备直接传入的数据信号；
S310，若输入电信号幅值低于协议要求(20mV)，则链路处于空闲状态；
S311，CXL中继控制设备控制MCU进入状态3；
S312，MCU控制DSP芯片处于噪声抑制状态，MCU控制数据选通芯片传输经DSP芯片抑制后的低噪声信号，避免接收端将低幅值噪声信号识别为正常信号；
S306，经数据选通芯片传入的电信号经光发送器进行光电转换为光信号后经光纤传输。
在本实施例中提供了一种控制信号传输的方法，图4是根据本申请实施例的控制信号传输的方法的流程图二，如图4所示，该流程包括如下步骤：
步骤S402，获取第二设备发送的第二信号，其中，第二信号是光接收器将接收到的光信号进行电信号转换得到的，光信号是第二设备发送的；
步骤S404，将第二信号传输至中继控制设备，其中，中继控制设备是支持开放式互连标准CXL协议的设备，中继控制设备被配置为对第二信号进行恢复处理后通过第一链路传输至第一设备。
其中，上述步骤的执行主体可以为MCU设备等，但不限于此。
本实施例中，第二设备包括但不限于是CPU、GPU。第二设备与第一设备均是外接设备，通过链路与中继控制设备连接，需要说明的是，第一设备个第二设备各连接一个中继控制设备。中继控制设备可以是支持开放式互连标准CXL协议的芯片设备，例如，包括但不限于是Switch芯片、Retimer芯片、FPGA芯片等，用以实现信号中继并支持接收端的检测。CXL协议是基于PCIe5.0的互连协议，正常工作状态数据信号传输速率为32Gbps/lane，设备之间通过CXL互连协议建立连接过程中存在链路训练等过程。得益于CXL协议的特点，CXL协议非常适用于搭建资源池平台，为独立的资源设备提供高速、低延迟数据传输通道。由于外部铜缆高速互连方案链路损耗较大，现有技术在CXL协议标准32Gbps/lane的速率工况下仅能实现米级长度互连，极大地限制了资源池的空间和CXL协议外部互连的优势。而光纤链路损耗远小于铜缆链路损耗，基于光纤技术的CXL外部互连方案可实现长距离、高速率数据传输，有效拓展资源池物理边界，充分发挥CXL协议的外部互连优势，并不需要提前在CPU与设备之间设定好对应链路状态，也可以实现在服务器等主机和资源池等设备之间通过光 纤链路传输CXL协议所定义的数据信号，实现CXL协议高速信号的外部长距离互连。本实施例还根据CXL链路传输和训练过程定义了三种链路状态，并通过MCU配置DSP设备和数据信号选通设备以实现不同类型数据信号的传输。
在本实施例中，在光接收器通过光纤链路接收第二信号时，MCU设备结合第二信号和中继控制设备中标识当前数据链路状态的寄存器值进入对应状态，以将光接收器光电转换后的电信号经DSP设备和信号选通设备传入到中继控制设备中，最后经第一链路传输到第一设备。
通过上述步骤，由于MCU设备获取第二设备发送的第二信号，其中，第二信号是光接收器将接收到的光信号进行电信号转换得到的，光信号是第二设备发送的；将第二信号传输至中继控制设备，其中，中继控制设备是支持开放式互连标准CXL协议的设备，中继控制设备被配置为对第二信号进行恢复处理后通过第一链路传输至第一设备，MCU可以进入对应的链路状态，控制第二信号的传输。从而可以实现对CXL协议规定的不同速率数据信号的传输。因此，可以解决相关技术中存在的无法实现设备之间通过光纤链路传输CXL协议所定义的数据信号的问题，达到实现设备之间通过光纤链路传输CXL协议所定义的数据信号的效果。
在一个示例性实施例中，获取第二设备发送的第二信号，包括：从DSP设备或者信号选通设备中获取第二信号，其中，第二信号是光接收器传输至DSP设备和信号选通设备的信号。在本实施例中，信号选通设备可以是数据信号选通芯片，包括但不限于是ASIC芯片、ARM芯片或FPGA芯片等，用以实现信号的选择通过，支持的信号速率覆盖CXL协议规定的信号速率，包括但不限于ASIC芯片、ARM芯片或FPGA芯片等。光接收器和DSP设备、信号选通设备均连接，会将第二信号传输至DSP设备和信号选通设备，DSP设备和信号选通设备又均与MCU设备连接，所以MCU设备可以从DSP设备或者信号选通设备中获取第二信号，对第二信号进行判断。
在一个示例性实施例中，将第二信号传输至中继控制设备，包括：在第二信号的信号幅值小于或等于第二预设幅值的情况下，向DSP设备发送第三控制指令，以控制DSP设备对第二信号进行噪声抑制处理，得到噪声抑制处理后的信号；向信号选通设备发送第四控制指令，以控制信号选通设备向中继控制设备传输噪声抑制处理后的信号。在本实施例中，第二预设幅值可以是低噪声信号的幅值，在第二信号的信号幅值小于或等于低噪声信号的幅值的情况下，MCU设备保持控制DSP设备的状态，MCU设备控制信号选通设备传输经DSP设备抑制后的低噪声信号。从而可以保证信号的正常传输。
在一个示例性实施例中，将第二信号传输至中继控制设备，包括：在第二信号的信号幅值大于第二预设幅值的情况下，判断第二信号中是否包括字符序列和寄存器值，其中，字符序列用于标识第二链路处于链路训练状态，寄存器值用于标识第二链路的当前链路状态；在第二信号中包括字符序列和寄存器值，且第二信号的信号幅值小于或等于第二预设幅值的情况下，向DSP设备发送第五控制指令，以控制DSP设备对第二信号进行噪声抑制处理，得到噪声抑制处 理后的信号；向信号选通设备发送第六控制指令，以控制信号选通设备向中继控制设备传输噪声抑制处理后的信号。在本实施例中，在第二信号的信号幅值大于低噪声信号的幅值的情况下MCU设备退出控制DSP设备的状态，MCU设备根据第二信号中是否有代表链路训练的字符序列和中继控制设备中标识当前链路状态的寄存器值进行状态判断。
在一个示例性实施例中，将第二信号传输至中继控制设备，包括：在第二信号中包括字符序列，且寄存器值是预设寄存器值的情况下，向DSP设备发送第七控制指令，以控制DSP设备对第二信号进行噪声抑制处理，得到噪声抑制处理后的信号，其中，字符序列用于标识第二链路处于链路训练状态，寄存器值用于标识第二链路的当前链路状态；向信号选通设备发送第八控制指令，以控制信号选通设备向中继控制设备传输噪声抑制处理后的信号。在本实施例中，在第二信号中没有代表链路训练的字符序列或有代表链路训练状态的字符序列，但中继控制设备中代表当前链路速率的寄存器对应16Gbps，则MCU设备进入控制DSP的状态；MCU设备控制DSP设备处于正常数据传输状态，MCU设备控制信号选通设备传输DSP设备处理后的数据信号。可以实现整个链路数据信号的正常传输。
在一个示例性实施例中，方法还包括：通过第一链路接收中继控制设备发送的第一控制指令，其中，第一控制指令中包括第一链路处于链路训练状态的信息，第一链路连接第一设备和中继控制设备；响应第一控制指令，以控制信号选通设备从中继控制设备处接收第一信号，并控制信号选通设备将第一信号传输至光发送器，其中，第一信号是中继控制设备通过第一链路从第一设备处接收的电信号。在本实施例中，在第一链路处于链路训练过程中，数据信号还存在4种速率，分别是2.5Gbps、5Gbps、8Gbps和16Gbps，一般光纤链路或光模块中所用DSP设备主要针对高带宽信号设计，难以支持链路训练过程中的低速率信号。并且，DSP设备进行速率切换所需时间约为百ms或s级，会产生极大延时。因此，一般将DSP设备设定为处理恒定速率的信号，不进行速率切换。而2.5Gbps、5Gbps、8Gbps和16Gbps四种速率信号可以在不经DSP设备整形恢复保证信号传输质量，因此链路训练时的数据信号直接通过信号选通设备传输到光发送器，无需经过DSP设备整形恢复。本实施例在第一链路处于链路训练状态时，控制MCU设备控制信号选通设备直接传输第一信号，使得低速数据信号不经过DSP设备，直接传输至光接收器，从而实现了整个链路训练过程中低速数据信号的正常传输。
在一个示例性实施例中，方法还包括：通过第一链路接收中继控制设备发送的第二控制指令，其中，第二控制指令中包括第一链路处于信号传输状态的信息，第一链路连接第一设备和中继控制设备；响应第二控制指令，以控制DSP设备从中继控制设备处接收第一信号，并控制DSP设备对第一信号进行处理，得到第一处理信号，以及控制信号选通设备将第一处理信号传输至光发送器。在本实施例中，DSP设备处理的数据信号速率被设定为32Gbps，对应CXL协议标准速率。DSP设备需对传入的第一信号进行整形恢复后传输至信号选通设备。 本实施例通过DSP设备对第一信号进行整形恢复，可以实现整个链路数据信号的正常传输。
在一个示例性实施例中，方法还包括：通过第一链路接收中继控制设备发送的第三控制指令，其中，第三控制指令中第一链路处于空闲状态的信息，第一链路连接第一设备和中继控制设备；响应第三控制指令，以控制DSP设备从中继控制设备处接收第一信号，并控制DSP设备对第一信号进行噪声抑制处理，得到第二处理信号，以及控制信号选通设备从DSP设备处接收第二处理信号后将第二处理信号传输至光发送器。在本实施例中，MCU设备控制DSP设备处于噪声抑制状态，MCU设备控制信号选通设备传输经DSP设备抑制后的低噪声信号，以避免接收端将低幅值噪声信号识别为正常信号。本实施例在链路训练过程中和无数据传输时整个第一链路会进入空闲状态，此时仍有低幅值(小于20mV)噪声信号产生。将此低幅值噪声信号通过DSP设备，利用DSP设备内部数字电路对噪声进行抑制，之后再通过信号选通设备进行传输，可以降低接收端光互连设备将噪声信号识别为正常数据信号的概率。
在一个示例性实施例中，方法还包括：通过光发送器将从信号选通设备处接收到的信号进行光信号转换，并将转换后的光信号传输至第二设备。从而实现对信号的发送。
下面结合图5对本实施例进行详细说明，如图5所示，是本实施例中的CXL外部光互连接收端的流程图，具体包括以下步骤：
S501，光接收器接收到光信号后进行电光转换为电信号(对应于上述中的第二信号)后传入DSP和数据选通芯片；
S502，根据输入电信号幅值是否超过低噪声信号幅值水平进行状态判断；
S503，若输入DSP电信号幅值超过低噪声信号幅值水平，则MCU退出状态3(状态3包括控制数据选通芯片传输DSP抑制后的低噪声信号)；
S504，根据输入信号中是否有代表链路训练的字符序列和CXL中继控制中标识当前链路状态的寄存器值进行S505的状态判断；
S505-S506，若信号中有代表链路训练状态的字符序列且CXL中继控制设备中代表当前链路速率的寄存器不是16Gbps，则MCU进入状态2；MCU控制DSP芯片处于噪声抑制状态，降低其功耗；
S507，MCU控制数据选通芯片传输经CXL中继控制设备直接传入的数据信号；
S508，经数据选通芯片传入的电信号经CXL中继控制设备后继续传输；
S509，若输入DSP电信号幅值未超过低噪声信号幅值水平，则MCU保持状态3；
S510，MCU控制DSP芯片处于噪声抑制状态，MCU控制数据选通芯片传输经DSP芯片抑制后的低噪声信号；
S511，若信号中无代表链路训练的字符序列或有代表链路训练状态的字符序列但CXL中继控制设备中代表当前链路速率的寄存器对应16Gbps，则MCU进入状态1；
S512，MCU控制DSP处于正常数据传输状态，MCU控制数据选通芯片传输DSP 芯片处理后的数据信号。
在本实施例中，在初始上电和复位后MCU会控制DSP和数据信号选通芯片进入状态3，此时链路是处于空闲状态，仅有低幅值噪声信号。当开始链路训练或传输正常速率信号时才会退出状态3，并根据设定逻辑判断进入状态1还是状态2。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个非易失性可读存储介质(如ROM(Read-0nly Memory，只读存储器)/RAM(Random Access Memory，随机存取存储器)、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本申请各个实施例所述的方法。
在本实施例中还提供了一种控制信号传输的装置，该装置被配置为实现上述实施例及可选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件，和/或，硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
图6是根据本申请实施例的控制信号传输的装置的结构框图，如图6所示，该装置包括：
中继控制设备，中继控制设备通过第一链路与第一设备连接，其中，中继控制设备是支持开放式互连标准CXL协议的设备，在第一设备发送第一信号时，中继控制设备被配置为通过第一链路接收第一信号，并被配置为利用第一信号确定第一链路的链路状态；
MCU设备，MCU设备与中继控制设备连接，被配置为按照中继控制设备发送的控制指令，控制信号选通设备和DSP设备传输第一信号，其中，控制指令中包括第一链路的链路状态，信号选通设备和DSP设备均与MCU设备连接。
在一个示例性实施例中，装置还包括：光发送器，光发送器和信号选通设备连接，被配置为接收信号选通设备发送的第一信号，并被配置为对第一信号进行光信号转换，得到第一光信号，并被配置为将第一光信号传输至第二设备。
在一个示例性实施例中，装置还包括：光接收器，光接收器和第二设备连接，被配置为将从第二设备接收到的光信号进行电信号转换，得到第二信号，并被配置为将第二信号发送至DSP设备和信号选通设备。
在一个示例性实施例中，MCU设备还被配置为从DSP设备或信号选通设备处获取第二信号，并通过DSP设备和信号选通设备将第二信号传输至中继控制设备，其中，DSP设备被配置为按照MCU设备发送的之控制指令对第二信号进行处理，信号选通设备被配置为按照MCU发送的控制指令将处理后的第二信号发送至中继控制设备。
在本实施例中，如图6所示，中继控制设备、MCU设备、DSP设备、信号选 通设备、光发送器以及光接收器均设置在PCB(Printed Circuit Board，印制电路板)板中。PCB板可以是通过金手指或线缆与服务器主板或资源池底板连接的板卡，也可以是服务器主板或资源池底板本体，用以安装本实施例中所示的设备和部件并提供电链路。中继控制设备、MCU设备、DSP设备、信号选通设备、光发送器以及光接收器可以是可插拔光模块的形式、也可以为板载光模块的形式，也可以为与中继控制设备同一PCB板的共封装光模块的形式，用以实现信号选通处理和光电或电光的转换。
可选地，第一设备包括但不限于是CPU、GPU，通过第一链路与中继控制设备外部互联，第一链路是光纤链路。中继控制设备可以是支持开放式互连标准CXL协议的芯片设备，例如，包括但不限于是Switch芯片、Retimer芯片、FPGA芯片等，用以实现信号中继并支持接收端的检测。信号选通设备可以是数据信号选通芯片，包括但不限于是ASIC芯片、ARM芯片或FPGA芯片等，用以实现信号的选择通过，支持的信号速率覆盖CXL协议规定的信号速率。MCU设备可以控制信号选通设备传输经中继控制设备直接传入的数据信号。需要说明的是，DSP设备的数量可以是一个，也可以是多个，信号选通设备的数量可以是一个，也可以是多个；MCU设备、光接收器、光发送器的数量均是一个。
可选地，当第一设备通过第一链路发送第一信号时，中继控制设备将当前第一链路的状态信息传输给MCU设备，MCU设备控制DSP设备和信号选通设备进入对应状态，以将中继控制设备传入的信号传送到光发送器进行电光转换，最后经光纤向外传输。
可选地，当通过光纤链路接收信号时，MCU设备结合输入的第二信号和中继控制设备中标识当前数据链路状态的寄存器值进入对应状态，以将光接收器光电转换后的电信号经DSP设备和信号选通设备传入到CXL中继控制设备，最后经电链路传输到第一设备。
通过上述装置，由于中继控制设备是支持开放式互连标准CXL协议的设备，具备根据接收的第一设备发送的第一信号，识别出传输第一信号的第一链路的状态的能力。可以通过与MCU设备进行通信，向MCU设备发送控制指令，使得MCU设备进入对应的链路状态，控制第一信号的传输。从而可以实现对CXL协议规定的不同速率数据信号的传输。因此，可以解决相关技术中存在的无法实现设备之间通过光纤链路传输CXL协议所定义的数据信号的问题，达到实现设备之间通过光纤链路传输CXL协议所定义的数据信号的效果。
本申请的实施例还提供了一种控制信号传输的系统，控制信号传输的系统包括上述控制信号传输的装置。本实施例以具体实施例的方式对控制信号传输的系统说明，如图7所示，是本实施例控制信号传输的系统的系统结构框图，该系统包括两个控制信号传输装置之间进行信号传输的设备。例如，第一设备是CPU、第二设备是CPU/GPU内存硬盘、中继控制设备是CXL中继控制设备、信号选通设备是数据信号选通芯片、MCU设备是MCU、DSP设备是DSP。具体交互过程包括：
CPU将电信号通过第一链路传输至CXL中继控制设备，CXL中继控制设备根 据输入电信号判断第一链路的状态，若输入电信号传输速率为32Gpbs/s，则链路处于正常数据传输状态，CXL中继控制设备控制MCU进入状态1，MCU控制DSP处于正常数据传输状态，MCU控制数据选通芯片传输DSP芯片处理后的数据信号；若输入电信号为低于32Gbps/s速率的信号，则链路处于链路训练状态；CXL中继控制设备控制MCU进入状态2，MCU控制数据选通芯片传输经CXL中继控制设备直接传入的数据信号；若输入电信号幅值低于协议要求(20mV)，则链路处于空闲状态，CXL中继控制设备控制MCU进入状态3。MCU控制DSP芯片处于噪声抑制状态，MCU控制数据选通芯片传输经DSP芯片抑制后的低噪声信号，避免接收端将低幅值噪声信号识别为正常信号；经数据选通芯片传入的电信号经光发送器进行光电转换为光信号后经光纤传输至CPU/GPU内存硬盘对应的光接收器中。光接收器将光信号转换为电信号传输至DSP和数据信号选通芯片中。MCU从DSP或数据信号选通芯片中获取电信号，根据输入电信号幅值是否超过低噪声信号幅值水平进行状态判断；若输入DSP电信号幅值超过低噪声信号幅值水平，则MCU退出状态3；根据输入信号中是否有代表链路训练的字符序列和CXL中继控制中标识当前链路状态的寄存器值进行状态判断；若信号中有代表链路训练状态的字符序列且CXL中继控制设备中代表当前链路速率的寄存器不是16Gbps，则MCU进入状态2；MCU控制DSP芯片处于噪声抑制状态，降低其功耗。若输入DSP电信号幅值未超过低噪声信号幅值水平，则MCU保持状态3；MCU控制DSP芯片处于噪声抑制状态，MCU控制数据选通芯片传输经DSP芯片抑制后的低噪声信号。若信号中无代表链路训练的字符序列或有代表链路训练状态的字符序列但CXL中继控制设备中代表当前链路速率的寄存器对应16Gbps，则MCU进入状态1，MCU控制DSP处于正常数据传输状态，MCU控制数据选通芯片传输DSP芯片处理后的数据信号。
综上所述，本实施例利用数据信号选通芯片搭配DSP芯片实现对CXL协议规定的不同速率数据信号的传输，且能够实现对电路空闲状态时的低幅值噪声信号进行抑制。定义3种数据链路状态，通过MCU对DSP芯片和数据信号选通芯片的控制适配。本方法可以充分发挥DSP数字芯片在高速率信号传输时的优势及对低幅值噪声信号的抑制能力，又通过数据信号选通芯片实现了超出DSP芯片带宽的低速数据信号的传输。同时可以实现CXL外部光互连，有效拓展CXL协议外部传输距离，且集成形式较为灵活。可以实现CXL协议链路中高速率和低速率信号的传输，并且可以实现对低幅值噪声信号的抑制，以降低接收端误识别概率。本方案集成形式较为灵活，并且方便拓展，利于设备之间的外部互连。
需要说明的是，上述各个模块是可以通过软件或硬件来实现的，对于后者，可以通过以下方式实现，但不限于此：上述模块均位于同一处理器中；或者，上述各个模块以任意组合的形式分别位于不同的处理器中。
本申请的实施例还提供了一种计算机非易失性可读存储介质，该计算机非易失性可读存储介质中存储有计算机程序，其中，该计算机程序被设置为运行时执行上述任一项方法实施例中的步骤。
在一个示例性实施例中，上述计算机非易失性可读存储介质可以包括但不 限于：U盘、只读存储器(Read-Only Memory，简称为ROM)、随机存取存储器(Random Access Memory，简称为RAM)、移动硬盘、磁碟或者光盘等各种可以存储计算机程序的非易失性可读存储介质。
本申请的实施例还提供了一种电子设备，包括存储器和处理器，该存储器中存储有计算机程序，该处理器被设置为运行计算机程序以执行上述任一项方法实施例中的步骤。
在一个示例性实施例中，上述电子设备还可以包括传输设备以及输入输出设备，其中，该传输设备和上述处理器连接，该输入输出设备和上述处理器连接。
本实施例中的具体示例可以参考上述实施例及示例性实施方式中所描述的示例，本实施例在此不再赘述。
显然，本领域的技术人员应该明白，上述的本申请的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本申请不限制于任何特定的硬件和软件结合。
以上所述仅为本申请的可选实施例而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的原则之内，所作的任何修改、等同替换、改进等，均应包括在本申请的保护范围之内。

Claims (28)

  1. 一种控制信号传输的方法，其特征在于，应用于中继控制设备，包括：
    通过第一链路接收第一设备发送的第一信号，其中，所述第一链路连接所述第一设备和中继控制设备，所述中继控制设备是支持开放式互连标准CXL协议的设备，所述第一信号是电信号；
    利用所述第一信号确定所述第一链路的链路状态；
    基于所述第一链路的链路状态向微控制处理单元MCU设备发送控制指令，以通过所述MCU设备控制所述第一信号的传输，其中，所述MCU与所述中继控制设备连接。
  2. 根据权利要求1所述的方法，其特征在于，利用所述第一信号确定所述第一链路的链路状态，包括：
    在所述第一信号的信号传输速率小于第一预设速率的情况下，确定所述第一链路处于链路训练状态，所述第一预设速率是基于所述CXL协议的标准速率设定的。
  3. 根据权利要求2所述的方法，其特征在于，基于所述第一链路的链路状态向微控制处理单元MCU设备发送控制指令，以通过所述MCU设备控制所述第一信号的传输，包括：
    向所述MCU设备发送第一控制指令，以通过所述MCU设备控制信号选通设备从所述中继控制设备处接收所述第一信号，并控制所述信号选通设备将所述第一信号传输至光发送器，其中，所述第一控制指令中包括所述第一链路处于链路训练状态的信息。
  4. 根据权利要求1所述的方法，其特征在于，利用所述第一信号确定所述第一链路的链路状态，包括：
    在所述第一信号的信号传输速率等于第一预设速率的情况下，确定所述第一链路处于信号传输状态，其中，所述第一预设速率是基于所述CXL协议的标准速率设定的。
  5. 根据权利要求4所述的方法，其特征在于，基于所述第一链路的链路状态向微控制处理单元MCU设备发送控制指令，以通过所述MCU设备控制所述第一信号的传输，包括：
    向所述MCU设备发送第二控制指令，以通过所述MCU设备控制DSP设备从所述中继控制设备处接收所述第一信号，并控制所述DSP设备对所述第一信号进行处理，得到第一处理信号；并通过所述MCU设备控制信号选通设备从所述DSP设备处接收所述处理后的信号，并控制所述信号选通设备将所述第一处理信号传输至光发送器，其中，所述第二控制指令中包括所述第一链路处于信号传输状态的信息。
  6. 根据权利要求1所述的方法，其特征在于，所述第一链路的链路状态包括：所述第一信号的信号传输速率小于第一预设速率，所述第一信号的信号传输速率等于第一预设速率。
  7. 根据权利要求1所述的方法，其特征在于，所述通过所述MCU设备控制所述第一信号的传输，包括：通过所述MCU设备控制是否直接通过信号选通设备传输所述第一信号。
  8. 根据权利要求1所述的方法，其特征在于，所述第一链路的链路状态还包括所述第一信号的信号幅值小于第一预设幅值，利用所述第一信号确定所述第一链路的链路状态，包括：
    在所述第一信号的信号幅值小于第一预设幅值的情况下，确定所述第一链路处于空闲状态，其中，所述第一预设幅值是基于所述CXL协议的标准幅值设定的。
  9. 根据权利要求8所述的方法，其特征在于，基于所述第一链路的链路状态向微控制处理单元MCU设备发送控制指令，以通过所述MCU设备控制所述第一信号的传输，包括：
    向所述MCU设备发送第三控制指令，以通过所述MCU设备控制DSP设备从所述中继控制设备处接收所述第一信号，并控制所述DSP设备对所述第一信号进行噪声抑制处理，得到第二处理信号；并通过所述MCU设备控制信号选通设备从所述DSP设备处接收所述第二处理信号，并控制所述信号选通设备将所述第二处理信号传输至光发送器，其中，所述第三控制指令包括所述第一链路处于空闲状态的信息。
  10. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    通过信号选通设备将所述第一信号传输至光发送器；
    通过所述光发送器对所述第一信号进行光信号转换，得到第一光信号；
    通过所述光发送器将所述第一光信号传输至第二设备。
  11. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    接收信号选通设备发送的第二信号，其中，所述第二信号是电信号；
    对所述第二信号进行恢复处理，得到恢复信号；
    通过所述第一链路将所述恢复信号发送至所述第一设备。
  12. 一种控制信号传输的方法，其特征在于，应用于MCU设备，包括：
    获取第二设备发送的第二信号，其中，所述第二信号是光接收器将接收到的光信号进行电信号转换得到的，所述光信号是所述第二设备发送的；
    将所述第二信号传输至中继控制设备，其中，所述中继控制设备是支持开放式互连标准CXL协议的设备，所述中继控制设备被配置为对所述第二信号进行恢复处理后通过第一链路传输至第一设备。
  13. 根据权利要求12所述的方法，其特征在于，所述第一链路的链路状态包括：第一信号的信号传输速率小于第一预设速率，所述第一信号的信号传输速率等于第一预设速率，所述第一信号是电信号；
    所述中继控制设备还被配置为基于所述第一链路的链路状态向微控制处理单元MCU设备发送控制指令，以通过所述MCU设备控制是否直接通过信号选通设备传输所述第一信号，所述MCU设备与所述中继控制设备连接。
  14. 根据权利要求12所述的方法，其特征在于，获取第二设备发送的第二信号，包括：
    从DSP设备或者信号选通设备中获取所述第二信号，其中，所述第二信号是所述光接收器传输至所述DSP设备和所述信号选通设备的信号。
  15. 根据权利要求12所述的方法，其特征在于，将所述第二信号传输至中继控制设备，包括：
    在所述第二信号的信号幅值小于或等于第二预设幅值的情况下，向DSP设备发送第三控制指令，以控制所述DSP设备对所述第二信号进行噪声抑制处理，得到噪声抑制处理后的信号；
    向信号选通设备发送第四控制指令，以控制所述信号选通设备向所述中继控制设备传输所述噪声抑制处理后的信号。
  16. 根据权利要求12所述的方法，其特征在于，将所述第二信号传输至中继控制设备，包括：根据中继控制设备中代表链路状态的寄存器值，控制DSP设备向所述中继控制设备传输对所述第二信号进行噪声抑制处理后的信号。
  17. 根据权利要求12所述的方法，其特征在于，所述方法还包括：
    通过第一链路接收所述中继控制设备发送的第一控制指令，其中，所述第一控制指令中包括所述第一链路处于链路训练状态的信息，所述第一链路连接所述第一设备和中继控制设备，所述链路训练状态用于表示第一信号的信号传输速率小于第一预设速率；
    响应所述第一控制指令，以控制信号选通设备从所述中继控制设备处接收第一信号，并控制所述信号选通设备将所述第一信号传输至光发送器，其中，所述第一信号是所述中继控制设备通过所述第一链路从所述第一设备处接收的电信号。
  18. 根据权利要求12所述的方法，其特征在于，所述方法还包括：
    通过第一链路接收所述中继控制设备发送的第二控制指令，其中，所述第二控制指令中包括所述第一链路处于信号传输状态的信息，所述第一链路连接所述第一设备和中继控制设备，所述信号传输状态用于表示第一信号的信号传输速率等于第一预设速率；
    响应所述第二控制指令，以控制DSP设备从所述中继控制设备处接收第一信号，并控制所述DSP设备对所述第一信号进行处理，得到第一处理信号，以及控制信号选通设备将所述第一处理信号传输至光发送器。
  19. 根据权利要求12所述的方法，其特征在于，所述方法还包括：
    通过第一链路接收所述中继控制设备发送的第三控制指令，其中，所述第三控制指令中所述第一链路处于空闲状态的信息，所述第一链路连接所述第一设备和中继控制设备，所述空闲状态用于表示所述第一链路的链路状态中还包括的第一信号的信号幅值小于第一预设幅值；
    响应所述第三控制指令，以控制DSP设备从所述中继控制设备处接收第一信号，并控制所述DSP设备对所述第一信号进行噪声抑制处理，得到第二处理信号，以及控制信号选通设备从所述DSP设备处接收所述第二处理信号后将所述第二处理信号传输至光发送器。
  20. 根据权利要求17-19任一项所述的方法，其特征在于，所述方法 还包括：
    通过所述光发送器将从所述信号选通设备处接收到的信号进行光信号转换，并将转换后的光信号传输至所述第二设备。
  21. 一种控制信号传输的装置，其特征在于，包括：
    中继控制设备，所述中继控制设备通过第一链路与第一设备连接，其中，所述中继控制设备是支持开放式互连标准CXL协议的设备，在所述第一设备发送第一信号时，所述中继控制设备被配置为通过所述第一链路接收所述第一信号，并被配置为利用所述第一信号确定所述第一链路的链路状态；
    MCU设备，所述MCU设备与所述中继控制设备连接，被配置为按照所述中继控制设备发送的控制指令，控制信号选通设备和DSP设备传输所述第一信号，其中，所述控制指令中包括所述第一链路的链路状态，所述信号选通设备和所述DSP设备均与所述MCU设备连接。
  22. 根据权利要求21所述的装置，其特征在于，所述装置还包括：
    光发送器，所述光发送器和所述信号选通设备连接，被配置为接收所述信号选通设备发送的所述第一信号，并被配置为对所述第一信号进行光信号转换，得到第一光信号，并被配置为将所述第一光信号传输至第二设备。
  23. 根据权利要求21所述的装置，其特征在于，所述装置还包括：
    光接收器，所述光接收器和第二设备连接，被配置为将从所述第二设备接收到的光信号进行电信号转换，得到第二信号，并被配置为将所述第二信号发送至DSP设备和信号选通设备。
  24. 根据权利要求23所述的装置，其特征在于，所述MCU设备还被配置为从所述DSP设备或所述信号选通设备处获取所述第二信号，并通过所述DSP设备和所述信号选通设备将所述第二信号传输至所述中继控制设备，其中，所述DSP设备被配置为按照所述MCU设备发送的之控制指令对所述第二信号进行处理，所述信号选通设备被配置为按照所述MCU发送的控制指令将处理后的第二信号发送至中继控制设备。
  25. 根据权利要求23所述的装置，其特征在于，所述第一信号是电信号，所述第一链路的链路状态包括：所述第一信号的信号传输速率小于第一预设速率，所述第一信号的信号传输速率等于第一预设速率；MCU设备控制信号选通设备将所述第一信号传输至光发送器；通过所述光发送器对所述第一信号进行光信号转换，得到第一光信号；通过所述光发送器将所述第一光信号传输至第二设备。
  26. 一种控制信号传输的系统，其特征在于，所述控制信号传输的系统包括权利要求21至25任一项所述的控制信号传输的装置。
  27. 一种计算机非易失性可读存储介质，其特征在于，所述计算机非易失性可读存储介质中存储有计算机程序，其中，所述计算机程序被处理器执行时实现所述权利要求1至11任一项中所述的方法的步骤，或者实现权利要求12-20任一项中所述的方法的步骤。
  28. 一种电子设备，包括存储器、处理器以及存储在所述存储器上并可在所述处理器上运行的计算机程序，其特征在于，所述处理器执行所述计算 机程序时实现所述权利要求1至11任一项中所述的方法的步骤，或者实现权利要求12-20任一项中所述的方法的步骤。
PCT/CN2024/083113 2023-06-13 2024-03-21 控制信号传输的方法及装置、系统、存储介质、电子设备 Ceased WO2024255377A1 (zh)

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