WO2024255469A1 - 一种背接触电池及其制造方法、光伏组件 - Google Patents

一种背接触电池及其制造方法、光伏组件 Download PDF

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WO2024255469A1
WO2024255469A1 PCT/CN2024/090414 CN2024090414W WO2024255469A1 WO 2024255469 A1 WO2024255469 A1 WO 2024255469A1 CN 2024090414 W CN2024090414 W CN 2024090414W WO 2024255469 A1 WO2024255469 A1 WO 2024255469A1
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layer
equal
type doped
material layer
doped polysilicon
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English (en)
French (fr)
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王涛
於龙
童洪波
李华
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Taizhou Longi Solar Technology Co Ltd
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Taizhou Longi Solar Technology Co Ltd
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Priority to JP2025525739A priority Critical patent/JP2025536423A/ja
Priority to EP24822424.8A priority patent/EP4611047A4/en
Priority to AU2024303504A priority patent/AU2024303504B2/en
Publication of WO2024255469A1 publication Critical patent/WO2024255469A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
    • H10F10/146—Back-junction photovoltaic cells, e.g. having interdigitated base-emitter regions on the back side
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/129—Passivating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H10F77/219—Arrangements for electrodes of back-contact photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/30—Coatings
    • H10F77/306—Coatings for devices having potential barriers
    • H10F77/311—Coatings for devices having potential barriers for photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • H10F77/703—Surface textures, e.g. pyramid structures of the semiconductor bodies, e.g. textured active layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/546—Polycrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the field of photovoltaic technology, and in particular to a back-contact cell and a method for manufacturing the same, and a photovoltaic module.
  • Tunneling passivated back contact solar cells refer to solar cells with positive and negative electrodes on the back of the cell, no metal electrode blocking the front, and with tunneling passivated contact structures. Passivated back contact solar cells have advantages such as large light absorption area and low carrier back recombination rate, which have attracted extensive attention from the photovoltaic academic and industrial circles and become a hot development direction of high-efficiency solar cell technology.
  • the morphology of the N-type doped polysilicon layer containing phosphorus as the doping element is poor, resulting in poor working performance of the tunneling passivated back-contact solar cell.
  • the purpose of the present application is to provide a back contact cell and a method for manufacturing the same, and a photovoltaic module.
  • this application involves the following aspects:
  • the present application discloses a back-contact battery, which includes: a semiconductor substrate, the semiconductor substrate having a first surface and a second surface arranged opposite to each other, the first surface having a velvet structure, and a tunneling passivation layer and an N-type doped polysilicon layer stacked in sequence on a local area of the second surface along a thickness direction of the semiconductor substrate.
  • the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge area of the second surface to the portion of the N-type doped polysilicon layer located on the central area of the second surface is greater than or equal to 1 and less than or equal to 1.2.
  • the tunnel passivation contact structure composed of the above tunnel passivation layer and the N-type doped polysilicon layer can achieve excellent interface passivation and carrier selective collection, which is beneficial to improve the photoelectric conversion efficiency of the back contact battery.
  • the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge region of the second surface to the portion of the N-type doped polysilicon layer located on the central region of the second surface in the present application is greater than or equal to 1 and less than or equal to 1.2, and at this time, the difference between the thickness of the edge portion and the thickness of the central portion of the N-type doped polysilicon layer is small.
  • a tunneling passivation material layer and an intrinsic amorphous silicon material layer used to manufacture a tunneling passivation layer and an N-type doped polysilicon layer are usually formed by processes such as chemical vapor deposition. Based on this, when the difference between the thickness of the edge portion and the thickness of the central portion of the N-type doped polysilicon layer is small, the difference between the thickness of the edge portion and the thickness of the central portion of the intrinsic amorphous silicon material layer forming the N-type doped polysilicon layer is also small.
  • the chemical dosage ratio of the intrinsic amorphous silicon material located on the edge area of the second surface and the intrinsic amorphous silicon material located on the central area of the second surface are roughly the same. Therefore, when the thickness difference between the edge portion and the central portion of the intrinsic amorphous silicon material layer is small, the structural density of the edge portion and the central portion of the intrinsic amorphous silicon material layer is less different.
  • the density of the edge portion of the phosphosilicate glass layer obtained by the reaction of silicon in the intrinsic amorphous silicon material layer with oxygen in the diffusion environment is also slightly different from the density of its central portion, so that the edge portion of the phosphosilicate glass layer has a high corrosion resistance that is roughly the same as that of its central portion.
  • the phosphosilicate glass layer can well protect the portion of the N-type doped polycrystalline silicon material layer located therebelow for forming the N-type doped polycrystalline silicon layer, so that the morphology and formation range of the obtained N-type doped polycrystalline silicon layer meet the target requirements, which is beneficial to the collection of carriers, reduces reverse leakage, and further helps to improve the photoelectric conversion efficiency of the back contact battery.
  • the size uniformity of the suede structure in each area of the first surface is greater than or equal to 85% and less than 100%.
  • the velvet surface on each area of the first surface has a high size uniformity, which is conducive to making each area of the first surface have a high light transmittance, so that more light can be transmitted through the first surface into the semiconductor substrate, further improving the photoelectric conversion efficiency of the back contact battery.
  • the area on the second surface where the tunnel passivation layer and the N-type doped polysilicon layer are not stacked is a polished surface or has a suede structure.
  • the thickness of a portion of the N-type doped polysilicon layer located on the edge region of the second surface is greater than or equal to 175 nm and less than or equal to 225 nm.
  • the thickness of the portion of the N-type doped polysilicon layer located on the edge region of the second surface is within the above range, which can prevent the overall thickness of the N-type doped polysilicon layer from being too small and not meeting the target requirements due to the above thickness value being too small, and prevent the difficulty in manufacturing the N-type doped polysilicon layer with high thickness uniformity, which is conducive to obtaining a back contact battery.
  • the corrosion resistance of the phosphorus silicon glass layer located on the edge portion of the N-type doped polysilicon material layer after the phosphorus diffusion treatment from being poor due to the above thickness value being too large, ensuring that the phosphorus silicon glass layer can well include the various portions of the N-type doped polysilicon material layer used to form the N-type doped polysilicon layer during the texturing process, ensuring that the N-type doped polysilicon layer has a good morphology and a formation range that meets the target requirements.
  • the thickness of the portion of the N-type doped polysilicon layer located in the central area of the second surface is greater than or equal to 150 nm and less than or equal to 200 nm.
  • the average doping concentration of impurities in the N-type doped polysilicon layer is greater than or equal to 3.5 ⁇ 10 20 /cm 3 and less than or equal to 4.0 ⁇ 10 20 /cm 3 .
  • the average doping concentration of impurities in the N-type doped polysilicon layer is within the above range, and the impurity doping concentration in the N-type doped polysilicon layer in the present application can be appropriately reduced compared with the N-type doped polysilicon layer in the related art (the average doping concentration of impurities in the N-type doped polysilicon layer is greater than 5.0 ⁇ 10 20 /cm 3 ) under the premise of ensuring that the N-type doped polysilicon layer has excellent carrier selective collection effect and does not affect the contact resistance between the N-type doped polysilicon layer and the negative electrode.
  • the average doping concentration of impurities in the N-type doped polysilicon material layer used to manufacture the N-type doped polysilicon layer is also low.
  • the average doping concentration of impurities in the N-type doped polysilicon material layer after phosphorus diffusion treatment is proportional to the average doping concentration of impurities in the phosphorus silicon glass layer formed on itself, so appropriately reducing the impurity doping concentration in the N-type doped polysilicon layer also means that the average doping concentration of impurities (the impurities include phosphorus) in the phosphorus silicon glass layer is reduced.
  • the phosphorus doping concentration in the phosphosilicate glass layer is inversely proportional to its own corrosion resistance, appropriately reducing the phosphorus doping concentration in the phosphosilicate glass layer can also improve its own corrosion resistance, further ensuring that the N-type doped polysilicon layer has a good morphology and a formation range that meets the target requirements.
  • the present application further discloses a photovoltaic module, which includes a back-contact cell provided by the first aspect and various implementations thereof.
  • beneficial effects of the second aspect of the present application can be analyzed by referring to the beneficial effects of the first aspect and its various implementation methods, and will not be repeated here.
  • the present application also discloses a method for manufacturing a back-contact battery, which comprises: first, providing a semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface arranged opposite to each other. Next, along the thickness direction of the semiconductor substrate, a tunnel passivation material layer and an intrinsic amorphous silicon material layer are sequentially formed on one side of the second surface of the semiconductor substrate in a stacked manner. Next, the intrinsic amorphous silicon material layer is subjected to phosphorus diffusion treatment so that the intrinsic amorphous silicon material layer forms an N-type doped polycrystalline silicon material layer, and a phosphosilicate glass layer is formed on the N-type doped polycrystalline silicon material layer.
  • the thickness ratio of the portion of the N-type doped polycrystalline silicon material layer located on the edge area of the second surface to the portion of the N-type doped polycrystalline silicon material layer located on the central area of the second surface is greater than or equal to 1 and less than or equal to 1.2.
  • the first surface of the semiconductor substrate is subjected to a texturing treatment so that the first surface forms a velvet structure.
  • the phosphosilicate glass layer, the stacked tunnel passivation material layer and the N-type doped polysilicon material layer are patterned to form a tunnel passivation layer and an N-type doped polysilicon layer stacked on a local area of the second surface.
  • the remaining phosphosilicate glass layer is removed.
  • beneficial effects of the third aspect of the present application can be analyzed by referring to the beneficial effects of the first aspect and its various implementation methods, and will not be repeated here.
  • the ambient pressure for forming the intrinsic amorphous silicon material layer is greater than or equal to 100 mTorr and less than or equal to 150 mTorr.
  • the environmental pressure for forming the intrinsic amorphous silicon material layer is within the above range, which can prevent the edge portion of the intrinsic amorphous silicon material layer from having a large thickness due to the high environmental pressure, ensure that the thickness difference between the edge portion and the central portion of the intrinsic amorphous silicon material layer is small, ensure that the structure of the edge portion of the intrinsic amorphous silicon material layer is as dense as the structure of its central portion, and thus make the phosphorus silicon glass layer formed after the phosphorus diffusion treatment have high corrosion resistance in all parts parallel to the second surface direction, and ensure that the morphology and formation range of the formed N-type doped polysilicon meet the target requirements. At the same time, it can also prevent the process efficiency from being low due to low environmental pressure.
  • reducing the gas flow rate can reduce the total gas flow rate in the diffusion device, thereby reducing the disturbance caused by the gas flow in the diffusion device, which is beneficial to optimizing the deposition quality of the portion of the intrinsic amorphous silicon material layer located on the edge region of the second surface, ensuring that the structure of the edge portion of the intrinsic amorphous silicon material layer is as dense as the structure of its central portion, thereby making the phosphorus silicon glass layer formed after the phosphorus diffusion treatment have high corrosion resistance in all portions parallel to the second surface, ensuring that the morphology and formation range of the formed N-type doped polysilicon meet the target requirements. At the same time, it can also prevent the process efficiency from being low due to a small gas flow rate.
  • a wrap-around amorphous silicon layer is formed on the side and part of the first surface of the semiconductor substrate.
  • the width of the formation area of the wrap-around amorphous silicon layer on the first surface is greater than or equal to 0 and less than 10 mm.
  • the width direction of the formation area is parallel to the radial direction of the semiconductor substrate.
  • the wrap-around amorphous silicon layer forms a wrap-around doped layer, and a wrap-around phosphosilicate glass layer is formed on the wrap-around doped layer.
  • the manufacturing method of the back contact battery also includes: removing the wrap-around phosphosilicate glass layer and the wrap-around doped layer.
  • the phosphorus-silicate glass layer and the doped layer formed by the winding plating need to be removed in sequence, and the etching solution for removing the doped layer will also The surface of the portion of the first surface of the semiconductor substrate covered by the wrap-plated doping layer is affected, so that a porous structure is formed on the surface of this portion, while the surface of the central area of the first surface of the semiconductor substrate that is not covered by the wrap-plated doping layer is relatively flat, resulting in inconsistent sizes of the velvet structures located on the edge area and the central area of the first surface after subsequent velveting treatment, thereby affecting the light trapping effect of the first surface.
  • the thickness of the phosphosilicate glass layer is greater than or equal to 60 nm and less than or equal to 65 nm.
  • the thickness of the phosphosilicate glass layer is within the above range, which can prevent the poor corrosion resistance of the phosphosilicate glass layer due to the small thickness of the phosphosilicate glass layer, and ensure that the morphology and formation range of the formed N-type doped polysilicon layer meet the target requirements. At the same time, it can also prevent the large amount of consumables used in manufacturing the intrinsic amorphous silicon material layer and the phosphosilicate glass layer due to the large thickness of the phosphosilicate glass layer, which is conducive to controlling the manufacturing cost of the back contact battery.
  • the average thickness of the intrinsic amorphous silicon material layer is H1
  • the average thickness of the phosphosilicate glass layer is H2
  • the average thickness of the N-type doped polysilicon material layer is H3, and 40% H2 ⁇ H1-H3 ⁇ 60% H2.
  • the processing conditions of the phosphorus diffusion treatment are:
  • the deposition process temperature is greater than or equal to 850°C and less than or equal to 900°C. And/or, the deposition process environment pressure is greater than or equal to 150mbar and less than or equal to 200mbar. And/or, the deposition process phosphorus source pressure is greater than or equal to 250mbar and less than or equal to 450mbar. And/or, the deposition process nitrogen flow rate is greater than or equal to 1500sccm and less than or equal to 2000sccm. And/or, the deposition process oxygen flow rate is greater than or equal to 750sccm and less than or equal to 1000sccm. And/or, the post-oxidation process temperature is greater than or equal to 850°C and less than or equal to 900°C. And/or, the post-oxidation process oxygen flow rate is greater than or equal to 5000sccm and less than or equal to 10000sccm.
  • the deposition process temperature, deposition process environmental pressure, deposition process phosphorus source pressure, deposition process nitrogen flow rate and deposition process oxygen flow rate during the above phosphorus diffusion treatment are changed, and the average doping concentration of impurities in the formed phosphorus silicon glass layer and the N-type doped polysilicon material can be regulated.
  • the average doping concentration of phosphorus in the phosphorus silicon glass layer can be appropriately reduced, so that the phosphorus silicon glass layer has a higher corrosion resistance, thereby ensuring that the N-type doped polysilicon layer formed based on the N-type doped polysilicon material layer has a good morphology and meets the target requirements. Formation range.
  • changing the post-oxidation process temperature and the post-oxidation process oxygen flow rate during the phosphorus diffusion treatment can regulate the thickness of the formed phosphorus silicon glass layer.
  • FIG2 is a schematic diagram of the SEM morphology of a portion of an N-type doped polysilicon layer formed in the related art and located on an edge region of the second surface;
  • FIG. 3 is a schematic diagram of the SEM morphology of a portion of the N-type doped polysilicon layer located on the edge region of the second surface in an embodiment of the present application;
  • FIG5 is a second schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;
  • FIG6 is a third schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;
  • FIG7 is a fourth schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;
  • FIG8 is a fifth schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;
  • FIG9 is a sixth schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;
  • FIG10 is a seventh schematic longitudinal cross-sectional view of the structure of the back-contact battery during the manufacturing process provided in an embodiment of the present application.
  • FIG. 11 is a semiconductor substrate
  • 12 is a tunneling passivation material layer
  • 13 is an intrinsic amorphous silicon material layer
  • 14 is a plated amorphous silicon layer
  • 15 is an N-type doped polysilicon material layer
  • 16 is a phosphosilicate glass layer
  • 17 is a plated doped layer
  • 18 is a plated phosphosilicate glass layer
  • 19 is a velvet surface
  • 20 is a tunneling passivation layer
  • 21 is an N-type doped polysilicon layer
  • 22 is a positive electrode
  • 23 is a negative electrode.
  • Tunneling passivated back contact solar cells refer to solar cells where both the positive and negative electrodes are located on the back of the cell.
  • the tunneling passivation back-contact solar cell in the related art usually includes at least a semiconductor substrate, and a tunneling passivation layer and an N-type doped polysilicon layer stacked in sequence on a local area of the backlight surface of the semiconductor substrate along the thickness direction of the semiconductor substrate.
  • the intrinsic amorphous silicon material layer will be subjected to phosphorus diffusion treatment, so that the intrinsic amorphous silicon material layer forms an N-type doped polysilicon material layer, and a phosphorus silicon glass layer is formed on the N-type doped polysilicon material layer.
  • the phosphosilicate glass layer formed in the phosphorus diffusion process is directly used as a mask layer to protect the N-type doped polysilicon layer. There is no need to form other additional mask layers to protect the N-type doped polysilicon layer, so as to simplify the process steps of the tunnel passivation back-contact solar cell and improve the process efficiency.
  • the thickness of the edge portion of the intrinsic amorphous silicon material layer formed by the relevant manufacturing method is relatively large, and the thickness of the central portion thereof is relatively small; and the thickness difference between the edge portion and the middle portion of the intrinsic amorphous silicon material layer is relatively large (the thickness ratio between the two is generally greater than 1.3).
  • the chemical dosage ratio of the intrinsic amorphous silicon material located at the edge region of the backlight surface and the intrinsic amorphous silicon material located at the central region of the backlight surface is substantially the same, so when the thickness difference between the edge portion and the central portion of the intrinsic amorphous silicon material layer is relatively large, the structure of the edge portion of the intrinsic amorphous silicon material layer is more loose.
  • the formation of the phosphosilicate glass layer consumes the silicon element in the intrinsic amorphous silicon material layer and reacts it with the oxygen in the diffusion environment.
  • the formation quality of the phosphosilicate glass layer on the edge portion of the intrinsic amorphous silicon material layer is also poor, resulting in poor corrosion resistance of the phosphosilicate glass layer in this portion, which makes it difficult for the phosphosilicate glass layer to well protect the N-type doped polysilicon material layer underneath during the texturing treatment.
  • the N-type doped polysilicon layer formed based on the N-type doped polysilicon material layer has a poor morphology and a small formation range in the edge region, which is not conducive to the collection of carriers, resulting in poor working performance of the tunneling passivated back-contact solar cell.
  • the embodiment of the present application provides a back contact battery.
  • the back contact battery includes: a semiconductor substrate 11, the semiconductor substrate 11 has a first surface and a second surface arranged oppositely, and the first surface has a velvet structure; and a tunneling passivation layer 20 and an N-type doped polysilicon layer 21 are sequentially stacked on a local area of the second surface along the thickness direction of the semiconductor substrate 11.
  • the doping elements in the N-type doped polysilicon layer 21 include phosphorus, and the thickness ratio of the portion of the N-type doped polysilicon layer 21 located on the edge area of the second surface to the portion of the N-type doped polysilicon layer 21 located on the central area of the second surface is greater than or equal to 1 and less than or equal to 1.2.
  • the second surface is the backlight surface.
  • the first surface of the semiconductor substrate 11 is the light-facing surface
  • the second surface is the light-facing surface.
  • the material of the semiconductor substrate may be semiconductor materials such as silicon, silicon germanium or germanium.
  • the semiconductor substrate may be an N-type semiconductor substrate or a P-type semiconductor substrate.
  • the specific structure of the semiconductor substrate can be determined according to the conductivity type of the semiconductor substrate and the actual application scenario.
  • the backlight surface of the semiconductor substrate has a P-type region that is alternately spaced with the stacked tunneling passivation layer and the N-type doped polysilicon layer.
  • the P-type region is the back surface field of the back contact battery.
  • the back surface field in the back contact battery provided in the embodiment of the present application is a region possessed by the P-type semiconductor substrate, and there is no need to perform additional doping treatment to form the back surface field, thereby simplifying the process steps of the back contact battery and improving the process efficiency.
  • a P-type doped region may also be formed on a local area of the backlight surface of the semiconductor substrate.
  • the doped regions are alternately distributed with the stacked tunnel passivation layer and the N-type doped polysilicon layer.
  • a P-type doped region is formed in a local area of the backlight surface of the semiconductor substrate or on a local area of the backlight surface.
  • the P-type doped region and the stacked tunnel passivation layer and the N-type doped polysilicon layer are alternately distributed.
  • the light-facing surface of the semiconductor substrate is a velvet surface.
  • the side surface of the semiconductor substrate can be a polished surface or a velvet surface.
  • the surface of the area of the semiconductor substrate that is not covered by the stacked tunnel passivation layer and the N-type doped polysilicon layer can be a velvet surface or a polished surface.
  • the material and thickness of the tunnel passivation layer can be set according to actual needs, and are not specifically limited here.
  • the material of the tunnel passivation layer may include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium nitride carbide.
  • the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge region of the backlight surface to the portion of the N-type doped polysilicon layer located on the central region of the backlight surface may be any value greater than or equal to 1 and less than or equal to 1.2.
  • the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge region of the backlight surface to the portion of the N-type doped polysilicon layer located on the central region of the backlight surface may be 1, 1.12, 1.14, 1.16, 1.18 or 1.2, etc.
  • the tunneling passivation contact structure composed of the above tunneling passivation layer and the N-type doped polysilicon layer can achieve excellent interface passivation and carrier selective collection, which is beneficial to improve the photoelectric conversion efficiency of the back contact battery.
  • the thickness ratio of the edge portion to the middle portion of the N-type doped polysilicon layer is greater than 1.3
  • the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge area of the backlight surface to the portion of the N-type doped polysilicon layer located on the central area of the backlight surface in the embodiment of the present application is greater than or equal to 1 and less than or equal to 1.2.
  • the difference between the thickness of the edge portion of the N-type doped polysilicon layer 21 and the thickness of the central portion is small.
  • a tunneling passivation material layer 12 and an intrinsic amorphous silicon material layer 13 for manufacturing a tunneling passivation layer and an N-type doped polysilicon layer are usually formed by chemical vapor deposition and other processes. Based on this, when the difference between the thickness of the edge portion and the thickness of the central portion of the N-type doped polysilicon layer is small, the difference between the thickness of the edge portion and the thickness of the central portion of the intrinsic amorphous silicon material layer 13 forming the N-type doped polysilicon layer is also small.
  • the portions of the intrinsic amorphous silicon material layer 13 parallel to the backlight surface are formed simultaneously, and the chemical dosage ratio of the intrinsic amorphous silicon material located on the edge area of the backlight surface is roughly the same as that of the intrinsic amorphous silicon material located on the center area of the backlight surface. Therefore, when the thickness difference between the edge portion and the center portion of the intrinsic amorphous silicon material layer 13 is small, the structural density of the edge portion and the center portion of the intrinsic amorphous silicon material layer 13 is slightly different (see Figure 3).
  • the density of the edge portion of the phosphosilicate glass layer 16 obtained by the reaction of silicon in the intrinsic amorphous silicon material layer 13 with oxygen in the diffusion environment is also slightly different from the density of the central portion thereof, so that the edge portion of the phosphosilicate glass layer 16 has a high corrosion resistance substantially the same as that of the central portion thereof, so that in the process of texturing at least the light-facing surface of the semiconductor substrate 11, the phosphosilicate glass layer 16 can well protect the portion of the N-type doped polycrystalline silicon material layer 15 located therebelow for forming the N-type doped polycrystalline silicon layer 21 (see FIGS. 7 and 8 ), so that the morphology and formation range of the obtained N-type doped polycrystalline silicon layer 21 meet the target requirements, facilitate the collection of carriers, reduce reverse leakage, and further help improve the photoelectric conversion efficiency of the back contact battery.
  • the thickness ratio of the portion of the N-type doped polysilicon layer located on the edge area of the backlight surface to the portion of the N-type doped polysilicon layer located on the central area of the backlight surface will affect the corrosion resistance of the phosphorus silicon glass layer formed after the phosphorus diffusion treatment, and further affect its own morphology and its own formation range on the backlight side.
  • the specific thickness of each portion of the N-type doped polysilicon layer can be determined according to the requirements for the morphology of the N-type doped polysilicon layer and the formation range on the backlight side in the actual application scenario, as long as it can be applied to the back contact battery provided in the embodiment of the present application.
  • the thickness of the portion of the N-type doped polysilicon layer 21 located on the edge region of the backlight surface may be greater than or equal to 175 nm and less than or equal to 225 nm.
  • the thickness of the portion of the N-type doped polysilicon layer 21 located on the edge region of the backlight surface may be 175 nm, 185 nm, 195 nm, 205 nm, 215 nm or 225 nm, etc.
  • the thickness of the portion of the N-type doped polysilicon layer 21 located on the edge region of the backlight surface is within the above range, which can prevent the overall thickness of the N-type doped polysilicon layer 21 from being too small and not meeting the target requirements due to the small thickness value, and prevent the difficulty in manufacturing the N-type doped polysilicon layer 21 with high thickness uniformity, thereby facilitating the acquisition of a back-contact battery.
  • the phosphosilicate glass layer can well include various parts of the N-type doped polysilicon material layer used to form the N-type doped polysilicon layer 21, ensuring that the N-type doped polysilicon layer 21 has a good morphology and a formation range that meets the target requirements.
  • the thickness of the portion of the N-type doped polysilicon layer 21 located in the central area of the backlight surface may be greater than or equal to 150 nm and less than or equal to 200 nm.
  • the thickness of the portion of the N-type doped polysilicon layer 21 located in the central area of the backlight surface may be 150 nm, 160 nm, 170 nm, 180 nm, 190 nm or 200 nm, etc.
  • the N-type doped polysilicon layer may be doped with only one N-type impurity, phosphorus, or may be doped with N-type impurities, such as nitrogen or arsenic.
  • the doping concentration of the impurities in the N-type doped polysilicon layer it can be set according to actual needs and is not specifically limited here.
  • the average doping concentration of impurities in the N-type doped polysilicon layer may be greater than or equal to 3.5 ⁇ 10 20 /cm 3 and less than or equal to 4.0 ⁇ 10 20 /cm 3.
  • the average doping concentration of impurities in the N-type doped polysilicon layer may be 3.5 ⁇ 10 20 /cm 3 , 3.6 ⁇ 10 20 /cm 3 , 3.7 ⁇ 10 20 /cm 3 , 3.8 ⁇ 10 20 /cm 3 , 3.9 ⁇ 10 20 /cm 3 or 4.0 ⁇ 10 20 /cm 3 , etc.
  • the average doping concentration of impurities in the N-type doped polysilicon layer is within the above range, and the impurity doping concentration in the N-type doped polysilicon layer in the embodiment of the present application can be appropriately reduced compared to the N-type doped polysilicon layer in the related art (the average doping concentration of impurities in the N-type doped polysilicon layer is greater than 5.0 ⁇ 10 20 /cm 3 ) under the premise of ensuring that the N-type doped polysilicon layer has excellent carrier selective collection effect and does not affect the contact resistance between the N-type doped polysilicon layer and the negative electrode.
  • the average doping concentration of impurities in the N-type doped polysilicon material layer used to manufacture the N-type doped polysilicon layer is also low.
  • the average doping concentration of impurities in the N-type doped polysilicon material layer after the phosphorus diffusion treatment is proportional to the average doping concentration of impurities in the phosphorus silicon glass layer formed on itself, so appropriately reducing the impurity doping concentration in the N-type doped polysilicon layer also means that the average doping concentration of impurities (the impurities include phosphorus) in the phosphorus silicon glass layer is reduced.
  • the phosphorus doping concentration in the phosphosilicate glass layer is inversely proportional to its own corrosion resistance, appropriately reducing the phosphorus doping concentration in the phosphosilicate glass layer can also improve its own corrosion resistance, further ensuring that the N-type doped polysilicon layer has a good morphology and a formation range that meets the target requirements.
  • a doped layer and a phosphorus-silicon glass layer are formed on the side and part of the light-facing surface of the semiconductor substrate due to the wrap-around plating.
  • the phosphosilicon glass layer and the doped layer are removed, and the etching solution for removing the doped layer will also affect the surface of the portion of the semiconductor substrate facing the light that is covered by the doped layer, so that a porous structure is formed on the surface of this portion, while the surface of the central area of the semiconductor substrate facing the light that is not covered by the doped layer is relatively flat, resulting in inconsistent sizes of the velvet structures on the edge area and the central area of the light-facing surface after subsequent velvet treatment, thereby affecting the light trapping effect of the light-facing surface.
  • the size uniformity of the velvet structures on each area of the light-facing surface can be determined based on the formation of the N-type doped polysilicon layer, which is not specifically limited here.
  • the size uniformity of the velvet structure on each area of the light-facing surface is greater than or equal to 85% and less than 100%.
  • the specific value of the size uniformity of the velvet structure on each area of the light-facing surface can be determined according to the actual manufacturing process and is not specifically limited here.
  • the velvet on each area of the light-facing surface has a high size uniformity, which is conducive to making each area of the light-facing surface have a high light transmittance, so that more light can be transmitted through the light-facing surface into the semiconductor substrate 11, further improving the photoelectric conversion efficiency of the back contact battery.
  • the back contact cell provided in the embodiment of the present application may further include a positive electrode 22 and a negative electrode 23.
  • the positive electrode 22 is in ohmic contact with the P-type region of the semiconductor substrate 11.
  • the negative electrode 23 is in ohmic contact with the N-type doped polysilicon layer 21.
  • the materials of the positive electrode 22 and the negative electrode 23 may be conductive materials such as copper, aluminum or silver.
  • an embodiment of the present application further provides a photovoltaic module, which includes a back-contact cell provided by the first aspect and various implementations thereof.
  • beneficial effects of the second aspect in the embodiments of the present application can be analyzed by referring to the beneficial effects of the first aspect and its various implementation methods, and will not be repeated here.
  • the present application also provides a method for manufacturing a back-contact battery.
  • the manufacturing process will be described below based on the cross-sectional views of the operations shown in FIG. 4 to FIG. 10 .
  • the manufacturing method of the back contact battery includes: first, providing a semiconductor substrate. Next, as shown in FIG4, a tunnel passivation material layer 12 and an intrinsic amorphous silicon material layer 13 are sequentially formed in a stacked manner on the backlight side of the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11. Next, as shown in FIG5, the intrinsic amorphous silicon material layer is subjected to phosphorus diffusion treatment to form an N-type doped polysilicon material layer 15 in the intrinsic amorphous silicon material layer, and a phosphorus silicon glass layer 16 is formed on the N-type doped polysilicon material layer 15. The above-mentioned N-type doped polysilicon material layer 15 is located on the central area of the backlight side.
  • the thickness ratio of the part is greater than or equal to 1 and less than or equal to 1.2.
  • the light-facing surface of the semiconductor substrate 11 is subjected to a texturing treatment so that a velvet surface 19 is formed on the light-facing surface.
  • the phosphosilicate glass layer 16, and the stacked tunneling passivation material layer and the N-type doped polysilicon material layer are patterned to form a tunneling passivation layer 20 and an N-type doped polysilicon layer 21 stacked on a local area of the backlight surface.
  • the remaining phosphosilicate glass layer is removed.
  • the specific structure, conductivity type and material of the above-mentioned semiconductor substrate can refer to the above text, and will not be repeated here.
  • the tunnel passivation material layer and the intrinsic amorphous silicon material layer can be formed by chemical vapor deposition and other processes. Among them, the material and thickness of the tunnel passivation material layer can refer to the above text.
  • the intrinsic amorphous silicon material layer the intrinsic amorphous silicon material layer is used to manufacture the N-type doped polycrystalline silicon layer included in the back contact battery.
  • the phosphorus silicon glass layer formed after the phosphorus diffusion treatment needs to consume part of the silicon in the intrinsic amorphous silicon material layer, resulting in a reduction in the thickness of the N-type polycrystalline silicon material layer formed based on the intrinsic amorphous silicon material layer after the phosphorus diffusion treatment.
  • the thickness of each part of the intrinsic amorphous silicon material layer can be determined according to the thickness of each part of the N-type doped polycrystalline silicon material layer and the phosphorus silicon glass layer, and the thickness ratio of the intrinsic amorphous silicon material required to form the phosphorus silicon glass layer of the corresponding thickness.
  • the average thickness of the intrinsic amorphous silicon material layer is H1
  • the average thickness of the phosphosilicate glass layer is H2
  • the average thickness of the N-type doped polysilicon material layer is H3, 40% H2 ⁇ H1-H3 ⁇ 60% H2.
  • the average thickness of the intrinsic amorphous silicon material layer, the phosphosilicate glass layer and the N-type doped polysilicon material layer meets the above conditions, indicating that the thickness of the intrinsic amorphous silicon material layer is appropriate, and the density of each region of the intrinsic amorphous silicon material layer along the direction parallel to the backlight surface and the uniformity of the structural density are both high, which is conducive to the consumption thickness of the N-type doped polysilicon material layer after the formation of the phosphosilicate glass layer to meet the theoretical consumption of the N-type doped polysilicon material layer with higher density (that is, the thickness of the phosphosilicate glass layer is approximately equal to half of the reduction in the thickness of the N-type doped polysilicon material layer) or the difference with the above theoretical consumption is small, which further indicates that the formation quality of the optimized phosphosilicate glass layer is high, ensuring that the formed N-type doped polysilicon layer has a good morphology and meets the formation range required by the target.
  • the N-type doped polysilicon material layer formed based on the intrinsic amorphous silicon material layer is located at The thickness ratio of the portion on the edge area of the backlight surface to the portion located on the central area of the backlight surface is greater than or equal to 1 and less than or equal to 1.2, and accordingly, the thickness ratio of the portion of the intrinsic amorphous silicon material layer located on the edge area of the backlight surface to the portion located on the central area of the backlight surface also satisfies that it is greater than or equal to 1 and less than or equal to 1.2.
  • the thickness of the corresponding area of the intrinsic amorphous silicon material layer can be controlled by adjusting any parameters that can affect the formation thickness of different areas of the intrinsic amorphous silicon material layer, such as the ambient pressure and gas flow rate during the formation of the intrinsic amorphous silicon material layer.
  • the specific parameter values that affect the formation thickness of different areas of the intrinsic amorphous silicon material layer can be determined according to the specific formation thickness of different areas of the intrinsic amorphous silicon material layer, as long as it can be applied to the manufacturing method of the back contact battery provided in the embodiment of the present application.
  • the ambient pressure for forming the intrinsic amorphous silicon material layer may be greater than or equal to 100 mTorr and less than or equal to 150 mTorr.
  • the ambient pressure for forming the intrinsic amorphous silicon material layer may be 100 mTorr, 110 mTorr, 120 mTorr, 130 mTorr, 140 mTorr or 150 mTorr, etc.
  • reducing the ambient pressure can increase the molecular free path, allowing the reactive molecular groups to reach various areas of the surface of the tunnel passivation material layer faster, rather than gathering at the same location.
  • the environmental pressure for forming the intrinsic amorphous silicon material layer is within the above range, which can prevent the edge portion of the intrinsic amorphous silicon material layer from having a large thickness due to the high environmental pressure, ensure that the thickness difference between the edge portion and the central portion of the intrinsic amorphous silicon material layer is small, ensure that the structure of the edge portion of the intrinsic amorphous silicon material layer is as dense as the structure of its central portion, and thus make the phosphorus silicon glass layer formed after the phosphorus diffusion treatment have high corrosion resistance in all parts parallel to the backlight surface, and ensure that the morphology and formation range of the formed N-type doped polysilicon meet the target requirements. At the same time, it can also prevent the process efficiency from being low due to low environmental pressure.
  • the gas flow rate for forming the intrinsic amorphous silicon material layer can be greater than or equal to 0.9slm and less than or equal to 1.2slm.
  • the gas flow rate for forming the intrinsic amorphous silicon material layer can be 0.9slm, 1.0slm, 1.1slm or 1.2slm.
  • reducing the gas flow rate can reduce the total gas flow rate in the diffusion device, thereby reducing the degree of disturbance caused by the airflow in the diffusion device, which is beneficial to optimize the deposition quality of the portion of the intrinsic amorphous silicon material layer located on the edge area of the backlight surface, thereby ensuring the intrinsic amorphous silicon material layer is formed.
  • the structure of the edge of the amorphous silicon material layer is as dense as that of the center, so that the phosphorus-silicon glass layer formed after phosphorus diffusion treatment has high corrosion resistance in all parts parallel to the backlight surface, ensuring that the morphology and formation range of the formed N-type doped polysilicon meet the target requirements. At the same time, it can also prevent the process efficiency from being low due to low gas flow.
  • a wrap-around amorphous silicon layer 14 is formed on the side and part of the light-facing surface of the semiconductor substrate 11.
  • the width of the formation area of the wrap-around amorphous silicon layer 14 on the light-facing surface is affected by parameters such as the environmental pressure and gas flow rate when manufacturing the intrinsic amorphous silicon material layer 13.
  • the width of the formation area of the wrap-around amorphous silicon layer 14 on the light-facing surface can be determined according to the manufacturing conditions of the intrinsic amorphous silicon material layer 13.
  • the width of the formation area of the above-mentioned plated amorphous silicon layer on the light-facing surface can be greater than or equal to 0 and less than 10 mm.
  • the width of the formation area of the plated amorphous silicon layer on the light-facing surface can be 1 mm, 3 mm, 6 mm, 9 mm or 9.5 mm, etc.
  • the plated phosphorus silicon glass layer and the plated doping layer formed by the plating need to be removed in sequence, and the etching solution for removing the plated doping layer will also affect the surface of the portion of the semiconductor substrate facing the light that is covered by the plated doping layer, so that a porous structure is formed on the surface of this portion, and the surface of the central area of the semiconductor substrate facing the light that is not covered by the plated doping layer is relatively flat, resulting in inconsistent sizes of the velvet structure located on the edge area and the central area of the light-facing surface after the subsequent texturing process, thereby affecting the light trapping effect of the light-facing surface.
  • the plating width is smaller, which is beneficial to improve the size uniformity of the velvet structure located in each area of the light-facing surface, thereby improving the light trapping effect of the light-facing surface, and further improving the photoelectric conversion efficiency of the back-contact battery.
  • the specific value of the size uniformity of the velvet structure on each area of the light-facing surface of the semiconductor substrate can be determined according to the width of the formation area of the amorphous silicon layer on the light-facing surface during the actual manufacturing process and the size of the semiconductor substrate, and is not specifically limited here.
  • the phosphorus diffusion treatment includes a phosphorus source deposition step, a crystallization step, and a post-oxidation step performed in sequence.
  • the above-mentioned phosphorus source deposition step can regulate the doping concentration of phosphorus in the N-type doped polysilicon material layer and the phosphosilicate glass layer
  • the above-mentioned post-oxidation step can regulate the thickness of the N-type doped polysilicon material layer and the phosphosilicate glass layer.
  • the doping concentration of phosphorus in the N-type doped polysilicon material layer and the phosphosilicate glass layer, as well as the thickness of the phosphosilicate glass layer have an impact on the corrosion resistance of the phosphosilicate glass layer during the texturing process.
  • the specific process parameters of the phosphorus diffusion treatment can be determined according to the thickness and doping concentration of the N-type doped polysilicon material layer and the phosphosilicate glass layer, and the requirements of the actual application scenario for the morphology and formation range of the N-type doped polysilicon layer, and no specific limitation is made here.
  • the treatment conditions of the phosphorus diffusion treatment are:
  • the deposition process temperature is greater than or equal to 850° C. and less than or equal to 900° C.
  • the deposition process temperature may be 850° C., 860° C., 870° C., 880° C., 890° C., or 900° C., etc.
  • the deposition process environment pressure is greater than or equal to 150 mbar and less than or equal to 200 mbar.
  • the deposition process environment pressure may be 150 mbar, 160 mbar, 170 mbar, 180 mbar, 190 mbar or 200 mbar.
  • the pressure of the phosphorus source in the deposition process is greater than or equal to 250 mbar and less than or equal to 450 mbar.
  • the pressure of the phosphorus source in the deposition process can be 250 mbar, 300 mbar, 350 mbar, 400 mbar or 450 mbar.
  • the nitrogen flow rate of the deposition process is greater than or equal to 1500 sccm and less than or equal to 2000 sccm.
  • the nitrogen flow rate of the deposition process may be 1500 sccm, 1600 sccm, 1700 sccm, 1800 sccm, 1900 sccm or 2000 sccm.
  • the oxygen flow rate of the deposition process is greater than or equal to 750 sccm and less than or equal to 1000 sccm.
  • the oxygen flow rate of the deposition process may be 750 sccm, 800 sccm, 850 sccm, 900 sccm, 950 sccm or 1000 sccm.
  • the post-oxidation process temperature is greater than or equal to 850° C. and less than or equal to 900° C.
  • the post-oxidation process temperature may be 850° C., 860° C., 870° C., 880° C., 890° C., or 900° C., etc.
  • the oxygen flow rate of the post-oxidation process is greater than or equal to 5000 sccm and less than or equal to 10000 sccm.
  • the oxygen flow rate of the post-oxidation process can be 5000 sccm, 6000 sccm, 7000sccm, 8000sccm, 9000sccm or 10000sccm, etc.
  • any one of the above process parameters may meet the corresponding range requirements, or at least two of the above process parameters may meet the corresponding range requirements.
  • the deposition process temperature, deposition process environmental pressure, deposition process phosphorus source pressure, deposition process nitrogen flow rate and deposition process oxygen flow rate during the above phosphorus diffusion treatment are changed, and the average doping concentration of impurities in the formed phosphorus silicon glass layer and the N-type doped polysilicon material can be regulated.
  • the average doping concentration of phosphorus in the phosphorus silicon glass layer can be appropriately reduced, so that the phosphorus silicon glass layer has a higher corrosion resistance, thereby ensuring that the N-type doped polysilicon layer formed based on the N-type doped polysilicon material layer has a good morphology and meets the target requirements. Formation range.
  • changing the post-oxidation process temperature and the post-oxidation process oxygen flow rate during the phosphorus diffusion treatment can regulate the thickness of the formed phosphorus silicon glass layer.
  • the formation thickness of the phosphorus silicon glass layer can be appropriately increased, thereby improving the corrosion resistance of the phosphorus silicon glass layer.
  • the amorphous silicon layer is formed into a doped layer 17, and a phosphorus-silicate glass layer 18 is formed on the doped layer 17.
  • a process such as wet etching can be used to sequentially remove the phosphorus-silicate glass layer and the doped layer.
  • the phosphorus diffusion treatment is performed on the intrinsic amorphous silicon material layer
  • the texturing treatment is performed on at least the light-facing surface of the semiconductor substrate
  • laser etching or the like can be used to only diffuse phosphorus into the phosphorus silicon layer.
  • the glass layer 16 is patterned so that the remaining portion of the phosphosilicate glass layer 16 is formed on a local area of the N-type doped polysilicon material layer 15.
  • the tunnel passivation material layer and the N-type doped polysilicon material layer arranged in a stacked manner can be patterned while the light-facing surface of the semiconductor substrate 11 is textured under the masking action of the phosphosilicate glass layer 16.
  • the phosphosilicate glass layer can be patterned by laser etching, and then wet etching or dry etching can be used to pattern the tunnel passivation material layer and the N-type doped polysilicon material layer under the mask of the remaining part of the phosphosilicate glass layer to obtain the tunnel passivation layer and the N-type doped polysilicon layer.
  • a process such as wet etching or dry etching can be used to remove the remaining part of the phosphorus silicon glass layer.
  • a positive electrode 22 and a negative electrode 23 can be formed on the backlight side by screen printing or electroplating.
  • the positive electrode 22 is in ohmic contact with the P-type region of the semiconductor substrate 11, and the negative electrode 23 is in ohmic contact with the N-type doped polysilicon layer 21.
  • the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.
  • one embodiment means that a particular feature, structure or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present application. In one embodiment, the present invention is described in detail. In some embodiments, the present invention is described in detail. ...
  • any reference signs placed between brackets shall not be construed as limiting the claims.
  • the word “comprising” does not exclude the presence of elements or steps not listed in the claims.
  • the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
  • the present application may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware.
  • the use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

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Abstract

一种背接触电池及其制造方法、光伏组件，属于光伏技术领域。所述背接触电池包括：半导体基底，所述半导体基底具有相对设置的第一面和第二面，所述第一面具有绒面结构；以及沿所述半导体基底的厚度方向，依次层叠设置在所述第二面局部区域上的隧穿钝化层和N型掺杂多晶硅层；所述N型掺杂多晶硅层位于所述第二面的边缘区域上的部分与所述N型掺杂多晶硅层位于所述第二面的中心区域上的部分的厚度比大于或者等于1且小于或者等于1.2。

Description

一种背接触电池及其制造方法、光伏组件
本申请要求在2023年06月13日提交中国专利局、申请号为202310702158.2、发明名称为“一种背接触电池及其制造方法、光伏组件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及光伏技术领域，具体涉及一种背接触电池及其制造方法、光伏组件。
背景技术
隧穿钝化背接触式太阳能电池指正电极和负电极都处于电池的背面，正面没有金属电极遮挡，并且具有隧穿钝化接触结构的太阳能电池。因钝化背接触式太阳能电池具有较大的吸光面积、以及较低的载流子背面复合速率等优势，使其受到光伏学术界及工业界的广泛关注，成为高效太阳能电池技术的热门发展方向。
但是，采用相关制造方法所形成的隧穿钝化背接触式太阳能电池中，掺杂元素含有磷的N型掺杂多晶硅层的形貌较差，导致隧穿钝化背接触式太阳能电池的工作性能不佳。
发明内容
本申请的目的在于提供一种背接触电池及其制造方法、光伏组件。
具体来说，本申请涉及如下方面：
第一方面，本申请公开了一种背接触电池，该背接触电池包括：半导体基底，所述半导体基底具有相对设置的第一面和第二面，所述第一面具有绒面结构，以及沿半导体基底的厚度方向，依次层叠设置在所述第二面局部区域上的隧穿钝化层和N型掺杂多晶硅层。N型掺杂多晶硅层位于所述第二面的边缘区域上的部分与N型掺杂多晶硅层位于所述第二面的中心区域上的部分的厚度比大于或者等于1且小于或者等于1.2。
采用上述技术方案的情况下，由上述隧穿钝化层和N型掺杂多晶硅层可构成的隧穿钝化接触结构可以实现优异的界面钝化和载流子选择性收集，利于提高背接触电池的光电转换效率。另外，与相关技术中N型掺杂多晶硅层 的边缘部分与中间部分的厚度比大于1.3相比，本申请中的N型掺杂多晶硅层位于第二面的边缘区域上的部分与N型掺杂多晶硅层位于第二面的中心区域上的部分的厚度比大于或者等于1且小于或者等于1.2，此时N型掺杂多晶硅层的边缘部分的厚度与中心部分的厚度差值较小。在此情况下，在实际的制造过程中，通常采用化学气相沉积等工艺形成用于制造隧穿钝化层和N型掺杂多晶硅层的隧穿钝化材料层和本征非晶硅材料层。基于此，当N型掺杂多晶硅层的边缘部分的厚度与中心部分的厚度差值较小时，形成该N型掺杂多晶硅层的本征非晶硅材料层的边缘部分的厚度与中心部分的厚度差值也较小。因本征非晶硅材料层沿平行于第二面的各部分均是同时形成，位于第二面边缘区域上的本征非晶硅材料与位于第二面中心区域上的本征非晶硅材料的化学剂量比大致相同，故当本征非晶硅材料层的边缘部分与中心部分之间的厚度差较小时，本征非晶硅材料层的边缘部分和中心部分的结构致密性相差较少。相应地，在对本征非晶硅材料层进行磷扩散处理时，本征非晶硅材料层内的硅与扩散环境中的氧发生反应而获得的磷硅玻璃层的边缘部分的致密性也与自身中心部分的致密性相差较小，使得磷硅玻璃层的边缘部分具有与自身中心部分大致相同的较高的抗腐蚀性能，从而在对半导体基底的至少第一面进行制绒处理过程中通过该磷硅玻璃层能够很好地保护位于其下方的N型掺多晶硅材料层中用于形成N型掺杂多晶硅层的部分，使得获得的N型掺杂多晶硅层的形貌和形成范围满足目标要求，利于载流子的收集，降低反向漏电，进而利于提高背接触电池的光电转换效率。
作为一种可能的实现方式，上述第一面各区域上具有的绒面结构的尺寸均匀性大于或者等于85％且小于100％。
采用上述技术方案的情况下，第一面各区域上具有的绒面具有的尺寸均匀性较高，利于使得第一面各区域均具有较高的透光性，使得更多的光线可以经第一面透射至半导体基底内，进一步提高背接触电池的光电转换效率。
作为一种可能的实现方式，第二面上未被层叠设置所述隧穿钝化层和所述N型掺杂多晶硅层的区域为抛光面或者具有绒面结构。
作为一种可能的实现方式，上述N型掺杂多晶硅层位于第二面的边缘区域上的部分厚度大于或者等于175nm且小于或者等于225nm。
采用上述技术方案的情况下，N型掺杂多晶硅层位于第二面的边缘区域上的部分的厚度在上述范围内，可以防止因上述厚度值较小而导致N型掺杂多晶硅层的整体厚度较小而不满足目标要求、以及防止制造厚度均匀性较高的N型掺杂多晶硅层的难度较大，利于获得背接触电池。同时，还可以防止因上述厚度值较大而导致磷扩散处理后位于N型掺杂多晶硅材料层边缘部分上的磷硅玻璃层的抗腐蚀性能不佳，确保在进行制绒处理过程中磷硅玻璃层能够很好地包括N型掺多晶硅材料层中用于形成N型掺杂多晶硅层的各个部分，确保N型掺杂多晶硅层具有良好的形貌和满足目标要求的形成范围。
作为一种可能的实现方式，上述N型掺杂多晶硅层位于第二面的中心区域上的部分的厚度大于或者等于150nm且小于或者等于200nm。
作为一种可能的实现方式，上述N型掺杂多晶硅层内杂质的平均掺杂浓度大于或者等于3.5×1020/cm3且小于或者等于4.0×1020/cm3。
采用上述技术方案的情况下，N型掺杂多晶硅层内杂质的平均掺杂浓度在上述范围内，可以在确保N型掺杂多晶硅层具有优异的载流子选择性收集作用、且不影响N型掺杂多晶硅层与负极之间的接触电阻的前提下，相比于相关技术中N型掺杂多晶硅层(其内杂质的平均掺杂浓度大于5.0×1020/cm3)，适当降低本申请中N型掺杂多晶硅层内的杂质掺杂浓度。相应地，用于制造N型掺杂多晶硅层的N型掺杂多晶硅材料层内杂质的平均掺杂浓度也较低。基于此，在实际制造过程中，磷扩散处理后N型掺杂多晶硅材料层内杂质的平均掺杂浓度与形成在自身上的磷硅玻璃层内杂质的平均掺杂浓度成正比，故适当降低N型掺杂多晶硅层内的杂质掺杂浓度，也代表磷硅玻璃层内杂质(该杂质包括磷)的平均掺杂浓度降低。在此情况下，因磷硅玻璃层内的磷掺杂浓度与自身的抗腐蚀性能成反比，故适当降低磷硅玻璃层内磷掺杂浓度还可以提高自身的防腐蚀性能，进一步确保N型掺杂多晶硅层具有良好的形貌和满足目标要求的形成范围。
第二方面，本申请还公开了一种光伏组件，该光伏组件包括上述第一方面及其各种实现方式提供的背接触电池。
本申请中第二方面的有益效果，可以参考第一方面及其各种实现方式中的有益效果分析，此处不赘述。
第三方面，本申请还公开了一种背接触电池的制造方法，该背接触电池的制造方法包括：首先，提供一半导体基底，所述半导体基底具有相对设置的第一面和第二面。接下来，沿半导体基底的厚度方向，在半导体基底的第二面一侧依次形成层叠设置的隧穿钝化材料层和本征非晶硅材料层。接着，对本征非晶硅材料层进行磷扩散处理，以使本征非晶硅材料层形成N型掺杂多晶硅材料层，并在N型掺杂多晶硅材料层上形成磷硅玻璃层。上述N型掺杂多晶硅材料层位于第二面的边缘区域上的部分与自身位于第二面的中心区域上的部分的厚度比大于或者等于1且小于或者等于1.2。接下来，在磷硅玻璃层的掩膜作用下，对半导体基底的第一面进行制绒处理，以使第一面形成绒面结构。然后，对磷硅玻璃层、以及层叠设置的隧穿钝化材料层和N型掺杂多晶硅材料层进行图案化处理，以形成层叠设置在第二面的局部区域上的隧穿钝化层和N型掺杂多晶硅层。接着，去除剩余的磷硅玻璃层。
本申请中第三方面的有益效果，可以参考第一方面及其各种实现方式中的有益效果分析，此处不赘述。
作为一种可能的实现方式，形成本征非晶硅材料层的环境压力大于或者等于100mTorr且小于或者等于150mTorr。
采用上述技术方案的情况下，在实际制造本征非晶硅材料层的过程中，在一定范围内，降低环境压力可以提高分子自由程，让反应分子基团更快达到隧穿钝化材料层表面各区域处，而不在同一个位置聚集。基于此，形成本征非晶硅材料层的环境压力在上述范围内，可以防止因环境压力较大而导致本征非晶硅材料层的边缘部分的厚度较大，确保本征非晶硅材料层的边缘部分和中心部分的厚度差较小，确保本征非晶硅材料层的边缘部分的结构像自身中心部分的结构一样致密，进而使得磷扩散处理后形成的磷硅玻璃层沿平行于第二面方向的各部分均具有较高的抗腐蚀性能，确保所形成的N型掺杂多晶硅的形貌和形成范围满足目标要求。同时，还可以防止因环境压力较小而导致制程效率较低。
作为一种可能的实现方式，形成本征非晶硅材料层的气体流量大于或者等于0.9slm且小于或者等于1.2slm。
采用上述技术方案的情况下，在实际制造本征非晶硅材料层的过程中， 在一定范围内，降低气体流量可以使得扩散设备内的总气体流量降低，进而使得扩散设备内因气流导致的扰动程度降低，利于使得本征非晶硅材料层位于第二面边缘区域上的部分的沉积质量得到优化，确保本征非晶硅材料层的边缘部分的结构像自身中心部分的结构一样致密，进而使得磷扩散处理后形成的磷硅玻璃层沿平行于第二面方向的各部分均具有较高的抗腐蚀性能，确保所形成的N型掺杂多晶硅的形貌和形成范围满足目标要求。同时，还可以防止因气体流量较小而导致制程效率较低。
作为一种可能的实现方式，对本征非晶硅材料层进行磷扩散处理后，在磷硅玻璃层的掩膜作用下，对半导体基底的第一面进行制绒处理前，仅对磷硅玻璃层进行图案化处理，以使磷硅玻璃层的剩余部分形成在N型掺杂多晶硅材料层的局部区域上。在此情况下，上述在磷硅玻璃层的掩膜作用下，对半导体基底的第一面进行制绒处理的同时，对层叠设置的隧穿钝化材料层和N型掺杂多晶硅材料层进行图案化处理。
采用上述技术方案的情况下，在进行制绒处理前对位于第二面一侧的磷硅玻璃层进行图案化处理，使得后续制绒处理过程中，制绒腐蚀液不仅能够使得至少第一面形成绒面，还可以在磷硅玻璃层的剩余部分的掩膜作用下，实现对N型掺杂多晶硅材料层的图案化处理，获得N型掺杂多晶硅层，从而能够在确保N型掺杂多晶硅层的形貌和形成范围满足目标要求的情况下，提高背接触电池的制程效率。
作为一种可能的实现方式，沿半导体基底的厚度方向，在半导体基底的第二面一侧形成本征非晶硅材料层的同时，在半导体基底的侧面和部分第一面上形成绕镀非晶硅层。绕镀非晶硅层在第一面上的形成区域的宽度大于或者等于0且小于10mm。形成区域的宽度方向平行于半导体基底的径向。并且，经磷扩散处理后，绕镀非晶硅层形成绕镀掺杂层，并在绕镀掺杂层上形成有绕镀磷硅玻璃层。在上述情况下，上述对本征非晶硅材料层进行磷扩散处理后，并且在磷硅玻璃层的掩膜作用下，对半导体基底的第一面进行制绒处理前，背接触电池的制造方法还包括：去除绕镀磷硅玻璃层和绕镀掺杂层。
采用上述技术方案的情况下，在进行制绒处理前，需要依次去除因绕镀而形成的绕镀磷硅玻璃层和绕镀掺杂层，而去除绕镀掺杂层的腐蚀液也会对 半导体基底第一面被绕镀掺杂层覆盖的部分的表面造成影响，使得该部分表面形成有多孔结构，而半导体基底第一面未被绕镀掺杂层覆盖的中心区域的表面较为平坦，导致后续制绒处理后，位于第一面边缘区域和中心区域上的绒面结构的尺寸不一致，进而影响第一面的陷光效果。在此情况下，与相关技术中，制造背接触电池时所形成的绕镀掺杂层在第一面上的形成区域的宽度大于10mm相比，本申请中绕镀非晶硅层在第一面上的形成区域的宽度大于或者等于0且小于10mm时，其绕镀宽度较小，利于提高位于第一面各区域上的绒面结构的尺寸均匀性，进而利于提高第一面的陷光效果，进一步提高背接触电池的光电转换效率。
作为一种可能的实现方式，上述磷硅玻璃层的厚度大于或者等于60nm且小于或者等于65nm。
采用上述技术方案的情况下，磷硅玻璃层的厚度在上述范围内，可以防止因磷硅玻璃层的厚度较小而导致磷硅玻璃层的抗腐蚀性能不佳，确保所形成的N型掺杂多晶硅层的形貌和形成范围满足目标要求。同时，还可以防止因磷硅玻璃层的厚度较大而导致制造本征非晶硅材料层和磷硅玻璃层的耗材使用量较大，利于控制背接触电池的制造成本。
作为一种可能的实现方式，上述本征非晶硅材料层的平均厚度为H1，磷硅玻璃层的平均厚度为H2，N型掺杂多晶硅材料层的平均厚度为H3，40％H2＜H1-H3＜60％H2。
采用上述技术方案的情况下，如前文所述，形成磷硅玻璃层需要消耗N型掺杂多晶硅材料层内的硅元素。基于此，本征非晶硅材料层、磷硅玻璃层和N型掺杂多晶硅材料层的平均厚度满足上述条件表明本征非晶硅材料层的形成厚度适当，并且本征非晶硅材料层沿平行于第二面方向的各区域的致密性、以及结构致密均匀性均较高，利于使得形成磷硅玻璃层后，N型掺杂多晶硅材料层的消耗厚度能够满足理论上致密性均较高的N型掺杂多晶硅材料层消耗量(即磷硅玻璃层的厚度大致等于N型掺杂多晶硅材料层厚度减小量的一半)或与上述理论消耗量相差较小，进而表明优化后的磷硅玻璃层的形成质量较高，确保所形成的N型掺杂多晶硅层具有良好的形貌和满足目标要求的形成范围。
作为一种可能的实现方式，上述磷扩散处理的处理条件为：
沉积工艺温度大于或者等于850℃且小于或者等于900℃。和/或，沉积工艺环境压力大于或者等于150mbar且小于或者等于200mbar。和/或，沉积工艺磷源压力大于或者等于250mbar且小于或者等于450mbar。和/或，沉积工艺氮气流量大于或者等于1500sccm且小于或者等于2000sccm。和/或，沉积工艺氧气流量大于或者等于750sccm且小于或者等于1000sccm。和/或，后氧化工艺温度大于或者等于850℃且小于或者等于900℃。和/或，后氧化工艺氧气流量大于或者等于5000sccm且小于或者等于10000sccm。
采用上述技术方案的情况下，在实际制造过程中，改变上述磷扩散处理时的沉积工艺温度、沉积工艺环境压力、沉积工艺磷源压力、沉积工艺氮气流量和沉积工艺氧气流量，可以对形成的磷硅玻璃层和N型掺杂多晶硅材料内杂质的平均掺杂浓度进行调控。基于此，当沉积工艺温度、沉积工艺环境压力、沉积工艺磷源压力、沉积工艺氮气流量和沉积工艺氧气流量中的至少一者在上述相应范围内，可以适当降低磷硅玻璃层内磷的平均掺杂浓度，使得磷硅玻璃层具有较高的抗腐蚀性能，进而确保基于N型掺杂多晶硅材料层形成的N型掺杂多晶硅层具有良好的形貌和满足目标要求的形成范围。另外，改变磷扩散处理时的后氧化工艺温度和后氧化工艺氧气流量可以对形成的磷硅玻璃层的厚度进行调控。基于此，当后氧化工艺温度和后氧化工艺氧气流量中的至少一者在上述相应范围内，可以适当增加磷硅玻璃层的形成厚度，进而提高磷硅玻璃层的抗腐蚀性能。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的背接触电池的结构纵向剖视示意图；
图2为相关技术中形成的N型掺杂多晶硅层位于第二面的边缘区域上的部分的SEM形貌示意图；
图3为本申请实施例中N型掺杂多晶硅层位于第二面的边缘区域上的部分的SEM形貌示意图；
图4为本申请实施例提供的背接触电池在制造过程中的结构纵向剖视示意图一；
图5为本申请实施例提供的背接触电池在制造过程中的结构纵向剖视示意图二；
图6为本申请实施例提供的背接触电池在制造过程中的结构纵向剖视示意图三；
图7为本申请实施例提供的背接触电池在制造过程中的结构纵向剖视示意图四；
图8为本申请实施例提供的背接触电池在制造过程中的结构纵向剖视示意图五；
图9为本申请实施例提供的背接触电池在制造过程中的结构纵向剖视示意图六；
图10为本申请实施例提供的背接触电池在制造过程中的结构纵向剖视示意图七。
附图标记：11为半导体基底，12为隧穿钝化材料层，13为本征非晶硅材料层，14为绕镀非晶硅层，15为N型掺杂多晶硅材料层，16为磷硅玻璃层，17为绕镀掺杂层，18为绕镀磷硅玻璃层，19为绒面，20为隧穿钝化层，21为N型掺杂多晶硅层，22为正极，23为负极。
具体实施例
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
隧穿钝化背接触式太阳能电池指正电极和负电极都处于电池的背面，正 面没有金属电极遮挡，并且具有隧穿钝化接触结构的太阳能电池。因隧穿钝化背接触式太阳能电池具有较大的吸光面积、以及较低的载流子背面复合速率等优势，使其受到光伏学术界及工业界的广泛关注，成为高效太阳能电池技术的热门发展方向。
具体的，相关技术中的隧穿钝化背接触式太阳能电池通常至少包括半导体基底、以及沿半导体基底的厚度方向，依次层叠设置在半导体基底背光面的局部区域上的隧穿钝化层和N型掺杂多晶硅层。在此情况下，在实际制造上述隧穿钝化背接触式太阳能电池的过程中，在依次形成整层覆盖在半导体基底的背光面上的隧穿钝化材料层和本征非晶硅材料层后，会对本征非晶硅材料层进行磷扩散处理，以使得本征非晶硅材料层形成N型掺杂多晶硅材料层，并在N型掺杂多晶硅材料层上形成磷硅玻璃层。接着，会在磷硅玻璃层的掩膜作用下，对半导体基底的至少向光面进行制绒处理，以使得至少向光面形成绒面，进而使得更多的光线可以经由向光面透射至半导体基底内，利于提升隧穿钝化背接触式太阳能电池的光电转换效率。同时，以在磷扩散处理中形成的磷硅玻璃层直接作为保护N型掺杂多晶硅层的掩膜层，无须为了保护N型掺杂多晶硅层而额外形成其它掩膜层，以简化隧穿钝化背接触式太阳能电池的制程工序，提高制程效率。
但是，采用相关的制造方法所形成的本征非晶硅材料层的边缘部分的厚度较大，其中心部分的厚度较小；并且本征非晶硅材料层的边缘部分和中间部分之间的厚度差较大(二者之间的厚度比值通常大于1.3)。在此情况下，因本征非晶硅材料层沿平行于背光面的各部分均是同时形成，位于背光面边缘区域上的本征非晶硅材料与位于背光面中心区域上的本征非晶硅材料的化学剂量比大致相同，故当本征非晶硅材料层的边缘部分与中心部分之间的厚度差较大时，本征非晶硅材料层的边缘部分的结构更加疏松。而进行磷扩散处理时，磷硅玻璃层的形成是消耗本征非晶硅材料层内的硅元素，使其与扩散环境中的氧发生反应而获得的，因此当本征非晶硅材料层的边缘部分的结构更加疏松时，位于本征非晶硅材料层的边缘部分上的磷硅玻璃层的形成质量也较差，使得该部分的磷硅玻璃层的抗腐蚀性能较差，从而导致磷硅玻璃层在制绒处理过程中难以很好的保护位于其下方的N型掺多晶硅材料层， 进而使得基于该N型掺杂多晶硅材料层形成的N型掺杂多晶硅层的形貌较差、且边缘区域的形成范围较小，不利于载流子的收集，导致隧穿钝化背接触式太阳能电池的工作性能不佳。
为了解决上述技术问题，第一方面，本申请实施例提供了一种背接触电池。如图1所示，该背接触电池包括：半导体基底11，半导体基底11具有相对设置的第一面和第二面，第一面具有绒面结构；以及沿半导体基底11的厚度方向，依次层叠设置在第二面局部区域上的隧穿钝化层20和N型掺杂多晶硅层21。N型掺杂多晶硅层21内的掺杂元素包括磷，N型掺杂多晶硅层21位于第二面的边缘区域上的部分与N型掺杂多晶硅层21位于第二面的中心区域上的部分的厚度比大于或者等于1且小于或者等于1.2。
需要说明的是，在半导体基底11的第一面为向光面的情况下，第二面为背光面。在半导体基底11的第一面为背光面的情况下，第二面则为向光面。对此，本申请不做具体的限制。以下将以半导体基底11的第一面为向光面，第二面为背光面为例，进行相关的说明。
具体来说，从材料方面来讲，上述半导体基底的材料可以为硅、锗硅或锗等半导体材料。从导电类型方面来讲，半导体基底可以为N型半导体基底，也可以为P型半导体基底。
从结构方面来讲，半导体基底的具体结构可以根据半导体基底的导电类型、以及实际应用场景确定。
示例性的，在半导体基底为P型半导体基底的情况下，沿平行于背光面的方向，半导体基底的背光面具有与层叠设置的隧穿钝化层和N型掺杂多晶硅层交替间隔分布的P型区域。此时P型区域为背接触电池的背面场。换句话说，本申请实施例提供的背接触电池中背面场为P型半导体基底具有的区域，无须进行额外的掺杂处理形成背面场，简化背接触电池的制程工序，提高制程效率。同时，还可以防止因需要在背光面一侧进行N型和P型两次高温掺杂而导致半导体基底的少子寿命低以及边缘PN结难以去除等问题的发生，利于提升背接触电池的良率。
当然，在半导体基底为P型半导体基底的情况下，也可以是在半导体基底的背光面的局部区域上形成P型掺杂区。沿平行于背光面的方向，P型掺 杂区与上述层叠设置的隧穿钝化层和N型掺杂多晶硅层交替间隔分布。
示例性的，在半导体基底为N型半导体基底的情况下，半导体基底的背光面的局部区域内或背光面的局部区域上形成有P型掺杂区。沿平行于背光面的方向，P型掺杂区与上述层叠设置的隧穿钝化层和N型掺杂多晶硅层交替间隔分布。
从形貌方面来讲，半导体基底的向光面为绒面。半导体基底的侧面可以为抛光面，也可以为绒面。半导体基底的背光面未被层叠设置的隧穿钝化层和N型掺杂多晶硅层覆盖的区域表面可以为绒面，也可以为抛光面。
对于上述隧穿钝化层来说，该隧穿钝化层的材料和厚度可以根据实际需求进行设置，此处不做具体限定。例如：该隧穿钝化层的材料可以包括氧化硅、氧化铝、氧化钛、二氧化铪、氧化镓、五氧化二钽、五氧化铌、氮化硅、碳氮化硅、氮化铝、氮化钛、氮碳化钛中的一种或多种。
对于上述N型掺杂多晶硅层来说，N型掺杂多晶硅层位于背光面的边缘区域上的部分与N型掺杂多晶硅层位于背光面的中心区域上的部分的厚度比可以是大于或者等于1且小于或者等于1.2的任一数值。例如：N型掺杂多晶硅层位于背光面的边缘区域上的部分与N型掺杂多晶硅层位于背光面的中心区域上的部分的厚度比可以为1、1.12、1.14、1.16、1.18或1.2等。
采用上述技术方案的情况下，由上述隧穿钝化层和N型掺杂多晶硅层可构成的隧穿钝化接触结构可以实现优异的界面钝化和载流子选择性收集，利于提高背接触电池的光电转换效率。另外，与相关技术的N型掺杂多晶硅层(参见图2)的边缘部分与中间部分的厚度比大于1.3相比，本申请实施例中的N型掺杂多晶硅层位于背光面的边缘区域上的部分与N型掺杂多晶硅层位于背光面的中心区域上的部分的厚度比大于或者等于1且小于或者等于1.2。如图1所示，此时N型掺杂多晶硅层21的边缘部分的厚度与中心部分的厚度差值较小。在此情况下，在实际的制造过程中，如图4所示，通常采用化学气相沉积等工艺形成用于制造隧穿钝化层和N型掺杂多晶硅层的隧穿钝化材料层12和本征非晶硅材料层13。基于此，当N型掺杂多晶硅层的边缘部分的厚度与中心部分的厚度差值较小时，形成该N型掺杂多晶硅层的本征非晶硅材料层13的边缘部分的厚度与中心部分的厚度差值也较小。因本 征非晶硅材料层13沿平行于背光面的各部分均是同时形成，位于背光面边缘区域上的本征非晶硅材料与位于背光面中心区域上的本征非晶硅材料的化学剂量比大致相同，故当本征非晶硅材料层13的边缘部分与中心部分之间的厚度差较小时，本征非晶硅材料层13的边缘部分和中心部分的结构致密性相差较少(参见图3)。相应地，如图5所示，在对本征非晶硅材料层13进行磷扩散处理时，本征非晶硅材料层13内的硅与扩散环境中的氧发生反应而获得的磷硅玻璃层16的边缘部分的致密性也与自身中心部分的致密性相差较小，使得磷硅玻璃层16的边缘部分具有与自身中心部分大致相同的较高的抗腐蚀性能，从而在对半导体基底11的至少向光面进行制绒处理过程中通过该磷硅玻璃层16能够很好地保护位于其下方的N型掺杂多晶硅材料层15中用于形成N型掺杂多晶硅层21的部分(参见图7和图8)，使得获得的N型掺杂多晶硅层21的形貌和形成范围满足目标要求，利于载流子的收集，降低反向漏电，进而利于提高背接触电池的光电转换效率。
由上述内容可知，N型掺杂多晶硅层位于背光面的边缘区域上的部分与N型掺杂多晶硅层位于背光面的中心区域上的部分的厚度比的大小会对磷扩散处理后所形成的磷硅玻璃层的抗腐蚀性能造成影响，进而影响自身的形貌、以及自身在背光面一侧形成范围。基于此，沿平行于背光面的方向，N型掺杂多晶硅层各部分的具体厚度可以根据实际应用场景中对N型掺杂多晶硅层的形貌和在背光面一侧的形成范围要求确定，只要能够应用至本申请实施例提供的背接触电池中均可。
示例性的，如图1所示，上述N型掺杂多晶硅层21位于背光面的边缘区域上的部分厚度可以大于或者等于175nm且小于或者等于225nm。例如：N型掺杂多晶硅层21位于背光面的边缘区域上的部分厚度可以为175nm、185nm、195nm、205nm、215nm或225nm等。在此情况下，N型掺杂多晶硅层21位于背光面的边缘区域上的部分的厚度在上述范围内，可以防止因上述厚度值较小而导致N型掺杂多晶硅层21的整体厚度较小而不满足目标要求、以及防止制造厚度均匀性较高的N型掺杂多晶硅层21的难度较大，利于获得背接触电池。同时，还可以防止因上述厚度值较大而导致磷扩散处理后位于N型掺杂多晶硅材料层边缘部分上的磷硅玻璃层的抗腐蚀性能不佳，确保 在进行制绒处理过程中磷硅玻璃层能够很好地包括N型掺多晶硅材料层中用于形成N型掺杂多晶硅层21的各个部分，确保N型掺杂多晶硅层21具有良好的形貌和满足目标要求的形成范围。
示例性的，如图1所示，上述N型掺杂多晶硅层21位于背光面的中心区域上的部分的厚度可以大于或者等于150nm且小于或者等于200nm。例如：N型掺杂多晶硅层21位于背光面的中心区域上的部分的厚度可以为150nm、160nm、170nm、180nm、190nm或200nm等。
从掺杂方面来说，上述N型掺杂多晶硅层内可以仅掺杂有磷这一种N型杂质，或者还可以掺杂有氮或砷等N型杂质。至于N型掺杂多晶硅层内杂质的掺杂浓度，可以根据实际需求进行设置，此处不做具体限定。
示例性的，上述N型掺杂多晶硅层内杂质的平均掺杂浓度可以大于或者等于3.5×1020/cm3且小于或者等于4.0×1020/cm3。例如：N型掺杂多晶硅层内杂质的平均掺杂浓度可以为3.5×1020/cm3、3.6×1020/cm3、3.7×1020/cm3、3.8×1020/cm3、3.9×1020/cm3或4.0×1020/cm3等。在此情况下，N型掺杂多晶硅层内杂质的平均掺杂浓度在上述范围内，可以在确保N型掺杂多晶硅层具有优异的载流子选择性收集作用、且不影响N型掺杂多晶硅层与负极之间的接触电阻的前提下，相比于相关技术N型掺杂多晶硅层(其内杂质的平均掺杂浓度大于5.0×1020/cm3)，适当降低本申请实施例中N型掺杂多晶硅层内的杂质掺杂浓度。相应地，用于制造N型掺杂多晶硅层的N型掺杂多晶硅材料层内杂质的平均掺杂浓度也较低。基于此，在实际制造过程中，磷扩散处理后N型掺杂多晶硅材料层内杂质的平均掺杂浓度与形成在自身上的磷硅玻璃层内杂质的平均掺杂浓度成正比，故适当降低N型掺杂多晶硅层内的杂质掺杂浓度，也代表磷硅玻璃层内杂质(该杂质包括磷)的平均掺杂浓度降低。在此情况下，因磷硅玻璃层内的磷掺杂浓度与自身的抗腐蚀性能成反比，故适当降低磷硅玻璃层内磷掺杂浓度还可以提高自身的防腐蚀性能，进一步确保N型掺杂多晶硅层具有良好的形貌和满足目标要求的形成范围。
在实际的应用过程中，在背光面一侧形成N型掺杂多晶硅层的过程中，会在半导体基底的侧面和部分向光面上因绕镀而形成绕镀掺杂层和绕镀磷硅玻璃层。并且，在对半导体基底的至少向光面进行制绒处理前，需要依次 去除绕镀磷硅玻璃层和绕镀掺杂层，而去除绕镀掺杂层的腐蚀液也会对半导体基底向光面被绕镀掺杂层覆盖的部分的表面造成影响，使得该部分表面形成有多孔结构，而半导体基底向光面未被绕镀掺杂层覆盖的中心区域的表面较为平坦，导致后续制绒处理后，位于向光面边缘区域和中心区域上的绒面结构的尺寸不一致，进而影响向光面的陷光效果。具体的，向光面各区域上具有的绒面结构的尺寸均匀性可以根据N型掺杂多晶硅层的形成情况进行确定，此处不做具体限定。
示例性的，如图1所示，上述向光面各区域上具有的绒面结构的尺寸均匀性大于或者等于85％且小于100％。其中，向光面各区域上具有的绒面结构的尺寸均匀性的具体数值，可以根据实际制造过程确定，此处不做具体限定。在此情况下，向光面各区域上具有的绒面具有的尺寸均匀性较高，利于使得向光面各区域均具有较高的透光性，使得更多的光线可以经向光面透射至半导体基底11内，进一步提高背接触电池的光电转换效率。
在一些情况下，如图10所示，本申请实施例提供的背接触电池还可以包括正极22和负极23。其中，正极22与半导体基底11具有的P型区域欧姆接触。负极23与N型掺杂多晶硅层21欧姆接触。正极22和负极23的材料可以为铜、铝或银等导电材料。
第二方面，本申请实施例还提供了一种光伏组件，该光伏组件包括上述第一方面及其各种实现方式提供的背接触电池。
本申请实施例中第二方面的有益效果，可以参考第一方面及其各种实现方式中的有益效果分析，此处不赘述。
第三方面，本申请实施例还提供了一种背接触电池的制造方法。下文将根据图4至图10示出的操作的剖视图，对制造过程进行描述。
具体的，该背接触电池的制造方法包括：首先，提供一半导体基底。接下来，如图4所示，沿半导体基底11的厚度方向，在半导体基底11的背光面一侧依次形成层叠设置的隧穿钝化材料层12和本征非晶硅材料层13。接着，如图5所示，对本征非晶硅材料层进行磷扩散处理，以使本征非晶硅材料层形成N型掺杂多晶硅材料层15，并在N型掺杂多晶硅材料层15上形成磷硅玻璃层16。上述N型掺杂多晶硅材料层15位于背光面的中心区域上的 部分的厚度比大于或者等于1且小于或者等于1.2。接下来，如图8所示，在磷硅玻璃层16的掩膜作用下，对半导体基底11的向光面进行制绒处理，以使向光面形成绒面19。然后，如图8所示，对磷硅玻璃层16、以及层叠设置的隧穿钝化材料层和N型掺杂多晶硅材料层进行图案化处理，以形成层叠设置在背光面的局部区域上的隧穿钝化层20和N型掺杂多晶硅层21。接着，如图9所示，去除剩余的磷硅玻璃层。
本申请实施例中第三方面的有益效果，可以参考第一方面及其各种实现方式中的有益效果分析，此处不赘述。
具体来说，上述半导体基底的具体结构、导电类型和材料等可以参考前文，此处不再赘述。在提供半导体基底后，可以采用化学气相沉积等工艺形成上述隧穿钝化材料层和本征非晶硅材料层。其中，隧穿钝化材料层的材料和厚度等可以参考前文。至于本征非晶硅材料层，该本征非晶硅材料层用于制造背接触电池包括的N型掺杂多晶硅层。并且，在进行磷扩散处理后所形成的磷硅玻璃层需要消耗本征非晶硅材料层内的部分硅，导致磷扩散处理后基于本征非晶硅材料层形成的N型多晶硅材料层的厚度减小。基于此，本征非晶硅材料层各部分的厚度可以根据N型掺杂多晶硅材料层和磷硅玻璃层的各部分的厚度、以及形成相应厚度的磷硅玻璃层需要消耗的本征非晶硅材料的厚度比例进行确定。
示例性的，在上述本征非晶硅材料层的平均厚度为H1、磷硅玻璃层的平均厚度为H2、以及N型掺杂多晶硅材料层的平均厚度为H3的情况下，40％H2＜H1-H3＜60％H2。此时，本征非晶硅材料层、磷硅玻璃层和N型掺杂多晶硅材料层的平均厚度满足上述条件表明本征非晶硅材料层的形成厚度适当，并且本征非晶硅材料层沿平行于背光面方向的各区域的致密性、以及结构致密均匀性均较高，利于使得形成磷硅玻璃层后，N型掺杂多晶硅材料层的消耗厚度能够满足理论上致密性均较高的N型掺杂多晶硅材料层消耗量(即磷硅玻璃层的厚度大致等于N型掺杂多晶硅材料层厚度减小量的一半)或与上述理论消耗量相差较小，进而表明优化后的磷硅玻璃层的形成质量较高，确保所形成的N型掺杂多晶硅层具有良好的形貌和满足目标要求的形成范围。
另外，基于本征非晶硅材料层所形成的N型掺杂多晶硅材料层，其位于 背光面的边缘区域上的部分与自身位于背光面的中心区域上的部分的厚度比大于或者等于1且小于或者等于1.2，相应地本征非晶硅材料层位于背光面的边缘区域上的部分与自身位于背光面的中心区域上的部分的厚度比也满足大于或者等于1且小于或者等于1.2。在此情况下，在实际的制造过程中，可以通过调整形成本征非晶硅材料层时的环境压力、气体流量等任意能够对本征非晶硅材料层不同区域的形成厚度造成影响的参数的方式，实现对本征非晶硅材料层相应区域的厚度进行调控。具体的，上述对本征非晶硅材料层不同区域的形成厚度造成影响的具体参数值大小，可以根据对本征非晶硅材料层不同区域的具体形成厚度进行确定，只要能够应用至本申请实施例提供的背接触电池的制造方法中均可。
示例性的，形成本征非晶硅材料层的环境压力可以大于或者等于100mTorr且小于或者等于150mTorr。例如：形成本征非晶硅材料层的环境压力可以为100mTorr、110mTorr、120mTorr、130mTorr、140mTorr或150mTorr等。在此情况下，在实际制造本征非晶硅材料层的过程中，在一定范围内，降低环境压力可以提高分子自由程，让反应分子基团更快达到隧穿钝化材料层表面各区域处，而不在同一个位置聚集。基于此，形成本征非晶硅材料层的环境压力在上述范围内，可以防止因环境压力较大而导致本征非晶硅材料层的边缘部分的厚度较大，确保本征非晶硅材料层的边缘部分和中心部分的厚度差较小，确保本征非晶硅材料层的边缘部分的结构像自身中心部分的结构一样致密，进而使得磷扩散处理后形成的磷硅玻璃层沿平行于背光面方向的各部分均具有较高的抗腐蚀性能，确保所形成的N型掺杂多晶硅的形貌和形成范围满足目标要求。同时，还可以防止因环境压力较小而导致制程效率较低。
示例性的，形成本征非晶硅材料层的气体流量可以大于或者等于0.9slm且小于或者等于1.2slm。例如：形成本征非晶硅材料层的气体流量可以为0.9slm、1.0slm、1.1slm或1.2slm。在此情况下，在实际制造本征非晶硅材料层的过程中，在一定范围内，降低气体流量可以使得扩散设备内的总气体流量降低，进而使得扩散设备内因气流导致的扰动程度降低，利于使得本征非晶硅材料层位于背光面边缘区域上的部分的沉积质量得到优化，确保本 征非晶硅材料层的边缘部分的结构像自身中心部分的结构一样致密，进而使得磷扩散处理后形成的磷硅玻璃层沿平行于背光面方向的各部分均具有较高的抗腐蚀性能，确保所形成的N型掺杂多晶硅的形貌和形成范围满足目标要求。同时，还可以防止因气体流量较小而导致制程效率较低。
需要说明的是，如图4所示，沿半导体基底11的厚度方向，在半导体基底11的背光面一侧形成本征非晶硅材料层13的同时，在半导体基底11的侧面和部分向光面上形成绕镀非晶硅层14。该绕镀非晶硅层14在向光面上的形成区域的宽度(形成区域的宽度方向平行于半导体基底11的径向)受制造本征非晶硅材料层13时的环境压力和气体流量等参数的影响。例如：在一定范围内，造本征非晶硅材料层13时的环境压力越小，绕镀非晶硅层14在向光面上的形成区域的宽度也越小。在上述情况下，可以根据本征非晶硅材料层13的制造情况确定，绕镀非晶硅层14在向光面上的形成区域的宽度。
示例性的，上述绕镀非晶硅层在向光面上的形成区域的宽度可以大于或者等于0且小于10mm。例如：绕镀非晶硅层在向光面上的形成区域的宽度可以1mm、3mm、6mm、9mm或9.5mm等。在此情况下，在进行制绒处理前，需要依次去除因绕镀而形成的绕镀磷硅玻璃层和绕镀掺杂层，而去除绕镀掺杂层的腐蚀液也会对半导体基底向光面被绕镀掺杂层覆盖的部分的表面造成影响，使得该部分表面形成有多孔结构，而半导体基底向光面未被绕镀掺杂层覆盖的中心区域的表面较为平坦，导致后续制绒处理后，位于向光面边缘区域和中心区域上的绒面结构的尺寸不一致，进而影响向光面的陷光效果。在此情况下，与相关制造背接触电池时所形成的绕镀掺杂层在向光面上的形成区域的宽度大于10mm相比，本申请实施例中绕镀非晶硅层在向光面上的形成区域的宽度大于或者等于0且小于10mm时，其绕镀宽度较小，利于提高位于向光面各区域上的绒面结构的尺寸均匀性，进而利于提高向光面的陷光效果，进一步提高背接触电池的光电转换效率。由此可见，半导体基底向光面各区域上具有的绒面结构的尺寸均匀性的具体数值，可以根据实际制造过程中绕镀非晶硅层在向光面上的形成区域的宽度、以及半导体基底的尺寸确定，此处不做具体限定。
在实际的制造过程中，在形成上述本征非晶硅材料层后，需要对本征非晶硅材料层进行磷扩散处理，以形成上述N型掺杂多晶硅材料层和磷硅玻璃层。其中，磷扩散处理包括依次执行的磷源沉积步骤、推进晶化步骤、以及后氧化步骤。上述磷源沉积步骤可以调控N型掺杂多晶硅材料层和磷硅玻璃层内磷的掺杂浓度，上述后氧化步骤可以调控N型掺杂多晶硅材料层和磷硅玻璃层的厚度。并且，N型掺杂多晶硅材料层和磷硅玻璃层内磷的掺杂浓度、以及磷硅玻璃层的厚度均对磷硅玻璃层在制绒处理过程中的抗腐蚀性能有影响。基于此，可以根据N型掺杂多晶硅材料层和磷硅玻璃层的厚度与掺杂浓度、以及实际应用场景对N型掺杂多晶硅层的形貌和形成范围要求确定磷扩散处理的具体工艺参数，此处不做具体限定。
示例性的，上述磷扩散处理的处理条件为：
沉积工艺温度大于或者等于850℃且小于或者等于900℃。例如：沉积工艺温度可以为850℃、860℃、870℃、880℃、890℃或900℃等。
沉积工艺环境压力大于或者等于150mbar且小于或者等于200mbar。例如：沉积工艺环境压力可以为150mbar、160mbar、170mbar、180mbar、190mbar或200mbar等。
沉积工艺磷源压力大于或者等于250mbar且小于或者等于450mbar。例如：沉积工艺磷源压力可以为250mbar、300mbar、350mbar、400mbar或450mbar等。
沉积工艺氮气流量大于或者等于1500sccm且小于或者等于2000sccm。例如：沉积工艺氮气流量可以为1500sccm、1600sccm、1700sccm、1800sccm、1900sccm或2000sccm等。
沉积工艺氧气流量大于或者等于750sccm且小于或者等于1000sccm。例如：沉积工艺氧气流量可以为750sccm、800sccm、850sccm、900sccm、950sccm或1000sccm等。
后氧化工艺温度大于或者等于850℃且小于或者等于900℃。例如：后氧化工艺温度可以为850℃、860℃、870℃、880℃、890℃或900℃等。
后氧化工艺氧气流量大于或者等于5000sccm且小于或者等于10000sccm。例如：后氧化工艺氧气流量可以为5000sccm、6000sccm、 7000sccm、8000sccm、9000sccm或10000sccm等。
其中，可以是上述工艺参数中的任一个满足相应范围要求，也可以是上述工艺参数中的至少两个满足相应范围要求。
采用上述技术方案的情况下，在实际制造过程中，改变上述磷扩散处理时的沉积工艺温度、沉积工艺环境压力、沉积工艺磷源压力、沉积工艺氮气流量和沉积工艺氧气流量，可以对形成的磷硅玻璃层和N型掺杂多晶硅材料内杂质的平均掺杂浓度进行调控。基于此，当沉积工艺温度、沉积工艺环境压力、沉积工艺磷源压力、沉积工艺氮气流量和沉积工艺氧气流量中的至少一者在上述相应范围内，可以适当降低磷硅玻璃层内磷的平均掺杂浓度，使得磷硅玻璃层具有较高的抗腐蚀性能，进而确保基于N型掺杂多晶硅材料层形成的N型掺杂多晶硅层具有良好的形貌和满足目标要求的形成范围。另外，改变磷扩散处理时的后氧化工艺温度和后氧化工艺氧气流量可以对形成的磷硅玻璃层的厚度进行调控。基于此，当后氧化工艺温度和后氧化工艺氧气流量中的至少一者在上述相应范围内，可以适当增加磷硅玻璃层的形成厚度，进而提高磷硅玻璃层的抗腐蚀性能。
示例性的，上述磷硅玻璃层的厚度可以大于或者等于60nm且小于或者等于65nm。例如：磷硅玻璃层的厚度可以为60nm、61nm、62nm、63nm、64nm或65nm等。在此情况下，磷硅玻璃层的厚度在上述范围内，可以防止因磷硅玻璃层的厚度较小而导致磷硅玻璃层的抗腐蚀性能不佳，确保所形成的N型掺杂多晶硅层的形貌和形成范围满足目标要求。同时，还可以防止因磷硅玻璃层的厚度较大而导致制造本征非晶硅材料层和磷硅玻璃层的耗材使用量较大，利于控制背接触电池的制造成本。
需要说明的是，如图5所示，经磷扩散处理后，绕镀非晶硅层形成绕镀掺杂层17，并在绕镀掺杂层17上形成有绕镀磷硅玻璃层18。在此情况下，在形成上述N型掺杂多晶硅材料层15后，并在对半导体基底11的至少向光面进行制绒处理前，如图6所示，可以采用湿法刻蚀等工艺，依次去除绕镀磷硅玻璃层和绕镀掺杂层。
另外，对本征非晶硅材料层进行磷扩散处理后，在对半导体基底的至少向光面进行制绒处理前，如图7所示，可以采用激光刻蚀等方式，仅对磷硅 玻璃层16进行图案化处理，以使磷硅玻璃层16的剩余部分形成在N型掺杂多晶硅材料层15的局部区域上。在此情况下，如图8所示，上述在磷硅玻璃层16的掩膜作用下，对半导体基底11的向光面进行制绒处理的同时，可以对层叠设置的隧穿钝化材料层和N型掺杂多晶硅材料层进行图案化处理。换句话说，在进行制绒处理前对位于背光面一侧的磷硅玻璃层16进行图案化处理，使得后续制绒处理过程中，制绒腐蚀液不仅能够使得至少向光面形成绒面19，还可以在磷硅玻璃层16的剩余部分的掩膜作用下，实现对N型掺杂多晶硅材料层和隧穿钝化材料层的图案化处理，获得N型掺杂多晶硅层21和隧穿钝化层20，从而能够在确保N型掺杂多晶硅层21的形貌和形成范围满足目标要求的情况下，提高背接触电池的制程效率。
当然，可也以在去除绕镀磷硅玻璃层和绕镀掺杂层后，直接在整层磷硅玻璃层的掩膜作用下，对半导体基底的至少向光面进行制绒处理。此时，制绒腐蚀液不会对N型掺杂多晶硅材料层沿平行于背光面的每个区域造成影响。在此情况下，在进行制绒处理后，可以采用激光刻蚀等方式，对磷硅玻璃层进行图案化处理，然后可以采用湿法刻蚀或干法刻蚀等方式，在磷硅玻璃层的剩余部分的掩膜作用下，再对隧穿钝化材料层和N型掺杂多晶硅材料层进行图案化处理，获得隧穿钝化层和N型掺杂多晶硅层。
接着，如图9所示，可以采用湿法刻蚀或干法刻蚀等工艺，去除磷硅玻璃层的剩余部分。然后，如图10所示，可以采用丝网印刷或电镀等方式，在背光面一侧形成正极22和负极23。正极22与半导体基底11具有的P型区域欧姆接触，负极23与N型掺杂多晶硅层21欧姆接触。
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本申请的至少一 个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本申请的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本申请可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (12)

  1. 一种背接触电池，其中，包括：
    半导体基底，所述半导体基底具有相对设置的第一面和第二面，所述第一面具有绒面结构；
    以及沿所述半导体基底的厚度方向，依次层叠设置在所述第二面局部区域上的隧穿钝化层和N型掺杂多晶硅层；所述N型掺杂多晶硅层位于所述第二面的边缘区域上的部分与所述N型掺杂多晶硅层位于所述第二面的中心区域上的部分的厚度比大于或者等于1且小于或者等于1.2。
  2. 根据权利要求1所述的背接触电池，其中，所述第一面各区域上具有的绒面结构的尺寸均匀性大于或者等于85％且小于100％。
  3. 根据权利要求1所述的背接触电池，其中，所述第二面上未被层叠设置所述隧穿钝化层和所述N型掺杂多晶硅层的区域为抛光面或者具有绒面结构。
  4. 根据权利要求1所述的背接触电池，其中，所述N型掺杂多晶硅层位于所述第二面的边缘区域上的部分厚度大于或者等于175nm且小于或者等于225nm；和/或，
    所述N型掺杂多晶硅层位于所述第二面的中心区域上的部分的厚度大于或者等于150nm且小于或者等于200nm。
  5. 根据权利要求1至4中任一项所述的背接触电池，其中，所述N型掺杂多晶硅层内杂质的平均掺杂浓度大于或者等于3.5×1020/cm3且小于或者等于4.0×1020/cm3。
  6. 一种光伏组件，其中，包括：如权利要求1至5中任一项所述的背接触电池。
  7. 一种背接触电池的制造方法，其中，包括：
    提供一半导体基底，所述半导体基底具有相对设置的第一面和第二面；
    沿所述半导体基底的厚度方向，在所述第二面一侧依次形成层叠设置的隧穿钝化材料层和本征非晶硅材料层；
    对所述本征非晶硅材料层进行磷扩散处理，以使所述本征非晶硅材料层形成N型掺杂多晶硅材料层，并在所述N型掺杂多晶硅材料层上形成磷硅玻 璃层；所述N型掺杂多晶硅材料层位于所述第二面的边缘区域上的部分与自身位于所述第二面的中心区域上的部分的厚度比大于或者等于1且小于或者等于1.2；
    在所述磷硅玻璃层的掩膜作用下，对所述第一面进行制绒处理，以使所述第一面形成绒面；
    对所述磷硅玻璃层、以及所述层叠设置的隧穿钝化材料层和N型掺杂多晶硅材料层进行图案化处理，以形成层叠设置在所述第二面的局部区域上的隧穿钝化层和N型掺杂多晶硅层；
    去除剩余的所述磷硅玻璃层。
  8. 根据权利要求7所述的背接触电池的制造方法，其中，形成所述本征非晶硅材料层的环境压力大于或者等于100mTorr且小于或者等于150mTorr；和/或，
    形成所述本征非晶硅材料层的气体流量大于或者等于0.9slm且小于或者等于1.2slm。
  9. 根据权利要7所述的背接触电池的制造方法，其中，所述对所述本征非晶硅材料层进行磷扩散处理后，所述在所述磷硅玻璃层的掩膜作用下，对所述第一面进行制绒处理前，仅对所述磷硅玻璃层进行所述图案化处理，以使所述磷硅玻璃层的剩余部分形成在所述N型掺杂多晶硅材料层的局部区域上；
    在所述磷硅玻璃层的掩膜作用下，对所述第一面进行制绒处理的同时，对所述层叠设置的隧穿钝化材料层和N型掺杂多晶硅材料层进行所述图案化处理。
  10. 根据权利要7所述的背接触电池的制造方法，其中，沿所述半导体基底的厚度方向，在所述第二面一侧形成本征非晶硅材料层的同时，在所述半导体基底的侧面和部分所述第一面上形成绕镀非晶硅层；所述绕镀非晶硅层在所述第一面上的形成区域的宽度大于或者等于0且小于10mm；所述形成区域的宽度方向平行于所述半导体基底的径向；
    经所述磷扩散处理后，所述绕镀非晶硅层形成绕镀掺杂层，并在所述绕镀掺杂层上形成有绕镀磷硅玻璃层；
    所述对所述本征非晶硅材料层进行磷扩散处理后，所述在所述磷硅玻璃层的掩膜作用下，对所述第一面进行制绒处理前，所述背接触电池的制造方法还包括：去除所述绕镀磷硅玻璃层和所述绕镀掺杂层。
  11. 根据权利要求7至10中任一项所述的背接触电池的制造方法，其中，所述磷硅玻璃层的厚度大于或者等于60nm且小于或者等于65nm；和/或，
    所述本征非晶硅材料层的平均厚度为H1，所述磷硅玻璃层的平均厚度为H2，所述N型掺杂多晶硅材料层的平均厚度为H3，40％H2＜H1-H3＜60％H2。
  12. 根据权利要求7至10中任一项所述的背接触电池的制造方法，其中，所述磷扩散处理的处理条件为：
    沉积工艺温度大于或者等于850℃且小于或者等于900℃；和/或，沉积工艺环境压力大于或者等于150mbar且小于或者等于200mbar；和/或，沉积工艺磷源压力大于或者等于250mbar且小于或者等于450mbar；和/或，沉积工艺氮气流量大于或者等于1500sccm且小于或者等于2000sccm；和/或，沉积工艺氧气流量大于或者等于750sccm且小于或者等于1000sccm；和/或，后氧化工艺温度大于或者等于850℃且小于或者等于900℃；和/或，后氧化工艺氧气流量大于或者等于5000sccm且小于或者等于10000sccm。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119730468A (zh) * 2025-02-28 2025-03-28 金阳(泉州)新能源科技有限公司 设置反向漏电通道的联合钝化背接触电池制备方法及模组
CN119894108A (zh) * 2025-03-25 2025-04-25 金阳(泉州)新能源科技有限公司 一种背接触太阳电池及其制备方法、电池组件
CN120730871A (zh) * 2025-08-26 2025-09-30 阿特斯阳光电力集团股份有限公司 背接触电池及其制造方法、光伏组件
CN120813109A (zh) * 2025-09-03 2025-10-17 浙江晶科能源有限公司 背接触电池及其制造方法、叠层电池、光伏组件

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117558798B (zh) * 2023-06-13 2025-05-09 泰州隆基乐叶光伏科技有限公司 一种背接触电池及其制造方法、光伏组件
CN119421556B (zh) * 2024-07-26 2025-12-05 隆基绿能科技股份有限公司 一种太阳能电池及其制作方法、光伏组件
WO2025195032A1 (zh) * 2024-03-19 2025-09-25 隆基绿能科技股份有限公司 一种太阳能电池及其制作方法、光伏组件
CN118538827A (zh) * 2024-05-27 2024-08-23 淮安捷泰新能源科技有限公司 一种P型TopCon电池及其制备方法
CN118658933B (zh) * 2024-08-20 2024-11-19 金阳(泉州)新能源科技有限公司 一种背接触电池的制备方法、背接触电池以及光伏组件
CN118763131B (zh) * 2024-09-09 2024-11-22 通威太阳能（成都）有限公司 太阳电池及光伏组件
CN120603394B (zh) * 2025-08-08 2025-11-25 鄂尔多斯市隆基光伏科技有限公司 一种太阳能电池及其制造方法、光伏组件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112885925A (zh) * 2021-02-05 2021-06-01 泰州隆基乐叶光伏科技有限公司 一种太阳能电池及其制作方法
US20220393044A1 (en) * 2021-06-04 2022-12-08 Solarlab Aiko Europe Gmbh Back contact structure and selective contact region buried solar cell comprising the same
CN115513309A (zh) * 2022-08-31 2022-12-23 隆基绿能科技股份有限公司 背接触太阳能电池及其制备方法
WO2023029059A1 (zh) * 2021-08-31 2023-03-09 正泰新能科技有限公司 一种N-TOPCon电池的绕镀多晶硅去除方法
CN117558798A (zh) * 2023-06-13 2024-02-13 泰州隆基乐叶光伏科技有限公司 一种背接触电池及其制造方法、光伏组件

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101627204B1 (ko) * 2013-11-28 2016-06-03 엘지전자 주식회사 태양 전지 및 이의 제조 방법
CN110634964B (zh) * 2019-09-26 2021-06-15 苏州腾晖光伏技术有限公司 一种高效晶硅太阳电池及其制备方法
CN110931596A (zh) * 2019-10-31 2020-03-27 泰州中来光电科技有限公司 一种基于pvd技术制备钝化接触结构的方法
CN113823704A (zh) * 2021-11-23 2021-12-21 陕西众森电能科技有限公司 一种p基硅背接触太阳能电池及其制备方法
CN115621333B (zh) * 2022-11-22 2023-03-10 金阳(泉州)新能源科技有限公司 双面隧穿氧化硅钝化的背接触太阳能电池及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112885925A (zh) * 2021-02-05 2021-06-01 泰州隆基乐叶光伏科技有限公司 一种太阳能电池及其制作方法
US20220393044A1 (en) * 2021-06-04 2022-12-08 Solarlab Aiko Europe Gmbh Back contact structure and selective contact region buried solar cell comprising the same
WO2023029059A1 (zh) * 2021-08-31 2023-03-09 正泰新能科技有限公司 一种N-TOPCon电池的绕镀多晶硅去除方法
CN115513309A (zh) * 2022-08-31 2022-12-23 隆基绿能科技股份有限公司 背接触太阳能电池及其制备方法
CN117558798A (zh) * 2023-06-13 2024-02-13 泰州隆基乐叶光伏科技有限公司 一种背接触电池及其制造方法、光伏组件

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4611047A4

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119730468A (zh) * 2025-02-28 2025-03-28 金阳(泉州)新能源科技有限公司 设置反向漏电通道的联合钝化背接触电池制备方法及模组
CN119894108A (zh) * 2025-03-25 2025-04-25 金阳(泉州)新能源科技有限公司 一种背接触太阳电池及其制备方法、电池组件
CN119894108B (zh) * 2025-03-25 2025-05-27 金阳(泉州)新能源科技有限公司 一种背接触太阳电池及其制备方法、电池组件
CN120730871A (zh) * 2025-08-26 2025-09-30 阿特斯阳光电力集团股份有限公司 背接触电池及其制造方法、光伏组件
CN120813109A (zh) * 2025-09-03 2025-10-17 浙江晶科能源有限公司 背接触电池及其制造方法、叠层电池、光伏组件

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