WO2025001771A1 - 用于芯粒互联接口的数据传输方法及芯粒互联接口 - Google Patents

用于芯粒互联接口的数据传输方法及芯粒互联接口 Download PDF

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Publication number
WO2025001771A1
WO2025001771A1 PCT/CN2024/097274 CN2024097274W WO2025001771A1 WO 2025001771 A1 WO2025001771 A1 WO 2025001771A1 CN 2024097274 W CN2024097274 W CN 2024097274W WO 2025001771 A1 WO2025001771 A1 WO 2025001771A1
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Prior art keywords
data
clock signal
clock
signals
data signals
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English (en)
French (fr)
Inventor
梁岩
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Hygon Information Technology Co Ltd
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Hygon Information Technology Co Ltd
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Priority to EP24830418.0A priority Critical patent/EP4567617A4/en
Publication of WO2025001771A1 publication Critical patent/WO2025001771A1/zh
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G06F13/4273—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines

Definitions

  • the embodiments of the present disclosure relate to a data transmission method, a transmitting end, a receiving end, a core-grain interconnection interface, a chip, and an electronic device.
  • a chiplet is a unit chip with certain functions and an interconnect interface within the package. It is the latest development in chip design technology. Chiplet technology uses multiple chiplets to implement chip design, which can not only reduce costs but also improve chip performance.
  • serial bus can provide a shorter delay between two chiplets, and can also expand the bandwidth between chiplets by increasing the bus bandwidth.
  • clock-to-data alignment is an essential part of data transmission.
  • clock-to-data alignment is a component of data link training. If the clock and data are not aligned after training, the data link needs to be fully trained again, which seriously affects the normal operation of the chip.
  • the embodiments of the present disclosure provide a data transmission method, a transmitting end, a receiving end, a core-grain interconnection interface, a chip, and an electronic device.
  • At least one embodiment of the present disclosure provides a data transmission method, applied to a receiving end, comprising: receiving N data signals and a first clock signal, wherein the number of cycles of the first clock signal is limited, and the number of cycles of each data signal in the N data signals is less than or equal to the number of cycles of the first clock signal.
  • the number of cycles, N is a positive integer; according to the first clock signal, the starting position of the data in the N data signals is located, and the data in the N data signals is obtained.
  • the starting position of data in N data signals is located, and the data in the N data signals is obtained, including: according to the first clock signal, N second clock signals are obtained, and the N second clock signals correspond to the N data signals respectively; according to the N second clock signals, the starting position of the data of each data signal in the N data signals is located respectively, and the data in the N data signals is converted from serial data to parallel data respectively; wherein each of the N second clock signals has the same number of cycles as the first clock signal.
  • the method further includes: according to N second clock signals, correspondingly saving the data in the N data signals to a buffer memory.
  • the method further includes: reading data in N data signals from a buffer memory according to a third clock signal, wherein the third clock signal is a local clock signal of the receiving end.
  • data in a data signal is read from a buffer memory according to a third clock signal, including: accessing a read pointer of the buffer memory according to the third clock signal to read data in N data signals.
  • data in N data signals are correspondingly saved to a buffer memory according to N second clock signals, including: according to the N second clock signals, respectively accessing the write pointer of the buffer memory to save the data in the N data signals to the buffer memory.
  • the method further includes: after at least one empty data is read from the buffer memory, stopping reading the buffer memory.
  • the number of cycles of each of the N data signals is M
  • the number of cycles of the first clock signal is M+X
  • M is an integer greater than or equal to 2
  • X is an integer greater than or equal to 0.
  • At least one embodiment of the present disclosure provides a data transmission method, applied to a transmitting end, comprising: sending N data signals and a first clock signal, wherein N is a positive integer, the number of cycles of the first clock signal is limited, and the number of cycles of each data signal in the N data signals is less than or equal to is equal to the number of cycles of the first clock signal, and the first clock signal is used to locate the starting position of data in the N data signals and obtain the data in the N data signals.
  • sending N data signals and a first clock signal includes: sending N data signals and the first clock signal at the same time; or, sending the first clock signal first, and then sending N data signals after a preset period.
  • the method further includes: when or after N data signals stop being sent, stopping sending the first clock signal.
  • the number of cycles of each of the N data signals is M
  • the number of cycles of the first clock signal is M+X
  • M is an integer greater than or equal to 2
  • X is an integer greater than or equal to 0.
  • At least one embodiment of the present disclosure provides a receiving end, applied to a chip interconnection interface, comprising: N data ports, configured to receive N data signals, where N is a positive integer; a clock port, configured to receive a first clock signal, the first clock signal has a limited number of cycles, and the number of cycles of each of the N data signals is less than or equal to the number of cycles of the first clock signal; a data processing module, connected to the N data ports and the clock port, configured to locate the starting position of the data in the N data signals according to the first clock signal, and obtain the data in the N data signals.
  • the receiving end also includes: a clock acquisition module, connected to the clock port and the data processing module, configured to acquire N second clock signals based on the first clock signal, and send the N second clock signals to the data processing module; the data processing module is configured to convert the data in the N data signals from serial data to parallel data according to the N second clock signals; wherein each of the N second clock signals has the same number of cycles as the first clock signal.
  • a clock acquisition module connected to the clock port and the data processing module, configured to acquire N second clock signals based on the first clock signal, and send the N second clock signals to the data processing module
  • the data processing module is configured to convert the data in the N data signals from serial data to parallel data according to the N second clock signals; wherein each of the N second clock signals has the same number of cycles as the first clock signal.
  • the receiving end further includes: a buffer memory connected to the data processing module and configured to store data in N data signals.
  • the data processing module is also configured to access the write pointer of the buffer memory respectively according to N second clock signals to save the data in the N data signals to the buffer memory.
  • the receiving end further includes: a data reading module connected to the buffer memory and configured to read data from the buffer memory according to the third clock signal.
  • the data reading module is further configured to access the read pointer of the buffer memory according to the third clock signal to read data in the N data signals.
  • the data reading module is further configured to stop reading data from the buffer memory after reading at least one empty data from the buffer memory.
  • the buffer memory is an asynchronous FIFO memory.
  • the receiving end also includes: a local clock configured to generate a local clock signal.
  • the number of cycles of each data signal in N data signals is M
  • the number of cycles of the first clock signal is M+X
  • M is an integer greater than or equal to 2
  • X is an integer greater than or equal to 0.
  • At least one embodiment of the present disclosure provides a transmitting end, applied to a chip interconnection interface, comprising: N data ports, configured to correspondingly send N data signals, where N is a positive integer; a clock port, configured to send a first clock signal; a local clock, connected to the clock port and the N data ports, configured to generate a first clock signal; wherein the first clock signal has a limited number of cycles, the number of cycles of each of the N data signals is less than or equal to the number of cycles of the first clock signal, and the first clock signal is used to locate the starting position of the data in the N data signals and obtain the data in the N data signals.
  • N data ports and clock ports are configured to send N data signals and a first clock signal at the same time; or, the clock port is configured to send the first clock signal first, and the N data ports are configured to send N data signals after a preset period after the first clock signal is sent.
  • the transmitting end also includes: a clock switch, connected to the local clock and to the clock port, and configured to disconnect the local clock from the clock port when N data signals stop sending or one cycle after stopping sending.
  • a clock switch connected to the local clock and to the clock port, and configured to disconnect the local clock from the clock port when N data signals stop sending or one cycle after stopping sending.
  • the number of cycles of each data signal of N data signals is M
  • the number of cycles of the first clock signal is M+X
  • M is an integer greater than or equal to 2
  • X is an integer greater than or equal to 0.
  • At least one embodiment of the present disclosure further provides a chiplet interconnection interface configured as Perform any method as described in the first aspect above.
  • At least one embodiment of the present disclosure further provides a chip interconnect interface configured to execute any method as described in the second aspect above.
  • At least one embodiment of the present disclosure further provides a chip interconnection interface, comprising a receiving end as described in any one of the third aspects.
  • At least one embodiment of the present disclosure further provides a chip-to-chip interconnection interface, comprising a transmitting end as described in any one of the third aspects.
  • At least one embodiment of the present disclosure further provides a chip comprising a plurality of core particles, wherein any two of the plurality of core particles are connected via a core particle interconnection interface such as the fifth aspect or the seventh aspect and a core particle interconnection interface such as the sixth aspect or the eighth aspect.
  • At least one embodiment of the present disclosure provides an electronic device comprising a chip as in the ninth aspect.
  • FIG1 shows a schematic diagram of a chip interconnection interface in the prior art
  • FIG2 is a schematic diagram showing clock-to-data alignment between chiplets in the prior art
  • FIG3 shows a flow chart of a data transmission method provided according to at least one embodiment of the present disclosure
  • FIG4 shows a flowchart of another data transmission method provided according to at least one embodiment of the present disclosure
  • FIG5 shows a schematic diagram of a receiving end provided by at least one embodiment of the present disclosure
  • FIG6 shows a schematic diagram of a transmitting end provided by at least one embodiment of the present disclosure
  • FIG7a shows a schematic diagram of the structure of a clock switch provided by at least one embodiment of the present disclosure
  • FIG7b is a schematic diagram showing a first clock signal and a data signal provided by at least one embodiment of the present disclosure
  • FIG7c shows a schematic diagram of a first clock signal and a data signal provided by at least one embodiment of the present disclosure
  • FIG8 shows a schematic diagram of a chip provided by at least one embodiment of the present disclosure
  • FIG9 shows a timing diagram of a data transmission method after chiplet interconnection provided by at least one embodiment of the present disclosure.
  • FIG. 10 shows a schematic diagram of an electronic device provided by at least one embodiment of the present disclosure.
  • the training of the data link is usually carried out after the initialization of the coreparticle is completed. It requires the cooperation of the coreparticle on the sending side and the coreparticle on the receiving side so that the coreparticle on the receiving side can find the most suitable data sampling window.
  • the training of the complete data link includes multiple parts, such as offset calibration, reference power supply Verf calibration, data path deskew, clock to data alignment (CDA, Clock and Data Alignment), parallel data reorder and data check.
  • Clock to data alignment is to adjust the phase between data and clock to finally obtain the appropriate sampling phase.
  • FIG. 1 shows a schematic diagram of a chip interconnection interface in the prior art.
  • chiplet A and chiplet B are connected via chiplet interconnection interface 110 and chiplet interconnection interface 120.
  • Chiplet A is the sending side
  • chiplet B is the receiving side.
  • Chiplet interconnection interface 110 includes multiple Data port 111, clock port 112 and local clock 113.
  • the core particle interconnection interface 120 includes multiple data ports 121, clock port 122, clock receiving module 123 and data sampling module 124. The number of data ports of multiple data ports 111 and multiple data ports 121 is equal, and they are respectively connected through multiple data paths.
  • the clock port 112 is connected to the clock port 122 through the clock path.
  • the local clock 113 generates a clock signal and sends the clock signal to the multiple data ports 111 and the clock port 112.
  • the clock receiving module 123 receives the clock signal generated by the local clock 113 and adjusts the clock signal, and sends the adjusted clock signal to the data sampling module 124.
  • the data sampling module 124 uses the clock signal to perform data sampling.
  • the clock signal can be a differential clock signal.
  • the clock signal and the data signal are continuously sent to the core particle B, and the data signal carries valid data and empty data, that is, the data signal does not carry all valid data.
  • Valid data is what core A wants to send to core B. Core A transmits valid data according to a preset data format. The length of valid data sent each time is limited. Valid data is not sent continuously. There will be some time gaps. Empty data is used to fill the gaps between valid data. Therefore, the data transmission between core A and core B will have data misalignment between multiple data channels. In the prior art, it is necessary to pre-train the clock-to-data alignment so that accurate data can be received.
  • FIG. 2 shows a schematic diagram of clock and data alignment between chiplets in the prior art.
  • Valid flags are usually used to train clock-to-data alignment.
  • Core A and Core B in FIG2 may be Core A and Core B shown in FIG1.
  • the valid flag is vld, which has a value of 1.
  • the sender copies it three times to become 3-bit data, and uses the first 3 bits of each data channel to carry the valid flag.
  • the valid flag can indicate the beginning of a valid data segment.
  • Core B can accurately locate the valid data from each data signal.
  • the valid data has an agreed data format, including the data length. Therefore, after the core B finds the valid flag, it can locate a valid data segment.
  • the three data signals sent from Core A are aligned. There is a certain phase difference or delay between the three data signals received by Core B. This delay is difficult to eliminate and is affected by many factors such as core design, working environment, temperature, humidity, and manufacturing process. As long as the receiver successfully receives two of the three valid flags, it determines that the data channels are aligned.
  • the three data paths still have two valid flags aligned, so the three data paths are considered to be aligned.
  • This alignment is not an absolute alignment, and a certain error is allowed.
  • the clock-to-data alignment training is included in the complete data link training. If there is misalignment between data signals or misalignment between data and clock during normal use of the chip, even if other training in the data link training is not necessary, the complete data link training must be performed again, which will seriously affect the normal operation of the chip and increase power consumption.
  • the embodiments of the present disclosure provide a data transmission method, a transmitting end, a receiving end, a chip interconnection interface, a chip and an electronic device, which can realize real-time clock and data alignment between chiplets without the need for prior clock-to-data alignment training, and provide a feasible solution for removing clock-to-data alignment from data link training.
  • FIG. 3 shows a flowchart of a data transmission method provided according to at least one embodiment of the present disclosure.
  • the data transmission method 300 shown in FIG. 3 is applied to the receiving end of the chiplet interconnection interface.
  • the data transmission method 300 comprises the following steps:
  • Step S310 receiving N data signals and a first clock signal, where N is a positive integer, the number of cycles of the first clock signal is limited, and the number of cycles of each of the N data signals is less than or equal to the number of cycles of the first clock signal.
  • Step S320 locate the starting position of data in the N data signals according to the first clock signal, and obtain the data in the N data signals.
  • N data signals correspond to N data paths
  • the first clock signal corresponds to the clock path.
  • Each data path transmits 1 data signal, and each data signal carries serial data.
  • the first clock signal can be a differential clock signal.
  • N is 2, 3, 4, ..., 16, etc.
  • the value of N is related to the bandwidth required by the core particle interconnection interface. The more data paths, the greater the bandwidth of data transmission between core particles. The number of data paths can be set according to demand.
  • the data carried by each data signal is of limited length, that is, the number of cycles carrying data in each data signal is limited.
  • the number of cycles of the N data signals or the number of cycles of each data signal involved in the embodiments of the present disclosure refers to the number of cycles carrying valid data.
  • the number of cycles may also be referred to as length or cycle length, and these terms can be interchanged in the present disclosure.
  • data transmission between core particles usually has a fixed data format, that is, the data length of each transmission is fixed and equal, for example, the data format specifies that the data length is 128 bits.
  • the number of cycles of the N data signals in this embodiment is equal, that is, the number of cycles of the N data signals and the number of cycles of each data signal refer to the same number of cycles.
  • the data in each data signal does not include a valid flag.
  • the data carried in each data signal may have a predefined data format, such as a predetermined data length or number of cycles. For example, the number of cycles is 8.
  • the length or number of cycles of the data signal mentioned in the present disclosure refers to the part of the data signal that carries valid data, and the data in the data signal also refers to valid data.
  • the data signal in the present disclosure is a square wave, and the square wave may be continuously received, but the part carrying data is the part of the data signal to be discussed in the present disclosure.
  • the length of the first clock signal is also limited, which is the length of carrying a valid clock cycle, for example, the length is 4 cycles.
  • the first clock signal valid clock cycle is, for example, a cycle with clock jumps, and each valid clock cycle includes 1 rising edge and 1 falling edge of the clock.
  • the first clock signal can also be transmitted in the form of a square wave. Unlike the data signal, the first clock signal in the present disclosure is a square wave when valid, and can be a continuous low level when invalid.
  • the data in the data signal of the present disclosure does not carry a valid flag bit, but uses the first clock signal to determine the starting position of the data.
  • There is a corresponding relationship between the N data signals and the first clock signal and the corresponding relationship is that the difference in the number of cycles is less than or equal to a preset number.
  • the number of cycles of the first clock signal is limited and the number of cycles of the first clock signal is greater than or equal to the number of cycles of each data signal.
  • the number of cycles of the first clock signal is equal to the number of cycles of each data signal.
  • the length of the first clock signal needs to be greater than or equal to the length of each data signal, and the length of each data signal is the same.
  • the length of the first clock signal is greater than or greater than the length of the data signal, it is possible to ensure that the data in the data signal is completely acquired, otherwise the data may be incomplete.
  • the first clock signal determines the starting position of the data in the data signal, and the scheme disclosed in the present invention does not involve a valid flag bit, so that the position of the first time period of the first clock signal corresponds to the starting position of the data carried in the data signal, such as Figure 9.
  • the number of N data signal cycles is M
  • the number of N first clock signal cycles is M+X
  • M is an integer greater than or equal to 2
  • X is an integer greater than or equal to 0.
  • X also needs to be less than or equal to a preset number.
  • the preset number is, for example, 1, 2, 3, 4, etc.
  • the preset number can be adjusted according to demand, and the smaller the preset number, the shorter the length of the first clock signal, and thus the smaller the power consumption of sending and receiving the first clock signal.
  • the data in the data signal can be obtained according to the first clock signal.
  • the data in the data signal here refers to the valid data carried by the data signal.
  • the opposite of valid data is invalid data or empty data, which can be garbled code, preset fill value, etc., so that the reading After invalid data or empty data is obtained, it is determined that valid data in the data signal has been received.
  • the first clock signal is not continuous but has a limited length, and the first clock signal is used to locate the position of the data in the data signal.
  • the first clock signal can be used to determine and obtain the data in the data signal.
  • the data does not need to include a valid flag bit, nor does it need to perform clock-to-data alignment training in advance, and the clock-to-data alignment effect can be obtained in real time.
  • executing step S320 may include: locating the starting position of data in N data signals according to the first clock signal, and obtaining N second clock signals, the N second clock signals corresponding to the N data signals respectively; locating the starting position of data of each of the N data signals according to the N second clock signals, and converting the data in the N data signals from serial data to parallel data respectively; wherein each of the N second clock signals has the same number of cycles as the first clock signal.
  • the first clock signal is extended to N second clock signals without changing the frequency and number of cycles (or length) of the clock signal.
  • Different phase differences may exist between the N second clock signals.
  • different phases are adjusted for each second clock signal, such as the clock signals of multiple lanes in FIG. 9 having different phase differences.
  • the phase difference in this embodiment can be understood as a delay.
  • the data in the N data signals is located according to each clock signal in the N second clock signals, for example, the starting position of the data is located.
  • N data signals are sampled correspondingly using N second clock signals, thereby converting the data in each data signal from serial to parallel, wherein each second clock signal is used to sample a corresponding data signal.
  • data sampling is performed once at each falling edge of the clock or each rising edge of the clock, thereby obtaining the data in the data signal.
  • the data transmission method further includes: saving the data in the N data signals to a buffer memory correspondingly according to the N second clock signals.
  • the data in each data signal may be stored in a partial storage area of the buffer memory, or may be stored in a separate buffer memory. That is, the number of buffer memories may be 1 or N.
  • the number of buffer memories may be 1 or N.
  • a number of data blocks may be obtained, and each data block may be stored in a storage space of the buffer memory, such as an entry.
  • data in different data signals can be saved to different buffer memories, which is easier to implement and facilitate subsequent processing.
  • the buffer memory reserves a fixed storage area for the data in each data signal.
  • the buffer memory is divided into N storage areas, each storage area including multiple storage spaces.
  • saving data in the N data signals into a buffer memory includes: accessing a write pointer of the buffer memory respectively according to N second clock signals to save the data in the N data signals into the buffer memory.
  • N second clock signals are used to access write pointers of different storage areas to store data in N data signals into different storage areas.
  • the buffer memory may include N storage areas, each storage area having its own write pointer and read pointer.
  • N second clock signals are used to access write pointers of different buffer memories to store data in the N data signals into different buffer memories.
  • the buffer memory writes data by accessing the write pointer, so the write pointer can be counted by the second clock signal, such as each rising edge or each falling edge of the second clock signal causes the value of the write pointer to increase by 1, that is, points to the next storage space.
  • Each write pointer regularly cycles to point to a plurality of storage spaces in a storage area. For example, the write pointer jumps according to the address of the storage space from large to small or from small to large.
  • the data transmission method further comprises: reading data in the N data signals from the buffer memory according to a third clock signal, wherein the third clock signal is a local clock signal of the receiving end.
  • the data in the N data signals can be read using the same third clock signal.
  • the method of reading data from the buffer memory is similar to the method of saving data.
  • the read pointer of the buffer memory can be accessed according to the third clock signal to read the data in the N data signals.
  • the N buffer memories can be accessed according to the third clock signal to obtain the data in the N data signals.
  • the value of the read pointer will also be increased by 1 and point to the next storage space.
  • the number of values of the read pointer is limited or the value range is limited, and the value of the read pointer cyclically jumps within the value range.
  • the read pointers of the N buffer memories are accessed and counted according to the rising edge or falling edge in the third clock signal, so that the data in the N data signals can be read out at the same time.
  • the third clock signal can be used to read them simultaneously.
  • the length of the data in the N data signals and the number of data blocks are stipulated to be the same, and the data blocks can be stored in several similar storage spaces in different buffer memories, or the data blocks can be stored in the same order. Therefore, when reading data, the same signal can be used to trigger, so that data in different buffer memories or different storage areas can be read simultaneously and in order.
  • the third clock signal can also be a clock signal generated according to the first clock signal, for example, a third clock signal whose length exceeds the first clock signal is generated according to the frequency of the first clock signal, or the first clock signal is delayed to obtain the third clock signal.
  • the data in the N data signals can be considered to be “aligned” and saved in the buffer memory, and then the same third clock signal is further used to read the data in the buffer memory.
  • the reading process is also "aligned”. Even if the N data signals are not aligned during the transmission process (for example, the phase difference between different data signals exceeds 2 cycles), the data finally obtained is still aligned. Therefore, when the data channels are not aligned under the normal working state of the core particle, there is no need to re-train the data link.
  • the data transmission method further includes stopping reading the N buffer memories after at least one empty data is read from the buffer memory.
  • the data length of each data signal is limited, so after reading empty data from the buffer memory, it can be considered that the data reading is completed and the access to the buffer memory is stopped.
  • the data transmission method at the receiving end of the chip-grain interconnection interface is introduced above with reference to the accompanying drawings.
  • the data transmission method at the sending end of the chip-grain interconnection interface will be introduced below with reference to FIG. 4 .
  • At least one embodiment of the present disclosure also provides a data transmission method, applied to a transmitting end, comprising: sending N data signals and a first clock signal, wherein N is a positive integer, and there is a corresponding relationship between the N data signals and the first clock signal, the corresponding relationship being that the difference in the number of cycles is less than or equal to a preset number, and the first clock signal is used to obtain data in the N data signals.
  • FIG. 4 shows a flow chart of another data transmission method provided according to at least one embodiment of the present disclosure.
  • the data transmission method 400 is applicable to a sending end.
  • the data transmission method 400 includes the following steps:
  • Step S410 sending N data signals and a first clock signal, wherein N is a positive integer, the number of cycles of the first clock signal is limited, the number of cycles of each of the N data signals is less than or equal to the number of cycles of the first clock signal, and the first clock signal is used to locate the starting position of the data in the N data signals and obtain the data in the N data signals.
  • the definitions of the N data signals and the first clock signal can be found in the relevant description in FIG3 , which will not be repeated here.
  • not any clock signal having the same number of cycles as the number of cycles of the data signal can be used to obtain data in the data signal.
  • the number of cycles of each of the N data signals is M
  • the number of cycles of the first clock signal is M+X
  • M is an integer greater than or equal to 2
  • X is an integer greater than or equal to zero.
  • the number of cycles of each data signal in the N data signals is the same.
  • the number of cycles of the first clock signal is greater than or equal to the number of cycles of the data signal, so that the data in the data signal can be completely obtained.
  • M is equal to 6
  • X is equal to 1 or 2.
  • the difference between the number of cycles of the first clock signal and the number of cycles of the data signal is less than a preset value.
  • the preset value is 4 or 3.
  • N data signals and the first clock signal may be sent simultaneously; or, the first clock signal may be sent first, and then N data signals may be sent after a preset cycle length.
  • the corresponding data signal and the first clock signal may be sent simultaneously.
  • the first clock signal may be sent first, and then the data signal may be sent, thereby ensuring that the first clock signal can "cover" all cycles of the data signal.
  • the sending of the first clock signal is related to the sending of the data signal, for example, The sending determines the sending of the first clock signal.
  • the first clock signal may be set to be sent at the same time as the N data signals are sent, so that the start position of the first clock signal is aligned with the start position of the data in the N data signals.
  • the data transmission method further includes: stopping sending the first clock signal when or after the N data signals stop sending.
  • stopping sending each data signal can also be understood as completing the sending of each data signal.
  • At least one embodiment of the present disclosure further provides a chip interconnect interface, which is configured to execute any method in the first method embodiment described above.
  • the chip interconnect interface includes a processing module, which can implement the method in the method embodiment described above.
  • At least one embodiment of the present disclosure further provides a chip interconnect interface, which is configured to execute any method in the second method embodiment described above.
  • the chip interconnect interface includes a processing module, which can implement the method in the method embodiment described above.
  • Fig. 5 shows a schematic diagram of a receiving end provided by at least one embodiment of the present disclosure.
  • the receiving end 500 in this embodiment can execute the data transmission method described with reference to Fig. 3 , and its execution method can refer to the relevant description of Fig. 3 .
  • the receiving end 500 includes N data ports 510, a clock port 520 and a data processing module 530.
  • the data processing module 530 is respectively connected to the N data ports 510, and the data processing module 530 is connected to the clock port 520.
  • the receiving end 500 is connected to N data paths and 1 clock path, and each data path is connected to one data port.
  • the N data ports 510 receive N data signals correspondingly.
  • N is a positive integer.
  • the N clock ports 520 receive N first clock signals correspondingly.
  • There is a corresponding relationship between the N data signals and the first clock signal and the corresponding relationship is that the difference in the number of cycles is less than or equal to a preset number.
  • the number of cycles of the first clock signal is limited, and the number of cycles of each data signal in the N data signals is less than or equal to the number of cycles of the first clock signal.
  • the data processing module 530 locates the starting position of the data in the N data signals according to the N first clock signals, and obtains the data in the N data signals.
  • the receiving end also includes: a clock acquisition module, connected to the clock port and the data processing module, configured to acquire N second clock signals according to the first clock signal, and send the N second clock signals to the data processing module.
  • a clock acquisition module connected to the clock port and the data processing module, configured to acquire N second clock signals according to the first clock signal, and send the N second clock signals to the data processing module.
  • the clock port is not directly connected to the data processing module, but is connected to the data processing module via a clock acquisition module.
  • the clock acquisition module can extend or delay the first clock signal to obtain N second clock signals.
  • the first clock signal can be delayed and extended by circuit design, for example, by adjusting the phase difference between the second clock signals using the length of the connecting line.
  • the data processing module is configured to convert data in the N data signals from serial data to parallel data according to N second clock signals, wherein each of the N second clock signals has the same number of cycles as the first clock signal.
  • each data processing module is connected to one second clock signal and is responsible for the serial-to-parallel conversion of the data of one corresponding data signal.
  • the data processing module may include multiple processing units, each processing unit is connected to one second clock signal and is responsible for the serial-to-parallel conversion of the data of one corresponding data signal.
  • the data processing module 530 includes a serial-to-parallel converter, which can convert serial data into parallel data.
  • the data processing module 530 includes a sampler and a demultiplexer, and the sampler can sample the data in the data signal according to the second clock signal to obtain the data in the data signal, and then convert the sampled data into parallel data through the demultiplexer.
  • the receiving end further includes: a buffer memory connected to the data processing module and configured to store data in the N data signals.
  • a buffer memory connected to the data processing module and configured to store data in the N data signals.
  • the number of the buffer memories is 1 or N.
  • the receiving end 500 further includes N buffer memories 540, which are indicated by dashed boxes in the figure.
  • the N buffer memories 540 respectively store data in the N data signals.
  • the data processing module is further configured to access write pointers of N buffer memories correspondingly according to the N second clock signals to save data in the N data signals.
  • the buffer memory 540 writes data by accessing the write pointer, so the write pointer can be counted by the second clock signal. For example, each rising edge or each falling edge of the second clock signal causes the value of the write pointer to increase by 1, that is, to point to the next storage space. Since the period of the second clock signal corresponds to the period of the corresponding data signal, the write pointer is controlled according to the second clock signal. By counting the needles, the data in the data signal can be completely written into the N buffer memories 540.
  • each of the N buffer memories 540 is an asynchronous FIFO memory.
  • the receiving end further includes: a data reading module connected to the buffer memory and configured to read data from the N data signals from the buffer memory according to a third clock signal, wherein the third clock signal is a local clock signal.
  • the receiving end 500 further includes a data reading module 550.
  • the number of the data reading module 550 is 1.
  • the data reading module 550 is connected to the N buffer memories 540.
  • the data reading module 550 can read data in the N data signals from the N buffer memories 540 at the same time according to the third clock signal. It should be noted that the data reading module 550 needs to wait until all the N buffer memories 540 have written data before reading the data.
  • the data reading module is further configured to access a read pointer of the buffer memory according to a third clock signal to read data in the N data signals.
  • the data reading module 550 can simultaneously access the read pointers of the N buffer memories 540 according to the third clock signal.
  • the read pointers of the N buffer memories 540 are accessed and counted according to the rising edge or falling edge in each cycle of the third clock signal, so as to simultaneously read out the data in the N data signals.
  • the data reading module is further configured to stop reading data from the buffer memory after at least one empty data is read from the buffer memory.
  • the data reading module 550 is configured to determine that all data has been read after reading empty data from the N buffer memories 540, thereby stopping the data reading of the N buffer memories 540. For example, the data reading module 550 reads the data in the N buffer memories 540 according to the local clock signal. Since the local clock signal always exists, the data reading module 550 needs to use the empty data to determine whether all data has been read successfully. For another example, the data reading module 550 reads the data in the N buffer memories 540 according to the first clock signal or the second clock signal. The effective clock cycle length of the first clock signal and the second clock signal is limited, so that the data reading of the N buffer memories 540 can be automatically stopped after all the effective clock cycles have passed.
  • the receiving end further includes: a local clock configured to generate a local clock signal.
  • Fig. 6 shows a schematic diagram of a transmitting end provided by at least one embodiment of the present disclosure.
  • the transmitting end 600 in Fig. 6 can execute the method shown in Fig. 4 , and the execution method can refer to the relevant description of Fig. 4 .
  • the transmitting end 600 includes N data ports 610, a clock port 620 and a local clock 630.
  • the N data ports 610 send N data signals correspondingly, where N is a positive integer.
  • the clock port 620 sends a first clock signal.
  • the local clock 630 generates a first clock signal.
  • the local clock 630 is connected to the clock port 620 and the N data ports 610.
  • the N data signals and the first clock signal there is a corresponding relationship between the N data signals and the first clock signal, and the corresponding relationship is that the difference in the number of cycles is less than or equal to a preset number, for example, the number of cycles of the first clock signal is limited, and the number of cycles of each data signal in the N data signals is less than or equal to the number of cycles of the first clock signal.
  • the first clock signal is used to locate the starting position of the data in the N data signals and obtain the data in the N data signals.
  • the local clock 630 can be a phase-locked loop.
  • the number of cycles of the N data signals is M
  • the number of cycles of the N first clock signals is M+X
  • M is an integer greater than or equal to 2
  • X is an integer greater than or equal to zero.
  • the N data ports and the clock ports are configured to simultaneously send one data signal among the N data signals and a corresponding first clock signal; or, the clock port is configured to send the first clock signal first, and the N data ports are configured to send the N data signals after a preset period after the first clock signal is sent.
  • Different sending methods can be selected. For example, when the number of cycles of the data signal and the first clock signal is equal, they must be sent at the same time. When the number of cycles of the first clock signal is greater than the number of cycles of the data signal, the first clock signal and the data signal can be sent at the same time, or the first clock signal can be sent first and then the data signal. It should be noted that since the first clock signal will be used to locate the data in the data signal, when the first clock signal is sent first, it is necessary to determine the period difference or phase difference between sending the first clock signal and sending the data signal, so as to ensure that the receiving end can use the first clock signal to locate the data.
  • the chip interconnect interface further includes: a clock switch connected to the local clock and the clock port, configured to disconnect the local clock from the clock port when N data signals stop being sent or one cycle after they stop being sent.
  • the clock switch can also disconnect the local clock from the clock port after 2 cycles or multiple cycles after N data signals stop being sent.
  • the clock switch can also control the sending of the first clock signal.
  • the local clock outputs a clock signal that always exists, and the clock switch determines whether to send the first clock signal, when to send the first clock signal, and when to stop sending the first clock signal.
  • the clock switch 640 is shown in a dashed box in FIG6.
  • the clock switch 640 and the local clock The clock switch 640 is connected to the clock port 630, and is also connected to the clock port 620.
  • the clock switch 640 can control the transmission or stop of the first clock signal of the clock port 620.
  • the N clock switches 640 may be implemented using clock gating circuits or switches.
  • FIG. 7 a shows a schematic structural diagram of a clock switch provided by at least one embodiment of the present disclosure.
  • the clock switch 700 in FIG7a is a latch-based clock gating circuit.
  • the clock switch 700 includes a latch 701 and an AND gate 702.
  • the inputs of the latch 701 are the clock enable signal ClkEn and the clock signal Clock
  • the inputs of the AND gate 702 are the clock signal Clock and the output of the latch 701.
  • the clock switch 700 can turn off the clock signal when the clock enable signal ClkEn is low and inactive, that is, the first clock signal is a few clock cycles when the clock enable signal ClkEn is high and effective.
  • FIG. 7 b shows a schematic diagram of a first clock signal and a data signal provided by at least one embodiment of the present disclosure.
  • FIG7b is a schematic diagram showing a data signal and a first clock signal when a clock switch is not used.
  • Clock is a clock signal
  • Data is a data signal.
  • the data signal in FIG7b carries four valid data, namely D0, D1, D2 and D3, and the remaining oblique line parts are invalid data.
  • the first clock signal in FIG7b exists continuously.
  • FIG. 7 c shows a schematic diagram of a first clock signal and a data signal provided by at least one embodiment of the present disclosure.
  • FIG7c is a schematic diagram showing a data signal and a first clock signal when a clock switch is used.
  • ClkEn in FIG7c is an enable signal of the clock
  • Clock is a clock signal
  • Data is a data signal.
  • the data signal in FIG7c carries four valid data, namely D0, D1, D2, and D3, and the remaining oblique line portions are invalid data.
  • the first clock signal in FIG7b exists corresponding to the valid data.
  • At least one embodiment of the present disclosure further provides a chip, comprising a plurality of core particles, wherein any two of the plurality of core particles are connected via a core particle interconnection interface such as any one of the first device embodiments described above and a core particle interconnection interface such as any one of the second device embodiments described above.
  • At least one embodiment of the present disclosure further provides a chip, comprising a plurality of core particles, wherein any two of the plurality of core particles are connected via a core particle interconnection interface such as any one of the third device embodiments described above and a core particle interconnection interface such as any one of the fourth device embodiments described above.
  • FIG. 8 shows a schematic diagram of a chip provided by at least one embodiment of the present disclosure.
  • chip 800 includes a core 810 and a core 820.
  • Core 810 is a transmitting side
  • core 820 is a receiving side.
  • Fig. 8 only shows the core interconnection interface portion of core 810 and core 820.
  • the core 810 includes a serial-to-parallel converter 811, a phase-locked loop 812, a clock gating 813, a data port 814, and a clock port 815.
  • the core 820 includes a serial-to-parallel converter 821, a local clock 822, a data port 823, a clock port 824, and an asynchronous FIFO memory 825.
  • the data port 814 is connected to the data port 823 via a data path.
  • the clock port 815 is connected to the clock port 824 via a clock path.
  • FIG8 shows only one data port for illustration, and it is understandable that an actual design includes at least one data port.
  • the serial-to-parallel converter 811 receives parallel data and converts it into serial data, and the serial-to-parallel converter 821 converts the serial data into parallel data.
  • the input of the phase-locked loop 812 is the clock signal Clock, which can output the clock signal to the clock gating 813 and the serial-to-parallel converter 811 (only one clock signal is output in the figure).
  • Another input of the clock gating 813 is the clock enable signal ClkEn.
  • the clock port 824 sends the received clock signal to the serial-to-parallel converter 821, and the serial-to-parallel converter 821 inputs a clock signal into the asynchronous FIFO memory 825, and the clock signal controls the write pointer count of the asynchronous FIFO memory 825.
  • the local clock 822 inputs another clock signal into the asynchronous FIFO memory 825, and the clock signal controls the read pointer count of the asynchronous FIFO memory 825.
  • the core particle 820 may include multiple serial-to-parallel converters 821 and multiple asynchronous FIFO memories 825.
  • the core particle 820 may also include a clock acquisition module connected to the clock port 824 and the multiple serial-to-parallel converters 821.
  • the clock acquisition module may expand one clock signal received from the clock port 824 into multiple clock signals, and the multiple clock signals are input into multiple serial-to-parallel converters 821 accordingly.
  • multiple asynchronous FIFOs 825 are connected to multiple serial-to-parallel converters 821, and each serial-to-parallel converter 821 inputs one clock signal into a corresponding asynchronous FIFO memory 825.
  • the local clock 822 is connected to multiple asynchronous FIFO memories 825 and provides a local clock signal to the multiple asynchronous FIFO memories 825.
  • FIG. 9 shows a timing diagram of a method for data transmission after chiplet interconnection according to at least one embodiment of the present disclosure.
  • lane represents the control signal from the data path
  • FIFO represents the control signal of the buffer memory.
  • laneY_gated_clock represents the first clock signal of data path Y, where Y is 0-N.
  • laneY_wrpt represents the write pointer signal to the buffer memory.
  • FIFO_read_clock is the second clock signal, which is a continuously existing clock signal.
  • FIFO_rdpt is the read pointer signal of the buffer memory.
  • FIFO_read is the read enable signal.
  • FIFO_read_sync is the synchronous read signal of the buffer memory.
  • FIFO_valid is the valid signal of the buffer memory.
  • the first clock signal and the read pointer signal of each lane correspond to each other, which indicates that the data in the data signal is written to the buffer memory when there is a rising edge or a falling edge of the first clock signal.
  • the values of the read pointer and the write pointer of each buffer memory are not equal.
  • the read enable signal FIFO_read is pulled high and becomes valid.
  • the read enable signal FIFO_read is synchronized to the FIFO_read_clock signal, and the data is read out in the next cycle (FIFO_valid becomes high and valid in the next cycle).
  • the values 0, 1, 2 and 3 of the pointer signal in the figure represent the values of the pointer, and the data read is the corresponding value.
  • the value of FIFO_rdpt is 0, and the data read is the corresponding data of the laneY_wrpt value of 0. Therefore, when the value of FIFO_rdpt is 1 to 3, the data at the position of the write pointer value 1 to 3 in each lane is read accordingly.
  • laneY_gated_clock is turned off or disconnected. Since FIFO_read_clock is still valid, data will continue to be read, but empty data will be read. As long as empty data is read, the read enable signal will be pulled low and become invalid, waiting for the next data signal transmission.
  • At least one embodiment of the present disclosure provides an electronic device, including the chip in the above embodiment.
  • FIG. 10 shows a schematic diagram of an electronic device provided by at least one embodiment of the present disclosure.
  • the electronic device 1000 includes a chip 1001.
  • the chip 1001 is, for example, the chip 800 shown in FIG8.
  • the electronic device 1000 may be any device with a computing function, such as a computer, a server, a smart phone, a tablet computer, etc., and the embodiments of the present disclosure are not limited thereto.
  • step flow charts and the above method descriptions in this application are only illustrative examples and are not intended to require or imply that the steps of each embodiment must be performed in the order given, and some steps can be performed in parallel, independently of each other, or in other appropriate orders.
  • words such as “secondly”, “then”, “next”, etc. are not intended to limit the order of the steps; these words are only used to guide the reader to read through the descriptions of these methods.

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Abstract

本公开的实施例提供用于芯粒互联接口的数据传输方法及芯粒互联接口。数据传输方法应用于接收端，该方法包括：接收N个数据信号和第一时钟信号，第一时钟信号的周期数量有限，N个数据信号中的每个数据信号的周期数量小于或等于第一时钟信号的周期数量，N为正整数；根据第一时钟信号，定位N个数据信号中的数据的开始位置，并获取N个数据信号中的数据。本公开的实施例接收端使用第一时钟信号来获取数据信号中的数据，而不是使用有效标志位，从而无需预先进行时钟到数据对齐训练，并且还能够实时对齐。

Description

用于芯粒互联接口的数据传输方法及芯粒互联接口
本申请要求于2023年6月30日递交的中国专利申请第202310802966.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种数据传输方法、发送端、接收端、芯粒互联接口、芯片及电子设备。
背景技术
芯粒(Chiplet)是一种具有一定功能且含有封装内互联接口的单元芯片，其为芯片设计技术的最新发展。Chiplet技术通过使用多个芯粒实现芯片设计，不仅可以降低成本，还可以提升芯片的性能。
芯粒间的互连自然成为影响芯片性能的重要因素。目前有串行总线和并行总线两种实现方式，其中并行总线互连是当下的主流。并行总线可以给两个芯粒之间较短的延迟，还能够通过增加总线带宽来扩大芯粒间的带宽。
实现了物理层面的互连之后，芯粒互联还需要完成数据链路的训练，其中的时钟到数据对齐是数据传输必不可少的一个环节。但是时钟到数据对齐是属于数据链路的训练的组成部分，若在训练完成之后出现时钟与数据不对齐的情况，就需要重新进行数据链路的完整训练，这严重影响了芯片的正常工作。
发明内容
本公开的实施例提供了数据传输方法、发送端、接收端、芯粒互联接口、芯片及电子设备。
第一方面，本公开至少一个实施例提供一种数据传输方法，应用于接收端，包括：接收N个数据信号和第一时钟信号，第一时钟信号的周期数量有限，N个数据信号中的每个数据信号的周期数量小于或等于第一时钟信号的 周期数量，N为正整数；根据第一时钟信号，定位N个数据信号中的数据的开始位置，并获取N个数据信号中的数据。
例如，在本公开一实施例提供的方法中，根据第一时钟信号，定位N个数据信号中的数据的开始位置，并获取N个数据信号中的数据，包括：根据第一时钟信号，获取N个第二时钟信号，N个第二时钟信号分别对应于N个数据信号；根据N个第二时钟信号，分别定位N个数据信号中的每个数据信号的数据的开始位置，并分别将N个数据信号中的数据从串行数据转换为并行数据；其中，N个第二时钟信号中的每一个第二时钟信号具有与第一时钟信号相同的周期数量。
例如，在本公开一实施例提供的方法中，在获取N个数据信号中的数据之后，方法还包括：根据N个第二时钟信号，对应地将N个数据信号中的数据保存到缓冲存储器。
例如，在本公开一实施例提供的方法中，方法还包括：根据第三时钟信号，从缓冲存储器中读取N个数据信号中的数据，其中，第三时钟信号为接收端的本地时钟信号。
例如，在本公开一实施例提供的方法中，根据第三时钟信号，从缓冲存储器中读取数据信号中的数据，包括：根据第三时钟信号，访问缓冲存储器的读指针，以读取N个数据信号中的数据。
例如，在本公开一实施例提供的方法中，根据N个第二时钟信号，对应地将N个数据信号中的数据保存到缓冲存储器，包括：根据N个第二时钟信号，分别访问缓冲存储器的写指针，以将N个数据信号中的数据保存到缓冲存储器。
例如，在本公开一实施例提供的方法中，方法还包括：在从缓冲存储器中读取到至少一个空数据之后，停止对缓冲存储器的读取。
例如，在本公开一实施例提供的方法中，N个数据信号中的每个数据信号的周期数量为M，第一时钟信号的周期数量为M+X，M为大于或等于2的整数，X为大于或等于0的整数。
第二方面，本公开至少一个实施例提供一种数据传输方法，应用于发送端，包括：发送N个数据信号和第一时钟信号，其中，N为正整数，第一时钟信号的周期数量有限，N个数据信号中的每个数据信号的周期数量小于或 等于所述第一时钟信号的周期数量，并且第一时钟信号用于定位N个数据信号中的数据的开始位置并获取N个数据信号中的数据。
例如，在本公开一实施例提供的方法中，发送N个数据信号和第一时钟信号，包括：同时发送N个数据信号和第一时钟信号；或者，先发送第一时钟信号，然后在预设周期之后发送N个数据信号。
例如，在本公开一实施例提供的方法中，方法还包括：在N个数据信号停止发送时或者停止发送之后，停止发送第一时钟信号。
例如，在本公开一实施例提供的方法中，N个数据信号中的每个数据信号的周期数量为M，第一时钟信号的周期数量为M+X，M为大于或等于2的整数，X为大于或等于0的整数。
第三方面，本公开至少一个实施例提供一种接收端，应用于芯粒互联接口，包括：N个数据端口，被配置为接收N个数据信号，N为正整数；时钟端口，被配置为接收第一时钟信号，第一时钟信号的周期数量有限，N个数据信号中的每个数据信号的周期数量小于或等于第一时钟信号的周期数量；数据处理模块，与N个数据端口及时钟端口连接，被配置为根据第一时钟信号，定位N个数据信号中的数据的开始位置，并获取N个数据信号中的数据。
例如，在本公开一实施例提供的接收端中，接收端还包括：时钟获取模块，与时钟端口及数据处理模块连接，被配置根据将第一时钟信号，获取N个第二时钟信号，并将N个第二时钟信号发送至数据处理模块；数据处理模块被配置为根据N个第二时钟信号，分别将N个数据信号中的数据从串行数据转换为并行数据；其中，N个第二时钟信号中的每一个第二时钟信号具有与第一时钟信号相同的周期数量。
例如，在本公开一实施例提供的接收端中，接收端还包括：缓冲存储器，与数据处理模块连接，被配置为保存N个数据信号中的数据。
例如，在本公开一实施例提供的接收端中，数据处理模块还被配置为根据N个第二时钟信号，分别访问缓冲存储器的写指针，以将N个数据信号中的数据保存到缓冲存储器。
例如，在本公开一实施例提供的接收端中，接收端还包括：数据读取模块，与缓冲存储器连接，被配置为根据第三时钟信号从缓冲存储器中读取出 N个数据信号中的数据，其中，第三时钟信号为接收端的本地时钟信号。
例如，在本公开一实施例提供的接收端中，数据读取模块还被配置为根据第三时钟信号，访问缓冲存储器的读指针，以读取N个数据信号中的数据。
例如，在本公开一实施例提供的接收端中，数据读取模块还被配置为在从缓冲存储器中读取到至少一个空数据之后，停止对缓冲存储器的数据读取。
例如，在本公开一实施例提供的接收端中，缓冲存储器为异步FIFO存储器。
例如，在本公开一实施例提供的接收端中，接收端还包括：本地时钟，被配置为生成本地时钟信号。
例如，在本公开一实施例提供的接收端中，N个数据信号中的每个数据信号的周期数量为M，第一时钟信号的周期数量为M+X，M为大于或等于2的整数，X为大于或等于0的整数。
第四方面，本公开至少一个实施例提供一种发送端，应用于芯粒互联接口，包括：N个数据端口，被配置为对应地发送N个数据信号，N为正整数；时钟端口，被配置为发送第一时钟信号；本地时钟，与时钟端口及N个数据端口连接，被配置为生成第一时钟信号；其中，第一时钟信号的周期数量有限，N个数据信号中的每个数据信号的周期数量小于或等于第一时钟信号的周期数量，并且第一时钟信号用于定位N个数据信号中的数据的开始位置并获取N个数据信号中的数据。
例如，在本公开一实施例提供的发送端中，N个数据端口和时钟端口被配置为同时发送N个数据信号和第一时钟信号；或者，时钟端口被配置为先发送第一时钟信号，N个数据端口被配置为在第一时钟信号发送后的预设周期之后发送N个数据信号。
例如，在本公开一实施例提供的发送端中，发送端还包括：时钟开关，与本地时钟连接以及与时钟端口连接，被配置为在N个数据信号停止发送时或者停止发送的一个周期之后，断开本地时钟与时钟端口的连接。
例如，在本公开一实施例提供的发送端中，N个数据信号的每个数据信号的周期数量为M，第一时钟信号的周期数量为M+X，M为大于或等于2的整数，X为大于或等于0的整数。
第五方面，本公开至少一个实施例还提供一种芯粒互联接口，被配置为 执行如上述第一方面中任一项的方法。
第六方面，本公开至少一个实施例还提供一种芯粒互联接口，被配置为执行如上述第二方面中任一项的方法。
第七方面，本公开至少一个实施例还提供一种芯粒互联接口，包括如第三方面中任一项的接收端。
第八方面，本公开至少一个实施例还提供一种芯粒互联接口，包括如第三方面中任一项的发送端。
第九方面，本公开至少一个实施例还提供一种芯片，包括多个芯粒，其中，多个芯粒中的任意两个芯粒通过如第五方面或第七方面的芯粒互联接口和如第六方面或第八方面的芯粒互联接口连接。
第十方面，本公开至少一个实施例提供一种电子设备，包括如第九方面的芯片。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1示出了一种现有技术中的芯粒互联接口的示意图；
图2示出了一种现有技术中芯粒间进行时钟到数据对齐的示意图；
图3示出了根据本公开至少一个实施例提供的数据传输方法的流程图；
图4示出了根据本公开至少一个实施例提供的又一种数据传输方法的流程图；
图5示出了本公开至少一个实施例提供的接收端的示意图；
图6示出了本公开至少一个实施例提供的发送端的示意图；
图7a示出了本公开至少一个实施例提供的时钟开关的结构示意图；
图7b示出了本公开至少一个实施例提供的第一时钟信号和数据信号的示意图；
图7c示出了本公开至少一个实施例提供的第一时钟信号和数据信号的有一种示意图；
图8示出了本公开至少一个实施例提供的芯片的示意图；
图9示出了本公开至少一个实施例提供的芯粒互联后的数据传输方法的时序图；以及
图10示出了本公开至少一个实施例提供的电子设备的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
数据链路的训练通常是在芯粒的初始化完成之后进行的，其需要作为发送侧的芯粒和作为接收侧的芯粒协作完成，从而使得接收侧的芯粒可以找到最合适的数据采样窗口。完整的数据链路的训练包括多个部分，例如偏置Offset校准、参考电源Verf校准、数据通路去歪斜(deskew)、时钟到数据对齐(CDA，Clock and Data Alignment)、并行数据保序(reorder)和数据检查等。时钟到数据对齐是调整数据和时钟之间的相位，最终获得合适的采样相位。
图1示出了一种现有技术中的芯粒互联接口的示意图。
在图1中，芯粒A和芯粒B通过芯粒互联接口110和芯粒互联接口120实现连接。芯粒A是发送侧，芯粒B是接收侧。芯粒互联接口110包括多个 数据端口111、时钟端口112和本地时钟113。芯粒互联接口120包括多个数据端口121、时钟端口122、时钟接收模块123和数据采样模块124。多个数据端口111和多个数据端口121的数据端口数量相等，其分别通过多个数据通路连接。时钟端口112通过时钟通路连接到时钟端口122。本地时钟113产生时钟信号，并将时钟信号发送给多个数据端口111和时钟端口112。时钟接收模块123接收本地时钟113产生的时钟信号并对该时钟信号进行调整，并将调整后的时钟信号发送给数据采样模块124。数据采样模块124利用该时钟信号进行数据采样。该时钟信号可以是差分时钟信号。时钟信号和数据信号是持续发送给芯粒B的，数据信号携带有效数据和空数据，即数据信号携带的不全是有效数据。有效数据是芯粒A希望发送给芯粒B的，芯粒A是按照预设数据格式传输有效数据，每一次发送的有效数据的长度有限，有效数据之间不是连续发送的，其会存在一些时间间隙，空数据则是用来填充有效数据之间的间隙。因此，芯粒A和芯粒B之间的数据传输会存在多个数据通道之间的数据不对齐。在现有技术中，需要对时钟到数据对齐进行预先的训练，从而才能接收到准确的数据。
图2示出了一种现有技术中芯粒间进行时钟和数据对齐的示意图。
通常使用有效标志位来进行时钟到数据对齐的训练。图2中的芯粒A和芯粒B可以是图1所示的芯粒A和芯粒B。有效标志位为vld，其取值为1，发送端将其复制3次变成长度为3bit的数据，使用每个数据通道的前3bit携带有效标志位。有效标志位可以表示一段有效数据的开始。根据有效标志位，芯粒B可以从每个数据信号中准确的定位到有效数据。有效数据又具有约定的数据格式，包括数据长度。因此芯粒B在发现有效标志位之后，就能够定位到一段有效数据。图2中，从芯粒A中的发送出的3个数据信号是对齐的。芯粒B接收到的3个数据信号之间存在一定的相位差或延迟，这种延迟是难以消除的，其受到芯粒设计、工作环境、温度、湿度、制造工艺等多种因素的影响。接收端只要成功接收到3个有效标志位中的2个有效标志位就判断数据通道之间是对齐的。
图2中的下方的两个数据通路和上方的第一个数据通路之间虽然存在一定相位差，但3个数据通路仍有2个有效标志位对齐，因此认定这三个数据通路是对齐的。这种对齐方式并不是绝对的对齐，其允许一定的误差存在。 然而时钟到数据对齐的训练包含在完整的数据链路训练中，如果在芯片正常使用的过程中出现数据信号之间的不对齐、数据和时钟不对齐，即使数据链路训练中的其他训练没有必要进行，也必须重新进行完整的数据链路训练，对芯片的正常工作造成严重影响，还增加功耗。
基于此，本公开的实施例提供了数据传输方法、发送端、接收端、芯粒互联接口、芯片及电子设备，能够实现芯粒间实时的时钟和数据对齐，无需预先的时钟到数据对齐训练，并且提供了将时钟到数据对齐从数据链路训练中移除的可行方案。
下面结合附图对本公开所提供的实施例进行描述。
图3示出了根据本公开至少一个实施例提供的数据传输方法的流程图。
图3所示的数据传输方法300应用于芯粒互联接口的接收端。
数据传输方法300包括以下步骤：
步骤S310，接收N个数据信号和第一时钟信号，N为正整数，第一时钟信号的周期数量有限，N个数据信号中的每个数据信号的周期数量小于或等于第一时钟信号的周期数量。
步骤S320，根据第一时钟信号，定位N个数据信号中的数据的开始位置，并获取N个数据信号中的数据。
在本公开中，N个数据信号对应于N个数据通路，第一时钟信号对应于时钟通路。每个数据通路传输1个数据信号，每个数据信号携带的是串行数据。第一时钟信号可以是差分时钟信号。例如N为2、3、4、……、16等。N的取值跟芯粒互联接口所需的带宽相关，数据通路越多，芯粒间的数据传输的带宽越大，数据通路的数量可以根据需求来设置。
每个数据信号携带的数据是长度有限，即每个数据信号中携带数据的周期数量有限。本公开的实施例中所涉及的N个数据信号的周期数量或者每个数据信号的周期数量都是指携带有效数据的周期数量。周期数量也可能被称为长度或周期长度，这些术语可以在本公开中互换。可以理解地，芯粒之间的数据传输通常有固定的数据格式，即每次传输的数据长度是固定的并且是相等的，例如数据格式规定数据长度为128位。本实施例中的N个数据信号的周期数量是相等的，即N个数据信号的周期数量和每个数据信号的周期数量指的是相同的周期数量。
每个数据信号中的数据不包括有效标志位。每个数据信号中携带的数据可以具有预定义的数据格式，比如具有预定的数据长度或周期数量。例如，周期数量为8。为了便于描述，在本公开中提及的数据信号的长度或周期数量都是指数据信号中携带有效数据的部分，数据信号中的数据也是指有效数据。本公开中的数据信号是方波，方波可能会被持续接收到，但是其中携带有数据的部分才是本公开要讨论的数据信号的部分。
相应地，第一时钟信号的长度也有限，该长度为携带有效时钟周期的长度，例如该长度为4个周期。第一时钟信号有效时钟周期例如是具有时钟跳变的周期，每个有效时钟周期包括时钟的1个上升沿和1个下降沿。第一时钟信号也可以是方波的形式传输的，与数据信号不同的是，本公开中的第一时钟信号有效时是方波，无效时可以是持续的低电平。
本公开中的数据信号中的数据不携带有效标志位，而是利用第一时钟信号来确定数据的开始位置。N个数据信号与第一时钟信号存在对应关系，对应关系为周期数量相差小于或等于预设数量。例如，第一时钟信号的周期数量有限并且第一时钟信号的周期数量大于或等于每个数据信号的周期数量。优选地，第一时钟信号的周期数量等于每个数据信号的周期数量。
第一时钟信号的长度需要大于或等于每个数据信号的长度，每个数据信号的长度是相同的。第一时钟信号的长度大于或大于数据信号的长度时，才能够保证数据信号中的数据被完整的获取，否则可能出现数据残缺。例如，可以认为是第一时钟信号决定了数据信号中数据的开始位置，本公开的方案不涉及有效标志位，从而第一时钟信号的第一时间周期的位置就对应了数据信号中携带的数据的开始位置，例如图9。例如，N个数据信号周期数量为M，N个第一时钟信号的周期数量为M+X，M为大于或等于2的整数，X为大于或等于0的整数。X还需要小于或等于预设数量。预设数量例如是1、2、3、4等。预设数量可以根据需求进行调整，预设数量越小，第一时钟信号的长度越短，从而发送和接收第一时钟信号的功耗就越小。
在执行步骤S320时，由于第一时钟信号和N个数据信号之间的对应关系。因此可以根据第一时钟信号得到数据信号中的数据。这里的数据信号中数据是指数据信号携带的有效数据。本实施例中，与有效数据相对的是无效数据或者空数据，无效数据或空数据可以是乱码、预设填充数值等，从而读 取到无效数据或空数据之后就确定数据信号中的有效数据已经接收完。例如，本实施例中，第一时钟信号不是持续存在而是长度有限的，将第一时钟信号用来定位数据信号中的数据的位置。
按照本实施例所提供的方法，接收的N个数据信号和第一时钟信号存在对应关系，从而可以利用第一时钟信号来确定并获取数据信号中的数据，数据中无需包括有效标志位，亦无需预先进行时钟到数据对齐的训练，并且可以实时得到时钟到数据对齐的效果。
在一些实施例中，执行步骤S320可以包括：根据第一时钟信号，定位N个数据信号中的数据的开始位置，并获取N个第二时钟信号，N个第二时钟信号分别对应于N个数据信号；根据N个第二时钟信号，分别定位N个数据信号中的每个数据信号的数据的开始位置，并分别将N个数据信号中的数据从串行数据转换为并行数据；其中，N个第二时钟信号中的每一个第二时钟信号具有与第一时钟信号相同的周期数量。
例如，将第一时钟信号扩展出N个第二时钟信号，不改变时钟信号的频率和周期数量(或长度)。N个第二时钟信号之间可以存在不同的相位差，例如获取N个第二时钟信号时，对每个第二时钟信号调整不同的相位，如图9中的多个lane的时钟信号具有不同的相位差。本实施例中的相位差可以被理解为延迟。然后根据N个第二时钟信号中的每个时钟信号对N个数据信号中的数据进行定位，例如定位数据的开始位置。
例如，利用N个第二时钟信号对应地对N个数据信号进行采样，从而将每个数据信号中的数据从串行转换为并行，其中每个第二时钟信号被用于对应的1个数据信号的采样。比如在每个时钟下降沿或每个时钟上升沿进行一次数据采样，从而得到数据信号中的数据。
在一些实施例中，在获取N个数据信号中的数据之后，数据传输方法还包括：根据N个第二时钟信号，对应地将N个数据信号中的数据保存到缓冲存储器。
可选地，每个数据信号中的数据可以被保存到缓冲存储器的部分存储区域，或者被单独保存到1个缓冲存储器中。即，缓冲存储器的数量可以为1个或N个。例如，将数据信号中的数据解串行之后，得到若干个数据块，每个数据块可以存储在缓冲存储器的一个存储空间内，例如一个条目entry内、 一段地址空间内。不同数据信号中的数据可以被保存到不同的缓冲存储器，这样更容易实现并便于后续的处理。
在将N个数据信号中的数据保存到一个缓冲存储器的不同区域内时，缓冲存储器为每个数据信号中的数据预留固定的存储区域。例如缓冲存储器分为N个存储区域，每个存储区别包括多个存储空间。
在一些实施例中，将N个数据信号中的数据保存到缓冲存储器，包括：根据N个第二时钟信号，分别访问缓冲存储器的写指针，以将N个数据信号中的数据保存到缓冲存储器。
例如，在仅有一个缓冲存储器时，利用N个第二时钟信号来访问不同存储区域的写指针，以将N个数据信号中的数据存储到不同的存储区域。缓冲存储器可以包括N个存储区域，每个存储区域有自己的写指针以及读指针。
又如，在有N个缓冲存储器时，利用N个第二时钟信号来访问不同的缓冲存储器的写指针，以将N个数据信号中的数据存储到不同的缓冲存储器。
例如，缓冲存储器是利用访问写指针的方式写入数据，从而可以利用第二时钟信号对写指针进行计数，比如第二时钟信号的每一次上升沿或每一次下降沿使得写指针的取值加1，即指向下一个存储空间。每个写指针有规律的循环指向一个存储区域中的若干个存储空间。例如，写指针按照存储空间的地址由大到小或者由小到大来跳转。
在一些实施例中，数据传输方法还包括：根据第三时钟信号，从缓冲存储器中读取N个数据信号中的数据，其中，第三时钟信号为接收端的本地时钟信号。可以利用同一个第三时钟信号，对N个数据信号中的数据进行读取。
从缓冲存储器中读取数据的方式和保存数据的方式类似。例如，可以根据第三时钟信号，访问缓冲存储器的读指针，以读取N个数据信号中的数据。比如在有N个缓冲存储器时，可以根据第三时钟信号去访问N个缓冲存储器，从而得到N个数据信号中的数据。缓冲存储器的读指针被访问之后，读指针的取值也会加1，并指向下一个存储空间。可选地，读指针的取值数量有限或者取值范围有限，读指针的取值在该取值范围内循环跳转。例如，根据第三时钟信号中的上升沿或下降沿对N个缓冲存储器的读指针进行访问以及计数，从而就可以同时读取出N个数据信号中的数据。
可选地，N个数据信号中的数据被保存到缓冲存储器之后，可以被同时 读取出来。例如，在确定所有的N个数据信号中的数据都被对应保存到缓冲存储器之后，可以使用第三时钟信号来同时进行读取。N个数据信号中的数据的长度和以及数据块的数量是规定相同的，数据块可以保存在不同缓冲存储器的相似的若干个存储空间中，或者数据块可以被按照相同的顺序进行保存。因此，在读取数据时，就可以使用同一个信号来触发，使得不同缓冲存储器或不同存储区域中的数据可以被同时且有序的读取。第三时钟信号还可以是根据第一时钟信号生成的时钟信号，例如根据第一时钟信号的频率来生成长度超过第一时钟信号的第三时钟信号，或者对第一时钟信号进行延迟得到第三时钟信号。
采用本实施例中的方法，N个数据信号中的数据可以被认为是“对齐的”保存到缓冲存储器，而后进一步使用同一个第三时钟信号来读取缓冲存储器中的数据，该读取过程也是“对齐的”，即使传输过程中N个数据信号之间不对齐(例如，不同数据信号之间的相差超过2个周期)，最终得到的数据仍旧是对齐的，因此在芯粒正常工作状态下数据通道之间出现不对齐，也无需重新进行数据链路的训练。进一步，采用本实施例中的方法，可以不需要在数据链路的训练阶段进行时钟到数据对齐的训练，直接通过N个数据信号和第一时钟信号对应发送/接收的方式来完成数据对齐，由于无需进行时钟到数据对齐的训练以及重复的数据链路的训练，不仅减少设计的复杂度还可以降低功耗。
在一些实施例中，数据传输方法还包括在从缓冲存储器中读取到至少一个空数据之后，停止对N个缓冲存储器的读取。
本实施例中的每个数据信号中的数据长度有限，从而在从缓冲存储器中读取到空数据之后，就可以认为数据读取已经完成，并停止访问缓冲存储器。
上文中结合附图介绍了芯粒互联接口的接收端的数据传输方法，下面将结合图4介绍芯粒互联接口的发送端的数据传输方法。
本公开至少一个实施例还提供一种数据传输方法，应用于发送端，包括：发送N个数据信号和第一时钟信号，其中，N为正整数，N个数据信号与第一时钟信号存在对应关系，对应关系为周期数量相差小于或等于预设数量，并且第一时钟信号用于获取N个数据信号中的数据。
图4示出了根据本公开至少一个实施例提供的又一种数据传输方法的流 程图。数据传输方法400适用于发送端。
在图4中，数据传输方法400包括以下步骤：
步骤S410，发送N个数据信号和第一时钟信号，其中，N为正整数，第一时钟信号的周期数量有限，N个数据信号中的每个数据信号的周期数量小于或等于第一时钟信号的周期数量，并且第一时钟信号用于定位N个数据信号中的数据的开始位置并获取N个数据信号中的数据。
N个数据信号和第一时钟信号的定义可参见图3中的相关描述，在此不再赘述。本实施例中，并不是任意一个周期数量和数据信号的周期数量相同的时钟信号都可以用来获取数据信号中的数据。第一时钟信号和N个数据信号是存在对应关系的，例如，第一时钟信号和N个数据信号在发送时，是对齐发送的、或者是同时发送的，从而第一时钟信号的第一个边沿和N个数据信号中的第一个携带有效数据的周期对齐。对于接收端，经过设计或数据去歪斜训练之后，该对应关系没有发生变化。
可选地，N个数据信号中的每个数据信号的周期数量为M，第一时钟信号的周期数量为M+X，M为大于或等于2的整数，X为大于或等于0的整数。
N个数据信号中的每个数据信号的周期数量相同。第一时钟信号的周期数量大于或等于数据信号的周期数量，这样可以保证对完整获得数据信号中的数据。例如，M等于6，X等于1或2。可选地，第一时钟信号的周期数量与数据信号的周期数量的差值小于预设值。例如，预设值是4或3。在第一时钟信号的周期数量不超出数据信号的周期数量太多时，可以节省用于接收第一时钟信号的功率。
在进一步的实施例中，在执行步骤S410时，可以同时发送N个数据信号和第一时钟信号；或者，先发送第一时钟信号，然后在预设周期长度之后发送N个数据信号。
例如，在第一时钟信号的周期数量等于或者大于数据信号的周期数量时，可以同时发送对应的数据信号和第一时钟信号。在第一时钟信号的周期数量大于数据信号的周期数量时，可以先发送第一时钟信号，然后再发送数据信号，从而保证第一时钟信号的可以“覆盖”数据信号的所有周期。
可选地，第一时钟信号的发送与数据信号的发送相关，例如数据信号的 发送决定了第一时钟信号的发送。例如，可以设置第一时钟信号在N个数据信号发送的同时进行发送，从而第一时钟信号的开始位置和N个数据信号中的数据的开始位置对齐。
在一些实施例中，数据传输方法还包括：在N个数据信号停止发送时或者停止发送之后，停止发送第一时钟信号。
例如，每个数据信号停止发送也可以理解为每个数据信号发送完成，在所有数据信号停止发送时，可以选择将第一时钟信号停止发送，或者让第一时钟信号继续发送几个周期。如此可以既保证第一时钟信号的周期数量大于或等于数据信号的周期数量，还可以停止继续后续不会被用到的时钟周期，即在不发送数据信号的时候停止发送时钟信号，从而可以降低发送时钟信号带来的功耗。
本公开至少一个实施例还提供一种芯粒互联接口，被配置为执行如上述第一个方法实施例中任一项的方法。例如，芯粒互联接口中有处理模块，其可以实现如上述方法实施例中的方法。
本公开至少一个实施例还提供一种芯粒互联接口，被配置为执行如上述第二个方法实施例中任一项的方法。例如，芯粒互联接口中有处理模块，其可以实现如上述方法实施例中的方法。
图5示出了本公开至少一个实施例提供的接收端的示意图。本实施例中的接收端500可以执行参照图3描述的数据传输方法，其执行方式可参见图3的相关描述。
在图5中，接收端500包括N个数据端口510、时钟端口520和数据处理模块530。数据处理模块530分别与N个数据端口510连接，以及数据处理模块530与时钟端口520连接。接收端500连接N个数据通路和1个时钟通路，每个数据通路连接到一个数据端口。
其中，N个数据端口510对应地接收N个数据信号。N为正整数。N个时钟端口520对应地接收N个第一时钟信号。N个数据信号与第一时钟信号存在对应关系，对应关系为周期数量相差小于或等于预设数量。例如，第一时钟信号的周期数量有限，N个数据信号中的每个数据信号的周期数量小于或等于第一时钟信号的周期数量。数据处理模块530根据N第一时钟信号，定位N个数据信号中的数据的开始位置，并获取N个数据信号中的数据。
可选地，接收端还包括：时钟获取模块，与时钟端口及数据处理模块连接，被配置根据将第一时钟信号，获取N个第二时钟信号，并将N个第二时钟信号发送至数据处理模块。
在此实现方式中，时钟端口不直接与数据处理模块连接，而是经由时钟获取模块连接到数据处理模块。时钟获取模块可以对第一时钟信号进行扩展或延迟，以得到N个第二时钟信号。在没有时钟获取模块的实现方式中，可以通过电路的设计，对第一时钟信号进行延迟和扩展，例如利用连接线的长度来调整第二时钟信号之间的相位差。
进一步可选地，数据处理模块被配置为根据N个第二时钟信号，分别将N个数据信号中的数据从串行数据转换为并行数据。其中，N个第二时钟信号中的每一个第二时钟信号具有与第一时钟信号相同的周期数量。
例如在数据处理模块的数量为N时，每个数据处理模块连接1个第二时钟信号，并负责对应的1个数据信号的数据的串并转换。在数据处理模块的数量为1时，数据处理模块可以包括多个处理单元，每个处理单元连接1个第二时钟信号并负责对应的1个数据信号的数据的串并转换。
例如，数据处理模块530串并转换器，串并转换器可以将串行数据转换为并行数据。又如，数据处理模块530包括采样器和解复用器，采样器可以根据第二时钟信号对数据信号中的数据进行采样，从而获得数据信号中的数据，然后通过解复用器将采样后的数据变为并行数据。
在一些实施例中，接收端还包括：缓冲存储器，与数据处理模块连接，被配置为保存N个数据信号中的数据。例如，缓冲存储器的数量为1个或N个。
例如，接收端500还包括N个缓冲存储器540，N个缓冲存储器540在图中用虚线框表示。N个缓冲存储器540分别保存N个数据信号中的数据。
在一些实施例中，数据处理模块还被配置为根据N个第二时钟信号，对应地访问N个缓冲存储器的写指针，以保存N个数据信号中的数据。
例如，缓冲存储器540是利用访问写指针的方式写入数据，从而可以利用第二时钟信号对写指针进行计数，比如第二时钟信号的每一次上升沿或每一次下降沿使得写指针的取值加1，即指向下一个存储空间。由于第二时钟信号的周期与相应的数据信号的周期对应，从而根据第二时钟信号控制写指 针计数，就能够将数据信号中的数据完整的写入N个缓冲存储器540。
可选地，N个缓冲存储器540中的每个缓冲存储器为异步FIFO存储器。
在一些实施例中，接收端还包括：数据读取模块，与缓冲存储器连接，被配置为根据第三时钟信号，从缓冲存储器中读取出N个数据信号中的数据，其中，第三时钟信号为本地时钟信号。
例如，接收端500还包括数据读取模块550。数据读取模块550的数量为1。数据读取模块550与N个缓冲存储器540连接。数据读取模块550可以根据第三时钟信号同时从N个缓冲存储器540中读取出N个数据信号中的数据。需要注意的是数据读取模块550需要等待所有的N个缓冲存储器540都写入数据之后，再进行数据的读取。
在一些实施例中，数据读取模块还被配置为根据第三时钟信号，访问缓冲存储器的读指针，以读取N个数据信号中的数据。
例如，数据读取模块550可以根据第三时钟信号，同时访问N个缓冲存储器540各自的读指针。例如，根据第三时钟信号中的每个周期内的上升沿或下降沿对N个缓冲存储器540的读指针进行访问以及计数，从而同时读取出N个数据信号中的数据。
在一些实施例中，数据读取模块还被配置为在从缓冲存储器中读取到至少一个空数据之后，停止对缓冲存储器的数据读取。
例如，数据读取模块550被配置为从N个缓冲存储器540读取到空数据之后，就确定数据已经全部读取，从而停止对N个缓冲存储器540的数据读取。例如，数据读取模块550是根据本地时钟信号来读取N个缓冲存储器540中的数据，由于本地时钟信号一直存在，因此数据读取模块550需要通过空数据来确定数据是否全部读取成功。又如，数据读取模块550是根据第一时钟信号或第二时钟信号读取N个缓冲存储器540中的数据，第一时钟信号和第二时钟信号的有效时钟周期长度有限，从而可以在经历全部有效时钟周期之后，自动停止对N个缓冲存储器540的数据读取。
在一些实施例中，接收端还包括：本地时钟，被配置为生成本地时钟信号。
图6示出了本公开至少一个实施例提供的发送端的示意图。图6中的发送端600可以执行如图4所示的方法，执行方式可参见图4的相关描述。
在图6中，发送端600包括N个数据端口610、时钟端口620和本地时钟630。N个数据端口610对应地发送N个数据信号，N为正整数。时钟端口620发送第一时钟信号。本地时钟630生成第一时钟信号。本地时钟630连接到时钟端口620和N个数据端口610。其中，N个数据信号与第一时钟信号存在对应关系，对应关系为周期数量相差小于或等于预设数量，例如第一时钟信号的周期数量有限，N个数据信号中的每个数据信号的周期数量小于或等于第一时钟信号的周期数量。并且第一时钟信号用于定位N个数据信号中的数据的开始位置并获取N个数据信号中的数据。可选地，本地时钟630可以是锁相环。
在一些实施例中，N个数据信号的周期数量为M，N个第一时钟信号的周期数量为M+X，M为大于或等于2的整数，X为大于或等于0的整数。
在一些实施例中，N个数据端口和时钟端口被配置为同时发送N个数据信号中的一个数据信号和对应的一个第一时钟信号；或者，时钟端口被配置为先发送第一时钟信号，N个数据端口被配置为在第一时钟信号发送后的预设周期之后发送N个数据信号。
可以选择不同的发送方式。例如，在数据信号和第一时钟信号的周期数量相等时，必须要同时发送。第一时钟信号的周期数量大于数据信号的周期数量时，可以同时发送第一时钟信号和数据信号，也可以先发送第一时钟信号再发送数据信号。需要注意的是，由于第一时钟信号会被用于对数据信号中的数据进行定位，从而先发送第一时钟信号的情况下，需要确定发送第一时钟信号和发送数据信号之间的周期差或者相位差，从而保证接收端可以利用第一时钟信号来实现数据的定位。
在一些实施列中，芯粒互联接口还包括：时钟开关，与本地时钟连接以及与时钟端口连接，被配置为在N个数据信号停止发送时或者停止发送的一个周期之后，断开本地时钟与时钟端口的连接。可选地，时钟开关还可以在N个数据信号停止发送后的2个周期或等多个周期之后，断开本地时钟与时钟端口的连接。可选地，时钟开关还可以控制第一时钟信号的发送，例如本地时钟输出的是一直存在的时钟信号，由时钟开关来决定是否发送第一时钟信号、何时发送第一时钟信号以及何时停止发送第一时钟信号。
例如，图6中用虚线框示出的时钟开关640。时钟开关640和本地时钟 630连接，时钟开关640还连接到时钟端口620。时钟开关640可以控制时钟端口620的第一时钟信号的发送或停止发送。
可选地，N个时钟开关640可以用时钟门控电路或开关来实现。
图7a示出了本公开至少一个实施例提供的时钟开关的结构示意图。
图7a中时钟开关700为基于锁存器的时钟门控电路。时钟开关700包括锁存器701和与门702。锁存器701的输入为时钟的使能信号ClkEn和时钟信号Clock，与门702的输入为时钟信号Clock和锁存器701的输出。时钟开关700可以关断时钟的使能信号ClkEn低无效时的时钟信号，即第一时钟信号是时钟的使能信号ClkEn高有效时的几个时钟周期。
图7b示出了本公开至少一个实施例提供的第一时钟信号和数据信号的示意图。
图7b示出的是不使用时钟开关时的数据信号和第一时钟信号的示意图。图7b中的Clock为时钟信号，Data为数据信号。图7b中的数据信号携带4个有效数据，分别是D0、D1、D2和D3，其余斜线部分为无效数据。图7b中的第一时钟信号则是持续存在的。
图7c示出了本公开至少一个实施例提供的第一时钟信号和数据信号的有一种示意图。
图7c示出的是使用时钟开关时的数据信号和第一时钟信号的示意图。图7c中的ClkEn为时钟的使能信号，Clock为时钟信号，Data为数据信号。图7c中的数据信号携带4个有效数据，分别是D0、D1、D2和D3，其余斜线部分为无效数据。图7b中的第一时钟信号与有效数据对应存在。
本公开至少一个实施例还提供一种芯片，包括多个芯粒，其中，多个芯粒中的任意两个芯粒通过如上述第一装置实施例中任一项的芯粒互联接口和如上述第二装置实施例中任一项的芯粒互联接口连接。
本公开至少一个实施例还提供一种芯片，包括多个芯粒，其中，多个芯粒中的任意两个芯粒通过如上述第三装置实施例中任一项的芯粒互联接口和如上述第四装置实施例中任一项的芯粒互联接口连接。
图8示出了本公开至少一个实施例提供的芯片的示意图。
在图8中，芯片800包括芯粒810和芯粒820。芯粒810为发送侧，芯粒820位接收侧。图8中仅示出芯粒810和芯粒820的芯粒互联接口部分。 芯粒810包括串并转换器811、锁相环812、时钟门控813、数据端口814和时钟端口815。芯粒820包括串并转换器821、本地时钟822、数据端口823、时钟端口824和异步FIFO存储器825。
数据端口814和数据端口823通过数据通路连接。时钟端口815和时钟端口824通过时钟通路连接。图8中仅示出一个数据端口作为示意，可以理解地，实际设计包括至少一个数据端口。
串并转换器811接收并行数据并转换为串行数据，串并转换器821则将串行数据转化为并行数据。锁相环812的输入是时钟信号Clock，可以输出时钟信号到时钟门控813和串并转换器811(图中仅示出输出1个时钟信号)。时钟门控813的另一个输入是时钟的使能信号ClkEn。
时钟端口824将接收到的时钟信号发送至串并转换器821，串并转换器821将1个时钟信号输入异步FIFO存储器825，该时钟信号控制异步FIFO存储器825的写指针计数。本地时钟822将另一个时钟信号输入异步FIFO存储器825，该时钟信号控制异步FIFO存储器825的读指针计数。
可选地，芯粒820可以包括多个串并转换器821和多个异步FIFO存储器825。芯粒820还可以包括时钟获取模块，与时钟端口824以及多个串并转换器821连接。时钟获取模块可以将从时钟端口824接收到1个时钟信号扩展为多个时钟信号，多个时钟信号对应输入多个串并转换器821。对应的，多个异步FIFO 825连接到多个串并转换器821，每个串并转换器821将1个时钟信号输入对应的1个异步FIFO存储器825。本地时钟822连接多个异步FIFO存储器825，并向多个异步FIFO存储器825提供本地时钟信号。
图9示出了本公开至少一个实施例提供的芯粒互联后的数据传输方法的时序图。
图9中的芯粒互联可采用如图8所示的互联方式。在图9中，lane表示来自数据通路的控制信号，FIFO表示缓冲存储器的控制信号。laneY_gated_clock表示数据通路Y的第一时钟信号，Y为0-N。laneY_wrpt表示对缓冲存储器的写指针信号。FIFO_read_clock为第二时钟信号，其为持续存在的时钟信号。FIFO_rdpt为缓冲存储器读指针信号。FIFO_read为读使能信号。FIFO_read_sync为缓冲存储器的同步读信号。FIFO_valid为缓冲存储器的有效信号。
每个lane的第一时钟信号和读指针信号是对应的，其表示在有第一时钟信号的上升沿或下降沿时将数据信号中的数据写入缓冲存储器。当所有的缓冲存储器都有数据写入之后，每个缓冲存储器的读指针和写指针的取值不相等，此时读使能信号FIFO_read被拉高变为有效。然后将读使能信号FIFO_read同步到FIFO_read_clock信号，并在下一个周期开始读出数据(下一个周期时FIFO_valid变成高有效)。图中的指针信号的取值0、1、2和3为表示指针的取值，其读取的是对应取值的数据。例如，FIFO_rdpt的取值为0，其读取的是laneY_wrpt取值为0对应的数据。因此，FIFO_rdpt的取值为1至3时，对应读取每个lane中写指针取值1至3位置的数据。
在发送端停止发送数据信号之后，laneY_gated_clock被关闭或断开，由于FIFO_read_clock还有效，会继续读取数据，但读取到的是空数据。只要读取到空数据，读使能信号就会拉低变为无效，等待下一次数据信号的传输。
本公开至少一个实施例提供一种电子设备，包括如上述实施例中的芯片。
图10示出了本公开至少一个实施例提供的电子设备的示意图。
电子设备1000包括芯片1001。芯片1001例如是图8所示的芯片800。电子设备1000可以为任意的具有计算功能的设备，例如为计算机、服务器、智能手机、平板电脑等，本公开的实施例对此不作限制。
以上结合具体实施例描述了本申请的基本原理，但是，需要指出的是，在本申请中提及的优点、优势、效果等仅是示例而非限制，不能认为这些优点、优势、效果等是本申请的各个实施例必须具备的。另外，上述公开的具体细节仅是为了示例的作用和便于理解的作用，而非限制，上述细节并不限制本申请为必须采用上述具体的细节来实现。
值得注意的，本申请中的步骤流程图以及以上方法描述仅作为例示性的例子并且不旨在于要求或暗示必须按照给出的顺序进行各个实施例的步骤，某些步骤可以并行、彼此独立或按照其他适当的顺序执行。另外，诸如“其次”、“然后”、“接下来”等等的词语不旨在于限制步骤的顺序；这些词语仅用于引导读者通读这些方法的描述。
本申请中涉及的器件、装置、设备、系统的方框图仅作为例示性的例子并且不意图要求或暗示必须按照方框图示出的方式进行连接、布置、配置。还需要指出的是，在本申请的装置和方法中，各部件或各步骤是可以分解和 /或重新组合的。这些分解和/或重新组合应视为本申请的等效方案。
有以下几点需要说明：(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (30)

  1. 一种数据传输方法，应用于接收端，包括：
    接收N个数据信号和第一时钟信号，其中，所述第一时钟信号的周期数量有限，所述N个数据信号中的每个数据信号的周期数量小于或等于所述第一时钟信号的周期数量，N为正整数；
    根据所述第一时钟信号，定位所述N个数据信号中的数据的开始位置，并获取所述N个数据信号中的数据。
  2. 根据权利要求1所述的方法，其中，所述根据所述第一时钟信号，定位所述N个数据信号中的数据的开始位置，并获取所述N个数据信号中的数据，包括：
    根据所述第一时钟信号，获取N个第二时钟信号，其中，所述N个第二时钟信号分别对应于所述N个数据信号；
    根据所述N个第二时钟信号，分别定位所述N个数据信号中的每个数据信号的数据的开始位置，并分别将所述N个数据信号中的数据从串行数据转换为并行数据；
    其中，所述N个第二时钟信号中的每一个第二时钟信号具有与所述第一时钟信号相同的周期数量。
  3. 根据权利要求2所述的方法，其中，在获取所述N个数据信号中的数据之后，所述方法还包括：
    根据所述N个第二时钟信号，对应地将所述N个数据信号中的数据保存到缓冲存储器。
  4. 根据权利要求3所述的方法，其中，所述方法还包括：
    根据第三时钟信号，从所述缓冲存储器中读取所述N个数据信号中的数据，
    其中，所述第三时钟信号为所述接收端的本地时钟信号。
  5. 根据权利要求4所述的方法，其中，所述根据第三时钟信号，从所述缓冲存储器中读取所述数据信号中的数据，包括：
    根据所述第三时钟信号，访问所述缓冲存储器的读指针，以读取所述N个数据信号中的数据。
  6. 根据权利要求3所述的方法，其中，根据所述N个第二时钟信号，对应地将所述N个数据信号中的数据保存到缓冲存储器，包括：
    根据所述N个第二时钟信号，分别访问所述缓冲存储器的写指针，以将所述N个数据信号中的数据保存到所述缓冲存储器。
  7. 根据权利要求5所述的方法，其中，所述方法还包括：
    在从所述缓冲存储器中读取到至少一个空数据之后，停止对所述缓冲存储器的读取。
  8. 根据权利要求1-7中任一项所述的方法，其中，所述N个数据信号中的每个数据信号的周期数量为M，所述第一时钟信号的周期数量为M+X，M为大于或等于2的整数，X为大于或等于0的整数。
  9. 一种数据传输方法，应用于发送端，包括：
    发送N个数据信号和第一时钟信号，
    其中，N为正整数，所述第一时钟信号的周期数量有限，所述N个数据信号中的每个数据信号的周期数量小于或等于所述第一时钟信号的周期数量，并且所述第一时钟信号用于定位所述N个数据信号中的数据的开始位置并获取所述N个数据信号中的数据。
  10. 根据权利要求9所述的方法，其中，所述发送所述N个数据信号和所述第一时钟信号，包括：
    同时发送所述N个数据信号和所述第一时钟信号；或者，
    先发送所述第一时钟信号，然后在预设周期之后发送所述N个数据信号。
  11. 根据权利要求9所述的方法，还包括：
    在所述N个数据信号停止发送时或者停止发送之后，停止发送所述第一时钟信号。
  12. 根据权利要求9所述的方法，其中，所述N个数据信号中的每个数据信号的周期数量为M，所述第一时钟信号的周期数量为M+X，M为大于或等于2的整数，X为大于或等于0的整数。
  13. 一种接收端，应用于芯粒互联接口，包括：
    N个数据端口，被配置为接收N个数据信号，其中，N为正整数；
    时钟端口，被配置为接收第一时钟信号，其中，所述第一时钟信号的周期数量有限，所述N个数据信号中的每个数据信号的周期数量小于或等于所述第一时钟信号的周期数量；
    数据处理模块，与所述N个数据端口及所述时钟端口连接，被配置为根据所述第一时钟信号，定位所述N个数据信号中的数据的开始位置，并获取所述N个数据信号中的数据。
  14. 根据权利要求13所述的接收端，还包括：
    时钟获取模块，与所述时钟端口及所述数据处理模块连接，被配置根据将所述第一时钟信号，获取N个第二时钟信号，并将所述N个第二时钟信号发送至所述数据处理模块；
    所述数据处理模块被配置为根据所述N个第二时钟信号，分别将所述N个数据信号中的数据从串行数据转换为并行数据；
    其中，所述N个第二时钟信号中的每一个第二时钟信号具有与所述第一时钟信号相同的周期数量。
  15. 根据权利要求14所述的接收端，还包括：
    缓冲存储器，与所述数据处理模块连接，被配置为保存所述N个数据信号中的数据。
  16. 根据权利要求15所述的接收端，其中，所述数据处理模块还被配置为根据所述N个第二时钟信号，分别访问所述缓冲存储器的写指针，以将所述N个数据信号中的数据保存到所述缓冲存储器。
  17. 根据权利要求15所述的接收端，还包括：
    数据读取模块，与所述缓冲存储器连接，被配置为根据第三时钟信号从所述缓冲存储器中读取出所述N个数据信号中的数据，其中，所述第三时钟信号为所述接收端的本地时钟信号。
  18. 根据权利要求17所述的接收端，其中，所述数据读取模块还被配置为根据所述第三时钟信号，访问所述缓冲存储器的读指针，以读取所述N个数据信号中的数据。
  19. 根据权利要求17所述的接收端，其中，所述数据读取模块还被配置为在从所述缓冲存储器中读取到至少一个空数据之后，停止对所述缓冲存储器的数据读取。
  20. 根据权利要求15所述的接收端，其中，所述缓冲存储器为异步FIFO存储器。
  21. 根据权利要求13所述的接收端，其中，所述接收端还包括：
    本地时钟，被配置为生成本地时钟信号。
  22. 根据权利要求13所述的接收端，其中，所述N个数据信号中的每个数据信号的周期数量为M，所述第一时钟信号的周期数量为M+X，M为大于或等于2的整数，X为大于或等于0的整数。
  23. 一种发送端，应用于芯粒互联接口，包括：
    N个数据端口，被配置为对应地发送N个数据信号，N为正整数；
    时钟端口，被配置为发送第一时钟信号；
    本地时钟，与所述时钟端口及所述N个数据端口连接，被配置为生成所述第一时钟信号；
    其中，所述第一时钟信号的周期数量有限，所述N个数据信号中的每个数据信号的周期数量小于或等于所述第一时钟信号的周期数量，并且所述第一时钟信号用于定位所述N个数据信号中的数据的开始位置并获取所述N个数据信号中的数据。
  24. 根据权利要求23所述的发送端，其中，所述N个数据端口和所述时钟端口被配置为同时发送所述N个数据信号和所述第一时钟信号；或者，所述时钟端口被配置为先发送所述第一时钟信号，所述N个数据端口被配置为在所述第一时钟信号发送后的预设周期之后发送所述N个数据信号。
  25. 根据权利要求23所述的发送端，还包括：
    时钟开关，与所述本地时钟连接以及与所述时钟端口连接，被配置为在所述N个数据信号停止发送时或者停止发送的一个周期之后，断开所述本地时钟与所述时钟端口的连接。
  26. 根据权利要求23所述的发送端，其中，所述N个数据信号的每个数据信号的周期数量为M，所述第一时钟信号的周期数量为M+X，M为大于或等于2的整数，X为大于或等于0的整数。
  27. 一种芯粒互联接口，包括如权利要求13-22中任一项所述的接收端。
  28. 一种芯粒互联接口，包括如权利要求23-26中任一项所述的发送端。
  29. 一种芯片，包括多个芯粒，其中，所述多个芯粒中的任意两个芯粒通过如权利要求27所述的芯粒互联接口和如权利要求28所述的芯粒互联接口连接。
  30. 一种电子设备，包括如权利要求29所述的芯片。
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