WO2025001866A1 - 一种数据处理系统、存储器、数据读写方法及设备 - Google Patents

一种数据处理系统、存储器、数据读写方法及设备 Download PDF

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Publication number
WO2025001866A1
WO2025001866A1 PCT/CN2024/099055 CN2024099055W WO2025001866A1 WO 2025001866 A1 WO2025001866 A1 WO 2025001866A1 CN 2024099055 W CN2024099055 W CN 2024099055W WO 2025001866 A1 WO2025001866 A1 WO 2025001866A1
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WIPO (PCT)
Prior art keywords
address
memory
remapping
bank
module
Prior art date
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Ceased
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PCT/CN2024/099055
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English (en)
French (fr)
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WO2025001866A9 (zh
Inventor
朱晓明
陈一峰
王成旭
崔紫荆
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority claimed from CN202311199956.4A external-priority patent/CN119226187A/zh
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to KR1020267000782A priority Critical patent/KR20260028013A/ko
Priority to EP24830512.0A priority patent/EP4715609A4/en
Publication of WO2025001866A1 publication Critical patent/WO2025001866A1/zh
Publication of WO2025001866A9 publication Critical patent/WO2025001866A9/zh
Priority to US19/431,523 priority patent/US20260119075A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7204—Capacity control, e.g. partitioning, end-of-life degradation

Definitions

  • the present application relates to the field of communication technology, and in particular to a data processing system, a memory, a data reading and writing method and a device.
  • Memory addressing usually refers to locating a certain position of a BANK in a storage particle in the memory according to the logical address sent by the processor.
  • the data at the logical address is usually distributed in various storage particles, and the various storage particles share the logical address. That is, in the process of memory addressing, it is necessary to determine a certain position of a BANK in each storage particle, that is, it is necessary to locate multiple positions.
  • the BANK of the storage particle may include multiple areas with different error rate ranges. If the multiple locations are all located in the area with the highest error rate range in the BANK to which they belong when the memory is addressed, then the probability of error when reading and writing data at the logical address will double. On the contrary, if the multiple locations are all located in the area with the lowest error rate range in the BANK to which they belong when the memory is addressed, then the probability of error when reading and writing data at the logical address will be greatly reduced.
  • the overall error rate of the memory will change with the change of the logical address, and the overall error rate of the memory is not stable, which also increases the difficulty of subsequently designing the memory as a memory with error correction capability.
  • the embodiments of the present application provide a data processing system, a memory, a data reading and writing method and a device for stabilizing the error rate of the memory.
  • an embodiment of the present application provides a data processing system, which includes a processor and a memory.
  • the processor sends a read/write request to the memory, where the read/write request is used to request to read/write data to/from the memory, and the read/write request carries a logical address of the data.
  • the memory After receiving the read/write request, the memory maps the logical address to the target location on the BANK of the N storage particles of the memory, and reads and writes data to the target location on the BANK of the N storage particles; wherein the target locations on the BANK of the N storage particles are distributed in different areas, N is a positive integer, and the areas on the BANK are formed based on the error rate, and the error rates of different areas are different.
  • the memory maps the logical address to the target location on the BANK of N storage particles, and the N target locations are distributed in different areas.
  • the N target locations are no longer located in the same area, so that in the process of a single read and write to the memory, the error rate of the memory will not fluctuate significantly due to different logical addresses, ensuring that the error rate of the memory is stable within a smaller range.
  • the memory has an address remapping function, and the memory provides an option to enable the address remapping function.
  • the processor sends an address remapping instruction to the memory, and the address remapping instruction is used to enable the address remapping function of the memory, so that the processor can enable the address remapping function of the memory according to actual needs.
  • the memory includes N first address remapping modules, each storage particle corresponds to a first address remapping module, and after receiving the address remapping instruction, the control circuit controls the M first address remapping modules to be in a working state according to the address remapping instruction, where M is a positive integer and M is not greater than N.
  • any first address remapping module in working state modifies the physical address converted from the logical address, and the modified physical address points to the target position on the BANK of the storage particle corresponding to the first address remapping module.
  • the first address remapping module in working state can modify the physical address. Since the first address remapping modules corresponding to M storage particles among N storage particles can modify the physical address, the physical addresses obtained by the M storage particles are not exactly the same, further ensuring that the logical address can eventually be mapped to the target position in different areas of the N storage particles.
  • the first address remapping module in operation may modify the field in the physical address pointing to the row and/or column in the BANK.
  • the first address remapping module in working state only needs to change some fields in the physical address to ensure that the logical address can eventually be mapped to the target position in different areas of N storage particles, and the implementation method is relatively simple.
  • the first address remapping module that is not in working state does not modify the physical address, maintains each field in the physical address unchanged, and the physical address points to the target location on the BANK of the storage particle corresponding to the first address remapping module.
  • the first address remapping module in a working state and the first address remapping module not in a working state process the physical address differently, and ultimately it can be ensured that the N physical addresses obtained by the N storage particles are different, and the target addresses of the BANKs of the N storage particles mapped with different N physical addresses will also belong to different areas.
  • any storage particle determines a target location on the BANK of the storage particle according to the physical address obtained from the corresponding first address remapping module, and reads and writes data to the target location.
  • the physical address obtained by the storage particle from the second address remapping module in a working state is a modified physical address
  • the physical address obtained by the storage particle from the second address remapping module that is not in a working state is an original physical address.
  • the physical addresses obtained by the N storage particles from the corresponding first address remapping modules are no longer completely the same, and the target positions on the BANKs of the storage particles finally determined are also different.
  • the address remapping function of the memory is implemented by directly modifying the physical address converted from the logical address.
  • the address remapping function of the memory can also be implemented by modifying the logical address. This implementation is described below.
  • the control circuit includes N second address remapping modules, and each storage particle corresponds to a second address remapping module.
  • the control circuit controls M second address remapping modules to be in a working state according to the address remapping instruction, wherein M is not greater than N.
  • Any second address remapping module in working state modifies the logical address, and the modified logical address is mapped to the target position on the BANK of the storage particle corresponding to the second address remapping module.
  • the second address remapping module in working state can modify the logical address. Since the second address remapping modules corresponding to M storage particles among N storage particles can modify the logical address, the physical addresses converted from the logical address obtained by the M storage particles are not exactly the same, further ensuring that the logical address can eventually be mapped to the target position in different areas of the N storage particles.
  • the second address remapping module in working state modifies the field in the logical address pointing to the row and/or column in the BANK.
  • the second address remapping module in working state only needs to change some fields in the logical address to ensure that the logical address can eventually be mapped to the target position in different areas of N storage particles, and the implementation method is relatively simple.
  • the second address remapping module that is not in a working state maintains each field in the logical address unchanged.
  • the logical address points to a target location on the BANK of the storage particle corresponding to the first address remapping module.
  • the second address remapping module in a working state and the second address remapping module not in a working state process the logical address differently, and ultimately it can be ensured that the N physical addresses obtained by the N storage particles are different, and the target positions of the BANKs of the N storage particles mapped with different N physical addresses will also belong to different areas.
  • control circuit includes an address conversion module; the address conversion module converts the logical address obtained from the second address remapping module into a physical address; and sends the physical address to the storage particle corresponding to the second address remapping module.
  • the logical address obtained by the address conversion module from the second address remapping module in a working state is a modified logical address, and the logical address obtained by the address conversion module from the second address remapping module that is not in a working state is an original logical address.
  • the address conversion module can realize the conversion from logical address to physical address. Different logical addresses will be converted into different physical addresses, ensuring that the logical address received by the memory can be mapped to the BANKs of N storage particles and the target locations distributed in different areas.
  • the present application further provides a memory, which has the functions of implementing the first aspect and any possible implementation method, and some beneficial effects can be found in the description of the first aspect and are not repeated here.
  • the memory includes a control circuit and N storage particles, where N is a positive integer.
  • the control circuit receives a read/write request sent by the processor, the read request is used to request data reading and writing to the memory, and the read/write request carries the logical address of the data.
  • the control circuit converts the logical address into a physical address, and sends the physical address converted from the logical address to the N storage particles of the memory respectively, the physical address points to the target position on the BANK of the N storage particles of the memory, and the target position on the BANK of the N storage particles is distributed in different areas, and N is a positive integer. Different areas are formed based on the error rate division within the BANK, and the error rate range of different areas is different.
  • any storage particle After receiving the physical address, any storage particle reads and writes data to the target location on the BANK of the storage particle;
  • the same logical address can be mapped to the target location on the BANK of N storage particles inside the memory. These N target locations are distributed in different areas, ensuring that the error rate of the memory will not fluctuate significantly with the different logical addresses received by the memory.
  • control circuit receives an address remapping instruction sent by the processor, where the address remapping instruction is used to enable an address remapping function of the memory.
  • the memory includes N first address remapping modules, each storage particle includes a first address remapping module, and the control circuit controls the M first address remapping modules to be in a working state according to the address remapping instruction, where M is a positive integer and M is not greater than N.
  • Any first address remapping module in working state modifies the physical address converted from the logical address, and the modified physical address points to the target position on the BANK of the storage particle corresponding to the first address remapping module.
  • the first address remapping module in working state modifies the field pointing to the row and/or column in the BANK in the physical address.
  • the first address remapping module that is not in a working state maintains each field in the physical address unchanged, and the physical address points to a target location on the BANK of the storage particle corresponding to the first address remapping module.
  • any storage particle determines a target location on the BANK of the storage particle according to the physical address obtained from the corresponding first address remapping module, and reads and writes data to the target location.
  • the physical address obtained by the storage particle from the first address remapping module in a working state is a modified physical address
  • the physical address obtained by the storage particle from the first address remapping module not in a working state is an original physical address.
  • control circuit includes N second address remapping modules, each storage particle corresponds to a second address remapping module, and the control circuit controls the M second address remapping modules to be in a working state according to the address remapping instruction, where M is a positive integer and M is not greater than N.
  • Any second address remapping module in working state modifies the logical address, and the modified logical address points to the target position on the BANK of the storage particle corresponding to the second address remapping module.
  • the second address remapping module in working state modifies the field in the logical address pointing to the row and/or column in the BANK.
  • the second address remapping module that is not in a working state maintains each field in the logical address unchanged.
  • the logical address is mapped to a target location on the BANK of the storage particle corresponding to the second address remapping module.
  • control circuit includes an address conversion module; the address conversion module converts the logical address obtained from the second address remapping module into a physical address; and sends the physical address to the storage particle corresponding to the second address remapping module.
  • the logical address obtained by the address conversion module from the second address remapping module in a working state is a modified logical address, and the logical address obtained by the address conversion module from the second address remapping module that is not in a working state is an original logical address.
  • the present application also provides a data reading and writing method, in which the memory has the function of implementing the above-mentioned first aspect and any possible implementation method.
  • the beneficial effects can be found in the description of the first aspect and will not be repeated here.
  • the control circuit receives a read/write request sent by the processor, wherein the read request is used to request data reading/writing of the memory, and the read/write request carries the logical address of the data; converts the logical address into a physical address, and sends the physical address converted from the logical address to N storage particles respectively, wherein the physical address points to a target position on the BANK of the N storage particles of the memory, wherein the target positions on the BANK of the N storage particles are distributed in different areas;
  • Any storage particle reads and writes data to a target location on the BANK of the storage particle.
  • control circuit may also receive an address remapping instruction sent by the processor, where the address remapping instruction is used to enable the address remapping function of the method.
  • the memory includes N first address remapping modules, each storage particle corresponds to a first address remapping module, and the control circuit controls the M first address remapping modules to be in a working state according to the address remapping instruction, wherein M is not greater than N.
  • Any first address remapping module in working state modifies the physical address converted from the logical address, and the modified physical address points to the target position on the BANK of the storage particle corresponding to the first address remapping module.
  • the working first address remapping module modifies the physical address converted from the logical address
  • the working first address remapping module modifies the field in the physical address pointing to the row and/or column in the BANK.
  • the first address remapping module that is not in a working state maintains each field in the physical address unchanged.
  • the physical address points to a target location on a BANK of a storage particle corresponding to the first address remapping module.
  • any storage particle when any storage particle reads or writes data to a target location on a BANK of the storage particle, any storage particle determines the target location on the BANK of the storage particle according to a physical address obtained from the corresponding first address remapping module, and reads or writes data to the target location.
  • control circuit includes N second address remapping modules, each storage particle corresponds to a second address remapping module, and when the control circuit converts the logical address into a physical address, the control circuit controls the M second address remapping modules to be in a working state according to the address remapping instruction, where M is not greater than N.
  • Any second address remapping module in working state modifies the logical address, and the modified logical address points to the target position on the BANK of the storage particle corresponding to the second address remapping module.
  • the second address remapping module that is not in a working state maintains each field in the logical address unchanged, and the logical address points to a target location on the BANK of the storage particle corresponding to the second address remapping module.
  • control circuit includes an address conversion module; the address conversion module converts the logical address obtained from the second address remapping module into a physical address; and sends the physical address to the storage particle corresponding to the second address remapping module.
  • the logical address obtained by the address conversion module from the second address remapping module in a working state is a modified logical address, and the logical address obtained by the address conversion module from the second address remapping module that is not in a working state is an original logical address.
  • the present application further provides a computing device, which includes the memory mentioned in each possible implementation of the second aspect and the first aspect above, and optionally, may also include a processor.
  • the present application also provides a computer-readable storage medium, in which instructions are stored, and when the computer-readable storage medium is run on a computer, the computer executes the method in the third aspect and various possible implementations of the third aspect.
  • the present application also provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method in the third aspect and various possible implementations of the third aspect.
  • the present application also provides a computer chip, which is connected to a memory, and the chip is used to read and execute a software program stored in the memory, and to execute the methods in the above-mentioned third aspect and various possible implementation methods of the third aspect.
  • FIG1 is a schematic diagram of memory addressing in a memory
  • FIG2 is a schematic diagram of the structure of a data processing system provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of the structure of a memory provided by an embodiment of the present application.
  • FIG4 is a schematic diagram of the structure of a storage particle provided by an embodiment of the present application.
  • FIG5A is a schematic diagram of the distribution of the area within a BANK of a storage particle provided in an embodiment of the present application
  • 5B to 5D are schematic diagrams of mapping physical addresses within a BANK of a storage particle provided in an embodiment of the present application.
  • 6A-6B are schematic diagrams showing the distribution of a BANK of a storage particle provided in an embodiment of the present application.
  • FIG7 is a schematic diagram of a data reading and writing method provided in an embodiment of the present application.
  • FIG8 is a schematic diagram of the structure of a memory provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a data reading and writing method provided in an embodiment of the present application.
  • a memory as a memory may include a plurality of storage chips.
  • the memory may be a phase change memory (PCM), a dynamic random access memory (DRAM), or other types of memory.
  • PCM phase change memory
  • DRAM dynamic random access memory
  • the storage particle is the smallest physical unit for storing data in the memory.
  • the storage space inside any storage particle can be further divided.
  • Each storage particle includes multiple BANKs.
  • Each BANK can be regarded as a storage matrix, which is like a grid array. This "grid array" has many columns and many rows. When you need to get a certain data in the storage space, you only need to specify the BANK, the row in the BANK, and the column.
  • the size, number of rows, and number of columns of each BANK are relatively fixed, that is, the logical address range covered by each BANK is fixed.
  • multiple storage particles included in the memory share the same set of logical addresses. That is, after receiving a read or write request carrying a logical address, the control circuit inside the memory converts the logical address into a physical address and sends the physical address to each storage particle.
  • the address decoding circuit deployed in each storage particle will parse the physical address, parse out the address information pointing to the bank, column, and row, and read and write data to the bank, column, and row pointed to by the address information.
  • FIG1 it is a schematic diagram of memory addressing in a memory.
  • FIG1 exemplarily shows the addressing mode of a storage particle in the memory, and an address register is provided in the storage particle.
  • the address register is used to receive a physical address sent from the control circuit of the memory. After receiving the physical address, the address register sends the received physical address to the address decoding circuit in the storage particle.
  • the address decoding circuit can determine the address information pointing to the BANK, column, and row from the received physical address, and then locate the BANK in the storage particle, and the row or column in the BANK.
  • the address decoding circuit includes a BANK control logic, a column address decoding logic, and a row address decoding logic.
  • the address register can send the portion of the physical address representing the BANK (such as 4 bits) to the BANK control logic, send the portion of the logical address representing the column (such as 15 bits) to the column address decoding logic, and send the portion of the logical address representing the row (such as 11 bits) to the row address decoding logic.
  • the BANK control logic parses the address information pointing to the BANK based on the received portion of the physical address
  • the column address decoding logic parses the address information pointing to the column based on the received portion of the physical address
  • the row address decoding logic parses the address information pointing to the row based on the received portion of the physical address.
  • each storage particle can contribute part of the data, such as each storage particle contributes 8 bytes of data, so that the amount of data read and written in each data read and write operation is the sum of the amount of data contributed by each storage particle, such as the amount of data read and written in a data read and write operation is 64 bytes of data.
  • the data at the logical address is physically distributed in each storage particle of the memory.
  • the final parsed address information pointing to the bank, column, and row is usually the same.
  • the logical address will be mapped to the same position inside each storage particle, or it can be understood that the same physical address will be mapped to the same position inside each storage particle.
  • each BANK of the storage particle Due to the influence of factors such as the routing method of the internal circuit of the memory and the design method of the driving voltage inside the memory, the error rates of different areas in the BANK of each storage particle are different, that is, each BANK can be further divided into multiple areas according to the error rate, and the range of the error rate in each area is the same, while the range of the error rate in different areas is different. That is, each BANK of the storage particle includes an area with a high error rate, an area with a low error rate, and an area with a moderate error rate. If the position in the BANK to which the logical address is mapped transmits an area with a high error rate, then the error probability of data reading and writing at this position is high, that is, the data read or written may have errors.
  • the error probability of data reading and writing at this position is low, that is, the data read or written is not prone to errors.
  • the error rate indicates the probability of erroneous data appearing when reading and writing data at this position or area.
  • the specific method of calculating the error rate is not limited.
  • the error rate of a certain position or a certain area can be equal to the ratio of the number of erroneous bits in data read and write operations performed a set number of times to the total number of bits read and written by the set number of data read and write operations, or it can be equal to the ratio of the number of erroneous bits in multiple data read and write operations performed in a unit time to the total number of bits read and written by the set number of data read and write operations.
  • the same logical address (or the physical address converted from the logical address) will eventually be mapped to the same position of a BANK in each storage particle. Since the positions are the same, the error rate range of the area to which the position belongs will also be the same. If the error rate of the area to which it belongs is high, then the error rate of reading and writing data from the logical address will double.
  • the overall error rate of the memory will change with the area where the data is located, which is relatively unstable.
  • an error correction circuit will be added to the memory, and the unstable error rate will also increase the difficulty of setting the error correction circuit.
  • the memory mentioned in the present application has an address remapping function.
  • the position of the BANK of each storage particle to which the logical address is mapped may be different, that is, the position in each BANK to which the logical address is mapped no longer belongs to the same area with the same error rate range, and the position in each BANK to which the logical address is mapped may be distributed in multiple areas. In this way, the error rates of the positions in each BANK to which the logical address is mapped are no longer exactly the same.
  • the address remapping function of the memory has two implementation methods. One implementation method is to process the physical address after the received logical address is converted to each storage particle in the memory.
  • the address remapping function of the memory is implemented with the help of a first address remapping module inside the storage particle (the first address remapping module is used to modify the physical address).
  • the control circuit in the memory converts the logical address into a non-completely identical physical address, and sends the non-completely identical physical address to each storage particle respectively.
  • the memory The address remapping function is implemented with the help of the second address remapping module inside the control circuit (the second address remapping module is used to modify the logical address).
  • the final effect is that the same logical address is finally mapped to different positions in the BANK of each storage particle. In this way, when reading and writing data to the memory, the overall error rate of the memory will not fluctuate greatly with the area where the data is located, and the overall error rate of the memory is relatively stable.
  • the first implementation method the address remapping function of the memory is implemented by means of a first address remapping module inside the storage particle.
  • the data processing system provided by the embodiment of the present application is described below in conjunction with the accompanying drawings. As shown in Figure 2, it is a structural diagram of a data processing system provided by the embodiment of the present application.
  • the data processing system 10 includes a processor 100 and a memory 200.
  • the processor 100 is the computing core of the system.
  • the processor 100 can perform major data computing operations.
  • the processor 100 can access the memory 200 to read data or write data in the memory 200.
  • the processor 100 can read data from the memory 200 and perform data computing on the read data; the processor 100 can also store data generated after data computing in the memory 200.
  • the processor 100 When accessing the memory 200 , the processor 100 sends a read/write request to the memory 200 .
  • the read/write request carries a logical address of the data to instruct the memory 200 to read/write the data at the logical address.
  • the processor 100 in addition to being able to access the memory 200, can also enable an address remapping function of the memory 200.
  • the processor 100 can send an address remapping instruction to the memory 200, and the address remapping instruction is used to enable the address remapping function of the memory 200.
  • the processor 100 may be a central processing unit (CPU) or other specific integrated circuits.
  • the processor 100 may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • DSP digital signal processors
  • ASIC application specific integrated circuits
  • FPGA field programmable gate arrays
  • the memory 200 has a data storage function.
  • the memory 200 can store data required by the processor 100 for data calculation, and can also store data generated after the processor 100 performs data calculation.
  • the memory 200 receives and processes read and write requests from the processor 100, reads and writes data to the logical address, writes the data calculated by the processor 100 to the logical address, or reads the data required by the processor 100 for data calculation from the logical address, and feeds the read data back to the processor 100.
  • the memory 200 also has an address remapping function.
  • the memory 200 can map the logical address to the target locations of multiple BANKs.
  • the target locations of the multiple BANKs are distributed in multiple areas, where different areas correspond to different error rate ranges.
  • the memory 200 may provide an option to enable the address remapping function, that is, the memory 200 allows a device outside the memory 200 to enable the address remapping function.
  • the memory 200 may map the received logical address to the target locations of multiple BANKs, and the target locations of the multiple BANKs are distributed in multiple areas.
  • the memory 200 may map the received logical address to the same location of multiple BANKs.
  • the embodiment of the present application does not limit the manner in which the memory 200 provides the enabling option of the address remapping function.
  • the device of the memory 200 is configured with an enabling switch of the address remapping function, and the user can turn on or off the enabling switch of the address remapping function according to actual needs.
  • the memory 200 is configured with a parsing function of the address remapping instruction, and a device outside the memory 200 can send an address remapping instruction to the memory 200, and the memory 200 enables the address remapping function by parsing the received address remapping instruction.
  • the memory 200 can also provide a variety of different address remapping strategies. Any address remapping strategy describes part or all of the following information:
  • Different address remapping strategies may describe different numbers of first address remapping modules 222 in operation and/or different ways of modifying the physical address after logical address conversion by any first address remapping module 222 in operation.
  • the embodiments of the present application do not limit the manner in which the memory 200 provides a plurality of different address remapping strategies.
  • a plurality of selection buttons for different address remapping strategies are configured on the memory 200, and the user can select an address remapping strategy through the selection button according to actual needs.
  • the memory 200 is configured with a parsing function for address remapping instructions.
  • the address remapping instructions sent to the memory 200 by a device outside the memory 200 can also indicate a certain address remapping strategy.
  • the memory 200 enables the address remapping function by parsing the received address remapping instructions, and performs address remapping using the address remapping strategy indicated in the address remapping instructions.
  • the address remapping function can also be enabled before the memory 200 leaves the factory, that is, the memory 200 leaves the factory. After that, the address remapping function is enabled and no additional operation is required.
  • a memory 200 provided in an embodiment of the present application includes a control circuit 210 and a plurality of storage particles 220 .
  • the description of the storage particles 220 can be found in the above description and will not be repeated here.
  • the storage particles 220 are mainly used to store data
  • the control circuit 210 is the control center of the memory 200.
  • the control circuit 210 can process the read and write requests received by the memory 200. That is, the control circuit 210 can parse the logical address carried in the read and write request, and read and write data to each storage particle 220 according to the logical address.
  • control circuit 210 can convert the logical address into a physical address, and send the physical address to each storage particle 220.
  • the physical address points to a target location of a BANK of the storage particle 220.
  • the target locations of the multiple BANKs are distributed in different areas, and different areas correspond to different error rate ranges.
  • the target locations of the multiple BANKs are distributed in the same area.
  • the control circuit 210 can detect the enable state of the address remapping function, that is, determine whether the address remapping function is enabled. For example, when the device of the memory 200 is configured with an enable switch for the address remapping function, the control circuit 210 can detect the enable switch for the address remapping function to determine whether the address remapping function is enabled. For another example, when the memory 200 is configured with a parsing function for an address remapping instruction, the parsing function can be implemented by the control circuit 210, and the control circuit 210 can parse the received address remapping instruction to enable the address remapping function.
  • each storage particle 220 parses the physical address to determine the address information pointing to the BANK, row, and column, and then locates the position in the BANK according to the address information pointing to the BANK, row, and column.
  • different storage particles 220 may adopt different parsing methods when parsing the physical address, and the address information pointing to the bank, row, and column obtained by adopting different parsing methods is not completely the same.
  • not completely the same means that the address information of the bank, row, and column obtained by adopting different parsing methods is completely different or partially different.
  • each set of address information includes address information pointing to a bank, a row, and a column. If the address information pointing to the bank in the two sets of address information is the same, and the address information pointing to the row and column is completely different, then the two sets of address information will correspond to two different positions on the bank, and the areas where the two positions are located may also be different. If the address information pointing to the bank and the row in the two sets of address information is the same, and the address information pointing to the column is different, then the two sets of address information will correspond to different positions on a bank, and the areas where the two positions are located may also be different.
  • the storage particles 220 may use completely different parsing methods for the physical address to obtain multiple sets of non-completely identical address information. That is, in multiple storage particles 220, the storage particles 220 may convert the physical address into multiple sets of non-completely identical address information, and the multiple sets of non-completely identical address information correspond to different target locations in multiple BANKs. In this way, the target locations of the multiple BANKs will no longer belong to the same area.
  • not completely the same means two situations, one is partially the same and partially different, and the other is completely different.
  • each storage particle 220 for the physical address may be partially different, so as to obtain multiple sets of address information that are not completely the same, that is, for some storage particles 220 in the multiple storage particles 220, one parsing method is used to parse the logical address for the physical address, and finally multiple sets of identical address information are obtained, and for another part of the storage particles 220 in the multiple storage particles 220, another parsing method is used to parse the logical address for the physical address, and finally multiple sets of identical address information are obtained.
  • a part of the multiple sets of address information corresponds to the same target location in multiple BANKs, and another part of the multiple sets of address information corresponds to the same another target location in multiple BANKs.
  • each storage particle 220 adopts two different parsing methods for the physical address, wherein the storage particles 220-1, 220-2, 220-3, and 220-4 adopt one parsing method, and the storage particles 220-5, 220-6, Storage particles 220-7 and 220-8 adopt another parsing method, then the four sets of address information obtained by parsing in storage particles 220-1, 220-2, 220-3, and 220-4 are the same, and point to target positions A on a certain BANK in storage particles 220-1, 220-2, 220-3, and 220-4 respectively.
  • the positions of each target position A in the BANK to which it belongs are the same, that is, the same target position in multiple BANKs.
  • the four sets of address information obtained by parsing in storage particles 220-5, 220-6, 220-7, and 220-8 are the same, and point to target positions B on a certain BANK in storage particles 220-5, 220-6, 220-7, and 220-8 respectively.
  • the positions of each target position B in the BANK to which it belongs are the same, that is, the same target position in multiple BANKs.
  • the embodiment of the present application does not limit the specific parsing method adopted by the storage particle 220 for the physical address. Any method that can parse the physical address into address information pointing to BANK, row, and column is applicable to the embodiment of the present application.
  • the storage particle 220 can modify some fields of the physical address, and then analyze the modified physical address based on the first mapping relationship to generate address information pointing to BANK, row, and column.
  • the first mapping relationship records the correspondence between each field in the physical address and BANK, row, and column.
  • the memory 200 includes a control circuit 210 and a plurality of storage particles 220.
  • Each storage particle 220 includes an address register 221, a first address remapping module 222, and an address decoding circuit 223.
  • the address register 221 is a register with a storage function
  • the first address remapping module 222 and the address decoding circuit 223 can be logic circuits.
  • the embodiment of the present application does not limit the specific internal structure of the first address remapping module 222 and the address decoding circuit 223. Any logic circuit that can implement the corresponding function can be used as the first address remapping module 222 and the address decoding circuit 223.
  • the first address remapping module 222 is set between the address register 221 and the address decoding circuit 223, that is, the physical address sent by the address register 221 to the address decoding circuit 223 will first pass through the first address remapping module 222. After the first address remapping module 222 processes the physical address, it can send the physical address after the processing operation to the address decoding circuit 223.
  • the first address remapping module 222 can perform one of two processing operations on the physical address, one is to modify the physical address, and the other is to maintain the various fields in the physical address unchanged. In particular, the first address remapping module 222 in the working state can modify the physical address, and the first address remapping module 222 in the non-working state maintains the various fields of the physical address unchanged.
  • the address register 221 is used to store the physical address sent by the control circuit 210.
  • the control circuit 210 sends the physical address, it needs to go through multiple clock cycles to send the complete physical address to the storage particle 220. That is, the amount of data transmitted by the control circuit 210 in one clock cycle is limited.
  • the control circuit 210 can send the fields included in the physical address to the storage particle 220 in multiple times, and the address register 221 can receive and cache the fields included in the physical address sent by the control circuit 210.
  • the control circuit 210 can send a 6-bit address in each clock cycle, and the total length of the physical address is 48 bits.
  • the control circuit 210 can send the 48-bit physical address to the storage particle 220 through 8 clock cycles.
  • the address register 221 caches the 6 bits every time it receives 6 bits until the cached data amount reaches 48 bits.
  • the address register 221 may send the physical address to the first address remapping module 222 .
  • the first address remapping module 222 may perform a processing operation on the physical address, and send the physical address after the processing operation to the address decoding circuit 223.
  • the embodiment of the present application does not limit the way in which the first address remapping module 222 modifies the physical address.
  • the first address remapping module 222 may invert some fields in the physical address, or for another example, the first address remapping module 222 may subtract some fields in the physical address from a preset value to obtain a difference, and use the difference to replace the part of the fields in the physical address.
  • the address decoding circuit 223 can analyze the physical address based on the first mapping relationship to obtain address information pointing to the BANK, row, and column, and then determine the target location on the BANK in the storage particle 220, and read and write data to the target address.
  • the embodiment of the present application does not limit the specific implementation method of the address decoding circuit 223 obtaining the address information pointing to the BANK, row, and column from the physical address, and any method of analyzing the physical address to obtain the address information pointing to the BANK, row, and column is applicable to the embodiment of the present application.
  • the address decoding circuit 223 includes a BANK control logic, a column address decoding logic, and a row address decoding logic.
  • the first address remapping module 222 can send the part of the modified physical address that represents the BANK (such as 4 bits) to the BANK control logic, send the part of the physical address that represents the column (such as 15 bits) to the column address decoding logic, and send the part of the physical address that represents the row (such as 11 bits) to the row address decoding logic.
  • the BANK control logic receives the received The address information pointing to the BANK is obtained according to the partial physical address received, the column address decoding logic obtains the address information pointing to the column according to the partial physical address received, and the row address decoding logic obtains the address information pointing to the column according to the partial physical address received.
  • the address decoding circuit 223 After obtaining the address information pointing to the bank, row and column, the address decoding circuit 223 can locate the target position of the bank and realize data reading and writing by changing the working voltage of the device in the target position.
  • the address register 221 will send the physical address to the address decoding circuit 223, and the address decoding circuit 223 can parse the received physical address to obtain the address information pointing to the bank, row, and column.
  • a first address remapping module 222 is added before the address decoding circuit 223, and the first address remapping module 222 added before the address decoding circuit 223 can modify the physical address received by the address decoding circuit 223, so that the address decoding circuit 223 can parse the modified physical address.
  • the modification method only needs to add part of the circuit logic to the original design of the memory 200, and the modification method is simple and low in cost.
  • the BANK of the memory 200 includes three areas, and the error rate range corresponding to each area is different.
  • these three areas are respectively called AREA1, AREA2, and AREA3.
  • the physical address distribution within these three areas can be shown in Table 1.
  • ADDR[M] represents the Mth bit of the physical address
  • ADDR[M:N] represents the Nth to Mth bits of the physical address.
  • FIG. 5A it is a schematic diagram of the distribution of AREA1, AREA2, and AREA3 in a BANK, where AREA1 is located below the BANK, AREA3 is located above the BANK, and AREA2 is located in the middle of the BANK. After testing, among the three areas, the error rate of AREA1 is the highest, the error rate of AREA2 is in the middle, and the error rate of AREA3 is the lowest.
  • the division of regions with different error rate ranges in the BANK is related to multiple factors such as the routing of the control circuit 210 inside the memory 200 and the design of the driving voltage in the memory 200.
  • the number of regions included in the BANK and the error rate range of each region will be related to the specific design of the memory 200.
  • the number of regions with different error rate ranges in the BANK and the error rate range of each region will also change due to the setting of test parameters. For example, during specific tests, when a higher accuracy or more error rate gears can be selected, the number of regions included in the BANK may also increase. Table 1 only lists one possible distribution.
  • the memory 200 can implement address remapping in the following two ways.
  • Method 1 Map the physical address pointing to a location in the AREA1 area in the BANK of the storage particle 220 to the target location in the AREA3 area.
  • the first address remapping module 222 modifies the fields representing rows and columns in the physical address, so that the address information pointing to BANK, row, and column obtained according to the modified physical address will change from the address information pointing to BANK, row, and column obtained according to the physical address before modification.
  • ADDR'[15:12] 40-ADDR[15:12]
  • the address register 221 sends the physical address to the first address remapping module 222.
  • the first address remapping module 222 modifies the field representing the row of the physical address, the physical address pointing to a location in the AREA1 area of the BANK of the storage particle 220 will be mapped to the target location in the AREA3 area.
  • Method 2 Map the physical address pointing to a certain location in the AREA1 area in the BANK of the storage particle 220 to the target location in the AREA2 area.
  • AREA1 The simplest way to map from AREA1 to AREA2 is to change the field representing the row, or the field representing the row and column in the physical address.
  • the first address remapping module 222 can modify the field representing the row in the physical address, so that the address information pointing to the bank, row, and column obtained according to the modified physical address will change from the address information pointing to the bank, row, and column obtained according to the physical address before modification.
  • the first address remapping module 222 only needs to modify the field representing the row in the physical address.
  • the address register 221 sends the row field in the physical address to the first address remapping module 222.
  • the first address remapping module 222 modifies the row field in the physical address, the physical address pointing to a location in the AREA1 area in the BANK of the storage particle 220 will be mapped to the target location in the AREA2 area.
  • the first address remapping module 222 can modify the fields representing rows and columns in the physical address, so that the address information pointing to the bank, row, and column obtained according to the modified physical address will change from the address information pointing to the bank, row, and column obtained according to the physical address before the modification.
  • the first address remapping module 222 only needs to modify the fields representing rows and columns in the physical address.
  • the address register 221 sends the column field in the physical address to the first address remapping module 222.
  • the first address remapping module 222 modifies the column field in the physical address, the physical address pointing to a location in the AREA1 area in the BANK of the storage particle 220 will be mapped to the target location in the AREA2 area.
  • the specific way in which the first address remapping module 222 modifies the physical address is only an example. In practical applications, the way in which the first address remapping module 222 modifies the physical address can be designed according to the location of the fields representing rows and columns in the physical address and the distribution of areas with different error rate ranges.
  • the BANKs inside the storage particles 220 may be arranged in a planar manner, that is, the BANKs included in the storage particles 220 are located in the same plane.
  • the BANKs inside the storage particles 220 may also be arranged in a three-dimensional manner, that is, a certain BANK in the storage particles 220 may include multiple stacked layers.
  • FIG6A is a schematic diagram showing that the BANKs inside the storage particle 220 are arranged in a planar manner, and the BANKs inside the storage particle 220 are in the same plane.
  • the areas in the BANKs inside the storage particle 220 are all located in the same plane, that is, when performing address remapping, the field representing the row/or column in the physical address can be changed.
  • FIG. 6B is a schematic diagram showing that the BANKs in the storage particle 220 are arranged in a three-dimensional manner, and each BANK in the storage particle 220 includes two layers, an upper layer and a lower layer.
  • the BANK includes two layers as an example, but in fact, the BANK may also include three layers or even more layers.
  • Each layer of the BANK may include multiple different areas, and the error rate range corresponding to each area is also different.
  • the error rate ranges of the relative areas in the upper and lower layers of the BANK may also be different.
  • the relative areas refer to two areas with relative positions in the same BANK.
  • the physical address usually includes a field representing the middle layer of the bank, in addition to changing the physical address table
  • address remapping can also be implemented by changing the field representing the BANK layer in the physical address.
  • the error rates at the same row and column positions in different BANKs are also different, that is, the error rates at the same position in different BANKs may also be different.
  • the first address remapping module 222 modifies the physical address, it can also modify the bit representing the BANK in the physical address, and the modification method is similar to the method in which the first address remapping module 222 modifies the bit representing the row or column in the physical address, which will not be repeated here.
  • the memory 200 when the memory 200 enables the address remapping function, it is not necessary for all first address remapping modules 222 in the memory 200 to be in a working state. That is, when the memory 200 enables the address remapping function, it is only necessary to ensure that some of the first address remapping modules 222 among the multiple first address remapping modules 222 can modify the received physical address. The other first address remapping modules 222 do not need to modify the received physical address, and after receiving the physical address, the physical address can be directly sent to the address decoding circuit 223.
  • the memory 200 will also include N first address remapping modules 222.
  • M first address remapping modules 222 can be enabled in the memory 200 and are in working state, where M is a positive integer less than N.
  • Whether the first address remapping module 222 in the memory 200 is in a working state can be set by the control circuit 210 itself. For example, after receiving an address remapping instruction, the control circuit 210 can control the first address remapping modules 222 among the multiple first address remapping modules 222, whose number is equal to the set value, to be in a working state.
  • first address remapping modules 222 in the memory 200 are in a working state and which first address remapping modules 222 are in a working state can also be set before the memory 200 leaves the factory, that is, some of the multiple first address remapping modules 222 are set to a working state before leaving the factory.
  • the address remapping instruction sent by the processor 100 also carries an address remapping strategy, which indicates the number of the first address remapping modules 222 in a working state (such as M).
  • the control circuit 210 can control some of the first address remapping modules 222 in the multiple first address remapping modules 222 to be in a working state, and the number of the first address remapping modules 222 meets the instruction of the address remapping instruction.
  • the address remapping instruction sent by the processor 100 in addition to indicating enabling the address remapping function, also indicates the working status of the first address remapping module 222, that is, it informs which first address remapping modules 222 need to be in a working state.
  • the control circuit 210 can control some of the multiple first address remapping modules 222 to be in a working state, and these some first address remapping modules 222 are the first address remapping modules 222 indicated by the address remapping instruction.
  • control circuit 210 can also control the first address remapping module 222 in working state to modify the received physical address using the modification method indicated by the address remapping strategy.
  • each first address remapping module 222 in a working state modifies the physical address in a different way
  • the memory 200 can also control all the first address remapping modules 222 to be in a working state. Since each first address remapping module 222 in a working state modifies the physical address in a different way, the physical address processed by the first address remapping module 222 in each storage particle 220 (that is, the modified physical address) will not be exactly the same. The multiple not exactly the same physical addresses will point to the target position in the BANK of each storage particle 220.
  • a corresponding first address remapping module 222 is provided for each storage particle 220.
  • the memory 200 may also only provide the first address remapping module 222 for some storage particles 220.
  • the first address remapping module 222 may be set to a working state before leaving the factory, or when the processor 100 sends an address remapping instruction indicating enabling the address remapping function, the control circuit 210 controls the included first address remapping module 222 to be in a working state.
  • the memory 200 provides an enable option for the address remapping function as an example for description. If the memory 200 does not provide an enable option for the address remapping function, steps 700 to 701 can be omitted.
  • Step 700 The processor 100 sends an address remapping instruction to the memory 200.
  • the address remapping instruction is used to indicate enabling of the address remapping function.
  • the address remapping instruction also indicates the first address remapping module 222 that needs to be in working state.
  • Step 701 The memory 200 receives the address remapping instruction, and controls the first address remapping module 222 indicated by the address remapping instruction to be in a working state according to the address remapping instruction.
  • Step 702 The processor 100 sends a read/write request to the memory 200, where the read/write request carries the logical address of the data.
  • Step 703 the memory 200 receives the read/write request, and maps the logical address to a target location on the BANK of the storage particle 220 in each storage particle 220 of the memory 200 .
  • the control circuit 210 sends the physical address to each storage particle 220.
  • the internal address register 221 of each storage particle 220 receives the physical address sent by the control circuit 210, and sends the physical address to the first address remapping module 222 of each storage particle 220.
  • the first address remapping module 222 modifies the physical address and sends the modified physical address to the address decoding circuit 223 of the storage particle 220.
  • the address decoding circuit 223 analyzes the modified physical address to obtain the address information of the execution bank, row, and column, and then locates the target position on the bank according to the address information.
  • the first address remapping module 222 For the first address remapping module 222 that is not in working state, the first address remapping module 222 sends the received physical address to the address decoding circuit 223 of the storage particle 220.
  • the address decoding circuit 223 analyzes the obtained physical address to obtain the address information of the execution bank, row, and column, and then locates the target position on the bank according to the address information.
  • Step 704 the memory 200 reads and writes data to the target location on the BANK of each storage particle 220 .
  • the memory 200 reads data from the target location on the BANK of each storage particle 220 , aggregates the data read from each storage particle 220 , and feeds it back to the processor 100 .
  • the memory 200 When the read-write request is a write request requesting to write data, the memory 200 writes the data carried by the write request at the target location on the BANK of each storage particle 220, wherein the data written at each target location is part of the data carried by the write request, and the data written at all target locations is the data carried by the write request.
  • the address remapping function of the memory 200 is implemented by means of the second address remapping module 211 inside the control circuit 210 .
  • the memory 200 can also provide a variety of different address remapping strategies to the outside. Any address remapping strategy describes part or all of the following information:
  • a method of modifying a logical address by any second address remapping module 211 in working state is a method of modifying a logical address by any second address remapping module 211 in working state.
  • Different address remapping strategies may describe different numbers of the second address remapping modules 211 in operation and/or different ways of modifying the physical address after the logical address is converted by any second address remapping module 211 in operation.
  • the embodiments of the present application do not limit the manner in which the memory 200 provides a plurality of different address remapping strategies.
  • a plurality of selection buttons for different address remapping strategies are configured on the memory 200, and the user can select an address remapping strategy through the selection button according to actual needs.
  • the memory 200 is configured with a parsing function for address remapping instructions.
  • the address remapping instructions sent to the memory 200 by a device outside the memory 200 can also indicate a certain address remapping strategy.
  • the memory 200 enables the address remapping function by parsing the received address remapping instructions, and performs address remapping using the address remapping strategy indicated in the address remapping instructions.
  • the structure of the memory 200 is described below. Similar to the structure of the memory 200 shown in FIG3 , in this implementation, the memory 200 includes a control circuit 210 and a plurality of storage particles 220. However, in this implementation, the structure of the control circuit 210 and the storage particles 220 are different from the structure of the memory 200 shown in FIG3 .
  • the structure of the storage particles 220 is similar to the structure of the storage particles 220 in the embodiment shown in FIG1 , and the details can be referred to the above description, which will not be repeated here.
  • the storage particles 220 are mainly used to store data
  • the control circuit 210 is the control center of the memory 200.
  • the control circuit 210 can process the read and write requests received by the memory 200. That is, the control circuit 210 can parse the logical address carried in the read and write request, and read and write data to each storage particle 220 according to the logical address.
  • control circuit 210 can map the logical address to each storage particle 220.
  • the logical address can be mapped to a target location of a BANK of the storage particle 220. That is, the control circuit 210, The logical address may be mapped to target locations of multiple BANKs respectively.
  • the target locations of the multiple BANKs are distributed in different areas, and different areas correspond to different error rate ranges.
  • the target locations of the multiple BANKs are distributed in the same area.
  • the control circuit 210 can detect the enable state of the address remapping function, that is, determine whether the address remapping function is enabled. For example, when the device of the memory 200 is configured with an enable switch for the address remapping function, the control circuit 210 can detect the enable switch for the address remapping function to determine whether the address remapping function is enabled. For another example, when the memory 200 is configured with a parsing function for an address remapping instruction, the parsing function can be implemented by the control circuit 210, and the control circuit 210 can parse the received address remapping instruction to enable the address remapping function.
  • control circuit 210 needs to convert the logical address to obtain a corresponding physical address, and then send the physical address to each storage particle 220 .
  • control circuit 210 when converting the logical address, may adopt different conversion methods for different storage particles 220, and adopt different conversion methods to ultimately obtain different physical addresses.
  • the control circuit 210 may use different conversion methods for the logical address for each storage particle 220 to obtain multiple physical addresses that are not completely the same. For example, for some storage particles 220 in the multiple storage particles 220, the control circuit 210 uses one conversion method to convert the logical address, and finally obtains multiple identical physical addresses. For another part of the storage particles 220 in the multiple storage particles 220, the control circuit 210 uses another conversion method to convert the logical address, and finally obtains multiple identical physical addresses. In this way, the multiple physical addresses that are not completely the same are finally obtained, a part of the multiple physical addresses corresponds to the same target location in multiple BANKs, and another part of the multiple physical addresses corresponds to another identical target location in multiple BANKs.
  • control circuit 210 uses completely different conversion methods for the logical address for each storage particle 220 to obtain multiple sets of completely different address information. That is, in different storage particles 220, the control circuit 210 uses different conversion methods to convert the logical address, and finally obtains completely different physical addresses. In this way, the multiple physical addresses correspond to different target locations in multiple BANKs. In this way, the target locations of the multiple BANKs will no longer belong to the same area.
  • the control circuit 210 uses two different conversion methods for the logical address for each storage particle 220, wherein one conversion method is used for the storage particles 220-1, 220-2, 220-3, and 220-4, and another conversion method is used for the storage particles 220-5, 220-6, 220-7, and 220-8. Then, the physical addresses obtained by the storage particles 220-1, 220-2, 220-3, and 220-4 are the same, and point to the target position A on a certain BANK in the storage particles 220-1, 220-2, 220-3, and 220-4 respectively. The positions of the target positions A in the BANKs to which they belong are the same, that is, they are the same target positions in multiple BANKs.
  • the physical addresses obtained in the storage particles 220-5, 220-6, 220-7, and 220-8 are the same, and point to the target position B on a certain BANK in the storage particles 220-5, 220-6, 220-7, and 220-8 respectively.
  • the positions of the target positions B in the BANKs to which they belong are the same, that is, the target positions are the same in multiple BANKs.
  • the embodiment of the present application does not limit the specific conversion method adopted by the control circuit 210 for the logical address, and any method that can convert the logical address into a physical address is applicable to the embodiment of the present application.
  • the control circuit 210 can modify some or all fields in the logical address, and then analyze the modified logical address based on the preset mapping relationship to generate a physical address.
  • the control circuit 210 includes a plurality of second address remapping modules 211 and a plurality of address conversion modules 212.
  • the second address remapping module 211 and the plurality of address conversion modules 212 may be logic circuits.
  • the embodiment of the present application does not limit the specific internal structures of the second address remapping module 211 and the plurality of address conversion modules 212. Any logic circuit that can realize the corresponding functions is applicable to the embodiment of the present application.
  • Each storage particle 220 corresponds to a second address remapping module 211 and an address conversion module 212.
  • the second address remapping module 211 is arranged between the storage particle 220 and the address conversion module 212. That is, the logical address will first pass through the second address remapping module 211. After the second address remapping module 211 processes the logical address, it can convert the logical address after the processing operation into the second address remapping module 211. The address is sent to the address conversion module 212.
  • the address conversion module 212 is used to convert the logical address after the processing operation is performed into a physical address based on the second mapping relationship.
  • the second mapping relationship is a mapping relationship between a physical address and a logical address.
  • the second address remapping module 211 can perform one of two processing operations on the logical address. One is to modify the logical address.
  • the embodiment of the present application does not limit the modification method of the logical address by the second address remapping module 211.
  • the second address remapping module 211 can invert some fields in the logical address.
  • the second address remapping module 211 can subtract some fields in the logical address from the preset value to obtain the difference, and use the difference to replace the part of the fields in the logical address.
  • the other is to maintain the various fields in the logical address unchanged.
  • the second address remapping module 211 in the working state can modify the logical address
  • the second address remapping module 211 in the non-working state maintains the various fields of the logical address unchanged.
  • the address conversion module 212 can convert the obtained logical address into a corresponding physical address according to the second mapping relationship, and convert the physical address to the storage particle 220.
  • the physical address parsing process inside the storage particle 220 can refer to the relevant description in the embodiment shown in Figure 1 and will not be repeated here.
  • Fig. 8 is only a schematic diagram of a possible structure of the control circuit 210.
  • the embodiment of the present application does not limit the division method of each module in the control circuit 210.
  • the way in which the second address remapping module 211 modifies the logical address is similar to the way in which the first address remapping module 222 modifies the physical address.
  • the second address remapping module 211 may have different specific values of the fields representing BANK, row, and column in the logical address and the specific operations adopted for each field.
  • the configuration method of the second address remapping module 211 in the working state is similar to the configuration method of the first address remapping module 222 in the working state. For details, please refer to the above description and will not be repeated here.
  • the memory 200 provides an enable option for the address remapping function as an example for description. If the memory 200 does not provide an enable option for the address remapping function, steps 900 to 901 can be omitted.
  • Step 900 The processor 100 sends an address remapping instruction to the memory 200.
  • the address remapping instruction is used to indicate enabling of the address remapping function.
  • the address remapping instruction also indicates a second address remapping module 211 that needs to be in working state.
  • Step 901 the memory 200 receives the address remapping instruction, and controls the second address remapping module 211 indicated by the address remapping instruction to be in a working state according to the address remapping instruction.
  • Step 902 The processor 100 sends a read/write request to the memory 200, where the read/write request carries a logical address.
  • Step 903 the memory 200 receives the read/write request, and maps the logical address to a target location on the BANK of the storage particle 220 in each storage particle 220 of the memory 200 .
  • the second address remapping module 211 of each storage particle 220 obtains the logical address and sends it.
  • the second address remapping module 211 modifies the field in the logical address and sends the modified logical address to the address conversion module 212 corresponding to the storage particle 220.
  • the address conversion module 212 converts the modified logical address to obtain a physical address and sends the physical address to the corresponding storage particle 220.
  • the second address remapping module 211 For the second address remapping module 211 that is not in working state, the second address remapping module 211 sends the received logical address to the address conversion module 212 of the storage particle 220 , and the address conversion module 212 converts the logical address to obtain a physical address and sends the physical address to the corresponding storage particle 220 .
  • Step 904 the memory 200 reads and writes data to the target location on the BANK of each storage particle 220 .
  • the memory 200 reads data from the target location on the BANK of each storage particle 220 , aggregates the data read from each storage particle 220 , and feeds it back to the processor 100 .
  • the memory 200 When the read-write request is a write request requesting to write data, the memory 200 writes the data carried by the write request at the target location on the BANK of each storage particle 220, wherein the data written at each target location is part of the data carried by the write request, and the data written at all target locations is the data carried by the write request.
  • the second address remapping module 211 directly modifies the logical address as an example.
  • the second address remapping module 211 may not directly modify the logical address, but may modify the address conversion module 211 directly modify the logical address.
  • the physical address obtained after the conversion is modified 212, and the modified physical address is sent to the corresponding storage particle 220.
  • the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.
  • the functional modules in the embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.
  • the above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.
  • the above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination.
  • the above embodiments can be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part.
  • the computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium.
  • the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.
  • the computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets.
  • the available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium.
  • the semiconductor medium can be a solid state drive (SSD).
  • the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.
  • a computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.
  • These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

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Abstract

一种数据处理系统、存储器、数据读写方法及设备，本申请中，处理器向存储器发送读写请求，读写请求用于请求对存储器进行数据读写，读写请求中携带有数据的逻辑地址。存储器接收该读写请求后，将逻辑地址映射到存储器的N个存储颗粒的BANK上的目标位置，对N个存储颗粒的BANK上的目标位置进行数据读写；其中，N个存储颗粒的BANK上的目标位置分布在不同的区域，N个目标位置不再位于相同的区域内，使得在对存储器的单次读写的过程中，存储器的出错率不会因为逻辑地址的不同而发生明显波动，保证存储器的出错率稳定在一个较小的范围内。

Description

一种数据处理系统、存储器、数据读写方法及设备
相关申请的交叉引用
本申请要求在2023年06月29日提交中国国家知识产权局、申请号为202310794233.2、申请名称为“一种存储装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中；本申请要求在2023年09月15日提交中国国家知识产权局、申请号为202311199956.4、申请名称为“一种数据处理系统、存储器、数据读写方法及设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及一种数据处理系统、存储器、数据读写方法及设备。
背景技术
内存寻址通常是指根据处理器发送的逻辑地址定位到内存中存储颗粒中BANK的某个位置。在一些存储器中，逻辑地址上的数据通常是分布在各个存储颗粒中的，该各个存储颗粒是共享该逻辑地址的。也即在内存寻址的过程中，需要确定该各个存储颗粒中BANK的某个位置，也即需要定位多个位置。
事实上，由于存储器内部电路的设计，存储颗粒的BANK可能包括多个出错率范围不同的区域，若内存寻址时，该多个位置均位于所属BANK中出错率范围最高的区域，那么，在该逻辑地址上进行数据读写时出错的概率将会翻倍增大。相反的，若内存寻址时，该多个位置均位于所属BANK中出错率范围最低的区域，那么，在该逻辑地址上进行数据读写时出错的概率将大幅度减少。
可见，基于已有的内存寻址方式，该存储器整体的出错率会随着逻辑地址的变化而发生变化，存储器整体的出错率并不稳定，这也对后续将存储器设计为具备纠错能力的存储器增大了难度。
发明内容
本申请实施例提供的一种数据处理系统、存储器、数据读写方法及设备，用以稳定存储器的出错率。
第一方面，本申请实施例提供了一种数据处理系统，该数据处理系统包括处理器以及存储器。
处理器向存储器发送读写请求，该读写请求用于请求对存储器进行数据读写，读写请求中携带有数据的逻辑地址。
存储器在接收该读写请求后，将逻辑地址映射到存储器的N个存储颗粒的BANK上的目标位置，对N个存储颗粒的BANK上的目标位置进行数据读写；其中，N个存储颗粒的BANK上的目标位置分布在不同的区域，N为正整数，BANK上的区域是基于出错率划分形成的，不同区域的出错率不同。
通过上述系统，对于同一个逻辑地址，存储器将该逻辑地址映射到N个存储颗粒的BANK上的目标位置，该N个目标位置分布在不同的区域内。N个目标位置不再位于相同的区域内，使得在对存储器的单次读写的过程中，存储器的出错率不会因为逻辑地址的不同而发生明显波动，保证存储器的出错率稳定在一个较小的范围内。
在一种可能的实现方式中，存储器具备地址重映射功能，存储器对外提供该地址重映射功能的使能选项。例如，处理器在发送读写请求之前，向存储器发送地址重映射指令，地址重映射指令用于使能存储器的地址重映射功能，这样处理器能够根据实际需要使能存储器的地址重映射功能。
在一种可能的实现方式中，存储器包括N个第一地址重映射模块，每个存储颗粒对应一个第一地址重映射模块，控制电路在接收到地址重映射指令后，根据地址重映射指令控制M个第一地址重映射模块处于工作状态，其中，M为正整数，M不大于N。
其中，任一处于工作状态的第一地址重映射模块对逻辑地址转换后的物理地址进行修改，修改后的物理地址指向第一地址重映射模块对应的存储颗粒的BANK上的目标位置。
通过上述系统，处于工作状态的第一地址重映射模块能够修改物理地址，由于N个存储颗粒中M个存储颗粒对应的第一地址重映射模块能够修改该物理地址，使得M个存储颗粒所获取的物理地址不完全相同，进一步保证逻辑地址最终能够映射到N个存储颗粒的不同区域内的目标位置上。
在一种可能的实现方式中，处于工作状态的第一地址重映射模块在对物理地址进行修改时，可以对物理地址中指向BANK中行和/或列的字段进行修改。
通过上述系统，处于工作状态的第一地址重映射模块只需改变物理地址中的部分字段，即可保证逻辑地址最终能够映射到N个存储颗粒的不同区域内的目标位置上，实现方式较为简单。
在一种可能的实现方式中，未处于工作状态的第一地址重映射模块不对物理地址进行修改，维持物理地址中各个字段不变，物理地址指向第一地址重映射模块对应的存储颗粒的BANK上的目标位置。
通过上述系统，处于工作状态的第一地址重映射模块与未处于工作状态的第一地址重映射模块对物理地址的处理方式不同，最终能够保证N个存储颗粒所获得的N个物理地址是不同的，不同的N个物理地址映射到N个存储颗粒的BANK的目标地址也将属于不同的区域。
在一种可能的实现方式中，任一存储颗粒根据从所对应的第一地址重映射模块获取的物理地址确定存储颗粒的BANK上的目标位置，对目标位置进行数据读写。其中，存储颗粒从处于工作状态的第二地址重映射模块所获取的物理地址为修改后的物理地址，存储颗粒从未处于工作状态的第二地址重映射模块所获取的物理地址为原始的物理地址。
通过上述系统，N个存储颗粒从所对应的第一地址重映射模块获取的物理地址不再是完全相同的，最终确定的存储颗粒的BANK上的目标位置也不同。
在一种可能的实现方式中，在前述说明中，存储器的地址重映射功能通过直接修改逻辑地址转换的物理地址来实现的。存储器的地址重映射功能也可以通过修改逻辑地址来实现。下面对这种实现方式进行说明。控制电路包括N个第二地址重映射模块，每个存储颗粒对应一个第二地址重映射模块。
控制电路根据地址重映射指令控制M个第二地址重映射模块处于工作状态，其中，M不大于N。
任一处于工作状态的第二地址重映射模块对逻辑地址进行修改，修改后的逻辑地址映射到第二地址重映射模块对应的存储颗粒的BANK上的目标位置。
通过上述系统，处于工作状态的第二地址重映射模块能够修改逻辑地址，由于N个存储颗粒中M个存储颗粒对应的第二地址重映射模块能够修改该逻辑地址，使得M个存储颗粒所获取的由该逻辑地址转换后的物理地址不完全相同，进一步保证逻辑地址最终能够映射到N个存储颗粒的不同区域内的目标位置上。
在一种可能的实现方式中，处于工作状态的第二地址重映射模块对逻辑地址中指向BANK中行和/或列的字段进行修改。
通过上述系统，处于工作状态的第二地址重映射模块只需改变逻辑地址中的部分字段，即可保证逻辑地址最终能够映射到N个存储颗粒的不同区域内的目标位置上，实现方式较为简单。
在一种可能的实现方式中，未处于工作状态的第二地址重映射模块维持逻辑地址中各个字段不变。逻辑地址指向第一地址重映射模块对应的存储颗粒的BANK上的目标位置。
通过上述系统，处于工作状态的第二地址重映射模块与未处于工作状态的第二地址重映射模块对逻辑地址的处理方式不同，最终能够保证N个存储颗粒所获得的N个物理地址是不同的，不同的N个物理地址映射到N个存储颗粒的BANK的目标位置也将属于不同的区域。
在一种可能的实现方式中，控制电路包括地址转换模块；地址转换模块将从第二地址重映射模块获取的逻辑地址转换为物理地址；将物理地址发送给第二地址重映射模块对应的存储颗粒。其中，地址转换模块从处于工作状态的第二地址重映射模块所获取的逻辑地址为修改后的逻辑地址，地址转换模块从未处于工作状态的第二地址重映射模块所获取的逻辑地址为原始的逻辑地址。
通过上述系统，地址转换模块能够实现逻辑地址到物理地址的转换，不同的逻辑地址所转换成的物理地址也将不同，保证存储器所接收到的该逻辑地址能够映射到N个存储颗粒的BANK、分布在不同区域的目标位置。
第二方面，本申请还提供了一种存储器，存储器具有实现上述第一方面以及任一可能的是实现方式中存储器所具备的功能，部分有益效果可以参见第一方面的描述此处不再赘述。该存储器包括控制电路以及N个存储颗粒，N为正整数。
在该存储器中，控制电路接收处理器发送的读写请求，该读取请求用于请求对存储器进行数据读写，读写请求中携带有数据的逻辑地址。控制电路在接收到该读写请求后，将该逻辑地址转换为物理地址，将逻辑地址转换后的物理地址分别发送给存储器的N个存储颗粒，物理地址指向存储器的N个存储颗粒的BANK上的目标位置，N个存储颗粒的BANK上的目标位置分布在不同的区域，N为正整数。不同区域是基于BANK内的出错率划分形成的，不同区域的出错率范围不同。
任一存储颗粒在接收到物理地址后，对存储颗粒的BANK上的目标位置进行数据读写；
通过上述存储器，对于同一个逻辑地址，在存储器内部可以被映射到N个存储颗粒的BANK上的目标位置，这N个目标位置分布在不同的区域，保证存储器的出错率不会随着该存储器所接收到的逻辑地址的不同而发生明显波动。
在一种可能的实现方式中，控制电路接收处理器发送的发送地址重映射指令，地址重映射指令用于使能存储器的地址重映射功能。
在一种可能的实现方式中，存储器包括N个第一地址重映射模块，每个存储颗粒包括一个第一地址重映射模块，控制电路根据地址重映射指令控制M个第一地址重映射模块处于工作状态，其中，M为正整数，M不大于N。
任一处于工作状态的第一地址重映射模块对逻辑地址转换后的物理地址进行修改，修改后的物理地址指向第一地址重映射模块对应的存储颗粒的BANK上的目标位置。
在一种可能的实现方式中，处于工作状态的第一地址重映射模块对物理地址中指向BANK中行和/或列的字段进行修改。
在一种可能的实现方式中，未处于工作状态的第一地址重映射模块维持物理地址中各个字段不变，物理地址指向第一地址重映射模块对应的存储颗粒的BANK上的目标位置。
在一种可能的实现方式中，任一存储颗粒根据从所对应的第一地址重映射模块获取的物理地址确定存储颗粒的BANK上的目标位置，对目标位置进行数据读写。其中，存储颗粒从处于工作状态的第一地址重映射模块获取的物理地址为修改后的物理地址，存储颗粒从未处于工作状态的第一地址重映射模块获取的物理地址为原始的物理地址。
在一种可能的实现方式中，控制电路包括N个第二地址重映射模块，每个存储颗粒对应一个第二地址重映射模块，控制电路根据地址重映射指令控制M个第二地址重映射模块处于工作状态，其中，M为正整数，M不大于N。
任一处于工作状态的第二地址重映射模块对逻辑地址进行修改，修改后的逻辑地址指向第二地址重映射模块对应的存储颗粒的BANK上的目标位置。
在一种可能的实现方式中，处于工作状态的第二地址重映射模块对逻辑地址中指向BANK中行和/或列的字段进行修改。
在一种可能的实现方式中，未处于工作状态的第二地址重映射模块维持逻辑地址中各个字段不变。逻辑地址映射到第二地址重映射模块对应的存储颗粒的BANK上的目标位置。
在一种可能的实现方式中，控制电路包括地址转换模块；地址转换模块将从第二地址重映射模块获取的逻辑地址转换为物理地址；将物理地址发送给第二地址重映射模块对应的存储颗粒。地址转换模块从处于工作状态的第二地址重映射模块所获取的逻辑地址为修改后的逻辑地址，地址转换模块从未处于工作状态的第二地址重映射模块所获取的逻辑地址为原始的逻辑地址。
第三方面，本申请还提供了一种数据读写方法，在该数据读写方法中，存储器具有实现上述第一方面以及任一可能的是实现方式中存储器的功能，有益效果可以参见第一方面的描述此处不再赘述。
控制电路接收处理器发送的读写请求，读取请求用于请求对存储器进行数据读写，读写请求中携带有数据的逻辑地址；将逻辑地址转换为物理地址，将逻辑地址转换后的物理地址分别发送给N个存储颗粒，物理地址指向存储器的N个存储颗粒的BANK上的目标位置，其中，N个存储颗粒的BANK上的目标位置分布在不同的区域；
任一存储颗粒对存储颗粒的BANK上的目标位置进行数据读写。
在一种可能的实现方式中，控制电路还可以接收处理器发送的发送地址重映射指令，地址重映射指令用于使能方法的地址重映射功能。
在一种可能的实现方式中，存储器包括N个第一地址重映射模块，每个存储颗粒对应一个第一地址重映射模块，控制电路根据地址重映射指令控制M个第一地址重映射模块处于工作状态，其中，M不大于N。
任一处于工作状态的第一地址重映射模块对逻辑地址转换后的物理地址进行修改，修改后的物理地址指向第一地址重映射模块对应的存储颗粒的BANK上的目标位置。
在一种可能的实现方式中，处于工作状态的第一地址重映射模块对逻辑地址转换后的物理地址进行修改时，处于工作状态的第一地址重映射模块对物理地址中指向BANK中行和/或列的字段进行修改。
在一种可能的实现方式中，未处于工作状态的第一地址重映射模块维持物理地址中各个字段不变， 物理地址指向第一地址重映射模块对应的存储颗粒的BANK上的目标位置。
在一种可能的实现方式中，任一存储颗粒对存储颗粒的BANK上的目标位置进行数据读写时，任一存储颗粒根据从所对应的第一地址重映射模块获取的物理地址确定存储颗粒的BANK上的目标位置，对目标位置进行数据读写。
在一种可能的实现方式中，控制电路包括N个第二地址重映射模块，每个存储颗粒对应一个第二地址重映射模块，控制电路将逻辑地址转换为物理地址时，控制电路根据地址重映射指令控制M个第二地址重映射模块处于工作状态，其中，M不大于N。
任一处于工作状态的第二地址重映射模块对逻辑地址进行修改，修改后的逻辑地址指向第二地址重映射模块对应的存储颗粒的BANK上的目标位置。
在一种可能的实现方式中，未处于工作状态的第二地址重映射模块维持逻辑地址中各个字段不变，逻辑地址指向第二地址重映射模块对应的存储颗粒的BANK上的目标位置。
在一种可能的实现方式中，控制电路包括地址转换模块；地址转换模块将从第二地址重映射模块获取的逻辑地址转换为物理地址；将物理地址发送给第二地址重映射模块对应的存储颗粒。地址转换模块从处于工作状态的第二地址重映射模块所获取的逻辑地址为修改后的逻辑地址，地址转换模块从未处于工作状态的第二地址重映射模块所获取的逻辑地址为原始的逻辑地址。
第四方面，本申请还提供了一种计算设备，该计算设备包括上述第二方面以及第为方面的各个可能的实现方式中提及的存储器，可选的，还可以包括处理器。
第五方面，本申请还提供一种计算机可读存储介质，计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述第三方面以及第三方面的各个可能的实现方式中的方法。
第六方面，本申请还提供一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第三方面以及第三方面的各个可能的实现方式中的方法。
第七方面，本申请还提供一种计算机芯片，芯片与存储器相连，芯片用于读取并执行存储器中存储的软件程序，执行上述第三方面以及第三方面的各个可能的实现方式中的方法。
附图说明
图1为存储器中内存寻址的示意图；
图2位本申请实施例提供的一种数据处理系统的结构示意图；
图3位本申请实施例提供的一种存储器的结构示意图；
图4位本申请实施例提供的一种存储颗粒的结构示意图；
图5A位本申请实施例提供的一种存储颗粒的BANK内区域的分布示意图；
图5B～5D位本申请实施例提供的一种存储颗粒的BANK内物理地址的映射示意图；
图6A～6B位本申请实施例提供的一种存储颗粒的BANK的分布示意图；
图7为本申请实施例提供的一种数据读写方法示意图；
图8位本申请实施例提供的一种存储器的结构示意图；
图9为本申请实施例提供的一种数据读写方法示意图。
具体实施方式
在对本申请实施例提及的数据处理系统、存储器、数据读写方法以及设备介绍之前，先对本申请实施例所涉及的内存寻址方式进行说明。
内存寻址方式：
通常，作为内存的存储器可以包括多个存储颗粒(chip)。该存储器可以相变存储器(phase change memory，PCM)，也可以为动态随机存储器(dynamic random access memory，DRAM)，也可以为其他类型的存储器。
从硬件结构上，存储颗粒是该存储器中存储数据的最小物理单元。任一存储颗粒内部的存储空间还可以进步进行划分，每个存储颗粒的包括多个BANK，每个BANK可以看成一个存储矩阵，该存储矩阵像一个格子阵。这个“格子阵”有很多列(column)和很多行(row)。当需要取该存储空间中的某个数据时，只需要指定BANK、该BANK中的行、以及列。每个BANK的大小、行数以及列数都是相对固定的，也即每个BANK所覆盖的逻辑地址范围是固定的。
在PCM或DRAM这类存储器中，存储器所包括的多个存储颗粒共享同一组逻辑地址。也就是说，该存储器在接收到携带有逻辑地址的读写请求后，存储器内部的控制电路将该逻辑地址转换为物理地址，将该物理地址发送给各个存储颗粒，每个存储颗粒中部署的地址解码电路会对该物理地址进行解析，解析出指向BANK、column、row的地址信息，并对该地址信息所指向的BANK、column、row进行数据读写。
如图1所示，为存储器中内存寻址的示意图，图1中示例性的展示了存储器中一个存储颗粒的寻址方式，在该存储颗粒中设置有地址寄存器。该地址寄存器用于接收来自该存储器的控制电路发送的物理地址。地址寄存器在接收到物理地址后，会将所接收到的物理地址发送到存储颗粒中的地址解码电路。地址解码电路能够从所接收到的物理地址中确定指向BANK、column、row的地址信息，进而定位到存储颗粒中的BANK，以及该BANK中的行或列。
具体的，该地址解码电路包括BANK控制逻辑、列地址解码逻辑、以及行地址解码逻辑。地址寄存器在接收到物理地址后可以将物理地址中表征BANK的部分(如4bit)发送给BANK控制逻辑，将逻辑地址中表征列(column)的部分(如15bit)发送给列地址解码逻辑，将逻辑地址中表征行(row)的部分(如11bit)发送给行地址解码逻辑。BANK控制逻辑根据所接收到的部分物理地址解析出指向BANK的地址信息，列地址解码逻辑根据所接收到的部分物理地址解析出指向列的地址信息，行地址解码逻辑根据所接收到的部分物理地址解析出指向行的地址信息。
当存储器包括8个存储颗粒时，每个存储颗粒可以贡献部分数据，如每个存储颗粒贡献8字节(byte)数据，这样在每次数据读写操作所读写的数据量为每个存储颗粒所贡献的数据量的总和，如一次数据读写操作所读写的数据量为64byte数据。该逻辑地址上的数据从物理位置上是分布在该存储器的各个存储颗粒中的。
由于每个存储颗粒的地址解码电路所解析的物理地址是基于同一个逻辑地址转换而来的，最终解析出的指向BANK、column、row的地址信息通常也是相同的。换句话说，该逻辑地址会映射到每个存储颗粒内部的相同位置处，或者也可以理解为同一个物理地址会映射到每个存储颗粒内部的相同位置处。
由于存储器内部电路的走线方式以及存储器内部的驱动电压的设计方式等因素的影响，会导致每个存储颗粒的BANK中不同区域的出错率不同，也即在每个BANK可以根据出错率进一步划分为多个区域，每个区域内出错率的范围是相同的，而不同区域的出错率的范围不同。也即在存储颗粒的每个BANK中包括出错率较高的区域、出错率较低的区域以及出错率适中的区域。若逻辑地址映射到的BANK中的位置传输出错率较高的区域，那么，在该位置上数据读写的出错概率较高，也即读出的数据或者写入的数据可能存在出错。若逻辑地址映射到的BANK中的位置传输出错率较低的区域，那么，在该位置上数据读写的出错概率较低，也即读出的数据或者写入的数据不容易出错。其中，出错率指示了在该位置或区域内进行数据读写出现错误数据的概率。在本申请实施例，并不限定出错率的具体计算方式，某个位置或者某个区域的出错率可以等于执行设定次数的数据读写操作中出错的比特数量与设定次数的数据读写操作所读写的总比特数的比值，也可以等于单位时间内执行的多次数据读写操作中出错的比特数量与设定次数的数据读写操作所读写的总比特数的比值。
可见，同一个逻辑地址(或该逻辑地址所转换的物理地址)最终会映射到每个存储颗粒的某个BANK的相同位置上，由于位置相同，那么该位置所属的区域的出错率的范围也将是相同的，若所属的区域的出错率较高，那么，将导致从该逻辑地址上读写数据的出错率会翻倍。
也即，在这种内存寻址方式中，在对存储器进行数据读写时，存储器整体的出错率会随着数据所在的区域发生变化，较不稳定。另外，为了降低存储器整体的出错率，会为存储器增加纠错电路，而不稳定的出错率也会对纠错电路的设置增加难度。
为此，在本申请所提及的存储器具备地址重映射功能，该具备该功能的存储器在对逻辑地址进行映射时，该逻辑地址所映射到的每个存储颗粒的BANK的位置可以是不同的，也即该逻辑地址映射到的各个BANK中的位置不再属于同一个出错率的范围相同的区域，逻辑地址映射到的各个BANK中的位置可以分布在多个区域中。这样，逻辑地址映射到的各个BANK中的位置的出错率不再是完全相同的。存储器的地址重映射功能具备两种实现方式，一种实现方式为对存储器中各个存储颗粒对所接收到的逻辑地址转换后的物理地址进行处理，该存储器的地址重映射功能借助存储颗粒内部的第一地址重映射模块(第一地址重映射模块用于对物理地址进行修改)实现。另一种实现方式为存储器中控制电路将逻辑地址转换为不完全相同的物理地址，并分别向各个存储颗粒发送该不完全相同的物理地址，该存储器的 地址重映射功能借助控制电路内部的第二地址重映射模块(第二地址重映射模块用于对逻辑地址进行修改)实现。无论采用哪一种实现方式，其最终效果均使得同一个逻辑地址上最终映射到各个存储颗粒的BANK中的不同位置上，这样，在对存储器进行数据读写时，存储器整体的出错率不会随着数据所在的区域发生较大的波动，存储器整体的出错率较为稳定。
第一种实现方式：该存储器的地址重映射功能借助存储颗粒内部的第一地址重映射模块实现。
下面结合附图对本申请实施例提供的数据处理系统进行说明。如图2所示，为本申请实施例提供的一种数据处理系统的结构示意图。在该数据处理系统10中包括处理器100以及存储器200。
处理器100为该系统的计算核心。处理器100能够完成主要的数据计算操作。处理器100在执行数据计算操作过程中，可以访问存储器200，以在存储器200中读取数据或写入数据。例如，处理器100能够从存储器200中读取数据，对读取的数据进行数据计算；处理器100还可以将数据计算后产生的数据存储在存储器200中。
处理器100在访问存储器200时，向存储器200发送读写请求，该读写请求中携带有数据的逻辑地址，以指示存储器200对该逻辑地址进行数据读写。
在本申请实施例中，处理器100除了能够访问存储器200之外。处理器100还能够使能存储器200地址重映射功能。例如，处理器100可以向存储器200发送地址重映射指令，该地址重映射指令用于使能该存储器200地址重映射功能。
处理器100可以是中央处理器(central processing unit，CPU)，也可以是其他特定的集成电路。处理器100还可以是其他通用处理器、数字信号处理器(digital signal processing,DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field programmable gate array,FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。
存储器200具备数据存储功能，存储器200中可以存储处理器100进行数据计算所需的数据，还可以存储处理器100数据计算后产生的数据。示例性的，存储器200接收处理来自处理器100的读写请求，对该逻辑地址进行数据读写，将处理器100进行数据计算后的数据写入到该逻辑地址上或者从该逻辑地址上读取处理器100进行数据计算所需的数据，将读取的数据反馈给处理器100。
在本申请实施例中，存储器200还具备地址重映射功能，存储器200能够将逻辑地址映射到多个BANK的目标位置上，该多个BANK的目标位置分布在多个区域内，其中，不同区域对应不同的出错率范围。
对外，存储器200可以提供地址重映射功能的使能选项，也即存储器200允许该存储器200之外的装置使能该地址重映射功能。在使能该地址重映射功能的情况下，存储器200可以将所接收到的逻辑地址映射到多个BANK的目标位置上，该多个BANK的目标位置分布在多个区域内。在未使能该地址重映射功能的情况下，存储器200可以将所接收到的逻辑地址映射到多个BANK的相同位置上。
本申请实施例并不限定存储器200提供地址重映射功能的使能选项的方式，例如，存储器200的装置上配置有地址重映射功能的使能开关，用户可以根据实际需要打开或者关闭该地址重映射功能的使能开关。又例如，存储器200配置地址重映射指令的解析功能，存储器200之外的装置可以向该存储器200发送地址重映射指令，存储器200通过解析接收到的地址重映射指令，使能该地址重映射功能。
此外针对使能地址重映射功能的情况，存储器200还可以对外提供多种不同的地址重映射策略。任一地址重映射策略描述了下列的部分或全部信息：
处于工作状态的第一地址重映射模块222的数量；
任一处于工作状态的第一地址重映射模块222对逻辑地址转换后的物理地址的修改方式。
不同的地址重映射策略所描述的处于工作状态的第一地址重映射模块222的数量和/或任一处于工作状态的第一地址重映射模块222对逻辑地址转换后的物理地址的修改方式可能不同。
相应的，本申请实施例也不限定存储器200提供多种不同的地址重映射策略的方式。例如，在存储器200上配置了多种不同地址重映射策略的选择按钮，用户可以根据实际需要通过该选择按钮选择地址重映射策略。又例如，存储器200配置地址重映射指令的解析功能，存储器200之外的装置向该存储器200发送的地址重映射指令除了指示使能该地址重映射功能，还可以指示某一种地址重映射策略，存储器200通过解析接收到的地址重映射指令，使能该地址重映射功能，并采用该地址重映射指令中所指示地址重映射策略的进行地址重映射。
当然，在实际应用中，也可以在存储器200出厂前使能该地址重映射功能，也即存储器200在出厂 后该地址重映射功能处于使能状态，无需额外操作。
下面结合图3对存储器200的结构进行说明，如图3所示，为本申请实施例提供的一种存储器200，在该存储器200包括控制电路210以及多个存储颗粒220。关于存储颗粒220的说明具体可以参见前述说明，此处不再赘述。
在该存储器200中，存储颗粒220主要用于存储数据，而控制电路210则是该存储器200的控制中心，控制电路210能够对该存储器200所接收的读写请求进行处理。也即控制电路210能够解析该读写请求中携带的逻辑地址，根据该逻辑地址对各个存储颗粒220进行数据读写。
在本申请实施例中，控制电路210能够将逻辑地址转换为物理地址，并将该物理地址发送给每个存储颗粒220上。而在任一存储颗粒220中，该物理地址指向到该存储颗粒220的一个BANK的目标位置处。
在该存储器200使能地址重映射功能的情况下，该多个BANK的目标位置分布在不同的区域，不同区域对应不同的出错率范围。
在该存储器200未使能地址重映射功能的情况下，该多个BANK的目标位置分布在相同区域。
可选的，当存储器200对外提供地址重映射功能的使能选项时，控制电路210能够检测地址重映射功能的使能状态，也即确定是否使能地址重映射功能。例如，当存储器200的装置上配置有地址重映射功能的使能开关，控制电路210可以检测该地址重映射功能的使能开关，以此确定是否使能地址重映射功能。又例如，当存储器200配置地址重映射指令的解析功能，该解析功能可以由控制电路210实现，控制电路210可以解析所接收到的地址重映射指令，使能该地址重映射功能。
在后续说明中，只针对存储器200使能地址重映射功能的情况进行说明，对于存储器200未使能地址重映射功能的情况，存储器200内部对逻辑地址进行数据读写的方式可以参见图1所示的方式，此处不再赘述。
从图1所示的内存寻址方式可知，逻辑地址映射到各个存储颗粒220时，控制电路210需要对逻辑地址转换，获得对应的物理地址，之后该物理地址传输给各个存储颗粒220，各个存储颗粒220对该物理地址解析，确定指向BANK、行、列的地址信息，之后再根据指向BANK、行、列的地址信息定位到BANK中的位置。
在本申请实施例中，不同存储颗粒220在对物理地址进行解析时，可以采用不同的解析方式，采用不同的解析方式最终获得指向BANK、行、列的地址信息是不完全相同的。这里不完全相同是指采用不同的解析方式获得的BANK、行、列的地址信息完全不同或者部分不同。
假设，当对同一个物理地址进行分别采用两种不同的方式进行解析时，可以产生两组地址信息，每组地址信息包括指向BANK、行和列的地址信息，若该两组地址信息中指向BANK的地址信息相同，指向行和列的地址信息完全不同，那么两组地址信息将分别对应该BANK上两个不同的位置，进而该两个位置所在的区域也可能不同。若该两组地址信息中指向BANK以及行的地址信息相同，指向列的地址信息不同，那么两组地址信息将分别对应一个BANK上不同位置，进而该两个位置所在的区域也有可能不同。
在该存储器200使能地址重映射功能的情况下，为了保证逻辑地址所映射到的多个BANK的目标位置分布在不同的区域，存储颗粒220对该物理地址所采用的解析方式可以完全不同，以获取多组不完全相同的地址信息，也即在多个存储颗粒220中，存储颗粒220可以将物理地址转换为多组不完全相同的地址信息，该多组不完全相同对应多个BANK中的不同的目标位置，这样，该多个BANK的目标位置也将不再属于相同区域。
在本申请实施例中，“不完全相同”表示两种情况，一种为部分相同部分不同。另一种为完全不同。
各个存储颗粒220对该物理地址所采用的解析方式可以部分不同，以获取不完全相同的多组地址信息，也即对在该多个存储颗粒220中的部分存储颗粒220，对物理地址采用一种解析方式对逻辑地址进行解析，最终获得多组相同的地址信息，对该多个存储颗粒220中的另一部分存储颗粒220，对物理地址采用另一种解析方式对逻辑地址进行解析，最终获得多组相同的地址信息。这样，最终获取的不完全相同的多组地址信息，多组地址信息中一部分对应多个BANK中的相同的一个目标位置，多组地址信息中另一部分对应多个BANK中的相同的另一个目标位置。
例如，各个的存储颗粒220对该物理地址所采用两种不同的解析方式，其中，存储颗粒220-1、存储颗粒220-2、存储颗粒220-3、存储颗粒220-4采用一种解析方式，存储颗粒220-5、存储颗粒220-6、 存储颗粒220-7、存储颗粒220-8采用另一种解析方式，那么，存储颗粒220-1、存储颗粒220-2、存储颗粒220-3、存储颗粒220-4中解析所获得的四组地址信息是相同的，分别指向存储颗粒220-1、存储颗粒220-2、存储颗粒220-3、存储颗粒220-4中某个BANK上的目标位置A。该各个目标位置A在所属BANK中的位置是相同的，也即是多个BANK中相同的目标位置。存储颗粒220-5、存储颗粒220-6、存储颗粒220-7、存储颗粒220-8中解析所获得的四组地址信息是相同的，分别指向存储颗粒220-5、存储颗粒220-6、存储颗粒220-7、存储颗粒220-8中某个BANK上的目标位置B。该各个目标位置B在所属的BANK中的位置是相同的，也即是多个BANK中相同的目标位置。
本申请实施例并不限定存储颗粒220对物理地址所采用的具体解析方式，凡是能够将物理地址解析为指向BANK、行、列的地址信息的方式均适用于本申请实施例。例如，存储颗粒220在解析物理地址的过程中，可以修改物理地址的部分字段，之后再基于第一映射关系对修改后的物理地址进行分析，进而生成指向BANK、行、列的地址信息。该第一映射关系记录了物理地址中各个字段与BANK、行、列的对应关系。
下面对存储器200的结构以及具体功能进行说明，如图4所示，为本申请实施例提供的一种存储器200的结构示意图，该存储器200包括控制电路210以及多个存储颗粒220，每个存储颗粒220包括地址寄存器221、第一地址重映射模块222、以及地址解码电路223。
地址寄存器221为具备存储功能的寄存器，第一地址重映射模块222、以及地址解码电路223可以为逻辑电路，本申请实施例并不限定第一地址重映射模块222、以及地址解码电路223内部具体结构，凡是能够实现相应的功能的逻辑电路均可以作为第一地址重映射模块222、以及地址解码电路223。
其中，每个存储颗粒220中，第一地址重映射模块222设置在地址寄存器221以及地址解码电路223之间，也即地址寄存器221向地址解码电路223发送的物理地址会先经过第一地址重映射模块222，第一地址重映射模块222在对物理地址进行处理操作后，可以将执行处理操作后的物理地址发送给地址解码电路223。第一地址重映射模块222在对物理地址可以执行两种处理操作中的一种，一种为对该物理地址进行修改，另一种为维持该物理地址中的各个字段不变。其中，处于工作状态该第一地址重映射模块222可以对该物理地址进行修改，未处于工作状态该第一地址重映射模块222维持该物理地址的各个字段不变。
对于任一存储颗粒220，地址寄存器221用于存储该控制电路210发送的物理地址。通常，控制电路210在发送物理地址时，需要经过多个时钟周期，才能将完整的物理地址发送给存储颗粒220。也即，控制电路210在一个时钟周期所传递数据的数据量是有限的，控制电路210可以分多次将该物理地址中所包括的字段发送给存储颗粒220，地址寄存器221可以接收、并缓存控制电路210所发送的物理地址所包括的字段。例如，控制电路210在每个时钟周期可以发送6比特的地址，物理地址的总长度为48比特，控制电路210可以通过8个时钟周期将该48比特的物理地址发送给存储颗粒220。地址寄存器221每接收6个比特，缓存该6比特，直至缓存的数据量达到48比特。
当地址寄存器221接收到了该物理地址所包括的所有地址后，地址寄存器221可以将物理地址发送给第一地址重映射模块222。
第一地址重映射模块222在接收到地址寄存器221发送的物理地址后，可以对物理地址执行处理操作，并将执行处理操作后的物理地址发送给地址解码电路223本申请实施例并不限定该第一地址重映射模块222对物理地址的修改方式。例如，第一地址重映射模块222可以对物理地址中的部分字段取反，又例如，第一地址重映射模块222可以对物理地址中的部分字段和预设值做减法，获取差值，利用该差值替换该物理地址中的该部分字段。
地址解码电路223在从第一地址重映射模块222获取物理地址后，可以基于第一映射关系对该物理地址进行分析，获得指向BANK、行、列的地址信息，进而确定出该存储颗粒220中的BANK上的目标位置，对该目标地址进行数据读写。本申请实施例并不限定地址解码电路223根据物理地址中获得指向BANK、行、列的地址信息的具体实现方式，凡是对该物理地址分析，获得指向BANK、行、列的地址信息的方式均适用于本申请实施例。
具体的，该地址解码电路223包括BANK控制逻辑、列地址解码逻辑、以及行地址解码逻辑。第一地址重映射模块222在对物理地址修改后，可以将修改后的物理地址中表征BANK的部分(如4bit)发送给BANK控制逻辑，将物理地址中表征列(column)的部分(如15bit)发送给列地址解码逻辑，将物理地址中表征行(row)的部分(如11bit)发送给行地址解码逻辑。BANK控制逻辑根据所接收到 的部分物理地址获得指向BANK的地址信息，列地址解码逻辑根据所接收到的部分物理地址获得指向列的地址信息，行地址解码逻辑根据所接收到的部分物理地址获得指向列的地址信息。
该地址解码电路223在获得指向BANK、行以及列的地址信息后，即可定位该BANK的目标位置上，通过改变该目标位置中器件的工作电压实现数据读写。
从图1可知，地址寄存器221会将物理地址发送给地址解码电路223，地址解码电路223则可以对所接收到的物理地址进行解析，获得指向BANK、行、列的地址信息。在本申请实施例中，在地址解码电路223之前增设第一地址重映射模块222，在地址解码电路223之前增设的第一地址重映射模块222能够对该地址解码电路223所接收到的物理地址进行修改，这样，地址解码电路223可以对修改后的物理地址进行解析。这种，修改方式仅需要在存储器200原有的设计中增加部分电路逻辑，修改方式简单，成本较低。
下面基于图4所示的控制电路210，列举几种存储器200实现地址重映射功能的具体方式。
在介绍这几种具体实现方式之前，先假设经过对存储器200的测试，确定该存储器200的BANK中包括三种区域，每个区域对应的出错率的范围不同。为方便说明，这三个区域分别称为AREA1、AREA2、AREA3区域。这三个区域所内的物理地址分布可以如表1所示。
表1
其中，ADDR[M]表示物理地址的第M位，ADDR[M：N]表示物理地址的第N位到第M位。举例来说，ADDR[1]＝0表示物理地址的第1位为0。ADDR[2：8]+ADDR[9：31]>＝40则表示物理地址中第2位到第8位与物理地址中第9位到第31位的2倍的和大于或等于40。
如图5A所示，为一个BANK中AREA1、AREA2、AREA3区域的分布示意图，其中，AREA1区域位于BANK的下方，AREA3区域位于BANK的上方，AREA2区域位于BANK的中间区域。经过测试在三个区域中，AREA1区域的出错率最高，AREA2区域的出错率居中，AREA3区域颜色的出错率最低。
需要说明的是，BANK中不同出错率范围的区域划分，与该存储器200内部控制电路210的走线以及存储器200中驱动电压的设计等多个因素有关，BANK所包括的区域的数量以及每个区域的出错率范围会随着存储器200的具体设计有关。另外，在具体测试时，BANK中不同出错率范围的区域的数量以及每个区域的出错率范围也会因为测试参数的设置发生变化。例如，在具体测试时，可以选择了更高的精确度或者出错率的档位选择更多时，BANK所包括的区域也可能变多。表1仅是列举了其中一种可能的分布情况。
对其中任一一个存储颗粒220，存储器200可以采用下列两种方式实现地址重映射。
方式一、将指向该存储颗粒220的BANK中AREA1区域内的某个位置的物理地址映射到AREA3区域内的目标位置。
AREA1区域以及AREA3区域内的位置的行不同，故而从AREA1区域到AREA3区域的映射需要改变物理地址中表征行的字段。
第一地址重映射模块222对该物理地址中表征行与列的字段进行修改，这样根据修改后的物理地址获取的指向BANK、行、列的地址信息与根据未修改之前的物理地址获取的指向BANK、行、列的地址信息中指向行、列的地址信息的会发生变化。
例如，修改后的物理地址中表征行的字段ADDR’[15：12]满足：
ADDR’[15：12]＝40-ADDR[15：12]
如图5B所示，地址寄存器221将物理地址发送该第一地址重映射模块222，第一地址重映射模块222对物理地址表征行的字段进行修改后，指向该存储颗粒220的BANK中AREA1区域内的某个位置的物理地址将被映射到AREA3区域内的目标位置。
方式二、将指向该存储颗粒220的BANK中AREA1区域内的某个位置的物理地址映射到AREA2区域内的目标位置。
从AREA1区域到AREA2区域的映射最简单的方式是改变物理地址中表征行的字段、或者表征行和列的字段。
1)、改变物理地址中表征行的字段。
第一地址重映射模块222可以对该物理地址中表征行的字段进行修改，这样根据修改后的物理地址获取的指向BANK、行、列的地址信息与根据未修改之前的物理地址获取的指向BANK、行、列的地址信息中指向行的地址信息的会发生变化。
也即第一地址重映射模块222只需要修改后的物理地址中表征行的字段即可。例如，第一地址重映射模块222可以对物理地址中表征行的字段中的某一位或多位取反，如可以将物理地址中表征行的字段中的一位ADDR[16]取反，也即修改后的物理地址中表征行的一位ADDR’[16]，满足：ADDR’[13]＝invADDR[16]。
如图5C所示，在控制电路210中地址寄存器221将物理地址中的行字段发送该第一地址重映射模块222，第一地址重映射模块222对物理地址中的行字段进行修改后，指向该存储颗粒220的BANK中AREA1区域内的某个位置的物理地址将被映射到AREA2区域内的目标位置。
2)、改变物理地址中表征行和列的字段。
第一地址重映射模块222可以对该物理地址中表征行和列的字段进列修改，这样根据修改后的物理地址获取的指向BANK、行、列的地址信息与根据未修改之前的物理地址获取的指向BANK、行、列的地址信息中指向列的地址信息的会发生变化。
也即第一地址重映射模块222需要修改后的物理地址中表征行和列的字段即可。例如，第一地址重映射模块222可以对物理地址中表征列的字段中的某一位或多位取反，如可以将物理地址中表征列的字段中的一位ADDR[23]取反，也即修改后的物理地址中表征列的一位ADDR’[23]，满足：ADDR’[23]＝invADDR[23]，第一地址重映射模块222可以对物理地址中表征行的字段中的某一位或多位取反，如可以将物理地址中表征行的字段中的一位ADDR[16]取反，也即修改后的物理地址中表征行的一位ADDR’[16]，满足：ADDR’[13]＝invADDR[16]。
如图5D所示，在控制电路210中地址寄存器221将物理地址中的列字段发送该第一地址重映射模块222，第一地址重映射模块222对物理地址中的列字段进列修改后，指向该存储颗粒220的BANK中AREA1区域内的某个位置的物理地址将被映射到AREA2区域内的目标位置。
上述第一地址重映射模块222对物理地址进行修改的具体方式仅是举例。在实际应用中，第一地址重映射模块222对物理地址进行修改的方式可以根据物理地址中表征行、列的字段所在的位置以及不同出错率范围的区域的分布位置进行设计。
除此之外，在实际应用中，鉴于存储颗粒220的设计方式不同，存储颗粒220内部BANK可以是采用平面的方式排布的，也即存储颗粒220所包括的各个BANK位于同一个平面。存储颗粒220内部BANK也可以采用三维方式排布，也即在存储颗粒220中的某个BANK可以包括堆叠的多层。
如图6A为存储颗粒220内部BANK是采用平面的方式排布的示意图，在该存储颗粒220内部BANK处于同一平面内。在这种排布方式中，该存储颗粒220内部，BANK中的区域均位于同一个平面内，也即进行地址重映射时，可以改变物理地址中表征行/或列的字段即可。
如图6B为存储颗粒220内部BANK是采用三维的方式排布的示意图，在该存储颗粒220内部每个BANK包括上下两层。这里仅是以BANK包括两层为例，事实上，BANK也可以包括三层甚至更多层。
对于该BANK的每一层中可以包括多个不同的区域，每个区域对应的出错率范围也不同，而且由于存储器200内部的设计等因素，该BANK中上下两层中相对区域的出错率范围也可能不同。其中相对区域是指同个BANK内位置是相对的两个区域。
在这种排布方式中，物理地址通常会包括表征BANK中层的字段，除了通过该改变物理地址中表 征行/或列的字段实现地址重映射之外，也可以通过改变物理地址中表征BANK中层的字段实现地址重映射。
前述说明中，所列举的仅是以举例的方式展示了几种可能的实现地址重映射的具体方式。本申请实施例中对控制电路210实现地址重映射时对物理地址中各个字段的修改方式并不做限定，凡是实现从指向一个区域的位置的物理地址映射到另一个区域的位置的针对物理地址修改方式均适用于本申请实施例。
此外，在一些场景中，不同BANK中相同行以及列的位置上的出错率也不同，也即不同BANK内相同位置的出错率也可能不同。在这种场景中，第一地址重映射模块222在对物理地址进行修改时，还可以修改该物理地址中表征BANK的比特，其修改方式与第一地址重映射模块222修改该物理地址中表征行或列的比特的方式类似，此处不再赘述。
基于图4所示的控制电路210中，在存储器200使能地址重映射功能的情况下，存储器200内部并不需要所有第一地址重映射模块222处于工作状态。也即在存储器200使能地址重映射功能的情况下，只需要保证该多个第一地址重映射模块222中部分第一地址重映射模块222能够对所接收到的物理地址进行修改即可。其他第一地址重映射模块222则不需要对所接收到的物理地址进行修改，在接收到物理地址后，可以该物理地址直接发送给地址解码电路223。
举例来说，存储器200包括N个存储颗粒，那么该存储器200也将包括N个第一地址重映射模块222，在存储器200中可以使能M个第一地址重映射模块222，该M个第一地址重映射模块222处于工作状态。其中，M为小于N的正整数。
存储器200中第一地址重映射模块222是否处于工作状态可以是由控制电路210自身设置的，例如，当控制电路210在接收到地址重映射指令后，控制电路210可以控制该多个第一地址重映射模块222中数量等于设定数值的第一地址重映射模块222处于工作状态。
存储器200中第一地址重映射模块222是否处于工作状态、哪些第一地址重映射模块222处于工作状态也可以在存储器200出厂前就设置好的，也即在出厂前已将该多个第一地址重映射模块222中部分第一地址重映射模块222设置为工作状态。
存储器200中第一地址重映射模块222是否处于工作状态、以及处于工作状态的第一地址重映射模块222也可以是由处理器100指示的。例如，处理器100所发送的地址重映射指令中除了指示使能地址重映射功能，还携带了地址重映射策略，该地址重映射策略指示了处于工作状态的第一地址重映射模块222的数量(如M)，控制电路210可以控制该多个第一地址重映射模块222中部分第一地址重映射模块222处于工作状态，该部分第一地址重映射模块222的数量满足地址重映射指令的指示。又例如，处理器100所发送的地址重映射指令中除了指示使能地址重映射功能，还指示了工作状态的第一地址重映射模块222，也即告知了哪些第一地址重映射模块222需要处于工作状态，控制电路210可以控制该多个第一地址重映射模块222中部分第一地址重映射模块222处于工作状态，该部分第一地址重映射模块222即为地址重映射指令所指示的第一地址重映射模块222。
此外，若该地址重映射策略还指示了处于工作状态的第一地址重映射模块222对物理地址的修改方式，控制电路210还可以控制处于工作状态的第一地址重映射模块222采用地址重映射策略所指示的修改方式对所接收到的物理地址进行修改。
当然，在实际应用中，若每个处于工作状态的第一地址重映射模块222对物理地址的修改方式不同，存储器200内部也可以控制所有第一地址重映射模块222处于工作状态，由于每个处于工作状态的第一地址重映射模块222对物理地址的修改方式，那么，在各个存储颗粒220中第一地址重映射模块222处理后的物理地址(也即修改后的物理地址)也将不完全相同，该多个不完全相同的物理地址将指向各个存储颗粒220的BANK中的目标位置上。
在图4所示的控制电路210中，为每个存储颗粒220设置了一个对应的第一地址重映射模块222，在实际应用中，存储器200也可以仅是对部分存储颗粒220设置第一地址重映射模块222。在出厂前可以将该第一地址重映射模块222中设置为工作状态，或者在处理器100发送指示使能地址重映射功能的地址重映射指令时，控制电路210控制所包括的第一地址重映射模块222处于工作状态。
下面结合图7对本申请提供的数据读写方法进行说明，这里以存储器200对外提供地址重映射功能的使能选项为例进行说明，对于存储器200对外不提供地址重映射功能的使能选项的情况，可以省略步骤700～701。
步骤700：处理器100向存储器200发送地址重映射指令，该地址重映射指令用于指示使能地址重映射功能该地址重映射指令还指示了需要处于工作状态的第一地址重映射模块222。
步骤701：存储器200接收该地址重映射指令，根据该地址重映射指令控制该地址重映射指令指示的第一地址重映射模块222处于工作状态。
步骤702：处理器100向存储器200发送读写请求，该读写请求中携带了数据的逻辑地址。
步骤703：存储器200接收该读写请求，在该存储器200的每个存储颗粒220中将该逻辑地址映射到该存储颗粒220的BANK上的目标位置。
在存储器200内部，控制电路210在将逻辑地址转换为物理地址后，向各个存储颗粒220发送该物理地址，每个存储颗粒220内部地址寄存器221接收控制电路210所发送的物理地址，将物理地址发送给每个存储颗粒220的第一地址重映射模块222，对于处于工作状态的第一地址重映射模块222，第一地址重映射模块222对物理地址进行修改，将修改后的物理地址发送给该存储颗粒220的地址解码电路223，地址解码电路223对修改后的物理地址进行分析，获得执行BANK、行、列的地址信息，进而根据该地址信息定位到BANK上的目标位置。
对于不处于工作状态的第一地址重映射模块222，第一地址重映射模块222将接收到的物理地址中发送给该存储颗粒220的地址解码电路223，地址解码电路223对所获取的物理地址进行分析，获得执行BANK、行、列的地址信息，进而根据该地址信息定位到BANK上的目标位置。
步骤704：存储器200对该每个存储颗粒220的BANK上的目标位置进行数据读写。
当该读写请求为请求读取数据的读取请求时，存储器200从该每个存储颗粒220的BANK上的目标位置读取数据，将从各个存储颗粒220读取的数据汇总后反馈给处理器100。
当该读写请求为请求写入数据的写入请求时，存储器200在该每个存储颗粒220的BANK上的目标位置写入该写入请求携带的数据，其中，在每个目标位置上写入的数据为该写入请求所携带的部分数据，所有目标位置上写入的数据为该写入请求所携带的数据。
第二种实现方式：该存储器200的地址重映射功能借助控制电路210内部的第二地址重映射模块211实现。
在该种实现方式中，本申请实施例所提供的一种数据处理系统10的结构以及该数据处理系统中包括处理器100以及存储器200的功能与图2所示的数据处理系统类似，具体可以参见前述说明此处不再赘述。
区别在于，在该种实现方式中，针对使能地址重映射功能的情况，存储器200还可以对外提供多种不同的地址重映射策略。任一地址重映射策略描述了下列的部分或全部信息：
处于工作状态的第二地址重映射模块211的数量；
任一处于工作状态的第二地址重映射模块211对逻辑地址的修改方式。
不同的地址重映射策略所描述的处于工作状态的第二地址重映射模块211的数量和/或任一处于工作状态的第二地址重映射模块211对逻辑地址转换后的物理地址的修改方式可能不同。
相应的，本申请实施例也不限定存储器200提供多种不同的地址重映射策略的方式。例如，在存储器200上配置了多种不同地址重映射策略的选择按钮，用户可以根据实际需要通过该选择按钮选择地址重映射策略。又例如，存储器200配置地址重映射指令的解析功能，存储器200之外的装置向该存储器200发送的地址重映射指令除了指示使能该地址重映射功能，还可以指示某一种地址重映射策略，存储器200通过解析接收到的地址重映射指令，使能该地址重映射功能，并采用该地址重映射指令中所指示地址重映射策略的进行地址重映射。
下面对存储器200的结构进行说明，与图3所示的存储器200的结构类似，在该种实现方式中，在该存储器200包括控制电路210以及多个存储颗粒220。但在该种实现方式在，控制电路210与存储颗粒220的结构与图3所示的存储器200的结构不同。存储颗粒220的结构与图1所示的实施例中存储颗粒220的结构类似，具体可以参见前述说明，此处不再赘述。
在该存储器200中，存储颗粒220主要用于存储数据，而控制电路210则是该存储器200的控制中心，控制电路210能够对该存储器200所接收的读写请求进行处理。也即控制电路210能够解析该读写请求中携带的逻辑地址，根据该逻辑地址对各个存储颗粒220进行数据读写。
在本申请实施例中，控制电路210能够将逻辑地址分别映射到每个存储颗粒220上。而在任一存储颗粒220中，该逻辑地址可以映射到该存储颗粒220的一个BANK的目标位置处。也即控制电路210， 可以将该逻辑地址分别映射到的多个BANK的目标位置处。
在该存储器200使能地址重映射功能的情况下，该多个BANK的目标位置分布在不同的区域，不同区域对应不同的出错率范围。
在该存储器200未使能地址重映射功能的情况下，该多个BANK的目标位置分布在相同区域。
可选的，当存储器200对外提供地址重映射功能的使能选项时，控制电路210能够检测地址重映射功能的使能状态，也即确定是否使能地址重映射功能。例如，当存储器200的装置上配置有地址重映射功能的使能开关，控制电路210可以检测该地址重映射功能的使能开关，以此确定是否使能地址重映射功能。又例如，当存储器200配置地址重映射指令的解析功能，该解析功能可以由控制电路210实现，控制电路210可以解析所接收到的地址重映射指令，使能该地址重映射功能。
在后续说明中，只针对存储器200使能地址重映射功能的情况进行说明，对于存储器200未使能地址重映射功能的情况，控制电路210对逻辑地址进行地址读写的方式可以参见图1所示的方式，此处不再赘述。
从图1所示的内存寻址方式可知，逻辑地址映射到各个存储颗粒220时，控制电路210需要对逻辑地址进行转换获得对应的物理地址，之后再将物理地址发送给各个存储颗粒220。
在本申请实施例中，控制电路210在对逻辑地址进行转换时，针对不同的存储颗粒220，可以采用不同的转换方式，采用不同的转换方式最终获得不同的物理地址。
控制电路210针对各个的存储颗粒220对该逻辑地址所采用的转换方式可以不完全相同，以获取不完全相同的多个物理地址。例如，对在该多个存储颗粒220中的部分存储颗粒220，控制电路210对逻辑地址采用一种转换方式对逻辑地址进行转换，最终获得多个相同的物理地址，对该多个存储颗粒220中的另一部分存储颗粒220，控制电路210对逻辑地址采用另一种转换方式对逻辑地址进行转换，最终获得多个相同的物理地址。这样，最终获取的该不完全相同的多个物理地址，多个物理地址中一部分对应多个BANK中的相同的一个目标位置，多个物理地址中另一部分对应多个BANK中的相同的另一个目标位置。又例如，控制电路210针对各个的存储颗粒220对该逻辑地址所采用的转换方式完全不同，以获取多组完全不同的地址信息，也即对在不同存储颗粒220中，控制电路210对逻辑地址采用不同的转换方式对逻辑地址进行转换，最终获得完全不同的多个物理地址，这样该多个物理地址对应多个BANK中的不同的目标位置，这样，该多个BANK的目标位置也将不再属于相同区域。
举例来说，控制电路210针对各个的存储颗粒220对该逻辑地址所采用两种不同的转换方式，其中，对存储颗粒220-1、存储颗粒220-2、存储颗粒220-3、存储颗粒220-4采用一种转换方式，对存储颗粒220-5、存储颗粒220-6、存储颗粒220-7、存储颗粒220-8采用另一种转换方式，那么，在存储颗粒220-1、存储颗粒220-2、存储颗粒220-3、存储颗粒220-4所获得的物理地址是相同的，分别指向存储颗粒220-1、存储颗粒220-2、存储颗粒220-3、存储颗粒220-4中某个BANK上的目标位置A。该各个目标位置A在所属BANK中的位置是相同的，也即是多个BANK中相同的目标位置。在存储颗粒220-5、存储颗粒220-6、存储颗粒220-7、存储颗粒220-8中所获得的物理地址是相同的，分别指向存储颗粒220-5、存储颗粒220-6、存储颗粒220-7、存储颗粒220-8中某个BANK上的目标位置B。该各个目标位置B在所属的BANK中的位置是相同的，也即是多个BANK中相同的目标位置。
本申请实施例并不限定控制电路210对逻辑地址所采用的具体转换方式，凡是能够将逻辑地址转换为物理地址的方式均适用于本申请实施例。例如，控制电路210在转换逻辑地址的过程中，可以修改逻辑地址的中部分或全部字段，之后再基于预设的映射关系对修改后的逻辑地址进行分析，进而生成物理地址。
下面对存储器200的结构以及具体功能进行说明，如图8所示，为本申请实施例提供的一种存储器200的结构示意图，该控制电路210中包括多个第二地址重映射模块211以及多个地址转换模块212。第二地址重映射模块211以及多个地址转换模块212可以为逻辑电路，本申请实施例并不限定第二地址重映射模块211以及多个地址转换模块212内部的具体结构，凡是能够实现相应功能的逻辑电路均适用于本申请实施例。
其中，每个存储颗粒220对应一个第二地址重映射模块211以及一个地址转换模块212，第二地址重映射模块211设置在存储颗粒220以及地址转换模块212之间，也即逻辑地址会先经过第二地址重映射模块211，第二地址重映射模块211在对逻辑地址进行处理操作后，可以将执行处理操作后的逻辑地 址发送给地址转换模块212。地址转换模块212用于基于第二映射关系将执行处理操作后的逻辑地址转换为物理地址。第二映射关系为物理地址与逻辑地址之间的映射关系。
第二地址重映射模块211在对逻辑地址可以执行两种处理操作中的一种，一种为对该逻辑地址进行修改，本申请实施例并不限定该第二地址重映射模块211对逻辑地址的修改方式。例如，第二地址重映射模块211可以对逻辑地址中的部分字段取反，又例如，第二地址重映射模块211可以对逻辑地址中的部分字段和预设值做减法，获取差值，利用该差值替换该逻辑地址中的该部分字段。另一种为维持该逻辑地址中的各个字段不变。其中，处于工作状态该第二地址重映射模块211可以对该逻辑地址进行修改，未处于工作状态该第二地址重映射模块211维持该逻辑地址的各个字段不变。
地址转换模块212在接收到第二地址重映射模块211发送的逻辑地址后，可以第二映射关系将所获取的逻辑地址转换为对应的物理地址，将该物理地址转换给存储颗粒220，存储颗粒220内部对物理地址的解析过程可以参见图1所示实施例中的相关说明此处不再赘述。
图8仅是列举了控制电路210的一种可能结构示意图。本申请实施例并不限定该控制电路210中各个模块的划分方式。
第二地址重映射模块211对逻辑地址进行修改的方式与第一地址重映射模块222对的物理地址的修改方式类似，具体可以参见前述内容此处不再赘述，区别在于，第二地址重映射模块211对逻辑地址中表征BANK、行、以及列的字段的具体取值以及对各个字段所采用的具体操作可能不同。
基于图8所示的存储器200中，在存储器200使能地址重映射功能的情况下，控制电路210内部并不需要所有第二地址重映射模块211处于工作状态。也即在存储器200使能地址重映射功能的情况下，只需要保证该多个第二地址重映射模块211中部分第二地址重映射模块211能够对所接收到的逻辑地址进行修改即可。其他第二地址重映射模块211则不需要对所接收到的逻辑地址进行修改，在接收到逻辑地址后，可以该路基地址直接发送给地址解码电路223。
第二地址重映射模块211处于工作状态的设置方式与第一地址重映射模块222处于工作状态的设置方式类似具体可以参见前述说明此处不再赘述。
下面结合图9对本申请提供的数据读写方法进行说明，这里以存储器200对外提供地址重映射功能的使能选项为例进行说明，对于存储器200对外不提供地址重映射功能的使能选项的情况，可以省略步骤900～901。
步骤900：处理器100向存储器200发送地址重映射指令，该地址重映射指令用于指示使能地址重映射功能该地址重映射指令还指示了需要处于工作状态的第二地址重映射模块211。
步骤901：存储器200接收该地址重映射指令，根据该地址重映射指令控制该地址重映射指令指示的第二地址重映射模块211处于工作状态。
步骤902：处理器100向存储器200发送读写请求，该读写请求中携带了逻辑地址。
步骤903：存储器200接收该读写请求，在该存储器200的每个存储颗粒220中将该逻辑地址映射到该存储颗粒220的BANK上的目标位置。
在存储器200内部，各个存储颗粒220的第二地址重映射模块211获取该逻辑地址发送，对于处于工作状态的第二地址重映射模块211，第二地址重映射模块211对逻辑地址中的字段进行修改，将修改后的逻辑地址发送给该存储颗粒220对应的地址转换模块212，地址转换模块212对修改后的逻辑地址进行转换获得物理地址，将该物理地址发送给对应的存储颗粒220。
对于未处于工作状态的第二地址重映射模块211，第二地址重映射模块211将接收到的逻辑地址中发送给该存储颗粒220的地址转换模块212，该地址转换模块212对逻辑地址进行转换获得物理地址，将该物理地址发送给对应的存储颗粒220。
步骤904：存储器200对该每个存储颗粒220的BANK上的目标位置进行数据读写。
当该读写请求为请求读取数据的读取请求时，存储器200从该每个存储颗粒220的BANK上的目标位置读取数据，将从各个存储颗粒220读取的数据汇总后反馈给处理器100。
当该读写请求为请求写入数据的写入请求时，存储器200在该每个存储颗粒220的BANK上的目标位置写入该写入请求携带的数据，其中，在每个目标位置上写入的数据为该写入请求所携带的部分数据，所有目标位置上写入的数据为该写入请求所携带的数据。
需要说明的是，在第二实现方式中是以第二地址重映射模块211直接修改逻辑地址为例进行说明的。作为一种可能的实现方式，第二地址重映射模块211可以不直接修改逻辑地址，而是对地址转换模块 212转换后获得的物理地址进行修改，再将修改后的物理地址发送给对应的存储颗粒220。
需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。在本申请的实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
上述实施例，可以全部或部分地通过软件、硬件、固件或其他任意组合来实现。当使用软件实现时，上述实施例可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载或执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以为通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集合的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质。半导体介质可以是固态硬盘(solid state drive，SSD)。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变形在内。

Claims (32)

  1. 一种数据处理系统，其特征在于，所述系统包括：
    处理器，用于向存储器发送读写请求，所述读写请求中携带有数据的逻辑地址；
    存储器，用于接收所述读写请求，将所述逻辑地址映射到所述存储器的N个存储颗粒的BANK上的目标位置，对所述N个存储颗粒的BANK上的目标位置进行数据读写；
    其中，所述N个存储颗粒的BANK上的目标位置分布在不同的区域，N为正整数。
  2. 如权利要求1所述的系统，其特征在于，所述处理器在发送所述读写请求之前，还用于：向所述存储器发送地址重映射指令，所述地址重映射指令用于使能所述存储器的地址重映射功能。
  3. 如权利要求2所述的系统，其特征在于，所述存储器包括控制电路以及N个第一地址重映射模块，每个存储颗粒对应一个第一地址重映射模块，所述控制电路，用于：
    根据所述地址重映射指令控制所述M个第一地址重映射模块处于工作状态，其中，M不大于N；
    任一处于工作状态的所述第一地址重映射模块，用于：对所述逻辑地址转换后的物理地址进行修改，修改后的所述物理地址指向所述第一地址重映射模块对应的存储颗粒的BANK上的目标位置。
  4. 如权利要求3所述的系统，其特征在于，处于工作状态的所述第一地址重映射模块，用于：
    对所述物理地址中指向BANK中行和/或列的字段进行修改。
  5. 如权利要求2～4任一项所述的系统，其特征在于，所述第一地址重映射模块位于所对应的存储颗粒中；
    所述控制电路，还用于接收所述读写请求，将所述逻辑地址转换为物理地址，向每个存储颗粒发送所述物理地址。
  6. 如权利要求3所述的系统，其特征在于，未处于工作状态的所述第一地址重映射模块，用于：
    维持所述物理地址中各个字段不变，所述物理地址指向所述第一地址重映射模块对应的存储颗粒的BANK上的目标位置。
  7. 如权利要求2～4任一项所述的系统，其特征在于，任一所述存储颗粒，用于：根据从所对应的所述第一地址重映射模块获取的物理地址确定所述存储颗粒的BANK上的目标位置，对所述目标位置进行数据读写。
  8. 如权利要求2所述的系统，其特征在于，所述控制电路包括N个第二地址重映射模块，每个存储颗粒对应一个第二地址重映射模块，所述控制电路，用于：
    根据所述地址重映射指令控制所述M个第一地址重映射模块处于工作状态，其中，M不大于N；
    任一处于工作状态的所述第二地址重映射模块，用于对所述逻辑地址进行修改，修改后的所述逻辑地址映射到所述第二地址重映射模块对应的存储颗粒的BANK上的目标位置。
  9. 如权利要求8所述的系统，其特征在于，处于工作状态的所述第二地址重映射模块，用于：
    对所述逻辑地址中指向BANK中行和/或列的字段进行修改。
  10. 如权利要求8所述的系统，其特征在于，未处于工作状态的所述第二地址重映射模块，用于：
    维持所述逻辑地址中各个字段不变。
  11. 如权利要求2、8～10任一项所述的系统，其特征在于，所述控制电路包括地址转换模块；
    所述地址转换模块，用于从所述第二地址重映射模块获取的逻辑地址；将从所述第二地址重映射模块获取的逻辑地址转换为物理地址；将所述物理地址发送给所述第二地址重映射模块对应的存储颗粒。
  12. 一种存储器，其特征在于，所述存储器包括控制电路以及N个存储颗粒；
    控制电路，用于接收处理器发送的读写请求，所述读取请求用于请求对存储器进行数据读写，所述读写请求中携带有数据的逻辑地址；将所述逻辑地址转换为物理地址，将所述逻辑地址转换后的物理地址分别发送给所述N个存储颗粒，所述物理地址指向所述存储器的N个存储颗粒的BANK上的目标位置，其中，所述N个存储颗粒的BANK上的目标位置分布在不同的区域；
    任一所述存储颗粒，用于对所述存储颗粒的BANK上的目标位置进行数据读写。
  13. 如权利要求12所述的存储器，其特征在于，所述控制电路，还用于：接收所述处理器发送的发送地址重映射指令，所述地址重映射指令用于使能所述存储器的地址重映射功能。
  14. 如权利要求13所述的存储器，其特征在于，所述存储器包括N个第一地址重映射模块，每个存 储颗粒对应一个所述第一地址重映射模块，所述控制电路，用于：
    根据所述地址重映射指令控制所述M个第一地址重映射模块处于工作状态，其中，M不大于N；
    任一处于工作状态的所述第一地址重映射模块，用于：对所述逻辑地址转换后的物理地址进行修改，修改后的所述物理地址指向所述第一地址重映射模块对应的存储颗粒的BANK上的目标位置。
  15. 如权利要求13所述的存储器，其特征在于，处于工作状态的所述第一地址重映射模块，用于：
    对所述物理地址中指向BANK中行和/或列的字段进行修改。
  16. 如权利要求15所述的存储器，其特征在于，未处于工作状态的所述第一地址重映射模块，用于：
    维持所述物理地址中各个字段不变，所述物理地址指向所述第一地址重映射模块对应的存储颗粒的BANK上的目标位置。
  17. 如权利要求14～16任一项所述的存储器，其特征在于，任一所述存储颗粒，用于：根据从所对应的所述第一地址重映射模块获取的物理地址确定所述存储颗粒的BANK上的目标位置，对所述目标位置进行数据读写。
  18. 如权利要求13所述的存储器，其特征在于，所述控制电路包括N个第二地址重映射模块，每个存储颗粒对应一个第二地址重映射模块，所述控制电路，用于：
    根据所述地址重映射指令控制所述M个第二地址重映射模块处于工作状态，其中，M不大于N；
    任一处于工作状态的所述第二地址重映射模块，用于对所述逻辑地址进行修改，修改后的所述逻辑地址映射到所述第二地址重映射模块对应的存储颗粒的BANK上的目标位置。
  19. 如权利要求18所述的存储器，其特征在于，处于工作状态的所述第二地址重映射模块，用于：
    对所述逻辑地址中指向BANK中行和/或列的字段进行修改。
  20. 如权利要求18所述的存储器，其特征在于，未处于工作状态的所述第二地址重映射模块，用于：
    维持所述逻辑地址中各个字段不变，所述逻辑地址映射到所述第二地址重映射模块对应的存储颗粒的BANK上的目标位置。
  21. 如权利要求13、18～20任一项所述的存储器，其特征在于，所述控制电路包括地址转换模块；
    所述地址转换模块，用于将从所述第二地址重映射模块获取的逻辑地址转换为物理地址；将所述物理地址发送给所述第二地址重映射模块对应的存储颗粒。
  22. 一种数据读写方法，其特征在于，所述方法应用于存储器，所述包括控制电路以及N个存储颗粒，N为正整数，所述方法包括：
    所述控制电路接收处理器发送的读写请求，所述读取请求用于请求对存储器进行数据读写，所述读写请求中携带有数据的逻辑地址；将所述逻辑地址转换为物理地址，将所述逻辑地址转换后的物理地址分别发送给所述N个存储颗粒，所述物理地址指向所述存储器的N个存储颗粒的BANK上的目标位置，其中，所述N个存储颗粒的BANK上的目标位置分布在不同的区域；
    任一所述存储颗粒对所述存储颗粒的BANK上的目标位置进行数据读写。
  23. 如权利要求22所述的方法，其特征在于，所述方法还包括：
    所述控制电路接收所述处理器发送的发送地址重映射指令，所述地址重映射指令用于使能所述方法的地址重映射功能。
  24. 如权利要求23所述的方法，其特征在于，所述存储器包括N个第一地址重映射模块，每个存储颗粒对应一个所述第一地址重映射模块，所述方法还包括：
    所述控制电路根据所述地址重映射指令控制所述M个第一地址重映射模块处于工作状态，其中，M不大于N；
    任一处于工作状态的所述第一地址重映射模块对所述逻辑地址转换后的物理地址进行修改，修改后的所述物理地址指向所述第一地址重映射模块对应的存储颗粒的BANK上的目标位置。
  25. 如权利要求24所述的方法，其特征在于，所述处于工作状态的所述第一地址重映射模块对所述逻辑地址转换后的物理地址进行修改，包括：
    处于工作状态的所述第一地址重映射模块对所述物理地址中指向BANK中行和/或列的字段进行修改。
  26. 如权利要求24所述的方法，其特征在于，所述方法还包括：
    未处于工作状态的所述第一地址重映射模块维持所述物理地址中各个字段不变，所述物理地址指向 所述第一地址重映射模块对应的存储颗粒的BANK上的目标位置。
  27. 如权利要求24～26任一项所述的方法，其特征在于，所述任一所述存储颗粒对所述存储颗粒的BANK上的目标位置进行数据读写，包括：
    任一所述存储颗粒根据从所对应的所述第一地址重映射模块获取的物理地址确定所述存储颗粒的BANK上的目标位置，对所述目标位置进行数据读写。
  28. 如权利要求23所述的方法，其特征在于，所述控制电路包括N个第二地址重映射模块，每个存储颗粒对应一个第二地址重映射模块，所述方法还包括：
    所述控制电路根据所述地址重映射指令控制所述M个第二地址重映射模块处于工作状态，其中，M不大于N；
    任一处于工作状态的所述第二地址重映射模块对所述逻辑地址进行修改，修改后的所述逻辑地址指向所述第二地址重映射模块对应的存储颗粒的BANK上的目标位置。
  29. 如权利要求28所述的方法，其特征在于，所述处于工作状态的所述第二地址重映射模块对所述逻辑地址进行修改，包括：
    所述处于工作状态的所述第二地址重映射模块对所述逻辑地址中指向BANK中行和/或列的字段部分字段进行修改。
  30. 如权利要求28所述的方法，其特征在于，所述方法还包括：
    未处于工作状态的所述第二地址重映射模块维持所述逻辑地址中各个字段不变，所述逻辑地址指向所述第二地址重映射模块对应的存储颗粒的BANK上的目标位置。
  31. 如权利要求23、28～30任一项所述的方法，其特征在于，所述控制电路包括地址转换模块；所述控制电路所述逻辑地址转换为物理地址，将所述逻辑地址转换后的物理地址发送给所述存储器的N个存储颗粒，包括：
    所述地址转换模块将从所述第二地址重映射模块获取的逻辑地址转换为物理地址；将所述物理地址发送给所述第二地址重映射模块对应的存储颗粒。
  32. 一种计算设备，其特征在于，所述计算设备包括如权利要求12～21任一项所述的存储器。
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