WO2025020130A1 - 像素电路、显示装置及驱动方法 - Google Patents

像素电路、显示装置及驱动方法 Download PDF

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Publication number
WO2025020130A1
WO2025020130A1 PCT/CN2023/109362 CN2023109362W WO2025020130A1 WO 2025020130 A1 WO2025020130 A1 WO 2025020130A1 CN 2023109362 W CN2023109362 W CN 2023109362W WO 2025020130 A1 WO2025020130 A1 WO 2025020130A1
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WIPO (PCT)
Prior art keywords
transistor
electrode
control signal
coupled
signal terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
PCT/CN2023/109362
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English (en)
French (fr)
Inventor
汪锐
邱远游
张润鑫
张手强
胡明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chongqing BOE Display Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chongqing BOE Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chongqing BOE Display Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to PCT/CN2023/109362 priority Critical patent/WO2025020130A1/zh
Priority to EP23946217.9A priority patent/EP4583091A4/en
Priority to CN202380009802.6A priority patent/CN120112977A/zh
Publication of WO2025020130A1 publication Critical patent/WO2025020130A1/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit, a display device and a driving method.
  • OLED display is one of the hot topics in the field of flat panel display research today. Compared with Liquid Crystal Display (LCD), OLED display has the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle and fast response speed. Among them, the pixel circuit used to control the light emission of the light-emitting device is the core technical content of OLED display and has important research significance. However, the pixel circuit of the existing OLED display includes a large number of transistors, which leads to greater process difficulty, increased production cost, and causes the pixel circuit to occupy a larger area, which is not conducive to the OLED display to achieve higher resolution.
  • a driving transistor coupled to the light emitting device and configured to generate a driving current for driving the light emitting device to emit light according to a data voltage signal
  • a first compensation circuit coupled to the driving transistor and configured to provide a first reference signal at a first reference signal terminal to a first electrode of the driving transistor in response to a signal at a first control signal terminal;
  • a second compensation circuit coupled to the driving transistor and configured to provide the threshold voltage of the driving transistor and the first reference signal input to the first electrode of the driving transistor to the gate of the driving transistor in response to signals at the second control signal terminal and the third control signal terminal;
  • a data writing circuit coupled to the first node and configured to provide the data voltage signal of the data signal terminal to the first node in response to a signal of the fourth control signal terminal;
  • a coupling control circuit coupled to the first node and the driving transistor, and configured to couple the data voltage signal of the first node to the gate of the driving transistor;
  • the light emitting control circuit is coupled to the light emitting device and the driving transistor, and is configured to connect the first electrode of the driving transistor to the first power supply terminal and the second electrode of the driving transistor to the light emitting device in response to a signal at the light emitting control signal terminal, thereby driving the light emitting device to emit light.
  • the first compensation circuit includes: a first transistor
  • the gate of the first transistor is coupled to the first control signal terminal, the first electrode of the first transistor is coupled to the first electrode of the driving transistor, and the second electrode of the first transistor is coupled to the first reference signal terminal.
  • the second compensation circuit includes: a second transistor and a third transistor
  • the gate of the second transistor is coupled to the second control signal terminal, the first electrode of the second transistor is coupled to the second node, and the second electrode of the second transistor is coupled to the second electrode of the driving transistor;
  • the gate of the third transistor is coupled to the third control signal terminal, the first electrode of the third transistor is coupled to the gate of the driving transistor, and the second electrode of the third transistor is coupled to the second node.
  • the second compensation circuit further includes: a fourth transistor
  • the gate of the fourth transistor is coupled to the fifth control signal terminal, the first electrode of the fourth transistor is coupled to the gate of the driving transistor or the second node, and the second electrode of the fourth transistor is coupled to the first initialization signal terminal.
  • the fifth control signal terminal and the light-emitting control signal terminal may be the same signal terminal.
  • the data writing circuit includes: a fifth transistor
  • the gate of the fifth transistor is coupled to the fourth control signal terminal, the first electrode of the fifth transistor is coupled to the data signal terminal, and the second electrode of the fifth transistor is coupled to the first node. catch.
  • the coupling control circuit includes: a first capacitor
  • a first electrode of the first capacitor is coupled to the first node, and a second electrode of the first capacitor is coupled to the gate of the driving transistor.
  • the light emitting control circuit includes: a sixth transistor and a seventh transistor;
  • the gate of the sixth transistor is coupled to the light emitting control signal terminal, the first electrode of the sixth transistor is coupled to the first power supply terminal, and the second electrode of the sixth transistor is coupled to the first electrode of the driving transistor;
  • the gate of the seventh transistor is coupled to the light emitting control signal terminal, the first electrode of the seventh transistor is coupled to the second electrode of the driving transistor, and the second electrode of the seventh transistor is coupled to the light emitting device.
  • the invention further includes: a first reset circuit coupled to the light emitting device and configured to provide a signal at a second initialization signal terminal to the light emitting device in response to a signal at a sixth control signal terminal.
  • the first reset circuit includes: an eighth transistor;
  • a gate of the eighth transistor is coupled to the sixth control signal terminal, a first electrode of the eighth transistor is coupled to the light emitting device, and a second electrode of the eighth transistor is coupled to the second initialization signal terminal.
  • the method further includes: a voltage stabilizing circuit coupled to the first node and configured to stabilize the voltage of the first node.
  • the voltage stabilization circuit includes: a second capacitor
  • a first electrode of the second capacitor is coupled to the first power supply terminal, and a second electrode of the second capacitor is coupled to the first node.
  • the invention further includes: a second reset circuit coupled to the second electrode of the driving transistor and configured to provide a signal from a third initialization signal terminal to the second electrode of the driving transistor in response to a signal from a seventh control signal terminal.
  • the second reset circuit includes: a ninth transistor
  • the gate of the ninth transistor is coupled to the seventh control signal terminal, the first electrode of the ninth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the ninth transistor is coupled to the third initialization signal terminal.
  • the third reset circuit includes: a tenth transistor
  • a gate of the tenth transistor is coupled to the eighth control signal terminal, a first electrode of the tenth transistor is coupled to the first node, and a second electrode of the tenth transistor is coupled to the second reference signal terminal.
  • the third reset circuit includes: an eleventh transistor and a twelfth transistor;
  • the gate of the eleventh transistor is coupled to the eighth control signal terminal, the first electrode of the eleventh transistor is coupled to the first node, and the second electrode of the eleventh transistor is coupled to the third node;
  • a gate of the twelfth transistor is coupled to the eighth control signal terminal, a first electrode of the twelfth transistor is coupled to the third node, and a second electrode of the eleventh transistor is coupled to the second reference signal terminal.
  • the third reset circuit further includes: a thirteenth transistor
  • a gate of the thirteenth transistor is coupled to the ninth control signal terminal, a first electrode of the thirteenth transistor is coupled to the third node, and a second electrode of the thirteenth transistor is coupled to the third reference signal terminal.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned pixel circuit.
  • the first compensation circuit provides the first reference signal at the first reference signal terminal to the first electrode of the driving transistor in response to the signal at the first control signal terminal;
  • the first compensation circuit provides the first reference signal of the first reference signal terminal to the first electrode of the driving transistor in response to the signal of the first control signal terminal;
  • the second compensation circuit provides the threshold voltage of the driving transistor and the first reference signal input to the first electrode of the driving transistor to the gate of the driving transistor in response to the signals of the second control signal terminal and the third control signal terminal;
  • the data writing circuit provides the data voltage signal of the data signal terminal to the first node in response to the signal of the fourth control signal terminal; the coupling control circuit couples the data voltage signal of the first node to the gate of the driving transistor;
  • the light-emitting control circuit responds to the signal at the light-emitting control signal terminal to conduct the first electrode of the driving transistor with the first power supply terminal and the second electrode of the driving transistor with the light-emitting device, thereby driving the light-emitting device to emit light.
  • FIG1 is a schematic diagram of some structures of pixel circuits provided in an embodiment of the present disclosure.
  • FIG2 is another schematic diagram of the structure of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG3 is a flow chart of a driving method of a pixel circuit provided in an embodiment of the present disclosure
  • FIG4 is a timing diagram of some signals provided by an embodiment of the present disclosure.
  • FIG5 is a schematic diagram of some other structures of pixel circuits provided by embodiments of the present disclosure.
  • FIG6 is another signal timing diagram provided by an embodiment of the present disclosure.
  • FIG7 is a schematic diagram of some other structures of the pixel circuit provided by the embodiment of the present disclosure.
  • FIG8 is a timing diagram of some further signals provided by an embodiment of the present disclosure.
  • FIG9 is a schematic diagram of some other structures of pixel circuits provided by embodiments of the present disclosure.
  • FIG10 is a timing diagram of some further signals provided by an embodiment of the present disclosure.
  • FIG11 is a schematic diagram of some other structures of pixel circuits provided in an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of some further structures of the pixel circuit provided in the embodiment of the present disclosure.
  • the display device may include a display panel.
  • the display panel may include a substrate.
  • the substrate may include a display area and a non-display area (i.e., an area in the substrate except for the area surrounded by the display area).
  • the display area may include a plurality of pixel units arranged in an array.
  • each pixel unit includes sub-pixels of the same color or sub-pixels of multiple different colors.
  • a pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that red, green, and blue can be mixed to achieve color display.
  • a pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that red, green, blue, and white can be mixed to achieve color display.
  • the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.
  • each sub-pixel may include a pixel circuit and a light-emitting device coupled to the pixel circuit.
  • the pixel circuit may include a driving transistor to control the light-emitting device to emit light, so that the display The display panel realizes the function of displaying the picture. Due to the process, aging and other reasons, the threshold voltage Vth of the driving transistor may drift, which affects the generated driving current, resulting in poor display effect. Therefore, the threshold voltage Vth of the driving transistor is compensated, but the existing technology adopts the method of compensating the threshold voltage Vth while charging the data, which will lead to the phenomenon that the compensation and charging speed are too slow, and thus it cannot be applied to high-frequency circuits.
  • an embodiment of the present disclosure provides a pixel circuit, as shown in FIG1 , comprising:
  • the driving transistor T0 is coupled to the light emitting device L and is configured to generate a driving current for driving the light emitting device L to emit light according to the data voltage signal;
  • the first compensation circuit 10 is coupled to the driving transistor T0 and is configured to provide a first reference signal of the first reference signal terminal VREF1 to a first electrode of the driving transistor T0 in response to a signal of the first control signal terminal CS1;
  • the second compensation circuit 20 is coupled to the driving transistor T0 and is configured to provide the threshold voltage Vth of the driving transistor T0 and the first reference signal input to the first electrode of the driving transistor T0 to the gate of the driving transistor T0 in response to the signals of the second control signal terminal CS2 and the third control signal terminal CS3;
  • the data writing circuit 30 is coupled to the first node N1 and is configured to provide a data voltage signal of the data signal terminal DA to the first node N1 in response to a signal of the fourth control signal terminal CS4;
  • a coupling control circuit 40 is coupled to the first node N1 and the driving transistor T0 and is configured to couple the data voltage signal of the first node N1 to the gate of the driving transistor T0;
  • the light emitting control circuit 50 is coupled to the light emitting device L and the driving transistor T0, and is configured to connect the first electrode of the driving transistor T0 to the first power supply terminal VDD and the second electrode of the driving transistor T0 to the light emitting device L in response to the signal of the light emitting control signal terminal EM, thereby driving the light emitting device L to emit light.
  • the pixel circuit provided by the embodiment of the present disclosure realizes the time-sharing of threshold voltage Vth compensation and data charging through the cooperation among the light-emitting device, the driving transistor, the first compensation circuit, the second compensation circuit, the data writing circuit, the coupling control circuit and the light-emitting control circuit, so that the threshold voltage Vth compensation is no longer restricted, and there is more time for compensation, thereby improving the compensation effect and improving the low grayscale display effect.
  • the threshold voltage Vth of the driving transistor is compensated, which can further reduce the light-emitting control signal terminal required by the light-emitting control circuit, that is, a simple structure and fewer signal lines are adopted to realize driving the light-emitting device to emit light, thereby simplifying the preparation process, reducing the production cost and the occupied area, and improving the pixel density, which is conducive to achieving higher resolution and improving the display effect.
  • the driving transistor T0 can be set as a P-type transistor; wherein the first electrode of the driving transistor T0 can be its source, the second electrode of the driving transistor T0 can be its drain, and when the driving transistor T0 is in a saturated state, the current flows from the source of the driving transistor T0 to its drain.
  • the driving transistor T0 can also be set as an N-type transistor, which is not limited here.
  • the second pole of the light emitting device L is coupled to the second power supply terminal VSS;
  • the light emitting device L may be an electroluminescent diode.
  • the light emitting device L may include at least one of an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), a micro light emitting diode (Micro LED), a mini light emitting diode (Mini LED), etc.
  • the light emitting device L may include a stacked anode, a light emitting layer, and a cathode.
  • the light emitting layer may also include a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, and other film layers.
  • a hole injection layer may also include a hole transport layer, an electron transport layer, an electron injection layer, and other film layers.
  • the specific structure of the light emitting device L can be determined according to the needs of the practical application, and is not limited here.
  • the first compensation circuit 10 includes: a first transistor T1; wherein the gate of the first transistor T1 is coupled to the first control signal terminal CS1, the first electrode of the first transistor T1 is coupled to the first electrode of the driving transistor T0, and the second electrode of the first transistor T1 is coupled to the first reference signal terminal VREF1.
  • the first transistor T1 may be turned on under the control of the effective level of the first control signal transmitted on the first control signal terminal CS1, and may be turned off under the control of the ineffective level of the first control signal.
  • the first transistor T1 can be set as an N-type transistor, then the effective level of the first control signal is a high level, and the invalid level of the first control signal is a low level.
  • the first transistor T1 can be set as a P-type transistor, then the effective level of the first control signal is a low level, and the invalid level of the first control signal is a high level.
  • the second compensation circuit 20 includes: a second transistor T2 and a third transistor T3; wherein the gate of the second transistor T2 is coupled to the second control signal terminal CS2, the first electrode of the second transistor T2 is coupled to the second node N2, and the second electrode of the second transistor T2 is coupled to the second electrode of the driving transistor T0; the gate of the third transistor T3 is coupled to the third control signal terminal CS3, the first electrode of the third transistor T3 is coupled to the gate of the driving transistor T0, and the second electrode of the third transistor T3 is coupled to the second node N2.
  • the second transistor T2 can be turned on under the control of the effective level of the second control signal transmitted on the second control signal terminal CS2, and can be turned off under the control of the ineffective level of the second control signal.
  • the second transistor T2 can be set as an N-type transistor, then the effective level of the second control signal is a high level, and the ineffective level of the second control signal is a low level.
  • the second transistor T2 can be set as a P-type transistor, then the effective level of the second control signal is a low level, and the ineffective level of the second control signal is a high level.
  • the third transistor T3 can be turned on under the control of the effective level of the third control signal transmitted on the third control signal terminal CS3, and can be turned off under the control of the ineffective level of the third control signal.
  • the third transistor T3 can be set as an N-type transistor, then the effective level of the third control signal is a high level, and the ineffective level of the third control signal is a low level.
  • the third transistor T3 can be set as a P-type transistor, then the effective level of the third control signal is a low level, and the ineffective level of the third control signal is a high level.
  • the second compensation circuit 20 also includes: a fourth transistor T4; wherein the gate of the fourth transistor T4 is coupled to the fifth control signal terminal CS5, the first electrode of the fourth transistor T4 is coupled to the second node N2, and the second electrode of the fourth transistor T4 is coupled to the first initialization signal terminal VINIT1.
  • the fourth transistor T4 can transmit a fifth control signal at the fifth control signal terminal CS5.
  • the fourth transistor T4 can be turned on under the control of the effective level of the fifth control signal, and can be turned off under the control of the ineffective level of the fifth control signal.
  • the fourth transistor T4 can be set as an N-type transistor, then the effective level of the fifth control signal is a high level, and the ineffective level of the fifth control signal is a low level.
  • the fourth transistor T4 can be set as a P-type transistor, then the effective level of the fifth control signal is a low level, and the ineffective level of the fifth control signal is a high level.
  • the data writing circuit 30 includes: a fifth transistor T5; wherein the gate of the fifth transistor T5 is coupled to the fourth control signal terminal CS4, the first electrode of the fifth transistor T5 is coupled to the data signal terminal DA, and the second electrode of the fifth transistor T5 is coupled to the first node N1.
  • the fifth transistor T5 can be turned on under the control of the effective level of the fourth control signal transmitted on the fourth control signal terminal CS4, and can be turned off under the control of the invalid level of the fourth control signal.
  • the fifth transistor T5 can be set as an N-type transistor, then the effective level of the fourth control signal is a high level, and the invalid level of the fourth control signal is a low level.
  • the fifth transistor T5 can be set as a P-type transistor, then the effective level of the fourth control signal is a low level, and the invalid level of the fourth control signal is a high level.
  • the coupling control circuit 40 includes: a first capacitor C1 ; wherein a first electrode of the first capacitor C1 is coupled to the first node N1 , and a second electrode of the first capacitor C1 is coupled to the gate of the driving transistor T0 .
  • the light-emitting control circuit 50 includes: a sixth transistor T6 and a seventh transistor T7; wherein the gate of the sixth transistor T6 is coupled to the light-emitting control signal terminal EM, the first electrode of the sixth transistor T6 is coupled to the first power supply terminal VDD, and the second electrode of the sixth transistor T6 is coupled to the first electrode of the driving transistor T0; the gate of the seventh transistor T7 is coupled to the light-emitting control signal terminal EM, the first electrode of the seventh transistor T7 is coupled to the second electrode of the driving transistor T0, and the second electrode of the seventh transistor T7 is coupled to the light-emitting device L.
  • the sixth transistor T6 can be turned on under the control of the effective level of the light emitting control signal transmitted on the first light emitting control signal terminal EM, and can be turned off under the control of the invalid level of the light emitting control signal.
  • the sixth transistor T6 can be set as an N-type transistor, then the effective level of the light emitting control signal is a high level, and the invalid level of the light emitting control signal is a low level.
  • the sixth transistor T6 can be If it is set as a P-type transistor, the effective level of the light-emitting control signal is a low level, and the invalid level of the light-emitting control signal is a high level.
  • the seventh transistor T7 can be turned on under the control of the effective level of the light emitting control signal transmitted on the first light emitting control signal terminal EM, and can be turned off under the control of the invalid level of the light emitting control signal.
  • the seventh transistor T7 can be set as an N-type transistor, then the effective level of the light emitting control signal is a high level, and the invalid level of the light emitting control signal is a low level.
  • the seventh transistor T7 can be set as a P-type transistor, then the effective level of the light emitting control signal is a low level, and the invalid level of the light emitting control signal is a high level.
  • FIG. 2 it further includes: a first reset circuit 60 coupled to the light emitting device L, configured to provide a signal from the second initialization signal terminal VINIT2 to the light emitting device L in response to a signal from the sixth control signal terminal CS6 .
  • the first reset circuit 60 includes: an eighth transistor T8; wherein the gate of the eighth transistor T8 is coupled to the sixth control signal terminal CS6, the first electrode of the eighth transistor T8 is coupled to the light-emitting device L, and the second electrode of the eighth transistor T8 is coupled to the second initialization signal terminal VINIT2.
  • the eighth transistor T8 can be turned on under the control of the effective level of the sixth control signal transmitted on the sixth control signal terminal CS6, and can be turned off under the control of the ineffective level of the sixth control signal.
  • the eighth transistor T8 can be set as an N-type transistor, then the effective level of the sixth control signal is a high level, and the ineffective level of the sixth control signal is a low level.
  • the eighth transistor T8 can be set as a P-type transistor, then the effective level of the sixth control signal is a low level, and the ineffective level of the sixth control signal is a high level.
  • the device further includes: a voltage stabilizing circuit 70 coupled to the first node N1 and configured to stabilize the voltage of the first node N1 .
  • the voltage stabilizing circuit 70 includes: a second capacitor C2 ; wherein a first electrode of the second capacitor C2 is coupled to the first power supply terminal VDD, and a second electrode of the second capacitor C2 is coupled to the first node N1 .
  • a third reset circuit 90 which is connected to the first The node N1 is coupled to the eighth control signal terminal CS8 and is configured to provide the signal of the second reference signal terminal VREF2 to the first node N1 in response to the signal of the eighth control signal terminal CS8.
  • the third reset circuit 90 includes: an eleventh transistor T11 and a twelfth transistor T12; wherein, the gate of the eleventh transistor T11 is coupled to the eighth control signal terminal CS8, the first electrode of the eleventh transistor T11 is coupled to the first node N1, and the second electrode of the eleventh transistor T11 is coupled to the third node N3; the gate of the twelfth transistor T12 is coupled to the eighth control signal terminal CS8, the first electrode of the twelfth transistor T12 is coupled to the third node N3, and the second electrode of the eleventh transistor T11 is coupled to the second reference signal terminal VREF2.
  • the eleventh transistor T11 can be turned on under the control of the effective level of the eighth control signal transmitted on the eighth control signal terminal CS8, and can be turned off under the control of the invalid level of the eighth control signal.
  • the eleventh transistor T11 can be set as an N-type transistor, then the effective level of the eighth control signal is a high level, and the invalid level of the eighth control signal is a low level.
  • the eleventh transistor T11 can be set as a P-type transistor, then the effective level of the eighth control signal is a low level, and the invalid level of the eighth control signal is a high level.
  • the twelfth transistor T12 can be turned on under the control of the effective level of the eighth control signal transmitted on the eighth control signal terminal CS8, and can be turned off under the control of the invalid level of the eighth control signal.
  • the twelfth transistor T12 can be set as an N-type transistor, then the effective level of the eighth control signal is a high level, and the invalid level of the eighth control signal is a low level.
  • the twelfth transistor T12 can be set as a P-type transistor, then the effective level of the eighth control signal is a low level, and the invalid level of the eighth control signal is a high level.
  • the first electrode of the transistor may be its source, and the second electrode may be its drain.
  • the first electrode may be its drain, and the second electrode may be its source. This is not limited here.
  • transistors using low temperature polysilicon (LTPS) material as active layers have high mobility and can be made thinner and smaller, with lower power consumption, etc.
  • the material of the active layer of at least one transistor can be set to low temperature polysilicon material. In this way, the transistor can be set to an LTPS transistor, so that the pixel circuit can achieve high mobility and can be made thinner and smaller, with lower power consumption, etc.
  • the material of the active layer of at least one of the transistors may include a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide). Of course, it may also be other metal oxide semiconductor materials, which are not limited here. In this way, the transistor may be set as an oxide-type transistor (Oxide Thin Film Transistor) to reduce the leakage current of the pixel circuit.
  • IGZO Indium Gallium Zinc Oxide
  • the transistor may be set as an oxide-type transistor (Oxide Thin Film Transistor) to reduce the leakage current of the pixel circuit.
  • all transistors may be set as LTPS transistors.
  • all transistors may be set as oxide transistors.
  • some transistors may be set as oxide transistors, and the remaining transistors may be set as LTPS transistors.
  • the leakage current of the gate of the driving transistor T0 may be smaller, and the power consumption may be lower.
  • the pixel circuit is applied to a display panel, and when the display panel reduces the refresh frequency for display, the uniformity of the display may be ensured.
  • the first power supply terminal VDD may be configured to load a constant first power supply voltage Vdd, and the first power supply voltage Vdd is generally a positive value, for example, the first power supply voltage Vdd includes 4.6, etc.
  • the second power supply terminal VSS may load a constant second power supply voltage Vss, and the second power supply voltage Vss may generally be a ground voltage or a negative value, for example, the second power supply voltage Vss includes -5, etc.
  • the specific values of the first power supply voltage Vdd and the second power supply voltage Vss may be designed and determined according to the actual application environment, and are not limited here.
  • a driving method for driving a pixel circuit is provided in an embodiment of the present disclosure, which may include the following steps:
  • the first compensation circuit in a reset stage, provides a first reference signal from a first reference signal terminal to a first electrode of the driving transistor in response to a signal from a first control signal terminal;
  • the first compensation circuit responds to the signal of the first control signal terminal, and provides the first reference signal of the first reference signal terminal to the first electrode of the driving transistor;
  • the second compensation circuit responds to the signals of the second control signal terminal and the third control signal terminal, and provides the threshold voltage of the driving transistor and the first reference signal input to the first electrode of the driving transistor to the gate of the driving transistor;
  • the data writing circuit provides the data voltage signal of the data signal terminal to the first node in response to the signal of the fourth control signal terminal;
  • the coupling control circuit couples the data voltage signal of the first node to the gate of the driving transistor;
  • the light emitting control circuit responds to the signal at the light emitting control signal terminal to conduct the first electrode of the driving transistor with the first power supply terminal, and conduct the second electrode of the driving transistor with the light emitting device, to drive the light emitting device to emit light.
  • the following takes the pixel circuit shown in FIG. 2 as an example, and describes the working process of the pixel circuit provided by the embodiment of the present disclosure in combination with the signal timing diagram shown in FIG. 4 .
  • em represents the light-emitting signal of the light-emitting control signal terminal EM
  • cs1 represents the first control signal of the first control signal terminal CS1
  • cs2 represents the second control signal of the second control signal terminal CS2
  • cs3 represents the third control signal of the third control signal terminal CS3
  • cs4 represents the fourth control signal of the fourth control signal terminal CS4
  • cs5 represents the fifth control signal of the fifth control signal terminal CS5
  • cs6 represents the sixth control signal of the sixth control signal terminal CS6
  • cs8 represents the eighth control signal of the eighth control signal terminal CS8,
  • da represents the data voltage signal of the data signal terminal DA.
  • the first transistor T1 is turned on under the control of the low level of the first control signal cs1
  • the second transistor T2 is turned off under the control of the high level of the second control signal cs2
  • the third transistor T3 is turned on under the control of the low level of the third control signal cs3
  • the fourth transistor T4 is turned on under the control of the low level of the fifth control signal cs5
  • the fifth transistor T5 is turned off under the control of the high level of the fourth control signal cs4
  • the sixth transistor T6 is turned off under the control of the high level of the light emitting signal em
  • the seventh transistor T7 is turned off under the control of the high level of the light emitting signal em
  • the eighth transistor T8 is turned on under the control of the low level of the sixth control signal cs6,
  • the eleventh transistor T11 is turned off under the control of the high level of the eighth control signal cs8, and the twelfth transistor T12 is turned off under the control of the high level of
  • the turned-on eighth transistor T8 provides the second initialization signal of the second initialization signal terminal VINIT2 to the anode of the light-emitting device L, and the voltage VL on the anode of the light-emitting device L is Vinit2.
  • Vinit1 represents the voltage of the first initialization signal
  • Vinit2 represents the voltage of the second initialization signal
  • Vref1 represents the voltage of the first reference signal.
  • the first reference signal input to the first electrode of the driving transistor T0 can pass through the driving transistor T0 formed in the diode connection mode, and input to the gate of the driving transistor T0, and compensate the threshold voltage Vth of the driving transistor T0, so that the gate Vg voltage of the driving transistor T0 is Vref1+Vth, then the voltage VN2 on the second node N2 and the voltage Vd of the second electrode of the driving transistor T0 are Vref1+Vth.
  • the turned-on eighth transistor T8 provides the second initialization signal of the second initialization signal terminal VINIT2 to the anode of the light-emitting device L, and the voltage VL on the anode of the light-emitting device L is Vinit2.
  • the turned-on twelfth transistor T12 provides the second reference signal of the second reference signal terminal VREF2 to the third node N3, and the turned-on eleventh transistor T11 provides the second reference signal on the third node N3 to the first node N1, so the voltage VN1 on the first node N1 is Vref2.
  • the second capacitor C2 stabilizes the voltage of the first node N1. Among them, Vref2 represents the voltage of the second reference signal, and Vth represents the threshold voltage of the driving transistor T0. Value voltage.
  • the first transistor T1 is turned off under the control of the high level of the first control signal cs1
  • the second transistor T2 is turned off under the control of the high level of the second control signal cs2
  • the third transistor T3 is turned off under the control of the high level of the third control signal cs3
  • the fourth transistor T4 is turned off under the control of the high level of the fifth control signal cs5
  • the fifth transistor T5 is turned on under the control of the low level of the fourth control signal cs4
  • the sixth transistor T6 is turned off under the control of the high level of the light emitting signal em
  • the seventh transistor T7 is turned off under the control of the high level of the light emitting signal em
  • the eighth transistor T8 is turned off under the control of the high level of the sixth control signal cs6,
  • the eleventh transistor T11 is turned off under the control of the high level of the eighth control signal cs8, and the twelfth transistor T12 is turned off under the control of the high level of
  • the turned-on fifth transistor T5 provides the data voltage signal of the data signal terminal DA to the first node N1, and the first capacitor C1 couples the data voltage signal of the first node N1 to the gate of the driving transistor T0, so the gate Vg voltage of the driving transistor T0 is Vref1+Vth+Vda-Vref2.
  • the second capacitor C2 stabilizes the voltage of the first node N1.
  • Vda represents the voltage of the data voltage signal.
  • the turned-on fourth transistor T4 provides the first initialization signal of the first initialization signal terminal VINIT1 to the second node N2, and the voltage VN2 on the second node N2 is Vinit1.
  • the turned-on sixth transistor T6 provides the first power supply voltage Vdd of the first power supply terminal VDD to the first electrode of the driving transistor T0, and the voltage of the first electrode Vs of the driving transistor T0 is Vdd.
  • the turned-on seventh transistor T7 turns on the second electrode of the driving transistor T0 and the light emitting device L, driving the light emitting device L to emit light.
  • the driving transistor T0 operates in the saturation region, and the driving current I generated by it can be expressed as: in, ⁇ represents the mobility of the driving transistor T0 , Cox represents the capacitance per unit area of the gate insulating layer of the driving transistor T0 , and W/L represents the channel width-to-length ratio of the driving transistor T0 .
  • the first control signal terminal CS1, the third control signal terminal CS3 and the sixth control signal terminal CS6 may be the same signal terminal, which can reduce the number of signal lines and the space occupied by wiring.
  • the second control signal terminal CS2 and the eighth control signal terminal CS8 may be the same signal terminal, which can reduce the number of signal lines and the space occupied by wiring.
  • the second compensation circuit 20 also includes: a fourth transistor T4; wherein the gate of the fourth transistor T4 is coupled to the fifth control signal terminal CS5, the first electrode of the fourth transistor T4 is coupled to the gate of the driving transistor T0, and the second electrode of the fourth transistor T4 is coupled to the first initialization signal terminal VINIT1.
  • the second control signal terminal CS2 and the third control signal terminal CS3 may be the same signal terminal.
  • the gate of the third transistor T3 is coupled to the second control signal terminal CS2. This can reduce the number of signal lines and the space occupied by wiring.
  • the third reset circuit 90 includes: a tenth transistor T10; wherein the gate of the tenth transistor T10 is coupled to the eighth control signal terminal CS8, the first electrode of the tenth transistor T10 is coupled to the first node N1, and the second electrode of the tenth transistor T10 is coupled to the second reference signal terminal VREF2.
  • the tenth transistor T10 can be turned on under the control of the effective level of the eighth control signal transmitted on the eighth control signal terminal CS8, and can be turned off under the control of the ineffective level of the eighth control signal.
  • the tenth transistor T10 can be set as an N-type transistor, then the effective level of the eighth control signal
  • the tenth transistor T10 can be set as a P-type transistor, then the effective level of the eighth control signal is a low level, and the ineffective level of the eighth control signal is a high level.
  • the following takes the pixel circuit shown in FIG. 5 as an example, and describes the working process of the pixel circuit provided by the embodiment of the present disclosure in combination with the signal timing diagram shown in FIG. 6 .
  • em represents the light-emitting signal of the light-emitting control signal terminal EM
  • cs1 represents the first control signal of the first control signal terminal CS1
  • cs2 represents the second control signal of the second control signal terminal CS2
  • cs4 represents the fourth control signal of the fourth control signal terminal CS4
  • cs5 represents the fifth control signal of the fifth control signal terminal CS5
  • cs6 represents the sixth control signal of the sixth control signal terminal CS6
  • cs8 represents the eighth control signal of the eighth control signal terminal CS8
  • da represents the data voltage signal of the data signal terminal DA
  • vinit2 represents the second initialization signal of the second initialization signal terminal VINIT2.
  • the first transistor T1 is turned on under the control of the low level of the first control signal cs1
  • the second transistor T2 is turned off under the control of the high level of the second control signal cs2
  • the third transistor T3 is turned off under the control of the high level of the second control signal cs2
  • the fourth transistor T4 is turned on under the control of the low level of the fifth control signal cs5
  • the fifth transistor T5 is turned off under the control of the high level of the fourth control signal cs4
  • the sixth transistor T6 is turned off under the control of the high level of the light emitting signal em
  • the seventh transistor T7 is turned off under the control of the high level of the light emitting signal em
  • the eighth transistor T8 is turned on under the control of the low level of the sixth control signal cs6, and the tenth transistor T10 is turned on under the control of the low level of the eighth control signal cs8.
  • the turned-on first transistor T1 provides the first reference signal of the first reference signal terminal VREF1 to the first electrode of the driving transistor T0, and the voltage Vs on the first electrode of the driving transistor T0 is Vref1.
  • the turned-on fourth transistor T4 provides the first initialization signal of the first initialization signal terminal VINIT1 to the gate of the driving transistor T0, and the voltage Vg on the gate of the driving transistor T0 is Vinit1.
  • the turned-on eighth transistor T8 provides the second initialization signal of the second initialization signal terminal VINIT2 to the anode of the light emitting device L, and the voltage VL on the anode of the light emitting device L is Vinit2.
  • the first transistor T1 is turned on under the control of the low level of the first control signal cs1
  • the second transistor T2 is turned on under the control of the low level of the second control signal cs2
  • the third transistor T3 is turned on under the control of the low level of the second control signal cs2
  • the fourth transistor T4 is turned off under the control of the high level of the fifth control signal cs5
  • the fifth transistor T5 is turned off under the control of the high level of the fourth control signal cs4
  • the sixth transistor T6 is turned off under the control of the high level of the light emitting signal em
  • the seventh transistor T7 is turned off under the control of the high level of the light emitting signal em
  • the eighth transistor T8 is turned on under the control of the low level of the sixth control signal cs6, and the tenth transistor T10 is turned off under the control of the high level of the eighth control signal cs8.
  • the turned-on first transistor T1 provides the first reference signal of the first reference signal terminal VREF1 to the first electrode of the driving transistor T0, and the voltage Vs on the first electrode of the driving transistor T0 is Vref1.
  • the turned-on second transistor T2 conducts the second electrode of the driving transistor T0 with the second node N2, and the turned-on third transistor T3 conducts the second node N2 with the gate of the driving transistor T0.
  • the first reference signal input to the first electrode of the driving transistor T0 can pass through the driving transistor T0 formed in the diode connection mode, and input to the gate of the driving transistor T0, and compensate the threshold voltage Vth of the driving transistor T0, so that the gate Vg voltage of the driving transistor T0 is Vref1+Vth, then the voltage VN2 on the second node N2 and the voltage Vd of the second electrode of the driving transistor T0 are Vref1+Vth.
  • the turned-on eighth transistor T8 provides the second initialization signal of the second initialization signal terminal VINIT2 to the anode of the light-emitting device L, and the voltage VL on the anode of the light-emitting device L is Vinit2.
  • the second capacitor C2 stabilizes the voltage of the first node N1.
  • the first transistor T1 is turned off under the control of the high level of the first control signal cs1
  • the second transistor T2 is turned off under the control of the high level of the second control signal cs2
  • the third transistor T3 is turned off under the control of the high level of the second control signal cs2
  • the fourth transistor T4 is turned off under the control of the high level of the fifth control signal cs5
  • the fifth transistor T5 is turned on under the control of the low level of the fourth control signal cs4
  • the sixth transistor T6 is turned off under the control of the high level of the light emitting signal em
  • the seventh transistor T7 is turned off under the control of the high level of the light emitting signal em
  • the eighth transistor T8 is turned off under the control of the high level of the sixth control signal cs6, and the tenth transistor T11 is turned off under the control of the high level of the eighth control signal cs8.
  • the turned-on fifth transistor T5 turns the data voltage of the data signal terminal DA
  • the signal is provided to the first node N1
  • the first capacitor C1 couples the data voltage signal of the first node N1 to the gate of the driving transistor T0, so the gate Vg voltage of the driving transistor T0 is Vref1+Vth+Vda-Vref2.
  • the second capacitor C2 stabilizes the voltage of the first node N1.
  • the first transistor T1 is turned off under the control of the high level of the first control signal cs1
  • the second transistor T2 is turned off under the control of the high level of the second control signal cs2
  • the third transistor T3 is turned off under the control of the high level of the second control signal cs2
  • the fourth transistor T4 is turned off under the control of the high level of the fifth control signal cs5
  • the fifth transistor T5 is turned off under the control of the high level of the fourth control signal cs4
  • the sixth transistor T6 is turned on under the control of the low level of the light-emitting signal em
  • the seventh transistor T7 is turned on under the control of the low level of the light-emitting signal em
  • the eighth transistor T8 is turned off under the control of the high level of the sixth control signal cs6, and the tenth transistor T10 is turned off under the control of the high level of the eighth control signal cs8.
  • the turned-on sixth transistor T6 provides the first power supply voltage Vdd of the first power supply terminal VDD to the first electrode of the driving transistor T0, so the voltage of the first electrode Vs of the driving transistor T0 is Vdd, and the turned-on seventh transistor T7 turns on the second electrode of the driving transistor T0 and the light-emitting device L, driving the light-emitting device L to emit light.
  • the driving transistor T0 works in the saturation region, and the driving current I generated by it can be expressed as:
  • the first control signal terminal CS1 and the sixth control signal terminal CS6 may be the same signal terminal, which can reduce the number of signal lines and the space occupied by wiring.
  • the fifth control signal terminal CS5 and the eighth control signal terminal CS8 may be the same signal terminal, which can reduce the number of signal lines and the space occupied by wiring.
  • the disclosed embodiment provides some further structural schematic diagrams of pixel circuits, as shown in Figure 7, which are modified from the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the second control signal terminal CS2 and the eighth control signal terminal CS8 may be the same signal terminal.
  • the gate of the tenth transistor T10 is coupled to the eighth control signal terminal CS8. This can reduce the number of signal lines and the space occupied by wiring.
  • the following takes the pixel circuit shown in FIG7 as an example, and combines the signal timing diagram shown in FIG8 to explain the present invention.
  • the working process of the pixel circuit provided by the embodiment is described below.
  • em represents the light-emitting signal of the light-emitting control signal terminal EM
  • cs1 represents the first control signal of the first control signal terminal CS1
  • cs2 represents the second control signal of the second control signal terminal CS2
  • cs4 represents the fourth control signal of the fourth control signal terminal CS4
  • cs5 represents the fifth control signal of the fifth control signal terminal CS5
  • cs6 represents the sixth control signal of the sixth control signal terminal CS6
  • da represents the data voltage signal of the data signal terminal DA
  • vinit2 represents the second initialization signal of the second initialization signal terminal VINIT2.
  • the first transistor T1 is turned on under the control of the low level of the first control signal cs1
  • the second transistor T2 is turned off under the control of the high level of the second control signal cs2
  • the third transistor T3 is turned off under the control of the high level of the second control signal cs2
  • the fourth transistor T4 is turned on under the control of the low level of the fifth control signal cs5
  • the fifth transistor T5 is turned off under the control of the high level of the fourth control signal cs4
  • the sixth transistor T6 is turned off under the control of the high level of the light emitting signal em
  • the seventh transistor T7 is turned off under the control of the high level of the light emitting signal em
  • the eighth transistor T8 is turned on under the control of the low level of the sixth control signal cs6, and the tenth transistor T10 is turned off under the control of the high level of the second control signal cs2.
  • the turned-on first transistor T1 provides the first reference signal of the first reference signal terminal VREF1 to the first electrode of the driving transistor T0, and the voltage Vs on the first electrode of the driving transistor T0 is Vref1.
  • the turned-on fourth transistor T4 provides the first initialization signal of the first initialization signal terminal VINIT1 to the gate of the driving transistor T0, and the voltage Vg on the gate of the driving transistor T0 is Vinit1.
  • the turned-on eighth transistor T8 provides the second initialization signal of the second initialization signal terminal VINIT2 to the anode of the light emitting device L, and the voltage VL on the anode of the light emitting device L is Vinit2.
  • the first transistor T1 is turned on under the control of the low level of the first control signal cs1
  • the second transistor T2 is turned on under the control of the low level of the second control signal cs2
  • the third transistor T3 is turned on under the control of the low level of the second control signal cs2
  • the fourth transistor T4 is turned off under the control of the high level of the fifth control signal cs5
  • the fifth transistor T5 is turned off under the control of the high level of the fourth control signal cs4
  • the sixth transistor T6 is turned off under the control of the high level of the light emitting signal em
  • the seventh transistor T7 is turned off under the control of the high level of the light emitting signal em
  • the eighth transistor T8 is turned on under the control of the low level of the sixth control signal cs6,
  • the tenth transistor T10 is turned on under the control of the second control signal cs2
  • the first transistor T1 is turned on under the control of the low level of .
  • the turned-on first transistor T1 provides the first reference signal of the first reference signal terminal VREF1 to the first electrode of the driving transistor T0, and the voltage Vs on the first electrode of the driving transistor T0 is Vref1.
  • the turned-on second transistor T2 turns on the second electrode of the driving transistor T0 and the second node N2, and the turned-on third transistor T3 turns on the second node N2 and the gate of the driving transistor T0.
  • the first reference signal input to the first electrode of the driving transistor T0 can pass through the driving transistor T0 formed in the diode connection mode, input to the gate of the driving transistor T0, and compensate the threshold voltage Vth of the driving transistor T0, so that the gate Vg voltage of the driving transistor T0 is Vref1+Vth, and the voltage VN2 on the second node N2 and the voltage Vd of the second electrode of the driving transistor T0 are Vref1+Vth.
  • the turned-on eighth transistor T8 provides the second initialization signal of the second initialization signal terminal VINIT2 to the anode of the light emitting device L, and the voltage VL on the anode of the light emitting device L is Vinit2.
  • the turned-on tenth transistor T10 provides the second reference signal of the second reference signal terminal VREF2 to the first node N1, and the voltage VN1 on the first node N1 is Vref2.
  • the second capacitor C2 stabilizes the voltage of the first node N1.
  • the second capacitor C2 stabilizes the voltage of the first node N1.
  • the first transistor T1 is turned off under the control of the high level of the first control signal cs1
  • the second transistor T2 is turned off under the control of the high level of the second control signal cs2
  • the third transistor T3 is turned off under the control of the high level of the second control signal cs2
  • the fourth transistor T4 is turned off under the control of the high level of the fifth control signal cs5
  • the fifth transistor T5 is turned on under the control of the low level of the fourth control signal cs4
  • the sixth transistor T6 is turned off under the control of the high level of the light emitting signal em
  • the seventh transistor T7 is turned off under the control of the high level of the light emitting signal em
  • the eighth transistor T8 is turned off under the control of the high level of the sixth control signal cs6, and the tenth transistor T11 is turned off under the control of the high level of the eighth control signal cs8.
  • the turned-on fifth transistor T5 provides the data voltage signal of the data signal terminal DA to the first node N1, and the first capacitor C1 couples the data voltage signal of the first node N1 to the gate of the driving transistor T0, so the gate Vg voltage of the driving transistor T0 is Vref1+Vth+Vda-Vref2.
  • the second capacitor C2 stabilizes the voltage of the first node N1.
  • the first transistor T1 is turned off under the control of the high level of the first control signal cs1
  • the second transistor T2 is turned off under the control of the high level of the second control signal cs2
  • the third transistor T3 is turned off under the control of the high level of the second control signal cs2
  • the fourth transistor T4 is turned off under the control of the high level of the fifth control signal cs5
  • the fifth transistor T5 is turned off under the control of the high level of the fourth control signal cs4
  • the sixth transistor T6 is turned on under the control of the low level of the light-emitting signal em
  • the seventh transistor T7 is turned on under the control of the low level of the light-emitting signal em
  • the eighth transistor T8 is turned off under the control of the high level of the sixth control signal cs6, and the tenth transistor T10 is turned off under the control of the high level of the eighth control signal cs8.
  • the turned-on sixth transistor T6 provides the first power supply voltage Vdd of the first power supply terminal VDD to the first electrode of the driving transistor T0, then the voltage of the first electrode Vs of the driving transistor T0 is Vdd, and the turned-on seventh transistor T7 turns on the second electrode of the driving transistor T0 and the light-emitting device L, driving the light-emitting device L to emit light. Then, the driving transistor T0 works in the saturation region, and the driving current I generated by it can be expressed as:
  • the first control signal terminal CS1 and the sixth control signal terminal CS6 may be the same signal terminal, which can reduce the number of signal lines and the space occupied by wiring.
  • the disclosed embodiment provides some further structural schematic diagrams of pixel circuits, as shown in Figure 9, which are modified from the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the fifth control signal terminal CS5 and the light emitting control signal terminal EM may be the same signal terminal, which can reduce the number of signal lines and the space occupied by wiring.
  • FIG. 9 it further includes: a second reset circuit 80 coupled to the second electrode of the driving transistor T0 , and configured to provide a signal from the third initialization signal terminal VINIT3 to the second electrode of the driving transistor T0 in response to a signal from the seventh control signal terminal CS7 .
  • a second reset circuit 80 coupled to the second electrode of the driving transistor T0 , and configured to provide a signal from the third initialization signal terminal VINIT3 to the second electrode of the driving transistor T0 in response to a signal from the seventh control signal terminal CS7 .
  • the second reset circuit 80 includes: a ninth transistor T9; wherein the gate of the ninth transistor T9 is coupled to the seventh control signal terminal CS7, the first electrode of the ninth transistor T9 is coupled to the second electrode of the driving transistor T0, and the second electrode of the ninth transistor T9 is coupled to the third initialization signal terminal VINIT3.
  • the ninth transistor T9 can transmit the seventh control signal at the seventh control signal terminal CS7.
  • the ninth transistor T9 can be turned on under the control of the effective level of the seventh control signal, and can be turned off under the control of the ineffective level of the seventh control signal.
  • the ninth transistor T9 can be set as an N-type transistor, then the effective level of the seventh control signal is a high level, and the ineffective level of the seventh control signal is a low level.
  • the ninth transistor T9 can be set as a P-type transistor, then the effective level of the seventh control signal is a low level, and the ineffective level of the seventh control signal is a high level.
  • the third reset circuit 90 also includes: a thirteenth transistor T13; wherein the gate of the thirteenth transistor T13 is coupled to the ninth control signal terminal CS9, the first electrode of the thirteenth transistor T13 is coupled to the third node N3, and the second electrode of the thirteenth transistor T13 is coupled to the third reference signal terminal VREF3.
  • the thirteenth transistor T13 can be turned on under the control of the effective level of the ninth control signal transmitted on the ninth control signal terminal CS9, and can be turned off under the control of the invalid level of the ninth control signal.
  • the thirteenth transistor T13 can be set as an N-type transistor, then the effective level of the ninth control signal is a high level, and the invalid level of the ninth control signal is a low level.
  • the thirteenth transistor T13 can be set as a P-type transistor, then the effective level of the ninth control signal is a low level, and the invalid level of the ninth control signal is a high level.
  • the following takes the pixel circuit shown in FIG. 9 as an example, and describes the working process of the pixel circuit provided by the embodiment of the present disclosure in combination with the signal timing diagram shown in FIG. 10 .
  • em represents the light-emitting signal of the light-emitting control signal terminal EM
  • cs1 represents the first control signal of the first control signal terminal CS1
  • cs2 represents the second control signal of the second control signal terminal CS2
  • cs4 represents the fourth control signal of the fourth control signal terminal CS4
  • cs5 represents the fifth control signal of the fifth control signal terminal CS5
  • cs6 represents the sixth control signal of the sixth control signal terminal CS6
  • cs7 represents the seventh control signal of the seventh control signal terminal CS7
  • cs8 represents the eighth control signal of the eighth control signal terminal CS8
  • cs9 represents the ninth control signal of the ninth control signal terminal CS9
  • da represents the data voltage signal of the data signal terminal DA
  • vinit2 represents the second initialization signal of the second initialization signal terminal VINIT2.
  • the first transistor T1 is turned off under the control of the high level of the first control signal cs1
  • the second transistor T2 is turned on under the control of the low level of the second control signal cs2
  • the third transistor T3 is turned on under the control of the low level of the second control signal cs2
  • the fourth transistor T4 is turned off under the control of the high level of the light emitting signal em
  • the fifth transistor T5 is turned off under the control of the high level of the fourth control signal cs4
  • the sixth transistor T6 is turned off under the control of the high level of the light emitting signal em
  • the seventh transistor T7 is turned off under the control of the high level of the light emitting signal em
  • the eighth transistor T8 is turned off under the control of the high level of the sixth control signal cs6
  • the ninth transistor T9 is turned on under the control of the low level of the seventh control signal cs7
  • the eleventh transistor T11 is turned off under the control of the high level of the eighth control
  • the turned-on ninth transistor T9 provides the third initialization signal of the third initialization signal terminal VINIT3 to the second electrode of the driving transistor T0, and the voltage Vd of the second electrode of the driving transistor T0 is Vinit3.
  • the turned-on second transistor T2 and the turned-on third transistor T3 provide the third initialization signal on the second electrode of the driving transistor T0 to the gate of the driving transistor T0, and the voltage Vg on the gate of the driving transistor T0 is Vinit3, where Vinit3 represents the voltage of the third initialization signal.
  • the first transistor T1 is turned on under the control of the low level of the first control signal cs1
  • the second transistor T2 is turned on under the control of the low level of the second control signal cs2
  • the third transistor T3 is turned on under the control of the low level of the second control signal cs2
  • the fourth transistor T4 is turned off under the control of the high level of the light emitting signal em
  • the fifth transistor T5 is turned off under the control of the high level of the fourth control signal cs4
  • the sixth transistor T6 is turned off under the control of the high level of the light emitting signal em
  • the seventh transistor T7 is turned off under the control of the high level of the light emitting signal em
  • the eighth transistor T8 is turned on under the control of the low level of the sixth control signal cs6
  • the ninth transistor T9 is turned off under the control of the high level of the seventh control signal cs7
  • the eleventh transistor T11 is turned on under the control of the low level of the eighth control
  • the turned-on first transistor T1 provides the first reference signal of the first reference signal terminal VREF1 to the first electrode of the driving transistor T0, and the voltage Vs on the first electrode of the driving transistor T0 is Vref1.
  • the turned-on second transistor T2 conducts the second electrode of the driving transistor T0 with the second node N2, and the turned-on third transistor T3 conducts the second node N2 with the gate of the driving transistor T0.
  • the three transistors T3 can make the driving transistor T0 form a diode connection mode, then the first reference signal input to the first electrode of the driving transistor T0 can pass through the driving transistor T0 formed in the diode connection mode, and input to the gate of the driving transistor T0, and compensate the threshold voltage Vth of the driving transistor T0, so that the gate Vg voltage of the driving transistor T0 is Vref1+Vth, then the voltage VN2 on the second node N2 and the voltage Vd of the second electrode of the driving transistor T0 are Vref1+Vth.
  • the turned-on eighth transistor T8 provides the second initialization signal of the second initialization signal terminal VINIT2 to the anode of the light-emitting device L, then the voltage VL on the anode of the light-emitting device L is Vinit2.
  • the turned-on twelfth transistor T12 provides the second reference signal of the second reference signal terminal VREF2 to the third node N3, and the turned-on eleventh transistor T11 provides the second reference signal on the third node N3 to the first node N1, then the voltage VN1 on the first node N1 is Vref2.
  • the second capacitor C2 stabilizes the voltage of the first node N1.
  • the first transistor T1 is turned off under the control of the high level of the first control signal cs1
  • the second transistor T2 is turned off under the control of the high level of the second control signal cs2
  • the third transistor T3 is turned off under the control of the high level of the second control signal cs2
  • the fourth transistor T4 is turned off under the control of the high level of the light emitting signal em
  • the fifth transistor T5 is turned on under the control of the low level of the fourth control signal cs4
  • the sixth transistor T6 is turned off under the control of the high level of the light emitting signal em
  • the seventh transistor T7 is turned off under the control of the high level of the light emitting signal em
  • the eighth transistor T8 is turned off under the control of the high level of the sixth control signal cs6
  • the ninth transistor T9 is turned off under the control of the high level of the seventh control signal cs7
  • the eleventh transistor T11 is turned off under the control of the high level of the eighth control
  • the turned-on fifth transistor T5 provides the data voltage signal of the data signal terminal DA to the first node N1, and the first capacitor C1 couples the data voltage signal of the first node N1 to the gate of the driving transistor T0, so the gate Vg voltage of the driving transistor T0 is Vref1+Vth+Vda-Vref2.
  • the second capacitor C2 stabilizes the voltage of the first node N1.
  • the first transistor T1 is turned off under the control of the high level of the first control signal cs1
  • the second transistor T2 is turned off under the control of the high level of the second control signal cs2
  • the third transistor T3 is turned off under the control of the high level of the second control signal cs2
  • the fourth transistor T4 is turned off under the control of the high level of the light emitting signal
  • the fourth transistor T4 is turned on under the control of the low level of the first control signal em
  • the fifth transistor T5 is turned off under the control of the high level of the fourth control signal cs4
  • the sixth transistor T6 is turned on under the control of the low level of the light emitting signal em
  • the seventh transistor T7 is turned on under the control of the low level of the light emitting signal em
  • the eighth transistor T8 is turned off under the control of the high level of the sixth control signal cs6,
  • the ninth transistor T9 is turned off under the control of the high level of the seventh control signal cs7
  • the turned-on fourth transistor T4 provides the first initialization signal of the first initialization signal terminal VINIT1 to the second node N2, and the voltage VN2 on the second node N2 is Vinit1.
  • the turned-on thirteenth transistor T13 provides the third reference signal of the third reference signal terminal VREF3 to the third node N3, and the voltage VN3 on the third node N3 is Vref3.
  • the turned-on sixth transistor T6 provides the first power supply voltage Vdd of the first power supply terminal VDD to the first electrode of the driving transistor T0, and the voltage of the first electrode Vs of the driving transistor T0 is Vdd.
  • the turned-on seventh transistor T7 turns on the second electrode of the driving transistor T0 and the light emitting device L, and drives the light emitting device L to emit light.
  • the driving transistor T0 works in the saturation region, and the driving current I generated by it can be expressed as: in, ⁇ represents the mobility of the driving transistor T0 , Cox represents the capacitance per unit area of the gate insulating layer of the driving transistor T0 , and W/L represents the channel width-to-length ratio of the driving transistor T0 .
  • the first control signal terminal CS1, the sixth control signal terminal CS6 and the eighth control signal terminal CS8 may be the same signal terminal, which can reduce the number of signal lines and the space occupied by wiring.
  • the light emitting control signal terminal EM and the ninth control signal terminal CS9 may be the same signal terminal, which can reduce the number of signal lines and the space occupied by wiring.
  • the disclosed embodiment provides some further structural schematic diagrams of pixel circuits, as shown in Figure 11, which are modified from the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the third reference signal terminal and the first initialization signal terminal VINIT1 can be the same signal terminal. This can reduce the number of signal lines and reduce the space occupied by wiring.
  • the signal timing diagram corresponding to the pixel circuit shown in Figure 11 may be shown in Figure 10. Moreover, the specific working process of the pixel circuit shown in Figure 11 combined with the signal timing diagram shown in Figure 10 may refer to the description of the above embodiment, which will not be repeated here.
  • the disclosed embodiment provides some further structural schematic diagrams of pixel circuits, as shown in Figure 12, which are modified from the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the following takes the pixel circuit shown in FIG. 12 as an example, and describes the working process of the pixel circuit provided by the embodiment of the present disclosure in combination with the signal timing diagram shown in FIG. 10 .
  • the first transistor T1 is turned off under the control of the high level of the first control signal cs1
  • the second transistor T2 is turned on under the control of the low level of the second control signal cs2
  • the third transistor T3 is turned on under the control of the low level of the second control signal cs2
  • the fourth transistor T4 is turned off under the control of the high level of the light emitting signal em
  • the fifth transistor T5 is turned off under the control of the high level of the fourth control signal cs4
  • the sixth transistor T6 is turned off under the control of the high level of the light emitting signal em
  • the seventh transistor T7 is turned off under the control of the high level of the light emitting signal em
  • the eighth transistor T8 is turned off under the control of the high level of the sixth control signal cs6
  • the ninth transistor T9 is turned on under the control of the low level of the seventh control signal cs7
  • the eleventh transistor T11 is turned off under the control of the high level of the eighth control
  • the turned-on ninth transistor T9 provides the third initialization signal of the third initialization signal terminal VINIT3 to the second electrode of the driving transistor T0, and the voltage Vd of the second electrode of the driving transistor T0 is Vinit3.
  • the turned-on second transistor T2 and the turned-on third transistor T3 provide the third initialization signal on the second electrode of the driving transistor T0 to the gate of the driving transistor T0 , and the voltage Vg on the gate of the driving transistor T0 is Vinit3 .
  • the first transistor T1 is turned on under the control of the low level of the first control signal cs1
  • the second transistor T2 is turned on under the control of the low level of the second control signal cs2
  • the third transistor T3 is turned on under the control of the low level of the second control signal cs2
  • the fourth transistor T4 is turned off under the control of the high level of the light emitting signal em
  • the fifth transistor T5 is turned on under the control of the high level of the fourth control signal cs4.
  • the sixth transistor T6 is turned off under the control of the high level of the light emitting signal em
  • the seventh transistor T7 is turned off under the control of the high level of the light emitting signal em
  • the eighth transistor T8 is turned on under the control of the low level of the sixth control signal cs6
  • the ninth transistor T9 is turned off under the control of the high level of the seventh control signal cs7
  • the eleventh transistor T11 is turned on under the control of the low level of the eighth control signal cs8
  • the twelfth transistor T12 is turned on under the control of the low level of the eighth control signal cs8.
  • the turned-on first transistor T1 provides the first reference signal of the first reference signal terminal VREF1 to the first electrode of the driving transistor T0, and the voltage Vs on the first electrode of the driving transistor T0 is Vref1.
  • the turned-on second transistor T2 conducts the second electrode of the driving transistor T0 with the second node N2, and the turned-on third transistor T3 conducts the second node N2 with the gate of the driving transistor T0.
  • the first reference signal input to the first electrode of the driving transistor T0 can pass through the driving transistor T0 formed in the diode connection mode, and input to the gate of the driving transistor T0, and compensate the threshold voltage Vth of the driving transistor T0, so that the gate Vg voltage of the driving transistor T0 is Vref1+Vth, then the voltage VN2 on the second node N2 and the voltage Vd of the second electrode of the driving transistor T0 are Vref1+Vth.
  • the turned-on eighth transistor T8 provides the second initialization signal of the second initialization signal terminal VINIT2 to the anode of the light-emitting device L, and the voltage VL on the anode of the light-emitting device L is Vinit2.
  • the turned-on twelfth transistor T12 provides the second reference signal of the second reference signal terminal VREF2 to the third node N3, and the turned-on eleventh transistor T11 provides the second reference signal on the third node N3 to the first node N1, so the voltage VN1 on the first node N1 is Vref2.
  • the second capacitor C2 stabilizes the voltage of the first node N1.
  • the first transistor T1 is turned off under the control of the high level of the first control signal cs1
  • the second transistor T2 is turned off under the control of the high level of the second control signal cs2
  • the third transistor T3 is turned off under the control of the high level of the second control signal cs2
  • the fourth transistor T4 is turned off under the control of the high level of the light emitting signal em
  • the fifth transistor T5 is turned on under the control of the low level of the fourth control signal cs4
  • the sixth transistor T6 is turned off under the control of the high level of the light emitting signal em
  • the seventh transistor T7 is turned off under the control of the high level of the light emitting signal em
  • the eighth transistor T8 is turned off under the control of the high level of the sixth control signal cs6,
  • the ninth transistor T9 is turned off under the control of the high level of the seventh control signal cs7
  • the eleventh transistor T11 is turned on under the control of the high level of the eighth control
  • the turned-on fourth transistor T4 provides the first initialization signal of the first initialization signal terminal VINIT1 to the second node N2, and the voltage VN2 on the second node N2 is Vinit1.
  • the turned-on sixth transistor T6 provides the first power supply voltage Vdd of the first power supply terminal VDD to the first electrode of the driving transistor T0, and the voltage of the first electrode Vs of the driving transistor T0 is Vdd.
  • the turned-on seventh transistor T7 turns on the second electrode of the driving transistor T0 and the light emitting device L, and drives the light emitting device L to emit light.
  • the driving transistor T0 works in the saturation region, and the driving current I generated by it can be expressed as: in, ⁇ represents the mobility of the driving transistor T0 , Cox represents the capacitance per unit area of the gate insulating layer of the driving transistor T0 , and W/L represents the channel width-to-length ratio of the driving transistor T0 .
  • the embodiment of the present disclosure also provides a display device, including the above pixel circuit provided by the embodiment of the present disclosure.
  • the principle of solving the problem by the display device is similar to that of the above pixel circuit, so the implementation of the display device can refer to the implementation of the above pixel circuit, and the repetition is not repeated here. I will elaborate on this.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.

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Abstract

提供了一种像素电路、显示装置及驱动方法。像素电路包括：发光器件；驱动晶体管（T0）根据数据电压信号产生驱动发光器件发光的驱动电流；第一补偿电路（10）响应于第一控制信号端（CS1）的信号，将第一参考信号端（VREF1）的第一参考信号提供给驱动晶体管（T0）的第一极；第二补偿电路（20）响应于第二控制信号端（CS2）和第三控制信号端（CS3）的信号，将驱动晶体管（T0）的阈值电压和输入驱动晶体管（T0）的第一极的第一参考信号，提供给驱动晶体管（T0）的栅极；数据写入电路（30）响应于第四控制信号端（CS4）的信号，将数据信号端（DA）的数据电压信号提供给第一节点（N1）；耦合控制电路（40）将第一节点（N1）的数据电压信号耦合至驱动晶体管（T0）的栅极；发光控制电路（50）响应于发光控制信号端（EM）的信号，驱动发光器件（L）发光。

Description

像素电路、显示装置及驱动方法 技术领域
本公开涉及显示技术领域，特别涉及像素电路、显示装置及驱动方法。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示器是当今平板显示器研究领域的热点之一，与液晶显示器(Liquid Crystal Display，LCD)相比，OLED显示器具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点。其中，用于控制发光器件发光的像素电路是OLED显示器的核心技术内容，具有重要的研究意义。然而，现有的OLED显示器的像素电路包括的晶体管的个数较多，导致工艺难度较大，生产成本增加，以及导致像素电路占用较大面积，从而不利于OLED显示器实现较高分辨率。
发明内容
本公开实施例提供的像素电路，包括：
发光器件；
驱动晶体管，与所述发光器件耦接，被配置为根据数据电压信号产生驱动所述发光器件发光的驱动电流；
第一补偿电路，与所述驱动晶体管耦接，被配置为响应于第一控制信号端的信号，将第一参考信号端的第一参考信号提供给所述驱动晶体管的第一极；
第二补偿电路，与所述驱动晶体管耦接，被配置为响应于第二控制信号端和第三控制信号端的信号，将所述驱动晶体管的阈值电压和输入所述驱动晶体管的第一极的第一参考信号，提供给所述驱动晶体管的栅极；
数据写入电路，与所述第一节点耦接，被配置为响应于第四控制信号端的信号，将数据信号端的所述数据电压信号提供给第一节点；
耦合控制电路，与所述第一节点和所述驱动晶体管耦接，被配置为将所述第一节点的数据电压信号耦合至所述驱动晶体管的栅极；
发光控制电路，与所述发光器件和所述驱动晶体管耦接，被配置为响应于发光控制信号端的信号，将所述驱动晶体管的第一极与第一电源端导通，以及将所述驱动晶体管的第二极与所述发光器件导通，驱动所述发光器件发光。
在一些可能的实施方式中，所述第一补偿电路包括：第一晶体管；
所述第一晶体管的栅极与所述第一控制信号端耦接，所述第一晶体管的第一极与所述驱动晶体管的第一极耦接，所述第一晶体管的第二极与所述第一参考信号端耦接。
在一些可能的实施方式中，所述第二补偿电路包括：第二晶体管和第三晶体管；
所述第二晶体管的栅极与所述第二控制信号端耦接，所述第二晶体管的第一极与所述第二节点耦接，所述第二晶体管的第二极与所述驱动晶体管的第二极耦接；
所述第三晶体管的栅极与所述第三控制信号端耦接，所述第三晶体管的第一极与所述驱动晶体管的栅极耦接，所述第三晶体管的第二极与所述第二节点耦接。
在一些可能的实施方式中，所述第二补偿电路还包括：第四晶体管；
所述第四晶体管的栅极与第五控制信号端耦接，所述第四晶体管的第一极与所述驱动晶体管的栅极或所述第二节点耦接，所述第四晶体管的第二极与第一初始化信号端耦接。
在一些可能的实施方式中，所述第五控制信号端与所述发光控制信号端可以为同一信号端。
在一些可能的实施方式中，所述数据写入电路包括：第五晶体管；
所述第五晶体管的栅极与所述第四控制信号端耦接，所述第五晶体管的第一极与所述数据信号端耦接，所述第五晶体管的第二极与所述第一节点耦 接。
在一些可能的实施方式中，所述耦合控制电路包括：第一电容；
所述第一电容的第一电极与所述第一节点耦接，所述第一电容的第二电极与所述驱动晶体管的栅极耦接。
在一些可能的实施方式中，所述发光控制电路包括：第六晶体管和第七晶体管；
所述第六晶体管的栅极与所述发光控制信号端耦接，所述第六晶体管的第一极与所述第一电源端耦接，所述第六晶体管的第二极与所述驱动晶体管的第一极耦接；
所述第七晶体管的栅极与所述发光控制信号端耦接，所述第七晶体管的第一极与所述驱动晶体管的第二极耦接，所述第七晶体管的第二极与所述发光器件耦接。
在一些可能的实施方式中，还包括：第一复位电路，与所述发光器件耦接，被配置为响应于第六控制信号端的信号，将第二初始化信号端的信号提供给所述发光器件。
在一些可能的实施方式中，所述第一复位电路包括：第八晶体管；
所述第八晶体管的栅极与所述第六控制信号端耦接，所述第八晶体管的第一极与所述发光器件耦接，所述第八晶体管的第二极与所述第二初始化信号端耦接。
在一些可能的实施方式中，还包括：稳压电路，与所述第一节点耦接，被配置为稳定所述第一节点的电压。
在一些可能的实施方式中，所述稳压电路包括：第二电容；
所述第二电容的第一电极与所述第一电源端耦接，所述第二电容的第二电极与所述第一节点耦接。
在一些可能的实施方式中，还包括：第二复位电路，与所述驱动晶体管的第二极耦接，被配置为响应于第七控制信号端的信号，将第三初始化信号端的信号提供给所述驱动晶体管的第二极。
在一些可能的实施方式中，所述第二复位电路包括：第九晶体管；
所述第九晶体管的栅极与所述第七控制信号端耦接，所述第九晶体管的第一极与所述驱动晶体管的第二极耦接，所述第九晶体管的第二极与所述第三初始化信号端耦接。
在一些可能的实施方式中，还包括：第三复位电路，与所述第一节点耦接，被配置为响应于第八控制信号端的信号，将第二参考信号端的信号提供给所述第一节点。
在一些可能的实施方式中，所述第三复位电路包括：第十晶体管；
所述第十晶体管的栅极与所述第八控制信号端耦接，所述第十晶体管的第一极与所述第一节点耦接，所述第十晶体管的第二极与所述第二参考信号端耦接。
在一些可能的实施方式中，所述第三复位电路包括：第十一晶体管和第十二晶体管；
所述第十一晶体管的栅极与所述第八控制信号端耦接，所述第十一晶体管的第一极与所述第一节点耦接，所述第十一晶体管的第二极与第三节点耦接；
所述第十二晶体管的栅极与所述第八控制信号端耦接，所述第十二晶体管的第一极与所述第三节点耦接，所述第十一晶体管的第二极与所述第二参考信号端耦接。
在一些可能的实施方式中，所述第三复位电路还包括：第十三晶体管；
所述第十三晶体管的栅极与第九控制信号端耦接，所述第十三晶体管的第一极与所述第三节点耦接，所述第十三晶体管的第二极与第三参考信号端耦接。
本公开实施例提供的显示装置，包括上述的像素电路。
本公开实施例提供的上述像素电路的驱动方法，包括：
复位阶段，第一补偿电路响应于第一控制信号端的信号，将第一参考信号端的第一参考信号提供给所述驱动晶体管的第一极；
阈值补偿阶段，第一补偿电路响应于第一控制信号端的信号，将第一参考信号端的第一参考信号提供给所述驱动晶体管的第一极；第二补偿电路响应于第二控制信号端和第三控制信号端的信号，将所述驱动晶体管的阈值电压和输入所述驱动晶体管的第一极的第一参考信号，提供给所述驱动晶体管的栅极；
数据写入阶段，数据写入电路响应于第四控制信号端的信号，将数据信号端的所述数据电压信号提供给第一节点；耦合控制电路将所述第一节点的数据电压信号耦合至所述驱动晶体管的栅极；
发光阶段，发光控制电路响应于发光控制信号端的信号，将所述驱动晶体管的第一极与第一电源端导通，以及将所述驱动晶体管的第二极与所述发光器件导通，驱动所述发光器件发光。
附图说明
图1为本公开实施例提供的像素电路的一些结构示意图；
图2为本公开实施例提供的像素电路的另一些结构示意图；
图3为本公开实施例提供的像素电路的驱动方法的流程图；
图4为本公开实施例提供的一些信号时序图；
图5为本公开实施例提供的像素电路的又一些结构示意图；
图6为本公开实施例提供的另一些信号时序图；
图7为本公开实施例提供的像素电路的又一些结构示意图；
图8为本公开实施例提供的又一些信号时序图；
图9为本公开实施例提供的像素电路的又一些结构示意图；
图10为本公开实施例提供的又一些信号时序图；
图11为本公开实施例提供的像素电路的又一些结构示意图；
图12为本公开实施例提供的像素电路的又一些结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本公开实施例提供的显示装置，可以包括显示面板。显示面板可以包括衬底基板。其中，衬底基板可以包括显示区域和非显示区域(即衬底基板中除显示区域包围区域之外的区域)。其中，显示区域可以包括多个阵列排布的像素单元。示例性地，每个像素单元包括同一种颜色的子像素或多种不同颜色的子像素。例如，像素单元可以包括红色子像素，绿色子像素以及蓝色子像素，这样可以通过红绿蓝进行混色，以实现彩色显示。或者，像素单元也可以包括红色子像素，绿色子像素、蓝色子像素以及白色子像素，这样可以通过红绿蓝白进行混色，以实现彩色显示。当然，在实际应用中，像素单元中的子像素的发光颜色可以根据实际应用环境来设计确定，在此不作限定。
在本公开实施例中，各子像素中可以包括像素电路和与像素电路耦接的发光器件，像素电路可以包括驱动晶体管，以控制发光器件发光，从而使显 示面板实现画面显示的功能。由于工艺、老化等原因会造成驱动晶体管的阈值电压Vth漂移，对产生的驱动电流造成影响，从而导致显示效果不佳。因此会对驱动晶体管的阈值电压Vth进行补偿，但是现有技术采用的是在数据充电的同时对阈值电压Vth进行补偿，就会导致补偿与充电速度过慢的现象，从而无法适用于高频的电路。
基于此，本公开实施例提供了像素电路，如图1所示，包括：
发光器件L；
驱动晶体管T0，与发光器件L耦接，被配置为根据数据电压信号产生驱动发光器件L发光的驱动电流；
第一补偿电路10，与驱动晶体管T0耦接，被配置为响应于第一控制信号端CS1的信号，将第一参考信号端VREF1的第一参考信号提供给驱动晶体管T0的第一极；
第二补偿电路20，与驱动晶体管T0耦接，被配置为响应于第二控制信号端CS2和第三控制信号端CS3的信号，将驱动晶体管T0的阈值电压Vth和输入驱动晶体管T0的第一极的第一参考信号，提供给驱动晶体管T0的栅极；
数据写入电路30，与第一节点N1耦接，被配置为响应于第四控制信号端CS4的信号，将数据信号端DA的数据电压信号提供给第一节点N1；
耦合控制电路40，与第一节点N1和驱动晶体管T0耦接，被配置为将第一节点N1的数据电压信号耦合至驱动晶体管T0的栅极；
发光控制电路50，与发光器件L和驱动晶体管T0耦接，被配置为响应于发光控制信号端EM的信号，将驱动晶体管T0的第一极与第一电源端VDD导通，以及将驱动晶体管T0的第二极与发光器件L导通，驱动发光器件L发光。
本公开实施例提供的像素电路，通过发光器件、驱动晶体管、第一补偿电路、第二补偿电路、数据写入电路、耦合控制电路以及发光控制电路的相互配合实现阈值电压Vth补偿与数据充电分时进行，从而使阈值电压Vth补偿不再受限制，有更多的时间进行补偿，提高了补偿效果，提高了低灰阶下 的显示效果。
并且，通过采用第一补偿电路将第一参考信号端的第一参考信号提供给驱动晶体管的第一极，第二补偿电路将驱动晶体管的阈值电压和输入驱动晶体管的第一极的第一参考信号，提供给驱动晶体管的栅极，对驱动晶体管进行阈值电压Vth补偿，可以进一步减少发光控制电路所需要的发光控制信号端，即采用简单的结构以及较少的信号线来实现驱动发光器件发光，从而可以简化制备工艺、降低生产成本以及减小占用面积，提高了像素密度，有利于实现较高分辨率，提高显示效果。
示例性的，如图1所示，驱动晶体管T0可以设置为P型晶体管；其中，驱动晶体管T0的第一极可以为其源极，驱动晶体管T0的第二极可以为其漏极，并且该驱动晶体管T0处于饱和状态时，电流由驱动晶体管T0的源极流向其漏极。当然，驱动晶体管T0也可以设置为N型晶体管，在此不作限定。
示例性的，如图1所示，发光器件L的第二极与第二电源端VSS耦接；示例性地，发光器件L可以为电致发光二极管。例如，发光器件L可以包括：有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)、微型发光二极管(Micro Light Emitting Diode，Micro LED)、迷你发光二极管(Mini Light Emitting Diode，Mini LED)等中的至少一种。示例性地，发光器件L可以包括层叠设置的阳极、发光层、阴极。进一步地，发光层还可以包括空穴注入层、空穴传输层、电子传输层、电子注入层等膜层。当然，在实际应用中，可以根据实际应用的需求确定发光器件L的具体结构，在此不作限定。
在本公开实施例中，如图2所示，第一补偿电路10包括：第一晶体管T1；其中，第一晶体管T1的栅极与第一控制信号端CS1耦接，第一晶体管T1的第一极与驱动晶体管T0的第一极耦接，第一晶体管T1的第二极与第一参考信号端VREF1耦接。
示例性地，第一晶体管T1可以在第一控制信号端CS1上传输的第一控制信号的有效电平的控制下导通，可以在第一控制信号的无效电平的控制下截 止。例如，第一晶体管T1可以设置为N型晶体管，则第一控制信号的有效电平为高电平，第一控制信号的无效电平为低电平。或者，第一晶体管T1可以设置为P型晶体管，则第一控制信号的有效电平为低电平，第一控制信号的无效电平为高电平。
在本公开实施例中，如图2所示，第二补偿电路20包括：第二晶体管T2和第三晶体管T3；其中，第二晶体管T2的栅极与第二控制信号端CS2耦接，第二晶体管T2的第一极与第二节点N2耦接，第二晶体管T2的第二极与驱动晶体管T0的第二极耦接；第三晶体管T3的栅极与第三控制信号端CS3耦接，第三晶体管T3的第一极与驱动晶体管T0的栅极耦接，第三晶体管T3的第二极与第二节点N2耦接。
示例性地，第二晶体管T2可以在第二控制信号端CS2上传输的第二控制信号的有效电平的控制下导通，可以在第二控制信号的无效电平的控制下截止。例如，第二晶体管T2可以设置为N型晶体管，则第二控制信号的有效电平为高电平，第二控制信号的无效电平为低电平。或者，第二晶体管T2可以设置为P型晶体管，则第二控制信号的有效电平为低电平，第二控制信号的无效电平为高电平。
示例性地，第三晶体管T3可以在第三控制信号端CS3上传输的第三控制信号的有效电平的控制下导通，可以在第三控制信号的无效电平的控制下截止。例如，第三晶体管T3可以设置为N型晶体管，则第三控制信号的有效电平为高电平，第三控制信号的无效电平为低电平。或者，第三晶体管T3可以设置为P型晶体管，则第三控制信号的有效电平为低电平，第三控制信号的无效电平为高电平。
在本公开实施例中，如图2所示，第二补偿电路20还包括：第四晶体管T4；其中，第四晶体管T4的栅极与第五控制信号端CS5耦接，第四晶体管T4的第一极与第二节点N2耦接，第四晶体管T4的第二极与第一初始化信号端VINIT1耦接。
示例性地，第四晶体管T4可以在第五控制信号端CS5上传输的第五控制 信号的有效电平的控制下导通，可以在第五控制信号的无效电平的控制下截止。例如，第四晶体管T4可以设置为N型晶体管，则第五控制信号的有效电平为高电平，第五控制信号的无效电平为低电平。或者，第四晶体管T4可以设置为P型晶体管，则第五控制信号的有效电平为低电平，第五控制信号的无效电平为高电平。
在本公开实施例中，如图2所示，数据写入电路30包括：第五晶体管T5；其中，第五晶体管T5的栅极与第四控制信号端CS4耦接，第五晶体管T5的第一极与数据信号端DA耦接，第五晶体管T5的第二极与第一节点N1耦接。
示例性地，第五晶体管T5可以在第四控制信号端CS4上传输的第四控制信号的有效电平的控制下导通，可以在第四控制信号的无效电平的控制下截止。例如，第五晶体管T5可以设置为N型晶体管，则第四控制信号的有效电平为高电平，第四控制信号的无效电平为低电平。或者，第五晶体管T5可以设置为P型晶体管，则第四控制信号的有效电平为低电平，第四控制信号的无效电平为高电平。
在本公开实施例中，如图2所示，耦合控制电路40包括：第一电容C1；其中，第一电容C1的第一电极与第一节点N1耦接，第一电容C1的第二电极与驱动晶体管T0的栅极耦接。
在本公开实施例中，如图2所示，发光控制电路50包括：第六晶体管T6和第七晶体管T7；其中，第六晶体管T6的栅极与发光控制信号端EM耦接，第六晶体管T6的第一极与第一电源端VDD耦接，第六晶体管T6的第二极与驱动晶体管T0的第一极耦接；第七晶体管T7的栅极与发光控制信号端EM耦接，第七晶体管T7的第一极与驱动晶体管T0的第二极耦接，第七晶体管T7的第二极与发光器件L耦接。
示例性地，第六晶体管T6可以在第发光控制信号端EM上传输的发光控制信号的有效电平的控制下导通，可以在发光控制信号的无效电平的控制下截止。例如，第六晶体管T6可以设置为N型晶体管，则发光控制信号的有效电平为高电平，发光控制信号的无效电平为低电平。或者，第六晶体管T6可 以设置为P型晶体管，则发光控制信号的有效电平为低电平，发光控制信号的无效电平为高电平。
示例性地，第七晶体管T7可以在第发光控制信号端EM上传输的发光控制信号的有效电平的控制下导通，可以在发光控制信号的无效电平的控制下截止。例如，第七晶体管T7可以设置为N型晶体管，则发光控制信号的有效电平为高电平，发光控制信号的无效电平为低电平。或者，第七晶体管T7可以设置为P型晶体管，则发光控制信号的有效电平为低电平，发光控制信号的无效电平为高电平。
在本公开实施例中，如图2所示，还包括：第一复位电路60，与发光器件L耦接，被配置为响应于第六控制信号端CS6的信号，将第二初始化信号端VINIT2的信号提供给发光器件L。
在本公开实施例中，如图2所示，第一复位电路60包括：第八晶体管T8；其中，第八晶体管T8的栅极与第六控制信号端CS6耦接，第八晶体管T8的第一极与发光器件L耦接，第八晶体管T8的第二极与第二初始化信号端VINIT2耦接。
示例性地，第八晶体管T8可以在第六控制信号端CS6上传输的第六控制信号的有效电平的控制下导通，可以在第六控制信号的无效电平的控制下截止。例如，第八晶体管T8可以设置为N型晶体管，则第六控制信号的有效电平为高电平，第六控制信号的无效电平为低电平。或者，第八晶体管T8可以设置为P型晶体管，则第六控制信号的有效电平为低电平，第六控制信号的无效电平为高电平。
在本公开实施例中，如图2所示，还包括：稳压电路70，与第一节点N1耦接，被配置为稳定第一节点N1的电压。
在本公开实施例中，如图2所示，稳压电路70包括：第二电容C2；其中，第二电容C2的第一电极与第一电源端VDD耦接，第二电容C2的第二电极与第一节点N1耦接。
在本公开实施例中，如图2所示，还包括：第三复位电路90，与第一节 点N1耦接，被配置为响应于第八控制信号端CS8的信号，将第二参考信号端VREF2的信号提供给第一节点N1。
在本公开实施例中，如图2所示，第三复位电路90包括：第十一晶体管T11和第十二晶体管T12；其中，第十一晶体管T11的栅极与第八控制信号端CS8耦接，第十一晶体管T11的第一极与第一节点N1耦接，第十一晶体管T11的第二极与第三节点N3耦接；第十二晶体管T12的栅极与第八控制信号端CS8耦接，第十二晶体管T12的第一极与第三节点N3耦接，第十一晶体管T11的第二极与第二参考信号端VREF2耦接。
示例性地，第十一晶体管T11可以在第八控制信号端CS8上传输的第八控制信号的有效电平的控制下导通，可以在第八控制信号的无效电平的控制下截止。例如，第十一晶体管T11可以设置为N型晶体管，则第八控制信号的有效电平为高电平，第八控制信号的无效电平为低电平。或者，第十一晶体管T11可以设置为P型晶体管，则第八控制信号的有效电平为低电平，第八控制信号的无效电平为高电平。
示例性地，第十二晶体管T12可以在第八控制信号端CS8上传输的第八控制信号的有效电平的控制下导通，可以在第八控制信号的无效电平的控制下截止。例如，第十二晶体管T12可以设置为N型晶体管，则第八控制信号的有效电平为高电平，第八控制信号的无效电平为低电平。或者，第十二晶体管T12可以设置为P型晶体管，则第八控制信号的有效电平为低电平，第八控制信号的无效电平为高电平。
示例性地，上述的晶体管的第一极可以为其源极，第二极可以为其漏极。或者，第一极为其漏极，第二极为其源极。在此不作限定。
一般采用低温多晶硅(Low Temperature Poly-Silicon，LTPS)材料作为有源层的晶体管的迁移率高且可以做得更薄更小、功耗更低等，在具体实施时，上述至少一个晶体管的有源层的材料可以设置为低温多晶硅材料。这样可以将上述晶体管设置为LTPS型晶体管，以使像素电路实现迁移率高且可以做得更薄更小、功耗更低等。
一般采用金属氧化物半导体材料作为有源层的晶体管的漏电流较小，因此为了降低漏电流，在本公开一些实施例中，也可以使上述至少一个晶体管的有源层的材料包括金属氧化物半导体材料，例如可以为IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)，当然，也可以为其他金属氧化物半导体材料，在此不作限定。这样可以将上述晶体管设置为氧化物型晶体管(Oxide Thin Film Transistor)，以使像素电路的漏电流减小。
示例性地，可以将所有晶体管均设置为LTPS型晶体管。或者，可以将所有晶体管均设置为氧化物型晶体管。或者，也可以使部分晶体管设置为氧化物型晶体管，其余晶体管设置为LTPS型晶体管。通过将LTPS型晶体管与氧化物型晶体管，这两种制备晶体管的工艺进行结合制备低温多晶硅氧化物的LTPO像素电路，可以使驱动晶体管T0的栅极的漏电流较小，以及使功耗较低。从而将该像素电路应用于显示面板中，在显示面板降低刷新频率进行显示时，可以保证显示的均一性。
示例性的，第一电源端VDD可以被配置为加载恒定的第一电源电压Vdd，并且第一电源电压Vdd一般为正值，例如，第一电源电压Vdd包括4.6等。以及，第二电源端VSS可以加载恒定的第二电源电压Vss，并且第二电源电压Vss一般可以为接地电压或为负值，例如，第二电源电压Vss包括-5等。在实际应用中，第一电源电压Vdd和第二电源电压Vss的具体数值可以根据实际应用环境来设计确定，在此不作限定。
在本公开实施例中，如图3所示，本公开实施例中提供驱动像素电路的驱动方法，可以包括如下步骤：
S100、复位阶段，第一补偿电路响应于第一控制信号端的信号，将第一参考信号端的第一参考信号提供给驱动晶体管的第一极；
S200、阈值补偿阶段，第一补偿电路响应于第一控制信号端的信号，将第一参考信号端的第一参考信号提供给驱动晶体管的第一极；第二补偿电路响应于第二控制信号端和第三控制信号端的信号，将驱动晶体管的阈值电压和输入驱动晶体管的第一极的第一参考信号，提供给驱动晶体管的栅极；
S300、数据写入阶段，数据写入电路响应于第四控制信号端的信号，将数据信号端的数据电压信号提供给第一节点；耦合控制电路将第一节点的数据电压信号耦合至驱动晶体管的栅极；
S400、发光阶段，发光控制电路响应于发光控制信号端的信号，将驱动晶体管的第一极与第一电源端导通，以及将驱动晶体管的第二极与发光器件导通，驱动发光器件发光。
下面以图2所示的像素电路为例，结合图4所示的信号时序图，对本公开实施例提供的像素电路的工作过程作以描述。
其中，如图4所示，em代表发光控制信号端EM的发光信号，cs1代表第一控制信号端CS1的第一控制信号，cs2代表第二控制信号端CS2的第二控制信号，cs3代表第三控制信号端CS3的第三控制信号，cs4代表第四控制信号端CS4的第四控制信号，cs5代表第五控制信号端CS5的第五控制信号，cs6代表第六控制信号端CS6的第六控制信号，cs8代表第八控制信号端CS8的第八控制信号，da代表数据信号端DA的数据电压信号。
在复位阶段F1，第一晶体管T1在第一控制信号cs1的低电平的控制下导通，第二晶体管T2在第二控制信号cs2的高电平的控制下截止，第三晶体管T3在第三控制信号cs3的低电平的控制下导通，第四晶体管T4在第五控制信号cs5的低电平的控制下导通，第五晶体管T5在第四控制信号cs4的高电平的控制下截止，第六晶体管T6在发光信号em的高电平的控制下截止，第七晶体管T7在发光信号em的高电平的控制下截止，第八晶体管T8在第六控制信号cs6的低电平的控制下导通，第十一晶体管T11在第八控制信号cs8的高电平的控制下截止，第十二晶体管T12在第八控制信号cs8的高电平的控制下截止。导通的第一晶体管T1将第一参考信号端VREF1的第一参考信号提供给驱动晶体管T0的第一极，则驱动晶体管T0的第一极上的电压Vs为Vref1。导通的第四晶体管T4将第一初始化信号端VINIT1的第一初始化信号提供给第二节点N2，则第二节点N2上的电压VN2为Vinit1。导通的第三晶体管T3将第二节点N2上的第一初始化信号提供给驱动晶体管T0的栅极， 则驱动晶体管T0的栅极上的电压Vg为Vinit1。导通的第八晶体管T8将第二初始化信号端VINIT2的第二初始化信号提供给发光器件L的阳极，则发光器件L的阳极上的电压VL为Vinit2。其中，Vinit1代表第一初始化信号的电压，Vinit2代表第二初始化信号的电压，Vref1代表第一参考信号的电压。
在阈值补偿阶段F2，第一晶体管T1在第一控制信号cs1的低电平的控制下导通，第二晶体管T2在第二控制信号cs2的低电平的控制下导通，第三晶体管T3在第三控制信号cs3的低电平的控制下导通，第四晶体管T4在第五控制信号cs5的高电平的控制下截止，第五晶体管T5在第四控制信号cs4的高电平的控制下截止，第六晶体管T6在发光信号em的高电平的控制下截止，第七晶体管T7在发光信号em的高电平的控制下截止，第八晶体管T8在第六控制信号cs6的低电平的控制下导通，第十一晶体管T11在第八控制信号cs8的低电平的控制下导通，第十二晶体管T12在第八控制信号cs8的低电平的控制下导通。导通的第一晶体管T1将第一参考信号端VREF1的第一参考信号提供给驱动晶体管T0的第一极，则驱动晶体管T0的第一极上的电压Vs为Vref1。导通的第二晶体管T2将驱动晶体管T0的第二极与第二节点N2导通，导通的第三晶体管T3将第二节点N2与驱动晶体管T0的栅极导通，由于导通的第二晶体管T2和第三晶体管T3可以使驱动晶体管T0形成二极管连接方式，则输入驱动晶体管T0的第一极的第一参考信号可以经过形成二极管连接方式的驱动晶体管T0，输入驱动晶体管T0的栅极，并对驱动晶体管T0的阈值电压Vth进行补偿，以使驱动晶体管T0的栅极Vg电压为Vref1+Vth，则第二节点N2上的电压VN2和驱动晶体管T0的第二极Vd电压为Vref1+Vth。导通的第八晶体管T8将第二初始化信号端VINIT2的第二初始化信号提供给发光器件L的阳极，则发光器件L的阳极上的电压VL为Vinit2。导通的第十二晶体管T12将第二参考信号端VREF2的第二参考信号提供给第三节点N3，导通的第十一晶体管T11将第三节点N3上的第二参考信号提供给第一节点N1，则第一节点N1上的电压VN1为Vref2。第二电容C2稳定第一节点N1的电压。其中，Vref2代表第二参考信号的电压，Vth代表驱动晶体管T0的阈 值电压。
在数据写入阶段F3，第一晶体管T1在第一控制信号cs1的高电平的控制下截止，第二晶体管T2在第二控制信号cs2的高电平的控制下截止，第三晶体管T3在第三控制信号cs3的高电平的控制下截止，第四晶体管T4在第五控制信号cs5的高电平的控制下截止，第五晶体管T5在第四控制信号cs4的低电平的控制下导通，第六晶体管T6在发光信号em的高电平的控制下截止，第七晶体管T7在发光信号em的高电平的控制下截止，第八晶体管T8在第六控制信号cs6的高电平的控制下截止，第十一晶体管T11在第八控制信号cs8的高电平的控制下截止，第十二晶体管T12在第八控制信号cs8的高电平的控制下截止。导通的第五晶体管T5将数据信号端DA的数据电压信号提供给第一节点N1，第一电容C1将第一节点N1的数据电压信号耦合至驱动晶体管T0的栅极，则驱动晶体管T0的栅极Vg电压为Vref1+Vth+Vda-Vref2。第二电容C2稳定第一节点N1的电压。其中，Vda代表数据电压信号的电压。
在发光阶段F4，第一晶体管T1在第一控制信号cs1的高电平的控制下截止，第二晶体管T2在第二控制信号cs2的高电平的控制下截止，第三晶体管T3在第三控制信号cs3的高电平的控制下截止，第四晶体管T4在第五控制信号cs5的低电平的控制下导通，第五晶体管T5在第四控制信号cs4的高电平的控制下截止，第六晶体管T6在发光信号em的低电平的控制下导通，第七晶体管T7在发光信号em的低电平的控制下导通，第八晶体管T8在第六控制信号cs6的高电平的控制下截止，第十一晶体管T11在第八控制信号cs8的高电平的控制下截止，第十二晶体管T12在第八控制信号cs8的高电平的控制下截止。导通的第四晶体管T4将第一初始化信号端VINIT1的第一初始化信号提供给第二节点N2，则第二节点N2上的电压VN2为Vinit1。导通的第六晶体管T6将第一电源端VDD的第一电源电压Vdd提供给驱动晶体管T0的第一极，则驱动晶体管T0的第一极Vs的电压为Vdd，导通的第七晶体管T7将驱动晶体管T0的第二极与发光器件L导通，驱动发光器件L发光。则， 驱动晶体管T0工作于饱和区，其产生的驱动电流I可表示为： 其中，μ代表驱动晶体管T0的迁移率，Cox代表驱动晶体管T0的栅绝缘层单位面积电容，W/L代表驱动晶体管T0的沟道宽长比。
示例性的，第一控制信号端CS1、第三控制信号端CS3以及第六控制信号端CS6可以为同一信号端。这样可以降低信号线的数量，降低布线占用的空间。
示例性的，第二控制信号端CS2和第八控制信号端CS8可以为同一信号端。这样可以降低信号线的数量，降低布线占用的空间。
本公开实施例提供了像素电路的另一些结构示意图，如图5所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，如图5所示，第二补偿电路20还包括：第四晶体管T4；其中，第四晶体管T4的栅极与第五控制信号端CS5耦接，第四晶体管T4的第一极与驱动晶体管T0的栅极耦接，第四晶体管T4的第二极与第一初始化信号端VINIT1耦接。
示例性的，如图5所示，第二控制信号端CS2和第三控制信号端CS3可以为同一信号端。第三晶体管T3的栅极与第二控制信号端CS2耦接。这样可以降低信号线的数量，降低布线占用的空间。
在本公开实施例中，如图5所示，第三复位电路90包括：第十晶体管T10；其中，第十晶体管T10的栅极与第八控制信号端CS8耦接，第十晶体管T10的第一极与第一节点N1耦接，第十晶体管T10的第二极与第二参考信号端VREF2耦接。
示例性地，第十晶体管T10可以在第八控制信号端CS8上传输的第八控制信号的有效电平的控制下导通，可以在第八控制信号的无效电平的控制下截止。例如，第十晶体管T10可以设置为N型晶体管，则第八控制信号的有 效电平为高电平，第八控制信号的无效电平为低电平。或者，第十晶体管T10可以设置为P型晶体管，则第八控制信号的有效电平为低电平，第八控制信号的无效电平为高电平。
下面以图5所示的像素电路为例，结合图6所示的信号时序图，对本公开实施例提供的像素电路的工作过程作以描述。
其中，如图6所示，em代表发光控制信号端EM的发光信号，cs1代表第一控制信号端CS1的第一控制信号，cs2代表第二控制信号端CS2的第二控制信号，cs4代表第四控制信号端CS4的第四控制信号，cs5代表第五控制信号端CS5的第五控制信号，cs6代表第六控制信号端CS6的第六控制信号，cs8代表第八控制信号端CS8的第八控制信号，da代表数据信号端DA的数据电压信号，vinit2代表第二初始化信号端VINIT2的第二初始化信号。
在复位阶段F1，第一晶体管T1在第一控制信号cs1的低电平的控制下导通，第二晶体管T2在第二控制信号cs2的高电平的控制下截止，第三晶体管T3在第二控制信号cs2的高电平的控制下截止，第四晶体管T4在第五控制信号cs5的低电平的控制下导通，第五晶体管T5在第四控制信号cs4的高电平的控制下截止，第六晶体管T6在发光信号em的高电平的控制下截止，第七晶体管T7在发光信号em的高电平的控制下截止，第八晶体管T8在第六控制信号cs6的低电平的控制下导通，第十晶体管T10在第八控制信号cs8的低电平的控制下导通。导通的第一晶体管T1将第一参考信号端VREF1的第一参考信号提供给驱动晶体管T0的第一极，则驱动晶体管T0的第一极上的电压Vs为Vref1。导通的第四晶体管T4将第一初始化信号端VINIT1的第一初始化信号提供给驱动晶体管T0的栅极，则驱动晶体管T0的栅极上的电压Vg为Vinit1。导通的第八晶体管T8将第二初始化信号端VINIT2的第二初始化信号提供给发光器件L的阳极，则发光器件L的阳极上的电压VL为Vinit2。导通的第十晶体管T10将第二参考信号端VREF2的第二参考信号提供给第一节点N1，则第一节点N1上的电压VN1为Vref2。第二电容C2稳定第一节点N1的电压。
在阈值补偿阶段F2，第一晶体管T1在第一控制信号cs1的低电平的控制下导通，第二晶体管T2在第二控制信号cs2的低电平的控制下导通，第三晶体管T3在第二控制信号cs2的低电平的控制下导通，第四晶体管T4在第五控制信号cs5的高电平的控制下截止，第五晶体管T5在第四控制信号cs4的高电平的控制下截止，第六晶体管T6在发光信号em的高电平的控制下截止，第七晶体管T7在发光信号em的高电平的控制下截止，第八晶体管T8在第六控制信号cs6的低电平的控制下导通，第十晶体管T10在第八控制信号cs8的高电平的控制下截止。导通的第一晶体管T1将第一参考信号端VREF1的第一参考信号提供给驱动晶体管T0的第一极，则驱动晶体管T0的第一极上的电压Vs为Vref1。导通的第二晶体管T2将驱动晶体管T0的第二极与第二节点N2导通，导通的第三晶体管T3将第二节点N2与驱动晶体管T0的栅极导通，由于导通的第二晶体管T2和第三晶体管T3可以使驱动晶体管T0形成二极管连接方式，则输入驱动晶体管T0的第一极的第一参考信号可以经过形成二极管连接方式的驱动晶体管T0，输入驱动晶体管T0的栅极，并对驱动晶体管T0的阈值电压Vth进行补偿，以使驱动晶体管T0的栅极Vg电压为Vref1+Vth，则第二节点N2上的电压VN2和驱动晶体管T0的第二极Vd电压为Vref1+Vth。导通的第八晶体管T8将第二初始化信号端VINIT2的第二初始化信号提供给发光器件L的阳极，则发光器件L的阳极上的电压VL为Vinit2。第二电容C2稳定第一节点N1的电压。
在数据写入阶段F3，第一晶体管T1在第一控制信号cs1的高电平的控制下截止，第二晶体管T2在第二控制信号cs2的高电平的控制下截止，第三晶体管T3在第二控制信号cs2的高电平的控制下截止，第四晶体管T4在第五控制信号cs5的高电平的控制下截止，第五晶体管T5在第四控制信号cs4的低电平的控制下导通，第六晶体管T6在发光信号em的高电平的控制下截止，第七晶体管T7在发光信号em的高电平的控制下截止，第八晶体管T8在第六控制信号cs6的高电平的控制下截止，第十晶体管T11在第八控制信号cs8的高电平的控制下截止。导通的第五晶体管T5将数据信号端DA的数据电压 信号提供给第一节点N1，第一电容C1将第一节点N1的数据电压信号耦合至驱动晶体管T0的栅极，则驱动晶体管T0的栅极Vg电压为Vref1+Vth+Vda-Vref2。第二电容C2稳定第一节点N1的电压。
在发光阶段F4，第一晶体管T1在第一控制信号cs1的高电平的控制下截止，第二晶体管T2在第二控制信号cs2的高电平的控制下截止，第三晶体管T3在第二控制信号cs2的高电平的控制下截止，第四晶体管T4在第五控制信号cs5的高电平的控制截止，第五晶体管T5在第四控制信号cs4的高电平的控制下截止，第六晶体管T6在发光信号em的低电平的控制下导通，第七晶体管T7在发光信号em的低电平的控制下导通，第八晶体管T8在第六控制信号cs6的高电平的控制下截止，第十晶体管T10在第八控制信号cs8的高电平的控制下截止。导通的第六晶体管T6将第一电源端VDD的第一电源电压Vdd提供给驱动晶体管T0的第一极，则驱动晶体管T0的第一极Vs的电压为Vdd，导通的第七晶体管T7将驱动晶体管T0的第二极与发光器件L导通，驱动发光器件L发光。则，驱动晶体管T0工作于饱和区，其产生的驱动电流I可表示为：
示例性的，第一控制信号端CS1和第六控制信号端CS6可以为同一信号端。这样可以降低信号线的数量，降低布线占用的空间。
示例性的，第五控制信号端CS5和第八控制信号端CS8可以为同一信号端。这样可以降低信号线的数量，降低布线占用的空间。
本公开实施例提供了像素电路的又一些结构示意图，如图7所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
示例性的，如图7所示，第二控制信号端CS2与第八控制信号端CS8可以为同一信号端。第十晶体管T10的栅极与第八控制信号端CS8耦接。这样可以降低信号线的数量，降低布线占用的空间。
下面以图7所示的像素电路为例，结合图8所示的信号时序图，对本公 开实施例提供的像素电路的工作过程作以描述。
其中，如图8所示，em代表发光控制信号端EM的发光信号，cs1代表第一控制信号端CS1的第一控制信号，cs2代表第二控制信号端CS2的第二控制信号，cs4代表第四控制信号端CS4的第四控制信号，cs5代表第五控制信号端CS5的第五控制信号，cs6代表第六控制信号端CS6的第六控制信号，da代表数据信号端DA的数据电压信号，vinit2代表第二初始化信号端VINIT2的第二初始化信号。
在复位阶段F1，第一晶体管T1在第一控制信号cs1的低电平的控制下导通，第二晶体管T2在第二控制信号cs2的高电平的控制下截止，第三晶体管T3在第二控制信号cs2的高电平的控制下截止，第四晶体管T4在第五控制信号cs5的低电平的控制下导通，第五晶体管T5在第四控制信号cs4的高电平的控制下截止，第六晶体管T6在发光信号em的高电平的控制下截止，第七晶体管T7在发光信号em的高电平的控制下截止，第八晶体管T8在第六控制信号cs6的低电平的控制下导通，第十晶体管T10在第二控制信号cs2的高电平的控制下截止。导通的第一晶体管T1将第一参考信号端VREF1的第一参考信号提供给驱动晶体管T0的第一极，则驱动晶体管T0的第一极上的电压Vs为Vref1。导通的第四晶体管T4将第一初始化信号端VINIT1的第一初始化信号提供给驱动晶体管T0的栅极，则驱动晶体管T0的栅极上的电压Vg为Vinit1。导通的第八晶体管T8将第二初始化信号端VINIT2的第二初始化信号提供给发光器件L的阳极，则发光器件L的阳极上的电压VL为Vinit2。
在阈值补偿阶段F2，第一晶体管T1在第一控制信号cs1的低电平的控制下导通，第二晶体管T2在第二控制信号cs2的低电平的控制下导通，第三晶体管T3在第二控制信号cs2的低电平的控制下导通，第四晶体管T4在第五控制信号cs5的高电平的控制下截止，第五晶体管T5在第四控制信号cs4的高电平的控制下截止，第六晶体管T6在发光信号em的高电平的控制下截止，第七晶体管T7在发光信号em的高电平的控制下截止，第八晶体管T8在第六控制信号cs6的低电平的控制下导通，第十晶体管T10在第二控制信号cs2 的低电平的控制下导通。导通的第一晶体管T1将第一参考信号端VREF1的第一参考信号提供给驱动晶体管T0的第一极，则驱动晶体管T0的第一极上的电压Vs为Vref1。导通的第二晶体管T2将驱动晶体管T0的第二极与第二节点N2导通，导通的第三晶体管T3将第二节点N2与驱动晶体管T0的栅极导通，由于导通的第二晶体管T2和第三晶体管T3可以使驱动晶体管T0形成二极管连接方式，则输入驱动晶体管T0的第一极的第一参考信号可以经过形成二极管连接方式的驱动晶体管T0，输入驱动晶体管T0的栅极，并对驱动晶体管T0的阈值电压Vth进行补偿，以使驱动晶体管T0的栅极Vg电压为Vref1+Vth，则第二节点N2上的电压VN2和驱动晶体管T0的第二极Vd电压为Vref1+Vth。导通的第八晶体管T8将第二初始化信号端VINIT2的第二初始化信号提供给发光器件L的阳极，则发光器件L的阳极上的电压VL为Vinit2。导通的第十晶体管T10将第二参考信号端VREF2的第二参考信号提供给第一节点N1，则第一节点N1上的电压VN1为Vref2。第二电容C2稳定第一节点N1的电压。第二电容C2稳定第一节点N1的电压。
在数据写入阶段F3，第一晶体管T1在第一控制信号cs1的高电平的控制下截止，第二晶体管T2在第二控制信号cs2的高电平的控制下截止，第三晶体管T3在第二控制信号cs2的高电平的控制下截止，第四晶体管T4在第五控制信号cs5的高电平的控制下截止，第五晶体管T5在第四控制信号cs4的低电平的控制下导通，第六晶体管T6在发光信号em的高电平的控制下截止，第七晶体管T7在发光信号em的高电平的控制下截止，第八晶体管T8在第六控制信号cs6的高电平的控制下截止，第十晶体管T11在第八控制信号cs8的高电平的控制下截止。导通的第五晶体管T5将数据信号端DA的数据电压信号提供给第一节点N1，第一电容C1将第一节点N1的数据电压信号耦合至驱动晶体管T0的栅极，则驱动晶体管T0的栅极Vg电压为Vref1+Vth+Vda-Vref2。第二电容C2稳定第一节点N1的电压。
在发光阶段F4，第一晶体管T1在第一控制信号cs1的高电平的控制下截止，第二晶体管T2在第二控制信号cs2的高电平的控制下截止，第三晶体管 T3在第二控制信号cs2的高电平的控制下截止，第四晶体管T4在第五控制信号cs5的高电平的控制截止，第五晶体管T5在第四控制信号cs4的高电平的控制下截止，第六晶体管T6在发光信号em的低电平的控制下导通，第七晶体管T7在发光信号em的低电平的控制下导通，第八晶体管T8在第六控制信号cs6的高电平的控制下截止，第十晶体管T10在第八控制信号cs8的高电平的控制下截止。导通的第六晶体管T6将第一电源端VDD的第一电源电压Vdd提供给驱动晶体管T0的第一极，则驱动晶体管T0的第一极Vs的电压为Vdd，导通的第七晶体管T7将驱动晶体管T0的第二极与发光器件L导通，驱动发光器件L发光。则，驱动晶体管T0工作于饱和区，其产生的驱动电流I可表示为：
示例性的，第一控制信号端CS1和第六控制信号端CS6可以为同一信号端。这样可以降低信号线的数量，降低布线占用的空间。
本公开实施例提供了像素电路的又一些结构示意图，如图9所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，如图9所示，第五控制信号端CS5与发光控制信号端EM可以为同一信号端。这样可以降低信号线的数量，降低布线占用的空间。
在本公开实施例中，如图9所示，还包括：第二复位电路80，与驱动晶体管T0的第二极耦接，被配置为响应于第七控制信号端CS7的信号，将第三初始化信号端VINIT3的信号提供给驱动晶体管T0的第二极。
在本公开实施例中，如图9所示，第二复位电路80包括：第九晶体管T9；其中，第九晶体管T9的栅极与第七控制信号端CS7耦接，第九晶体管T9的第一极与驱动晶体管T0的第二极耦接，第九晶体管T9的第二极与第三初始化信号端VINIT3耦接。
示例性地，第九晶体管T9可以在第七控制信号端CS7上传输的第七控制 信号的有效电平的控制下导通，可以在第七控制信号的无效电平的控制下截止。例如，第九晶体管T9可以设置为N型晶体管，则第七控制信号的有效电平为高电平，第七控制信号的无效电平为低电平。或者，第九晶体管T9可以设置为P型晶体管，则第七控制信号的有效电平为低电平，第七控制信号的无效电平为高电平。
在本公开实施例中，如图9所示，第三复位电路90还包括：第十三晶体管T13；其中，第十三晶体管T13的栅极与第九控制信号端CS9耦接，第十三晶体管T13的第一极与第三节点N3耦接，第十三晶体管T13的第二极与第三参考信号端VREF3耦接。
示例性地，第十三晶体管T13可以在第九控制信号端CS9上传输的第九控制信号的有效电平的控制下导通，可以在第九控制信号的无效电平的控制下截止。例如，第十三晶体管T13可以设置为N型晶体管，则第九控制信号的有效电平为高电平，第九控制信号的无效电平为低电平。或者，第十三晶体管T13可以设置为P型晶体管，则第九控制信号的有效电平为低电平，第九控制信号的无效电平为高电平。
下面以图9所示的像素电路为例，结合图10所示的信号时序图，对本公开实施例提供的像素电路的工作过程作以描述。
其中，如图10所示，em代表发光控制信号端EM的发光信号，cs1代表第一控制信号端CS1的第一控制信号，cs2代表第二控制信号端CS2的第二控制信号，cs4代表第四控制信号端CS4的第四控制信号，cs5代表第五控制信号端CS5的第五控制信号，cs6代表第六控制信号端CS6的第六控制信号，cs7代表第七控制信号端CS7的第七控制信号，cs8代表第八控制信号端CS8的第八控制信号，cs9代表第九控制信号端CS9的第九控制信号，da代表数据信号端DA的数据电压信号，vinit2代表第二初始化信号端VINIT2的第二初始化信号。
在复位阶段F1，第一晶体管T1在第一控制信号cs1的高电平的控制下截止，第二晶体管T2在第二控制信号cs2的低电平的控制下导通，第三晶体管 T3在第二控制信号cs2的低电平的控制下导通，第四晶体管T4在发光信号em的高电平的控制下截止，第五晶体管T5在第四控制信号cs4的高电平的控制下截止，第六晶体管T6在发光信号em的高电平的控制下截止，第七晶体管T7在发光信号em的高电平的控制下截止，第八晶体管T8在第六控制信号cs6的高电平的控制下截止，第九晶体管T9在第七控制信号cs7的低电平的控制下导通，第十一晶体管T11在第八控制信号cs8的高电平的控制下截止，第十二晶体管T12在第八控制信号cs8的高电平的控制下截止，第十三晶体管T13在第九控制信号cs9的高电平的控制下截止。导通的第九晶体管T9将第三初始化信号端VINIT3的第三初始化信号提供给驱动晶体管T0的第二极，则驱动晶体管T0的第二极的电压Vd为Vinit3。导通的第二晶体管T2和导通第三晶体管T3将驱动晶体管T0的第二极上的第三初始化信号提供给驱动晶体管T0的栅极，则驱动晶体管T0的栅极上的电压Vg为Vinit3。其中，Vinit3代表第三初始化信号的电压。
在阈值补偿阶段F2，第一晶体管T1在第一控制信号cs1的低电平的控制下导通，第二晶体管T2在第二控制信号cs2的低电平的控制下导通，第三晶体管T3在第二控制信号cs2的低电平的控制下导通，第四晶体管T4在发光信号em的高电平的控制下截止，第五晶体管T5在第四控制信号cs4的高电平的控制下截止，第六晶体管T6在发光信号em的高电平的控制下截止，第七晶体管T7在发光信号em的高电平的控制下截止，第八晶体管T8在第六控制信号cs6的低电平的控制下导通，第九晶体管T9在第七控制信号cs7的高电平的控制下截止，第十一晶体管T11在第八控制信号cs8的低电平的控制下导通，第十二晶体管T12在第八控制信号cs8的低电平的控制下导通，第十三晶体管T13在第九控制信号cs9的高电平的控制下截止。导通的第一晶体管T1将第一参考信号端VREF1的第一参考信号提供给驱动晶体管T0的第一极，则驱动晶体管T0的第一极上的电压Vs为Vref1。导通的第二晶体管T2将驱动晶体管T0的第二极与第二节点N2导通，导通的第三晶体管T3将第二节点N2与驱动晶体管T0的栅极导通，由于导通的第二晶体管T2和第 三晶体管T3可以使驱动晶体管T0形成二极管连接方式，则输入驱动晶体管T0的第一极的第一参考信号可以经过形成二极管连接方式的驱动晶体管T0，输入驱动晶体管T0的栅极，并对驱动晶体管T0的阈值电压Vth进行补偿，以使驱动晶体管T0的栅极Vg电压为Vref1+Vth，则第二节点N2上的电压VN2和驱动晶体管T0的第二极Vd电压为Vref1+Vth。导通的第八晶体管T8将第二初始化信号端VINIT2的第二初始化信号提供给发光器件L的阳极，则发光器件L的阳极上的电压VL为Vinit2。导通的第十二晶体管T12将第二参考信号端VREF2的第二参考信号提供给第三节点N3，导通的第十一晶体管T11将第三节点N3上的第二参考信号提供给第一节点N1，则第一节点N1上的电压VN1为Vref2。第二电容C2稳定第一节点N1的电压。
在数据写入阶段F3，第一晶体管T1在第一控制信号cs1的高电平的控制下截止，第二晶体管T2在第二控制信号cs2的高电平的控制下截止，第三晶体管T3在第二控制信号cs2的高电平的控制下截止，第四晶体管T4在发光信号em的高电平的控制下截止，第五晶体管T5在第四控制信号cs4的低电平的控制下导通，第六晶体管T6在发光信号em的高电平的控制下截止，第七晶体管T7在发光信号em的高电平的控制下截止，第八晶体管T8在第六控制信号cs6的高电平的控制下截止，第九晶体管T9在第七控制信号cs7的高电平的控制下截止，第十一晶体管T11在第八控制信号cs8的高电平的控制下截止，第十二晶体管T12在第八控制信号cs8的高电平的控制下截止，第十三晶体管T13在第九控制信号cs9的高电平的控制下截止。导通的第五晶体管T5将数据信号端DA的数据电压信号提供给第一节点N1，第一电容C1将第一节点N1的数据电压信号耦合至驱动晶体管T0的栅极，则驱动晶体管T0的栅极Vg电压为Vref1+Vth+Vda-Vref2。第二电容C2稳定第一节点N1的电压。
在发光阶段F4，第一晶体管T1在第一控制信号cs1的高电平的控制下截止，第二晶体管T2在第二控制信号cs2的高电平的控制下截止，第三晶体管T3在第二控制信号cs2的高电平的控制下截止，第四晶体管T4在发光信号 em的低电平的控制下导通，第五晶体管T5在第四控制信号cs4的高电平的控制下截止，第六晶体管T6在发光信号em的低电平的控制下导通，第七晶体管T7在发光信号em的低电平的控制下导通，第八晶体管T8在第六控制信号cs6的高电平的控制下截止，第九晶体管T9在第七控制信号cs7的高电平的控制下截止，第十一晶体管T11在第八控制信号cs8的高电平的控制下截止，第十二晶体管T12在第八控制信号cs8的高电平的控制下截止，第十三晶体管T13在第九控制信号cs9的低电平的控制下导通。导通的第四晶体管T4将第一初始化信号端VINIT1的第一初始化信号提供给第二节点N2，则第二节点N2上的电压VN2为Vinit1。导通的第十三晶体管T13将第三参考信号端VREF3的第三参考信号提供给第三节点N3，则第三节点N3上的电压VN3为Vref3。导通的第六晶体管T6将第一电源端VDD的第一电源电压Vdd提供给驱动晶体管T0的第一极，则驱动晶体管T0的第一极Vs的电压为Vdd，导通的第七晶体管T7将驱动晶体管T0的第二极与发光器件L导通，驱动发光器件L发光。则，驱动晶体管T0工作于饱和区，其产生的驱动电流I可表示为：其中，μ代表驱动晶体管T0的迁移率，Cox代表驱动晶体管T0的栅绝缘层单位面积电容，W/L代表驱动晶体管T0的沟道宽长比。
示例性的，第一控制信号端CS1、第六控制信号端CS6以及第八控制信号端CS8可以为同一信号端。这样可以降低信号线的数量，降低布线占用的空间。
示例性的，发光控制信号端EM和第九控制信号端CS9可以为同一信号端。这样可以降低信号线的数量，降低布线占用的空间。
本公开实施例提供了像素电路的又一些结构示意图，如图11所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
示例性的，如图11所示，第三参考信号端与第一初始化信号端VINIT1 可以为同一信号端。这样可以降低信号线的数量，降低布线占用的空间。
图11所示的像素电路对应的信号时序图，可以如图10所示。并且，图11所示的像素电路结合图10所示的信号时序图的具体工作过程，可以参照上述实施例的描述，在此不作赘述。
本公开实施例提供了像素电路的又一些结构示意图，如图12所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
下面以图12所示的像素电路为例，结合图10所示的信号时序图，对本公开实施例提供的像素电路的工作过程作以描述。
在复位阶段F1，第一晶体管T1在第一控制信号cs1的高电平的控制下截止，第二晶体管T2在第二控制信号cs2的低电平的控制下导通，第三晶体管T3在第二控制信号cs2的低电平的控制下导通，第四晶体管T4在发光信号em的高电平的控制下截止，第五晶体管T5在第四控制信号cs4的高电平的控制下截止，第六晶体管T6在发光信号em的高电平的控制下截止，第七晶体管T7在发光信号em的高电平的控制下截止，第八晶体管T8在第六控制信号cs6的高电平的控制下截止，第九晶体管T9在第七控制信号cs7的低电平的控制下导通，第十一晶体管T11在第八控制信号cs8的高电平的控制下截止，第十二晶体管T12在第八控制信号cs8的高电平的控制下截止。导通的第九晶体管T9将第三初始化信号端VINIT3的第三初始化信号提供给驱动晶体管T0的第二极，则驱动晶体管T0的第二极的电压Vd为Vinit3。导通的第二晶体管T2和导通第三晶体管T3将驱动晶体管T0的第二极上的第三初始化信号提供给驱动晶体管T0的栅极，则驱动晶体管T0的栅极上的电压Vg为Vinit3。
在阈值补偿阶段F2，第一晶体管T1在第一控制信号cs1的低电平的控制下导通，第二晶体管T2在第二控制信号cs2的低电平的控制下导通，第三晶体管T3在第二控制信号cs2的低电平的控制下导通，第四晶体管T4在发光信号em的高电平的控制下截止，第五晶体管T5在第四控制信号cs4的高电 平的控制下截止，第六晶体管T6在发光信号em的高电平的控制下截止，第七晶体管T7在发光信号em的高电平的控制下截止，第八晶体管T8在第六控制信号cs6的低电平的控制下导通，第九晶体管T9在第七控制信号cs7的高电平的控制下截止，第十一晶体管T11在第八控制信号cs8的低电平的控制下导通，第十二晶体管T12在第八控制信号cs8的低电平的控制下导通。导通的第一晶体管T1将第一参考信号端VREF1的第一参考信号提供给驱动晶体管T0的第一极，则驱动晶体管T0的第一极上的电压Vs为Vref1。导通的第二晶体管T2将驱动晶体管T0的第二极与第二节点N2导通，导通的第三晶体管T3将第二节点N2与驱动晶体管T0的栅极导通，由于导通的第二晶体管T2和第三晶体管T3可以使驱动晶体管T0形成二极管连接方式，则输入驱动晶体管T0的第一极的第一参考信号可以经过形成二极管连接方式的驱动晶体管T0，输入驱动晶体管T0的栅极，并对驱动晶体管T0的阈值电压Vth进行补偿，以使驱动晶体管T0的栅极Vg电压为Vref1+Vth，则第二节点N2上的电压VN2和驱动晶体管T0的第二极Vd电压为Vref1+Vth。导通的第八晶体管T8将第二初始化信号端VINIT2的第二初始化信号提供给发光器件L的阳极，则发光器件L的阳极上的电压VL为Vinit2。导通的第十二晶体管T12将第二参考信号端VREF2的第二参考信号提供给第三节点N3，导通的第十一晶体管T11将第三节点N3上的第二参考信号提供给第一节点N1，则第一节点N1上的电压VN1为Vref2。第二电容C2稳定第一节点N1的电压。
在数据写入阶段F3，第一晶体管T1在第一控制信号cs1的高电平的控制下截止，第二晶体管T2在第二控制信号cs2的高电平的控制下截止，第三晶体管T3在第二控制信号cs2的高电平的控制下截止，第四晶体管T4在发光信号em的高电平的控制下截止，第五晶体管T5在第四控制信号cs4的低电平的控制下导通，第六晶体管T6在发光信号em的高电平的控制下截止，第七晶体管T7在发光信号em的高电平的控制下截止，第八晶体管T8在第六控制信号cs6的高电平的控制下截止，第九晶体管T9在第七控制信号cs7的高电平的控制下截止，第十一晶体管T11在第八控制信号cs8的高电平的控制 下截止，第十二晶体管T12在第八控制信号cs8的高电平的控制下截止。导通的第五晶体管T5将数据信号端DA的数据电压信号提供给第一节点N1，第一电容C1将第一节点N1的数据电压信号耦合至驱动晶体管T0的栅极，则驱动晶体管T0的栅极Vg电压为Vref1+Vth+Vda-Vref2。第二电容C2稳定第一节点N1的电压。
在发光阶段F4，第一晶体管T1在第一控制信号cs1的高电平的控制下截止，第二晶体管T2在第二控制信号cs2的高电平的控制下截止，第三晶体管T3在第二控制信号cs2的高电平的控制下截止，第四晶体管T4在发光信号em的低电平的控制下导通，第五晶体管T5在第四控制信号cs4的高电平的控制下截止，第六晶体管T6在发光信号em的低电平的控制下导通，第七晶体管T7在发光信号em的低电平的控制下导通，第八晶体管T8在第六控制信号cs6的高电平的控制下截止，第九晶体管T9在第七控制信号cs7的高电平的控制下截止，第十一晶体管T11在第八控制信号cs8的高电平的控制下截止，第十二晶体管T12在第八控制信号cs8的高电平的控制下截止。导通的第四晶体管T4将第一初始化信号端VINIT1的第一初始化信号提供给第二节点N2，则第二节点N2上的电压VN2为Vinit1。导通的第六晶体管T6将第一电源端VDD的第一电源电压Vdd提供给驱动晶体管T0的第一极，则驱动晶体管T0的第一极Vs的电压为Vdd，导通的第七晶体管T7将驱动晶体管T0的第二极与发光器件L导通，驱动发光器件L发光。则，驱动晶体管T0工作于饱和区，其产生的驱动电流I可表示为： 其中，μ代表驱动晶体管T0的迁移率，Cox代表驱动晶体管T0的栅绝缘层单位面积电容，W/L代表驱动晶体管T0的沟道宽长比。
基于同一公开构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述像素电路。该显示装置解决问题的原理与前述像素电路相似，因此该显示装置的实施可以参见前述像素电路的实施，重复之处在此不 再赘述。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (20)

  1. 一种像素电路，包括：
    发光器件；
    驱动晶体管，与所述发光器件耦接，被配置为根据数据电压信号产生驱动所述发光器件发光的驱动电流；
    第一补偿电路，与所述驱动晶体管耦接，被配置为响应于第一控制信号端的信号，将第一参考信号端的第一参考信号提供给所述驱动晶体管的第一极；
    第二补偿电路，与所述驱动晶体管耦接，被配置为响应于第二控制信号端和第三控制信号端的信号，将所述驱动晶体管的阈值电压和输入所述驱动晶体管的第一极的第一参考信号，提供给所述驱动晶体管的栅极；
    数据写入电路，与所述第一节点耦接，被配置为响应于第四控制信号端的信号，将数据信号端的所述数据电压信号提供给第一节点；
    耦合控制电路，与所述第一节点和所述驱动晶体管耦接，被配置为将所述第一节点的数据电压信号耦合至所述驱动晶体管的栅极；
    发光控制电路，与所述发光器件和所述驱动晶体管耦接，被配置为响应于发光控制信号端的信号，将所述驱动晶体管的第一极与第一电源端导通，以及将所述驱动晶体管的第二极与所述发光器件导通，驱动所述发光器件发光。
  2. 如权利要求1所述的像素电路，其中，所述第一补偿电路包括：第一晶体管；
    所述第一晶体管的栅极与所述第一控制信号端耦接，所述第一晶体管的第一极与所述驱动晶体管的第一极耦接，所述第一晶体管的第二极与所述第一参考信号端耦接。
  3. 如权利要求1所述的像素电路，其中，所述第二补偿电路包括：第二晶体管和第三晶体管；
    所述第二晶体管的栅极与所述第二控制信号端耦接，所述第二晶体管的第一极与所述第二节点耦接，所述第二晶体管的第二极与所述驱动晶体管的第二极耦接；
    所述第三晶体管的栅极与所述第三控制信号端耦接，所述第三晶体管的第一极与所述驱动晶体管的栅极耦接，所述第三晶体管的第二极与所述第二节点耦接。
  4. 如权利要求3所述的像素电路，其中，所述第二补偿电路还包括：第四晶体管；
    所述第四晶体管的栅极与第五控制信号端耦接，所述第四晶体管的第一极与所述驱动晶体管的栅极或所述第二节点耦接，所述第四晶体管的第二极与第一初始化信号端耦接。
  5. 如权利要求4所述的像素电路，其中，所述第五控制信号端与所述发光控制信号端可以为同一信号端。
  6. 如权利要求1-5任一项所述的像素电路，其中，所述数据写入电路包括：第五晶体管；
    所述第五晶体管的栅极与所述第四控制信号端耦接，所述第五晶体管的第一极与所述数据信号端耦接，所述第五晶体管的第二极与所述第一节点耦接。
  7. 如权利要求1-5任一项所述的像素电路，其中，所述耦合控制电路包括：第一电容；
    所述第一电容的第一电极与所述第一节点耦接，所述第一电容的第二电极与所述驱动晶体管的栅极耦接。
  8. 如权利要求1-5任一项所述的像素电路，其中，所述发光控制电路包括：第六晶体管和第七晶体管；
    所述第六晶体管的栅极与所述发光控制信号端耦接，所述第六晶体管的第一极与所述第一电源端耦接，所述第六晶体管的第二极与所述驱动晶体管的第一极耦接；
    所述第七晶体管的栅极与所述发光控制信号端耦接，所述第七晶体管的第一极与所述驱动晶体管的第二极耦接，所述第七晶体管的第二极与所述发光器件耦接。
  9. 如权利要求1-8任一项所述的像素电路，其中，还包括：第一复位电路，与所述发光器件耦接，被配置为响应于第六控制信号端的信号，将第二初始化信号端的信号提供给所述发光器件。
  10. 如权利要求9所述的像素电路，其中，所述第一复位电路包括：第八晶体管；
    所述第八晶体管的栅极与所述第六控制信号端耦接，所述第八晶体管的第一极与所述发光器件耦接，所述第八晶体管的第二极与所述第二初始化信号端耦接。
  11. 如权利要求1-8任一项所述的像素电路，其中，还包括：稳压电路，与所述第一节点耦接，被配置为稳定所述第一节点的电压。
  12. 如权利要求11所述的像素电路，其中，所述稳压电路包括：第二电容；
    所述第二电容的第一电极与所述第一电源端耦接，所述第二电容的第二电极与所述第一节点耦接。
  13. 如权利要求1-8任一项所述的像素电路，其中，还包括：第二复位电路，与所述驱动晶体管的第二极耦接，被配置为响应于第七控制信号端的信号，将第三初始化信号端的信号提供给所述驱动晶体管的第二极。
  14. 如权利要求13所述的像素电路，其中，所述第二复位电路包括：第九晶体管；
    所述第九晶体管的栅极与所述第七控制信号端耦接，所述第九晶体管的第一极与所述驱动晶体管的第二极耦接，所述第九晶体管的第二极与所述第三初始化信号端耦接。
  15. 如权利要求1-8任一项所述的像素电路，其中，还包括：第三复位电路，与所述第一节点耦接，被配置为响应于第八控制信号端的信号，将第二 参考信号端的信号提供给所述第一节点。
  16. 如权利要求15所述的像素电路，其中，所述第三复位电路包括：第十晶体管；
    所述第十晶体管的栅极与所述第八控制信号端耦接，所述第十晶体管的第一极与所述第一节点耦接，所述第十晶体管的第二极与所述第二参考信号端耦接。
  17. 如权利要求15所述的像素电路，其中，所述第三复位电路包括：第十一晶体管和第十二晶体管；
    所述第十一晶体管的栅极与所述第八控制信号端耦接，所述第十一晶体管的第一极与所述第一节点耦接，所述第十一晶体管的第二极与第三节点耦接；
    所述第十二晶体管的栅极与所述第八控制信号端耦接，所述第十二晶体管的第一极与所述第三节点耦接，所述第十一晶体管的第二极与所述第二参考信号端耦接。
  18. 如权利要求17所述的像素电路，其中，所述第三复位电路还包括：第十三晶体管；
    所述第十三晶体管的栅极与第九控制信号端耦接，所述第十三晶体管的第一极与所述第三节点耦接，所述第十三晶体管的第二极与第三参考信号端耦接。
  19. 一种显示装置，其中，包括如权利要求1-18任一项所述的像素电路。
  20. 一种如权利要求1-18任一项所述的像素电路的驱动方法，其中，包括：
    复位阶段，第一补偿电路响应于第一控制信号端的信号，将第一参考信号端的第一参考信号提供给所述驱动晶体管的第一极；
    阈值补偿阶段，第一补偿电路响应于第一控制信号端的信号，将第一参考信号端的第一参考信号提供给所述驱动晶体管的第一极；第二补偿电路响应于第二控制信号端和第三控制信号端的信号，将所述驱动晶体管的阈值电 压和输入所述驱动晶体管的第一极的第一参考信号，提供给所述驱动晶体管的栅极；
    数据写入阶段，数据写入电路响应于第四控制信号端的信号，将数据信号端的所述数据电压信号提供给第一节点；耦合控制电路将所述第一节点的数据电压信号耦合至所述驱动晶体管的栅极；
    发光阶段，发光控制电路响应于发光控制信号端的信号，将所述驱动晶体管的第一极与第一电源端导通，以及将所述驱动晶体管的第二极与所述发光器件导通，驱动所述发光器件发光。
PCT/CN2023/109362 2023-07-26 2023-07-26 像素电路、显示装置及驱动方法 Pending WO2025020130A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119993043A (zh) * 2025-04-17 2025-05-13 南京大学 一种电流比例可调的像素驱动电路及其控制方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104091560A (zh) * 2014-06-23 2014-10-08 上海天马有机发光显示技术有限公司 有机发光二极管像素补偿电路及其显示面板、显示装置
US20140354711A1 (en) * 2013-05-30 2014-12-04 Samsung Display Co., Ltd. Organic light emitting display device and method of driving the same
CN105575331A (zh) * 2015-11-25 2016-05-11 友达光电股份有限公司 像素电压补偿电路
CN105931599A (zh) * 2016-04-27 2016-09-07 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板、显示装置
CN106910468A (zh) * 2017-04-28 2017-06-30 上海天马有机发光显示技术有限公司 显示面板、显示装置及像素电路的驱动方法
WO2020147477A1 (zh) * 2019-01-18 2020-07-23 京东方科技集团股份有限公司 显示装置及其像素补偿电路和驱动方法
CN114783382A (zh) * 2022-03-24 2022-07-22 京东方科技集团股份有限公司 像素电路、其驱动方法、显示面板及显示装置
CN115705823A (zh) * 2021-08-05 2023-02-17 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示基板和显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101682690B1 (ko) * 2010-07-20 2016-12-07 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치
EP4300474A4 (en) * 2021-07-30 2024-02-28 BOE Technology Group Co., Ltd. PIXEL CIRCUIT, CONTROL METHOD AND DISPLAY DEVICE
CN114038420B (zh) * 2021-11-30 2023-04-07 上海天马微电子有限公司 一种显示面板和显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140354711A1 (en) * 2013-05-30 2014-12-04 Samsung Display Co., Ltd. Organic light emitting display device and method of driving the same
CN104091560A (zh) * 2014-06-23 2014-10-08 上海天马有机发光显示技术有限公司 有机发光二极管像素补偿电路及其显示面板、显示装置
CN105575331A (zh) * 2015-11-25 2016-05-11 友达光电股份有限公司 像素电压补偿电路
CN105931599A (zh) * 2016-04-27 2016-09-07 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板、显示装置
CN106910468A (zh) * 2017-04-28 2017-06-30 上海天马有机发光显示技术有限公司 显示面板、显示装置及像素电路的驱动方法
WO2020147477A1 (zh) * 2019-01-18 2020-07-23 京东方科技集团股份有限公司 显示装置及其像素补偿电路和驱动方法
CN115705823A (zh) * 2021-08-05 2023-02-17 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示基板和显示装置
CN114783382A (zh) * 2022-03-24 2022-07-22 京东方科技集团股份有限公司 像素电路、其驱动方法、显示面板及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4583091A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119993043A (zh) * 2025-04-17 2025-05-13 南京大学 一种电流比例可调的像素驱动电路及其控制方法

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