WO2025059807A1 - 主机、系统及控制方法 - Google Patents

主机、系统及控制方法 Download PDF

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Publication number
WO2025059807A1
WO2025059807A1 PCT/CN2023/119474 CN2023119474W WO2025059807A1 WO 2025059807 A1 WO2025059807 A1 WO 2025059807A1 CN 2023119474 W CN2023119474 W CN 2023119474W WO 2025059807 A1 WO2025059807 A1 WO 2025059807A1
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WO
WIPO (PCT)
Prior art keywords
interface
host
peak power
power management
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2023/119474
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English (en)
French (fr)
Inventor
何有信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Priority to PCT/CN2023/119474 priority Critical patent/WO2025059807A1/zh
Priority to KR1020247030388A priority patent/KR20250044586A/ko
Priority to EP23924478.3A priority patent/EP4553635A4/en
Priority to JP2024553244A priority patent/JP2025537449A/ja
Priority to CN202380010903.5A priority patent/CN120112881A/zh
Priority to US18/392,682 priority patent/US12386737B2/en
Priority to TW113130483A priority patent/TW202514392A/zh
Publication of WO2025059807A1 publication Critical patent/WO2025059807A1/zh
Priority to US19/275,837 priority patent/US20250348428A1/en
Priority to US19/341,822 priority patent/US20260030156A1/en
Priority to US19/341,783 priority patent/US20260030155A1/en
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625—Power saving in storage systems
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of storage technology, and in particular to a host, a system and a control method.
  • the hardware system corresponding to some devices may include a host and a storage system.
  • the host can supply power to the storage system, and the maximum power supplied can be called peak power.
  • the embodiment of the present application provides a host, a system and a control method, wherein the storage system included in the system can sense the peak power capability supported by the host, and can determine an appropriate peak power management strategy based on the sensed peak power capability, so that the storage performance of the storage system can be fully utilized.
  • the technical solution is as follows:
  • a system including a host and a storage system, wherein the host is configured with a first interface, the storage system includes a storage controller, the storage controller is configured with a second interface, and the host and the storage system are coupled through the first interface and the second interface to implement information exchange.
  • the host is configured to send an identifier indicating the peak power capability supported by the host through the first interface.
  • the storage controller is configured to receive the identifier through the second interface and determine the peak power management strategy according to the received identifier.
  • the host includes a power management unit, which is used to supply power to the storage system, and the above-mentioned identifier is used to indicate the peak power capability supported by the power management unit.
  • the above-mentioned identifier is used to indicate the magnitude of the current that the power management unit can provide to the storage system according to the supported peak power capability.
  • the current that the power management unit can provide to the storage system according to the supported peak power capability includes Icc and/or Iccq.
  • a default peak power management policy is set in the storage controller.
  • the storage controller is configured to replace the default peak power management policy with the determined peak power management policy after determining the peak power management policy.
  • the peak power management policy includes parameters for controlling the operation of the storage system.
  • the parameters in the peak power management strategy include at least one of a clock frequency, a parallelism of the flash memory NAND, and an operation delay of an I/O request.
  • the storage system is a universal flash storage UFS storage system
  • the first interface and the second interface are UFS interfaces.
  • the above identifier is carried in an extension field of a UFS data packet.
  • the power management unit is a power management chip PMIC.
  • the storage controller is further configured to send a response message through the second interface after receiving the identifier, the response message being used to indicate that the storage controller has received the identifier.
  • the host is further configured to receive the response message through the first interface.
  • the host is further configured to send an I/O request through the first interface.
  • the storage controller is further configured to receive the I/O request through the second interface, and control the storage to process the I/O request according to the determined peak power management policy.
  • a host configured with a first interface.
  • the host is coupled to a second interface of a storage controller in a storage system through the first interface to implement information exchange.
  • the host is configured to send an identifier to the second interface of the storage controller through the first interface, where the identifier is used to indicate the peak power capability supported by the host, and receive a response message sent by the storage controller through the first interface, where the response message is used to indicate that the storage controller has received the identifier.
  • the host includes a power management unit, which is used to supply power to the storage system, and the above-mentioned identifier is used to indicate the peak power capability supported by the power management unit.
  • the above-mentioned identifier is used to indicate the magnitude of the current that the power management unit can provide to the storage system according to the supported peak power capability.
  • the current that the power management unit can provide to the storage system according to the supported peak power capability includes Icc and/or Iccq.
  • the host is further configured to send an I/O request to the second interface of the storage controller through the first interface.
  • the storage system is a flash universal storage UFS storage system
  • the first interface is a UFS interface
  • the identifier is carried in an extension field of a UFS data packet.
  • the power management unit is a power management chip PMIC.
  • a storage system includes a storage controller and a memory.
  • the storage controller is configured with a second interface.
  • the storage controller is coupled to a first interface of a host through the second interface to implement information exchange.
  • the storage controller is configured to receive, through the second interface, an identifier sent by the host through the first interface and used to indicate the peak power capability supported by the host, and determine a peak power management strategy according to the identifier.
  • the memory controller is configured to control the memory to process I/O requests according to the determined peak power management policy.
  • a default peak power management policy is set in the storage controller.
  • the storage controller is configured to replace the default peak power management policy with the determined peak power management policy after determining the peak power management policy.
  • the peak power management policy includes parameters for controlling the operation of the storage system.
  • the parameter includes at least one of a clock frequency, a parallelism of the flash memory NAND, and an operation delay of an I/O request.
  • the storage system is a flash universal storage UFS storage system
  • the second interface is a UFS interface
  • the identifier is carried in an extension field of the UFS data packet.
  • the storage controller is further configured to send a response message through the second interface after receiving the above-mentioned identifier, and the response message is used to indicate that the storage controller has received the identifier.
  • a control method of a system wherein the system includes a host and a storage system, wherein the host is configured with a first interface, the storage system includes a storage controller, the storage controller is configured with a second interface, the host and the storage system are coupled through the first interface and the second interface and information exchange is realized, and the control method includes: the host sends an identifier for indicating the peak power capability supported by the host through the first interface, the storage controller receives the identifier through the second interface, and determines a peak power management strategy matching the peak power capability according to the identifier.
  • the host includes a power management unit, which is used to supply power to the storage system, and the identifier is used to indicate a peak power capability supported by the power management unit.
  • the flag is used to indicate that the power management unit can provide power to the storage according to the supported peak power capability.
  • the amount of current provided by the system is used to indicate that the power management unit can provide power to the storage according to the supported peak power capability.
  • the current that the power management unit can provide to the storage system according to the supported peak power capability includes Icc and/or Iccq.
  • a default peak power management policy is set in the storage controller.
  • the control method further includes: after determining the peak power management policy, the storage controller replaces the default peak power management policy with the determined peak power management policy.
  • the peak power management policy includes parameters for controlling the operation of the storage system.
  • the parameter includes at least one of a clock frequency, a parallelism of the flash memory NAND, and an operation delay of an I/O request.
  • the storage system is a universal flash storage UFS storage system
  • the first interface and the second interface are UFS interfaces.
  • the identifier is carried in an extension field of the UFS data packet.
  • the power management unit is a power management chip PMIC.
  • control method further comprises: after receiving the identifier, the storage controller sends a response message through the second interface, the response message is used to indicate that the storage controller has received the identifier.
  • the host receives the response message through the first interface.
  • control method further comprises: the host sends an I/O request through the first interface, the storage controller receives the I/O request through the second interface, and controls the storage to process the I/O request according to the determined peak power management strategy.
  • the host can send an identifier corresponding to the supported peak power capability to the storage controller.
  • the storage controller can determine the peak power management policy that matches the peak power capability of the host based on the received identifier, and then process the I/O request based on the determined peak power management policy. In this way, the storage controller can adjust the peak power management policy based on the peak power capability of the host, without limiting the storage performance of the storage system in advance, so that the performance of the storage system can be fully utilized.
  • FIG1 is a schematic diagram of an exemplary system provided in an embodiment of the present application.
  • FIG2 is a diagram of an exemplary memory card provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of an exemplary solid-state drive provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of an exemplary system provided in an embodiment of the present application.
  • FIG5 is a flow chart of a control method of an exemplary system provided in an embodiment of the present application.
  • FIG6 is a flow chart of a control method of an exemplary system provided in an embodiment of the present application.
  • FIG. 7 is a schematic diagram of the structure of an exemplary memory provided in an embodiment of the present application.
  • FIG. 1 shows a block diagram of an exemplary system 100 with a storage system according to some aspects of the present disclosure.
  • the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device therein.
  • the system 100 may include a host 108 and a storage system 102, the storage system 102 having one or more memories 104 and a storage controller 106.
  • the host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device.
  • the host 108 may be configured to send data to or receive data from the memory 104.
  • the memory 104 may be any memory device disclosed in the present disclosure.
  • the memory 104 is a NAND flash memory device, such as a three-dimensional (3D) NAND flash memory device.
  • the storage controller 106 is coupled to the memory 104 and the host 108 and is configured to control the memory 104.
  • the storage controller 106 can manage data stored in the memory 104 and communicate with the host 108.
  • the storage controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or for use in a personal computer, a digital camera, a mobile phone, etc. Other media used in electronic devices.
  • the storage controller 106 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc.
  • SSD secure digital
  • CF compact flash
  • USB universal serial bus
  • the storage controller 106 can be configured to control the operation of the memory 104, such as reading, erasing and programming processes.
  • the storage controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc.
  • the storage controller 106 is also configured to process error correction codes (ECC) for data read from or written to the memory 104.
  • ECC error correction codes
  • the storage controller 106 can also perform any other suitable functions, such as formatting the memory 104.
  • the storage controller 106 can communicate with an external device (e.g., a host 108) according to a specific communication protocol.
  • the storage controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced mini disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.
  • various interface protocols such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced mini disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.
  • the storage controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the storage system 102 can be implemented and packaged into different types of terminal electronic products.
  • the storage controller 106 and a single memory 104 can be integrated into a memory card 202.
  • the memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc.
  • the memory card 202 may also include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG. 1).
  • the storage controller 106 and multiple memories 104 can be integrated into an SSD 306.
  • SSD 306 may also include an SSD connector 308 that couples SSD 306 to a host (e.g., host 108 in FIG. 1 ).
  • the storage capacity and/or operating speed of SSD 306 is greater than the storage capacity and/or operating speed of memory card 202.
  • the host 108 can provide power to the storage system 102.
  • the host 108 can include a PMU (Power Management Unit) 402.
  • the PMU 402 can provide power to the storage system 104 and the storage controller 106 respectively.
  • the voltage provided is Vcc and the current is Icc.
  • the voltage provided by PMU402 to storage controller 106 is Vccq and the current is Iccq.
  • the maximum power that PMU402 supplies to memory 104 is called peak power.
  • storage system 102 requires that the power it needs does not exceed the peak power supported by the host (or PMU).
  • the peak powers supported by the hosts 108 provided by different host manufacturers are not uniform, so the storage manufacturer generally limits the operating power of the storage system 102 to below the peak power supported by most hosts 108 on the market in order to improve the adaptability of the storage system 102.
  • the peak power can be represented by the corresponding peak current.
  • the storage manufacturer can limit the operating power of the storage system 102 to below 800mA.
  • the operating power of the storage system 102 is directly related to the storage performance of the storage system 102, and the limitation of the operating power is also achieved by limiting the storage performance of the storage system 102. For example, by limiting the read and write rate of the storage system 102, the operating power of the storage system 102 can be limited. In this way, although the adaptability of the storage system 102 is improved, if the host 108 in the system 100 can support a higher peak power, the storage system 102 cannot fully exert its storage performance.
  • the embodiment of the present application provides a control method for a system, which may be the system 100 shown in FIG1, including a host and a storage system.
  • the storage system can sense the peak power of the host, and then adjust the peak power management strategy according to the sensed peak power, so that the storage performance of the storage system can be fully utilized.
  • Figures 5 and 6 are flow charts of a control method for a system provided in an embodiment of the present application.
  • the host is configured with a first interface
  • the storage controller of the storage system is configured with a second interface.
  • the host and the storage system can be coupled through the first interface and the second interface to realize information exchange.
  • a system control method provided in an embodiment of the present application includes:
  • Step 501 The host sends an identifier indicating the peak power capability supported by the host through a first interface.
  • an identifier indicating the supported peak power capability may be stored in the host, and the host may send the identifier to the second interface of the storage controller through the configured first interface.
  • Step 502 The storage controller receives an identifier through the second interface.
  • Step 503 The storage controller determines a peak power management policy that matches the peak power capability according to the identifier. slightly.
  • the peak power management strategy can be used to control the operating power of the storage system.
  • the peak power management strategy is used to limit the write rate of the memory to achieve the effect of controlling the operating power of the storage system.
  • the second interface configured by the storage controller can determine the peak power management policy corresponding to the received identifier from the correspondence between the stored identifier and the peak power management policy, and then the determined peak power management policy can be used as the peak power management policy adopted during the operation of the storage system.
  • the peak power management strategy corresponding to an identifier matches the peak power capability indicated by the identifier.
  • the identifier "1h” indicates that the peak power supported by the host is 650mA.
  • the peak current that appears in the storage system can be less than and close to (or equal to) 650mA.
  • the identifier "2h” indicates that the peak power supported by the host is 800mA.
  • the peak current that appears in the storage system can be less than and close to (or equal to) 800mA.
  • the host can send the peak power capability supported by the host to the storage system, and the storage controller in the storage system can dynamically match and apply the appropriate peak power management strategy according to the peak power capability supported by the host.
  • the embodiment of the present application avoids the storage system setting a peak power management strategy with low storage performance to match most hosts, and enables the storage system to fully exert storage performance when working with various hosts.
  • the host in the system can send an initialization instruction to the second interface of the storage controller through the first interface.
  • the storage controller can perform an initialization operation and send an RSP (response message) to the host through the second interface.
  • the host initially receives the RSP of the storage system through the first interface, it can send an identifier indicating the peak power capability supported by the host to the storage controller through the first interface.
  • the storage controller receives the identifier indicating the peak power capability supported by the host through the second interface, it can determine and apply the peak power management policy corresponding to the received identifier based on the stored correspondence.
  • the storage controller can also send an RSP to the host again through the second interface. The RSP sent again is used to indicate the identifier sent by the host received by the storage controller.
  • the host can The first interface sends an I/O request to the storage controller.
  • the storage controller After the storage controller receives the I/O request through the second interface, it can control the storage to process the I/O request according to the determined peak power management policy.
  • the storage system can process the I/O request according to the peak power management policy that matches the peak power capability of the host, and can fully exert the storage performance under the premise that the operating power of the storage system does not exceed the peak power of the host.
  • the storage system can flexibly adjust the matching peak power management policy according to the peak power of the host, the storage system provided by the embodiment of the present application has higher adaptability than some implementation methods.
  • the host can supply power to the storage system through the PMU
  • the PMU can be a control chip integrated in the host controller of the host, or a control chip independent of the host controller.
  • the PMU can be a power management integrated circuit (Power Management IC, PMIC) independent of the host controller.
  • the identifier used to indicate the peak power capability supported by the host in the above embodiment can be used to indicate the peak power capability supported by the PMU. Since the operating voltage provided by the PMU to the storage controller and the memory is relatively stable during the operation of the storage system, the current provided by the PMU to the storage controller and the memory can reflect the peak power capability of the PMU. Therefore, the above identifier indicating the peak power capability of the PMU can also be used to indicate the current that the PMU can provide to the storage system according to the supported peak power capability.
  • the peak power management strategy includes at least one parameter for controlling the operation of the storage system.
  • the at least one parameter can be used to control the write rate of the memory in the storage system, thereby achieving control of the operating power of the storage system, so that the operating power of the storage system is less than and close to (or equal to) the peak power supported by the host.
  • Table 1 shows the relationship between the peak power capability supported by the host and the write rate of the memory, wherein the storage unit in the memory can be a triple-level cell (TLC).
  • TLC triple-level cell
  • At least one parameter included in the peak power management strategy may be a clock frequency of the storage system, a parallelism of the flash memory NAND, an operation delay of an I/O request, etc.
  • Frequency refers to the clock frequency used by the storage system during operation. Generally, the higher the clock frequency, the higher the write rate, and the corresponding storage system's operating power consumption is greater.
  • NAND's parallelism refers to the number of NAND units that perform write operations at the same time. Generally, the higher the parallelism, the higher the write rate, and the corresponding storage system's operating power consumption is greater.
  • the operation latency of an I/O request refers to the time interval for the storage controller to process adjacent I/O requests. Generally, the shorter the operation latency, the higher the write rate, and the corresponding storage system's operating power consumption is higher.
  • the specific values of the parameters included in the peak power management strategies corresponding to each identifier can be configured by a technician.
  • the write rate required to meet the peak power capability can be used as the input of the configuration algorithm, and the configuration algorithm outputs the specific values of the above-mentioned parameters.
  • the specific processing of the configuration algorithm belongs to the prior art and will not be described in detail in the embodiments of this application.
  • the storage controller can determine the peak power management strategy corresponding to the received identifier in the pre-stored correspondence, and then set the value of the parameter running the storage system to the value of the parameter included in the peak power management strategy. In this way, the write rate of the memory can be adjusted according to the peak power capability supported by the host, so that the storage performance of the memory can be fully utilized, and the operating power of the storage system does not exceed the peak power supported by the host.
  • the operating power of the storage system can be controlled by controlling the write rate.
  • it is not limited to controlling the operating power of the storage system only by controlling the write rate.
  • the erase rate and read rate of the memory can be controlled by adjusting the above parameters, thereby further controlling the operating power of the storage system.
  • the storage system provided in the embodiment of the present application may be a UFS storage system.
  • the host and the storage system may communicate according to the UFS protocol. Accordingly, the first interface of the host and the second interface of the storage controller may both be UFS interfaces.
  • the memory in the UFS storage system may be referred to as the UFS memory
  • the storage controller in the UFS storage system may be referred to as the UFS storage controller.
  • the PMU may power the UFS memory and the UFS storage controller respectively.
  • the voltage provided by the PMU to the UFS memory is Vcc and the current is Icc
  • the voltage provided by the PMU to the UFS storage controller is Vccq and the current is Iccq. Since the Vcc and Vccq provided by the PMU to the UFS storage system are relatively stable, the peak power capability of the host is
  • the identifiers can be divided into the sizes of Icc and Iccq respectively indicating the peak power capability provided by the host to the UFS storage system.
  • the identifier can be carried in the UFS data packet.
  • the identifier can be further added to the extension field of the UFS data packet.
  • Table 2 shows information added to the extension field of Icc and Iccq in a UFS data packet.
  • Size indicates the number of bits occupied by the identifier indicating the size of Iccq or Icc in the extended field.
  • Name indicates the name of the bits occupied by the identifier in the extended field.
  • Value indicates the numerical type of the identifier. As shown in Table 2, the above identifier can be a hexadecimal value.
  • User Conf indicates that the extended field needs to be pre-configured by a technician.
  • Delivery shows the host peak power capability indicated by the identifier corresponding to Iccq or Icc when it takes different values.
  • the host when the host sends a UFS data packet to the UFS storage controller, it may only carry the identifier corresponding to Icc. Correspondingly, in the correspondence of the UFS storage controller, the correspondence between different Icc identifiers and peak power management strategies may be stored. In another example, when the host sends a UFS data packet to the UFS storage controller, it may only carry the identifiers corresponding to Icc and Iccq. Correspondingly, in the correspondence of the UFS storage controller, the correspondence between different Icc and Iccq identifiers and peak power management strategies may be stored.
  • a default peak power management policy is set in the storage controller.
  • the default peak power management policy can control the operating power of the storage system to meet the peak power capabilities supported by most hosts on the market.
  • the default peak power management policy can control the operating power of the storage system to meet the peak power capabilities supported by more than a preset number of hosts.
  • the storage controller can still control the operation of the storage system with the default peak power management policy.
  • the storage controller even if the storage controller does not have the ability to match the peak power management policy according to the identifier sent by the host, The host sends an identifier to the storage controller without affecting the normal operation of the storage controller.
  • the embodiment of the present application further provides a host, which may be the host shown in Figures 1, 4 to 6.
  • the host is configured with a first interface, and the host is coupled to a second interface of a storage controller in a storage system through the first interface to implement information exchange.
  • the host is configured to send an identifier to the second interface of the storage controller through the first interface, the identifier being used to indicate the peak power capability supported by the host, and to receive a response message sent by the storage controller through the first interface, the response message being used to indicate that the storage controller has received the identifier.
  • the host includes a power management unit, which is used to supply power to the storage system, and the identifier is used to indicate a peak power capability supported by the power management unit.
  • the identifier is used to indicate the magnitude of current that the power management unit can provide to the storage system according to the supported peak power capability.
  • the current that the power management unit can provide to the storage system according to the supported peak power capability includes Icc and/or Iccq.
  • the host is further configured to send an I/O request to the second interface of the storage controller through the first interface.
  • the storage system is a UFS storage system
  • the first interface is a UFS interface
  • the identifier is carried in an extension field of a UFS data packet.
  • the power management unit is a power management chip PMIC.
  • the host provided in the embodiment of the present application can execute the method steps performed by the host in the control method provided in the embodiment of the present application. For details, please refer to the contents of the above embodiments, which will not be repeated here.
  • the host provided in the embodiment of the present application can actively send the peak power capacity supported by the host to the storage system, so that the storage system can adjust the peak power management strategy of the storage system according to the peak power capacity supported by the host, so as to give full play to the storage performance of the storage system.
  • the embodiment of the present application also provides a storage system, which may be the storage system shown in Figures 1 to 4.
  • the storage system includes a storage controller and a memory, the storage controller is configured with a second interface, and the storage controller is coupled to the first interface of the host through the second interface to achieve information exchange.
  • the storage controller is configured to receive, through the second interface, an identifier sent by the host through the first interface and used to indicate the peak power capability supported by the host, and determine a peak power management strategy according to the identifier;
  • the memory controller is configured to control the memory to process I/O requests according to the determined peak power management policy.
  • a default peak power management policy is set in the storage controller
  • the storage controller is configured to replace a default peak power management policy with the determined peak power management policy after determining the peak power management policy.
  • the peak power management policy includes parameters for controlling the operation of the storage system.
  • the parameter includes at least one of a clock frequency, a parallelism of the flash memory NAND, and an operation delay of an I/O request.
  • the storage system is a flash universal storage UFS storage system
  • the second interface is a UFS interface
  • the identifier is carried in an extension field of the UFS data packet.
  • the storage controller is further configured to send a response message through the second interface after receiving the identifier, where the response message is used to indicate that the storage controller has received the identifier.
  • the storage system provided in the embodiment of the present application can execute the method steps performed by the storage system in the control method provided in the embodiment of the present application. For details, please refer to the contents of the above embodiment, which will not be repeated here.
  • the storage system provided in the embodiment of the present application can receive an identifier indicating the peak power capability of the host, and then determine and apply the peak power management strategy of the storage system based on the identifier, so as to give full play to the storage performance of the storage system.
  • the embodiment of the present application further provides a system, which may be the system 100 shown in FIG. 1 above, comprising a host and a storage system, wherein the host is configured with a first interface, the storage system comprises a storage controller, the storage controller is configured with a second interface, and the host and the storage system are coupled through the first interface and the second interface to implement information exchange; wherein,
  • the host is configured to send, through the first interface, an identifier indicating a peak power capability supported by the host.
  • the storage controller is configured to receive the identifier through the second interface and determine the peak power management strategy according to the identifier.
  • the host includes a power management unit, which is used to supply power to the storage system, and the identifier is used to indicate a peak power capability supported by the power management unit.
  • the identifier is used to indicate the magnitude of current that the power management unit can provide to the storage system according to the supported peak power capability.
  • the power management unit can provide power to the storage system according to the supported peak power capability.
  • the flow includes Icc and/or Iccq.
  • a default peak power management policy is set in the storage controller.
  • the storage controller is configured to replace the default peak power management policy with the determined peak power management policy after determining the peak power management policy.
  • the peak power management policy includes parameters for controlling the operation of the storage system.
  • the parameter includes at least one of a clock frequency, a parallelism of the flash memory NAND, and an operation delay of an I/O request.
  • the storage system is a universal flash storage UFS storage system
  • the first interface and the second interface are UFS interfaces.
  • the identifier is carried in an extension field of the UFS data packet.
  • the storage controller is further configured to send a response message through the second interface after receiving the identifier, the response message being used to indicate that the storage controller has received the identifier.
  • the host is further configured to receive the response message through the first interface.
  • the host is further configured to send an I/O request through the first interface.
  • the storage controller is further configured to receive the I/O request through the second interface, and control the storage to process the I/O request according to the determined peak power management policy.
  • the system including a host and a storage system provided in the embodiment of the present application can implement the control method of the system in the above embodiment.
  • the host can send an identifier corresponding to the supported peak power capability to the storage controller.
  • the storage controller can determine the peak power management policy that matches the peak power capability of the host based on the received identifier, and then process the I/O request according to the determined peak power management policy. In this way, the storage controller can adjust the peak power management policy according to the peak power capability of the host, without limiting the storage performance of the storage system in advance, so that the performance of the storage system can be fully utilized.
  • the MLC can be programmed from an erased state to present one of three possible storage states by writing one of the three possible nominal storage values into the cell, and a fourth nominal storage value can be used for the erased state.
  • each NAND memory string 708 may include a source select gate (SSG) 710 at its source end and a drain select gate (DSG) 712 at its drain end.
  • the SSG 710 and the DSG 712 may be configured to activate a selected NAND memory string 708 (column of the array) during read and program processes.
  • the sources of the NAND memory strings 708 in the same block 704 are coupled by the same source line (SL) 714 (e.g., a common SL).
  • SL source line
  • all NAND memory strings 708 in the same block 704 have an array common source (ACS).
  • each NAND storage string 708 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having DSG 712) or a deselect voltage (e.g., 0 V) to a corresponding DSG 712 via one or more DSG lines 713 and/or by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having SSG 710) or a deselect voltage (e.g., 0 V) to a corresponding SSG 710 via one or more SSG lines 715.
  • a selection voltage e.g., higher than the threshold voltage of a transistor having DSG 712
  • a deselect voltage e.g., 0 V
  • a memory cell array device 701 includes a plurality of blocks 704, each block 704 includes a plurality of NAND memory strings 708, and each of the plurality of blocks 704 may have a common source line 714 (eg, a coupling 704a) and the unselected blocks 704b in the same plane as the selected block 704a.
  • the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of blocks or any suitable fraction of blocks.
  • the memory cells 706 of adjacent NAND memory strings 708 can be coupled by word lines 718, which select which row of memory cells 706 is affected by the read and program processes.
  • each word line 718 is coupled to a plurality of memory cells 706.
  • Each word line 718 may include a plurality of control gates (gate electrodes) at each memory cell 706 in a corresponding page 720 and a gate line coupling the control gates.
  • a peak power management strategy that matches the peak power capabilities supported by different hosts can be set according to the specific type of storage units included in the memory, so that the power of the memory during operation does not exceed the peak power of the power supply host.
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance.
  • the term “at least one” means one or more, and the term “plurality” means two or more, unless otherwise clearly defined.

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Abstract

本申请公开了一种主机、系统及控制方法，属于存储技术领域。其中，系统包括主机和存储系统，主机通过配置第一接口向存储系统的存储控制器发送用于指示主机所支持的峰值功率能力的标识。存储控制器通过第二接口接收到标识后，根据标识确定峰值功率管理策略，并根据确定的峰值功率管理策略处理I/O请求。采用本申请，存储系统的存储控制器能够感知主机支持的峰值功率能力，然后可以根据感知峰值功率能力，确定的峰值功率管理策略，能够使得存储系统的存储性能得到充分的发挥。

Description

主机、系统及控制方法 技术领域
本申请涉及存储技术领域，特别涉及一种主机、系统及控制方法。
背景技术
一些设备(如手机、平板电脑)对应的硬件系统中可以包括主机和存储系统。其中，主机可以为存储系统供电，且供电的最大功率可称为峰值功率。
为了保证电源管理单元和存储系统的正常工作，一般要求存储系统的运行功率不超出主机支持的峰值功率。
但市面上的主机所支持的峰值功率并不统一，所以存储厂商一般会限制存储系统的运行功率，以使其提供的存储系统能够适配市面上更多的主机。
发明内容
本申请实施例提供了一种主机、系统及控制方法，系统包括的存储系统能感知主机支持的峰值功率能力，能够根据感知峰值功率能力，确定合适的峰值功率管理策略，可以使得存储系统的存储性能得到充分的发挥。所述技术方案如下：
第一方面，提供了一种系统，包括主机和存储系统，主机被配置有第一接口，存储系统包括存储控制器，存储控制器被配置有第二接口，主机和存储系统通过第一接口和第二接口耦接并实现信息交互。其中，
主机被配置为通过第一接口发送用于指示主机所支持的峰值功率能力的标识。存储控制器被配置为通过第二接口接收标识，根据接收的标识确定峰值功率管理策略。
可选地，主机包括电源管理单元，电源管理单元用于向存储系统供电，上述标识用于指示电源管理单元所支持的峰值功率能力。
可选地，上述标识用于指示电源管理单元按照支持的峰值功率能力能够向存储系统提供电流的大小。
可选地，电源管理单元按照支持的峰值功率能力能够向存储系统提供的电流包括Icc和/或Iccq。
可选地，存储控制器中设置有默认的峰值功率管理策略。存储控制器被配置为在确定峰值功率管理策略后，将默认的峰值功率管理策略替换为确定的峰值功率管理策略。
可选地，峰值功率管理策略包括控制存储系统运行的参数。
可选地，峰值功率管理策略中的参数包括时钟频率、闪存存储器NAND的平行度、I/O请求的操作时延中的至少一个。
可选地，存储系统为闪存通用存储UFS存储系统，第一接口和第二接口为UFS接口。
可选地，上述标识被携带在UFS数据包的扩展字段中。
可选地，电源管理单元为电源管理芯片PMIC。
可选地，存储控制器还被配置为在接收到标识后，通过第二接口发送响应消息，该响应消息用于指示存储控制器已收到标识。主机还被配置为通过第一接口接收该响应消息。
可选地，主机还被配置为通过第一接口发送I/O请求。存储控制器还被配置为通过第二接口接收I/O请求，并根据确定的峰值功率管理策略控制存储器处理I/O请求。
第二方面，提供了一种主机，主机被配置有第一接口，主机通过第一接口与存储系统中存储控制器的第二接口耦接并实现信息交互。
主机被配置为通过第一接口向存储控制器的第二接口发送标识，该标识用于指示主机所支持的峰值功率能力，并通过第一接口接收存储控制器发送的响应消息，响应消息用于指示存储控制器已收到标识。
可选地，主机包括电源管理单元，电源管理单元用于向存储系统供电，上述标识用于指示电源管理单元所支持的峰值功率能力。
可选地，上述标识用于指示电源管理单元按照支持的峰值功率能力能够向存储系统提供电流的大小。
可选地，电源管理单元按照支持的峰值功率能力能够向存储系统提供的电流包括Icc和/或Iccq。
可选地，主机还被配置为通过第一接口向存储控制器的第二接口发送I/O请 求。
可选地，存储系统为闪存通用存储UFS存储系统，第一接口为UFS接口，标识携带在UFS数据包的扩展字段中。
可选地，电源管理单元为电源管理芯片PMIC。
第三方面，提供了一种存储系统，存储系统包括存储控制器和存储器，存储控制器被配置有第二接口，存储控制器通过第二接口与主机的第一接口耦接并实现信息交互。
存储控制器被配置为通过第二接口接收主机通过第一接口发送的用于指示主机所支持的峰值功率能力的标识，根据标识确定峰值功率管理策略。
存储控制器被配置为根据确定的峰值功率管理策略控制存储器处理I/O请求。
可选地，存储控制器中设置有默认的峰值功率管理策略。存储控制器被配置为在确定峰值功率管理策略后，将默认的峰值功率管理策略替换为确定的峰值功率管理策略。
可选地，峰值功率管理策略包括控制存储系统运行的参数。
可选地，参数包括时钟频率、闪存存储器NAND的平行度、I/O请求的操作时延中的至少一个。
可选地，存储系统为闪存通用存储UFS存储系统，第二接口为UFS接口，标识携带在UFS数据包的扩展字段中。
可选地，存储控制器还被配置为在接收到上述标识后，通过第二接口发送响应消息，响应消息用于指示存储控制器已收到标识。
第四方面，提供了一种系统的控制方法，系统包括主机和存储系统，主机被配置有第一接口，存储系统包括存储控制器，存储控制器被配置有第二接口，主机和存储系统通过第一接口和第二接口耦接并实现信息交互，该控制方法包括：主机通过第一接口发送用于指示主机所支持的峰值功率能力的标识。存储控制器通过第二接口接收标识，根据标识确定与峰值功率能力匹配的峰值功率管理策略。
可选地，主机包括电源管理单元，电源管理单元用于向存储系统供电，标识用于指示电源管理单元所支持的峰值功率能力。
可选地，标识用于指示电源管理单元按照支持的峰值功率能力能够向存储 系统提供电流的大小。
可选地，电源管理单元按照支持的峰值功率能力能够向存储系统提供的电流包括Icc和/或Iccq。
可选地，存储控制器中设置有默认的峰值功率管理策略。上述控制方法还包括：存储控制器在确定峰值功率管理策略后，将默认的峰值功率管理策略替换为确定的峰值功率管理策略。
可选地，峰值功率管理策略包括控制存储系统运行的参数。
可选地，参数包括时钟频率、闪存存储器NAND的平行度、I/O请求的操作时延中的至少一个。
可选地，存储系统为闪存通用存储UFS存储系统，第一接口和第二接口为UFS接口。
可选地，标识被携带在UFS数据包的扩展字段中。
可选地，电源管理单元为电源管理芯片PMIC。
可选地，上述控制方法还包括：存储控制器在接收到标识后，通过第二接口发送响应消息，响应消息用于指示存储控制器已收到标识。主机通过第一接口接收响应消息。
可选地，上述控制方法还包括：主机通过第一接口发送I/O请求。存储控制器通过第二接口接收I/O请求，并根据确定的峰值功率管理策略控制存储器处理I/O请求。
本申请实施例提供的技术方案带来的有益效果是：
在本申请实施例中，主机与存储系统的存储控制器通过接口建立信息交互后，主机可以将所支持的峰值功率能力对应的标识发送至存储控制器。存储控制器可以根据接收到的标识，确定与主机的峰值功率能力匹配峰值功率管理策略，然后根据确定的峰值功率管理策略处理I/O请求。这样，存储控制器可以根据主机的峰值功率能力调整峰值功率管理策略，无需提前限制存储系统的存储性能，能够使存储系统的性能得到充分的发挥。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请 的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种示例性系统的示意图；
图2是本申请实施例提供的一种示例性存储器卡的示图；
图3是本申请实施例提供的一种示例性固态驱动器的示意图；
图4是本申请实施例提供的一种示例性系统的示意图；
图5是本申请实施例提供的一种示例性系统的控制方法的流程图；
图6是本申请实施例提供的一种示例性系统的控制方法的流程图；
图7是本申请实施例提供的一种示例性存储器的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
图1示出了根据本公开的一些方面的具有存储系统的示例性系统100的块图。系统100可以是移动电话、台式计算机、膝上型计算机、平板计算机、车辆计算机、游戏控制台、打印机、定位设备、可穿戴电子设备、智能传感器、虚拟现实(VR)设备、增强现实(AR)设备或者其中具有存储器器件的任何其他合适的电子设备。如图1中所示，该系统100可以包括主机108和存储系统102，存储系统102具有一个或多个存储器104和存储控制器106。主机(host)108可以是电子设备的处理器(例如，中央处理单元(CPU))或者片上系统(SoC)(例如，应用处理器(AP))。主机108可以被配置为将数据发送到存储器104或从存储器104接收数据。
存储器104可以是本公开中公开的任何存储器器件。可选地，存储器104为与非门闪存(NAND flash)存储器器件，例如三维(3D)NAND闪存存储器器件。
在一些实施方式中，存储控制器106耦合到存储器104和主机108，并且被配置为控制存储器104。存储控制器106可以管理存储在存储器104中的数据，并且与主机108通信。在一些实施方式中，存储控制器106被设计为用于在低占空比环境中操作，如安全数字(SD)卡、紧凑型闪存(CF)卡、通用串行总线(USB)闪存驱动器、或用于在诸如个人计算器、数字相机、移动电话等的 电子设备中使用的其他介质。在一些实施方式中，存储控制器106被设计为用于在高占空比环境SSD或嵌入式多媒体卡(eMMC)中操作，SSD或eMMC用作诸如智能电话、平板计算机、膝上型计算机等的移动设备的数据储存器以及企业存储阵列。存储控制器106可以被配置为控制存储器104的操作，例如读取、擦除和编程处理。存储控制器106还可以被配置为管理关于存储在或要存储在存储器104中的数据的各种功能，包括但不限于坏块管理、垃圾收集、逻辑到物理地址转换、损耗均衡等。在一些实施方式中，存储控制器106还被配置为处理关于从存储器104读取的或者被写入到存储器104的数据的纠错码(ECC)。存储控制器106还可以执行任何其他合适的功能，例如，格式化存储器104。存储控制器106可以根据特定通信协议与外部设备(例如，主机108)通信。例如，存储控制器106可以通过各种接口协议中的至少一种与外部设备通信，接口协议例如USB协议、MMC协议、外围部件互连(PCI)协议、PCI高速(PCI-E)协议、高级技术附件(ATA)协议、串行ATA协议、并行ATA协议、小型计算机小型接口(SCSI)协议、增强型小型磁盘接口(ESDI)协议、集成驱动电子设备(IDE)协议、Firewire协议等。
存储控制器106和一个或多个存储器104可以集成到各种类型的存储设备中，例如，包括在相同封装(例如，通用闪存存储(UFS)封装或eMMC封装)中。也就是说，存储系统102可以实施并且封装到不同类型的终端电子产品中。在如图2中所示的一个示例中，存储控制器106和单个存储器104可以集成到存储器卡202中。存储器卡202可以包括PC卡(PCMCIA，个人计算机存储器卡国际协会)、CF卡、智能媒体(SM)卡、存储器棒、多媒体卡(MMC、RS-MMC、MMCmicro)、SD卡(SD、miniSD、microSD、SDHC)、UFS等。存储器卡202还可以包括将存储器卡202与主机(例如，图1中的主机108)耦合的存储器卡连接器204。在如图3中所示的另一示例中，存储控制器106和多个存储器104可以集成到SSD 306中。SSD 306还可以包括将SSD 306与主机(例如，图1中的主机108)耦合的SSD连接器308。在一些实施方式中，SSD 306的存储容量和/或操作速度大于存储器卡202的存储容量和/或操作速度。
系统100中主机108可以为存储系统102供电。如图4所示的一个示例中，主机108可以包括PMU(Power Management Unit，电源管理单元)402。PMU402可以分别为存储器104和存储控制器106供电。其中，PMU402向存储器104 提供的电压为Vcc、电流为Icc，PMU402向存储控制器106提供的电压为Vccq、电流为Iccq。PMU402向存储器104供电的功率最大值可称为峰值功率(peak power)。存储系统102在运行过程中，要求其所需的功率不超过主机(或PMU)所支持的峰值功率。
在一些实施方式中，不同主机厂商提供的主机108支持的峰值功率并不统一，所以存储厂商一般为了提高存储系统102的适配性，一般会将存储系统102的运行功率限制在市面上大多数主机108支持的峰值功率以下。在一种示例中，峰值功率可通过对应的峰值电流表示，对于市面上主机108支持的峰值功率可包括800mA、1A、1.2A，则存储厂商可以将存储系统102的运行功率限制在800mA以下。
存储系统102的运行功率与存储系统102的存储性能有着直接关系，对运行功率的限制也是通过限制存储系统102的存储性能实现的，如通过限制存储系统102的读写速率，可以实现对存储系统102运行功率的限制。如此，虽然提高了存储系统102的适配性，但如果系统100中的主机108能够支持更高的峰值功率，则存储系统102无法充分的发挥出存储性能。
本申请实施例提供了一种系统的控制方法，该系统可以是上述图1所示的系统100，包括主机和存储系统。在该系统中，存储系统能够感知主机峰值功率，然后根据感知的峰值功率，调整峰值功率管理策略，使得存储系统的存储性能得到充分发挥。
图5和图6是本申请实施例提供的一种系统的控制方法的流程图，如图5或图6所示，本申请实施例提供的系统中，在主机被配置有第一接口，存储系统的存储控制器被配置有第二接口，主机和存储系统可以通过第一接口和第二接口耦接并实现信息交互。
参见图5，本申请实施例提供的一种系统的控制方法包括：
步骤501、主机通过第一接口发送用于指示主机所支持的峰值功率能力的标识。
在实施中，主机中可以存储有指示所支持的峰值功率能力的标识，主机可以通过配置的第一接口将该标识发送至存储控制器的第二接口。
步骤502、存储控制器通过第二接口接收标识。
步骤503、存储控制器根据标识确定与峰值功率能力匹配的峰值功率管理策 略。
其中，峰值功率管理策略可用于控制存储系统的运行功率。在一示例中，峰值功率管理策略用于限制存储器的写速率，以达到控制存储系统的运行功率的效果。
在实施中，存储控制器配置的第二接口在接收到的主机发送的标识后，可以在存储的标识与峰值功率管理策略的对应关系中，确定接收到的标识对应的峰值功率管理策略，然后可以将确定的峰值功率管理策略作为存储系统运行过程中采用的峰值功率管理策略。
在上述对应关系中，一个标识对应的峰值功率管理策略与该标识所指示的峰值功率能力相匹配。例如，标识“1h”表示主机支持的峰值功率为650mA，则存储系统在应用该“1h”对应的峰值功率管理策略的过程中，出现的峰值电流可以小于且接近(或等于)650mA。标识“2h”表示主机支持的峰值功率为800mA，则存储系统在应用该“2h”对应的峰值功率管理策略的过程中，出现的峰值电流可以小于且接近(或等于)800mA。
在本申请实施例提供的系统的控制方法，主机可以向存储系统发送主机支持的峰值功率能力，存储系统中的存储控制器可以根据主机支持的峰值功率能力，动态匹配并应用合适的峰值功率管理策略。本申请实施例避免了存储系统为匹配大多数的主机设置存储性能较低的峰值功率管理策略，能够使得存储系统在与各种主机配合工作的情况下，充分的发挥存储性能。
如图6所示，系统中的主机可以在上电之后，通过第一接口向存储控制器的第二接口发送初始化指令。存储控制器在接收到初始化指令之后，可以进行初始化操作，并通过第二接口向主机发送的RSP(应答消息)。主机通过第一接口初次接收到存储系统的RSP后，可以再通过第一接口向存储控制器发送用于指示主机所支持的峰值功率能力的标识。存储控制器通过第二接口接收到指示主机所支持的峰值功率能力的标识后，可以根据存储的对应关系，确定并应用接收到的标识对应的峰值功率管理策略。存储控制器在接收到该标识后，还可以再次通过第二接口向主机发送的RSP，该再次发送的RSP用于指示存储控制器接收到的主机发送的标识。
继续参见图6，主机通过第一接口第二次接收到存储控制器发送的RSP后，且在主机中存在待处理的I/O(Input/Output，输入输出)请求时，主机可以通过 第一接口向存储控制器发送I/O请求。存储控制器在通过第二接口I/O请求后，可以根据确定的峰值功率管理策略控制存储器处理I/O请求。这样，存储系统能够根据与主机的峰值功率能力匹配的峰值功率管理策略来处理I/O请求，能够使得存储系统的运行功率不超出主机的峰值功率的前提下，充分的发挥存储性能。且由于存储系统能够灵活的根据主机的峰值功率调整匹配的峰值功率管理策略，因此本申请实施例提供的存储系统相对于一些实施方式具有更高的适配性。
在图4所示系统中，主机可以通过PMU向存储系统供电，该PMU可以集成在主机的主机控制器中的控制芯片，也可以是独立于主机控制器的控制芯片。在一示例中，PMU可以是独立于主机控制器的电源管理集成电路(Power Management IC，PMIC)。相应的，上述实施例中用于指示主机所支持的峰值功率能力的标识，可以用于指示PMU所支持的峰值功率能力。由于存储系统在运行过程中，PMU向存储控制器和存储器提供的工作电压相对稳定，因此PMU向存储控制器和存储器提供的电流大小，可以反映出PMU的峰值功率能力。所以上述指示PMU峰值功率能力的标识还可用于指示PMU按照支持的峰值功率能力能够向存储系统提供电流的大小。
在一示例中，上述峰值功率管理策略包括控制存储系统运行的至少一个参数。该至少一个参数可用于控制存储系统中存储器的写速率，进而实现对存储系统运行功率的控制，使得存储系统的运行功率小于且接近(或等于)主机支持的峰值功率。表一示出了主机支持的峰值功率能力与存储器的写速率的关系，其中，该存储器中的存储单元可以为三级单元(TLC)。
表一
如表一所示，在主机支持的峰值功率的能力为800mA时，可以通过峰值功率管理策略中的参数，将存储器的写速率控制在650MB/s，进而可以使得存储系统的运行功率不超过主机支持的峰值功率。
在一示例中，峰值功率管理策略中包括的至少一个参数可以为存储系统的时钟频率、闪存存储器NAND的平行度、I/O请求的操作时延等。其中，时钟 频率是指存储系统在运行过程中采用的时钟频率，一般时钟频率越高，写速率就越高，对应的存储系统的运行功耗就越大。NAND的平行度是指同时进行写操作的NAND单元的数目，一般平行度越高，写速率就越高，对应的存储系统的运行功耗就越大。I/O请求的操作时延是指存储控制器的处理相邻的I/O请求的时间间隔，一般操作时延越短，写速率就越高，对应的存储系统的运行功耗就越高。
在上述标识与峰值功率管理策略的对应关系中，每个标识对应的峰值功率管理策略中所包括参数的具体数值可以由技术人员进行配置。例如可以将满足峰值功率能力所需要限制的写速率作为配置算法的输入，由配置算法输出上述各个参数的具体数值。其中，对于配置算法的具体处理属于现有技术，本申请实施例中不再进行详细介绍。
在实施中，存储控制器中在接收到主机发送的指示峰值功率能力的标识后，可以在预先存储的对应关系中，确定接收到的标识对应的峰值功率管理策略，然后将存储系统运行的参数的数值，设置为峰值功率管理策略包括的参数的数值。如此，可以实现根据主机支持的峰值功率能力，调整存储器的写速率，进而使得存储器的存储性能可以充分发挥，且存储系统的运行功率不超出主机支持的峰值功率。
由于在存储器在进行写操作时，对应的功耗较大，因此通过控制写速率便可以实现对存储系统运行功率的控制。但在本申请实施例中不限制于仅通过对写速率进行控制实现对存储系统运行功率的控制。同样，本申请实施例中还可以通过对上述参数进行调整，实现对存储器的擦除速率、读速率的控制，进而实现对存储系统运行功率的进一步控制。
在一示例中，本申请实施例提供的存储系统可以是UFS存储系统。主机和存储系统之间可以根据UFS协议进行通信。相应的，上述主机的第一接口以及存储控制器的第二接口可以均UFS接口。
在本申请实施例中，对于UFS存储系统中存储器可称为UFS存储器，对于UFS存储系统中存储控制器可称为UFS存储控制器。PMU可以分别为UFS存储器和UFS存储控制器供电。其中，PMU向UFS存储器提供的电压为Vcc、电流为Icc，PMU向UFS存储控制器提供的电压为Vccq、电流为Iccq。由于PMU向UFS存储系统提供的Vcc和Vccq比较稳定。因此用于主机峰值功率能力的 标识可分为别表示主机以峰值功率能力向UFS存储系统分别提供Icc和Iccq的大小。
其中，主机通过UFS接口向UFS存储控制器发送用于指示Icc和Iccq大小的标识时，可以将该标识携带在UFS数据包中。进一步可以将标识添加在UFS数据包的扩展字段中。表二示出了一种Icc和Iccq在UFS数据包扩展字段中的添加的信息。
表二
其中，“Size”表示指示Iccq或Icc大小的标识在扩展字段中占用的比特位的数目。“Name”表示标识在扩展字段中占用的比特位的名称。“Value”表示标识的数值类型，如表二所示，上述标识可以是十六进制的数值。“User Conf.”表示扩展字段需要经过技术人员预先配置。“Description”示出了Iccq或Icc对应的标识在不同的取值时所指示的主机峰值功率能力。
在一种示例中，主机向UFS存储控制器发送的UFS数据包时，可以仅携带Icc对应的标识。对应的，UFS存储控制器的对应关系中，可以存储不同的Icc的标识与峰值功率管理策略的对应关系。在另一种示例中，主机向UFS存储控制器发送的UFS数据包时，可以仅携带Icc以及Iccq对应的标识。对应的，UFS存储控制器的对应关系中，可以存储不同的Icc以及Iccq的两个标识与峰值功率管理策略的对应关系。
在一示例中，存储控制器中设置有默认的峰值功率管理策略。该默认的峰值功率管理策略能够控制存储系统的运行功率满足的市面上多数的主机支持的峰值功率能力。例如默认的峰值功率管理策略能够控制存储系统的运行功率满足的大于预设数目种主机支持的峰值功率能力。
这样，一方面，即使主机不具备向存储控制器发送指示峰值功率能力的标识的能力，存储控制器也能够以默认的峰值功率管理策略能够控制存储系统的运行。另一方面，即使存储控制器不具备根据主机发送的标识匹配峰值功率管 理策略的能力，主机向存储控制器发送标识，也不会对存储控制器的正常运行产生影响。
本申请实施例还提供了一种主机，该主机可以是上述图1、图4至图6中所示的主机。该主机被配置有第一接口，主机通过第一接口与存储系统中存储控制器的第二接口耦接并实现信息交互。
主机被配置为通过第一接口向存储控制器的第二接口发送标识，标识用于指示主机所支持的峰值功率能力，并通过第一接口接收存储控制器发送的响应消息，响应消息用于指示存储控制器已收到标识。
可选地，主机包括电源管理单元，电源管理单元用于向存储系统供电，标识用于指示电源管理单元所支持的峰值功率能力。
可选地，标识用于指示电源管理单元按照支持的峰值功率能力能够向存储系统提供电流的大小。
可选地，电源管理单元按照支持的峰值功率能力能够向存储系统提供的电流包括Icc和/或Iccq。
可选地，主机还被配置为通过第一接口向存储控制器的第二接口发送I/O请求。
可选地，存储系统为UFS存储系统，第一接口为UFS接口，标识携带在UFS数据包的扩展字段中。
可选地，电源管理单元为电源管理芯片PMIC。
本申请实施例提供的主机，可以执行本申请实施例提供的控制方法中由主机执行的方法步骤，具体可参见上述实施例的内容，此处不在进行赘述。本申请实施例提供的主机，能够主动向存储系统发送该主机支持的峰值功率能力，可以使得存储系统能够根据主机支持的峰值功率能力调整存储系统的峰值功率管理策略，以充分的发挥存储系统的存储性能。
本申请实施例还提供了一种存储系统，该存储系统可以是上述图1至图4所示的存储系统。该存储系统包括存储控制器和存储器，存储控制器被配置有第二接口，存储控制器通过第二接口与主机的第一接口耦接并实现信息交互。
存储控制器被配置为通过第二接口接收主机通过第一接口发送的用于指示主机所支持的峰值功率能力的标识，根据标识确定峰值功率管理策略；
存储控制器被配置为根据确定的峰值功率管理策略控制存储器处理I/O请求。
可选地，存储控制器中设置有默认的峰值功率管理策略；
存储控制器被配置为在确定峰值功率管理策略后，将默认的峰值功率管理策略替换为确定的峰值功率管理策略。
可选地，峰值功率管理策略包括控制存储系统运行的参数。
可选地，参数包括时钟频率、闪存存储器NAND的平行度、I/O请求的操作时延中的至少一个。
可选地，存储系统为闪存通用存储UFS存储系统，第二接口为UFS接口，标识携带在UFS数据包的扩展字段中。
可选地，存储控制器还被配置为在接收到标识后，通过第二接口发送响应消息，响应消息用于指示存储控制器已收到标识。
本申请实施例提供的存储系统，可以执行本申请实施例提供的控制方法中由存储系统执行的方法步骤，具体可参见上述实施例的内容，此处不在进行赘述。本申请实施例提供的存储系统，能够接收指示主机峰值功率能力的标识，然后根据该标识，确定并应用存储系统的峰值功率管理策略，进而可以充分的发挥存储系统的存储性能。
本申请实施例还提供了一种系统，该系统可以是上述图1所示的系统100，该系统包括主机和存储系统，主机被配置有第一接口，存储系统包括存储控制器，存储控制器被配置有第二接口，主机和存储系统通过第一接口和第二接口耦接并实现信息交互；其中，
主机被配置为通过第一接口发送用于指示主机所支持的峰值功率能力的标识。
存储控制器被配置为通过第二接口接收标识，根据标识确定峰值功率管理策略。
可选地，主机包括电源管理单元，电源管理单元用于向存储系统供电，标识用于指示电源管理单元所支持的峰值功率能力。
可选地，标识用于指示电源管理单元按照支持的峰值功率能力能够向存储系统提供电流的大小。
可选地，电源管理单元按照支持的峰值功率能力能够向存储系统提供的电 流包括Icc和/或Iccq。
可选地，存储控制器中设置有默认的峰值功率管理策略。存储控制器被配置为在确定峰值功率管理策略后，将默认的峰值功率管理策略替换为确定的峰值功率管理策略。
可选地，峰值功率管理策略包括控制存储系统运行的参数。
可选地，参数包括时钟频率、闪存存储器NAND的平行度、I/O请求的操作时延中的至少一个。
可选地，存储系统为闪存通用存储UFS存储系统，第一接口和第二接口为UFS接口。
可选地，标识被携带在UFS数据包的扩展字段中。
可选地，电源管理单元为电源管理芯片PMIC。
可选地，存储控制器还被配置为在接收到标识后，通过第二接口发送响应消息，响应消息用于指示存储控制器已收到标识。主机还被配置为通过第一接口接收响应消息。
可选地，主机还被配置为通过第一接口发送I/O请求。存储控制器还被配置为通过第二接口接收I/O请求，并根据确定的峰值功率管理策略控制存储器处理I/O请求。
本申请实施例提供的包括主机和存储系统的系统，能够实现上述实施例中对系统的控制方法，具体可参见上述实施例的内容，此处不在进行赘述。本申请实施例提供的系统中，主机可以将所支持的峰值功率能力对应的标识发送至存储控制器。存储控制器可以根据接收到的标识，确定与主机的峰值功率能力匹配峰值功率管理策略，然后根据确定的峰值功率管理策略处理I/O请求。这样，存储控制器可以根据主机的峰值功率能力调整峰值功率管理策略，无需提前限制存储系统的存储性能，能够使存储系统性能得到充分的发挥。
图7示出了根据本公开的一些方面的包括外围电路的示例性存储器700的示意电路图。该存储器700可以是上述实施例中存储系统中包括的存储器，如可以是图1至图5中所示的存储器。
存储器700可以包括存储单元阵列器件701和耦合到存储单元阵列器件701的外围电路702。存储单元阵列器件701可以是NAND闪存存储单元阵列，其中，存储单元706以NAND存储串708的阵列的形式提供，每个NAND存储串 708在衬底(未示出)上方垂直地延伸。在一些实施方式中，每个NAND存储串708包括串联耦合并且垂直地堆叠的多个存储单元706。每个存储单元706可以保持连续模拟值，例如，电压或电荷，其取决于在存储单元706的区域内捕获的电子的数量。每个存储单元706可以是包括浮栅晶体管的浮栅类型的存储单元，或者是包括电荷捕获晶体管的电荷捕获类型的存储单元。
在一些实施方式中，每个存储单元706是具有两种可能的存储态并且因此可以存储一位数据的单级单元(SLC)。例如，第一存储态“0”可以对应于第一电压范围，并且第二存储态“1”可以对应于第二电压范围。在一些实施方式中，每个存储单元706是能够在多于或等于四个的存储态中存储多于单个位的数据的多级单元(MLC)。例如，MLC可以每单元存储两位，每单元存储三位(又被称为三级单元(TLC))，或者每单元存储四位(又被称为四级单元(QLC))。每个MLC可以被编程为采取可能的标称存储值的范围。在一个示例中，如果每个MLC存储两位数据，则可以通过将三个可能的标称存储值之一写入单元来将MLC从擦除状态编程为呈现三个可能的存储态之一，第四个标称存储值可用于擦除状态。
如图7中所示，每个NAND存储串708可以包括在其源极端处的源极选择栅极(SSG)710和在其漏极端处的漏极选择栅极(DSG)712。SSG710和DSG712可以被配置为在读取和编程处理期间激活选定的NAND存储串708(阵列的列)。在一些实施方式中，同一块704中的NAND存储串708的源极通过同一源极线(SL)714(例如，公共SL)耦合。换句话说，根据一些实施方式，同一块704中的所有NAND存储串708具有阵列公共源极(ACS)。根据一些实施方式，每个NAND存储串708的DSG 712耦合到相应的位线716，可以经由输出总线(未示出)从位线716读取或写入数据。在一些实施方式中，每个NAND存储串708被配置为通过经由一个或多个DSG线713将选择电压(例如，高于具有DSG 712的晶体管的阈值电压)或取消选择电压(例如，0V)施加到相应的DSG 712和/或通过经由一个或多个SSG线715将选择电压(例如，高于具有SSG 710的晶体管的阈值电压)或取消选择电压(例如，0V)施加到相应的SSG710而被选择或被取消选择。
如图7中所示，存储单元阵列器件701包括多个块704，每个块704包括多个NAND存储串708，多个块704的每一个可以具有公共源极线714(例如，耦 合到地)。在一些实施方式中，每个块704是用于擦除操作的基本数据单位，即，同一块704上的所有存储单元706同时被擦除。为了擦除选定块704a中的存储单元706，可以用擦除电压(Vers)(例如，高正电压(例如，20V或更高))偏置耦合到选定块704a以及与选定块704a在同一面中的未选定块704b的源极线714。应当理解，在一些示例中，可以在半块级、在四分之一块级或者在具有任何合适数量的块或块的任何合适的分数的级执行擦除操作。相邻NAND存储串708的存储单元706可以通过字线718耦合，字线718选择存储单元706的哪一行受读取和编程处理的影响。在一些实施方式中，每个字线718耦合到多个存储单元706。每个字线718可以包括在相应页720中的每个存储单元706处的多个控制栅极(栅极电极)以及耦合控制栅极的栅极线。
在本申请实施例中，可以根据存储器中包括的存储单元的具体类型设置与不同主机支持的峰值功率能力匹配的峰值功率管理策略，以使存储器在运行过程中的功率不超出供电主机的峰值功率。
在本申请中，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“至少一个”是指一个或多个，术语“多个”指两个或两个以上，除非另有明确的限定。
以上所述仅为本申请的示例性实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (26)

  1. 一种系统，其特征在于，包括主机和存储系统，所述主机被配置有第一接口，所述存储系统包括存储控制器，所述存储控制器被配置有第二接口，所述主机和所述存储系统通过所述第一接口和所述第二接口耦接并实现信息交互；其中，
    所述主机被配置为通过所述第一接口发送用于指示所述主机所支持的峰值功率能力的标识；
    所述存储控制器被配置为通过所述第二接口接收所述标识，根据所述标识确定峰值功率管理策略。
  2. 根据权利要求1所述的系统，其特征在于，所述主机包括电源管理单元，所述电源管理单元用于向所述存储系统供电，所述标识用于指示所述电源管理单元所支持的峰值功率能力。
  3. 根据权利要求2所述的系统，其特征在于，所述标识用于指示所述电源管理单元按照支持的峰值功率能力能够向所述存储系统提供电流的大小。
  4. 根据权利要求3所述的系统，其特征在于，所述电源管理单元按照支持的峰值功率能力能够向所述存储系统提供的电流包括Icc和/或Iccq。
  5. 根据权利要求1所述的系统，其特征在于，所述存储控制器中设置有默认的峰值功率管理策略；
    所述存储控制器被配置为在确定峰值功率管理策略后，将所述默认的峰值功率管理策略替换为所述确定的峰值功率管理策略。
  6. 根据权利要求1至5任一项所述的系统，其特征在于，所述峰值功率管理策略包括控制所述存储系统运行的参数。
  7. 根据权利要求6所述的系统，其特征在于，所述参数包括时钟频率、闪存存储器NAND的平行度、I/O请求的操作时延中的至少一个。
  8. 根据权利要求1至5任一项所述的系统，其特征在于，所述存储系统为闪存通用存储UFS存储系统，所述第一接口和第二接口为UFS接口。
  9. 根据权利要求8所述的系统，其特征在于，所述标识被携带在所述UFS数据包的扩展字段中。
  10. 根据权利要求2至5任一项所述的系统，其特征在于，所述电源管理单 元为电源管理芯片PMIC。
  11. 根据权利要求1至5任一项所述的系统，其特征在于，所述存储控制器还被配置为在接收到所述标识后，通过所述第二接口发送响应消息，所述响应消息用于指示所述存储控制器已收到所述标识；
    所述主机还被配置为通过所述第一接口接收所述响应消息。
  12. 根据权利要求1至5任一项所述的系统，其特征在于，所述主机还被配置为通过所述第一接口发送I/O请求；
    所述存储控制器还被配置为通过所述第二接口接收所述I/O请求，并根据确定的峰值功率管理策略控制所述存储器处理所述I/O请求。
  13. 一种主机，其特征在于，所述主机被配置有第一接口，所述主机通过所述第一接口与存储系统中存储控制器的第二接口耦接并实现信息交互；
    所述主机被配置为通过所述第一接口向所述存储控制器的第二接口发送标识，所述标识用于指示所述主机所支持的峰值功率能力，并通过所述第一接口接收所述存储控制器发送的响应消息，所述响应消息用于指示所述存储控制器已收到所述标识。
  14. 根据权利要求13所述的主机，其特征在于，所述主机包括电源管理单元，所述电源管理单元用于向所述存储系统供电，所述标识用于指示所述电源管理单元所支持的峰值功率能力。
  15. 根据权利要求14所述的主机，其特征在于，所述标识用于指示所述电源管理单元按照支持的峰值功率能力能够向所述存储系统提供电流的大小。
  16. 根据权利要求15所述的主机，其特征在于，所述电源管理单元按照支持的峰值功率能力能够向所述存储系统提供的电流包括Icc和/或Iccq。
  17. 根据权利要求13至16任一项所述的主机，其特征在于，所述主机还被配置为通过所述第一接口向所述存储控制器的第二接口发送I/O请求。
  18. 根据权利要求13至16任一项所述的主机，其特征在于，所述存储系统为闪存通用存储UFS存储系统，所述第一接口为UFS接口，所述标识携带在UFS数据包的扩展字段中。
  19. 根据权利要求14至16任一项所述的主机，其特征在于，所述电源管理单元为电源管理芯片PMIC。
  20. 一种存储系统，其特征在于，所述存储系统包括存储控制器和存储器，所述存储控制器被配置有第二接口，所述存储控制器通过所述第二接口与主机的第一接口耦接并实现信息交互；
    所述存储控制器被配置为通过所述第二接口接收所述主机通过第一接口发送的用于指示所述主机所支持的峰值功率能力的标识，根据所述标识确定峰值功率管理策略；
    所述存储控制器被配置为根据确定的峰值功率管理策略控制所述存储器处理I/O请求。
  21. 根据权利要求20所述的存储系统，其特征在于，所述存储控制器中设置有默认的峰值功率管理策略；
    所述存储控制器被配置为在确定峰值功率管理策略后，将所述默认的峰值功率管理策略替换为所述确定的峰值功率管理策略。
  22. 根据权利要求20或21所述的存储系统，其特征在于，所述峰值功率管理策略包括控制所述存储系统运行的参数。
  23. 根据权利要求22所述的存储系统，其特征在于，所述参数包括时钟频率、闪存存储器NAND的平行度、I/O请求的操作时延中的至少一个。
  24. 根据权利要求20或21所述的存储系统，其特征在于，所述存储系统为闪存通用存储UFS存储系统，所述第二接口为UFS接口，所述标识携带在UFS数据包的扩展字段中。
  25. 根据权利要求20或21所述的存储系统，其特征在于，所述存储控制器还被配置为在接收到所述标识后，通过所述第二接口发送响应消息，所述响应消息用于指示所述存储控制器已收到所述标识。
  26. 一种系统的控制方法，其特征在于，所述系统包括主机和存储系统，所述主机被配置有第一接口，所述存储系统包括存储控制器，所述存储控制器被配置有第二接口，所述主机和所述存储系统通过所述第一接口和所述第二接口耦接并实现信息交互，所述方法包括：
    所述主机通过所述第一接口发送用于指示所述主机所支持的峰值功率能力的标识；
    所述存储控制器通过所述第二接口接收所述标识；
    所述存储控制器根据所述标识确定与所述峰值功率能力匹配的峰值功率管理策略。
PCT/CN2023/119474 2023-09-18 2023-09-18 主机、系统及控制方法 Pending WO2025059807A1 (zh)

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