WO2025112410A1 - 数据处理方法和装置、电子设备以及存储介质 - Google Patents

数据处理方法和装置、电子设备以及存储介质 Download PDF

Info

Publication number
WO2025112410A1
WO2025112410A1 PCT/CN2024/097159 CN2024097159W WO2025112410A1 WO 2025112410 A1 WO2025112410 A1 WO 2025112410A1 CN 2024097159 W CN2024097159 W CN 2024097159W WO 2025112410 A1 WO2025112410 A1 WO 2025112410A1
Authority
WO
WIPO (PCT)
Prior art keywords
cache
data
response
memory
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/097159
Other languages
English (en)
French (fr)
Inventor
程永波
娄丽芳
曹俊
耿剑波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hygon Information Technology Co Ltd
Original Assignee
Hygon Information Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hygon Information Technology Co Ltd filed Critical Hygon Information Technology Co Ltd
Priority to KR1020257005683A priority Critical patent/KR20250083449A/ko
Priority to EP24837279.9A priority patent/EP4589930A4/en
Priority to JP2025504111A priority patent/JP2026500592A/ja
Publication of WO2025112410A1 publication Critical patent/WO2025112410A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/50—Network services
    • H04L67/56—Provisioning of proxy services
    • H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1829—Arrangements specially adapted for the receiver end
    • H04L1/1861—Physical mapping arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction

Definitions

  • Embodiments of the present disclosure relate to a data processing method, a data processing device, an electronic device, and a storage medium.
  • the Network-on-a-Chip (NOC) system is a necessary bus system for realizing mutual communication between components in large-scale integrated circuits.
  • a system-on-chip (SOC) contains many types of subsystems, such as CPU, GPU, memory, IO devices, etc., and each type of subsystem may have multiple entities that need to communicate with each other (data signals and control signals) to work together.
  • the NOC system provides a high-bandwidth transaction exchange network to connect the components on the chip. Through this network, efficient data transmission can be achieved between the subsystems.
  • the caches corresponding to different subsystems operate on the cached data of the same address, consistency problems will arise. In order to solve this problem, many technologies have emerged to maintain data consistency.
  • At least one embodiment of the present disclosure provides a data processing method, the data processing method comprising: in response to receiving a write request from a first cache to write first data back to a memory, a cache consistency node writes the first data to the memory or discards the first data, wherein the write request carries the first data, the cache consistency node is configured to maintain the consistency of data stored in multiple caches, the multiple caches include the first cache, and after the cache consistency node writes the first data to the memory or discards the first data, the cache consistency node sends a request to the cache consistency node to the memory.
  • the first cache returns a write response signal to directly end the processing operation of the write request.
  • the cache consistency node in response to receiving a write request from the first cache to write the first data back to the memory, the cache consistency node writes the first data to the memory or discards the first data, including: in response to receiving the write request from the first cache to write the first data back to the memory, the cache consistency node determines whether the first cache is the same as the cache that currently exclusively owns the first data recorded on the cache consistency node side; and in response to determining that the first cache is the same as the cache that currently exclusively owns the first data recorded on the cache consistency node side, the cache consistency node writes the first data to the memory.
  • the cache consistency node after the cache consistency node writes the first data to the memory or discards the first data, the cache consistency node returns a write response signal to the first cache to directly end the processing operation of the write request, including: after the cache consistency node writes the first data to the memory, the memory returns a write response to the cache consistency node indicating that the first data has been written to the memory; and in response to receiving the write response from the memory indicating that the first data has been written to the memory, the cache consistency node returns the write response signal to the first cache indicating that the first data has been written back to the memory to directly end the processing operation of the write request.
  • the data processing method also includes: after the cache consistency node writes the first data into the memory, the cache consistency node sets the data state of the first cache to an invalid state, a shared state or an exclusive state, wherein the invalid state indicates that the first cache does not cache the first data, the shared state indicates that the first cache and other caches both cache the first data, and the exclusive state indicates that the first data is cached only in the first cache.
  • the data processing method also includes: in response to receiving a read request for the first data from a second cache and the cache consistency node side recording that the first data is in an exclusive state or a shared state in the first cache, the cache consistency node initiates a monitoring signal to the first cache; in response to the first cache receiving the monitoring signal after issuing the write request, the first cache returns a monitoring response carrying the first data to the cache consistency node in response to the monitoring signal.
  • the data processing The processing method also includes: in response to receiving the monitoring response, the cache consistency node returns the first data to the second cache; and after receiving the first data, the second cache returns a message to the cache consistency node indicating that the first data has been received to end the read request.
  • the cache consistency node in response to receiving the monitoring response, returns the first data to the second cache, including: in response to receiving the monitoring response, the cache consistency node returns the first data to the second cache, and sets the data state of the second cache to an exclusive state, wherein the exclusive state indicates that the first data is cached only in the second cache.
  • the cache consistency node after the cache consistency node writes the first data into the memory or discards the first data, the cache consistency node returns a write response signal to the first cache to directly end the processing operation of the write request, including: after receiving the message, the cache consistency node discards the first data written by the write request on the cache consistency node side, and returns the write response signal to the first cache to directly end the processing operation of the write request.
  • the cache consistency node after receiving the message, discards the first data written by the write request to the cache consistency node side, including: in response to determining that the first data written by the write request to the cache consistency node side is invalid data after receiving the message, the cache consistency node discards the first data written by the write request to the cache consistency node side.
  • At least one embodiment of the present disclosure also provides an electronic device, comprising multiple caches and cache consistency nodes, the multiple caches including a first cache, and the cache consistency node is configured to write the first data to the memory or discard the first data in response to receiving a write request from the first cache to write the first data back to the memory, and after the cache consistency node writes the first data to the memory or discards the first data, return a write response signal to the first cache to directly end the processing operation of the write request, wherein the write request carries the first data, and the cache consistency node is configured to maintain the consistency of the data stored in the multiple caches.
  • the cache consistency node is further configured to: in response to receiving the write request from the first cache to write the first data back to the memory, determine whether the first cache is consistent with the current unique record on the cache consistency node side; The cache that occupies the first data is the same as the cache that currently exclusively occupies the first data recorded on the cache consistency node side, and in response to determining that the first cache is the same as the cache that currently exclusively occupies the first data, the first data is written into the memory.
  • the memory is configured to: after the cache consistency node writes the first data to the memory, return a write response to the cache consistency node indicating that the first data has been written to the memory, and the cache consistency node is further configured to: in response to receiving the write response from the memory indicating that the first data has been written to the memory, return the write response signal to the first cache indicating that the first data has been written back to the memory to directly end the processing operation of the write request.
  • the cache consistency node is further configured to: in response to receiving a read request for the first data from the second cache and the cache consistency node side recording that the first data is in an exclusive state or a shared state in the first cache, initiate a monitoring signal to the first cache, and the first cache is configured to: in response to the first cache receiving the monitoring signal after issuing the write request, return a monitoring response carrying the first data to the cache consistency node.
  • At least one embodiment of the present disclosure also provides a data processing device, which includes a memory and a processor, wherein the memory is configured to store computer-executable instructions, and the processor is configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the method described in any of the above embodiments.
  • At least one embodiment of the present disclosure further provides a non-transitory storage medium that non-transitorily stores computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the method described in any of the above embodiments is implemented.
  • FIG. 1 shows a schematic diagram of an electronic device.
  • FIG. 2A shows a schematic diagram of an electronic device performing data reading.
  • FIG. 2B shows a schematic diagram of an electronic device performing data write-back.
  • FIG. 3A shows a schematic diagram of a data processing method provided by at least one embodiment of the present disclosure. picture.
  • FIG. 3B shows a schematic diagram of data write-back performed by an electronic device provided by at least one embodiment of the present disclosure.
  • FIG4 shows a schematic diagram of read-write operations of an electronic device when a read-write conflict occurs, provided by at least one embodiment of the present disclosure.
  • FIG5 shows a schematic diagram of an electronic device provided by at least one embodiment of the present disclosure.
  • FIG6 shows a schematic diagram of a data processing device provided by at least one embodiment of the present disclosure.
  • FIG. 7 shows a schematic diagram of a non-transitory storage medium provided by at least one embodiment of the present disclosure.
  • a directory-based consistency protocol In order to keep the data with the same address in each cache consistent, a directory-based consistency protocol was developed. This protocol can track the status of data in the cache.
  • the directory storage structure can be the same as the cache. It is implemented by using a static random access memory (SRAM).
  • SRAM static random access memory
  • the directory storage structure can also be implemented by using other forms of memory, as long as directory storage can be implemented.
  • Fig. 1 shows a schematic diagram of an electronic device (or electronic system) 100.
  • the electronic device 100 may include a plurality of caches (hereinafter referred to as "cache") 1-n, processors (or processor cores) 1-n, an interconnection network, cache coherence nodes 1-n, memories 1-n, directories 1-n, etc.
  • each of the caches 1 to n is configured to store data storage information corresponding to at least one piece of data information.
  • the caches 1 to n may include one or more sub-caches, respectively.
  • cache consistency nodes 1-n can help track the cache data status in caches 1-n respectively, and the cache data status includes, for example, that there is only a single copy of the cache data in cache 1-n, that there are multiple copies of the cache data, or that the data only exists in the main memory.
  • Cache consistency nodes 1-n will track the status of caches 1-n of processors 1-n (for example, each processor in FIG. 1 may include one or more sub-processors), and store the tracked status information (or directory information) in directories 1-n.
  • a cache consistency node discovers a consistency transaction while listening to the bus, it will query the tracked status information in directories 1-n and issue corresponding probes to complete consistency maintenance.
  • directories 1-n are configured to store directory information corresponding to data information stored in caches 1-n to maintain cache consistency.
  • the directory includes multiple storage groups, each of which can store multiple directory information. For example, when directory information needs to be stored in the directory, the directory puts the directory information into the corresponding storage group according to the mapping relationship.
  • an interconnection network (such as a network on chip (NOC)) in the system is directly coupled to caches 1 to n, and is also directly coupled to cache coherence nodes 1 to n.
  • the interconnection network is a public communication trunk for information transmission, for example, the interconnection network can be a transmission line bundle composed of electronic components such as wires.
  • cache consistency nodes 1 to n are configured to connect directories 1 to n to the Internet respectively, and cache consistency nodes 1 to n are configured to connect memories 1 to n to the Internet respectively, thereby maintaining the consistency of all data stored in caches 1 to n.
  • NUMA non-uniform memory access architecture
  • processors or processor cores
  • memory devices belong to different nodes, so a directory consistency-based design sets up a static random access memory (SRAM) structure directory near each memory controller.
  • SRAM static random access memory
  • each node has its own local memory.
  • FIG2A is a schematic diagram showing a data reading process of an electronic device.
  • FIG2B is a schematic diagram showing a Schematic diagram of data writeback of an electronic device.
  • master device 0 may correspond to any one of caches 1 to n in FIG1
  • slave device may correspond to any one of cache coherence nodes 1 to n in FIG1
  • MEM may correspond to any one of memories 1 to n in FIG1.
  • RdE exclusive request
  • the slave device needs to manage data consistency between the multiple master devices.
  • the slave device side in the system may adopt a cache coherence protocol based on a directory, and the directory records which master device caches the data and the current state of the data in the corresponding master device.
  • the slave device when the slave device receives an exclusive request RdE, and the directory corresponding to the current slave device side is in an invalid state I, such as represented by Dir@I in Figure 2A (see Table 1 below, for example, the invalid state I indicates that no master device currently caches this data (for example, the data corresponding to the address accessed by the request)), the slave device sends a read request Rdmem to the memory and receives the data response rddat returned by the memory to the slave device, thereby directly reading the main memory (for example, memory) data, and returns an exclusive data response DatRspE to the master device 0 as the requester (see Table 5 below), and sets the corresponding directory on the slave device side to E:Master0 (for example, represented by Dir@E:Master0 in Figure 2A), thereby recording that the master device 0 caches this data and is in an exclusive state (E: Exclusive).
  • the master device 0 After receiving the exclusive data response DatRspE, the master device 0 sends a message ACK
  • the master device generally caches more data, and there is an overflow scenario in the master device, and the overflowed data needs to be written back to the slave device from the master device.
  • the master device 0 initiates a write-back request to the slave device (FIG2B only uses WBI as an example for illustration, but is not limited to this write-back request), and sends the data to be written back to the memory to the slave device through the signal WrDat, and the slave device side confirms that the write-back data has been received and returns a write response WrRap to the master device 0.
  • the master device 0 After receiving the write response WrRap, the master device 0 sends a message (or write response) ACK to the slave device. For example, as shown in FIG2B, after the slave device receives the message ACK sent by the master device 0, the directory state corresponding to the slave device side is set to Dir@I from Dir@E:Master0. For example, after receiving the message ACK, the slave device side sends a write request Rdmem to the memory to write the data to be written back to the memory, and receives the data write response WrRap returned by the memory to the slave device to end the write-back request.
  • both read and write transactions need to carry ACK messages, which will prolong the life cycle of the transaction in the slave device, that is, the time of occupying the slave device buffer (for example, cache or other storage area that can be used to implement the directory) will be longer, reducing the turnover rate of the slave device buffer. And waste of resources, and ACK message transmission requires a certain amount of power consumption.
  • a data processing method provided by the present disclosure includes: in response to receiving a write request from a first cache to write first data back to a memory, a cache consistency node writes the first data to the memory or discards the first data, wherein the write request carries the first data, and the cache consistency node is configured to maintain the consistency of data stored in multiple caches, and the multiple caches include the first cache; and after the cache consistency node writes the first data to the memory or discards the first data, the cache consistency node returns a write response signal to the first cache to directly end the processing operation of the write request.
  • scenario identification is performed by comparing the write-back transaction and the directory.
  • the master device After receiving the write response, the master device directly ends the write transaction processing, and there is no need to send an ACK message to the slave device, thereby reducing the number of ACK messages, reducing the protocol's demand for ACK messages, reducing the power consumption and delay as well as bandwidth occupancy caused by the transmission of ACK messages, and optimizing the turnover rate of the buffer on the master device side. Under the same performance, the number of buffers required on the master device side is smaller, saving area and power consumption.
  • At least some embodiments of the present disclosure also provide an electronic device, which includes multiple caches and a cache consistency node.
  • the multiple caches include a first cache, and the cache consistency node is configured to write the first data to the memory or discard the first data in response to receiving a write request from the first cache to write the first data back to the memory, and after the cache consistency node writes the first data to the memory or discards the first data, return a write response signal to the first cache to directly end the processing operation of the write request, wherein the write request carries the first data, and the cache consistency node is configured to maintain the consistency of the data stored in the multiple caches.
  • the first cache can be any cache among multiple caches, and the first data can be, for example, data corresponding to any accessed address, that is, the "first" (and “second”, etc.) here is only used to identify the cache or data as the description object, rather than specifically referring to a specific cache or data.
  • Fig. 3A shows a schematic flow chart of a data processing method provided by at least one embodiment of the present disclosure. As shown in Fig. 3A, in some embodiments of the present disclosure, the data processing method includes the following steps S101-S102.
  • Step S101 in response to receiving a write request from a first cache to write first data back to a memory, a cache consistency node writes the first data to the memory or discards the first data, wherein the write request carries the first data, and the cache consistency node is configured to maintain consistency of data stored in multiple caches, and the multiple caches include the first cache.
  • Step S102 After the cache coherence node writes the first data into the memory or discards the first data, the cache coherence node returns a write response signal to the first cache to directly end the processing operation of the write request.
  • 3B shows a schematic diagram of data writeback of an electronic device provided by at least one embodiment of the present disclosure.
  • the cache consistency node in response to receiving a write request from a first cache (or "master device 0") to write first data back to the memory, the cache consistency node (or “slave device”) writes the first data to the memory MEM.
  • the write request carries the first data
  • the cache consistency node is configured to maintain the consistency of data stored in multiple caches, including the first cache.
  • the cache consistency node returns a write response signal WrRsp to the first cache to directly end the processing operation of the write request.
  • FIG4 shows a schematic diagram of read and write operations of an electronic device provided by at least one embodiment of the present disclosure when there is a read-write conflict.
  • the cache consistency node in response to receiving a write request from a first cache (or "master device 0") to write first data back to the memory, the cache consistency node (or “slave device”) discards the first data.
  • the write request carries the first data
  • the cache consistency node is configured to maintain the consistency of data stored in multiple caches, including the first cache.
  • the cache consistency node returns a write response signal WrRsp to the first cache to directly end the processing operation of the write request.
  • first cache e.g., master device 0
  • second cache e.g., master device 1
  • cache consistency node e.g., a slave device
  • memory e.g., MEM
  • the master device (or cache) specified by the protocol of the embodiment of the present disclosure has multiple states, as shown in Table 1:
  • the cache state may be the state of the first cache, and the main memory may be the memory MEM.
  • the first cache may include the M state, the E state, the S state, and the I state.
  • the M state indicates that the first cache exclusively occupies the corresponding data, and the data has been modified;
  • the E state indicates that the first cache exclusively occupies the corresponding data, and the data has not been modified;
  • the S state indicates that the first cache shares the corresponding data with other master devices;
  • the I state indicates that the first cache does not cache the corresponding data.
  • the other caches are all in the I state where the modified data is not cached; when the first cache is in the E state, the other caches are all in the I state where the data is not cached; when the first cache is in the S state, there are other caches in the S state that share the data; when the first cache is in the I state, the other caches can be in any one of the M state, the E state, the S state, and the I state.
  • the state of the master device (eg, the first cache) is not limited to the four states listed above, and the master device may have other different states according to different needs.
  • Table 2 shows the request types that can be issued by the master device as specified in the protocol of the present disclosure, as well as the corresponding cache state transitions and slave device response messages.
  • the master device is the first cache as an example.
  • the request type may be a request type initiated by the first cache to the slave device.
  • the read request types that may be initiated by the first cache may include RdE (obtaining an exclusive data copy), RdD (obtaining a data copy in a non-I state, i.e., caching this data copy), RdS (obtaining a shared data copy), RdI (obtaining a data snapshot, not caching this data copy), and RdEE (obtaining data exclusive rights, not obtaining data).
  • RdE obtaining an exclusive data copy
  • RdD obtaining a data copy in a non-I state, i.e., caching this data copy
  • RdS obtaining a shared data copy
  • RdI obtaining a data snapshot, not caching this data copy
  • RdEE obtaining data exclusive rights, not obtaining data
  • the cache state when the read request type initiated by the first cache to the slave device is RdE, the cache state (or cache data state) when the first cache initiates the request can be I state, S state or E state; when the RdE request ends, the cache state of the first cache can be E state (in this case, the slave device returns a response DatRspE (see Table 6 below) to the first cache, so that the slave device obtains a response of an exclusive data copy) or M state (in this case, the slave device returns a response DatRspM (see Table 6 below), so that the slave device obtains a response of a modified data copy).
  • the slave device returns a response DatRspE (see Table 6 below) to the first cache, so that the slave device obtains a response of an exclusive data copy) or M state (in this case, the slave device returns a response DatRspM (see Table 6 below), so that the slave device obtains a response of a modified data copy).
  • the cache state of the first cache when initiating the request may be in the I state; when the RdD request ends, the cache state of the first cache may be in the S state (in this case, the slave device returns a response DatRspS to the first cache (see Table 6 below), so that the slave device obtains a response of a copy of the shared data), the E state (in this case, the slave device returns a response DatRspE to the first cache), or the M state (in this case, the slave device returns a response DatRspM to the first cache).
  • the cache state of the first cache when initiating the request may be in the I state; when the RdS request ends, the cache state of the first cache may be in the S state (in this case, the slave device returns a response DatRspS to the first cache (see Table 6 below), so that the slave device obtains a response of a copy of the shared data), the E state (in this case, the slave device returns a response DatRspE to the first cache), or the M state (in this case, the slave device returns a response DatRspM to the first cache).
  • the cache state may be in the S state (in this case, the slave device returns a response DatRspS to the first cache).
  • the cache state of the first cache when initiating the request may be in the I state; when the RdI request ends, the cache state of the first cache may be in the I state (in this case, the slave device returns a response DatRspI (see Table 6 below) to the first cache, so that the slave device obtains a response of a data copy).
  • the cache state of the first cache when initiating the request may be in the I state or the S state; when the RdEE request ends, the cache state of the first cache may be in the E state (in this case, the slave device returns a response RspE (see Table 6 below), so that the slave device obtains a response of exclusive rights).
  • the write request types that can be initiated by the first cache may include WBI (write the cached data copy back to the main memory, and set the cache to invalid I state), WBS (write the cached data copy back to the main memory, and set the cache to shared S state), and WBE (write the cached data copy back to the main memory, and set the cache to exclusive E state).
  • WBI write the cached data copy back to the main memory, and set the cache to invalid I state
  • WBS write the cached data copy back to the main memory, and set the cache to shared S state
  • WBE write the cached data copy back to the main memory, and set the cache to exclusive E state.
  • the embodiments of the present disclosure are not limited to this, and the first cache may also initiate other different write request types as needed.
  • the cache state of the first cache when initiating the request may be M state; when the write request WBI ends, the cache state of the first cache may be I state (in this case, the slave device returns a response WrRsp to the first cache).
  • the cache state of the first cache when initiating the request may be M state; when the write request WBS ends, the cache state of the first cache may be I state (in this case, the slave device returns a response WrRsp to the first cache) or S state (in this case, the slave device returns a response WrRsp to the first cache).
  • the cache state of the first cache when initiating the request may be M state; when the write request WBE ends, the cache state of the first cache may be I state (in this case, the slave device returns a response WrRsp to the first cache), S state (in this case, the slave device returns a response WrRsp to the first cache) or E state (in this case, the slave device returns a response WrRsp to the first cache).
  • the first cache write request is not limited to WBI, and the write request may also be WBS or WBE shown in Table 2.
  • the first cache may initiate a write request WBI to the slave device.
  • the cache consistency node writes the first data to the memory MEM (as shown in FIG. 3B ) or discards the first data (as shown in FIG. 4 ).
  • the cache consistency node After the first data is written into the memory MEM or the first data is discarded, the cache consistency node returns a write response signal WrRsp to the first cache to directly end the processing operation of the write request.
  • the first cache can initiate a write request WBS to the slave device.
  • the cache consistency node writes the first data to the memory MEM (as shown in FIG. 3B) or discards the first data (as shown in FIG. 4).
  • the cache consistency node returns a write response signal WrRsp to the first cache to directly end the processing operation of the write request.
  • the first cache can initiate a write request WBE to the slave device.
  • the cache consistency node In response to receiving the write request WBE from the first cache to write the first data back to the memory MEM, the cache consistency node writes the first data to the memory MEM (as shown in FIG. 3B) or discards the first data (as shown in FIG. 4). For example, after the cache coherence node writes the first data into the memory MEM or discards the first data, the cache coherence node returns a write response signal WrRsp to the first cache to directly end the processing operation of the write request.
  • the cache consistency node determines whether the first cache is the same as the cache that currently exclusively owns the first data recorded on the cache consistency node side, and in response to determining that the first cache is the same as the cache that currently exclusively owns the first data recorded on the cache consistency node side, the cache consistency node writes the first data to the memory MEM.
  • the slave device determines whether master device 0 is the same as the cache currently exclusive to the first data recorded on the slave device side.
  • the memory returns a write response to the cache coherence node indicating that the first data has been written into the memory, and in response to receiving a write response from the memory indicating that the first data has been written into the memory, the cache coherence node returns an indication to the first cache.
  • a write response signal indicating that the first data has been written back to the memory directly ends the processing operation of the write request.
  • the memory MEM returns a write response WrRsp indicating that the first data has been written into the memory MEM to the slave device, and in response to receiving the write response WrRsp indicating that the first data has been written into the memory MEM from the memory MEM, the slave device returns a write response signal WrRsp indicating that the first data has been written back into the memory MEM to the master device 0 to directly terminate the processing operation of the write request.
  • the master device 0 does not need to send a message to the slave device and directly terminates the processing operation of the write request.
  • the cache coherence node sets the data state of the first cache to an invalid state, a shared state, or an exclusive state.
  • the invalid state indicates that the first cache does not cache the first data
  • the shared state indicates that the first cache and other caches cache the first data
  • the exclusive state indicates that only the first cache caches the first data.
  • the slave device changes the data state of the first cache (e.g., master device 0) among the multiple caches to an invalid state (I state), a shared state (S state), or an exclusive state (e.g., E state).
  • I state an invalid state
  • S state shared state
  • E state an exclusive state
  • the invalid state indicates that the first cache does not cache the first data
  • the shared state indicates that the first cache and other caches cache the first data
  • the exclusive state indicates that only the first cache caches the first data.
  • the cache state of the first cache may be in the I state.
  • the cache state of the first cache may be in the I state (for example, after the first cache writes the data back to the memory MEM, the data cached in the first cache is replaced by other data) or the S state (for example, after the first cache writes the data back to the memory MEM, the data cached in the first cache is not replaced by other data).
  • the cache state of the first cache may be in the I state (for example, after the first cache writes the data back to the memory MEM, the data cached in the first cache is replaced by other data), the S state (for example, the data written back to the memory MEM by the first cache is shared by other caches) or the E state (for example, the data written back to the memory MEM by the first cache is not shared by other caches, and after the first cache writes the data back to the memory MEM, the data cached in the first cache is not replaced by other data).
  • the cache coherence node in response to receiving a read request for the first data from the second cache (or “master device 1”) and the cache coherence node side (e.g., a directory corresponding to the slave device) recording that the first data is in an exclusive state or a shared state in the first cache (or “master device 0”), the cache coherence node sends a request to the master device 1 to read the first data.
  • the first cache initiates a monitoring signal (e.g., ExpI); in response to the first cache receiving the monitoring signal after issuing a write request, the first cache returns a monitoring response (e.g., ExpRspIDat) carrying the first data to the cache consistency node in response to the monitoring signal.
  • a monitoring signal e.g., ExpI
  • Table 3 shows the monitoring signal types and their descriptions specified in the protocol of the present disclosure.
  • the detection signal Exp* is used to monitor the cache status and data at the master device and set the monitored master device to a corresponding status.
  • Table 4 shows the monitoring response types specified in the protocol of the present disclosure, that is, the monitoring responses that the master device may return to the slave device when being monitored by the detection signal Exp*.
  • Table 5 shows the non-monitoring response transaction types and their descriptions specified in the protocol of the present disclosure.
  • Table 6 is a state transition table of monitoring transactions on the master device side and monitoring response actions specified in the protocol of the present disclosure, which defines the target state that the master device side cache may be converted to after being monitored, and sends the corresponding monitoring response message.
  • the first cache when the first cache receives the detection signal ExpI, if the current cache state of the first cache is I, S, E, or M, the state of the first cache after processing the monitoring signal is I, and the first cache returns a detection response ExpRspI (for example, when the current state of the first cache is I) or ExpRspIDat (for example, when the current state of the first cache is S, E, or M) to the cache consistency node.
  • ExpRspI for example, when the current state of the first cache is I
  • ExpRspIDat for example, when the current state of the first cache is S, E, or M
  • the first cache receives the detection signal ExpS, if the current cache state of the first cache is I, then the state of the first cache after processing the monitoring signal is I, and the first cache returns a detection response ExpRspI to the cache consistency node; when the first cache receives the detection signal ExpS, if the current cache state of the first cache is S, then the state of the first cache after processing the monitoring signal is S, and the first cache returns a detection response ExpRspS to the cache consistency node; when the first cache receives the detection signal ExpS, If the current cache state of the first cache is E or M, the state of the first cache after processing the monitoring signal is S, and the first cache returns a detection response ExpRspS (for example, when the first cache executes a write request WBS or WBE) or ExpRspSDat (for example, when the first cache executes a write request WBI) to the cache consistency node.
  • ExpRspS for example, when the first cache executes a write request
  • the first cache when the first cache receives the detection signal ExpE, if the current cache state of the first cache is I, then the state of the first cache after processing the monitoring signal is I, and the first cache returns a detection response ExpRspI to the cache consistency node; when the first cache receives the detection signal ExpE, if the current cache state of the first cache is S, then the state of the first cache after processing the monitoring signal is S, and the first cache returns a detection response ExpRspS to the cache consistency node; when the first cache receives the detection signal ExpE, if the current cache state of the first cache is E or M, then the state of the first cache after processing the monitoring signal is E or M, and the first cache returns a detection response ExpRspE (for example, when the first cache executes a write request WBS or WBE) or ExpRspEDat (for example, when the first cache executes a write request WBI) to the cache consistency node.
  • ExpRspE for example, when the
  • Table 7 shows the situation where the monitoring transaction specified in the protocol of the present invention is processed on the master device side and there is a conflict, that is, when the monitoring transaction reaches the master device, the master device has currently initiated a read transaction (or read request) Rd* or a write transaction (or write request) WB* for the cache line of the same address.
  • Table 8 is the protocol definition of the present disclosure that after a slave device receives a read or write request from a master device, it may need to perform a state transition based on the directory state (including triggering a monitoring command, returning a response command to the master device, or reading and writing memory data).
  • the cache consistency node in response to receiving a read request RdE from the second cache for the first data and the first data being in the I state in the directory corresponding to the cache consistency node, the cache consistency node directly reads the first data from the memory and returns the first data to the second cache.
  • the cache consistency node side in response to receiving a read request RdE from the second cache for the first data and the cache consistency node side (for example, from the directory corresponding to the device) records that the first data is in the S state or the exclusive state E in the directory corresponding to the cache consistency node, the cache consistency node initiates a monitoring signal ExpI to the first cache (monitoring the target cache, obtaining the latest data copy, and setting its cached data to an invalid state).
  • the cache coherence node in response to receiving the monitoring response, returns the first data to the second cache, and after receiving the first data, the second cache returns a message indicating that the first data has been received to the cache coherence node to end the read request.
  • the slave device in response to receiving the monitoring response ExpRspIDat, returns the first data to the master device 1 in response to the monitoring response ExpRspIDat (e.g., through the response signal DatRspM), and the master device 1 returns the data on the slave device side to the master device 1.
  • the state is set to an exclusive state (for example, the slave device records Dir@E:Master1), and the exclusive state (or Dir@E:Master1) indicates that the first data is cached only in the master device 1. For example, after receiving the first data, the master device 1 returns a message ACK to the slave device indicating that the first data has been received to end the read request RdE.
  • an exclusive state for example, the slave device records Dir@E:Master1
  • Dir@E:Master1 indicates that the first data is cached only in the master device 1.
  • the master device 1 After receiving the first data, the master device 1 returns a message ACK to the slave device indicating that the first data has been received to end the read request RdE.
  • the cache coherence node discards the first data written by the write request to the cache coherence node side, and returns a write response signal to the first cache to directly end the processing operation of the write request.
  • the slave device receives the message ACK from the master device 1
  • the read request RdE previously issued by the master device is processed, and the write request WB* previously issued by the master device 0 on the slave device side, which is in a blocked state (it is in a blocked state after the slave device processes the read request initiated by the master device 1 (that is, since the slave device can only process one transaction with the same address at the same time, the write request WB* initiated by the master device 0 is always in a blocked state before the RdE processing of the master device 1 is completed)) is awakened to continue processing.
  • the slave device determines that the first data written by the write request to the slave device side is invalid data, the slave device discards the first data written by the write request to the slave device side, and returns a write response signal WrRsp to the master device 0 to directly end the processing operation of the write request. For example, after receiving the write response signal WrRsp, the slave device directly ends the corresponding write transaction processing, and there is no need to send a message ACK to the slave device.
  • the cache consistency node in response to receiving a read request RdD, RdS or RdI from the second cache for the first data and the cache consistency node side (for example, from the directory corresponding to the device) records that the first data is in the exclusive state E in the directory corresponding to the cache consistency node, the cache consistency node initiates a monitoring signal ExpS to the first cache (monitoring the target cache, obtaining the latest data copy, and setting its cached data to an invalid or shared state).
  • the cache coherence node in response to receiving the monitoring response, returns the first data to the second cache, and after receiving the first data, the second cache returns an indication to the cache coherence node that it has received the first data.
  • the slave device in response to receiving the monitoring response ExpRspIDat, returns the first data to the master device 1 in response to the monitoring response ExpRspIDat (for example, through the response signal DatRspM), and sets the data state of the master device 1 on the slave device side to an exclusive state (for example, the slave device side records Dir@E:Master1), and the exclusive state (or Dir@E:Master1) indicates that only the master device 1 has the first data cached.
  • the master device 1 after receiving the first data, the master device 1 returns a message ACK to the slave device indicating that the first data has been received to end the read request (for example, RdD or RdS).
  • the cache consistency node discards the first data written by the write request to the cache consistency node side, and returns a write response signal to the first cache to directly end the processing operation of the write request. For example, as shown in FIG4, after the slave device receives the message ACK from the master device 1, the read request RdD, RdS or RdI previously issued by the master device is processed, and the write request WB* previously issued by the master device 0 in the blocked state on the slave device side is awakened to continue processing.
  • the cache consistency node in response to receiving a read request RdEE for the first data from the second cache and the first data is in the I state in the directory corresponding to the cache consistency node, the cache consistency node returns a response RspE (no data monitoring response, the monitored cache is set to the E state or the M state) to the second cache to end the read request RdEE.
  • RspE no data monitoring response, the monitored cache is set to the E state or the M state
  • the cache consistency node in response to receiving a read request RdEE for the first data from the second cache and the cache consistency node side (for example, the directory corresponding to the slave device) records that the first data is in the S state or the exclusive state E in the directory corresponding to the cache consistency node, the cache consistency node initiates a monitoring signal ExpE to the first cache (monitoring the target cache, obtaining the latest data copy, and not changing its cache data state).
  • the cache coherence node in response to receiving the monitoring response, returns the first data to the second cache, and after receiving the first data, the second cache returns a message indicating that the first data has been received to the cache coherence node to end the read request.
  • the slave device in response to receiving the monitoring response ExpRspIDat, returns the first data to the master device 1 in response to the monitoring response ExpRspIDat (e.g., through the response signal DatRspM).
  • the master device After receiving the first data, the master device The device 1 returns a message ACK to the slave device indicating that the first data has been received, so as to end the read request RdEE.
  • the cache consistency node discards the first data written by the write request to the cache consistency node side, and returns a write response signal to the first cache to directly end the processing operation of the write request. For example, as shown in Figure 4, after the slave device receives the message ACK from the master device 1, the read request RdEE previously issued by the master device is processed, and the write request WB* previously issued by the master device 0 in the blocked state on the slave device side is awakened to continue processing.
  • the slave device side since the slave device side records that the master device 0 is no longer in the state of monopolizing the first data, and the write request is initiated by the master device 0, the data in the write transaction of the master device 0 is already expired and invalid data, so the slave device determines that this write transaction or write operation should be invalid data due to the conflict, and directly discards the data that has been written to the slave device by the master device 0. For example, the slave device determines that the first data written by the write request to the slave device side is invalid data, the slave device discards the first data written by the write request to the slave device side, and returns a write response signal WrRsp to the master device 0 to directly end the processing operation of the write request. For example, after receiving the write response signal WrRsp, the slave device directly ends the corresponding write transaction processing without sending the message ACK.
  • a write request e.g., WBI, WBS, or WBE
  • the detection signal will not be triggered, and the cache consistency node returns a response WrRsp to the second cache.
  • the data that the cache consistency node records needs to be written by the second cache is in an exclusive state and points to the second cache that initiated the write request WBI, the data is written to the memory, otherwise the data is discarded.
  • Table 9 is a state transition table specified by the protocol of the present disclosure after the slave device receives a response from the master device.
  • the cache coherence node needs to read the memory data.
  • the cache coherence node After the cache coherence node reads the memory data, the data is sent to the second cache, and the status of the read request transaction table entry corresponding to the read request of the second cache is set to a waiting confirmation state (for example, WaitACK), waiting for the second cache to send a confirmation signal (ACK) confirming that the data has been successfully received.
  • a waiting confirmation state for example, WaitACK
  • ACK confirmation signal
  • the cache coherence node receives a request type of a read request RdI from the second cache (for example, the cache coherence node creates a read request transaction table entry in response to receiving the read request RdI from the second cache, and records the status related to the current read request transaction), then after receiving the response signal ExpRspIDat sent by the first cache to the cache coherence node, the cache coherence node sends a response signal DatRspI carrying data to the second cache, and sets the status of the read request transaction table entry corresponding to the read request RdI of the second cache to a waiting confirmation state (for example, WaitACK), waiting for the second cache to send a confirmation signal (ACK) confirming that the data has been successfully received.
  • a waiting confirmation state for example, WaitACK
  • the cache coherence node sends a response signal ExpRspIDat to the cache coherence node, and the request type received by the cache coherence node from the second cache is a read request RdS (for example, after the cache coherence node creates a read request transaction processing table entry in response to receiving the read request RdS from the second cache, and records the status related to the current read request transaction), then after receiving the response signal ExpRspIDat sent by the first cache to the cache coherence node, the cache coherence node sends a response signal DatRspS carrying data to the second cache, and sets the status of the read request transaction processing table entry corresponding to the read request RdS of the second cache to a waiting confirmation state (for example, WaitACK), waiting for the second cache to send a confirmation signal (ACK) confirming that the data has been successfully received.
  • a waiting confirmation state for example, WaitACK
  • the cache coherence node sends a response signal ExpRspIDat to the cache coherence node, and the cache coherence node receives a request type of a read request RdD from the second cache (for example, after the cache coherence node responds to receiving the read request RdD from the second cache, it creates a read request transaction processing entry, recording the status related to the current read request transaction), then after receiving the response signal ExpRspIDat sent by the first cache to the cache consistency node, the cache consistency node sends a response signal DatRspE (recording that the second cache exclusively owns the data) or DatRspM (recording that the second cache exclusively owns the modified data) carrying data to the second cache, and sets the status of the read request transaction processing entry corresponding to the read request RdD of the second cache to the waiting confirmation state (for example, WaitACK), waiting for the second cache to send a confirmation signal (ACK) confirming that the data has been successfully received.
  • the cache coherence node sends a response signal ExpRspIDat to the cache coherence node, and the request type received by the cache coherence node from the second cache is a read request RdE (for example, after the cache coherence node responds to receiving the read request RdE from the second cache, it creates a read request transaction processing table entry to record the status related to the current read request transaction), then after receiving the response signal ExpRspIDat sent by the first cache to the cache coherence node, the cache coherence node sends a response signal DatRspE (recording that the second cache exclusively owns this data) or DatRspM (recording that the second cache exclusively owns this modified data) carrying data to the second cache, and sets the status of the read request transaction processing table entry corresponding to the read request RdE of the second cache to a waiting confirmation state (for example, WaitACK), waiting for the second cache to send a confirmation signal (ACK) confirming that the
  • the first cache sends a response signal ExpRspSDat to the cache coherence node, and the request type received by the cache coherence node from the second cache is a read request RdS or RdD (for example, after the cache coherence node responds to receiving the read request RdS or RdD from the second cache, it creates a read request transaction processing table entry to record the status related to the current read request transaction), then after receiving the response signal ExpRspSDat sent by the first cache to the cache coherence node, the cache coherence node sends a response signal DatRspS carrying data to the second cache (recording that the second cache shares this data), and sets the status of the read request transaction processing table entry corresponding to the read request RdS or RdD of the second cache to a waiting confirmation state (for example, WaitACK), waiting for the second cache to send a confirmation signal (ACK) confirming that the data has been successfully received.
  • a waiting confirmation state for example, WaitACK
  • the first cache sends a response signal ExpRspEDat to the cache coherence node, and the request type received by the cache coherence node from the second cache is a read request RdI (for example, after the cache coherence node responds to receiving the read request RdI from the second cache, it creates a read request transaction processing table entry and records the status related to the current read request transaction), then after receiving the response signal ExpRspEDat sent by the first cache to the cache coherence node, the cache coherence node sends a response signal DatRspI carrying data to the second cache (recording that the second cache obtains a copy of this data), and sets the status of the read request transaction processing table entry corresponding to the read request RdI of the second cache to a waiting for confirmation state.
  • the second buffer enters a state (eg, WaitACK) and waits for the second buffer to send an acknowledgment signal (ACK) confirming that the data has been successfully received.
  • the first cache sends a response signal ACK to the cache coherence node, and the request type received by the cache coherence node from the second cache is a read request Rd* (for example, after the cache coherence node responds to receiving the read request Rd* from the second cache, it creates a read request transaction processing table entry or a write request transaction processing table entry to record the status related to the current read request transaction), then after receiving the response signal ACK sent by the first cache to the cache coherence node, the cache coherence node sets the status of the read request transaction processing table entry to the end state to confirm that the data reading has been successfully completed.
  • scenario identification is performed by comparing the write-back transaction and the directory.
  • the master device After receiving the write response, the master device directly ends the write transaction processing, and there is no need to send an ACK message to the slave device, thereby reducing the number of ACK messages, reducing the protocol's demand for ACK messages, reducing the power consumption and delay as well as bandwidth occupancy caused by the transmission of ACK messages, and optimizing the turnover rate of the buffer on the master device side. Under the same performance, the number of buffers required on the master device side is smaller, saving area and power consumption.
  • FIG5 shows a schematic diagram of an electronic device 60 provided by at least one embodiment of the present disclosure.
  • the electronic device 60 includes a cache consistency node 605, a first cache 606, and a second cache 607.
  • the cache consistency node 605 is configured to write the first data to the memory or discard the first data in response to receiving a write request from the first cache 606 to write the first data back to the memory, and after the cache consistency node 605 writes the first data to the memory or discards the first data, return a write response signal to the first cache 606 to directly end the processing operation of the write request.
  • the write request carries the first data
  • the cache consistency node 605 is configured to maintain the consistency of the data stored in multiple caches.
  • the cache included in the electronic device 60 of the present disclosure is not limited to the two caches (the first cache 606 and the second cache 607) shown in FIG5, and the number of electronic devices 60 can be set to any number as needed.
  • the cache consistency node 605 is also configured to: in response to receiving a write request from the first cache 606 to write the first data back to the memory, determine whether the first cache 606 is the same as the cache that currently exclusively owns the first data recorded on the cache consistency node 605 side, and in response to determining that the first cache 606 is the same as the cache that currently exclusively owns the first data recorded on the cache consistency node 605 side, write the first data to the memory.
  • the memory is configured to: after the cache consistency node 605 writes the first data into the memory, return a write response indicating that the first data has been written into the memory to the cache consistency node 605.
  • the cache consistency node 605 is further configured to: in response to receiving an indication from the memory that the first data has been written into the memory The write response of the memory returns a write response signal indicating that the first data has been written back to the memory to the first cache 606 to directly end the processing operation of the write request.
  • the cache coherence node 605 is further configured to: after the cache coherence node 605 writes the first data into the memory, set the data state of the first cache 606 to an invalid state, a shared state, or an exclusive state.
  • the invalid state indicates that the first cache 606 does not cache the first data
  • the shared state indicates that the first cache 606 and other caches cache the first data
  • the exclusive state indicates that only the first cache 606 caches the first data.
  • the cache coherence node 605 is further configured to: in response to receiving a read request for the first data from the second cache 607 and the cache coherence node 605 recording that the first data is in an exclusive state or a shared state in the first cache 606, initiate a monitoring signal to the first cache 606.
  • the first cache 606 is configured to: in response to the first cache 606 receiving a monitoring signal after issuing a write request, return a monitoring response carrying the first data to the cache coherence node 605.
  • the cache coherence node 605 is further configured to: in response to receiving the monitoring response, return the first data to the second cache 607.
  • the second cache 607 is further configured to: return a message indicating that the first data has been received to the cache coherence node 605 to end the read request.
  • the cache coherence node 605 is further configured to: in response to receiving the monitoring response, return the first data to the second cache 607 and set the data state of the second cache 607 to an exclusive state.
  • the exclusive state indicates that only the second cache 607 caches the first data.
  • the cache coherence node 605 is further configured to: after receiving the message, discard the first data written by the write request to the cache coherence node 605 side, and return a write response signal to the first cache 606 to directly end the processing operation of the write request.
  • the cache consistency node 605 is further configured to: in response to determining that the first data written by the write request to the cache consistency node 605 side is invalid data after receiving the message, discard the first data written by the write request to the cache consistency node 605 side.
  • scenario identification is performed by comparing the write-back transaction and the directory.
  • the master device After receiving the write response, the master device directly ends the write transaction processing without sending an ACK message to the slave device, thereby reducing the number of ACK messages, reducing the protocol's demand for ACK messages, reducing the power consumption and delay as well as bandwidth occupancy caused by the transmission of ACK messages, and optimizing the turnover rate of the buffer on the master device side. Under the same performance, the master device side requires fewer buffers, saving area and power consumption.
  • At least some embodiments of the present disclosure further provide a data processing device, the data processing device comprising
  • the computer-readable medium includes a memory and a processor.
  • the memory is configured to store computer-executable instructions
  • the processor is configured to execute computer-executable instructions.
  • the data processing method provided by at least one embodiment of the present disclosure is implemented.
  • FIG6 shows a schematic diagram of a data processing device 500 provided by at least one embodiment of the present disclosure.
  • the electronic device 500 includes a processor 501 and a memory 502 , and the processor 501 and the memory 502 may be interconnected via a bus 503 .
  • the processor 501 can perform various actions and processes according to the program or code stored in the memory 502.
  • the processor 501 can be an integrated circuit chip with signal processing capabilities.
  • the processor 501 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, and can implement or execute the various methods and steps disclosed in the embodiments of the present disclosure.
  • the general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can be an X86 architecture or an ARM architecture, etc.
  • the memory 502 is used to store computer executable instructions in a non-temporary manner, and the processor 501 is used to execute the computer executable instructions.
  • the processor 501 is used to execute the computer executable instructions.
  • memory 502 may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory.
  • Nonvolatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory.
  • Volatile memory may be a random access memory (RAM), which is used as an external cache.
  • RAM random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • DDRSDRAM double data rate synchronous dynamic random access memory
  • ESDRAM enhanced synchronous dynamic random access memory
  • SLDRAM synchronously linked dynamic random access memory
  • DRRAM direct memory bus random access memory
  • the scene recognition is performed, and the master device directly ends the write transaction processing after receiving the write response, and does not need to send an ACK message to the slave device, thereby reducing the number of ACK messages and reducing the need for ACK messages in the protocol.
  • the requirements are reduced, the power consumption, delay and bandwidth occupancy caused by ACK message transmission are reduced, and the turnover rate of the buffer on the master device side is optimized. Under the same performance, the number of buffers required on the master device side is smaller, saving area and power consumption.
  • At least one embodiment of the present disclosure further provides a non-transitory storage medium that non-transitorily stores computer executable instructions. For example, when the computer executable instructions are executed by a processor, the data processing method provided by at least one embodiment of the present disclosure is implemented.
  • Fig. 7 is a schematic diagram of a non-transitory storage medium provided by some embodiments of the present disclosure. As shown in Fig. 7, the non-transitory storage medium 600 can non-transitorily store computer executable instructions 610, which implement the data processing method provided by any embodiment of the present disclosure when executed by a computer.
  • non-transitory storage medium in the embodiments of the present disclosure may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. It should be noted that the memory of the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.
  • each box in the flowchart or block diagram can represent a module, a program segment, or a part of a code, and the module, program segment, or a part of the code contains at least one executable instruction for realizing the specified logical function.
  • the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved.
  • each box in the block diagram and/or flowchart, and the combination of boxes in the block diagram and/or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.
  • various example embodiments of the present disclosure may be implemented in hardware or dedicated circuits, software, firmware, logic, or any combination thereof. Certain aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device.
  • firmware or software that may be executed by a controller, microprocessor, or other computing device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

本公开的实施例提供了数据处理方法和装置、电子设备和存储介质。该数据处理方法包括：响应于收到第一缓存要将第一数据写回内存的写请求，缓存一致性节点将第一数据写入内存或将第一数据丢弃，其中，写请求携带第一数据，缓存一致性节点配置为维护由多个缓存中存储的数据的一致性，多个缓存包括第一缓存；以及在缓存一致性节点将第一数据写入内存或将第一数据丢弃之后，缓存一致性节点向第一缓存返回写响应信号以直接结束对写请求的处理操作。该方法能够降低ACK报文的数量，减少协议对ACK报文的需求，减少ACK报文传输产生的功耗和延时以及带宽占用，并且优化了主设备侧缓冲区的周转率，在相同性能下主设备侧需要的缓冲区数量更少，节省面积和功耗。

Description

数据处理方法和装置、电子设备以及存储介质
本申请要求于2023年11月27日递交的中国专利申请第202311598492.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种数据处理方法、数据处理装置、电子设备和存储介质。
背景技术
片上网络(Network-on-a-Chip，NOC)系统是一种必要的总线系统，用于实现大规模集成电路中各组件之间的相互通信。在一个系统级芯片(SOC)中包含了多种类型的子系统，如CPU、GPU、内存、IO设备等，并且每种类型的子系统都可能存在多个实体，这些实体需要彼此通信(数据信号和控制信号)协同工作。
在一个SOC系统中，多个子系统实体之间需要进行频繁的读写交互。为了确保各子系统之间能够高性能地交互数据，NOC系统提供了一个大带宽的事务交换网络，用于连接片上各组件。通过这个网络，各个子系统之间可以实现高效的数据传输。当不同的子系统对应的缓存对所缓存的相同地址的数据进行操作时，会产生一致性问题。为了解决这个问题，出现了很多技术来维护数据一致性。
发明内容
本公开的至少一个实施例提供了一种数据处理方法，所述数据处理方法包括：响应于收到第一缓存要将第一数据写回内存的写请求，缓存一致性节点将所述第一数据写入内存或将所述第一数据丢弃，其中，所述写请求携带所述第一数据，所述缓存一致性节点配置为维护由多个缓存中存储的数据的一致性，所述多个缓存包括所述第一缓存，以及在所述缓存一致性节点将所述第一数据写入内存或将所述第一数据丢弃之后，所述缓存一致性节点向所 述第一缓存返回写响应信号以直接结束对所述写请求的处理操作。
例如，在本公开的至少一个实施例提供的数据处理方法中，所述响应于收到第一缓存要将第一数据写回内存的写请求，缓存一致性节点将所述第一数据写入内存或将所述第一数据丢弃，包括：响应于收到所述第一缓存要将所述第一数据写回所述内存的所述写请求，所述缓存一致性节点确定所述第一缓存是否与所述缓存一致性节点侧记录的当前独占所述第一数据的缓存相同；以及响应于确定所述第一缓存与所述缓存一致性节点侧记录的当前独占所述第一数据的缓存相同，所述缓存一致性节点将所述第一数据写入所述内存。
例如，在本公开的至少一个实施例提供的数据处理方法中，所述在所述缓存一致性节点将所述第一数据写入内存或将所述第一数据丢弃之后，所述缓存一致性节点向所述第一缓存返回写响应信号以直接结束对所述写请求的处理操作，包括：在所述缓存一致性节点将所述第一数据写入内存之后，所述内存向所述缓存一致性节点返回指示所述第一数据已经被写入所述内存的写响应；以及响应于从所述内存收到指示所述第一数据已经被写入所述内存的所述写响应，所述缓存一致性节点向所述第一缓存返回指示所述第一数据已经被写回所述内存的所述写响应信号以直接结束对所述写请求的处理操作。
例如，在本公开的至少一个实施例提供的数据处理方法中，所述数据处理方法还包括：在所述缓存一致性节点将所述第一数据写入所述内存之后，所述缓存一致性节点将所述第一缓存的数据状态置为无效态、共享态或独占态，其中，所述无效态表示所述第一缓存没有缓存所述第一数据，所述共享态表示所述第一缓存与其他缓存均缓存有所述第一数据，所述独占态表示仅所述第一缓存中缓存有所述第一数据。
例如，在本公开的至少一个实施例提供的数据处理方法中，所述数据处理方法还包括：响应于收到第二缓存对所述第一数据的读请求且所述缓存一致性节点侧记录所述第一数据在所述第一缓存中处于独占状态或共享状态，所述缓存一致性节点向所述第一缓存发起监测信号；响应于所述第一缓存在发出所述写请求之后收到所述监测信号，所述第一缓存响应于所述监测信号向所述缓存一致性节点返回携带所述第一数据的监测响应。
例如，在本公开的至少一个实施例提供的数据处理方法中，所述数据处 理方法还包括：响应于收到所述监测响应，所述缓存一致性节点将所述第一数据返回给所述第二缓存；以及在收到所述第一数据之后，所述第二缓存向所述缓存一致性节点返回指示已经收到所述第一数据的报文以结束所述读请求。
例如，在本公开的至少一个实施例提供的数据处理方法中，所述响应于收到所述监测响应，所述缓存一致性节点将所述第一数据返回给所述第二缓存，包括：响应于收到所述监测响应，所述缓存一致性节点将所述第一数据返回给所述第二缓存，并且将所述第二缓存的数据状态置为独占态，所述独占态表示仅所述第二缓存中缓存有所述第一数据。
例如，在本公开的至少一个实施例提供的数据处理方法中，所述在所述缓存一致性节点将所述第一数据写入内存或将所述第一数据丢弃之后，所述缓存一致性节点向所述第一缓存返回写响应信号以直接结束对所述写请求的处理操作，包括：在收到所述报文之后，所述缓存一致性节点丢弃所述写请求写入所述缓存一致性节点侧的所述第一数据，并且向所述第一缓存返回所述写响应信号以直接结束对所述写请求的处理操作。
例如，在本公开的至少一个实施例提供的数据处理方法中，所述在收到所述报文之后，所述缓存一致性节点丢弃所述写请求写入所述缓存一致性节点侧的所述第一数据，包括：响应于在收到所述报文之后确定所述写请求写入所述缓存一致性节点侧的所述第一数据为无效数据，所述缓存一致性节点丢弃所述写请求写入所述缓存一致性节点侧的所述第一数据。
本公开的至少一个实施例还提供了一种电子设备，所述电子设备包括多个缓存和缓存一致性节点，所述多个缓存包括第一缓存，并且所述缓存一致性节点配置为响应于收到所述第一缓存要将第一数据写回内存的写请求，将所述第一数据写入内存或将所述第一数据丢弃，以及在所述缓存一致性节点将所述第一数据写入内存或将所述第一数据丢弃之后，向所述第一缓存返回写响应信号以直接结束对所述写请求的处理操作，其中，所述写请求携带所述第一数据，所述缓存一致性节点配置为维护由所述多个缓存中存储的数据的一致性。
例如，在本公开的至少一个实施例提供的电子设备中，所述缓存一致性节点还配置为：响应于收到所述第一缓存要将所述第一数据写回所述内存的所述写请求，确定所述第一缓存是否与所述缓存一致性节点侧记录的当前独 占所述第一数据的缓存相同，以及响应于确定所述第一缓存与所述缓存一致性节点侧记录的当前独占所述第一数据的缓存相同，将所述第一数据写入所述内存。
例如，在本公开的至少一个实施例提供的电子设备中，所述内存配置为：在所述缓存一致性节点将所述第一数据写入内存之后，向所述缓存一致性节点返回指示所述第一数据已经被写入所述内存的写响应，并且所述缓存一致性节点还配置为：响应于从所述内存收到指示所述第一数据已经被写入所述内存的所述写响应，向所述第一缓存返回指示所述第一数据已经被写回所述内存的所述写响应信号以直接结束对所述写请求的处理操作。
例如，在本公开的至少一个实施例提供的电子设备中，所述缓存一致性节点还配置为：响应于收到第二缓存对所述第一数据的读请求且所述缓存一致性节点侧记录所述第一数据在所述第一缓存中处于独占状态或共享状态，向所述第一缓存发起监测信号，并且所述第一缓存配置为：响应于所述第一缓存在发出所述写请求之后收到所述监测信号，向所述缓存一致性节点返回携带所述第一数据的监测响应。
本公开的至少一个实施例还提供了一种数据处理装置，所述数据处理装置包括存储器和处理器，所述存储器配置为存储计算机可执行指令，并且所述处理器配置为执行所述计算机可执行指令，其中，所述计算机可执行指令被所述处理器执行时实现如上任一实施例所述的方法。
本公开的至少一个实施例还提供了一种非暂时性存储介质，非暂时性地存储计算机可执行指令，其中，当所述计算机可执行指令由处理器执行时，实现如上任一实施例所述的方法。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1示出了一种电子设备的示意图。
图2A示出了一种电子设备进行数据读取的示意图。
图2B示出了一种电子设备进行数据写回的示意图。
图3A示出了本公开至少一实施例提供的一种数据处理方法的流程示意 图。
图3B示出了本公开至少一实施例提供的一种电子设备进行数据写回的示意图。
图4示出了本公开至少一实施例提供的一种电子设备存在读写冲突时的读写操作示意图。
图5示出了本公开至少一实施例提供的一种电子设备的示意图。
图6示出了本公开至少一实施例提供的一种数据处理装置的示意图。
图7示出了本公开至少一实施例提供的一种非暂时性存储介质的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持对本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。
在包括多个处理器(或处理器核)和多个高速缓存的计算机系统的运行过程中，相同地址的数据可能会同时存在不同的缓存中。为使得各个缓存中相同地址的数据始终保持一致，产生了基于目录的一致性协议。该协议可以追踪高速缓存中的数据的状态，例如，目录存储结构可以与高速缓存一样， 采用静态随机存储器(SRAM)实现。例如，目录存储结构也可以采用其他形式的存储器实现，只要能够实现目录存储即可。
图1示出了一种电子设备(或电子系统)100的示意图。如图1所示，电子设备100可以包括多个高速缓存(以下也简称“缓存”)1～n、处理器(或处理器核)1～n、互联网络、缓存一致性节点1～n、内存1～n和目录1～n等。
例如，缓存1～n中的每个缓存被配置为能够存储至少一个数据信息对应的数据存储信息。例如，缓存1～n可以分别包括一个或多个子缓存。
例如，缓存一致性节点1～n可以分别帮助追踪高速缓存1～n中的缓存数据状态，缓存数据状态例如包括：缓存1～n中只有该缓存数据的单一副本、有该缓存数据的多个副本、或者数据只存在主存中等状态。缓存一致性节点1～n会追踪处理器1～n(例如，图1中的每个处理器可以包括一个或多个子处理器)的高速缓存1～n的状态，并把追踪的状态信息(或目录信息)存储在目录1～n中。当缓存一致性节点侦听总线的过程中发现一致性事务后，会查询目录1～n中追踪的状态信息并发出相应的探针完成一致性维护。
例如，目录1～n被配置为存储缓存1～n中存储的数据信息对应的目录信息以维护缓存一致性。例如，目录包括多个存储组，每个存储组可以存储多条目录信息。例如，当需要向目录中存入目录信息时，目录根据映射关系将该目录信息放入相应的存储组。
例如，如图1所示，系统中的互联网络(例如片上网络(NOC)等)与缓存1～n直接耦接，并且还与缓存一致性节点1～n直接耦接。互联网络为信息传输的公共通信干线，例如，互联网络可以为由导线等电子元件组成的传输线束。
例如，如图1所示，缓存一致性节点1～n被配置为将目录1～n分别连接接到互联网络，缓存一致性节点1～n被配置为将内存1～n分别连接接到互联网络，从而维护缓存1～n中存储的所有数据的一致性。
例如，在非一致性内存访问架构(Non Uniform Memory Access，NUMA)中，不同的处理器(或处理器核)与内存器件的组合从属于不同的节点，因此基于目录一致性的设计会在每个内存控制器的附近设置一个静态随机存储器(SRAM)结构的目录。在NUMA架构中，每个节点都有自己的本地内存。
图2A示出了一种电子设备进行数据读取的示意图。图2B示出了一种 电子设备进行数据回写的示意图。
例如，在图2A中，主设备0可以对应于图1中的缓存1～n中的任何一个，从设备可以对应于图1中的缓存一致性节点1～n中的任何一个，MEM可以对应于图1中的内存1～n中的任何一个。例如，如图2A所示，当主设备0向从设备发起独占请求RdE(参见下文的表2)以获取独占数据，由于系统(例如电子系统)中可能存在多个主设备，所以从设备需要管理多个主设备之间的数据一致性。例如，系统中的从设备侧可以采用基于目录(Directory)的缓存一致性协议，由目录记录数据被哪个主设备缓存，以及该数据当前在对应的主设备中所处的状态。
例如，如图2A所示，当从设备收到独占请求RdE，且当前从设备侧对应的目录为例如图2A中用Dir@I表示的无效态I(参见下文的表1，例如，无效态I表示当前没有主设备缓存此数据(例如，请求所访问的地址对应的数据))时从设备通过向内存发送读请求Rdmem且接收内存向从设备返回的数据响应rddat，从而直接读取主存(例如，内存)数据，并向作为请求者的主设备0返回独占数据响应DatRspE(参见下文的表5)，并将从设备侧对应的目录置为E:Master0(例如图2A中用Dir@E:Master0表示)，从而记录主设备0缓存此数据且为独占态(E：Exclusive)，主设备0收到独占数据响应DatRspE后向从设备发送报文ACK以结束读请求。
主设备处一般缓存较多的数据，且主设备存在溢出的场景，需要从主设备将溢出的数据写回到从设备。例如，如图2B所示，当主设备0的缓存数据发生溢出时，主设备0向从设备发起写回请求(图2B中仅以WBI为例进行说明，但不限于此写回请求)，并将要写回到内存的数据例如通过信号WrDat一并发送给从设备，从设备侧确认收到写回数据后向主设备0返回写响应WrRap，主设备0收到写响应WrRap后向从设备发送报文(或写响应)ACK。例如，如图2B所示，从设备收到主设备0发送的报文ACK后，从设备侧对应的目录状态被从Dir@E:Master0置为Dir@I。例如，从设备侧收到报文ACK后通过向内存发送写请求Rdmem以将待写回的数据写回内存，且接收内存向从设备返回的数据写响应WrRap，以结束写回请求。
在现有的缓存一致性协议中，读写事务都需要携带ACK报文，ACK报文会延长事务在从设备中的生命周期，即占用从设备缓冲区(例如，缓存或其他能够用于实现目录的存储区)的时间变长，降低从设备缓冲区的周转率 和浪费资源，并且ACK报文传输需要浪费一定的功耗。
本公开至少一个实施例提供一种数据处理方法。例如，本公开提供的一种数据处理方法包括：响应于收到第一缓存要将第一数据写回内存的写请求，缓存一致性节点将第一数据写入内存或将第一数据丢弃，其中，写请求携带第一数据，缓存一致性节点配置为维护由多个缓存中存储的数据的一致性，多个缓存包括第一缓存；以及在缓存一致性节点将第一数据写入内存或将第一数据丢弃之后，缓存一致性节点向第一缓存返回写响应信号以直接结束对写请求的处理操作。
在本公开的上述实施例的数据处理方法中，通过回写事务和目录的比较，进行场景识别，主设备收到写响应后直接结束写事务处理，不需要再向从设备发送ACK报文，从而降低ACK报文的数量，减少协议对ACK报文的需求，减少ACK报文传输产生的功耗和延时以及带宽占用，并且优化了主设备侧缓冲区的周转率，在相同性能下主设备侧需要的缓冲区数量更少，节省面积和功耗。
本公开至少一些实施例还提供了一种电子设备，该电子设备包括多个缓存和缓存一致性节点。多个缓存包括第一缓存，缓存一致性节点被配置为响应于收到第一缓存要将第一数据写回内存的写请求，将第一数据写入内存或将第一数据丢弃，以及在缓存一致性节点将第一数据写入内存或将第一数据丢弃之后，向第一缓存返回写响应信号以直接结束对写请求的处理操作，其中，写请求携带第一数据，缓存一致性节点配置为维护由多个缓存中存储的数据的一致性。
本公开上述实施例的电子设备的技术效果与上述数据处理方法的技术效果相同，因此不再赘述。
上述实施例中，第一缓存可以是多个缓存中的任一缓存，第一数据可以是例如任何被访问的地址对应的数据，即，这里的“第一”(以及“第二”等)仅用于标识作为描述对象的缓存或数据，而非特指某一特定的缓存或数据。
下面将结合具体示例对本公开的各个实施例进行说明。
图3A示出了本公开至少一实施例提供的一种数据处理方法的流程示意图。如图3A所示，在本公开的一些实施例中，数据处理方法包括以下步骤S101-S102。
步骤S101，响应于收到第一缓存要将第一数据写回内存的写请求，缓存一致性节点将第一数据写入内存或将第一数据丢弃，其中，写请求携带第一数据，缓存一致性节点配置为维护由多个缓存中存储的数据的一致性，多个缓存包括第一缓存。
步骤S102，在缓存一致性节点将第一数据写入内存或将第一数据丢弃之后，缓存一致性节点向第一缓存返回写响应信号以直接结束对写请求的处理操作。
图3B示出了本公开至少一实施例提供的一种电子设备进行数据回写的示意图。例如，如图3B所示，响应于收到第一缓存(或“主设备0”)要将第一数据写回内存的写请求，缓存一致性节点(或“从设备”)将第一数据写入内存MEM。例如，写请求携带第一数据，缓存一致性节点配置为维护由多个缓存中存储的数据的一致性，该多个缓存包括第一缓存。例如，在缓存一致性节点将第一数据写入内存MEM，缓存一致性节点向第一缓存返回写响应信号WrRsp以直接结束对写请求的处理操作。
图4示出了本公开至少一实施例提供的一种电子设备存在读写冲突时的读写操作示意图。例如，如图4所示，响应于收到第一缓存(或“主设备0”)要将第一数据写回内存的写请求，缓存一致性节点(或“从设备”)将第一数据丢弃。例如，写请求携带第一数据，缓存一致性节点配置为维护由多个缓存中存储的数据的一致性，该多个缓存包括第一缓存。例如，在缓存一致性节点将第一数据丢弃之后，缓存一致性节点向第一缓存返回写响应信号WrRsp以直接结束对写请求的处理操作。
需要说明的是，虽然本公开的例如图3B和图4中示出了具体的第一缓存(例如，主设备0)、第二缓存(例如，主设备1)、缓存一致性节点(例如，从设备)和内存(例如，MEM)及其相关的具体操作，但图中示出的内容仅为示例性的，以方便对本公开的实施例进行说明，但本公开的实施例不限于此，在本公开的具体示例的基础上能够想到的任何其他操作均包括在本公开的范围内。
以下结合表1-9对本公开的实施例的缓存一致性协议的一些规定进行示例性描述。
例如，本公开的实施例的协议规定的主设备(或缓存)均有多种状态，如表1中所示：
表1
例如，在表1中，缓存状态可以为第一缓存的状态，主存可以是内存MEM。例如，第一缓存可以包括M状态、E状态、S状态和I状态。M状态表示第一缓存独占相应的数据，且该数据已被修改；E状态表示第一缓存独占相应的数据，且该数据未被修改；S状态表示第一缓存与其他主设备共享相应的数据；I状态表示第一缓存未缓存相应的数据。例如，当第一缓存为M状态时，由于第一缓存已经修改了相应的数据，因此内存MEM中对应的数据已经无效，此时其他缓存均为未缓存有此修改后的数据的I状态；当第一缓存为E状态时，其他缓存均为未缓存有此数据的I状态；当第一缓存为S状态时，存在其他缓存处于共享此数据的S状态；当第一缓存为I状态时，其他缓存可以处于M状态、E状态、S状态和I状态中的任何一种状态。
需要说明的是，在本公开的实施例中，主设备(例如，第一缓存)的状态不限以上列出的四种状态，主设备可以根据不同需要而具有其他不同的状态。
例如，表2为本公开的协议规定的主设备可以发出的请求类型，以及对应的缓存(Cache)状态转换和从设备响应报文。
表2

下面以主设备为第一缓存时为例进行说明。
例如，在表2中，请求类型可以为第一缓存向从设备发起的请求类型。例如，第一缓存可以发起的读请求类型可以包括RdE(获取独占数据副本)、RdD(获取非I状态的数据副本，即需要缓存此数据副本)、RdS(获取共享数据副本)、RdI(获取数据快照，不缓存此数据副本)和RdEE(获取数据独占权限，不获取数据)。本公开的实施例不限于此，第一缓存也可以根据需要发起其他不同的读请求类型。
例如，当第一缓存向从设备发起的读请求类型为RdE时，第一缓存发起请求时的缓存状态(或缓存数据状态)可以为I状态、S状态或E状态；当RdE请求结束时，第一缓存的缓存状态可以为E状态(在此情况下，从设备向第一缓存返回响应DatRspE(参见下文的表6)，使得从设备获取独占态数据副本的响应)或M状态(在此情况下，从设备返回响应DatRspM(参见下的文表6)，使得从设备获取修改态数据副本的响应)。例如，当第一缓存向从设备发起的读请求类型为RdD时，第一缓存发起请求时的缓存状态可以为I状态；当RdD请求结束时，第一缓存的缓存状态可以为S状态(在此情况下，从设备向第一缓存返回响应DatRspS(参见见下文的表6)，使得从设备获取共享态数据副本的响应)、E状态(在此情况下，从设备向第一缓存返回响应DatRspE)或M状态(在此情况下，从设备向第一缓存返回响应DatRspM)。例如，当第一缓存向从设备发起的读请求类型为RdS时，第一缓存发起请求时的缓存状态可以为I状态；当RdS请求结束时，第一缓存的 缓存状态可以为S状态(在此情况下，从设备向第一缓存返回响应DatRspS)。例如，当第一缓存向从设备发起的读请求类型为RdI时，第一缓存发起请求时的缓存状态可以为I状态；当RdI请求结束时，第一缓存的缓存状态可以为I状态(在此情况下，从设备向第一缓存返回响应DatRspI(参见下文的表6)，使得从设备获取数据副本的响应)。例如，当第一缓存向从设备发起的读请求类型为RdEE时，第一缓存发起请求时的缓存状态可以为I状态或S状态；当RdEE请求结束时，第一缓存的缓存状态可以为E状态(在此情况下，从设备返回响应RspE(参见下文的表6)，使得从设备获取独占权限的响应)。
例如，在表2中，第一缓存可以发起的写请求类型可以包括WBI(将已缓存的数据副本写回主存，本缓存置为无效I态)、WBS(将已缓存的数据副本写回主存，本缓存置为共享S态)和WBE(将已缓存的数据副本写回主存，本缓存置为独占E态)。本公开的实施例不限于此，第一缓存也可以根据需要发起其他不同的写请求类型。
例如，当第一缓存向从设备发起的写请求类型为WBI时，第一缓存发起请求时的缓存状态可以为M状态；当写请求WBI结束时，第一缓存的缓存状态可以为I状态(在此情况下，从设备向第一缓存返回响应WrRsp)。例如，当第一缓存向从设备发起的写请求类型为WBS时，第一缓存发起请求时的缓存状态可以为M状态；当写请求WBS结束时，第一缓存的缓存状态可以为I状态(在此情况下，从设备向第一缓存返回响应WrRsp)或S状态(在此情况下，从设备向第一缓存返回响应WrRsp)。例如，当第一缓存向从设备发起的写请求类型为WBE时，第一缓存发起请求时的缓存状态可以为M状态；当写请求WBE结束时，第一缓存的缓存状态可以为I状态(在此情况下，从设备向第一缓存返回响应WrRsp)、S状态(在此情况下，从设备向第一缓存返回响应WrRsp)或E状态(在此情况下，从设备向第一缓存返回响应WrRsp)。
例如，在图3B和图4中，第一缓存写请求不限于WBI，写请求也可以是表2中示出的WBS或WBE。例如，第一缓存的缓存数据溢出时，第一缓存可以向从设备发起写请求WBI，响应于收到第一缓存要将第一数据写回内存MEM的写请求WBI，缓存一致性节点将第一数据写入内存MEM(如图3B所示)或将第一数据丢弃(如图4所示)。例如，在缓存一致性节点将第 一数据写入内存MEM或将第一数据丢弃之后，缓存一致性节点向第一缓存返回写响应信号WrRsp以直接结束对写请求的处理操作。例如，第一缓存的缓存数据溢出时，第一缓存可以向从设备发起写请求WBS，响应于收到第一缓存要将第一数据写回内存MEM的写请求WBS，缓存一致性节点将第一数据写入内存MEM(如图3B所示)或将第一数据丢弃(如图4所示)。例如，在缓存一致性节点将第一数据写入内存MEM或将第一数据丢弃之后，缓存一致性节点向第一缓存返回写响应信号WrRsp以直接结束对写请求的处理操作。例如，第一缓存的缓存数据溢出时，第一缓存可以向从设备发起写请求WBE，响应于收到第一缓存要将第一数据写回内存MEM的写请求WBE，缓存一致性节点将第一数据写入内存MEM(如图3B所示)或将第一数据丢弃(如图4所示)。例如，在缓存一致性节点将第一数据写入内存MEM或将第一数据丢弃之后，缓存一致性节点向第一缓存返回写响应信号WrRsp以直接结束对写请求的处理操作。
例如，响应于收到第一缓存要将第一数据写回内存MEM的写请求，缓存一致性节点确定第一缓存是否与缓存一致性节点侧记录的当前独占第一数据的缓存相同，以及响应于确定第一缓存与缓存一致性节点侧记录的当前独占第一数据的缓存相同，缓存一致性节点将第一数据写入内存MEM。
例如，如图3B所示，响应于收到主设备0要将第一数据写回内存MEM的写请求，从设备确定主设备0是否与从设备侧记录的当前独占第一数据的缓存相同。例如，如图3B中所示，响应于确定主设备0与从设备侧记录的当前独占第一数据的缓存相同(例如，从设备侧记录了Src:Master0＝＝Dir@E:Master0)，从设备通过写内存操作Wrmem将第一数据写回内存MEM，内存MEM收到写内存操作Wrmem后向缓存一致性节点返回写响应WrRsp以向从设备指示内存MEM已经成功收到第一数据。例如，响应于确定主设备0与从设备侧记录的当前独占第一数据的缓存不相同(例如，从设备侧记录了Src:Master0！＝Dir@E:Master0)，则判断从设备没有将第一数据写入内存MEM的权限，并且从设备不执行将第一数据写入内存MEM的操作。
例如，在缓存一致性节点将第一数据写入内存之后，内存向缓存一致性节点返回指示第一数据已经被写入内存的写响应，以及响应于从内存收到指示第一数据已经被写入内存的写响应，缓存一致性节点向第一缓存返回指示 第一数据已经被写回内存的写响应信号以直接结束对写请求的处理操作。
例如，如图3B所示，在从设备将第一数据写入内存MEM之后，内存MEM向从设备返回指示第一数据已经被写入内存MEM的写响应WrRsp，以及响应于从内存MEM收到指示第一数据已经被写入内存MEM的写响应WrRsp，从设备向主设备0返回指示第一数据已经被写回内存MEM的写响应信号WrRsp以直接结束对写请求的处理操作。例如，此时主设备0不需要再向从设备发送报文就直接结束对写请求的处理操作。
例如，在缓存一致性节点将第一数据写入内存之后，缓存一致性节点将第一缓存的数据状态置为无效态、共享态或独占态。例如，无效态表示第一缓存没有缓存第一数据，共享态表示第一缓存与其他缓存均缓存有第一数据，独占态表示仅第一缓存中缓存有第一数据。
例如，在从设备将第一数据写回内存MEM之后，从设备将多个缓存中的第一缓存(例如，主设备0)的数据状态为无效态(I状态)、共享态(S状态)或独占态(例如，E状态)。例如，无效态表示第一缓存没有缓存第一数据，共享态表示第一缓存与其他缓存均缓存有第一数据，独占态表示仅第一缓存中缓存有第一数据。
例如，如以上表2所示，如果第一缓存向从设备发起写请求WBI，则当写请求WBI结束时，第一缓存的缓存状态可以为I状态。例如，如果第一缓存向从设备发起写请求WBS，则当写请求WBS结束时，第一缓存的缓存状态可以为I状态(例如，第一缓存将数据写回内存MEM后，第一缓存中缓存的该数据被其他数据替换)或S状态(例如，第一缓存将数据写回内存MEM后，第一缓存中缓存的该数据未被其他数据替换)。例如，如果第一缓存向从设备发起写请求WBE，则当写请求WBE结束时，第一缓存的缓存状态可以为I状态(例如，第一缓存将数据写回内存MEM后，第一缓存中缓存的该数据被其他数据替换)、S状态(例如，第一缓存写回内存MEM的数据被其他缓存共享)或E状态(例如，第一缓存写回内存MEM的数据未被其他缓存共享，并且第一缓存将数据写回内存MEM后，第一缓存中缓存的该数据未被其他数据替换)。
例如，如图4所示，响应于收到第二缓存(或“主设备1”)对第一数据的读请求且缓存一致性节点侧(例如，从设备对应的目录)记录第一数据在第一缓存(或“主设备0”)中处于独占状态或共享状态，缓存一致性节点向 第一缓存发起监测信号(例如，ExpI)；响应于第一缓存在发出写请求之后收到监测信号，第一缓存响应于监测信号向缓存一致性节点返回携带第一数据的监测响应(例如，ExpRspIDat)。
例如，表3为本公开的协议规定的监测信号类型及其说明，检测信号Exp*用于监测主设备处的缓存状态和数据，并将被监测的主设备置为相应的状态。
表3
表4为本公开的协议规定的监测响应类型，即主设备被检测信号Exp*监测时可能向从设备返回的监测响应。
表4
表5为本公开的协议规定的非监测类响应事务类型及其说明。
表5

表6为本公开的协议规定的监测事务在主设备侧的状态转移表以及监测响应动作，定义了主设备侧缓存被监测后可能转换到的目标状态，以及发送相应的监测响应报文。
表6
例如，如表6中所示，当第一缓存收到检测信号ExpI后，如果第一缓存的当前缓存状态为I、S、E或M，则处理监测信号后第一缓存的状态为I，第一缓存向缓存一致性节点返回检测响应ExpRspI(例如，在第一缓存的当前状态为I时)或ExpRspIDat(例如，在第一缓存的当前状态为S、E或M时)。
例如，当第一缓存收到检测信号ExpS后，如果第一缓存的当前缓存状态为I，则处理监测信号后第一缓存的状态为I，第一缓存向缓存一致性节点返回检测响应ExpRspI；当第一缓存收到检测信号ExpS后，如果第一缓存的当前缓存状态为S，则处理监测信号后第一缓存的状态为S，第一缓存向缓存一致性节点返回检测响应ExpRspS；当第一缓存收到检测信号ExpS后， 如果第一缓存的当前缓存状态为E或M，则处理监测信号后第一缓存的状态为S，第一缓存向缓存一致性节点返回检测响应ExpRspS(例如，在第一缓存执行写请求WBS或WBE时)或ExpRspSDat(例如，在第一缓存执行写请求WBI时)。
例如，当第一缓存收到检测信号ExpE后，如果第一缓存的当前缓存状态为I，则处理监测信号后第一缓存的状态为I，第一缓存向缓存一致性节点返回检测响应ExpRspI；当第一缓存收到检测信号ExpE后，如果第一缓存的当前缓存状态为S，则处理监测信号后第一缓存的状态为S，第一缓存向缓存一致性节点返回检测响应ExpRspS；当第一缓存收到检测信号ExpE后，如果第一缓存的当前缓存状态为E或M，则处理监测信号后第一缓存的状态为E或M，第一缓存向缓存一致性节点返回检测响应ExpRspE(例如，在第一缓存执行写请求WBS或WBE时)或ExpRspEDat(例如，例如，在第一缓存执行写请求WBI时)。
表7为本公开的协议规定的监测事务在主设备侧处理且存在冲突的情况，即监测事务到达主设备时，主设备当前已经对相同地址的缓存行发起了读事务(或读请求)Rd*或写事务(或写请求)WB*。
表7
例如，如表7中所示，当缓存一致性节点向第一缓存发送的检测信号为 ExpI，且监测事务到达第一缓存时，第一缓存已经对相同地址的缓存行发起了读事务Rd*时，如果第一缓存当前状态为I、S或E，则处理监测信号后第一缓存的状态为I，第一缓存向缓存一致性节点返回检测响应ExpRspI(例如，在主设备的状态为I时)或ExpRspIDat(例如，在第一缓存的状态为S或E时)；当缓存一致性节点向第一缓存发送的检测信号为ExpI，且监测事务到达第一缓存时，第一缓存已经对相同地址的缓存行发起了写事务WB*时，如果第一缓存当前状态为M，则第一缓存向缓存一致性节点返回检测响应ExpRsplDat，处理监测信号后第一缓存的状态为I。
例如，如表7中所示，当缓存一致性节点向第一缓存发送的检测信号为ExpS，且监测事务到达第一缓存时，第一缓存已经对相同地址的缓存行发起了读事务Rd*时，如果第一缓存当前状态为I、S或E，则处理监测信号后第一缓存的状态为I，第一缓存向缓存一致性节点返回检测响应ExpRspI(例如，在第一缓存的状态为I时)或ExpRspIDat(例如，在第一缓存的状态为S或E时)；当缓存一致性节点向第一缓存发送的检测信号为ExpS，且监测事务到达第一缓存时，第一缓存已经对相同地址的缓存行发起了读事务WB*时，如果第一缓存当前状态为M，第一缓存向缓存一致性节点返回检测响应ExpRsplDat，处理监测信号ExpS后第一缓存的状态为I。
例如，如表7中所示，当缓存一致性节点向第一缓存发送的检测信号为ExpE，且监测事务到达第一缓存时，第一缓存已经对相同地址的缓存行发起了读事务Rd*时，如果第一缓存当前状态为I、S或E，则处理监测信号后第一缓存的状态为I，第一缓存向缓存一致性节点返回检测响应ExpRspI(例如，在第一缓存的状态为I时)或ExpRspIDat(例如，在第一缓存的状态为S或E时)；当缓存一致性节点向第一缓存发送的检测信号为ExpE，且监测事务到达第一缓存时，第一缓存已经对相同地址的缓存行发起了读事务WB*时，如果第一缓存当前状态为M，第一缓存向缓存一致性节点返回检测响应ExpRsplDat，处理监测信号ExpE后第一缓存的状态为I。
表8为本公开的协议定义的从设备收到主设备读写请求后，可能需要根据目录状态进行的状态转移(包括触发监测命令，向主设备返回响应命令，或对内存数据进行读写的处理)。
表8

例如，如表8中所示，响应于收到第二缓存对第一数据的读请求为RdE且第一数据在缓存一致性节点对应的目录中处于I状态，缓存一致性节点直接从内存中读取第一数据，并将第一数据返回给第二缓存。例如，响应于收到第二缓存对第一数据的读请求RdE且缓存一致性节点侧(例如，从设备对应的目录)记录第一数据在缓存一致性节点对应的目录中处于S状态或独占状态E，缓存一致性节点向第一缓存发起监测信号ExpI(监测目标缓存，获取最新数据副本，并将其缓存数据置为无效状态)。
例如，响应于收到监测响应，缓存一致性节点将第一数据返回给第二缓存，以及在收到第一数据之后，第二缓存向缓存一致性节点返回指示已经收到第一数据的报文以结束读请求。例如，如图4所示，响应于收到监测响应ExpRspIDat，从设备响应于监测响应ExpRspIDat而(例如，通过响应信号DatRspM)将第一数据返回给主设备1，并且将主设备1在从设备侧的数据 状态置为独占态(例如，从设备侧记录Dir@E:Master1)，独占态(或Dir@E:Master1)表示仅主设备1中缓存有第一数据。例如，在收到第一数据之后，主设备1向从设备返回指示已经收到第一数据的报文ACK以结束读请求RdE。
例如，在收到报文之后，缓存一致性节点丢弃写请求写入缓存一致性节点侧的第一数据，并且向第一缓存返回写响应信号以直接结束对写请求的处理操作。例如，如图4所示，在从设备收到主设备1的报文ACK之后，主设备之前发出的读请求RdE处理完成，从设备侧的处于阻塞状态(在从设备处理主设备1发起的读请求后处于阻塞状态(即，由于从设备对相同地址事务同一时刻只能处理一个，因此在主设备1的RdE处理完成之前主设备0所发起的写请求WB*一直处于阻塞状态))的主设备0之前发出的写请求WB*被唤醒继续处理，此时由于从设备侧记录了主设备1已经获取了第一数据的独占状态，而写请求由主设备0发起，因此主设备0的写事务中的数据已经是过期的无效数据，所以从设备判断此写事务或写操作由于冲突应为无效数据(如图4中所示，Src:Master0！＝Dir@E:Master1，即，请求回写的主设备0不是从设备指向的独占第一数据的主设备1)，直接丢弃由主设备0已经写入从设备的数据。例如，从设备确定写请求写入从设备侧的第一数据为无效数据，从设备丢弃写请求写入从设备侧的第一数据，并且向主设备0返回写响应信号WrRsp以直接结束对写请求的处理操作。例如，从设备收到写响应信号WrRsp后直接结束对应写事务处理，不需要再向从设备发送报文ACK。
例如，响应于收到第二缓存对第一数据的读请求为RdD、RdS或RdI且第一数据在缓存一致性节点对应的目录中处于I状态或S状态，缓存一致性节点可以直接从内存中读取第一数据，并将第一数据返回给第二缓存。例如，响应于收到第二缓存对第一数据的读请求RdD、RdS或RdI且缓存一致性节点侧(例如，从设备对应的目录)记录第一数据在缓存一致性节点对应的目录中处于独占状态E，缓存一致性节点向第一缓存发起监测信号ExpS(监测目标缓存，获取最新数据副本，并将其缓存数据置为无效或共享状态)。
例如，响应于收到监测响应，缓存一致性节点将第一数据返回给第二缓存，以及在收到第一数据之后，第二缓存向缓存一致性节点返回指示已经收 到第一数据的报文以结束读请求。例如，如图4所示，响应于收到监测响应ExpRspIDat，从设备响应于监测响应ExpRspIDat而(例如，通过响应信号DatRspM)将第一数据返回给主设备1，并且将主设备1在从设备侧的数据状态置为独占态(例如，从设备侧记录Dir@E:Master1)，独占态(或Dir@E:Master1)表示仅主设备1中缓存有第一数据。例如，在收到第一数据之后，主设备1向从设备返回指示已经收到第一数据的报文ACK以结束读请求(例如，RdD或RdS)。
例如，在收到报文之后，缓存一致性节点丢弃写请求写入缓存一致性节点侧的第一数据，并且向第一缓存返回写响应信号以直接结束对写请求的处理操作。例如，如图4所示，在从设备收到主设备1的报文ACK之后，主设备之前发出的读请求RdD、RdS或RdI处理完成，从设备侧的处于阻塞状态的主设备0之前发出的写请求WB*被唤醒继续处理，此时由于从设备侧记录了主设备1已经获取了第一数据的独占状态或共享状态，而写请求由主设备0发起，因此主设备0的写事务中的数据已经是过期的无效数据，所以从设备判断此写事务或写操作由于冲突应为无效数据，直接丢弃由主设备0已经写入从设备的数据。例如，从设备确定写请求写入从设备侧的第一数据为无效数据，从设备丢弃写请求写入从设备侧的第一数据，并且向主设备0返回写响应信号WrRsp以直接结束对写请求的处理操作。例如，从设备收到写响应信号WrRsp后直接结束对应写事务处理，不需要再发送报文ACK。
例如，响应于收到第二缓存对第一数据的读请求为RdEE且第一数据在缓存一致性节点对应的目录中处于I状态，缓存一致性节点向第二缓存返回响应RspE(无数据监测响应，被监测缓存置为E态或M态)以结束读请求RdEE。例如，响应于收到第二缓存对第一数据的读请求RdEE且缓存一致性节点侧(例如，从设备对应的目录)记录第一数据在缓存一致性节点对应的目录中处于S状态或独占状态E，缓存一致性节点向第一缓存发起监测信号ExpE(监测目标缓存，获取最新数据副本，不改变其缓存数据状态)。
例如，响应于收到监测响应，缓存一致性节点将第一数据返回给第二缓存，以及在收到第一数据之后，第二缓存向缓存一致性节点返回指示已经收到第一数据的报文以结束读请求。例如，如图4所示，响应于收到监测响应ExpRspIDat，从设备响应于监测响应ExpRspIDat而(例如，通过响应信号DatRspM)将第一数据返回给主设备1。例如，在收到第一数据之后，主设 备1向从设备返回指示已经收到第一数据的报文ACK以结束读请求RdEE。
例如，在收到报文之后，缓存一致性节点丢弃写请求写入缓存一致性节点侧的第一数据，并且向第一缓存返回写响应信号以直接结束对写请求的处理操作。例如，如图4所示，在从设备收到主设备1的报文ACK之后，主设备之前发出的读请求RdEE处理完成，从设备侧的处于阻塞状态的主设备0之前发出的写请求WB*被唤醒继续处理，此时由于从设备侧记录了主设备0已经不是独占第一数据的状态，而写请求由主设备0发起，因此主设备0的写事务中的数据已经是过期的无效数据，所以从设备判断此写事务或写操作由于冲突应为无效数据，直接丢弃由主设备0已经写入从设备的数据。例如，从设备确定写请求写入从设备侧的第一数据为无效数据，从设备丢弃写请求写入从设备侧的第一数据，并且向主设备0返回写响应信号WrRsp以直接结束对写请求的处理操作。例如，从设备收到写响应信号WrRsp后直接结束对应写事务处理，不需要再发送报文ACK。
例如，响应于收到第二缓存向缓存一致性节点发送对数据的写请求(例如，WBI、WBS或WBE)，无论此时目录处于什么状态(例如，I、S或E)，均不会不会触发检测信号，缓存一致性节点向第二缓存返回响应WrRsp。例如，如果此时缓存一致性节点侧记录第二缓存需要写入的数据处于独占状态且指向发起写请求WBI的第二缓存，则将该数据写入内存，否则丢弃数据。
表9为本公开的协议规定的从设备从主设备接收响应后的状态转换表。
表9

例如，如表9中所示，如果第一缓存向缓存一致性节点发送响应信号ExpRspI、ExpRspS或ExpRspE，且缓存一致性节点收到第二缓存的任何类型的读请求(例如，缓存一致性节点响应于收到第二缓存的读请求，创建读请求事务处理表项，记录当前读请求事务相关的状态)，则在收到第一缓存向缓存一致性节点发送的响应信号ExpRspI、ExpRspS或ExpRspE后，缓存一致性节点需要读取内存数据。例如，在缓存一致性节点读取内存数据之后，将该数据发送给第二缓存，并且将与第二缓存的读请求对应的读请求事务处理表项的状态置为等待确认状态(例如，WaitACK)，等待第二缓存发送确认已经成功接收数据的确认信号(ACK)。
例如，如表9中所示，如果第一缓存向缓存一致性节点发送响应信号ExpRspIDat，且缓存一致性节点收到第二缓存的请求类型为读请求RdI(例如，在缓存一致性节点响应于收到第二缓存的读请求RdI，创建读请求事务处理表项，记录当前读请求事务相关的状态)，则在收到第一缓存向缓存一致性节点发送的响应信号ExpRspIDat后，缓存一致性节点向第二缓存发送携带数据的响应信号DatRspI，并且将与第二缓存的读请求RdI对应的读请求事务处理表项的状态置为等待确认状态(例如，WaitACK)，等待第二缓存发送确认已经成功接收数据的确认信号(ACK)。
例如，如表9中所示，如果第一缓存向缓存一致性节点发送响应信号ExpRspIDat，且缓存一致性节点收到第二缓存的请求类型为读请求RdS(例如，在缓存一致性节点响应于收到第二缓存的读请求RdS后，创建读请求事务处理表项，记录当前读请求事务相关的状态)，则在收到第一缓存向缓存一致性节点发送的响应信号ExpRspIDat后，缓存一致性节点向第二缓存发送携带数据的响应信号DatRspS，并且将与第二缓存的读请求RdS对应的读请求事务处理表项的状态置为等待确认状态(例如，WaitACK)，等待第二缓存发送确认已经成功接收数据的确认信号(ACK)。
例如，如表9中所示，如果第一缓存向缓存一致性节点发送响应信号ExpRspIDat，且缓存一致性节点收到第二缓存的请求类型为读请求RdD(例如，在缓存一致性节点响应于收到第二缓存的读请求RdD后，创建读请求 事务处理表项，记录当前读请求事务相关的状态)，则在收到第一缓存向缓存一致性节点发送的响应信号ExpRspIDat后，缓存一致性节点向第二缓存发送携带数据的响应信号DatRspE(记录第二缓存独占此数据)或DatRspM(记录第二缓存独占此被修改后的数据)，并且将与第二缓存的读请求RdD对应的读请求事务处理表项的状态置为等待确认状态(例如，WaitACK)，等待第二缓存发送确认已经成功接收数据的确认信号(ACK)。
例如，如表9中所示，如果第一缓存向缓存一致性节点发送响应信号ExpRspIDat，且缓存一致性节点收到第二缓存的请求类型为读请求RdE(例如，在缓存一致性节点响应于收到第二缓存的读请求RdE后，创建读请求事务处理表项，记录当前读请求事务相关的状态)，则在收到第一缓存向缓存一致性节点发送的响应信号ExpRspIDat后，缓存一致性节点向第二缓存发送携带数据的响应信号DatRspE(记录第二缓存独占此数据)或DatRspM(记录第二缓存独占此被修改后的数据)，并且将与第二缓存的读请求RdE对应的读请求事务处理表项的状态置为等待确认状态(例如，WaitACK)，等待第二缓存发送确认已经成功接收数据的确认信号(ACK)。
例如，如表9中所示，如果第一缓存向缓存一致性节点发送响应信号ExpRspSDat，且缓存一致性节点收到第二缓存的请求类型为读请求RdS或RdD(例如，在缓存一致性节点响应于收到第二缓存的读请求RdS或RdD后，创建读请求事务处理表项，记录当前读请求事务相关的状态)，则在收到第一缓存向缓存一致性节点发送的响应信号ExpRspSDat后，缓存一致性节点向第二缓存发送携带数据的响应信号DatRspS(记录第二缓存共享此数据)，并且将与第二缓存的读请求RdS或RdD对应的读请求事务处理表项的状态置为等待确认状态(例如，WaitACK)，等待第二缓存发送确认已经成功接收数据的确认信号(ACK)。
例如，如表9中所示，如果第一缓存向缓存一致性节点发送响应信号ExpRspEDat，且缓存一致性节点收到第二缓存的请求类型为读请求RdI(例如，在缓存一致性节点响应于收到第二缓存的读请求RdI后，创建读请求事务处理表项，记录当前读请求事务相关的状态)，则在收到第一缓存向缓存一致性节点发送的响应信号ExpRspEDat后，缓存一致性节点向第二缓存发送携带数据的响应信号DatRspI(记录第二缓存获取此数据的副本)，并且将与第二缓存的读请求RdI对应的读请求事务处理表项的状态置为等待确认状 态(例如，WaitACK)，等待第二缓存发送确认已经成功接收数据的确认信号(ACK)。
例如，如表9中所示，如果第一缓存向缓存一致性节点发送响应信号ACK，且缓存一致性节点收到第二缓存的请求类型为读请求Rd*(例如，在缓存一致性节点响应于收到第二缓存的读请求Rd*后，创建读请求事务处理表项或写请求事务处理表项，记录当前读请求事务相关的状态)，则在收到第一缓存向缓存一致性节点发送的响应信号ACK后，缓存一致性节点将读请求事务处理表项的状态置为结束状态，以确认已经成功完成数据的读取。
在本公开的实施例的数据处理方法中，通过回写事务和目录的比较，进行场景识别，主设备收到写响应后直接结束写事务处理，不需要再向从设备发送ACK报文，从而降低ACK报文的数量，减少协议对ACK报文的需求，减少ACK报文传输产生的功耗和延时以及带宽占用，并且优化了主设备侧缓冲区的周转率，在相同性能下主设备侧需要的缓冲区数量更少，节省面积和功耗。
图5示出了本公开至少一实施例提供的一种电子设备60的示意图。例如，该电子设备60包括缓存一致性节点605、第一缓存606和第二缓存607。例如，缓存一致性节点605配置为响应于收到第一缓存606要将第一数据写回内存的写请求，将第一数据写入内存或将第一数据丢弃，以及在缓存一致性节点605将第一数据写入内存或将第一数据丢弃之后，向第一缓存606返回写响应信号以直接结束对写请求的处理操作。例如，该写请求携带第一数据，缓存一致性节点605配置为维护由多个缓存中存储的数据的一致性。本公开的电子设备60包括的缓存不限于图5中示出的两个缓存(第一缓存606和第二缓存607)，电子设备60的数量可以根据需要设置为任何数量。
例如，缓存一致性节点605还配置为：响应于收到第一缓存606要将第一数据写回内存的写请求，确定第一缓存606是否与缓存一致性节点605侧记录的当前独占第一数据的缓存相同，以及响应于确定第一缓存606与缓存一致性节点605侧记录的当前独占第一数据的缓存相同，将第一数据写入内存。
例如，内存配置为：在缓存一致性节点605将第一数据写入内存之后，向缓存一致性节点605返回指示第一数据已经被写入内存的写响应。例如，缓存一致性节点605还配置为：响应于从内存收到指示第一数据已经被写入 内存的写响应，向第一缓存606返回指示第一数据已经被写回内存的写响应信号以直接结束对写请求的处理操作。
例如，缓存一致性节点605还配置为：在缓存一致性节点605将第一数据写入内存之后，将第一缓存606的数据状态置为无效态、共享态或独占态。例如，无效态表示第一缓存606没有缓存第一数据，共享态表示第一缓存606与其他缓存均缓存有第一数据，独占态表示仅第一缓存606中缓存有第一数据。
例如，缓存一致性节点605还配置为：响应于收到第二缓存607对第一数据的读请求且缓存一致性节点605侧记录第一数据在第一缓存606中处于独占状态或共享状态，向第一缓存606发起监测信号。例如，第一缓存606配置为：响应于第一缓存606在发出写请求之后收到监测信号，向缓存一致性节点605返回携带第一数据的监测响应。
例如，缓存一致性节点605还配置为：响应于收到监测响应，将第一数据返回给第二缓存607。例如，第二缓存607还配置为：在收到第一数据之后，向缓存一致性节点605返回指示已经收到第一数据的报文以结束读请求。
例如，缓存一致性节点605还配置为：响应于收到监测响应，将第一数据返回给第二缓存607，并且将第二缓存607的数据状态置为独占态。例如，独占态表示仅第二缓存607中缓存有第一数据。
例如，缓存一致性节点605还配置为：在收到报文之后，丢弃写请求写入缓存一致性节点605侧的第一数据，并且向第一缓存606返回写响应信号以直接结束对写请求的处理操作。
例如，缓存一致性节点605还配置为：响应于在收到报文之后确定写请求写入缓存一致性节点605侧的第一数据为无效数据，丢弃写请求写入缓存一致性节点605侧的第一数据。
在本公开的实施例的电子设备60中，通过回写事务和目录的比较，进行场景识别，主设备收到写响应后直接结束写事务处理，不需要再向从设备发送ACK报文，从而降低ACK报文的数量，减少协议对ACK报文的需求，减少ACK报文传输产生的功耗和延时以及带宽占用，并且优化了主设备侧缓冲区的周转率，在相同性能下主设备侧需要的缓冲区数量更少，节省面积和功耗。
本公开至少一些实施例还提供了一种数据处理装置，该数据处理装置包 括存储器和处理器。例如，存储器配置为存储计算机可执行指令，处理器配置为执行计算机可执行指令。例如，计算机可执行指令被处理器执行时实现本公开至少一实施例提供的数据处理方法。
图6示出了本公开至少一实施例提供的一种数据处理装置500的示意图。
如图6所示，根据本公开实施例的电子设备500包括处理器501以及存储器502，处理器501和存储器502可以通过总线503进行互连。
处理器501可以根据存储在存储器502中的程序或代码执行各种动作和处理。具体地，处理器501可以是一种集成电路芯片，具有信号的处理能力。例如，上述处理器501可以是通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件，可以实现或者执行本公开实施例中公开的各种方法和步骤。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等，可以是X86架构或者是ARM架构等。
存储器502用于非暂时性存储计算机可执行指令，处理器501用于运行计算机可执行指令。当计算机可执行指令在被处理器501执行时实现本公开至少一实施例提供的数据处理方法。
例如，存储器502可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。非易失性存储器可以是只读存储器(ROM)、可编程只读存储器(PROM)、可擦除可编程只读存储器(EPROM)、电可擦除可编程只读存储器(EEPROM)或闪存。易失性存储器可以是随机存取存储器(RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)、同步动态随机存取存储器(SDRAM)、双倍数据速率同步动态随机存取存储器(DDRSDRAM)、增强型同步动态随机存取存储器(ESDRAM)、同步连接动态随机存取存储器(SLDRAM)和直接内存总线随机存取存储器(DRRAM)。应注意，本文描述的方法的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
在本公开的实施例的数据处理装置500中，通过回写事务和目录的比较，进行场景识别，主设备收到写响应后直接结束写事务处理，不需要再向从设备发送ACK报文，从而降低ACK报文的数量，减少协议对ACK报文的需 求，减少ACK报文传输产生的功耗和延时以及带宽占用，并且优化了主设备侧缓冲区的周转率，在相同性能下主设备侧需要的缓冲区数量更少，节省面积和功耗。
本公开的至少一个实施例还提供了一种非暂时性存储介质，非暂时性地存储计算机可执行指令。例如，当计算机可执行指令由处理器执行时，实现本公开至少一实施例提供的数据处理方法。
图7是本公开一些实施例提供的一种非暂时性存储介质的示意图。如图7所示，非暂时性存储介质600可以非暂时性地存储计算机可执行指令610，计算机可执行指令610在被计算机执行时实现本公开任一实施例提供的数据处理方法。
类似地，本公开实施例中的非暂时性存储介质可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。应注意，本文描述的方法的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
上述非暂时性存储介质的技术效果与上述数据处理方法的技术效果相同，此处不再赘述。
需要说明的是，附图中的流程图和框图，图示了按照本公开的各种实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段、或代码的一部分，所述模块、程序段、或代码的一部分包含至少一个用于实现规定的逻辑功能的可执行指令。也应当注意，在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个接连地表示的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合，可以用执行规定的功能或操作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
一般而言，本公开的各种示例实施例可以在硬件或专用电路、软件、固件、逻辑，或其任何组合中实施。某些方面可以在硬件中实施，而其他方面可以在可以由控制器、微处理器或其他计算设备执行的固件或软件中实施。当本公开的实施例的各方面被图示或描述为框图、流程图或使用某些其他图形表示时，将理解此处描述的方框、装置、系统、技术或方法可以作为非限制性的示例在硬件、软件、固件、专用电路或逻辑、通用硬件或控制器或其 他计算设备，或其某些组合中实施。
对于本公开，还有以下几点需要说明：
(1)本公开实施例的附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种数据处理方法，包括：
    响应于收到第一缓存要将第一数据写回内存的写请求，缓存一致性节点将所述第一数据写入内存或将所述第一数据丢弃，其中，所述写请求携带所述第一数据，所述缓存一致性节点配置为维护由多个缓存中存储的数据的一致性，所述多个缓存包括所述第一缓存，以及
    在所述缓存一致性节点将所述第一数据写入内存或将所述第一数据丢弃之后，所述缓存一致性节点向所述第一缓存返回写响应信号以直接结束对所述写请求的处理操作。
  2. 根据权利要求1所述的数据处理方法，所述响应于收到第一缓存要将第一数据写回内存的写请求，缓存一致性节点将所述第一数据写入内存或将所述第一数据丢弃，包括：
    响应于收到所述第一缓存要将所述第一数据写回所述内存的所述写请求，所述缓存一致性节点确定所述第一缓存是否与所述缓存一致性节点侧记录的当前独占所述第一数据的缓存相同，以及
    响应于确定所述第一缓存与所述缓存一致性节点侧记录的当前独占所述第一数据的缓存相同，所述缓存一致性节点将所述第一数据写入所述内存。
  3. 根据权利要求1或2所述的数据处理方法，所述在所述缓存一致性节点将所述第一数据写入内存或将所述第一数据丢弃之后，所述缓存一致性节点向所述第一缓存返回写响应信号以直接结束对所述写请求的处理操作，包括：
    在所述缓存一致性节点将所述第一数据写入内存之后，所述内存向所述缓存一致性节点返回指示所述第一数据已经被写入所述内存的写响应，以及
    响应于从所述内存收到指示所述第一数据已经被写入所述内存的所述写响应，所述缓存一致性节点向所述第一缓存返回指示所述第一数据已经被写回所述内存的所述写响应信号以直接结束对所述写请求的处理操作。
  4. 根据权利要求1-3中的任一项所述的数据处理方法，还包括：
    在所述缓存一致性节点将所述第一数据写入所述内存之后，所述缓存一致性节点将所述第一缓存的数据状态置为无效态、共享态或独占态，
    其中，所述无效态表示所述第一缓存没有缓存所述第一数据，所述共享态表示所述第一缓存与其他缓存均缓存有所述第一数据，所述独占态表示仅所述第一缓存中缓存有所述第一数据。
  5. 根据权利要求1-4中的任一项所述的数据处理方法，还包括：
    响应于收到第二缓存对所述第一数据的读请求且所述缓存一致性节点侧记录所述第一数据在所述第一缓存中处于独占状态或共享状态，所述缓存一致性节点向所述第一缓存发起监测信号；
    响应于所述第一缓存在发出所述写请求之后收到所述监测信号，所述第一缓存响应于所述监测信号向所述缓存一致性节点返回携带所述第一数据的监测响应。
  6. 根据权利要求5所述的数据处理方法，还包括：
    响应于收到所述监测响应，所述缓存一致性节点将所述第一数据返回给所述第二缓存，以及
    在收到所述第一数据之后，所述第二缓存向所述缓存一致性节点返回指示已经收到所述第一数据的报文以结束所述读请求。
  7. 根据权利要求6所述的数据处理方法，所述响应于收到所述监测响应，所述缓存一致性节点将所述第一数据返回给所述第二缓存，包括：
    响应于收到所述监测响应，所述缓存一致性节点将所述第一数据返回给所述第二缓存，并且将所述第二缓存的数据状态置为独占态，所述独占态表示仅所述第二缓存中缓存有所述第一数据。
  8. 根据权利要求6所述的数据处理方法，所述在所述缓存一致性节点将所述第一数据写入内存或将所述第一数据丢弃之后，所述缓存一致性节点向所述第一缓存返回写响应信号以直接结束对所述写请求的处理操作，包括：
    在收到所述报文之后，所述缓存一致性节点丢弃所述写请求写入所述缓 存一致性节点侧的所述第一数据，并且向所述第一缓存返回所述写响应信号以直接结束对所述写请求的处理操作。
  9. 根据权利要求8所述的数据处理方法，所述在收到所述报文之后，所述缓存一致性节点丢弃所述写请求写入所述缓存一致性节点侧的所述第一数据，包括：
    响应于在收到所述报文之后确定所述写请求写入所述缓存一致性节点侧的所述第一数据为无效数据，所述缓存一致性节点丢弃所述写请求写入所述缓存一致性节点侧的所述第一数据。
  10. 一种电子设备，包括：
    多个缓存，包括第一缓存；以及
    缓存一致性节点，配置为响应于收到所述第一缓存要将第一数据写回内存的写请求，将所述第一数据写入内存或将所述第一数据丢弃，以及在所述缓存一致性节点将所述第一数据写入内存或将所述第一数据丢弃之后，向所述第一缓存返回写响应信号以直接结束对所述写请求的处理操作，其中，所述写请求携带所述第一数据，所述缓存一致性节点配置为维护由所述多个缓存中存储的数据的一致性。
  11. 根据权利要求10所述的电子设备，其中，所述缓存一致性节点还配置为：
    响应于收到所述第一缓存要将所述第一数据写回所述内存的所述写请求，确定所述第一缓存是否与所述缓存一致性节点侧记录的当前独占所述第一数据的缓存相同，以及
    响应于确定所述第一缓存与所述缓存一致性节点侧记录的当前独占所述第一数据的缓存相同，将所述第一数据写入所述内存。
  12. 根据权利要求10或11所述的电子设备，其中，所述内存配置为：在所述缓存一致性节点将所述第一数据写入内存之后，向所述缓存一致性节点返回指示所述第一数据已经被写入所述内存的写响应，并且
    所述缓存一致性节点还配置为：响应于从所述内存收到指示所述第一数 据已经被写入所述内存的所述写响应，向所述第一缓存返回指示所述第一数据已经被写回所述内存的所述写响应信号以直接结束对所述写请求的处理操作。
  13. 根据权利要求10-12中的任一项所述的电子设备，其中，所述缓存一致性节点还配置为：响应于收到第二缓存对所述第一数据的读请求且所述缓存一致性节点侧记录所述第一数据在所述第一缓存中处于独占状态或共享状态，向所述第一缓存发起监测信号，并且
    所述第一缓存配置为：响应于所述第一缓存在发出所述写请求之后收到所述监测信号，向所述缓存一致性节点返回携带所述第一数据的监测响应。
  14. 一种数据处理装置，包括：
    存储器，配置为存储计算机可执行指令；以及
    处理器，配置为执行所述计算机可执行指令，
    其中，所述计算机可执行指令被所述处理器执行时实现根据权利要求1-9中任一项所述的方法。
  15. 一种非暂时性存储介质，非暂时性地存储计算机可执行指令，其中，当所述计算机可执行指令由处理器执行时，实现根据权利要求1-9中任一项所述的方法。
PCT/CN2024/097159 2023-11-27 2024-06-04 数据处理方法和装置、电子设备以及存储介质 Pending WO2025112410A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020257005683A KR20250083449A (ko) 2023-11-27 2024-06-04 데이터 처리 방법 및 장치, 전자 디바이스, 및 저장 매체
EP24837279.9A EP4589930A4 (en) 2023-11-27 2024-06-04 DATA PROCESSING METHOD AND APPARATUS, ELECTRONIC DEVICE AND STORAGE MEDIA
JP2025504111A JP2026500592A (ja) 2023-11-27 2024-06-04 データ処理方法、装置、電子機器及び記憶媒体

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202311598492.4A CN117560422B (zh) 2023-11-27 2023-11-27 数据处理方法和装置、电子设备以及存储介质
CN202311598492.4 2023-11-27

Publications (1)

Publication Number Publication Date
WO2025112410A1 true WO2025112410A1 (zh) 2025-06-05

Family

ID=89814463

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2024/097159 Pending WO2025112410A1 (zh) 2023-11-27 2024-06-04 数据处理方法和装置、电子设备以及存储介质

Country Status (5)

Country Link
EP (1) EP4589930A4 (zh)
JP (1) JP2026500592A (zh)
KR (1) KR20250083449A (zh)
CN (1) CN117560422B (zh)
WO (1) WO2025112410A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117560422B (zh) * 2023-11-27 2025-09-30 海光信息技术股份有限公司 数据处理方法和装置、电子设备以及存储介质
CN118051685B (zh) * 2024-03-15 2025-02-18 海光信息技术股份有限公司 数据处理方法和装置、电子设备和存储介质
CN118519957B (zh) * 2024-06-07 2025-02-18 北京开源芯片研究院 一种数据处理方法、装置、电子设备及可读存储介质
CN119135686B (zh) * 2024-09-27 2025-11-18 山东云海国创云计算装备产业创新中心有限公司 一种服务器，片上网络系统及一种报文处理设备和方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104991868A (zh) * 2015-06-09 2015-10-21 浪潮(北京)电子信息产业有限公司 一种多核处理器系统和缓存一致性处理方法
US20180157590A1 (en) * 2016-12-02 2018-06-07 Arm Limited Filtering coherency protocol transactions
CN114116531A (zh) * 2022-01-28 2022-03-01 苏州浪潮智能科技有限公司 一种缓存一致性写回的方法、装置、设备及介质
CN116089116A (zh) * 2022-12-16 2023-05-09 成都海光集成电路设计有限公司 数据处理方法及装置
CN117560422A (zh) * 2023-11-27 2024-02-13 海光信息技术股份有限公司 数据处理方法和装置、电子设备以及存储介质

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0816885B2 (ja) * 1993-04-27 1996-02-21 工業技術院長 キャッシュメモリ制御方法
US8205045B2 (en) * 2008-07-07 2012-06-19 Intel Corporation Satisfying memory ordering requirements between partial writes and non-snoop accesses
US8996812B2 (en) * 2009-06-19 2015-03-31 International Business Machines Corporation Write-back coherency data cache for resolving read/write conflicts
US8782347B2 (en) * 2009-06-26 2014-07-15 Intel Corporation Controllably exiting an unknown state of a cache coherency directory
US8327228B2 (en) * 2009-09-30 2012-12-04 Intel Corporation Home agent data and memory management
US8949547B2 (en) * 2011-08-08 2015-02-03 Arm Limited Coherency controller and method for data hazard handling for copending data access requests
CN102591800B (zh) * 2011-12-31 2015-01-07 龙芯中科技术有限公司 一种弱一致性存储模型的数据访存系统和方法
US20140040561A1 (en) * 2012-07-31 2014-02-06 Futurewei Technologies, Inc. Handling cache write-back and cache eviction for cache coherence
US10268583B2 (en) * 2012-10-22 2019-04-23 Intel Corporation High performance interconnect coherence protocol resolving conflict based on home transaction identifier different from requester transaction identifier
US10489298B2 (en) * 2015-07-28 2019-11-26 Hewlett Packard Enterprise Development Lp Hardware flush assist
JP6631317B2 (ja) * 2016-02-26 2020-01-15 富士通株式会社 演算処理装置、情報処理装置および情報処理装置の制御方法
US10489323B2 (en) * 2016-12-20 2019-11-26 Arm Limited Data processing system for a home node to authorize a master to bypass the home node to directly send data to a slave
US10621103B2 (en) * 2017-12-05 2020-04-14 Arm Limited Apparatus and method for handling write operations
US11803470B2 (en) * 2020-09-25 2023-10-31 Advanced Micro Devices, Inc. Multi-level cache coherency protocol for cache line evictions

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104991868A (zh) * 2015-06-09 2015-10-21 浪潮(北京)电子信息产业有限公司 一种多核处理器系统和缓存一致性处理方法
US20180157590A1 (en) * 2016-12-02 2018-06-07 Arm Limited Filtering coherency protocol transactions
CN114116531A (zh) * 2022-01-28 2022-03-01 苏州浪潮智能科技有限公司 一种缓存一致性写回的方法、装置、设备及介质
CN116089116A (zh) * 2022-12-16 2023-05-09 成都海光集成电路设计有限公司 数据处理方法及装置
CN117560422A (zh) * 2023-11-27 2024-02-13 海光信息技术股份有限公司 数据处理方法和装置、电子设备以及存储介质

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4589930A4

Also Published As

Publication number Publication date
EP4589930A4 (en) 2025-12-17
JP2026500592A (ja) 2026-01-08
CN117560422A (zh) 2024-02-13
KR20250083449A (ko) 2025-06-10
EP4589930A1 (en) 2025-07-23
CN117560422B (zh) 2025-09-30

Similar Documents

Publication Publication Date Title
WO2025112410A1 (zh) 数据处理方法和装置、电子设备以及存储介质
US12061562B2 (en) Computer memory expansion device and method of operation
US11741034B2 (en) Memory device including direct memory access engine, system including the memory device, and method of operating the memory device
TWI318737B (en) Method and apparatus for predicting early write-back of owned cache blocks, and multiprocessor computer system
CN113918101B (zh) 一种写数据高速缓存的方法、系统、设备和存储介质
CN106844048B (zh) 基于硬件特性的分布式共享内存方法及系统
CN106527974A (zh) 一种写数据的方法、设备及系统
CN117707999A (zh) 数据处理方法和装置、电子设备和存储介质
WO2021082877A1 (zh) 访问固态硬盘的方法及装置
CN116679886A (zh) 数据处理方法及装置、电子设备、缓存和存储介质
US12561271B2 (en) Computing systems having congestion monitors therein and methods of controlling operation of same
CN114238165B (zh) 数据处理方法、数据处理装置以及存储介质
US20170199819A1 (en) Cache Directory Processing Method for Multi-Core Processor System, and Directory Controller
US20030189944A1 (en) Distributed shared memory system and data-maintenance method of same
CN120336205A (zh) 内存页面迁移方法、cxl内存扩展设备及计算设备
CN119440881A (zh) 一种多核一致性处理方法、系统、设备及存储介质
CN114356839B (zh) 处理写操作的方法、设备、处理器及设备可读存储介质
CN109597776B (zh) 一种数据操作方法、内存控制器以及多处理器系统
CN112612726B (zh) 基于缓存一致性的数据存储方法、装置、处理芯片及服务器
US11054993B2 (en) Mass storage system having peer-to-peer data movements between a cache and a backend store
CN110309224A (zh) 一种数据复制方法及装置
CN114238170A (zh) 数据处理方法、数据处理装置和存储介质
CN114550805A (zh) 半导体装置
CN119690692B (zh) 数据处理方法及装置
US12517829B1 (en) Processing writes to multiple targets in a directory-based cache coherent electronic system

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2025504111

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2025504111

Country of ref document: JP

ENP Entry into the national phase

Ref document number: 2024837279

Country of ref document: EP

Effective date: 20250122

WWP Wipo information: published in national office

Ref document number: 1020257005683

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2024837279

Country of ref document: EP