WO2025236816A1 - 太阳能电池及光伏组件 - Google Patents

太阳能电池及光伏组件

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Publication number
WO2025236816A1
WO2025236816A1 PCT/CN2025/080544 CN2025080544W WO2025236816A1 WO 2025236816 A1 WO2025236816 A1 WO 2025236816A1 CN 2025080544 W CN2025080544 W CN 2025080544W WO 2025236816 A1 WO2025236816 A1 WO 2025236816A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
doped semiconductor
semiconductor layer
solar cell
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/080544
Other languages
English (en)
French (fr)
Inventor
李振国
童洪波
靳玉鹏
余元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Longi Green Energy Technology Co Ltd
Original Assignee
Longi Green Energy Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202410605390.9A external-priority patent/CN118335817A/zh
Priority claimed from CN202411280473.1A external-priority patent/CN119421557B/zh
Application filed by Longi Green Energy Technology Co Ltd filed Critical Longi Green Energy Technology Co Ltd
Priority to AU2025202205A priority Critical patent/AU2025202205B2/en
Priority to EP25716024.2A priority patent/EP4672924A4/en
Priority to US19/098,548 priority patent/US12610651B2/en
Publication of WO2025236816A1 publication Critical patent/WO2025236816A1/zh
Priority to AU2026200034A priority patent/AU2026200034A1/en
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/30—Coatings

Definitions

  • This application relates to a solar cell, and more particularly to a solar cell and a photovoltaic module.
  • solar cells include N-type and P-type regions.
  • a certain degree of electrical isolation is required between the N-type and P-type regions.
  • the N-type and P-type regions can be isolated by processes such as wet etching.
  • the existing methods are not perfect, and there is still a risk of leakage between the front and back of the solar cell.
  • the battery edges are prone to mutual friction, which can cause the passivation film to peel off or be scratched, exposing the substrate.
  • the surface passivation layer is damaged, leading to a weakening of the battery's passivation performance and thus affecting battery performance.
  • a solar cell comprising:
  • a semiconductor substrate having opposing first and second surfaces, and a plurality of side surfaces adjacent to the first and second surfaces;
  • a passivation contact structure is located at least on a portion of the first surface of a semiconductor substrate, and the passivation contact structure includes an interface passivation layer and a first doped semiconductor layer stacked sequentially.
  • the side surface In the direction from the first surface to the second surface, the side surface includes a first region and a second region that are sequentially adjacent to each other.
  • the first region protrudes in a direction away from the side surface compared to the second region.
  • the first doped semiconductor layer is also located on the surface of the first region, wherein the first doped semiconductor layer located on the first region is integrally continuous with the first doped semiconductor layer located on the first surface.
  • At least one side of the first region protrudes in a direction away from the side compared to the second region. This is beneficial to increase the effective area of the passivation contact structure of the first surface, improve the passivation contact performance of the first surface, improve the carrier collection efficiency, and thus improve the efficiency of the solar cell.
  • the solar cell in a direction parallel to the first surface, at least one side region of the first area protrudes in a direction away from the side compared to the second area. Since the surface of the protruding portion of the first area is a certain distance from the surface of the second area, it can enhance the electrical isolation between the front and back of the cell (the spatial electrical isolation distance between the first and second surfaces), reducing the risk of leakage between the front and back. Simultaneously, during the electrode fabrication process, it can effectively prevent the slurry used for electrode fabrication from leaking and distributing over a larger area on the side of the cell, thus preventing serious damage to the electrical performance of the cell. Furthermore, the protrusion of the first area can reduce the damage to the performance of the solar cell caused by scratches.
  • the first doped semiconductor layer is also located on a portion of the surface of the first region, which can increase the effective area of the passivated contact structure and improve the carrier collection efficiency while reducing the risk of leakage.
  • FIG. 1 is a cross-sectional schematic diagram of the solar cell provided in an embodiment of this application.
  • FIG. 2 is a partial cross-sectional schematic diagram of the solar cell provided in an embodiment of this application.
  • Figure 3 is a top view of a semiconductor substrate provided in another embodiment of this application.
  • FIG. 4 is a cross-sectional schematic diagram of a solar cell provided in another embodiment of this application.
  • FIG. 5 is a partial cross-sectional schematic diagram of a solar cell provided in another embodiment of this application.
  • FIG. 6 is a cross-sectional schematic diagram of a solar cell provided in another embodiment of this application.
  • FIG. 7 is a cross-sectional schematic diagram of a solar cell provided in another embodiment of this application.
  • Figure 8 is a scanning electron microscope image of the side of a solar cell provided in an embodiment of this application.
  • Figure 9 is a partial cross-sectional schematic diagram of a solar cell provided in another embodiment of this application.
  • Figure 10 is a scanning electron microscope image of the side of the solar cell in Figure 9;
  • FIG 11 is a partial cross-sectional schematic diagram of a solar cell provided in another embodiment of this application.
  • Figure 12 is a cross-sectional schematic diagram of a solar cell provided in another embodiment of this application.
  • Figure 13 is a longitudinal cross-sectional view of the solar cell provided in an embodiment of this application.
  • Figure 14 is a side SEM image of the solar cell provided in the embodiment of this application.
  • Figure 15 is a second side SEM image of the solar cell provided in the embodiment of this application.
  • Figure 16 is a 3D view of the side of a solar cell provided in an embodiment of this application.
  • Figure 17 is a SEM image of the chamfered surface of the solar cell provided in the embodiment of this application.
  • Figure 18 is a second SEM image of the chamfered surface of the solar cell provided in the embodiment of this application.
  • Figure 19 is a SEM image of the chamfered surface of the solar cell provided in the embodiment of this application.
  • Figure 20 is a cross-sectional schematic diagram of a back-contact solar cell provided in an embodiment of this application.
  • Figure 21 is a top view of the first surface of the back-contact solar cell provided in an embodiment of this application.
  • first, second, etc. are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as “first” or “second” may explicitly or implicitly include one or more of that feature.
  • “multiple” means two or more, unless otherwise explicitly specified. "Several” means one or more, unless otherwise explicitly specified.
  • connection should be interpreted broadly.
  • they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components.
  • connection should be interpreted broadly.
  • they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components.
  • the solar cell includes: a semiconductor substrate 1 having a first surface A and a second surface B opposite to each other, and a side surface C; a passivation contact structure located at least on a portion of the first surface A of the semiconductor substrate 1, the passivation contact structure including an interface passivation layer 2 and a first doped semiconductor layer 3 stacked sequentially; and a first passivation antireflection layer 4; wherein, in the direction from the first surface A to the second surface B, the side surface C of the semiconductor substrate includes an adjacent first region C1 and a second region C2, the first region C1 protruding in a direction away from the side surface C compared to the second region C2.
  • the first doped semiconductor layer 3 extends from the first surface A of the semiconductor substrate 1 to the first region C1 and covers the first region C1; the first doped semiconductor layer 3 located in the first region C1 is integrally continuous with the first doped semiconductor layer 3 located on the first surface A.
  • This structure suppresses leakage to a certain extent. Simultaneously, during electrode fabrication, it effectively prevents the slurry used for electrode fabrication from leaking and distributing over a larger area on the side of the cell, thus avoiding serious damage to the battery's electrical performance. Furthermore, the protrusion of the first region C1 reduces the damage to the solar cell's performance caused by scratches.
  • the surface of a portion of the first region C1 adjacent to the second region C2 is not covered with the first doped semiconductor layer 3.
  • the semiconductor substrate 1 in the direction from the first surface A to the second surface B, includes a first semiconductor substrate 11 and a second semiconductor substrate 12 integrally formed with the first semiconductor substrate 11; the side surface C includes a first region C1 located on the side surface of the first semiconductor substrate 11 and a second region C2 located on the side surface of the second semiconductor substrate 12, and at least the first region C1 of the side surface C protrudes in a direction away from the side surface C compared to the second region C2.
  • the area of the first semiconductor substrate 11 is larger than the area of the second semiconductor substrate 12.
  • the protrusion height d1 of the first region C1 compared to the second region C2 is 0.5 ⁇ m to 5 ⁇ m, for example, it can be 0.5 ⁇ m, 1 ⁇ m, 2 ⁇ m, or 5 ⁇ m, but is not limited to the values mentioned.
  • the semiconductor substrate 1 can be a silicon substrate.
  • the semiconductor substrate 1 can also be a substrate made of any semiconductor material, such as a germanium-silicon substrate, a germanium substrate, or a gallium arsenide substrate.
  • the semiconductor substrate 1 can be an N-type semiconductor substrate or a P-type semiconductor substrate.
  • the semiconductor substrate 1 can be single-crystal or polycrystalline.
  • the semiconductor substrate 1 is rectangular in shape, with chamfers between adjacent sides.
  • the semiconductor substrate 1 includes, for example, eight side surfaces C.
  • a passivation contact structure extends from the first surface A of the semiconductor substrate 1 to a portion of the surface of the first region C1 on at least one side surface C.
  • the passivation contact structure does not completely cover the first region C1, thus reducing the short-circuit risk associated with the passivation contact structure.
  • a stepped structure exists between the first region C1 and the second region C2. Doped regions of the substrate may exist on the sidewalls of this stepped structure, i.e., on the connecting sidewalls between the first region C1 and the second region C2.
  • the first doped semiconductor layer 3 can easily come into contact with these doped regions on the stepped sidewalls, leading to direct contact between the first doped semiconductor layer 3 and the semiconductor substrate 1, potentially causing a short circuit in the battery. Therefore, positioning the first doped semiconductor layer 3 away from this sidewall can prevent the aforementioned situation from occurring.
  • the distance between the first doped semiconductor layer 3 on the surface of the first region C1 and the second region C2 is greater than or equal to 1 ⁇ m.
  • the distribution width of the first doped semiconductor layer 3 in the first region C1 is less than 80% of the width of the first region C1.
  • the ratio of the width of the first region C1 in the direction perpendicular to the first surface A to the thickness of the semiconductor substrate 1 ranges from 1% to 20%, for example, it can be 1%, 5%, 10%, 15%, or 20%, but is not limited to the values listed. If the ratio range is too small, it is difficult to achieve the technical effect of increasing the passivation contact structure area and improving the carrier collection efficiency; if the ratio range is too large, leakage current is likely to occur between the first surface A and the second surface B.
  • the thickness of the first semiconductor substrate 11 in the direction perpendicular to the first surface A ranges from 0.5 ⁇ m to 20 ⁇ m, for example, it can be 0.5 ⁇ m, 1 ⁇ m, 5 ⁇ m, 10 ⁇ m, or 20 ⁇ m, but is not limited to the values mentioned above; the thickness of the first semiconductor substrate 11 in the direction perpendicular to the first surface A is the width of the first region C1 in the direction from the first surface A to the second surface B.
  • At least one side surface C in a direction parallel to the first surface A, has a first region C1 that protrudes from the second region C2 in a direction away from the side surface C1. This is beneficial to increase the effective area of the passivation contact structure of the first surface A, improve the passivation contact performance of the first surface A, improve the carrier collection efficiency, and thus improve the efficiency of the solar cell.
  • the doping concentration of the semiconductor layers is usually high, leakage current in solar cells typically occurs between semiconductor layers with different doping types.
  • the first region C1 has a large width in the direction perpendicular to the first surface A, the first doped semiconductor layer 3 covering the first region C1 is prone to leakage current with the second doped semiconductor layer 5 located on the second surface B.
  • the width of the first region C1 to 1% to 20% of the thickness of the semiconductor substrate, and by placing the first doped semiconductor layer 3 on a portion of the surface of the first region C1, the risk of leakage between the first doped semiconductor layer 3 and the second surface B is reduced.
  • the first doped semiconductor layer is located on a portion of the surface of the first region, which can reduce the risk of leakage current while increasing the effective area of the passivation contact structure and improving the carrier collection efficiency.
  • the interface passivation layer 2 includes one of an intrinsic amorphous silicon layer, a lightly doped intrinsic amorphous silicon layer (doping concentration lower than that of the first doped semiconductor layer), and a dielectric layer.
  • the dielectric layer includes, but is not limited to, silicon oxide, aluminum oxide, doped aluminum oxide, silicon nitride, and silicon carbonitride.
  • the first doped semiconductor layer 3 is at least one of a doped polycrystalline silicon layer, a doped microcrystalline silicon layer, a doped nanocrystalline silicon layer, and a doped amorphous silicon layer.
  • the interface passivation layer 2 is, for example, tunneling silicon oxide
  • the first doped semiconductor layer 3 is, for example, doped polysilicon.
  • the TOPCon solar cell further includes: a second doped semiconductor layer 5, located at least within the second surface B of the semiconductor substrate 1, serving as the emitter region of the TOPCon solar cell; one of the second doped semiconductor layer 5 and the first doped semiconductor layer 3 is N-type, and the other of the second doped semiconductor layer 5 and the first doped semiconductor layer 3 is P-type.
  • the TOPCon solar cell further includes a second passivation and antireflection layer 6, located at least on the surface of the second doped semiconductor layer 5 away from the semiconductor substrate 1.
  • the second passivation and antireflection layer 6 is used to achieve passivation and antireflection functions on the second surface B of the semiconductor substrate 1.
  • a heavily doped semiconductor substrate layer 111 is formed on the first surface A and the surface of the first region C1 of the semiconductor substrate 1.
  • the heavily doped semiconductor substrate layer 111 can be understood as having a doping concentration greater than that of the semiconductor substrate 1 itself.
  • the heavily doped semiconductor substrate layer 111 can be located on a portion of the surface of the first region C1 or on the entire surface of the first region C1.
  • At least one first region C1 of the side surface C is an inclined plane extending from the side away from the first surface A toward the side closer to the first surface A in a direction away from the side surface (C).
  • This increases the surface area of the first surface A, increases the area of the passivation contact structure located on the first surface A, and is beneficial to improving carrier collection efficiency. Furthermore, it increases the width of the entire side surface in the direction perpendicular to the first surface A, which is more conducive to the isolation between the first surface A and the second surface B.
  • the passivated contact structure extends from the first surface A of the semiconductor substrate 1 to a portion of the surface of the first region C1 of at least one side surface C.
  • the interface passivation layer 2 and the first doped semiconductor layer 3 are also located on a portion of the surface of the first region C1, which can increase the surface area of the passivation contact structure composed of the interface passivation layer 2 and the first doped semiconductor layer 3, thereby improving the carrier collection efficiency and thus improving the efficiency of the solar cell.
  • the first region C1 is a sloped surface, which is relatively flat. This is conducive to depositing a first passivation and antireflection layer 4 with better film quality on the side C, thereby improving the passivation and antireflection effect of the first passivation and antireflection layer 4.
  • the first doped semiconductor layer 3 can also cover most of the surface of the first region C1, or even cover the entire first region C1.
  • Figure 8 is a scanning electron microscope image of the side of a solar cell according to an embodiment of this application.
  • the first region C1 has multiple holes, which are recessed into the semiconductor substrate 1 in a direction parallel to the first surface A.
  • a passivation contact structure extends from a first surface A of a semiconductor substrate 1 to a portion of a first region C1 on at least one side surface C.
  • a hole is recessed into the semiconductor substrate 1 through the passivation contact structure in a direction parallel to the first surface A.
  • a first passivation antireflection layer 4 is located on the passivation contact structure at the first region C1 and on the sidewalls and bottom surface of the hole, allowing hydrogen from the first passivation antireflection layer 4 within the hole to enter the semiconductor substrate 1, improving the hydrogen passivation effect of the semiconductor substrate 1, thereby improving the efficiency of the solar cell.
  • the first passivation antireflection layer 4 may include one or more layers of aluminum oxide, silicon nitride, and silicon oxynitride, such as a stack of aluminum oxide and silicon nitride.
  • a large amount of hydrogen is introduced during aluminum oxide deposition, and due to the porous structure, a large amount of hydrogen can enter the semiconductor substrate 1.
  • the distribution density of pores in the region near the first surface A is lower than that in the region near the second region C2.
  • the lower distribution density of pores in the region near the first surface A reduces recombination centers of charge carriers in that region, thereby reducing carrier recombination and improving carrier collection efficiency.
  • the radial dimension of the hole gradually decreases from the surface of the first region C1 to the semiconductor substrate 1 in a direction parallel to the first surface A. That is, the hole is an inverted pyramid structure extending from the surface of the first region C1 to the semiconductor substrate 1 in a direction parallel to the first surface A.
  • the radial dimension of the hole is less than 5 ⁇ m, preferably less than 2 ⁇ m, and more preferably less than 1 ⁇ m; the radial dimension of the hole can be, for example, 4 ⁇ m, 3 ⁇ m, 2 ⁇ m, or 1 ⁇ m, but is not limited to the values mentioned above.
  • the ratio of the projected area of the hole in the first region C1 to the surface area of the first region can range from 1% to 30%, for example, it can be 1%, 5%, 10%, 20%, or 30%, but is not limited to the values mentioned. If the ratio range is too small, it is difficult to achieve the technical effects of improving the passivation effect of the semiconductor substrate and increasing the area of the passivation contact structure, or the effect is not obvious; if the ratio range is too large, it will result in too many defects in the semiconductor substrate 1, which is not conducive to the effective collection of charge carriers.
  • the distribution density and radial dimension of the hole structure in the region C1 covered by the doped semiconductor layer 3 or the passivation contact structure are both smaller than those in the region C1 not covered by the doped semiconductor layer 3. This reduces damage to the passivation contact structure.
  • Figure 9 is a partial cross-sectional schematic diagram of a solar cell provided in another embodiment of this application.
  • Figure 10 is a scanning electron microscope image of the side of the solar cell in Figure 9.
  • the first region C1 has a raised ridge that extends in a direction generally parallel to the first surface A.
  • the first doped semiconductor layer 3 is also located on a portion of the surface of the first region C1; the first doped semiconductor layer 3 located on the first region C1 is integrally continuous with the first doped semiconductor layer 3 located on the first surface A; the surface of the portion of the first region C1 adjacent to the second region C2 is not covered by the first doped semiconductor layer 3.
  • the first region C1 has raised ridges, and the first doped semiconductor layer 3 is located on a portion of the surface of the first region C1, which can enhance the electrical isolation between the front and back of the battery, and under the condition that leakage current is controllable, can increase the surface area of the first doped semiconductor layer 3, which is beneficial to improving the carrier collection efficiency.
  • the first region C1 has raised ridges that extend in a direction generally parallel to the first surface A, which can increase the surface area of the first region C1.
  • the first doped semiconductor layer 3 covers the entire first region C1, which can increase the surface area of the first doped semiconductor layer 3, thereby improving carrier collection efficiency.
  • the ridge extends in a direction generally parallel to the first surface A; that is, a portion of the first region C1 near the second region C2 is an inclined surface extending from one side of the second region C2 toward the side of the ridge in a direction away from the semiconductor substrate 1.
  • the first doped semiconductor layer can also cover most of the surface of the first region C1, or even cover the entire first region C1.
  • the second region C2 has a tower base structure. The width of the first region C1 in the direction perpendicular to the first surface A is smaller than the size of the tower base structure of the second region C2, wherein the size of the tower base structure is defined as the side length or diagonal length of the tower base structure.
  • the solar cell further includes: a first electrode 10, which passes through a first passivation antireflection layer 4 and is in electrical contact with a first doped semiconductor layer 3; and a second electrode 20, which passes through a second passivation antireflection layer 6 and is in electrical contact with a second doped semiconductor layer 5.
  • the distance between the first electrode 10 and the first region C1 in the direction perpendicular to the thickness direction of the semiconductor substrate 1 (parallel to the first surface A) is greater than or equal to 300 ⁇ m. Therefore, during the electrode fabrication process, it can effectively prevent the slurry used to fabricate the electrode from leaking and distributing over a larger area on the side of the battery, thus preventing serious damage to the battery's electrical performance.
  • the first doped semiconductor layer 3 is one or more of doped polycrystalline silicon, doped amorphous silicon, and doped microcrystalline silicon.
  • the first doped semiconductor layer 3 is doped polycrystalline silicon, with a thickness typically between 80 nm and 500 nm and a doping concentration typically between 1* 1017 and 1* 1021 atoms/ cm3 .
  • the side surface C further includes a third region C3 adjacent to the second region C2, and the third region C3 is closer to the second surface B than the second region C2. That is, the above-described solar cell further includes a third semiconductor substrate 13, integrally formed with the second semiconductor substrate 12, and the third semiconductor substrate 13 is closer to the second surface B than the second semiconductor substrate 12.
  • the third region C3 protrudes in a direction away from the side C compared to the second region C2.
  • the protrusion height d2 of the third region C3 is greater than the protrusion height d1 of the first region C1.
  • the protrusion height d2 of the third region C3 is 3 ⁇ m to 10 ⁇ m, for example, it can be 3 ⁇ m, 5 ⁇ m, 6 ⁇ m, 8 ⁇ m, or 10 ⁇ m, but is not limited to the values mentioned.
  • the second doped semiconductor layer 5 when a second doped semiconductor layer 5 is formed on the second surface B, the second doped semiconductor layer 5 is deposited around the side surface C.
  • a third region C3 is formed in the area of the side surface C near the second surface B.
  • the third region C3 protrudes in a direction away from the side surface C compared to the second region C2.
  • This increases the spatial electrical isolation distance between the first surface A and the second surface B, which can better prevent leakage current on the side of the solar cell.
  • it can effectively prevent the paste used to prepare the electrode on the second surface B from leaking to the side, thereby avoiding damage to the performance of the cell.
  • the third region C3 protrudes in a direction away from the side C compared to the second region C2, which can increase the junction area of the PN junction formed by the semiconductor substrate 1 and the second doped semiconductor layer 5, which is beneficial to improving the photocurrent of the solar cell.
  • the present invention provides another embodiment, as shown in FIG13, where the plating of the second doped semiconductor layer 5 around the side surface C is a fifth doped semiconductor layer 51.
  • the fifth doped semiconductor layer 51 is formed in a local region of the side surface of the semiconductor substrate 1 and is integrally continuous with the second doped semiconductor layer 5.
  • the fifth doped semiconductor layer 51 and the second doped semiconductor layer 5 have the same conductivity type, and the ratio between the maximum extension length of the fifth doped semiconductor layer 51 along the thickness direction of the semiconductor substrate 1 and the thickness of the semiconductor substrate 1 is greater than 5% and less than or equal to 50%.
  • a first tower-like textured structure 16 is formed on the surface of the side surface of the semiconductor substrate 1 in a region not corresponding to the fifth doped semiconductor layer 51. At least a portion of the first tower-like textured structure 16 has a side length greater than or equal to 10 ⁇ m.
  • a first doped semiconductor layer 3 is formed on one side of the first surface of the semiconductor substrate 1. The first doped semiconductor layer 3 and the second doped semiconductor layer 5 have opposite conductivity types.
  • the solar cell provided in this embodiment of the present application includes a second doped semiconductor layer 5 and a first doped semiconductor layer 3 with opposite conductivity types, located on opposite sides of the second and first surfaces of the semiconductor substrate 1, respectively.
  • One of the second doped semiconductor layer 5 and the first doped semiconductor layer 3 can form a PN junction with the semiconductor substrate 1, and the other can form a high-low junction with the semiconductor substrate 1.
  • carriers with opposite conductivity types are shunted, causing carriers of corresponding conductivity types to move towards and be collected by the second doped semiconductor layer 5 and the first doped semiconductor layer 3, respectively.
  • a fifth doped semiconductor layer 51 is formed by being deposited around the side surface of the semiconductor substrate 1 and at least part of the first surface. Because the fifth doped semiconductor layer 51 and the first doped semiconductor layer 3 have opposite conductivity types, before forming the first doped semiconductor layer 3, it is necessary to remove a portion of the fifth doped semiconductor layer 51 located near the first surface and side surface to prevent a short circuit between the second doped semiconductor layer 5 and the first doped semiconductor layer 3 through the fifth doped semiconductor layer 51.
  • the solar cell provided by this application embodiment only the portion of the fifth doped semiconductor layer 51 located near the first surface and side surface needs to be removed. This not only prevents short circuits but also helps solve the problem in the prior art where removing the entire portion of the fifth doped semiconductor layer 51 formed on the side surface leads to over-etching of the second doped semiconductor layer 5 on the second surface side. This ensures that the second doped semiconductor layer 5 has a larger formation range on the second surface side, capable of covering the edge region of the second surface. Furthermore, the presence of the fifth doped semiconductor layer 51 retained in the local area on the side surface helps increase the area of the junction region (PN junction or high/low junction) near the second surface side. Secondly, in this embodiment, retaining the fifth doped semiconductor layer 51 located in the side local area also helps to improve etching capacity and reduce cleaning fluid consumption and etching cost.
  • the surface of the aforementioned first pyramidal texture structure 16 is relatively flat, indicating that after removing the fifth doped semiconductor layer 51 on the side near the first surface and removing the doped silicon layer deposited around at least part of the side when forming the first doped semiconductor layer 3, there are no residual fifth doped semiconductor layer 51 and doped silicon layer on at least part of the side near the first surface, preventing short circuits.
  • the different maximum extension lengths of the fifth doped semiconductor layer 51 along the thickness direction of the semiconductor substrate 1 lead to different requirements for suppressing leakage current between the fifth doped semiconductor layer 51 and the first doped semiconductor layer 3.
  • the ratio between the maximum extension length of the retained fifth doped semiconductor layer 51 along the thickness direction of the semiconductor substrate 1 and the thickness of the semiconductor substrate 1 is greater than 5% and less than or equal to 50%, and when at least a portion of the aforementioned first tower-like textured structure 16 has a side length greater than or equal to 10 ⁇ m, it can be ensured that the fifth doped semiconductor layer 51 and the first doped semiconductor layer 3 can be isolated through the gap region located between them, reducing the leakage risk between them and improving the working performance of the solar cell.
  • a third texture structure 17 may be formed on the second surface, and a fourth texture structure 18 may be formed on the side surface of the semiconductor substrate 1 corresponding to the region of the fifth doped semiconductor layer 51.
  • the morphology of the fourth texture structure 18 may be the same as or different from that of the third texture structure 17.
  • the third texture structure and/or the fourth texture structure may be a textured structure such as a pyramidal structure, or a non-pyramidal structure (such as a hole-type structure, a V-groove structure, or a tower-based structure) or a polished structure.
  • the one-dimensional dimension of the fourth texture structure 18 can be smaller than the one-dimensional dimension of the third texture structure 17.
  • the one-dimensional dimension of the fourth texture structure 18 can be equal to or greater than the one-dimensional dimension of the third texture structure 17.
  • the one-dimensional dimension of the fourth texture structure 18 is smaller than the one-dimensional dimension of the third texture structure 17.
  • a third texture structure 17 with a relatively large one-dimensional dimension is formed on the second surface of the semiconductor substrate 1. This is beneficial for increasing the specific surface area of the second surface, ensuring that one side of the second surface has a good light-trapping effect, and allowing more light to be refracted through one side of the second surface into the semiconductor substrate 1 and utilized by the semiconductor substrate 1, thereby improving the photoelectric conversion efficiency of the solar cell.
  • a fourth texture structure 18 with a relatively small one-dimensional dimension is formed on the surface of the side of the semiconductor substrate 1 corresponding to the fifth doped semiconductor layer 51. This is beneficial for reducing the surface flatness difference of the side of the semiconductor substrate 1 corresponding to the fifth doped semiconductor layer 51, and reducing the number of recombination centers.
  • the side of the first tower-shaped textured structure 16 closest to the semiconductor substrate 1 is quadrilateral. Based on this, the side length of the first tower-shaped textured structure 16 can be the length of any side of the bottom (the side closest to the semiconductor substrate 1) of the first tower-shaped textured structure 16.
  • the side length of at least a portion of the first tower-like textured structure can be less than or equal to 15 ⁇ m.
  • the side length of at least a portion of the first tower-like textured structure can be 10 ⁇ m, 11 ⁇ m, 12 ⁇ m, 13 ⁇ m, 14 ⁇ m, or 15 ⁇ m, etc.
  • the solar cell also includes the first or second passivation antireflection layer mentioned above, when the side length of at least part of the first tower-like texture structure is less than or equal to 15 ⁇ m, it is also beneficial to prevent the thickness of the first or second passivation antireflection layer formed on the surface from being too small due to the excessive side length of the first tower-like texture structure.
  • the first or second passivation antireflection layer has a good passivation effect on the surface of the semiconductor substrate that does not correspond to the fifth doped semiconductor layer, reduces the number of defects at the surface, and further reduces the carrier recombination rate.
  • a fifth doped semiconductor layer 51 is formed in a localized area on the side surface of the semiconductor substrate 1.
  • a first tower-like textured structure 16 is formed on the surface of the side surface of the semiconductor substrate 1 in a region not corresponding to the fifth doped semiconductor layer.
  • the side lengths of the first tower-like textured structures 16 formed on different portions of the surface of the side surface of the semiconductor substrate 1 in a region not corresponding to the fifth doped semiconductor layer 51 can be approximately the same.
  • a first tower-like textured structure is formed in a second region C2 in the side surface C of the semiconductor substrate 1; a second tower-like textured structure is formed in the first region C1 and/or the first surface in the side surface C of the semiconductor substrate 1, with at least a portion of the first tower-like textured structure having a side length greater than that of the second tower-like textured structure.
  • it is advantageous to increase the area of the junction region (PN junction or high-low junction) near the first surface increase the intensity of the built-in electric field near the first surface, and further facilitate the acceleration of carrier shunting and transport rate toward the second doped semiconductor layer 5 and the first doped semiconductor layer 3, thereby improving carrier collection efficiency.
  • the side length of at least a portion of the first tower-like textured structure formed in the second region C2 in the side surface of the semiconductor substrate 1 is greater than the side length of the second tower-like textured structure formed in the first region C1 and/or the first surface, which can reduce the short-circuit risk between the fifth doped semiconductor layer 51 and the first doped semiconductor layer located in the side surface of the semiconductor substrate 1.
  • the side length of the first tower-like textured structure can be greater than or equal to 10.5 ⁇ m.
  • the side length of the first tower-like textured structure is within the above range, which can prevent the small spacing between the first doped semiconductor layer 3 and the fifth doped semiconductor layer 51 along the thickness direction of the semiconductor substrate due to the small value of the side length of the first tower-like textured structure, thus preventing a low degree of reduction in leakage risk and ensuring that the side of the semiconductor substrate has a low carrier recombination rate.
  • a plurality of first texture structure groups extending along a third direction and arranged along a fourth direction are formed in the second region (C2) on the side of the semiconductor substrate.
  • Each first texture structure group includes a plurality of first tower-shaped texture structures 16 arranged along the third direction.
  • the third direction is different from the fourth direction, and the third direction is inclined relative to the second surface.
  • the arrangement of the different first tower-shaped texture structures 16 is more regular, which is beneficial to improving the surface flatness of the second region (C2) on the side and increasing the formation thickness of the first or second passivation antireflection layer above the side, thereby improving the passivation effect of the first or second passivation antireflection layer on the side.
  • the third direction and the fourth direction can be any two different directions parallel to the side, as long as the third direction is inclined relative to the second surface.
  • the extension direction of the first texture structure group i.e., the third direction
  • the third direction is approximately parallel to the direction when cutting the semiconductor substrate, and cutting is performed along the direction inclined to the thickness direction of the semiconductor substrate, which helps to reduce cutting resistance and reduce the cutting difficulty of the semiconductor substrate.
  • a second tower-like textured structure is formed on the first surface and/or the first region C1.
  • the morphology of at least one second tower-like textured structure may be the same as or different from that of the first tower-like textured structure.
  • the side length of at least one first tower-like textured structure may be greater than the side length of the second tower-like textured structure. The side length of the first tower-like textured structure being greater than the side length of the second tower-like textured structure formed on the first surface or the first region C1 helps to prevent short circuits.
  • At least a portion of the second tower-shaped texture structure may be recessed along the direction close to the semiconductor substrate 1, and at least a portion of the second tower-shaped texture structure is quadrilateral on the side close to the semiconductor substrate 1.
  • the side length of the second pyramidal texture structure can be greater than or equal to 5 ⁇ m and less than or equal to 13 ⁇ m.
  • the side length of the second pyramidal texture structure can be 5 ⁇ m, 6 ⁇ m, 8 ⁇ m, 8.5 ⁇ m, 9 ⁇ m, 9.5 ⁇ m, 10 ⁇ m, 10.5 ⁇ m, 11 ⁇ m, or 13 ⁇ m, etc.
  • Having the side length of the second pyramidal texture structure within the above range helps prevent the etchant from etching the first surface side of the semiconductor substrate incompletely due to a shorter etching time caused by a smaller side length.
  • it helps prevent the first surface side of the semiconductor substrate from being over-etched due to a larger side length resulting in a larger specific surface area, ensuring a greater light absorption depth and higher photoelectric conversion efficiency of the solar cell.
  • the end of the fifth doped semiconductor layer near the first surface has an uneven feature.
  • the boundary between the region corresponding to the fifth doped semiconductor layer and the region not corresponding to the fifth doped semiconductor layer is serrated or wavy, the surface area of the sidewall of the boundary is further increased, which is beneficial for light absorption.
  • the wavy shape of the sidewall of the boundary can increase the multiple reflections of light.
  • the boundary between the region corresponding to the first doped semiconductor layer 3 and the region not corresponding to the first doped semiconductor layer 3 on the side surface of the semiconductor substrate can be a flat straight line.
  • the boundary between the region corresponding to the first doped semiconductor layer 3 and the region not corresponding to the first doped semiconductor layer 3 on the side surface of the semiconductor substrate can be a serrated or wavy curve.
  • the semiconductor substrate may further have a chamfered surface connecting the second surface and the first surface.
  • This chamfered surface may be a plane on which no textured structure is formed.
  • a plurality of second textured structure groups extending along a fifth direction and spaced apart along a sixth direction may be formed on the chamfered surface.
  • the fifth direction is different from the sixth direction and is substantially parallel to the thickness direction of the semiconductor substrate 1.
  • each second textured structure group includes a plurality of clustered textured structures extending along the sixth direction and arranged along the fifth direction.
  • the surface of the region located between two adjacent second textured structure groups has a concave-convex zigzag shape arranged along the fifth direction.
  • a clustered texture structure arranged in a certain pattern is formed on the chamfered surface of the semiconductor substrate 1, and when the surface of the region between two adjacent second texture structure groups composed of different clustered texture structures is arranged in a concave-convex zigzag shape along the fifth direction, the chamfered surface has an uneven surface morphology, which is beneficial to increasing the specific surface area of the chamfered surface, which is beneficial to making the chamfered surface have a good light trapping effect, and further improving the utilization rate of light by the semiconductor substrate 1.
  • the size and distribution of the clustered texture structure, the specific orientation of the fifth and sixth directions, and the degree of undulation of the surface of the region between two adjacent second texture structure groups in the chamfered surface are not specifically limited.
  • the fifth direction may be approximately parallel to the thickness direction of the semiconductor substrate
  • the sixth direction may be parallel to the edge of the chamfered surface along the thickness direction of the semiconductor substrate.
  • the solar cell is a solar cell with a single-sided electrode, such as an interdigitated back contact (IBC) cell.
  • IBC interdigitated back contact
  • Figure 20 is a cross-sectional schematic diagram of a back-contact solar cell provided in an embodiment of this application.
  • Figure 21 is a top view of the first surface of the back-contact solar cell provided in an embodiment of this application.
  • this application provides a back-contact solar cell.
  • a first surface A of a semiconductor substrate 1 has an electrode collection region, which includes a plurality of minority carrier regions 100 and a plurality of majority carrier regions 200 alternately distributed along a second direction, and an isolation region 300 is provided between adjacent minority carrier regions 100 and majority carrier regions 200.
  • the first doped semiconductor layer 3 includes a third doped semiconductor layer 31 and a fourth doped semiconductor layer 32; wherein, the third doped semiconductor layer 31 for collecting and venting minority carriers is disposed in the minority carrier region 100; and the fourth doped semiconductor layer 32 for collecting and venting majority carriers is disposed in the majority carrier region 200.
  • the third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 have opposite conductivity types, with one of the third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 being N-type and the other being P-type.
  • the conductivity type of the third doped semiconductor layer 31 can be N-type, in which case the conductivity type of the fourth doped semiconductor layer 32 is P-type; or, the conductivity type of the third doped semiconductor layer 31 can be P-type, in which case the conductivity type of the fourth doped semiconductor layer 32 is N-type.
  • a plurality of third doped semiconductor layers 31 extend in a first direction in a first plane parallel to the first surface A.
  • a plurality of fourth doped semiconductor layers 32 extend in a first direction, and a plurality of third doped semiconductor layers 31 and a plurality of fourth doped semiconductor layers 32 are alternately distributed on a first surface A in a second direction perpendicular to the first direction within a first plane.
  • the third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 are also located on a portion of the surface of the first region C1.
  • a first doped semiconductor layer 31 located on the minority carrier region 100 at the outermost edge of the semiconductor substrate 1 extends vertically from the first plane to a portion of the surface of the first region C1 on the side surface C; and/or, a second doped semiconductor layer 32 located on the majority carrier region 200 at the outermost edge of the semiconductor substrate 1 extends vertically from the first plane to a portion of the surface of the first region C1 on the side surface C.
  • a first interface passivation layer is further formed between the semiconductor substrate 1 and the third doped semiconductor layer 31.
  • a second interface passivation layer is further formed between the semiconductor substrate 1 and the fourth doped semiconductor layer 32.
  • the first interface passivation layer and/or the second interface passivation layer include one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon.
  • the first passivation antireflection layer 4 of the aforementioned back-contact solar cell is located on the surfaces of the third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 away from the semiconductor substrate 1, and on the semiconductor substrate 1 of the isolation region 300.
  • the material of the first passivation antireflection layer 4 includes one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon.
  • the first passivation antireflection layer 4 is used to achieve surface passivation and antireflection functions of the back-contact solar cell.
  • the aforementioned back-contact solar cell further includes: a first electrode 10, which penetrates the first passivation and antireflection layer 4 and is in electrical contact with the third doped semiconductor layer 31; and a second electrode 20, which penetrates the first passivation and antireflection layer 4 and is in electrical contact with the fourth doped semiconductor layer 32.
  • the width of the first electrode 10 is 5 ⁇ m to 600 ⁇ m, for example, it can be 5 ⁇ m, 10 ⁇ m, 100 ⁇ m, 500 ⁇ m, or 600 ⁇ m, but is not limited to the values mentioned.
  • the width of the second electrode 20 is 5 ⁇ m to 600 ⁇ m, for example, it can be 5 ⁇ m, 10 ⁇ m, 100 ⁇ m, 500 ⁇ m, or 600 ⁇ m, but is not limited to the values mentioned.
  • the materials of the first electrode 10 and/or the second electrode 20 include, but are not limited to, one or more of metals, metal oxides, metal nitrides, metal carbides, and metal sulfides.
  • the first electrode 10 and/or the second electrode 20 may also be other conductive connecting materials such as graphene.
  • an electrode paste is coated onto the first passivation and antireflection layer 4 on the first surface A, and then sintered so that the electrode paste passes through the first passivation and antireflection layer 4 and forms contact with the doped semiconductor layer.
  • this application provides a photovoltaic module including the solar cell described above.

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Abstract

本申请提供一种太阳能电池及光伏组件，属于太阳能电池技术领域。上述太阳能电池包括：半导体基底，半导体基底具有相对的第一表面和第二表面，以及邻接于第一表面和第二表面之间的多个侧面；钝化接触结构，至少位于半导体基底的部分第一表面上，钝化接触结构包括依次层叠的界面钝化层和第一掺杂半导体层；其中，在第一表面指向第二表面的方向上，侧面包括依次邻近的第一区域和第二区域，第一区域相比于第二区域在远离侧面的方向上凸起；第一掺杂半导体层还位于第一区域的表面上，其中位于第一区域上的第一掺杂半导体层与位于第一表面上的第一掺杂半导体层一体连续。

Description

太阳能电池及光伏组件
相关申请的交叉引用
本申请要求2024年09月12日提交的、申请号为202411280473.1的中国专利申请以及2024年05月15日提交的、申请号为202410605390.9的中国专利申请的优先权和利益，其内容通过引用全部纳入本文。
技术领域
本申请涉及一种太阳能电池，尤其涉及一种太阳能电池及光伏组件。
背景技术
相关技术中，太阳能电池包括N型区和P型区，N型区和P型区之间需要一定程度的电隔离，一般可以通过湿法刻蚀等工艺将N型区和P型区进行隔断处理，但现有的方式并不完善，太阳能电池的正面与背面之间仍然存在着漏电的风险。
同时，由于在搬运过程中，电池边缘极易发生互相摩擦，导致钝化膜层发生脱落或者划伤，导致基底裸露在外。这种情况下，表面钝化层被破坏，会导致电池钝化性能减弱，从而影响电池性能。
发明内容
有鉴于此，有必要针对相关技术中太阳能电池存在的缺陷，提供一种太阳能电池及太阳能电池形成的光伏组件。
根据本申请一个方面的实施例，提供了一种太阳能电池，包括：
半导体基底，半导体基底具有相对的第一表面和第二表面，以及邻接于第一表面和第二表面之间的多个侧面；
钝化接触结构，至少位于半导体基底的部分第一表面上，钝化接触结构包括依次层叠的界面钝化层和第一掺杂半导体层；
其中，在第一表面指向第二表面的方向上，侧面包括依次邻近的第一区域和第二区域，第一区域相比于第二区域在远离侧面的方向上凸起；第一掺杂半导体层还位于第一区域的表面上，其中位于第一区域上的第一掺杂半导体层与位于第一表面上的第一掺杂半导体层一体连续。
根据本申请上述实施例提供的太阳能电池，在平行于第一表面的方向上，至少一个侧面的第一区域相比于第二区域在远离侧面的方向上凸起，有利于增大第一表面的钝化接触结构的有效面积，提升第一表面的钝化接触性能，提高载流子收集效率，进而提升太阳能电池的效率。
根据本申请上述实施例提供的太阳能电池，在平行于第一表面的方向上，至少一个侧面的第一区域相比于第二区域在远离侧面的方向上凸起，由于第一区域的凸起部的表面与第二区域的表面具有一定的距离，能够增强电池正面与背面之间的电隔离(第一表面与第二表面的空间电性隔离距离)，减小正面与背面之间漏电的风险；同时，在制备电极的过程中，也可以有效阻挡制备电极所用的浆料泄露分布在电池侧面的更大范围内，对电池的电性能造成严重损害。并且，第一区域的突出，能够减小太阳能电池发生剐蹭对太阳能电池性能造成的损害。
根据本申请上述实施例提供的太阳能电池，第一掺杂半导体层还位于第一区域的部分表面上，在降低漏电风险的同时，能够增大钝化接触结构的有效面积，提高载流子的收集效率。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本申请的一些实施例，而非对本申请的限制。
图1为本申请实施例提供的太阳能电池的剖面示意图；
图2为本申请实施例提供的太阳能电池的局部剖面示意图；
图3为本申请另一实施例提供的半导体基底的俯视示意图；
图4为本申请另一实施例提供的太阳能电池的剖面示意图；
图5为本申请另一实施例提供的太阳能电池的局部剖面示意图；
图6为本申请另一实施例提供的太阳能电池的剖面示意图；
图7为本申请又一实施例提供的太阳能电池的剖面示意图；
图8为本申请实施例提供的太阳能电池的侧面的扫描电子显微镜图；
图9为本申请再一实施例提供的太阳能电池的局部剖面示意图；
图10为图9中的太阳能电池的侧面的扫描电子显微镜图；
图11为本申请又一实施例提供的太阳能电池的局部剖面示意图；
图12为本申请再一实施例提供的太阳能电池的剖面示意图；
图13为本申请实施例提供的太阳能电池的纵向剖视示意图；
图14为本申请实施例提供的太阳能电池的侧面SEM图一；
图15为本申请实施例提供的太阳能电池的侧面SEM图二；
图16为本申请实施例提供的太阳能电池的侧面的3D图；
图17为本申请实施例提供的太阳能电池的倒角面的SEM图一；
图18为本申请实施例提供的太阳能电池的倒角面的SEM图二；
图19为本申请实施例提供的太阳能电池的倒角面的SEM图三；
图20为本申请实施例提供的背接触太阳能电池的剖面示意图；以及
图21为本申请实施例提供的背接触太阳能电池的第一表面的俯视示意图。
附图标记说明：
1-半导体基底；
A-第一表面；
B-第二表面；
C-侧面；
C1-第一区域；
C2-第二区域；
C3-第三区域；
11-第一半导体基底部；
12-第二半导体基底部；
13-第三半导体基底部；
d1-第一区域的凸起高度；
d2-第三区域的凸起高度；
2-界面钝化层；
3-第一掺杂半导体层；
31-第三掺杂半导体层；
32-第四掺杂半导体层；
4-第一钝化减反层；
5-第二掺杂半导体层；
51-第五掺杂半导体层；
6-第二钝化减反层；
10-第一电极；
20-第二电极；
111-重掺杂的半导体基底层；
100-少子区；
200-多子区；
300-隔离区；
16-第一塔基状纹理结构；
17-第三纹理结构；
18-第四纹理结构。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本申请作进一步的详细说明。但是，本申请能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使本申请清楚且完整，并且将本申请的范围完全地传递给本领域技术人员。在附图中，相同附图标记表示相同元件。
在附图中示出了根据本申请实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本申请的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。为了使本申请所要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
此外，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。“若干”的含义是一个或一个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在此使用的术语仅仅是为了描述具体实施例，而并非意在限制本申请。在此使用的术语“包括”、“包含”等表明了所述特征、步骤、操作和/或部件的存在，但是并不排除存在或添加一个或多个其他特征、步骤、操作或部件。
如图1-图2，太阳能电池包括：半导体基底1，半导体基底1具有相对的第一表面A和第二表面B，侧面C；钝化接触结构，至少位于半导体基底1的部分第一表面A上，钝化接触结构包括依次层叠的界面钝化层2和第一掺杂半导体层3；以及第一钝化减反层4；其中，在第一表面A指向第二表面B的方向上，半导体基底的侧面C包括相邻的第一区域C1和第二区域C2，第一区域C1相比于第二区域C2在远离侧面C的方向上凸起。
参考图2所示，第一掺杂半导体层3可以从半导体基底1的第一表面A延伸至第一区域C1上并覆盖在第一区域C1上；位于第一区域C1上的第一掺杂半导体层3与位于第一表面A上的第一掺杂半导体层3一体连续。该结构在一定程度上抑制了漏电的情况。同时，在制备电极的过程中，也可以有效阻挡制备电极所用的浆料泄露分布在电池侧面的更大范围内，而对电池的电性能造成严重损害。并且，第一区域C1的突出，能够减小太阳能电池发生剐蹭对太阳能电池性能造成的损害。
根据本申请的一种示例性实施例，参考图3、图4所示，邻近第二区域C2的部分第一区域C1的表面未覆盖有第一掺杂半导体层3。
在本实施例中，在第一表面A指向第二表面B的方向上，半导体基底1包括第一半导体基底部11和与第一半导体基底部11一体形成的第二半导体基底部12；侧面C包括位于第一半导体基底部11侧面的第一区域C1和位于第二半导体基底部12侧面的第二区域C2，至少一个侧面C的第一区域C1相比于第二区域C2在远离侧面C的方向上凸起。
根据本申请的实施例，在平行于第一表面A的截面上，第一半导体基底部11的面积大于第二半导体基底部12的面积。
根据本申请的实施例，第一区域C1相比于第二区域C2的凸起高度d1为0.5μm～5μm，例如可以为0.5μm、1μm、2μm、5μm，但不限于所举数值。
根据本申请的实施例，半导体基底1可以为硅基底。或者，上述半导体基底1也可以为锗硅基底、锗基底或砷化镓基底等任一种半导体材质的基底。另外，上述半导体基底1可以为N型半导体基底，也可以为P型半导体基底。半导体基底1可以为单晶或多晶。
根据本申请的实施例，半导体基底1的形状为矩形，矩形的相邻两边之间具有倒角。参考图3所示，半导体基底1例如包括8个侧面C。
根据本申请的实施例，钝化接触结构从半导体基底1的第一表面A延伸至至少一个侧面C的第一区域C1的部分表面上。钝化接触结构不完全覆盖第一区域C1，能够降低钝化接触结构带来的短路风险。另外，第一区域C1与第二区域C2之间为台阶结构，在台阶结构的侧壁上，即第一区域C1与第二区域C2之间的连接侧壁上可能存在衬底的掺杂区域，第一掺杂半导体层3与台阶侧壁上的掺杂区域容易接触，从而导致第一掺杂半导体层3与半导体基底1的直接接触，引发电池的不良短路。因此设置第一掺杂半导体层3远离该侧壁能够避免上述情况的发生。
根据本申请的实施例，在第一表面A指向第二表面B的方向上，位于第一区域C1的表面上的第一掺杂半导体层3与第二区域C2的间距大于或等于1μm。
根据本申请的实施例，在垂直于第一表面A的方向上，第一掺杂半导体层3在第一区域C1的分布宽度小于第一区域C1的宽度的80％。
根据本申请的实施例，第一区域C1在垂直于第一表面A的方向上的宽度与半导体基底1的厚度的比例范围为1％～20％，例如可以为1％、5％、10％、15％、20％，但不限于所举数值。比例范围如果过小，难以实现增大钝化接触结构面积、提高载流子收集效率的技术效果；比例范围如果过大，第一表面A与第二表面B之间容易发生漏电风险。
根据本申请的实施例，第一半导体基底部11在垂直于第一表面A的方向上的厚度范围为0.5μm～20μm，例如可以为0.5μm、1μm、5μm、10μm、20μm，但不限于所举数值；第一半导体基底部11在垂直于第一表面A的方向上的厚度即为第一区域C1在第一表面A指向第二表面B方向上的宽度。
根据本申请的实施例，在平行于第一表面A的方向上，至少一个侧面C的第一区域C1相比于第二区域C2沿远离侧面C1的方向凸起，有利于增大第一表面A的钝化接触结构的有效面积，提升第一表面A的钝化接触性能，提高载流子收集效率，进而提升太阳能电池的效率。
由于掺杂半导体层的掺杂浓度通常较大，太阳能电池的漏电通常发生在不同掺杂类型的掺杂半导体层之间。在第一区域C1在垂直于第一表面A的方向上的宽度很大的情况下，覆盖在第一区域C1上的第一掺杂半导体层3容易与位于第二表面B的第二掺杂半导体层5发生漏电。
通过将第一区域C1的宽度设置为半导体基底厚度的1％～20％，并且第一掺杂半导体层3位于第一区域C1的部分表面上，降低第一掺杂半导体层3与第二表面B发生漏电的风险。
根据本申请上述实施例提供的太阳能电池，第一掺杂半导体层位于第一区域的部分表面上，在降低漏电风险的同时，能够增大钝化接触结构的有效面积，提高载流子的收集效率。
根据本申请的实施例，太阳能电池可以为双面太阳能电池，例如隧穿氧化钝化接触太阳能电池(Tunnel Oxide Passivated Contact，TOPCon)、异质结太阳能电池(Heterojunction with Intrinsic Thin-layer，HIT)。
根据本申请的实施例，界面钝化层2包括本征非晶硅层、低掺杂本征非晶硅层(掺杂浓度低于第一掺杂半导体层)和介质层中的一种，介质层包括但不限于氧化硅、氧化铝、掺杂氧化铝、氮化硅、碳氮化硅。第一掺杂半导体层3为掺杂多晶硅层、掺杂微晶硅层、掺杂纳米晶硅层和掺杂非晶硅层中的至少一种。
根据本申请的实施例，界面钝化层2例如为隧穿氧化硅，第一掺杂半导体层3例如为掺杂多晶硅。
根据本申请的实施例，界面钝化层2例如为本征非晶硅，第一掺杂半导体层3例如为掺杂非晶硅。
根据本申请的实施例，TOPCon太阳能电池还包括：第二掺杂半导体层5，至少位于半导体基底1的第二表面B内，用作TOPCon太阳能电池的发射极区(emitter)；第二掺杂半导体层5与第一掺杂半导体层3中的一个为N型，第二掺杂半导体层5与第一掺杂半导体层3中的另一个为P型。
根据本申请的实施例，TOPCon太阳能电池还包括第二钝化减反层6，至少位于第二掺杂半导体层5的远离半导体基底1的表面上。第二钝化减反层6用于实现半导体基底1的第二表面B的钝化和减反射功能。
根据本申请的实施例，参考图5所示，可选的，半导体基底1的第一表面A和第一区域C1的表面处形成有重掺杂的半导体基底层111，此处的重掺杂的半导体基底层111可以理解为掺杂浓度大于半导体基底1本身的掺杂浓度。具体而言，由于在形成第一掺杂半导体层3的过程中需要加入掺杂元素，部分掺杂元素会扩散进入半导体基底1内，使得半导体基底1的靠近第一表面A和第一区域C1的部分区域的掺杂元素的浓度大于半导体基底1的掺杂浓度。可选地，重掺杂的半导体基底层111可以位于第一区域C1的部分表面上，也可以位于第一区域C1的整个表面上。
在一些实施例中，参考图6所示，可选的，至少一个侧面C的第一区域C1为自远离第一表面A的一侧向靠近第一表面A的一侧沿远离侧面(C)方向延伸的斜面。如此能够增大第一表面A的表面积，增大位于第一表面A的钝化接触结构的面积，有利于提高载流子收集效率。并且能够增加整个侧面在垂直于第一表面A方向上的宽度，更有利于第一表面A和第二表面B之间的隔离。
根据本申请的实施例，钝化接触结构从半导体基底1的第一表面A延伸至至少一个侧面C的第一区域C1的部分表面上。
根据本申请的实施例，界面钝化层2和第一掺杂半导体层3还位于第一区域C1的部分表面上，可以增大由界面钝化层2和第一掺杂半导体层3组成的钝化接触结构的表面积，能够提高载流子收集效率，进而提高太阳能电池的效率。
第一区域C1为斜面，较为平坦，有利于在侧面C沉积成膜质量更佳的第一钝化减反层4，提高第一钝化减反层4的钝化和减反射的效果。
在一些实施例中，参考图7，由于至少一个侧面C的第一区域C1为自远离第一表面A的一侧向靠近第一表面A的一侧沿远离半导体基底1的方向延伸的斜面，第一区域C1和第二区域C2之间不具有较大的台阶，因此有利于提高第一钝化减反层的钝化效果，在考虑更优的钝化效果时，也可以将第一掺杂半导体层3覆盖在第一区域C1的绝大部分表面，甚至覆盖在全部第一区域C1上。
图8为本申请一种实施例的太阳能电池的侧面的扫描电子显微镜图。
参考图8所示，可选的，第一区域C1处具有多个孔洞，孔洞在平行于第一表面A的方向上凹陷至半导体基底1内。
根据本申请的实施例，钝化接触结构从半导体基底1的第一表面A延伸至至少一个侧面C的第一区域C1的部分表面上。孔洞在平行于第一表面A的方向上穿过钝化接触结构凹陷至半导体基底1内，第一钝化减反层4位于第一区域C1处的钝化接触结构上和孔洞的侧壁和底面，使得孔洞内的第一钝化减反层4中的氢进入半导体基底1，提高半导体基底1的氢钝化效果，从而提高太阳能电池的效率。一般而言，第一钝化减反层4可以包括氧化铝、氮化硅、氮氧化硅中的一层或多层，例如氧化铝和氮化硅的叠层。沉积氧化铝时会引入大量的氢，由于孔洞结构，大量的氢可以进入半导体基底1。
可选的，孔洞在靠近第一表面A的区域的分布密度小于在靠近第二区域C2的区域的分布密度。在靠近第一表面A的区域的孔洞的分布密度较低，能够减少载流子在靠近第一表面A的区域的复合中心，减少载流子的复合，从而提高载流子的收集效率。
可选的，孔洞的径向尺寸在平行于第一表面A的方向上从第一区域C1处的表面至半导体基底1逐渐减小。也就是说，孔洞为在平行于第一表面A的方向上从第一区域C1处的表面至半导体基底1延伸的倒金字塔结构。
可选的，孔洞的径向尺寸小于5μm，优选小于2μm，更优选小于1μm；孔洞的径向尺寸例如可以为4μm、3μm、2μm、1μm，但不限于所举数值。
可选的，孔洞在第一区域C1的投影面积与第一区域的表面积的比值范围为1％～30％，例如可以为1％、5％、10％、20％、30％，但不限于所举数值。比值范围过小，难以实现提高半导体基底钝化效果和增大钝化接触结构面积的技术效果，或者说效果不明显；比例范围过大，造成半导体基底1的缺陷过多，不利于载流子的有效收集。
根据本申请的实施例，孔洞结构在第一区域C1被掺杂半导体层3或者钝化接触结构覆盖的区域的分布密度和径向尺寸均小于第一区域C1未被掺杂半导体层3覆盖的区域。如此能够减小对钝化接触结构的破坏。
图9为本申请再一实施例提供的太阳能电池的局部剖面示意图。
图10为图9中的太阳能电池的侧面的扫描电子显微镜图。
在一些实施例中，参考图9、图10所示，第一区域C1上具有凸起的棱，棱沿大致平行于第一表面A的方向延伸。
参考图9所示，第一掺杂半导体层3还位于第一区域C1的部分表面上；位于第一区域C1上的第一掺杂半导体层3与位于第一表面A上的第一掺杂半导体层3一体连续；邻近第二区域C2的部分第一区域C1的表面未覆盖有第一掺杂半导体层3。第一区域C1上具有凸起的棱，第一掺杂半导体层3位于第一区域C1的部分表面上，能够增强电池正面和背面之间的电隔离，并且在漏电可控的情况下，能够增大第一掺杂半导体层3的表面积，有利于提高载流子收集效率。
在一些实施例中，参考图11所示，第一区域C1上具有凸起的棱，棱沿大致平行于第一表面A的方向延伸，可以增大第一区域C1的表面积。在漏电可控的情况下，第一掺杂半导体层3覆盖在全部第一区域C1上，可以增大第一掺杂半导体层3的表面积，进而有利于提高载流子收集效率。
由于至少一个侧面C的第一区域C1上具有凸起的棱，棱沿大致平行于第一表面A的方向延伸；也就是说，第一区域C1的靠近第二区域C2的部分区域为自第二区域C2的一侧向所述棱一侧沿远离半导体基底1的方向延伸的斜面。
第一区域C1和第二区域C2之间可不具有较大的台阶，甚至没有台阶，如此有利于提高钝化减反层的钝化效果，在考虑钝化效果时，也可以将第一掺杂半导体层覆盖在第一区域C1的绝大部分表面，甚至覆盖在全部第一区域C1上。根据本申请的实施例，第二区域C2具有塔基结构，第一区域C1在垂直于第一表面A的方向上的宽度小于第二区域C2的塔基结构的尺寸，其中塔基结构的尺寸定义为塔基结构的边长或对角线长度。
在一些实施例中，太阳能电池还包括：第一电极10，第一电极10穿过第一钝化减反层4并与第一掺杂半导体层3电性接触；第二电极20，第二电极20穿过第二钝化减反层6并与第二掺杂半导体层5电性接触。
可选的，第一电极10与第一区域C1在垂直于半导体基底1的厚度方向的方向(平行于第一表面A的方向)上的距离大于或等于300μm。因此，在制备电极的过程中，也可以有效阻挡制备电极所用的浆料泄露分布在电池侧面的更大范围内，对电池的电性能造成严重损害。
可选的，第一掺杂半导体层3为掺杂多晶硅、掺杂非晶硅和掺杂微晶硅中的一种或多种。第一掺杂半导体层3例如为掺杂多晶硅，掺杂多晶硅的厚度通常在80nm～500nm之间，掺杂浓度通常在1*1017～1*1021atoms/cm3。。在一些实施例中，参考图12所示，侧面C还包括与第二区域C2邻近的第三区域C3，第三区域C3相比于第二区域C2更靠近第二表面B。也就是说，上述的太阳能电池还包括：第三半导体基底部13，与第二半导体基底部12一体形成，且第三半导体基底部13相比第二半导体基底部12更靠近第二表面B。
根据本申请的实施例，第三区域C3相比于第二区域C2在远离侧面C的方向上凸起。可选的，第三区域C3的凸起高度d2大于第一区域C1的凸起高度d1。
在一些实施例中，第三区域C3的凸起高度d2为3μm～10μm，例如可以为3μm、5μm、6μm、8μm、10μm，但不限于所举数值。
在一些实施例中，在第二表面B形成第二掺杂半导体层5时，第二掺杂半导体层5会绕镀在侧面C。在使用碱液去除侧面C绕镀的第二掺杂半导体层5时，在侧面C的靠近第二表面B的区域形成第三区域C3，其中第三区域C3相比于第二区域C2在远离侧面C的方向上凸起，一方面可以增大第一表面A和第二表面B的空间电性隔离距离，能够较好地避免太阳能电池侧面上漏电的发生；另一方面可以有效阻挡在第二表面B制备电极所用的浆料泄露至侧面，进而可以避免对电池的性能造成损害。
另外，第三区域C3相比于第二区域C2在远离侧面C的方向上凸起，可以增大半导体基底1和第二掺杂半导体层5形成的PN结的结区面积，有利于提升太阳能电池的光生电流。
关于第二掺杂半导体层5在所述侧面C处的绕镀，本发明提供另一实施方式，如图13所示，第二掺杂半导体层5在侧面C处的绕镀为第五掺杂半导体层51。第五掺杂半导体层51形成在半导体基底1的侧面的局部区域、且与第二掺杂半导体层5一体连续。第五掺杂半导体层51和第二掺杂半导体层5的导电类型相同，且第五掺杂半导体层51沿半导体基底1的厚度方向的最大延伸长度与半导体基底1的厚度之间的比值大于5％、且小于等于50％。半导体基底1的侧面中未对应第五掺杂半导体层51的区域表面上形成有第一塔基状纹理结构16。至少部分第一塔基状纹理结构16的边长大于等于10μm。第一掺杂半导体层3形成在半导体基底1的第一表面一侧。第一掺杂半导体层3和第二掺杂半导体层5的导电类型相反。
采用上述技术方案的情况下，如图13所示，本申请实施例提供的太阳能电池包括导电类型相反、且分别位于半导体基底1相对的第二表面和第一表面一侧的第二掺杂半导体层5和第一掺杂半导体层3。其中，第二掺杂半导体层5和第一掺杂半导体层3中的一者可以与半导体基底1形成PN结，另一者可以与半导体基底1形成高低结，在上述PN结和高低结的内建电场的共同作用下，实现导电类型相反的载流子分流，并且使得相应导电类型的载流子分别朝向第二掺杂半导体层5和第一掺杂半导体层3运动并被其所收集。在实际的制造过程中，在半导体基底1的第二表面一侧制造第二掺杂半导体层5时，会因绕镀在半导体基底1的侧面和至少部分第一表面一侧形成第五掺杂半导体层51。因第五掺杂半导体层51和第一掺杂半导体层3的导电类型相反，故在形成第一掺杂半导体层3之前，还需要去掉第五掺杂半导体层51位于第一表面和侧面的靠近第一表面的区域的部分，以防止第二掺杂半导体层5和第一掺杂半导体层3通过第五掺杂半导体层51短路。在上述情况下，如图13-15所示，本申请实施例提供的太阳能电池中，只需要去除第五掺杂半导体层51位于第一表面和侧面的靠近第一表面的区域的部分，既可以防止短路，还可以利于解决现有技术中为将第五掺杂半导体层51形成在侧面的部分全部去除而导致位于第二表面一侧的第二掺杂半导体层5出现过刻问题，确保第二掺杂半导体层5在第二表面一侧具有较大的形成范围，能够覆盖第二表面中的边缘区域。并且，保留在侧面局部区域的第五掺杂半导体层51的存在利于增大靠近第二表面一侧的结区(PN结或高低结)面积。其次，本申请实施例中保留位于侧面局部区域的第五掺杂半导体层51，还利于提高刻蚀产能，降低清洗液耗量和刻蚀成本。
可选的，如图13-15所示，半导体基底1的侧面中未对应第五掺杂半导体层51的区域表面上形成有第一塔基状纹理结构16。可以理解的是，第一塔基状纹理结构16靠近半导体基底1的一侧呈四边形。基于此，第一塔基状纹理结构16大致为去掉金字塔结构后腐蚀溶液对裸露的半导体基底1的侧面中靠近第一表面的部分按照不同方向腐蚀速率不同的腐蚀方式重新形成的塔基状结构。基于此，与完整的金字塔型结构相比，上述第一塔基状纹理结构16的表面相对平整，表明在去除侧面靠近第一表面的部分上的第五掺杂半导体层51和去除形成第一掺杂半导体层3时绕镀在至少部分侧面上的绕镀掺杂硅层后，侧面靠近第一表面的至少部分区域上没有残留第五掺杂半导体层51和绕镀掺杂硅层，防止短路。其次，可以理解的是，第五掺杂半导体层51沿半导体基底1的厚度方向的最大延伸长度的不同，导致第五掺杂半导体层51与第一掺杂半导体层3之间的抑制漏电的需求不同。具体的，在一定范围内，第五掺杂半导体层51沿半导体基底1的厚度方向的最大延伸长度越大，第五掺杂半导体层51与第一掺杂半导体层3之间的距离越小，相应的二者之间的防漏电要求更高。并且，上述第一塔基状纹理结构16的边长越大，腐蚀溶液对半导体基底1的侧面中未对应第五掺杂半导体层51的部分的刻蚀程度越高。基于此，在保留的第五掺杂半导体层51沿半导体基底1的厚度方向的最大延伸长度与半导体基底1的厚度之间的比值大于5％、且小于等于50％的情况下，至少部分上述第一塔基状纹理结构16的边长大于等于10μm时，可以确保能够通过位于第五掺杂半导体层51与第一掺杂半导体层3之间的间隔区域将第五掺杂半导体层51和第一掺杂半导体层3隔离开，且降低二者之间的漏电风险，利于提高太阳能电池的工作性能。
可选的，上述半导体基底的第二表面可以与太阳能电池的向光面相对应，此时半导体基底的第一表面与太阳能电池的背光面相对应。
示例性的，如图13所示，上述第二表面上可以形成有第三纹理结构17，半导体基底1的侧面对应第五掺杂半导体层51的区域表面上可以形成有第四纹理结构18。在上述情况下，第四纹理结构18的形貌可以与第三纹理结构17的形貌相同，也可以不同。示例性的，第三纹理结构和/或第四纹理结构可以为金字塔型结构等绒面结构，也可以为非金字塔型结构(如孔洞型结构、V型槽结构或塔基型结构等)或抛光结构。
可选的，如图13所示，第四纹理结构18的一维尺寸可以小于第三纹理结构17的一维尺寸。或者，第四纹理结构18的一维尺寸也可以等于或大于第三纹理结构17的一维尺寸。
可选的，如图13所示，第四纹理结构18的一维尺寸小于第三纹理结构17的一维尺寸，半导体基底1的第二表面上形成有一维尺寸相对较大的第三纹理结构17，以利于增大第二表面的比表面积，确保第二表面一侧具有良好的陷光效果，利于使得更多光线经第二表面一侧折射至半导体基底1内并被半导体基底1所利用，提高太阳能电池的光电转换效率。其次，半导体基底1的侧面对应第五掺杂半导体层51的区域表面上形成有一维尺寸相对较小的第四纹理结构18，此时利于降低半导体基底1的侧面对应第五掺杂半导体层51的区域表面的平整度差异，降低复合中心数量。
如图14和图15所示，可选的，第一塔基状纹理结构16靠近半导体基底1的一侧呈四边形。基于此，第一塔基状纹理结构16的边长可以是第一塔基状纹理结构16的底部(靠近半导体基底1的一侧)任一边的长度。
优选的，至少部分第一塔基状纹理结构的边长可以小于等于15μm。例如：至少部分第一塔基状纹理结构的边长可以为10μm、11μm、12μm、13μm、14μm或15μm等。在此情况下，利于在降低第二掺杂半导体层5通过第五掺杂半导体层51与第一掺杂半导体层3之间的漏电风险的同时，防止腐蚀溶液对半导体基底的侧面的未对应第五掺杂半导体层51的裸露在外的部分过度刻蚀，确保半导体基底具有较低的损耗，进而确保半导体基底对折射至自身的光线进行充分吸收，且具有较大的光吸收横截面积，提高太阳能电池对光线的利用率。另外，在太阳能电池还包括上述第一或第二钝化减反层的情况下，当至少部分第一塔基状纹理结构的边长小于等于15μm时，还利于防止因第一塔基状纹理结构的边长过大使得形成在该表面上的第一或第二钝化减反层的厚度较小，确保第一或第二钝化减反层对半导体基底的侧面中未对应第五掺杂半导体层的表面具有良好的钝化效果，降低该表面处的缺陷数量，进一步降低载流子复合速率。
在一些实施方式中，如图13所示，在半导体基底1的侧面局部区域形成有第五掺杂半导体层51，而在半导体基底1的侧面未形成有第一掺杂半导体层3的情况下，第一塔基状纹理结构16形成在半导体基底1的侧面中未对应第五掺杂半导体层的区域表面上。半导体基底1的侧面中未对应第五掺杂半导体层51的区域表面的不同部分上形成的第一塔基状纹理结构16的边长可以大致相同。
可选的，如图12所示，第一塔基状纹理结构形成在在半导体基底1的侧面C中的第二区域C2处；半导体基底1的侧面C中的第一区域C1和/或第一表面处形成有第二塔基状纹理结构，至少部分第一塔基状纹理结构的边长大于第二塔基状纹理结构的边长。在此情况下，利于增大靠近第一表面一侧的结区(PN结或高低结)面积，提高靠近第一表面一侧的内建电场的强度，进一步利于加速载流子的分流与朝向第二掺杂半导体层5和第一掺杂半导体层3的传输速率，提高载流子收集效率。并且，该情况下，在半导体基底1的侧面中，形成在第二区域C2处的至少部分第一塔基状纹理结构的边长大于形成在第一区域C1和/或第一表面处的第二塔基状纹理结构的边长，该方式能够降低半导体基底1的侧面中第五掺杂半导体层51与位于侧面中的第一掺杂半导体层之间的短路风险。
可选的，上述第一塔基状纹理结构的边长可以大于等于10.5μm。在此情况下，第一塔基状纹理结构的边长在上述范围内，可以防止因第一塔基状纹理结构的边长的数值较小而导致第一掺杂半导体层3和第五掺杂半导体层51沿半导体基底的厚度方向的间距较小而导致漏电风险降低程度较低，确保半导体基底的侧面具有较低的载流子复合速率。
可选的，如图16所示，在半导体基底的侧面中，在第二区域(C2)形成有沿第三方向延伸、且沿第四方向排布的多个第一纹理结构组。每个第一纹理结构组包括沿第三方向排布的多个第一塔基状纹理结构16。第三方向不同于第四方向、且第三方向相对于第二表面倾斜设置。在此情况下，不同第一塔基状纹理结构16的排布较为规则，利于提高侧面中第二区域(C2)的表面平整度，利于增大第一或第二钝化减反层在侧面上方的形成厚度，进而提高第一或第二钝化减反层对侧面的钝化效果。其中，第三方向和第四方向可以为平行于侧面的任意两个互不相同的方向，只要第三方向相对于第二表面倾斜设置均可。具体的，在实际的制造过程中，第一纹理结构组的延伸方向(即第三方向)与切削半导体基底时的方向大致平行，沿着与半导体基底的厚度方向倾斜设置的方向进行切削，利于降低切削阻力，降低半导体基底的切削难度。
可选的，在第一表面和/或第一区域C1处形成有第二塔基状纹理结构，至少一个第二塔基状纹理结构的形貌与第一塔基状纹理结构的形貌可以相同，也可以不同。可选的，至少一个第一塔基状纹理结构的边长可以大于第二塔基状纹理结构的边长。第一塔基状纹理结构的边长大于第一表面或第一区域C1处形成的第二塔基状纹理结构的边长，有利于防止短路。
可选的，至少部分第二塔基状纹理结构可以沿靠近半导体基底1的方向凹入、且至少部分第二塔基状纹理结构靠近半导体基底1的一侧呈四边形。
可选的，上述第二塔基状纹理结构的边长可以大于等于5μm、且小于等于13μm。例如：第二塔基状纹理结构的边长可以为5μm、6μm、8μm、8.5μm、9μm、9.5μm、10μm、10.5μm、11μm或13μm等。第二塔基状纹理结构的边长在上述范围内，能够防止因第二塔基状纹理结构的边长较小使得腐蚀液对第一表面一侧的腐蚀时间较短而导致半导体基底的第一表面一侧的金字塔结构未完全去除。另外，还利于防止因第二塔基状纹理结构的边长较大使得第一表面一侧的比表面积较大而导致半导体基底的第一表面一侧被过度刻蚀，确保半导体基底具有较大光吸收深度，确保太阳能电池具有较高的光电转换效率。
可选的，第五掺杂半导体层靠近第一表面的一端具有不平整的特征。当对应第五掺杂半导体层的区域和未对应第五掺杂半导体层的区域之间的边界呈锯齿状或波浪状等曲线型时，边界的侧壁表面积进一步增大，有利于对光的吸收，同时边界的侧壁具有波浪形能够增加光线的多重反射。
可选的，当侧面还包括第一掺杂半导体层3，在半导体基底的侧面中，与第一掺杂半导体层3对应的区域表面和未对应第一掺杂半导体层3的区域之间的边界可以为平整的直线。或者，半导体基底的侧面中，对应第一掺杂半导体层3的区域和未对应第一掺杂半导体层3的区域之间的边界呈锯齿状或波浪形等曲线型。
可选的，上述半导体基底还可以具有连接第二表面和第一表面的倒角面。该倒角面可以为其上未形成有纹理结构的平面。或者，如图17至图19所示，倒角面上可以形成有沿第五方向延伸、且沿第六方向间隔分布的多个第二纹理结构组。第五方向不同于第六方向、且第五方向与半导体基底1的厚度方向大致平行。并且，每个第二纹理结构组包括沿第六方向延伸、且沿第五方向排布的多个簇状纹理结构。倒角面中，位于相邻两个第二纹理结构组之间的区域表面呈沿第五方向排布的凹凸折线形。在此情况下，半导体基底1的倒角面上形成有按照一定规律排布的簇状纹理结构，并且在由不同簇状纹理结构构成的相邻两个第二纹理结构组之间的区域表面呈沿第五方向排布的凹凸折线形时，倒角面具有凹凸不平的表面形貌，利于增大倒角面的比表面积，利于使得倒角面具有良好的陷光效果，进一步提高半导体基底1对光线的利用率。
其中，本申请实施例对簇状纹理结构的尺寸和分布情况、上述第五方向和第六方向的具体指向、以及倒角面中位于相邻两个第二纹理结构组之间的区域表面呈凹凸折线型的起伏程度不做具体限定。示例性的，上述第五方向可以与半导体基底的厚度方向大致平行，第六方向可以与倒角面沿半导体基底的厚度方向的边缘平行。
在一些实施方式中，太阳能电池为具有单面电极的太阳能电池，例如交叉指式背接触电池(Interdigitated Back Contact，IBC)。
图20为本申请实施例提供的背接触太阳能电池的剖面示意图。
图21为本申请实施例提供的背接触太阳能电池的第一表面的俯视示意图。
根据本申请的一种示例性实施例，参考图20、图21所示，本申请提供一种背接触太阳能电池。
根据本申请的实施例，半导体基底1的第一表面A上具有电极收集区，电极收集区包括沿第二方向交替分布的多个少子区100和多个多子区200，相邻的少子区100和多子区200之间具有隔离区300。
根据本申请的实施例，第一掺杂半导体层3包括第三掺杂半导体层31和第四掺杂半导体层32；其中，用于收集并导出少数载流子的第三掺杂半导体层31设置在少子区100；用于收集并导出多数载流子的第四掺杂半导体层32设置在多子区200，其中第三掺杂半导体层31与第四掺杂半导体层32的导电类型相反，第三掺杂半导体层31与第四掺杂半导体层32中的一个为N型，第三掺杂半导体层31与第四掺杂半导体层32中的另一个为P型。例如，第三掺杂半导体层31的导电类型可以为N型，此时第四掺杂半导体层32的导电类型为P型；或者，第三掺杂半导体层31的导电类型可以为P型，此时第四掺杂半导体层32的导电类型为N型。
根据本申请的实施例，参考图20、图21所示，多个第三掺杂半导体层31在平行于第一表面A的第一平面内在第一方向延伸。
根据本申请的实施例，多个第四掺杂半导体层32在第一方向延伸，多个第三掺杂半导体层31与多个第四掺杂半导体层32在第一平面内在与第一方向垂直的第二方向交替间隔分布在第一表面A。
根据本申请的实施例，第三掺杂半导体层31和第四掺杂半导体层32还位于第一区域C1的部分表面上。
根据本申请的实施例，位于半导体基底1最边缘的少子区100上的第一掺杂半导体层31从第一平面垂直延伸到侧面C的第一区域C1的部分表面上；和/或，位于半导体基底1最边缘的多子区200上的第二掺杂半导体层32从第一平面垂直延伸到侧面C的第一区域C1的部分表面上。
根据本申请的实施例，半导体基底1与第三掺杂半导体层31之间还形成有第一界面钝化层。半导体基底1与第四掺杂半导体层32之间还形成有第二界面钝化层。
根据本申请的实施例，第一界面钝化层和/或第二界面钝化层包括氮化硅、氧化硅、氮氧化硅、氧化铝、碳化硅和非晶硅中的一种或多种。
根据本申请的实施例，上述背接触太阳能电池的第一钝化减反层4位于第三掺杂半导体层31和第四掺杂半导体层32的远离半导体基底1的表面、和隔离区300的半导体基底1上。第一钝化减反层4的材料包括氮化硅、氧化硅、氮氧化硅、氧化铝、碳化硅和非晶硅中的一种或多种。第一钝化减反层4用于实现背接触电池的表面钝化和减反射功能。
根据本申请的实施例，上述背接触太阳能电池还包括：第一电极10，第一电极10贯穿第一钝化减反层4并与第三掺杂半导体层31电性接触；第二电极20，第二电极20贯穿第一钝化减反层4并与第四掺杂半导体层32电性接触。
根据本申请的实施例，第一电极10的宽度为5μm～600μm，例如可以为5μm、10μm、100μm、500μm、600μm，但不限于所举数值。
根据本申请的实施例，第二电极20的宽度为5μm～600μm，例如可以为5μm、10μm、100μm、500μm、600μm，但不限于所举数值。
根据本申请的实施例，第一电极10和/或第二电极20的材料包括但不限于金属、金属氧化物、金属氮化物、金属碳化物、金属硫化物中的一种或多种。第一电极10和/或第二电极20还可以为石墨烯等其它导电连接材料。
根据本申请的实施例，在电极制备过程中，使用电极浆料涂覆在第一表面A的第一钝化减反层4上，然后经过烧结，使得电极浆料穿过第一钝化减反层4并与掺杂半导体层形成接触。
根据本申请的一种示例性实施例，本申请提供一种光伏组件，包括上述的太阳能电池。
以上所述的具体实施例，对本申请的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本申请的具体实施例而已，并不用于限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种太阳能电池，其特征在于，包括：
    半导体基底(1)，所述半导体基底(1)具有相对的第一表面(A)和第二表面(B)，以及邻接于所述第一表面(A)和所述第二表面(B)之间的多个侧面(C)；
    钝化接触结构，至少位于所述半导体基底(1)的部分第一表面(A)上，所述钝化接触结构包括依次层叠的界面钝化层(2)和第一掺杂半导体层(3)；
    其中，在所述第一表面(A)指向所述第二表面(B)的方向上，所述侧面(C)包括依次邻近的第一区域(C1)和第二区域(C2)，所述第一区域(C1)相比于所述第二区域(C2)在远离所述侧面(C)的方向上凸起；
    所述第一掺杂半导体层(3)还位于所述第一区域(C1)的表面上，其中位于所述第一区域(C1)上的所述第一掺杂半导体层(3)与位于所述第一表面(A)上的所述第一掺杂半导体层(3)一体连续。
  2. 根据权利要求1所述的太阳能电池，其特征在于，所述第一掺杂半导体层(3)位于所述第一区域(C1)的部分表面上，且邻近所述第二区域(C2)的部分第一区域(C1)的表面未覆盖有所述第一掺杂半导体层(3)。
  3. 根据权利要求2所述的太阳能电池，其特征在于，在所述第一表面(A)指向所述第二表面(B)的方向上，位于所述第一区域(C1)的表面上的所述第一掺杂半导体层(3)与所述第二区域(C2)的间距大于或等于1μm。
  4. 根据权利要求2所述的太阳能电池，其特征在于，
    所述第一区域(C1)在垂直于所述第一表面(A)的方向上的宽度与所述半导体基底(1)的厚度的比例范围为1％～20％。
  5. 根据权利要求1所述的太阳能电池，其特征在于，
    所述第一区域(C1)在垂直于所述第一表面(A)的方向上的宽度为0.5μm～20μm。
  6. 根据权利要求2所述的太阳能电池，其特征在于，在垂直于所述第一表面(A)的方向上，所述第一掺杂半导体层(3)在所述第一区域(C1)的分布宽度小于所述第一区域(C1)的宽度的80％。
  7. 根据权利要求1-6中任一项所述的太阳能电池，其特征在于，
    至少一个所述侧面(C)的第一区域(C1)为自远离所述第一表面(A)的一侧向靠近所述第一表面(A)的一侧沿远离所述侧面(C)方向延伸的斜面。
  8. 根据权利要求1-6中任一项所述的太阳能电池，其特征在于，所述第一区域(C1)包括大致平行于第一表面(A)延伸的棱。
  9. 根据权利要求1-6中任一项所述的太阳能电池，其特征在于，
    所述第一区域(C1)处具有多个孔洞，所述孔洞在平行于所述第一表面(A)的方向上凹陷至所述半导体基底(1)内。
  10. 根据权利要求9所述的太阳能电池，其特征在于，所述孔洞在靠近所述第一表面(A)的区域的分布密度小于在靠近所述第二区域(C2)的区域的分布密度。
  11. 根据权利要求10所述的太阳能电池，其特征在于，
    所述孔洞的径向尺寸在从所述第一区域(C1)处的表面至所述半导体基底(1)的方向上逐渐减小；
    和/或，所述孔洞的径向尺寸小于5μm。
  12. 根据权利要求1-6中任一项所述的太阳能电池，其特征在于，还包括：
    第二掺杂半导体层(5)，至少位于所述半导体基底(1)的第二表面(B)上；以及
    第二钝化减反层(6)，至少位于所述第二掺杂半导体层(5)的远离所述半导体基底(1)的表面上。
  13. 根据权利要求1-6中任一项所述的太阳能电池，其特征在于，所述太阳能电池为背接触太阳能电池，
    所述第一掺杂半导体层(3)包括多个第三掺杂半导体层(31)和多个第四掺杂半导体层(32)，多个所述第三掺杂半导体层(31)与多个所述第四掺杂半导体层(32)交替间隔分布在所述第一表面(A)；
    其中，所述第三掺杂半导体层(31)与所述第四掺杂半导体层(32)中的一个为N型，所述第三掺杂半导体层与所述第四掺杂半导体层中的另一个为P型。
  14. 根据权利要求1-6中任一项所述的太阳能电池，其特征在于，还包括：
    第一钝化减反层(4)，至少位于所述钝化接触结构远离所述半导体基底(1)的表面上；
    第一电极(10)，所述第一电极(10)贯穿所述第一钝化减反层(4)与所述第一掺杂半导体层(3)接触；
    其中，所述第一电极(10)与所述第一区域(C1)在平行于所述第一表面(A)的方向上的距离大于或等于300μm。
  15. 根据权利要求1-6中任一项所述的太阳能电池，其特征在于，所述侧面(C)还包括与所述第二区域(C2)邻近的第三区域(C3)，所述第三区域(C3)相比于所述第二区域(C2)更靠近所述第二表面(B)；
    所述第三区域(C3)相比于所述第二区域(C2)在远离所述侧面(C)的方向上凸起。
  16. 根据权利要求15所述的太阳能电池，其特征在于，所述第三区域(C3)的凸起高度大于所述第一区域(C1)的凸起高度。
  17. 根据权利要求15所述的太阳能电池，其特征在于，所述第二区域(C2)处形成有第一塔基状纹理结构(16)，至少部分所述第一塔基状纹理结构(16)的边长大于等于10μm。
  18. 根据权利要求17所述的太阳能电池，其特征在于，所述第三区域(C3)包括第五掺杂半导体层(51)，所述第五掺杂半导体层(51)与所述第一掺杂半导体层(3)的掺杂类型相反；所述第五掺杂半导体层(51)沿半导体基底(1)的厚度方向的最大延伸长度与半导体基底(1)的厚度之间的比值大于5％、且小于等于50％。
  19. 根据权利要求17所述的太阳能电池，其特征在于，上述第一表面(A)形成有第二塔基状纹理结构；至少部分所述第一塔基状纹理结构(16)的边长大于所述第二塔基状纹理结构的边长。
  20. 一种光伏组件，其特征在于，包括如权利要求1～19中任一项所述的太阳能电池。
PCT/CN2025/080544 2024-05-15 2025-03-04 太阳能电池及光伏组件 Pending WO2025236816A1 (zh)

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