AT508441A3 - Verfahren zum prüfen einer chipkarte durch simulation von angriffen - Google Patents

Verfahren zum prüfen einer chipkarte durch simulation von angriffen Download PDF

Info

Publication number
AT508441A3
AT508441A3 ATA932/2010A AT9322010A AT508441A3 AT 508441 A3 AT508441 A3 AT 508441A3 AT 9322010 A AT9322010 A AT 9322010A AT 508441 A3 AT508441 A3 AT 508441A3
Authority
AT
Austria
Prior art keywords
attack
chip card
simulated
operating system
chip
Prior art date
Application number
ATA932/2010A
Other languages
English (en)
Other versions
AT508441B1 (de
AT508441A2 (de
Original Assignee
Austria Card Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Austria Card Gmbh filed Critical Austria Card Gmbh
Publication of AT508441A2 publication Critical patent/AT508441A2/de
Publication of AT508441A3 publication Critical patent/AT508441A3/de
Application granted granted Critical
Publication of AT508441B1 publication Critical patent/AT508441B1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/3604—Analysis of software for verifying properties of programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Debugging And Monitoring (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Storage Device Security (AREA)

Abstract

Verfahren zum Prüfen einer Chipkarte mit Angriffen auf das Betriebssystem oder die Applikationen bei der Herstellung der Chipkarte, wobei ein hardwaremäßiger Angriff auf die Chipkarte dadurch simuliert wird, dass stattdessen mit einer Angriffssoftware (18) in den Programmablauf des Betriebssystems oder der Applikationen über die Schnittstelle (16) eingegriffen wird und gezielt bestimmte Daten entsprechend einem hardwaremäßigen Angriff verändert werden, wobei Betriebssystem oder die Applikationen auf einem durch einen Chip-Simulator (17) simulierten Chip (15) ausgeführt werden, und wobei durch Variation der Anzahl von veränderten Speicher-Bits bzw. Bytes und der geschriebenen Werte unterschiedliche Angriffsparameter, wie insbesondere Fokussierung, Energie, Wellenlänge der eingestrahlten elektromagnetischen Wellen, Angriff durch direkte Kontaktierung mit Micro-Probes, Angriff durch ionisierende Strahlung, simuliert werden.
ATA932/2010A 2009-06-13 2010-06-08 Verfahren zum prüfen einer chipkarte durch simulation von angriffen AT508441B1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE200910024768 DE102009024768A1 (de) 2009-06-13 2009-06-13 Verfahren zum Prüfen einer Chipkarte durch Simulation von Angriffen

Publications (3)

Publication Number Publication Date
AT508441A2 AT508441A2 (de) 2011-01-15
AT508441A3 true AT508441A3 (de) 2016-01-15
AT508441B1 AT508441B1 (de) 2016-02-15

Family

ID=43122912

Family Applications (1)

Application Number Title Priority Date Filing Date
ATA932/2010A AT508441B1 (de) 2009-06-13 2010-06-08 Verfahren zum prüfen einer chipkarte durch simulation von angriffen

Country Status (2)

Country Link
AT (1) AT508441B1 (de)
DE (1) DE102009024768A1 (de)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5671352A (en) * 1995-07-07 1997-09-23 Sun Microsystems, Inc. Error injection to a behavioral model
US6195765B1 (en) * 1998-01-05 2001-02-27 Electronic Data Systems Corporation System and method for testing an application program
EP1505399A2 (de) * 2003-06-24 2005-02-09 Giesecke & Devrient GmbH Verfahren zum Erzeugen von Testdaten zum Austesten der Funktionsfähigkeit einer datenverarbeitenden Schaltung
US20060271822A1 (en) * 2005-05-26 2006-11-30 Cisco Technology, Inc. Method and system for quantifying the quality of diagnostic software
CN101131670A (zh) * 2006-08-25 2008-02-27 上海华虹集成电路有限责任公司 双界面智能卡仿真系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5671352A (en) * 1995-07-07 1997-09-23 Sun Microsystems, Inc. Error injection to a behavioral model
US6195765B1 (en) * 1998-01-05 2001-02-27 Electronic Data Systems Corporation System and method for testing an application program
EP1505399A2 (de) * 2003-06-24 2005-02-09 Giesecke & Devrient GmbH Verfahren zum Erzeugen von Testdaten zum Austesten der Funktionsfähigkeit einer datenverarbeitenden Schaltung
US20060271822A1 (en) * 2005-05-26 2006-11-30 Cisco Technology, Inc. Method and system for quantifying the quality of diagnostic software
CN101131670A (zh) * 2006-08-25 2008-02-27 上海华虹集成电路有限责任公司 双界面智能卡仿真系统

Also Published As

Publication number Publication date
AT508441B1 (de) 2016-02-15
AT508441A2 (de) 2011-01-15
DE102009024768A1 (de) 2010-12-23

Similar Documents

Publication Publication Date Title
Zhou et al. Phase field modeling of quasi-static and dynamic crack propagation: COMSOL implementation and case studies
Liu et al. Micro-cracking behavior of shale matrix during thermal recovery: Insights from phase-field modeling
WO2009056992A3 (en) Reservoir fracture simulation
ZA201900512B (en) Blockchain-implemented method and system
AR106027A1 (es) Simulación de yacimientos fracturados utilizando múltiples mallas
RU2013157623A (ru) Мультисегментные трещины
SA523450323B1 (ar) نمذجة الآبار المتصدعة
Yazdi et al. A framework for capturing, statistically modeling and analyzing the evolution of software models
AT508441A3 (de) Verfahren zum prüfen einer chipkarte durch simulation von angriffen
Aleem et al. A class of modified weighted Weibull distribution and its properties
WO2008102433A1 (ja) Ｌｓｉ試験装置、ｌｓｉ試験方法、ｌｓｉ試験プログラムおよび記録媒体
CN106407554B (zh) 一种同时支持主从机功能的lpc总线仿真验证方法和装置
Xu et al. Efficient simulation of Greeks of multiasset European and Asian style options by Malliavin calculus and quasi-Monte Carlo methods
Sepehrnoori et al. Basic EDFM approach using Cartesian grid
Radziszewska et al. Modeling of power consumption in a small microgrids
DI LUZIO et al. Numerical simulation of self-healing process and its application
Scazzosi et al. Rural Landscape as Heritage: Cultural Approaches towards a World Rural Landscape Recommendation
Benato Investigation Into Fracture Network Permeability Evolution And Geothermal Reservoir Deformation In Response To Hydraulic Stimulation, Utilizing Coupled Thermo-Hydro-Mechanical Modeling
Ionescu Romanian labor resources under the new Europe 2020 strategy
Lippe Simulating the impact of land use change on ecosystem functions in data-limited watersheds of Mountainous Mainland Southeast Asia
French The Impact of Squall Line-generated environmental perturbations on isolated convective storms
Wicaksono et al. Water, Energy, and Food Nexus: Inter-basin Resource Trading Model
Allee Mobilizing for Action through Planning and Partnerships (MAPP): An approach to resilience
Orzech et al. Modeling small-scale physics of waves and ice in the MIZ
Oosthuizen et al. System dynamics analysis of factors impacting on command and control technology acceptance for anti-poaching operations

Legal Events

Date Code Title Description
MM01 Lapse because of not paying annual fees

Effective date: 20230608