AT512066A3 - Steuervorrichtung und Verfahren zur Steuerung einer Bewegung eines Elementes einer Anlage - Google Patents

Steuervorrichtung und Verfahren zur Steuerung einer Bewegung eines Elementes einer Anlage Download PDF

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Publication number
AT512066A3
AT512066A3 ATA1129/2012A AT11292012A AT512066A3 AT 512066 A3 AT512066 A3 AT 512066A3 AT 11292012 A AT11292012 A AT 11292012A AT 512066 A3 AT512066 A3 AT 512066A3
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AT
Austria
Prior art keywords
processor
auxiliary processor
auxiliary
input signal
controlling
Prior art date
Application number
ATA1129/2012A
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English (en)
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AT512066B1 (de
AT512066A2 (de
Inventor
Frank Hielscher
Gunther May
Original Assignee
Bosch Gmbh Robert
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bosch Gmbh Robert filed Critical Bosch Gmbh Robert
Publication of AT512066A2 publication Critical patent/AT512066A2/de
Publication of AT512066A3 publication Critical patent/AT512066A3/de
Application granted granted Critical
Publication of AT512066B1 publication Critical patent/AT512066B1/de

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Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Program-control systems
    • G05B19/02Program-control systems electric
    • G05B19/04Program control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/045Program control other than numerical control, i.e. in sequence controllers or logic controllers using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5044Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering hardware capabilities
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B25HAND TOOLS; PORTABLE POWER-DRIVEN TOOLS; MANIPULATORS
    • B25JMANIPULATORS; CHAMBERS PROVIDED WITH MANIPULATION DEVICES
    • B25J9/00Program-controlled manipulators
    • B25J9/16Program controls
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Program-control systems
    • G05B19/02Program-control systems electric
    • G05B19/04Program control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042Program control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Program-control systems
    • G05B19/02Program-control systems electric
    • G05B19/04Program control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/20Pc systems
    • G05B2219/25Pc structure of the system
    • G05B2219/25144Between microcomputers, processors
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00Indexing scheme relating to G06F9/00
    • G06F2209/50Indexing scheme relating to G06F9/50
    • G06F2209/509Offload

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Computer Hardware Design (AREA)
  • Robotics (AREA)
  • Mechanical Engineering (AREA)
  • Programmable Controllers (AREA)
  • Image Processing (AREA)

Abstract

Die vorliegende Erfindung betrifft eine Steuervorrichtung (1 00) zur Steuerung einer Bewegung eines Elementes (175) einer Anlage (177), wobei die Steuervorrichtung (100) einen Hauptprozessor (120) und einen Hilfsprozessor (140) aufweist, wobei der Hilfsprozessor (140) mit den Hauptprozessor (120) verbunden ist und eine Rechnerarchitektur aufweist, die sich von einer Rechnerarchitektur des Hauptprozessors (120) unterscheidet, insbesondere wobei die Rechnerarchitektur des Hilfsprozessors (140) eine schnellere Verarbeitung von vorbestimmten Signalen ermöglicht, als die Rechnerarchitektur des Hauptprozessors (120). Der Hilfsprozessor (140) ist ausgebildet, um ein Hilfsprozessoreingangssignal (150) von dem Hauptprozessor (120) einzulesen und unter Verwendung des Hilfsprozessoreingangssignals (150) ein Hilfsprozessorausgangssignal (160) zu ermitteln und an den Hauptprozessor (120) auszugeben. Der Hauptprozessor (120) ist ausgebildet, um ein Eingangssignal (130) einzulesen, unter Verwendung des Eingangssignals (130) das Hilfsprozessoreingangssignal (150) zu ermitteln und an den Hilfsprozessor (140) zu übermitteln, das von dem Hilfsprozessor (140) ermittelte Hilfsprozessorausgangssignal (160) einzulesen und unter Verwendung des Hilfsprozessorausgangssignal (160) ein Steuersignal (170) zur Steuerung der Bewegung des Elementes (175) der Anlage (177) zu ermitteln.
ATA1129/2012A 2011-10-20 2012-10-18 Steuervorrichtung und Verfahren zur Steuerung einer Bewegung eines Elementes einer Anlage AT512066B1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102011116442A DE102011116442A1 (de) 2011-10-20 2011-10-20 Steuervorrichtung und Verfahren zur Steuerung einer Bewegung eines Elements einer Anlage

Publications (3)

Publication Number Publication Date
AT512066A2 AT512066A2 (de) 2013-05-15
AT512066A3 true AT512066A3 (de) 2015-10-15
AT512066B1 AT512066B1 (de) 2016-01-15

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ATA1129/2012A AT512066B1 (de) 2011-10-20 2012-10-18 Steuervorrichtung und Verfahren zur Steuerung einer Bewegung eines Elementes einer Anlage

Country Status (3)

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US (1) US20130103168A1 (de)
AT (1) AT512066B1 (de)
DE (1) DE102011116442A1 (de)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6411863B1 (en) * 1998-11-02 2002-06-25 The Minster Machine Company Auxiliary control system for use with programmable logic controller in a press machine
US20030097187A1 (en) * 1997-12-17 2003-05-22 Huppenthal Jon M. Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
US20060190942A1 (en) * 2004-02-20 2006-08-24 Sony Computer Entertainment Inc. Processor task migration over a network in a multi-processor system
US7613902B1 (en) * 2005-09-22 2009-11-03 Lockheed Martin Corporation Device and method for enabling efficient and flexible reconfigurable computing
US20120144160A1 (en) * 2010-12-07 2012-06-07 King Fahd University Of Petroleum And Minerals Multiple-cycle programmable processor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030097187A1 (en) * 1997-12-17 2003-05-22 Huppenthal Jon M. Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
US6411863B1 (en) * 1998-11-02 2002-06-25 The Minster Machine Company Auxiliary control system for use with programmable logic controller in a press machine
US20060190942A1 (en) * 2004-02-20 2006-08-24 Sony Computer Entertainment Inc. Processor task migration over a network in a multi-processor system
US7613902B1 (en) * 2005-09-22 2009-11-03 Lockheed Martin Corporation Device and method for enabling efficient and flexible reconfigurable computing
US20120144160A1 (en) * 2010-12-07 2012-06-07 King Fahd University Of Petroleum And Minerals Multiple-cycle programmable processor

Also Published As

Publication number Publication date
DE102011116442A1 (de) 2013-04-25
AT512066B1 (de) 2016-01-15
AT512066A2 (de) 2013-05-15
US20130103168A1 (en) 2013-04-25

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