ATA66693A - DEVICE FOR A DIGITAL SIGNAL PROCESSOR BOARD FOR ADAPTING A FAST PROCESSOR TO SLOW COMPONENTS - Google Patents

DEVICE FOR A DIGITAL SIGNAL PROCESSOR BOARD FOR ADAPTING A FAST PROCESSOR TO SLOW COMPONENTS

Info

Publication number
ATA66693A
ATA66693A AT66693A AT66693A ATA66693A AT A66693 A ATA66693 A AT A66693A AT 66693 A AT66693 A AT 66693A AT 66693 A AT66693 A AT 66693A AT A66693 A ATA66693 A AT A66693A
Authority
AT
Austria
Prior art keywords
adapting
digital signal
signal processor
fast
slow components
Prior art date
Application number
AT66693A
Other languages
German (de)
Other versions
AT401117B (en
Inventor
Ronald Dipl Ing Hasenberger
Original Assignee
Elin Energieanwendung
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elin Energieanwendung filed Critical Elin Energieanwendung
Priority to AT66693A priority Critical patent/AT401117B/en
Priority to EP94912986A priority patent/EP0692118A1/en
Priority to PCT/AT1994/000035 priority patent/WO1994023373A1/en
Publication of ATA66693A publication Critical patent/ATA66693A/en
Application granted granted Critical
Publication of AT401117B publication Critical patent/AT401117B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Bus Control (AREA)
AT66693A 1993-04-01 1993-04-01 DEVICE FOR A DIGITAL SIGNAL PROCESSOR BOARD FOR ADAPTING A FAST PROCESSOR TO SLOW COMPONENTS AT401117B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AT66693A AT401117B (en) 1993-04-01 1993-04-01 DEVICE FOR A DIGITAL SIGNAL PROCESSOR BOARD FOR ADAPTING A FAST PROCESSOR TO SLOW COMPONENTS
EP94912986A EP0692118A1 (en) 1993-04-01 1994-03-31 Device for a digital signal processor backplane for matching a fast processor to slow components
PCT/AT1994/000035 WO1994023373A1 (en) 1993-04-01 1994-03-31 Device for a digital signal processor backplane for matching a fast processor to slow components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AT66693A AT401117B (en) 1993-04-01 1993-04-01 DEVICE FOR A DIGITAL SIGNAL PROCESSOR BOARD FOR ADAPTING A FAST PROCESSOR TO SLOW COMPONENTS

Publications (2)

Publication Number Publication Date
ATA66693A true ATA66693A (en) 1995-10-15
AT401117B AT401117B (en) 1996-06-25

Family

ID=3496614

Family Applications (1)

Application Number Title Priority Date Filing Date
AT66693A AT401117B (en) 1993-04-01 1993-04-01 DEVICE FOR A DIGITAL SIGNAL PROCESSOR BOARD FOR ADAPTING A FAST PROCESSOR TO SLOW COMPONENTS

Country Status (3)

Country Link
EP (1) EP0692118A1 (en)
AT (1) AT401117B (en)
WO (1) WO1994023373A1 (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3753232A (en) * 1972-04-06 1973-08-14 Honeywell Inf Systems Memory control system adaptive to different access and cycle times
SE421151B (en) * 1979-01-02 1981-11-30 Ibm Svenska Ab COMMUNICATION CONTROL IN A DATA PROCESSING SYSTEM
US4476527A (en) * 1981-12-10 1984-10-09 Data General Corporation Synchronous data bus with automatically variable data rate
DE3735828C2 (en) * 1986-10-24 1994-11-10 Hitachi Ltd Method for resuming instruction execution after an interruption in a microprocessor-controlled data processing device
CA2007737C (en) * 1989-02-24 1998-04-28 Paul Samuel Gallo Data transfer operations between two asynchronous buses
US5058054A (en) * 1990-02-06 1991-10-15 Analogic Corporation Data transmission device for interfacing between a first rate data acquisition system and a second rate data processing system

Also Published As

Publication number Publication date
EP0692118A1 (en) 1996-01-17
AT401117B (en) 1996-06-25
WO1994023373A1 (en) 1994-10-13

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Legal Events

Date Code Title Description
ELJ Ceased due to non-payment of the annual fee