ATA75499A - Halbleiter-simulationsverfahren - Google Patents

Halbleiter-simulationsverfahren

Info

Publication number
ATA75499A
ATA75499A AT0075499A AT75499A ATA75499A AT A75499 A ATA75499 A AT A75499A AT 0075499 A AT0075499 A AT 0075499A AT 75499 A AT75499 A AT 75499A AT A75499 A ATA75499 A AT A75499A
Authority
AT
Austria
Prior art keywords
simulation process
semiconductor simulation
semiconductor
simulation
Prior art date
Application number
AT0075499A
Other languages
English (en)
Inventor
Shimizu Shunkichi
Mukai Mikio
Komatsu Yasutoshi
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP11797298A external-priority patent/JPH11312722A/ja
Priority claimed from JP16084398A external-priority patent/JPH11353346A/ja
Application filed by Sony Corp filed Critical Sony Corp
Publication of ATA75499A publication Critical patent/ATA75499A/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G06F30/23—Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
AT0075499A 1998-04-28 1999-04-28 Halbleiter-simulationsverfahren ATA75499A (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11797298A JPH11312722A (ja) 1998-04-28 1998-04-28 半導体シミュレーション方法
JP16084398A JPH11353346A (ja) 1998-06-09 1998-06-09 半導体素子のシミュレーション方法

Publications (1)

Publication Number Publication Date
ATA75499A true ATA75499A (de) 2005-12-15

Family

ID=26455995

Family Applications (1)

Application Number Title Priority Date Filing Date
AT0075499A ATA75499A (de) 1998-04-28 1999-04-28 Halbleiter-simulationsverfahren

Country Status (3)

Country Link
US (1) US6327555B1 (de)
KR (1) KR19990083575A (de)
AT (1) ATA75499A (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6514778B2 (en) * 2001-01-31 2003-02-04 United Microelectronics Corp. Method for measuring effective gate channel length during C-V method
JP4991062B2 (ja) * 2001-05-29 2012-08-01 ラピスセミコンダクタ株式会社 半導体プロセスデバイスモデリング方法
US7712056B2 (en) 2002-06-07 2010-05-04 Cadence Design Systems, Inc. Characterization and verification for integrated circuit designs
US7363099B2 (en) * 2002-06-07 2008-04-22 Cadence Design Systems, Inc. Integrated circuit metrology
AU2003274370A1 (en) * 2002-06-07 2003-12-22 Praesagus, Inc. Characterization adn reduction of variation for integrated circuits
US7853904B2 (en) * 2002-06-07 2010-12-14 Cadence Design Systems, Inc. Method and system for handling process related variations for integrated circuits based upon reflections
DE10303682B4 (de) 2003-01-30 2008-01-31 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Bewerten lateraler Dotier- und/oder Ladungsträgerprofile
KR100945512B1 (ko) * 2003-02-26 2010-03-09 삼성전자주식회사 손실 계수의 오차 보정을 이용한 게이트 커패시턴스 측정방법
US7394554B2 (en) * 2003-09-15 2008-07-01 Timbre Technologies, Inc. Selecting a hypothetical profile to use in optical metrology
JP2005093802A (ja) * 2003-09-18 2005-04-07 Oki Electric Ind Co Ltd Ｅｓｄ保護素子のモデル化方法，ｅｓｄシミュレーション方法
US7599051B1 (en) * 2006-11-21 2009-10-06 Kla-Tencor Technologies Corporation Calibration of a substrate inspection tool
US8359562B2 (en) * 2011-01-11 2013-01-22 Infineon Technologies Ag System and method for semiconductor device fabrication using modeling
KR102648616B1 (ko) * 2022-08-27 2024-03-18 광주과학기술원 반도체 소자 시뮬레이션을 위한 초기해 생성 방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2910611B2 (ja) * 1995-03-30 1999-06-23 日本電気株式会社 形状シミュレーション方法
JP2716009B2 (ja) * 1995-07-28 1998-02-18 日本電気株式会社 欠陥分布シミュレーション方法
US5719796A (en) * 1995-12-04 1998-02-17 Advanced Micro Devices, Inc. System for monitoring and analyzing manufacturing processes using statistical simulation with single step feedback
JP3592826B2 (ja) * 1996-03-05 2004-11-24 株式会社東芝 膜形状予測方法
JP2996194B2 (ja) * 1997-01-29 1999-12-27 日本電気株式会社 スパッタ形状シミュレーション方法
US5886909A (en) * 1997-12-19 1999-03-23 Advanced Micro Devices, Inc. Defect diagnosis using simulation for IC yield improvement

Also Published As

Publication number Publication date
US6327555B1 (en) 2001-12-04
KR19990083575A (ko) 1999-11-25

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Legal Events

Date Code Title Description
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