ATE105955T1 - Datenübertragungssystem und - verfahren. - Google Patents

Datenübertragungssystem und - verfahren.

Info

Publication number
ATE105955T1
ATE105955T1 AT88302646T AT88302646T ATE105955T1 AT E105955 T1 ATE105955 T1 AT E105955T1 AT 88302646 T AT88302646 T AT 88302646T AT 88302646 T AT88302646 T AT 88302646T AT E105955 T1 ATE105955 T1 AT E105955T1
Authority
AT
Austria
Prior art keywords
data
communications controller
serial communications
control
incoming
Prior art date
Application number
AT88302646T
Other languages
English (en)
Inventor
Stewart F Bryant
Michael J Harwood
Original Assignee
Digital Equipment Int
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Int filed Critical Digital Equipment Int
Application granted granted Critical
Publication of ATE105955T1 publication Critical patent/ATE105955T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
  • Measuring Pulse, Heart Rate, Blood Pressure Or Blood Flow (AREA)
  • Circuits Of Receivers In General (AREA)
  • Computer And Data Communications (AREA)
  • Bus Control (AREA)
AT88302646T 1987-04-01 1988-03-25 Datenübertragungssystem und - verfahren. ATE105955T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8707778A GB2203616B (en) 1987-04-01 1987-04-01 Improvements in or relating to data communication systems

Publications (1)

Publication Number Publication Date
ATE105955T1 true ATE105955T1 (de) 1994-06-15

Family

ID=10615043

Family Applications (1)

Application Number Title Priority Date Filing Date
AT88302646T ATE105955T1 (de) 1987-04-01 1988-03-25 Datenübertragungssystem und - verfahren.

Country Status (7)

Country Link
EP (1) EP0285335B1 (de)
JP (1) JPH0624395B2 (de)
AT (1) ATE105955T1 (de)
AU (1) AU609791B2 (de)
CA (1) CA1307347C (de)
DE (1) DE3889580T2 (de)
GB (1) GB2203616B (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6067408A (en) * 1993-05-27 2000-05-23 Advanced Micro Devices, Inc. Full duplex buffer management and apparatus
JP3191701B2 (ja) * 1996-10-29 2001-07-23 日本電気株式会社 伝送フレームフォーマット変換回路
US6782486B1 (en) 2000-08-11 2004-08-24 Advanced Micro Devices, Inc. Apparatus for stopping and starting a clock in a clock forwarded I/O system depending on the presence of valid data in a receive buffer

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5630347A (en) * 1979-08-20 1981-03-26 Nippon Telegr & Teleph Corp <Ntt> Single-speed digital subscriber's line transmission system
US4344132A (en) * 1979-12-14 1982-08-10 International Business Machines Corporation Serial storage interface apparatus for coupling a serial storage mechanism to a data processor input/output bus
JPS5766515A (en) * 1980-10-13 1982-04-22 Victor Co Of Japan Ltd Memory address control system
JPS5848551A (ja) * 1981-09-18 1983-03-22 Nippon Telegr & Teleph Corp <Ntt> デ−タ通信制御装置
IT1155575B (it) * 1982-07-27 1987-01-28 Cselt Centro Studi Lab Telecom Interfaccia multipla di comunicazione tra elaboratore di processo e mezzo trasmissivo numerico
US4649384A (en) * 1983-10-07 1987-03-10 Dialogic Systems Corp. Method and apparatus for fault tolerant serial communication of digital information
US4860244A (en) * 1983-11-07 1989-08-22 Digital Equipment Corporation Buffer system for input/output portion of digital data processing system
DE3424587A1 (de) * 1984-07-04 1986-01-09 Standard Elektrik Lorenz Ag, 7000 Stuttgart Schaltungsanordnung zur steuerung der bidirektionalen datenuebertragung zwischen einer rechnereinheit und ueber ein-/ausgabeeinheiten angeschlossenen uebertragungsleitungen
US4852127A (en) * 1985-03-22 1989-07-25 American Telephone And Telegraph Company, At&T Bell Laboratories Universal protocol data receiver

Also Published As

Publication number Publication date
JPS6427345A (en) 1989-01-30
EP0285335A3 (en) 1990-04-25
GB8707778D0 (en) 1987-05-07
EP0285335A2 (de) 1988-10-05
DE3889580T2 (de) 1994-12-22
EP0285335B1 (de) 1994-05-18
AU609791B2 (en) 1991-05-09
DE3889580D1 (de) 1994-06-23
GB2203616B (en) 1991-10-02
JPH0624395B2 (ja) 1994-03-30
AU1386388A (en) 1988-10-06
GB2203616A (en) 1988-10-19
CA1307347C (en) 1992-09-08

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties