ATE125067T1 - Selektive technik zur bestimmung einer unebenheit zur verwendung beim herstellen eines transistors mit schwebendem gate. - Google Patents

Selektive technik zur bestimmung einer unebenheit zur verwendung beim herstellen eines transistors mit schwebendem gate.

Info

Publication number
ATE125067T1
ATE125067T1 AT89203090T AT89203090T ATE125067T1 AT E125067 T1 ATE125067 T1 AT E125067T1 AT 89203090 T AT89203090 T AT 89203090T AT 89203090 T AT89203090 T AT 89203090T AT E125067 T1 ATE125067 T1 AT E125067T1
Authority
AT
Austria
Prior art keywords
layer
asperity
remainder
blanket
insulating layer
Prior art date
Application number
AT89203090T
Other languages
English (en)
Inventor
Teh-Yi James Chen
Original Assignee
Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics Nv filed Critical Philips Electronics Nv
Application granted granted Critical
Publication of ATE125067T1 publication Critical patent/ATE125067T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/964—Roughened surface

Landscapes

  • Non-Volatile Memory (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
  • Semiconductor Memories (AREA)
  • Bipolar Transistors (AREA)
AT89203090T 1988-12-12 1989-12-06 Selektive technik zur bestimmung einer unebenheit zur verwendung beim herstellen eines transistors mit schwebendem gate. ATE125067T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/283,340 US5008212A (en) 1988-12-12 1988-12-12 Selective asperity definition technique suitable for use in fabricating floating-gate transistor

Publications (1)

Publication Number Publication Date
ATE125067T1 true ATE125067T1 (de) 1995-07-15

Family

ID=23085571

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89203090T ATE125067T1 (de) 1988-12-12 1989-12-06 Selektive technik zur bestimmung einer unebenheit zur verwendung beim herstellen eines transistors mit schwebendem gate.

Country Status (6)

Country Link
US (1) US5008212A (de)
EP (1) EP0373698B1 (de)
JP (1) JP2942576B2 (de)
KR (1) KR0147293B1 (de)
AT (1) ATE125067T1 (de)
DE (1) DE68923436T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2598328B2 (ja) * 1989-10-17 1997-04-09 三菱電機株式会社 半導体装置およびその製造方法
US5057447A (en) * 1990-07-09 1991-10-15 Texas Instruments Incorporated Silicide/metal floating gate process
US5289026A (en) * 1991-08-14 1994-02-22 Intel Corporation Asymmetric floating gate overlap for improved device characteristics in buried bit-line devices
US5156987A (en) * 1991-12-18 1992-10-20 Micron Technology, Inc. High performance thin film transistor (TFT) by solid phase epitaxial regrowth
JP3272517B2 (ja) * 1993-12-01 2002-04-08 三菱電機株式会社 半導体装置の製造方法
KR0142601B1 (ko) * 1995-02-28 1998-07-01 김주용 플래쉬 이이피롬 셀의 제조방법
KR0142603B1 (ko) * 1995-03-14 1998-07-01 김주용 플래쉬 이이피롬 셀 및 그 제조방법
US6063665A (en) * 1997-12-08 2000-05-16 Advanced Micro Devices, Inc. Method for silicon surface control for shallow junction formation
US6335292B1 (en) 1999-04-15 2002-01-01 Micron Technology, Inc. Method of controlling striations and CD loss in contact oxide etch
US6165845A (en) * 1999-04-26 2000-12-26 Taiwan Semiconductor Manufacturing Company Method to fabricate poly tip in split-gate flash
US6204159B1 (en) * 1999-07-09 2001-03-20 Advanced Micro Devices, Inc. Method of forming select gate to improve reliability and performance for NAND type flash memory devices
DE10148491B4 (de) 2001-10-01 2006-09-07 Infineon Technologies Ag Verfahren zum Herstellen einer integrierten Halbleiteranordnung mit Hilfe einer thermischen Oxidation und Halbleiteranordnung
US6888755B2 (en) 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element
FR2871940B1 (fr) * 2004-06-18 2007-06-15 St Microelectronics Rousset Transistor mos a grille flottante, a double grille de controle
US7951669B2 (en) 2006-04-13 2011-05-31 Sandisk Corporation Methods of making flash memory cell arrays having dual control gates per memory cell charge storage element
KR102142155B1 (ko) * 2014-03-21 2020-08-10 에스케이하이닉스 주식회사 단일층 플로팅 게이트 비휘발성 메모리 소자 및 제조 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4119995A (en) * 1976-08-23 1978-10-10 Intel Corporation Electrically programmable and electrically erasable MOS memory cell
JPS56116670A (en) * 1980-02-20 1981-09-12 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
US4566175A (en) * 1982-08-30 1986-01-28 Texas Instruments Incorporated Method of making insulated gate field effect transistor with a lightly doped drain using oxide sidewall spacer and double implantations
US4757360A (en) * 1983-07-06 1988-07-12 Rca Corporation Floating gate memory device with facing asperities on floating and control gates
US4752912A (en) * 1985-05-14 1988-06-21 Xicor, Inc. Nonvolatile electrically alterable memory and method
US4763299A (en) * 1985-10-15 1988-08-09 Emanuel Hazani E2 PROM cell and architecture
EP0253014B1 (de) * 1986-07-18 1990-04-11 Nippondenso Co., Ltd. Verfahren zur Herstellung einer nichtflüchtigen Halbleiterspeicheranordnung mit Möglichkeit zum Einschreiben und Löschen
US4806202A (en) * 1987-10-05 1989-02-21 Intel Corporation Field enhanced tunnel oxide on treated substrates
US4853895A (en) * 1987-11-30 1989-08-01 Texas Instruments Incorporated EEPROM including programming electrode extending through the control gate electrode

Also Published As

Publication number Publication date
JP2942576B2 (ja) 1999-08-30
DE68923436T2 (de) 1996-03-21
KR900010955A (ko) 1990-07-11
US5008212A (en) 1991-04-16
EP0373698B1 (de) 1995-07-12
EP0373698A3 (de) 1991-09-25
DE68923436D1 (de) 1995-08-17
KR0147293B1 (ko) 1998-11-02
EP0373698A2 (de) 1990-06-20
JPH02246164A (ja) 1990-10-01

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