ATE145072T1 - Lese-ändern-schreiben funktion - Google Patents

Lese-ändern-schreiben funktion

Info

Publication number
ATE145072T1
ATE145072T1 AT89306718T AT89306718T ATE145072T1 AT E145072 T1 ATE145072 T1 AT E145072T1 AT 89306718 T AT89306718 T AT 89306718T AT 89306718 T AT89306718 T AT 89306718T AT E145072 T1 ATE145072 T1 AT E145072T1
Authority
AT
Austria
Prior art keywords
data
read
change
write function
output buffer
Prior art date
Application number
AT89306718T
Other languages
English (en)
Inventor
Paul M Goodwin
Kumar Chinnaswamy
John J Lynch
Michael A Gagliardo
James E Tessari
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE145072T1 publication Critical patent/ATE145072T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/1056—Updating check bits on partial write, i.e. read/modify/write

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Hall/Mr Elements (AREA)
AT89306718T 1989-01-27 1989-07-03 Lese-ändern-schreiben funktion ATE145072T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/303,621 US5008886A (en) 1989-01-27 1989-01-27 Read-modify-write operation

Publications (1)

Publication Number Publication Date
ATE145072T1 true ATE145072T1 (de) 1996-11-15

Family

ID=23172940

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89306718T ATE145072T1 (de) 1989-01-27 1989-07-03 Lese-ändern-schreiben funktion

Country Status (6)

Country Link
US (1) US5008886A (de)
EP (1) EP0379768B1 (de)
JP (1) JP2958368B2 (de)
AT (1) ATE145072T1 (de)
CA (1) CA1319998C (de)
DE (1) DE68927434T2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5235693A (en) * 1989-01-27 1993-08-10 Digital Equipment Corporation Method and apparatus for reducing buffer storage in a read-modify-write operation
US5412671A (en) * 1990-12-03 1995-05-02 Unisys Corporation Data protection and error correction, particularly for general register sets
US5270970A (en) * 1991-03-15 1993-12-14 Motorola, Inc. Memory device having a buffer for gating data transmissions
US5327570A (en) * 1991-07-22 1994-07-05 International Business Machines Corporation Multiprocessor system having local write cache within each data processor node
US5528610A (en) * 1992-04-30 1996-06-18 Hughes Aircraft Company Boundary test cell with self masking capability
US5638432A (en) * 1992-06-23 1997-06-10 Siemens Aktiengesellschaft Method of setting up telecommunication connections
US5430742A (en) * 1992-10-14 1995-07-04 Ast Research, Inc. Memory controller with ECC and data streaming control
US6125406A (en) * 1998-05-15 2000-09-26 Xerox Corporation Bi-directional packing data device enabling forward/reverse bit sequences with two output latches
US7051264B2 (en) * 2001-11-14 2006-05-23 Monolithic System Technology, Inc. Error correcting memory and method of operating same
US6718444B1 (en) 2001-12-20 2004-04-06 Advanced Micro Devices, Inc. Read-modify-write for partial writes in a memory controller
KR100521372B1 (ko) * 2003-01-24 2005-10-12 삼성전자주식회사 통합 디큐 모드 테스트시 에스디알 또는 디디알 모드로테스트 가능한 반도체 메모리 장치
US7099997B2 (en) * 2003-02-27 2006-08-29 International Business Machines Corporation Read-modify-write avoidance using a boundary word storage mechanism
US20060036817A1 (en) * 2004-08-10 2006-02-16 Oza Alpesh B Method and system for supporting memory unaligned writes in a memory controller
DE102004043036A1 (de) * 2004-09-06 2006-03-09 Rolls-Royce Deutschland Ltd & Co Kg Strömungsarbeitsmaschine mit Fluidentnahme
US7392456B2 (en) * 2004-11-23 2008-06-24 Mosys, Inc. Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory
US7275139B1 (en) * 2004-12-02 2007-09-25 Tormasov Alexander G Secure deletion of information from hard disk drive
JP2006190425A (ja) 2005-01-07 2006-07-20 Nec Electronics Corp 半導体記憶装置
JP2007184046A (ja) * 2006-01-10 2007-07-19 Hitachi Global Storage Technologies Netherlands Bv 回転円板形記憶装置および記録方法
US20080168331A1 (en) * 2007-01-05 2008-07-10 Thomas Vogelsang Memory including error correction code circuit
US7836262B2 (en) * 2007-06-05 2010-11-16 Apple Inc. Converting victim writeback to a fill
US8239638B2 (en) * 2007-06-05 2012-08-07 Apple Inc. Store handling in a processor
US8452920B1 (en) 2007-12-31 2013-05-28 Synopsys Inc. System and method for controlling a dynamic random access memory
US8397005B2 (en) 2010-03-16 2013-03-12 St-Ericsson Sa Masked register write method and apparatus
US9304709B2 (en) 2013-09-06 2016-04-05 Western Digital Technologies, Inc. High performance system providing selective merging of dataframe segments in hardware
JP2017010396A (ja) * 2015-06-24 2017-01-12 富士通株式会社 ストレージ装置、キャッシュ書込制御方法及びキャッシュ書込制御プログラム
US11887687B2 (en) 2022-02-23 2024-01-30 Micron Technology, Inc. Read operations for a memory array and register

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4371949A (en) * 1977-05-31 1983-02-01 Burroughs Corporation Time-shared, multi-phase memory accessing system having automatically updatable error logging means
US4464752A (en) * 1981-11-06 1984-08-07 The Singer Company Multiple event hardened core memory
US4651321A (en) * 1983-08-29 1987-03-17 Amdahl Corporation Apparatus for reducing storage necessary for error correction and detection in data processing machines
JPH0756640B2 (ja) * 1985-03-01 1995-06-14 株式会社日立製作所 記憶装置
US4710934A (en) * 1985-11-08 1987-12-01 Texas Instruments Incorporated Random access memory with error correction capability
US4761785B1 (en) * 1986-06-12 1996-03-12 Ibm Parity spreading to enhance storage access
US4768197A (en) * 1986-09-15 1988-08-30 Amdahl Corporation Cache error code update
US4884271A (en) * 1987-12-28 1989-11-28 International Business Machines Corporation Error checking and correcting for read-modified-write operations

Also Published As

Publication number Publication date
DE68927434D1 (de) 1996-12-12
EP0379768A3 (de) 1991-09-11
CA1319998C (en) 1993-07-06
JP2958368B2 (ja) 1999-10-06
JPH02206857A (ja) 1990-08-16
US5008886A (en) 1991-04-16
DE68927434T2 (de) 1997-06-12
EP0379768B1 (de) 1996-11-06
EP0379768A2 (de) 1990-08-01

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Legal Events

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