ATE160891T1 - Verfahren für einen blockdiagramm-simulator - Google Patents

Verfahren für einen blockdiagramm-simulator

Info

Publication number
ATE160891T1
ATE160891T1 AT88305664T AT88305664T ATE160891T1 AT E160891 T1 ATE160891 T1 AT E160891T1 AT 88305664 T AT88305664 T AT 88305664T AT 88305664 T AT88305664 T AT 88305664T AT E160891 T1 ATE160891 T1 AT E160891T1
Authority
AT
Austria
Prior art keywords
block
state
blocks
block diagram
input
Prior art date
Application number
AT88305664T
Other languages
English (en)
Inventor
William Curtis Newman
Paul Frederick Titchener
Douglas Baldwin Powell
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Application granted granted Critical
Publication of ATE160891T1 publication Critical patent/ATE160891T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/30—Creation or generation of source code
    • G06F8/34—Graphical or visual programming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/12—Symbolic schematics

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Computer Hardware Design (AREA)
  • Debugging And Monitoring (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Regulating Braking Force (AREA)
  • Feedback Control In General (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
AT88305664T 1987-06-22 1988-06-20 Verfahren für einen blockdiagramm-simulator ATE160891T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US6537287A 1987-06-22 1987-06-22
US17377188A 1988-03-23 1988-03-23

Publications (1)

Publication Number Publication Date
ATE160891T1 true ATE160891T1 (de) 1997-12-15

Family

ID=26745535

Family Applications (1)

Application Number Title Priority Date Filing Date
AT88305664T ATE160891T1 (de) 1987-06-22 1988-06-20 Verfahren für einen blockdiagramm-simulator

Country Status (7)

Country Link
US (1) US5313615A (de)
EP (1) EP0296812B1 (de)
JP (1) JP2635369B2 (de)
AT (1) ATE160891T1 (de)
AU (1) AU623337B2 (de)
CA (1) CA1300265C (de)
DE (1) DE3856079T2 (de)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
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GB8902464D0 (en) * 1989-02-03 1989-03-22 Texas Instruments Ltd Improvements in or relating to the simulation of circuits having analogue parts and digital parts
US5105373A (en) * 1990-01-22 1992-04-14 Texas Instruments Incorporated Method of simulating the operation of a circuit having analog and digital circuit parts
EP0513433A3 (en) * 1991-05-14 1993-04-21 Comdisco Systems, Inc. An apparatus and method for generating efficiently executable code representative of a block diagram
FR2728368A1 (fr) * 1994-12-20 1996-06-21 Andra Systeme d'etude par simulation d'une configuration physique en vue de fournir une aide a la decision, et utilisation de ce systeme dans des environnements naturels et artificiels
US5706473A (en) * 1995-03-31 1998-01-06 Synopsys, Inc. Computer model of a finite state machine having inputs, outputs, delayed inputs and delayed outputs
US5920711A (en) * 1995-06-02 1999-07-06 Synopsys, Inc. System for frame-based protocol, graphical capture, synthesis, analysis, and simulation
US6053948A (en) * 1995-06-07 2000-04-25 Synopsys, Inc. Method and apparatus using a memory model
GB2301911B (en) * 1995-06-08 2000-01-12 Advanced Risc Mach Ltd Simulation of digital circuits
US5745386A (en) * 1995-09-25 1998-04-28 International Business Machines Corporation Timing diagram method for inputting logic design parameters to build a testcase for the logic diagram
US5784593A (en) * 1995-09-29 1998-07-21 Synopsys, Inc. Simulator including process levelization
US5809283A (en) * 1995-09-29 1998-09-15 Synopsys, Inc. Simulator for simulating systems including mixed triggers
GB2321118B (en) * 1997-01-14 2002-03-27 Integral Design Res Ltd Development of integrated circuits
IT1302615B1 (it) * 1998-10-06 2000-09-29 Abb Research Ltd Procedimento di simulazione di processi industriali.
US6505328B1 (en) * 1999-04-27 2003-01-07 Magma Design Automation, Inc. Method for storing multiple levels of design data in a common database
US6425109B1 (en) 1999-07-23 2002-07-23 International Business Machines Corporation High level automatic core configuration
US7200838B2 (en) * 2000-12-20 2007-04-03 National Instruments Corporation System and method for automatically generating a graphical program in response to a state diagram
US7117069B2 (en) * 2001-11-28 2006-10-03 Siemens Building Technologies, Inc. Apparatus and method for executing block programs
WO2004104825A1 (en) * 2003-05-15 2004-12-02 Applianz Technologies, Inc. Systems and methods of creating and accessing software simulated computers
US7412366B1 (en) * 2003-07-18 2008-08-12 The Mathworks, Inc. Rate grouping during code generation for multi-rate models
US8875039B2 (en) * 2003-11-18 2014-10-28 The Mathworks, Inc. Propagation of characteristics in a graphical model environment
US7571395B1 (en) * 2005-08-03 2009-08-04 Xilinx, Inc. Generation of a circuit design from a command language specification of blocks in matrix form
US9329840B1 (en) 2005-12-30 2016-05-03 The Mathworks, Inc. Graphical programming of custom device drivers
US10884712B1 (en) 2005-12-30 2021-01-05 The Mathworks, Inc. Component-based framework for generating device driver model elements
US8413112B2 (en) * 2007-05-10 2013-04-02 International Business Machines Corporation Visualization of information using landmasses
US7941299B1 (en) * 2008-01-08 2011-05-10 The Mathworks, Inc. Verification and validation system for a graphical model
JP2009181446A (ja) * 2008-01-31 2009-08-13 Toshiba Corp プログラム生成装置およびブロック線図生成装置
US20110191739A1 (en) * 2008-09-30 2011-08-04 Advantest Corporation Circuit design method, circuit design system, and recording medium
US8161434B2 (en) * 2009-03-06 2012-04-17 Synopsys, Inc. Statistical formal activity analysis with consideration of temporal and spatial correlations
KR101400657B1 (ko) * 2010-08-16 2014-05-28 미쓰비시덴키 가부시키가이샤 제어 프로그램 생성 장치, 제어 프로그램 생성 프로그램을 기록한 컴퓨터 판독 가능 기록매체, 및 제어 프로그램 생성 방법
US9779195B2 (en) 2012-12-04 2017-10-03 The Mathworks, Inc. Model-based retiming with functional equivalence constraints
US8990739B2 (en) * 2012-12-04 2015-03-24 The Mathworks, Inc. Model-based retiming with functional equivalence constraints
US9201999B1 (en) * 2014-06-30 2015-12-01 Cadence Design Systems, Inc. Integrated circuit floorplan having feedthrough buffers
WO2016141319A1 (en) * 2015-03-05 2016-09-09 The Mathworks, Inc. Conditional-based duration logic
CN111228793B (zh) * 2020-01-21 2021-11-19 腾讯科技（深圳）有限公司 交互界面的显示方法和装置、存储介质及电子装置
DE102022117160A1 (de) * 2022-07-11 2024-01-11 Dspace Gmbh Computerimplementiertes Verfahren zum Konfigurieren eines virtuellen Testsystems und Trainingsverfahren

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4315315A (en) * 1971-03-09 1982-02-09 The Johns Hopkins University Graphical automatic programming
US3971000A (en) * 1974-06-20 1976-07-20 The Foxboro Company Computer-directed process control system with interactive display functions
JPS56101211A (en) * 1980-01-16 1981-08-13 Toyoda Mach Works Ltd Sequence display device
JPS56168263A (en) * 1980-05-30 1981-12-24 Hitachi Ltd Program making device
US4546435A (en) * 1980-06-24 1985-10-08 Herbert Frank P Graphic computer system and keyboard
US4570217A (en) * 1982-03-29 1986-02-11 Allen Bruce S Man machine interface
EP0099114B1 (de) * 1982-07-13 1988-05-11 Nec Corporation Logischer Simulator durchführbar auf Ebenenbasis und auf logischer Blockbasis auf jeder Ebene
US4615011A (en) * 1983-12-19 1986-09-30 Ibm Iterative method for establishing connections and resulting product
US4677587A (en) * 1985-05-14 1987-06-30 Sanders Associates, Inc. Program simulation system including means for ensuring interactive enforcement of constraints

Also Published As

Publication number Publication date
DE3856079D1 (de) 1998-01-15
EP0296812A3 (de) 1990-10-10
AU623337B2 (en) 1992-05-14
DE3856079T2 (de) 1998-07-02
JPH01280871A (ja) 1989-11-13
EP0296812B1 (de) 1997-12-03
JP2635369B2 (ja) 1997-07-30
CA1300265C (en) 1992-05-05
US5313615A (en) 1994-05-17
EP0296812A2 (de) 1988-12-28
AU1827088A (en) 1988-12-22

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