ATE173111T1 - Verfahren und vorrichtung zur prüfung eines speichers mit einer parallelen block-schreib- operation - Google Patents

Verfahren und vorrichtung zur prüfung eines speichers mit einer parallelen block-schreib- operation

Info

Publication number
ATE173111T1
ATE173111T1 AT95916796T AT95916796T ATE173111T1 AT E173111 T1 ATE173111 T1 AT E173111T1 AT 95916796 T AT95916796 T AT 95916796T AT 95916796 T AT95916796 T AT 95916796T AT E173111 T1 ATE173111 T1 AT E173111T1
Authority
AT
Austria
Prior art keywords
data bit
test data
arrays
test
block write
Prior art date
Application number
AT95916796T
Other languages
English (en)
Inventor
Timothy Dominic Dorney
Anthony Michael Balistreri
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of ATE173111T1 publication Critical patent/ATE173111T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C29/28—Dependent multiple arrays, e.g. multi-bit arrays

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT95916796T 1994-04-29 1995-04-28 Verfahren und vorrichtung zur prüfung eines speichers mit einer parallelen block-schreib- operation ATE173111T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US23559194A 1994-04-29 1994-04-29

Publications (1)

Publication Number Publication Date
ATE173111T1 true ATE173111T1 (de) 1998-11-15

Family

ID=22886151

Family Applications (1)

Application Number Title Priority Date Filing Date
AT95916796T ATE173111T1 (de) 1994-04-29 1995-04-28 Verfahren und vorrichtung zur prüfung eines speichers mit einer parallelen block-schreib- operation

Country Status (6)

Country Link
US (1) US5740179A (de)
EP (1) EP0757837B1 (de)
KR (1) KR100336951B1 (de)
AT (1) ATE173111T1 (de)
DE (1) DE69505806T2 (de)
WO (1) WO1995030227A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6560669B1 (en) * 1998-05-19 2003-05-06 Micron Technology, Inc. Double data rate synchronous memory with block-write
US6658610B1 (en) 2000-09-25 2003-12-02 International Business Machines Corporation Compilable address magnitude comparator for memory array self-testing
US6640296B2 (en) * 2002-03-07 2003-10-28 Nokia Corporation Data processing method and device for parallel stride access
KR100564033B1 (ko) * 2003-12-05 2006-03-23 삼성전자주식회사 단일 버퍼 선택 입력 단자를 가지는 반도체 메모리 및반도체 메모리 테스트 방법
US7246280B2 (en) * 2004-03-23 2007-07-17 Samsung Electronics Co., Ltd. Memory module with parallel testing
KR100673694B1 (ko) * 2005-10-10 2007-01-24 주식회사 하이닉스반도체 저전력 소비형 칼럼 디코더를 가지는 반도체 메모리 장치및 그 리드 동작 방법
US8832508B2 (en) * 2010-11-18 2014-09-09 Advanced Micro Devices, Inc. Apparatus and methods for testing writability and readability of memory cell arrays

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62170094A (ja) * 1986-01-21 1987-07-27 Mitsubishi Electric Corp 半導体記憶回路
JPS6337894A (ja) * 1986-07-30 1988-02-18 Mitsubishi Electric Corp ランダムアクセスメモリ
US4817058A (en) * 1987-05-21 1989-03-28 Texas Instruments Incorporated Multiple input/output read/write memory having a multiple-cycle write mask
KR910001744A (ko) * 1988-06-14 1991-01-31 미다 가쓰시게 반도체 기억장치
JPH02146199A (ja) * 1988-11-28 1990-06-05 Mitsubishi Electric Corp 半導体記憶装置のテスト回路
KR920001082B1 (ko) * 1989-06-13 1992-02-01 삼성전자 주식회사 반도체 메모리장치에 있어서 메모리 테스트용 멀티바이트 광역 병렬 라이트회로
JP2717712B2 (ja) * 1989-08-18 1998-02-25 三菱電機株式会社 半導体記憶装置
JP2831767B2 (ja) * 1990-01-10 1998-12-02 株式会社アドバンテスト 半導体メモリ試験装置
US5138619A (en) * 1990-02-15 1992-08-11 National Semiconductor Corporation Built-in self test for integrated circuit memory
US5228000A (en) * 1990-08-02 1993-07-13 Mitsubishi Denki Kabushiki Kaisha Test circuit of semiconductor memory device
JPH0676598A (ja) * 1992-08-28 1994-03-18 Mitsubishi Electric Corp 半導体記憶装置
JP3293935B2 (ja) * 1993-03-12 2002-06-17 株式会社東芝 並列ビットテストモード内蔵半導体メモリ

Also Published As

Publication number Publication date
DE69505806T2 (de) 1999-05-12
EP0757837B1 (de) 1998-11-04
EP0757837A1 (de) 1997-02-12
US5740179A (en) 1998-04-14
KR100336951B1 (ko) 2002-10-09
KR970703035A (ko) 1997-06-10
WO1995030227A1 (en) 1995-11-09
DE69505806D1 (de) 1998-12-10

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